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f7b2429f BS |
1 | /* |
2 | * x86 misc helpers | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
b6a0aa05 | 20 | #include "qemu/osdep.h" |
f7b2429f | 21 | #include "cpu.h" |
2ef6175a | 22 | #include "exec/helper-proto.h" |
63c91552 | 23 | #include "exec/exec-all.h" |
f08b6170 | 24 | #include "exec/cpu_ldst.h" |
3f7d8464 | 25 | #include "exec/address-spaces.h" |
92fc4b58 | 26 | |
3f7d8464 | 27 | void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) |
f7b2429f | 28 | { |
3f7d8464 PB |
29 | #ifdef CONFIG_USER_ONLY |
30 | fprintf(stderr, "outb: port=0x%04x, data=%02x\n", port, data); | |
31 | #else | |
32 | address_space_stb(&address_space_io, port, data, | |
33 | cpu_get_mem_attrs(env), NULL); | |
34 | #endif | |
f7b2429f BS |
35 | } |
36 | ||
3f7d8464 | 37 | target_ulong helper_inb(CPUX86State *env, uint32_t port) |
f7b2429f | 38 | { |
3f7d8464 PB |
39 | #ifdef CONFIG_USER_ONLY |
40 | fprintf(stderr, "inb: port=0x%04x\n", port); | |
41 | return 0; | |
42 | #else | |
43 | return address_space_ldub(&address_space_io, port, | |
44 | cpu_get_mem_attrs(env), NULL); | |
45 | #endif | |
f7b2429f BS |
46 | } |
47 | ||
3f7d8464 | 48 | void helper_outw(CPUX86State *env, uint32_t port, uint32_t data) |
f7b2429f | 49 | { |
3f7d8464 PB |
50 | #ifdef CONFIG_USER_ONLY |
51 | fprintf(stderr, "outw: port=0x%04x, data=%04x\n", port, data); | |
52 | #else | |
53 | address_space_stw(&address_space_io, port, data, | |
54 | cpu_get_mem_attrs(env), NULL); | |
55 | #endif | |
f7b2429f BS |
56 | } |
57 | ||
3f7d8464 | 58 | target_ulong helper_inw(CPUX86State *env, uint32_t port) |
f7b2429f | 59 | { |
3f7d8464 PB |
60 | #ifdef CONFIG_USER_ONLY |
61 | fprintf(stderr, "inw: port=0x%04x\n", port); | |
62 | return 0; | |
63 | #else | |
64 | return address_space_lduw(&address_space_io, port, | |
65 | cpu_get_mem_attrs(env), NULL); | |
66 | #endif | |
f7b2429f BS |
67 | } |
68 | ||
3f7d8464 | 69 | void helper_outl(CPUX86State *env, uint32_t port, uint32_t data) |
f7b2429f | 70 | { |
3f7d8464 PB |
71 | #ifdef CONFIG_USER_ONLY |
72 | fprintf(stderr, "outw: port=0x%04x, data=%08x\n", port, data); | |
73 | #else | |
74 | address_space_stl(&address_space_io, port, data, | |
75 | cpu_get_mem_attrs(env), NULL); | |
76 | #endif | |
f7b2429f BS |
77 | } |
78 | ||
3f7d8464 | 79 | target_ulong helper_inl(CPUX86State *env, uint32_t port) |
f7b2429f | 80 | { |
3f7d8464 PB |
81 | #ifdef CONFIG_USER_ONLY |
82 | fprintf(stderr, "inl: port=0x%04x\n", port); | |
83 | return 0; | |
84 | #else | |
85 | return address_space_ldl(&address_space_io, port, | |
86 | cpu_get_mem_attrs(env), NULL); | |
87 | #endif | |
f7b2429f BS |
88 | } |
89 | ||
4a7443be | 90 | void helper_into(CPUX86State *env, int next_eip_addend) |
f7b2429f BS |
91 | { |
92 | int eflags; | |
93 | ||
f0967a1a | 94 | eflags = cpu_cc_compute_all(env, CC_OP); |
f7b2429f BS |
95 | if (eflags & CC_O) { |
96 | raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend); | |
97 | } | |
98 | } | |
99 | ||
4a7443be | 100 | void helper_cpuid(CPUX86State *env) |
f7b2429f BS |
101 | { |
102 | uint32_t eax, ebx, ecx, edx; | |
103 | ||
104 | cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0); | |
105 | ||
90a2541b LG |
106 | cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], |
107 | &eax, &ebx, &ecx, &edx); | |
4b34e3ad | 108 | env->regs[R_EAX] = eax; |
70b51365 | 109 | env->regs[R_EBX] = ebx; |
a4165610 | 110 | env->regs[R_ECX] = ecx; |
00f5e6f2 | 111 | env->regs[R_EDX] = edx; |
f7b2429f BS |
112 | } |
113 | ||
114 | #if defined(CONFIG_USER_ONLY) | |
4a7443be | 115 | target_ulong helper_read_crN(CPUX86State *env, int reg) |
f7b2429f BS |
116 | { |
117 | return 0; | |
118 | } | |
119 | ||
4a7443be | 120 | void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) |
f7b2429f BS |
121 | { |
122 | } | |
f7b2429f | 123 | #else |
4a7443be | 124 | target_ulong helper_read_crN(CPUX86State *env, int reg) |
f7b2429f BS |
125 | { |
126 | target_ulong val; | |
127 | ||
128 | cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0); | |
129 | switch (reg) { | |
130 | default: | |
131 | val = env->cr[reg]; | |
132 | break; | |
133 | case 8: | |
134 | if (!(env->hflags2 & HF2_VINTR_MASK)) { | |
02e51483 | 135 | val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state); |
f7b2429f BS |
136 | } else { |
137 | val = env->v_tpr; | |
138 | } | |
139 | break; | |
140 | } | |
141 | return val; | |
142 | } | |
143 | ||
4a7443be | 144 | void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) |
f7b2429f BS |
145 | { |
146 | cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0); | |
147 | switch (reg) { | |
148 | case 0: | |
149 | cpu_x86_update_cr0(env, t0); | |
150 | break; | |
151 | case 3: | |
152 | cpu_x86_update_cr3(env, t0); | |
153 | break; | |
154 | case 4: | |
155 | cpu_x86_update_cr4(env, t0); | |
156 | break; | |
157 | case 8: | |
158 | if (!(env->hflags2 & HF2_VINTR_MASK)) { | |
02e51483 | 159 | cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0); |
f7b2429f BS |
160 | } |
161 | env->v_tpr = t0 & 0x0f; | |
162 | break; | |
163 | default: | |
164 | env->cr[reg] = t0; | |
165 | break; | |
166 | } | |
167 | } | |
f7b2429f BS |
168 | #endif |
169 | ||
4a7443be | 170 | void helper_lmsw(CPUX86State *env, target_ulong t0) |
f7b2429f BS |
171 | { |
172 | /* only 4 lower bits of CR0 are modified. PE cannot be set to zero | |
173 | if already set to one. */ | |
174 | t0 = (env->cr[0] & ~0xe) | (t0 & 0xf); | |
4a7443be | 175 | helper_write_crN(env, 0, t0); |
f7b2429f BS |
176 | } |
177 | ||
4a7443be | 178 | void helper_invlpg(CPUX86State *env, target_ulong addr) |
f7b2429f | 179 | { |
31b030d4 AF |
180 | X86CPU *cpu = x86_env_get_cpu(env); |
181 | ||
f7b2429f | 182 | cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0); |
31b030d4 | 183 | tlb_flush_page(CPU(cpu), addr); |
f7b2429f BS |
184 | } |
185 | ||
4a7443be | 186 | void helper_rdtsc(CPUX86State *env) |
f7b2429f BS |
187 | { |
188 | uint64_t val; | |
189 | ||
190 | if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) { | |
4054cdec | 191 | raise_exception_ra(env, EXCP0D_GPF, GETPC()); |
f7b2429f BS |
192 | } |
193 | cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0); | |
194 | ||
195 | val = cpu_get_tsc(env) + env->tsc_offset; | |
4b34e3ad | 196 | env->regs[R_EAX] = (uint32_t)(val); |
00f5e6f2 | 197 | env->regs[R_EDX] = (uint32_t)(val >> 32); |
f7b2429f BS |
198 | } |
199 | ||
4a7443be | 200 | void helper_rdtscp(CPUX86State *env) |
f7b2429f | 201 | { |
4a7443be | 202 | helper_rdtsc(env); |
a4165610 | 203 | env->regs[R_ECX] = (uint32_t)(env->tsc_aux); |
f7b2429f BS |
204 | } |
205 | ||
4a7443be | 206 | void helper_rdpmc(CPUX86State *env) |
f7b2429f BS |
207 | { |
208 | if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) { | |
4054cdec | 209 | raise_exception_ra(env, EXCP0D_GPF, GETPC()); |
f7b2429f BS |
210 | } |
211 | cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0); | |
212 | ||
213 | /* currently unimplemented */ | |
214 | qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n"); | |
215 | raise_exception_err(env, EXCP06_ILLOP, 0); | |
216 | } | |
217 | ||
218 | #if defined(CONFIG_USER_ONLY) | |
4a7443be | 219 | void helper_wrmsr(CPUX86State *env) |
f7b2429f BS |
220 | { |
221 | } | |
222 | ||
4a7443be | 223 | void helper_rdmsr(CPUX86State *env) |
f7b2429f BS |
224 | { |
225 | } | |
226 | #else | |
4a7443be | 227 | void helper_wrmsr(CPUX86State *env) |
f7b2429f BS |
228 | { |
229 | uint64_t val; | |
230 | ||
231 | cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1); | |
232 | ||
90a2541b LG |
233 | val = ((uint32_t)env->regs[R_EAX]) | |
234 | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32); | |
f7b2429f | 235 | |
a4165610 | 236 | switch ((uint32_t)env->regs[R_ECX]) { |
f7b2429f BS |
237 | case MSR_IA32_SYSENTER_CS: |
238 | env->sysenter_cs = val & 0xffff; | |
239 | break; | |
240 | case MSR_IA32_SYSENTER_ESP: | |
241 | env->sysenter_esp = val; | |
242 | break; | |
243 | case MSR_IA32_SYSENTER_EIP: | |
244 | env->sysenter_eip = val; | |
245 | break; | |
246 | case MSR_IA32_APICBASE: | |
02e51483 | 247 | cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val); |
f7b2429f BS |
248 | break; |
249 | case MSR_EFER: | |
250 | { | |
251 | uint64_t update_mask; | |
252 | ||
253 | update_mask = 0; | |
0514ef2f | 254 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) { |
f7b2429f BS |
255 | update_mask |= MSR_EFER_SCE; |
256 | } | |
0514ef2f | 257 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { |
f7b2429f BS |
258 | update_mask |= MSR_EFER_LME; |
259 | } | |
0514ef2f | 260 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) { |
f7b2429f BS |
261 | update_mask |= MSR_EFER_FFXSR; |
262 | } | |
0514ef2f | 263 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) { |
f7b2429f BS |
264 | update_mask |= MSR_EFER_NXE; |
265 | } | |
0514ef2f | 266 | if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { |
f7b2429f BS |
267 | update_mask |= MSR_EFER_SVME; |
268 | } | |
0514ef2f | 269 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) { |
f7b2429f BS |
270 | update_mask |= MSR_EFER_FFXSR; |
271 | } | |
272 | cpu_load_efer(env, (env->efer & ~update_mask) | | |
273 | (val & update_mask)); | |
274 | } | |
275 | break; | |
276 | case MSR_STAR: | |
277 | env->star = val; | |
278 | break; | |
279 | case MSR_PAT: | |
280 | env->pat = val; | |
281 | break; | |
282 | case MSR_VM_HSAVE_PA: | |
283 | env->vm_hsave = val; | |
284 | break; | |
285 | #ifdef TARGET_X86_64 | |
286 | case MSR_LSTAR: | |
287 | env->lstar = val; | |
288 | break; | |
289 | case MSR_CSTAR: | |
290 | env->cstar = val; | |
291 | break; | |
292 | case MSR_FMASK: | |
293 | env->fmask = val; | |
294 | break; | |
295 | case MSR_FSBASE: | |
296 | env->segs[R_FS].base = val; | |
297 | break; | |
298 | case MSR_GSBASE: | |
299 | env->segs[R_GS].base = val; | |
300 | break; | |
301 | case MSR_KERNELGSBASE: | |
302 | env->kernelgsbase = val; | |
303 | break; | |
304 | #endif | |
305 | case MSR_MTRRphysBase(0): | |
306 | case MSR_MTRRphysBase(1): | |
307 | case MSR_MTRRphysBase(2): | |
308 | case MSR_MTRRphysBase(3): | |
309 | case MSR_MTRRphysBase(4): | |
310 | case MSR_MTRRphysBase(5): | |
311 | case MSR_MTRRphysBase(6): | |
312 | case MSR_MTRRphysBase(7): | |
90a2541b LG |
313 | env->mtrr_var[((uint32_t)env->regs[R_ECX] - |
314 | MSR_MTRRphysBase(0)) / 2].base = val; | |
f7b2429f BS |
315 | break; |
316 | case MSR_MTRRphysMask(0): | |
317 | case MSR_MTRRphysMask(1): | |
318 | case MSR_MTRRphysMask(2): | |
319 | case MSR_MTRRphysMask(3): | |
320 | case MSR_MTRRphysMask(4): | |
321 | case MSR_MTRRphysMask(5): | |
322 | case MSR_MTRRphysMask(6): | |
323 | case MSR_MTRRphysMask(7): | |
90a2541b LG |
324 | env->mtrr_var[((uint32_t)env->regs[R_ECX] - |
325 | MSR_MTRRphysMask(0)) / 2].mask = val; | |
f7b2429f BS |
326 | break; |
327 | case MSR_MTRRfix64K_00000: | |
90a2541b LG |
328 | env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - |
329 | MSR_MTRRfix64K_00000] = val; | |
f7b2429f BS |
330 | break; |
331 | case MSR_MTRRfix16K_80000: | |
332 | case MSR_MTRRfix16K_A0000: | |
90a2541b LG |
333 | env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - |
334 | MSR_MTRRfix16K_80000 + 1] = val; | |
f7b2429f BS |
335 | break; |
336 | case MSR_MTRRfix4K_C0000: | |
337 | case MSR_MTRRfix4K_C8000: | |
338 | case MSR_MTRRfix4K_D0000: | |
339 | case MSR_MTRRfix4K_D8000: | |
340 | case MSR_MTRRfix4K_E0000: | |
341 | case MSR_MTRRfix4K_E8000: | |
342 | case MSR_MTRRfix4K_F0000: | |
343 | case MSR_MTRRfix4K_F8000: | |
90a2541b LG |
344 | env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - |
345 | MSR_MTRRfix4K_C0000 + 3] = val; | |
f7b2429f BS |
346 | break; |
347 | case MSR_MTRRdefType: | |
348 | env->mtrr_deftype = val; | |
349 | break; | |
350 | case MSR_MCG_STATUS: | |
351 | env->mcg_status = val; | |
352 | break; | |
353 | case MSR_MCG_CTL: | |
354 | if ((env->mcg_cap & MCG_CTL_P) | |
355 | && (val == 0 || val == ~(uint64_t)0)) { | |
356 | env->mcg_ctl = val; | |
357 | } | |
358 | break; | |
359 | case MSR_TSC_AUX: | |
360 | env->tsc_aux = val; | |
361 | break; | |
362 | case MSR_IA32_MISC_ENABLE: | |
363 | env->msr_ia32_misc_enable = val; | |
364 | break; | |
f4f1110e RH |
365 | case MSR_IA32_BNDCFGS: |
366 | /* FIXME: #GP if reserved bits are set. */ | |
367 | /* FIXME: Extend highest implemented bit of linear address. */ | |
368 | env->msr_bndcfgs = val; | |
369 | cpu_sync_bndcs_hflags(env); | |
370 | break; | |
f7b2429f | 371 | default: |
a4165610 | 372 | if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL |
90a2541b LG |
373 | && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + |
374 | (4 * env->mcg_cap & 0xff)) { | |
a4165610 | 375 | uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; |
f7b2429f BS |
376 | if ((offset & 0x3) != 0 |
377 | || (val == 0 || val == ~(uint64_t)0)) { | |
378 | env->mce_banks[offset] = val; | |
379 | } | |
380 | break; | |
381 | } | |
382 | /* XXX: exception? */ | |
383 | break; | |
384 | } | |
385 | } | |
386 | ||
4a7443be | 387 | void helper_rdmsr(CPUX86State *env) |
f7b2429f BS |
388 | { |
389 | uint64_t val; | |
390 | ||
391 | cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0); | |
392 | ||
a4165610 | 393 | switch ((uint32_t)env->regs[R_ECX]) { |
f7b2429f BS |
394 | case MSR_IA32_SYSENTER_CS: |
395 | val = env->sysenter_cs; | |
396 | break; | |
397 | case MSR_IA32_SYSENTER_ESP: | |
398 | val = env->sysenter_esp; | |
399 | break; | |
400 | case MSR_IA32_SYSENTER_EIP: | |
401 | val = env->sysenter_eip; | |
402 | break; | |
403 | case MSR_IA32_APICBASE: | |
02e51483 | 404 | val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state); |
f7b2429f BS |
405 | break; |
406 | case MSR_EFER: | |
407 | val = env->efer; | |
408 | break; | |
409 | case MSR_STAR: | |
410 | val = env->star; | |
411 | break; | |
412 | case MSR_PAT: | |
413 | val = env->pat; | |
414 | break; | |
415 | case MSR_VM_HSAVE_PA: | |
416 | val = env->vm_hsave; | |
417 | break; | |
418 | case MSR_IA32_PERF_STATUS: | |
419 | /* tsc_increment_by_tick */ | |
420 | val = 1000ULL; | |
421 | /* CPU multiplier */ | |
422 | val |= (((uint64_t)4ULL) << 40); | |
423 | break; | |
424 | #ifdef TARGET_X86_64 | |
425 | case MSR_LSTAR: | |
426 | val = env->lstar; | |
427 | break; | |
428 | case MSR_CSTAR: | |
429 | val = env->cstar; | |
430 | break; | |
431 | case MSR_FMASK: | |
432 | val = env->fmask; | |
433 | break; | |
434 | case MSR_FSBASE: | |
435 | val = env->segs[R_FS].base; | |
436 | break; | |
437 | case MSR_GSBASE: | |
438 | val = env->segs[R_GS].base; | |
439 | break; | |
440 | case MSR_KERNELGSBASE: | |
441 | val = env->kernelgsbase; | |
442 | break; | |
443 | case MSR_TSC_AUX: | |
444 | val = env->tsc_aux; | |
445 | break; | |
446 | #endif | |
447 | case MSR_MTRRphysBase(0): | |
448 | case MSR_MTRRphysBase(1): | |
449 | case MSR_MTRRphysBase(2): | |
450 | case MSR_MTRRphysBase(3): | |
451 | case MSR_MTRRphysBase(4): | |
452 | case MSR_MTRRphysBase(5): | |
453 | case MSR_MTRRphysBase(6): | |
454 | case MSR_MTRRphysBase(7): | |
90a2541b LG |
455 | val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - |
456 | MSR_MTRRphysBase(0)) / 2].base; | |
f7b2429f BS |
457 | break; |
458 | case MSR_MTRRphysMask(0): | |
459 | case MSR_MTRRphysMask(1): | |
460 | case MSR_MTRRphysMask(2): | |
461 | case MSR_MTRRphysMask(3): | |
462 | case MSR_MTRRphysMask(4): | |
463 | case MSR_MTRRphysMask(5): | |
464 | case MSR_MTRRphysMask(6): | |
465 | case MSR_MTRRphysMask(7): | |
90a2541b LG |
466 | val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - |
467 | MSR_MTRRphysMask(0)) / 2].mask; | |
f7b2429f BS |
468 | break; |
469 | case MSR_MTRRfix64K_00000: | |
470 | val = env->mtrr_fixed[0]; | |
471 | break; | |
472 | case MSR_MTRRfix16K_80000: | |
473 | case MSR_MTRRfix16K_A0000: | |
90a2541b LG |
474 | val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - |
475 | MSR_MTRRfix16K_80000 + 1]; | |
f7b2429f BS |
476 | break; |
477 | case MSR_MTRRfix4K_C0000: | |
478 | case MSR_MTRRfix4K_C8000: | |
479 | case MSR_MTRRfix4K_D0000: | |
480 | case MSR_MTRRfix4K_D8000: | |
481 | case MSR_MTRRfix4K_E0000: | |
482 | case MSR_MTRRfix4K_E8000: | |
483 | case MSR_MTRRfix4K_F0000: | |
484 | case MSR_MTRRfix4K_F8000: | |
90a2541b LG |
485 | val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - |
486 | MSR_MTRRfix4K_C0000 + 3]; | |
f7b2429f BS |
487 | break; |
488 | case MSR_MTRRdefType: | |
489 | val = env->mtrr_deftype; | |
490 | break; | |
491 | case MSR_MTRRcap: | |
0514ef2f | 492 | if (env->features[FEAT_1_EDX] & CPUID_MTRR) { |
f7b2429f BS |
493 | val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT | |
494 | MSR_MTRRcap_WC_SUPPORTED; | |
495 | } else { | |
496 | /* XXX: exception? */ | |
497 | val = 0; | |
498 | } | |
499 | break; | |
500 | case MSR_MCG_CAP: | |
501 | val = env->mcg_cap; | |
502 | break; | |
503 | case MSR_MCG_CTL: | |
504 | if (env->mcg_cap & MCG_CTL_P) { | |
505 | val = env->mcg_ctl; | |
506 | } else { | |
507 | val = 0; | |
508 | } | |
509 | break; | |
510 | case MSR_MCG_STATUS: | |
511 | val = env->mcg_status; | |
512 | break; | |
513 | case MSR_IA32_MISC_ENABLE: | |
514 | val = env->msr_ia32_misc_enable; | |
515 | break; | |
f4f1110e RH |
516 | case MSR_IA32_BNDCFGS: |
517 | val = env->msr_bndcfgs; | |
518 | break; | |
f7b2429f | 519 | default: |
a4165610 | 520 | if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL |
90a2541b LG |
521 | && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + |
522 | (4 * env->mcg_cap & 0xff)) { | |
a4165610 | 523 | uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; |
f7b2429f BS |
524 | val = env->mce_banks[offset]; |
525 | break; | |
526 | } | |
527 | /* XXX: exception? */ | |
528 | val = 0; | |
529 | break; | |
530 | } | |
4b34e3ad | 531 | env->regs[R_EAX] = (uint32_t)(val); |
00f5e6f2 | 532 | env->regs[R_EDX] = (uint32_t)(val >> 32); |
f7b2429f BS |
533 | } |
534 | #endif | |
535 | ||
81f3053b PB |
536 | static void do_pause(X86CPU *cpu) |
537 | { | |
27103424 | 538 | CPUState *cs = CPU(cpu); |
81f3053b PB |
539 | |
540 | /* Just let another CPU run. */ | |
27103424 | 541 | cs->exception_index = EXCP_INTERRUPT; |
5638d180 | 542 | cpu_loop_exit(cs); |
81f3053b PB |
543 | } |
544 | ||
259186a7 | 545 | static void do_hlt(X86CPU *cpu) |
f7b2429f | 546 | { |
259186a7 AF |
547 | CPUState *cs = CPU(cpu); |
548 | CPUX86State *env = &cpu->env; | |
549 | ||
f7b2429f | 550 | env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ |
259186a7 | 551 | cs->halted = 1; |
27103424 | 552 | cs->exception_index = EXCP_HLT; |
5638d180 | 553 | cpu_loop_exit(cs); |
f7b2429f BS |
554 | } |
555 | ||
4a7443be | 556 | void helper_hlt(CPUX86State *env, int next_eip_addend) |
f7b2429f | 557 | { |
259186a7 AF |
558 | X86CPU *cpu = x86_env_get_cpu(env); |
559 | ||
f7b2429f | 560 | cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0); |
a78d0eab | 561 | env->eip += next_eip_addend; |
f7b2429f | 562 | |
259186a7 | 563 | do_hlt(cpu); |
f7b2429f BS |
564 | } |
565 | ||
4a7443be | 566 | void helper_monitor(CPUX86State *env, target_ulong ptr) |
f7b2429f | 567 | { |
a4165610 | 568 | if ((uint32_t)env->regs[R_ECX] != 0) { |
4054cdec | 569 | raise_exception_ra(env, EXCP0D_GPF, GETPC()); |
f7b2429f BS |
570 | } |
571 | /* XXX: store address? */ | |
572 | cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0); | |
573 | } | |
574 | ||
4a7443be | 575 | void helper_mwait(CPUX86State *env, int next_eip_addend) |
f7b2429f | 576 | { |
259186a7 AF |
577 | CPUState *cs; |
578 | X86CPU *cpu; | |
55e5c285 | 579 | |
a4165610 | 580 | if ((uint32_t)env->regs[R_ECX] != 0) { |
4054cdec | 581 | raise_exception_ra(env, EXCP0D_GPF, GETPC()); |
f7b2429f BS |
582 | } |
583 | cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0); | |
a78d0eab | 584 | env->eip += next_eip_addend; |
f7b2429f | 585 | |
259186a7 AF |
586 | cpu = x86_env_get_cpu(env); |
587 | cs = CPU(cpu); | |
f7b2429f | 588 | /* XXX: not complete but not completely erroneous */ |
bdc44640 | 589 | if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) { |
81f3053b | 590 | do_pause(cpu); |
f7b2429f | 591 | } else { |
259186a7 | 592 | do_hlt(cpu); |
f7b2429f BS |
593 | } |
594 | } | |
595 | ||
81f3053b PB |
596 | void helper_pause(CPUX86State *env, int next_eip_addend) |
597 | { | |
598 | X86CPU *cpu = x86_env_get_cpu(env); | |
599 | ||
600 | cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0); | |
601 | env->eip += next_eip_addend; | |
602 | ||
603 | do_pause(cpu); | |
604 | } | |
605 | ||
4a7443be | 606 | void helper_debug(CPUX86State *env) |
f7b2429f | 607 | { |
27103424 AF |
608 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
609 | ||
610 | cs->exception_index = EXCP_DEBUG; | |
5638d180 | 611 | cpu_loop_exit(cs); |
f7b2429f | 612 | } |
0f70ed47 PB |
613 | |
614 | uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx) | |
615 | { | |
616 | if ((env->cr[4] & CR4_PKE_MASK) == 0) { | |
617 | raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC()); | |
618 | } | |
619 | if (ecx != 0) { | |
620 | raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); | |
621 | } | |
622 | ||
623 | return env->pkru; | |
624 | } | |
625 | ||
626 | void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val) | |
627 | { | |
628 | CPUState *cs = CPU(x86_env_get_cpu(env)); | |
629 | ||
630 | if ((env->cr[4] & CR4_PKE_MASK) == 0) { | |
631 | raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC()); | |
632 | } | |
633 | if (ecx != 0 || (val & 0xFFFFFFFF00000000ull)) { | |
634 | raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); | |
635 | } | |
636 | ||
637 | env->pkru = val; | |
638 | tlb_flush(cs, 1); | |
639 | } |