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Commit | Line | Data |
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eaa728ee | 1 | /* |
10774999 BS |
2 | * x86 segmentation related helpers: |
3 | * TSS, interrupts, system calls, jumps and call/task gates, descriptors | |
eaa728ee FB |
4 | * |
5 | * Copyright (c) 2003 Fabrice Bellard | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
eaa728ee | 19 | */ |
83dae095 | 20 | |
3e457172 | 21 | #include "cpu.h" |
1de7afc9 | 22 | #include "qemu/log.h" |
3e457172 | 23 | #include "helper.h" |
eaa728ee | 24 | |
3e457172 | 25 | //#define DEBUG_PCALL |
d12d51d5 | 26 | |
92fc4b58 | 27 | #if !defined(CONFIG_USER_ONLY) |
022c62cb | 28 | #include "exec/softmmu_exec.h" |
92fc4b58 BS |
29 | #endif /* !defined(CONFIG_USER_ONLY) */ |
30 | ||
d12d51d5 | 31 | #ifdef DEBUG_PCALL |
20054ef0 | 32 | # define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__) |
8995b7a0 AF |
33 | # define LOG_PCALL_STATE(cpu) \ |
34 | log_cpu_state_mask(CPU_LOG_PCALL, (cpu), CPU_DUMP_CCOP) | |
d12d51d5 | 35 | #else |
20054ef0 | 36 | # define LOG_PCALL(...) do { } while (0) |
8995b7a0 | 37 | # define LOG_PCALL_STATE(cpu) do { } while (0) |
d12d51d5 AL |
38 | #endif |
39 | ||
eaa728ee | 40 | /* return non zero if error */ |
2999a0b2 BS |
41 | static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr, |
42 | uint32_t *e2_ptr, int selector) | |
eaa728ee FB |
43 | { |
44 | SegmentCache *dt; | |
45 | int index; | |
46 | target_ulong ptr; | |
47 | ||
20054ef0 | 48 | if (selector & 0x4) { |
eaa728ee | 49 | dt = &env->ldt; |
20054ef0 | 50 | } else { |
eaa728ee | 51 | dt = &env->gdt; |
20054ef0 | 52 | } |
eaa728ee | 53 | index = selector & ~7; |
20054ef0 | 54 | if ((index + 7) > dt->limit) { |
eaa728ee | 55 | return -1; |
20054ef0 | 56 | } |
eaa728ee | 57 | ptr = dt->base + index; |
329e607d BS |
58 | *e1_ptr = cpu_ldl_kernel(env, ptr); |
59 | *e2_ptr = cpu_ldl_kernel(env, ptr + 4); | |
eaa728ee FB |
60 | return 0; |
61 | } | |
62 | ||
63 | static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2) | |
64 | { | |
65 | unsigned int limit; | |
20054ef0 | 66 | |
eaa728ee | 67 | limit = (e1 & 0xffff) | (e2 & 0x000f0000); |
20054ef0 | 68 | if (e2 & DESC_G_MASK) { |
eaa728ee | 69 | limit = (limit << 12) | 0xfff; |
20054ef0 | 70 | } |
eaa728ee FB |
71 | return limit; |
72 | } | |
73 | ||
74 | static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2) | |
75 | { | |
20054ef0 | 76 | return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000); |
eaa728ee FB |
77 | } |
78 | ||
20054ef0 BS |
79 | static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, |
80 | uint32_t e2) | |
eaa728ee FB |
81 | { |
82 | sc->base = get_seg_base(e1, e2); | |
83 | sc->limit = get_seg_limit(e1, e2); | |
84 | sc->flags = e2; | |
85 | } | |
86 | ||
87 | /* init the segment cache in vm86 mode. */ | |
2999a0b2 | 88 | static inline void load_seg_vm(CPUX86State *env, int seg, int selector) |
eaa728ee FB |
89 | { |
90 | selector &= 0xffff; | |
91 | cpu_x86_load_seg_cache(env, seg, selector, | |
92 | (selector << 4), 0xffff, 0); | |
93 | } | |
94 | ||
2999a0b2 | 95 | static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, |
eaa728ee FB |
96 | uint32_t *esp_ptr, int dpl) |
97 | { | |
98 | int type, index, shift; | |
99 | ||
100 | #if 0 | |
101 | { | |
102 | int i; | |
103 | printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit); | |
20054ef0 | 104 | for (i = 0; i < env->tr.limit; i++) { |
eaa728ee | 105 | printf("%02x ", env->tr.base[i]); |
20054ef0 BS |
106 | if ((i & 7) == 7) { |
107 | printf("\n"); | |
108 | } | |
eaa728ee FB |
109 | } |
110 | printf("\n"); | |
111 | } | |
112 | #endif | |
113 | ||
20054ef0 | 114 | if (!(env->tr.flags & DESC_P_MASK)) { |
eaa728ee | 115 | cpu_abort(env, "invalid tss"); |
20054ef0 | 116 | } |
eaa728ee | 117 | type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; |
20054ef0 | 118 | if ((type & 7) != 1) { |
eaa728ee | 119 | cpu_abort(env, "invalid tss type"); |
20054ef0 | 120 | } |
eaa728ee FB |
121 | shift = type >> 3; |
122 | index = (dpl * 4 + 2) << shift; | |
20054ef0 | 123 | if (index + (4 << shift) - 1 > env->tr.limit) { |
77b2bc2c | 124 | raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc); |
20054ef0 | 125 | } |
eaa728ee | 126 | if (shift == 0) { |
329e607d BS |
127 | *esp_ptr = cpu_lduw_kernel(env, env->tr.base + index); |
128 | *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 2); | |
eaa728ee | 129 | } else { |
329e607d BS |
130 | *esp_ptr = cpu_ldl_kernel(env, env->tr.base + index); |
131 | *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 4); | |
eaa728ee FB |
132 | } |
133 | } | |
134 | ||
135 | /* XXX: merge with load_seg() */ | |
2999a0b2 | 136 | static void tss_load_seg(CPUX86State *env, int seg_reg, int selector) |
eaa728ee FB |
137 | { |
138 | uint32_t e1, e2; | |
139 | int rpl, dpl, cpl; | |
140 | ||
141 | if ((selector & 0xfffc) != 0) { | |
2999a0b2 | 142 | if (load_segment(env, &e1, &e2, selector) != 0) { |
77b2bc2c | 143 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 BS |
144 | } |
145 | if (!(e2 & DESC_S_MASK)) { | |
77b2bc2c | 146 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 | 147 | } |
eaa728ee FB |
148 | rpl = selector & 3; |
149 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
150 | cpl = env->hflags & HF_CPL_MASK; | |
151 | if (seg_reg == R_CS) { | |
20054ef0 | 152 | if (!(e2 & DESC_CS_MASK)) { |
77b2bc2c | 153 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 BS |
154 | } |
155 | /* XXX: is it correct? */ | |
156 | if (dpl != rpl) { | |
77b2bc2c | 157 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 BS |
158 | } |
159 | if ((e2 & DESC_C_MASK) && dpl > rpl) { | |
77b2bc2c | 160 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 | 161 | } |
eaa728ee FB |
162 | } else if (seg_reg == R_SS) { |
163 | /* SS must be writable data */ | |
20054ef0 | 164 | if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) { |
77b2bc2c | 165 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 BS |
166 | } |
167 | if (dpl != cpl || dpl != rpl) { | |
77b2bc2c | 168 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 | 169 | } |
eaa728ee FB |
170 | } else { |
171 | /* not readable code */ | |
20054ef0 | 172 | if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) { |
77b2bc2c | 173 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 | 174 | } |
eaa728ee FB |
175 | /* if data or non conforming code, checks the rights */ |
176 | if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) { | |
20054ef0 | 177 | if (dpl < cpl || dpl < rpl) { |
77b2bc2c | 178 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 | 179 | } |
eaa728ee FB |
180 | } |
181 | } | |
20054ef0 | 182 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 183 | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc); |
20054ef0 | 184 | } |
eaa728ee | 185 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
20054ef0 BS |
186 | get_seg_base(e1, e2), |
187 | get_seg_limit(e1, e2), | |
188 | e2); | |
eaa728ee | 189 | } else { |
20054ef0 | 190 | if (seg_reg == R_SS || seg_reg == R_CS) { |
77b2bc2c | 191 | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc); |
20054ef0 | 192 | } |
eaa728ee FB |
193 | } |
194 | } | |
195 | ||
196 | #define SWITCH_TSS_JMP 0 | |
197 | #define SWITCH_TSS_IRET 1 | |
198 | #define SWITCH_TSS_CALL 2 | |
199 | ||
200 | /* XXX: restore CPU state in registers (PowerPC case) */ | |
2999a0b2 | 201 | static void switch_tss(CPUX86State *env, int tss_selector, |
eaa728ee FB |
202 | uint32_t e1, uint32_t e2, int source, |
203 | uint32_t next_eip) | |
204 | { | |
205 | int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i; | |
206 | target_ulong tss_base; | |
207 | uint32_t new_regs[8], new_segs[6]; | |
208 | uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap; | |
209 | uint32_t old_eflags, eflags_mask; | |
210 | SegmentCache *dt; | |
211 | int index; | |
212 | target_ulong ptr; | |
213 | ||
214 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; | |
20054ef0 BS |
215 | LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, |
216 | source); | |
eaa728ee FB |
217 | |
218 | /* if task gate, we read the TSS segment and we load it */ | |
219 | if (type == 5) { | |
20054ef0 | 220 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 221 | raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc); |
20054ef0 | 222 | } |
eaa728ee | 223 | tss_selector = e1 >> 16; |
20054ef0 | 224 | if (tss_selector & 4) { |
77b2bc2c | 225 | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc); |
20054ef0 | 226 | } |
2999a0b2 | 227 | if (load_segment(env, &e1, &e2, tss_selector) != 0) { |
77b2bc2c | 228 | raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc); |
20054ef0 BS |
229 | } |
230 | if (e2 & DESC_S_MASK) { | |
77b2bc2c | 231 | raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc); |
20054ef0 | 232 | } |
eaa728ee | 233 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; |
20054ef0 | 234 | if ((type & 7) != 1) { |
77b2bc2c | 235 | raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc); |
20054ef0 | 236 | } |
eaa728ee FB |
237 | } |
238 | ||
20054ef0 | 239 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 240 | raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc); |
20054ef0 | 241 | } |
eaa728ee | 242 | |
20054ef0 | 243 | if (type & 8) { |
eaa728ee | 244 | tss_limit_max = 103; |
20054ef0 | 245 | } else { |
eaa728ee | 246 | tss_limit_max = 43; |
20054ef0 | 247 | } |
eaa728ee FB |
248 | tss_limit = get_seg_limit(e1, e2); |
249 | tss_base = get_seg_base(e1, e2); | |
250 | if ((tss_selector & 4) != 0 || | |
20054ef0 | 251 | tss_limit < tss_limit_max) { |
77b2bc2c | 252 | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc); |
20054ef0 | 253 | } |
eaa728ee | 254 | old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; |
20054ef0 | 255 | if (old_type & 8) { |
eaa728ee | 256 | old_tss_limit_max = 103; |
20054ef0 | 257 | } else { |
eaa728ee | 258 | old_tss_limit_max = 43; |
20054ef0 | 259 | } |
eaa728ee FB |
260 | |
261 | /* read all the registers from the new TSS */ | |
262 | if (type & 8) { | |
263 | /* 32 bit */ | |
329e607d BS |
264 | new_cr3 = cpu_ldl_kernel(env, tss_base + 0x1c); |
265 | new_eip = cpu_ldl_kernel(env, tss_base + 0x20); | |
266 | new_eflags = cpu_ldl_kernel(env, tss_base + 0x24); | |
20054ef0 | 267 | for (i = 0; i < 8; i++) { |
329e607d | 268 | new_regs[i] = cpu_ldl_kernel(env, tss_base + (0x28 + i * 4)); |
20054ef0 BS |
269 | } |
270 | for (i = 0; i < 6; i++) { | |
329e607d | 271 | new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x48 + i * 4)); |
20054ef0 | 272 | } |
329e607d BS |
273 | new_ldt = cpu_lduw_kernel(env, tss_base + 0x60); |
274 | new_trap = cpu_ldl_kernel(env, tss_base + 0x64); | |
eaa728ee FB |
275 | } else { |
276 | /* 16 bit */ | |
277 | new_cr3 = 0; | |
329e607d BS |
278 | new_eip = cpu_lduw_kernel(env, tss_base + 0x0e); |
279 | new_eflags = cpu_lduw_kernel(env, tss_base + 0x10); | |
20054ef0 | 280 | for (i = 0; i < 8; i++) { |
329e607d BS |
281 | new_regs[i] = cpu_lduw_kernel(env, tss_base + (0x12 + i * 2)) | |
282 | 0xffff0000; | |
20054ef0 BS |
283 | } |
284 | for (i = 0; i < 4; i++) { | |
329e607d | 285 | new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x22 + i * 4)); |
20054ef0 | 286 | } |
329e607d | 287 | new_ldt = cpu_lduw_kernel(env, tss_base + 0x2a); |
eaa728ee FB |
288 | new_segs[R_FS] = 0; |
289 | new_segs[R_GS] = 0; | |
290 | new_trap = 0; | |
291 | } | |
4581cbcd BS |
292 | /* XXX: avoid a compiler warning, see |
293 | http://support.amd.com/us/Processor_TechDocs/24593.pdf | |
294 | chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */ | |
295 | (void)new_trap; | |
eaa728ee FB |
296 | |
297 | /* NOTE: we must avoid memory exceptions during the task switch, | |
298 | so we make dummy accesses before */ | |
299 | /* XXX: it can still fail in some cases, so a bigger hack is | |
300 | necessary to valid the TLB after having done the accesses */ | |
301 | ||
329e607d BS |
302 | v1 = cpu_ldub_kernel(env, env->tr.base); |
303 | v2 = cpu_ldub_kernel(env, env->tr.base + old_tss_limit_max); | |
304 | cpu_stb_kernel(env, env->tr.base, v1); | |
305 | cpu_stb_kernel(env, env->tr.base + old_tss_limit_max, v2); | |
eaa728ee FB |
306 | |
307 | /* clear busy bit (it is restartable) */ | |
308 | if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) { | |
309 | target_ulong ptr; | |
310 | uint32_t e2; | |
20054ef0 | 311 | |
eaa728ee | 312 | ptr = env->gdt.base + (env->tr.selector & ~7); |
329e607d | 313 | e2 = cpu_ldl_kernel(env, ptr + 4); |
eaa728ee | 314 | e2 &= ~DESC_TSS_BUSY_MASK; |
329e607d | 315 | cpu_stl_kernel(env, ptr + 4, e2); |
eaa728ee | 316 | } |
997ff0d9 | 317 | old_eflags = cpu_compute_eflags(env); |
20054ef0 | 318 | if (source == SWITCH_TSS_IRET) { |
eaa728ee | 319 | old_eflags &= ~NT_MASK; |
20054ef0 | 320 | } |
eaa728ee FB |
321 | |
322 | /* save the current state in the old TSS */ | |
323 | if (type & 8) { | |
324 | /* 32 bit */ | |
329e607d BS |
325 | cpu_stl_kernel(env, env->tr.base + 0x20, next_eip); |
326 | cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags); | |
4b34e3ad | 327 | cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]); |
a4165610 | 328 | cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]); |
00f5e6f2 | 329 | cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]); |
70b51365 | 330 | cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]); |
08b3ded6 | 331 | cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]); |
c12dddd7 | 332 | cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]); |
78c3c6d3 | 333 | cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI]); |
cf75c597 | 334 | cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI]); |
20054ef0 | 335 | for (i = 0; i < 6; i++) { |
329e607d BS |
336 | cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4), |
337 | env->segs[i].selector); | |
20054ef0 | 338 | } |
eaa728ee FB |
339 | } else { |
340 | /* 16 bit */ | |
329e607d BS |
341 | cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip); |
342 | cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags); | |
4b34e3ad | 343 | cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]); |
a4165610 | 344 | cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]); |
00f5e6f2 | 345 | cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]); |
70b51365 | 346 | cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]); |
08b3ded6 | 347 | cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]); |
c12dddd7 | 348 | cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]); |
78c3c6d3 | 349 | cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI]); |
cf75c597 | 350 | cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI]); |
20054ef0 | 351 | for (i = 0; i < 4; i++) { |
329e607d BS |
352 | cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4), |
353 | env->segs[i].selector); | |
20054ef0 | 354 | } |
eaa728ee FB |
355 | } |
356 | ||
357 | /* now if an exception occurs, it will occurs in the next task | |
358 | context */ | |
359 | ||
360 | if (source == SWITCH_TSS_CALL) { | |
329e607d | 361 | cpu_stw_kernel(env, tss_base, env->tr.selector); |
eaa728ee FB |
362 | new_eflags |= NT_MASK; |
363 | } | |
364 | ||
365 | /* set busy bit */ | |
366 | if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) { | |
367 | target_ulong ptr; | |
368 | uint32_t e2; | |
20054ef0 | 369 | |
eaa728ee | 370 | ptr = env->gdt.base + (tss_selector & ~7); |
329e607d | 371 | e2 = cpu_ldl_kernel(env, ptr + 4); |
eaa728ee | 372 | e2 |= DESC_TSS_BUSY_MASK; |
329e607d | 373 | cpu_stl_kernel(env, ptr + 4, e2); |
eaa728ee FB |
374 | } |
375 | ||
376 | /* set the new CPU state */ | |
377 | /* from this point, any exception which occurs can give problems */ | |
378 | env->cr[0] |= CR0_TS_MASK; | |
379 | env->hflags |= HF_TS_MASK; | |
380 | env->tr.selector = tss_selector; | |
381 | env->tr.base = tss_base; | |
382 | env->tr.limit = tss_limit; | |
383 | env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK; | |
384 | ||
385 | if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) { | |
386 | cpu_x86_update_cr3(env, new_cr3); | |
387 | } | |
388 | ||
389 | /* load all registers without an exception, then reload them with | |
390 | possible exception */ | |
391 | env->eip = new_eip; | |
392 | eflags_mask = TF_MASK | AC_MASK | ID_MASK | | |
393 | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK; | |
20054ef0 | 394 | if (!(type & 8)) { |
eaa728ee | 395 | eflags_mask &= 0xffff; |
20054ef0 | 396 | } |
997ff0d9 | 397 | cpu_load_eflags(env, new_eflags, eflags_mask); |
20054ef0 | 398 | /* XXX: what to do in 16 bit case? */ |
4b34e3ad | 399 | env->regs[R_EAX] = new_regs[0]; |
a4165610 | 400 | env->regs[R_ECX] = new_regs[1]; |
00f5e6f2 | 401 | env->regs[R_EDX] = new_regs[2]; |
70b51365 | 402 | env->regs[R_EBX] = new_regs[3]; |
08b3ded6 | 403 | env->regs[R_ESP] = new_regs[4]; |
c12dddd7 | 404 | env->regs[R_EBP] = new_regs[5]; |
78c3c6d3 | 405 | env->regs[R_ESI] = new_regs[6]; |
cf75c597 | 406 | env->regs[R_EDI] = new_regs[7]; |
eaa728ee | 407 | if (new_eflags & VM_MASK) { |
20054ef0 | 408 | for (i = 0; i < 6; i++) { |
2999a0b2 | 409 | load_seg_vm(env, i, new_segs[i]); |
20054ef0 | 410 | } |
eaa728ee FB |
411 | /* in vm86, CPL is always 3 */ |
412 | cpu_x86_set_cpl(env, 3); | |
413 | } else { | |
414 | /* CPL is set the RPL of CS */ | |
415 | cpu_x86_set_cpl(env, new_segs[R_CS] & 3); | |
416 | /* first just selectors as the rest may trigger exceptions */ | |
20054ef0 | 417 | for (i = 0; i < 6; i++) { |
eaa728ee | 418 | cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0); |
20054ef0 | 419 | } |
eaa728ee FB |
420 | } |
421 | ||
422 | env->ldt.selector = new_ldt & ~4; | |
423 | env->ldt.base = 0; | |
424 | env->ldt.limit = 0; | |
425 | env->ldt.flags = 0; | |
426 | ||
427 | /* load the LDT */ | |
20054ef0 | 428 | if (new_ldt & 4) { |
77b2bc2c | 429 | raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc); |
20054ef0 | 430 | } |
eaa728ee FB |
431 | |
432 | if ((new_ldt & 0xfffc) != 0) { | |
433 | dt = &env->gdt; | |
434 | index = new_ldt & ~7; | |
20054ef0 | 435 | if ((index + 7) > dt->limit) { |
77b2bc2c | 436 | raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc); |
20054ef0 | 437 | } |
eaa728ee | 438 | ptr = dt->base + index; |
329e607d BS |
439 | e1 = cpu_ldl_kernel(env, ptr); |
440 | e2 = cpu_ldl_kernel(env, ptr + 4); | |
20054ef0 | 441 | if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { |
77b2bc2c | 442 | raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc); |
20054ef0 BS |
443 | } |
444 | if (!(e2 & DESC_P_MASK)) { | |
77b2bc2c | 445 | raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc); |
20054ef0 | 446 | } |
eaa728ee FB |
447 | load_seg_cache_raw_dt(&env->ldt, e1, e2); |
448 | } | |
449 | ||
450 | /* load the segments */ | |
451 | if (!(new_eflags & VM_MASK)) { | |
2999a0b2 BS |
452 | tss_load_seg(env, R_CS, new_segs[R_CS]); |
453 | tss_load_seg(env, R_SS, new_segs[R_SS]); | |
454 | tss_load_seg(env, R_ES, new_segs[R_ES]); | |
455 | tss_load_seg(env, R_DS, new_segs[R_DS]); | |
456 | tss_load_seg(env, R_FS, new_segs[R_FS]); | |
457 | tss_load_seg(env, R_GS, new_segs[R_GS]); | |
eaa728ee FB |
458 | } |
459 | ||
a78d0eab | 460 | /* check that env->eip is in the CS segment limits */ |
eaa728ee | 461 | if (new_eip > env->segs[R_CS].limit) { |
20054ef0 | 462 | /* XXX: different exception if CALL? */ |
77b2bc2c | 463 | raise_exception_err(env, EXCP0D_GPF, 0); |
eaa728ee | 464 | } |
01df040b AL |
465 | |
466 | #ifndef CONFIG_USER_ONLY | |
467 | /* reset local breakpoints */ | |
428065ce LG |
468 | if (env->dr[7] & DR7_LOCAL_BP_MASK) { |
469 | for (i = 0; i < DR7_MAX_BP; i++) { | |
5902564a LG |
470 | if (hw_local_breakpoint_enabled(env->dr[7], i) && |
471 | !hw_global_breakpoint_enabled(env->dr[7], i)) { | |
01df040b | 472 | hw_breakpoint_remove(env, i); |
20054ef0 | 473 | } |
01df040b | 474 | } |
428065ce | 475 | env->dr[7] &= ~DR7_LOCAL_BP_MASK; |
01df040b AL |
476 | } |
477 | #endif | |
eaa728ee FB |
478 | } |
479 | ||
eaa728ee FB |
480 | static inline unsigned int get_sp_mask(unsigned int e2) |
481 | { | |
20054ef0 | 482 | if (e2 & DESC_B_MASK) { |
eaa728ee | 483 | return 0xffffffff; |
20054ef0 | 484 | } else { |
eaa728ee | 485 | return 0xffff; |
20054ef0 | 486 | } |
eaa728ee FB |
487 | } |
488 | ||
20054ef0 | 489 | static int exception_has_error_code(int intno) |
2ed51f5b | 490 | { |
20054ef0 BS |
491 | switch (intno) { |
492 | case 8: | |
493 | case 10: | |
494 | case 11: | |
495 | case 12: | |
496 | case 13: | |
497 | case 14: | |
498 | case 17: | |
499 | return 1; | |
500 | } | |
501 | return 0; | |
2ed51f5b AL |
502 | } |
503 | ||
eaa728ee | 504 | #ifdef TARGET_X86_64 |
08b3ded6 LG |
505 | #define SET_ESP(val, sp_mask) \ |
506 | do { \ | |
507 | if ((sp_mask) == 0xffff) { \ | |
508 | env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \ | |
509 | ((val) & 0xffff); \ | |
510 | } else if ((sp_mask) == 0xffffffffLL) { \ | |
511 | env->regs[R_ESP] = (uint32_t)(val); \ | |
512 | } else { \ | |
513 | env->regs[R_ESP] = (val); \ | |
514 | } \ | |
20054ef0 | 515 | } while (0) |
eaa728ee | 516 | #else |
08b3ded6 LG |
517 | #define SET_ESP(val, sp_mask) \ |
518 | do { \ | |
519 | env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \ | |
520 | ((val) & (sp_mask)); \ | |
20054ef0 | 521 | } while (0) |
eaa728ee FB |
522 | #endif |
523 | ||
c0a04f0e AL |
524 | /* in 64-bit machines, this can overflow. So this segment addition macro |
525 | * can be used to trim the value to 32-bit whenever needed */ | |
526 | #define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask)))) | |
527 | ||
eaa728ee | 528 | /* XXX: add a is_user flag to have proper security support */ |
329e607d BS |
529 | #define PUSHW(ssp, sp, sp_mask, val) \ |
530 | { \ | |
531 | sp -= 2; \ | |
532 | cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \ | |
20054ef0 | 533 | } |
eaa728ee | 534 | |
20054ef0 BS |
535 | #define PUSHL(ssp, sp, sp_mask, val) \ |
536 | { \ | |
537 | sp -= 4; \ | |
329e607d | 538 | cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \ |
20054ef0 | 539 | } |
eaa728ee | 540 | |
329e607d BS |
541 | #define POPW(ssp, sp, sp_mask, val) \ |
542 | { \ | |
543 | val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \ | |
544 | sp += 2; \ | |
20054ef0 | 545 | } |
eaa728ee | 546 | |
329e607d BS |
547 | #define POPL(ssp, sp, sp_mask, val) \ |
548 | { \ | |
549 | val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \ | |
550 | sp += 4; \ | |
20054ef0 | 551 | } |
eaa728ee FB |
552 | |
553 | /* protected mode interrupt */ | |
2999a0b2 BS |
554 | static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, |
555 | int error_code, unsigned int next_eip, | |
556 | int is_hw) | |
eaa728ee FB |
557 | { |
558 | SegmentCache *dt; | |
559 | target_ulong ptr, ssp; | |
560 | int type, dpl, selector, ss_dpl, cpl; | |
561 | int has_error_code, new_stack, shift; | |
1c918eba | 562 | uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0; |
eaa728ee | 563 | uint32_t old_eip, sp_mask; |
eaa728ee | 564 | |
eaa728ee | 565 | has_error_code = 0; |
20054ef0 BS |
566 | if (!is_int && !is_hw) { |
567 | has_error_code = exception_has_error_code(intno); | |
568 | } | |
569 | if (is_int) { | |
eaa728ee | 570 | old_eip = next_eip; |
20054ef0 | 571 | } else { |
eaa728ee | 572 | old_eip = env->eip; |
20054ef0 | 573 | } |
eaa728ee FB |
574 | |
575 | dt = &env->idt; | |
20054ef0 | 576 | if (intno * 8 + 7 > dt->limit) { |
77b2bc2c | 577 | raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
20054ef0 | 578 | } |
eaa728ee | 579 | ptr = dt->base + intno * 8; |
329e607d BS |
580 | e1 = cpu_ldl_kernel(env, ptr); |
581 | e2 = cpu_ldl_kernel(env, ptr + 4); | |
eaa728ee FB |
582 | /* check gate type */ |
583 | type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; | |
20054ef0 | 584 | switch (type) { |
eaa728ee FB |
585 | case 5: /* task gate */ |
586 | /* must do that check here to return the correct error code */ | |
20054ef0 | 587 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 588 | raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); |
20054ef0 | 589 | } |
2999a0b2 | 590 | switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip); |
eaa728ee FB |
591 | if (has_error_code) { |
592 | int type; | |
593 | uint32_t mask; | |
20054ef0 | 594 | |
eaa728ee FB |
595 | /* push the error code */ |
596 | type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; | |
597 | shift = type >> 3; | |
20054ef0 | 598 | if (env->segs[R_SS].flags & DESC_B_MASK) { |
eaa728ee | 599 | mask = 0xffffffff; |
20054ef0 | 600 | } else { |
eaa728ee | 601 | mask = 0xffff; |
20054ef0 | 602 | } |
08b3ded6 | 603 | esp = (env->regs[R_ESP] - (2 << shift)) & mask; |
eaa728ee | 604 | ssp = env->segs[R_SS].base + esp; |
20054ef0 | 605 | if (shift) { |
329e607d | 606 | cpu_stl_kernel(env, ssp, error_code); |
20054ef0 | 607 | } else { |
329e607d | 608 | cpu_stw_kernel(env, ssp, error_code); |
20054ef0 | 609 | } |
eaa728ee FB |
610 | SET_ESP(esp, mask); |
611 | } | |
612 | return; | |
613 | case 6: /* 286 interrupt gate */ | |
614 | case 7: /* 286 trap gate */ | |
615 | case 14: /* 386 interrupt gate */ | |
616 | case 15: /* 386 trap gate */ | |
617 | break; | |
618 | default: | |
77b2bc2c | 619 | raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
eaa728ee FB |
620 | break; |
621 | } | |
622 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
623 | cpl = env->hflags & HF_CPL_MASK; | |
1235fc06 | 624 | /* check privilege if software int */ |
20054ef0 | 625 | if (is_int && dpl < cpl) { |
77b2bc2c | 626 | raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
20054ef0 | 627 | } |
eaa728ee | 628 | /* check valid bit */ |
20054ef0 | 629 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 630 | raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); |
20054ef0 | 631 | } |
eaa728ee FB |
632 | selector = e1 >> 16; |
633 | offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); | |
20054ef0 | 634 | if ((selector & 0xfffc) == 0) { |
77b2bc2c | 635 | raise_exception_err(env, EXCP0D_GPF, 0); |
20054ef0 | 636 | } |
2999a0b2 | 637 | if (load_segment(env, &e1, &e2, selector) != 0) { |
77b2bc2c | 638 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 BS |
639 | } |
640 | if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) { | |
77b2bc2c | 641 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 642 | } |
eaa728ee | 643 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; |
20054ef0 | 644 | if (dpl > cpl) { |
77b2bc2c | 645 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 BS |
646 | } |
647 | if (!(e2 & DESC_P_MASK)) { | |
77b2bc2c | 648 | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc); |
20054ef0 | 649 | } |
eaa728ee FB |
650 | if (!(e2 & DESC_C_MASK) && dpl < cpl) { |
651 | /* to inner privilege */ | |
2999a0b2 | 652 | get_ss_esp_from_tss(env, &ss, &esp, dpl); |
20054ef0 | 653 | if ((ss & 0xfffc) == 0) { |
77b2bc2c | 654 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 BS |
655 | } |
656 | if ((ss & 3) != dpl) { | |
77b2bc2c | 657 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 | 658 | } |
2999a0b2 | 659 | if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) { |
77b2bc2c | 660 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 | 661 | } |
eaa728ee | 662 | ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3; |
20054ef0 | 663 | if (ss_dpl != dpl) { |
77b2bc2c | 664 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 | 665 | } |
eaa728ee FB |
666 | if (!(ss_e2 & DESC_S_MASK) || |
667 | (ss_e2 & DESC_CS_MASK) || | |
20054ef0 | 668 | !(ss_e2 & DESC_W_MASK)) { |
77b2bc2c | 669 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 BS |
670 | } |
671 | if (!(ss_e2 & DESC_P_MASK)) { | |
77b2bc2c | 672 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 | 673 | } |
eaa728ee FB |
674 | new_stack = 1; |
675 | sp_mask = get_sp_mask(ss_e2); | |
676 | ssp = get_seg_base(ss_e1, ss_e2); | |
677 | } else if ((e2 & DESC_C_MASK) || dpl == cpl) { | |
678 | /* to same privilege */ | |
20054ef0 | 679 | if (env->eflags & VM_MASK) { |
77b2bc2c | 680 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 681 | } |
eaa728ee FB |
682 | new_stack = 0; |
683 | sp_mask = get_sp_mask(env->segs[R_SS].flags); | |
684 | ssp = env->segs[R_SS].base; | |
08b3ded6 | 685 | esp = env->regs[R_ESP]; |
eaa728ee FB |
686 | dpl = cpl; |
687 | } else { | |
77b2bc2c | 688 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
eaa728ee FB |
689 | new_stack = 0; /* avoid warning */ |
690 | sp_mask = 0; /* avoid warning */ | |
691 | ssp = 0; /* avoid warning */ | |
692 | esp = 0; /* avoid warning */ | |
693 | } | |
694 | ||
695 | shift = type >> 3; | |
696 | ||
697 | #if 0 | |
698 | /* XXX: check that enough room is available */ | |
699 | push_size = 6 + (new_stack << 2) + (has_error_code << 1); | |
20054ef0 | 700 | if (env->eflags & VM_MASK) { |
eaa728ee | 701 | push_size += 8; |
20054ef0 | 702 | } |
eaa728ee FB |
703 | push_size <<= shift; |
704 | #endif | |
705 | if (shift == 1) { | |
706 | if (new_stack) { | |
707 | if (env->eflags & VM_MASK) { | |
708 | PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector); | |
709 | PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector); | |
710 | PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector); | |
711 | PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector); | |
712 | } | |
713 | PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector); | |
08b3ded6 | 714 | PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]); |
eaa728ee | 715 | } |
997ff0d9 | 716 | PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env)); |
eaa728ee FB |
717 | PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector); |
718 | PUSHL(ssp, esp, sp_mask, old_eip); | |
719 | if (has_error_code) { | |
720 | PUSHL(ssp, esp, sp_mask, error_code); | |
721 | } | |
722 | } else { | |
723 | if (new_stack) { | |
724 | if (env->eflags & VM_MASK) { | |
725 | PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector); | |
726 | PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector); | |
727 | PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector); | |
728 | PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector); | |
729 | } | |
730 | PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector); | |
08b3ded6 | 731 | PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]); |
eaa728ee | 732 | } |
997ff0d9 | 733 | PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env)); |
eaa728ee FB |
734 | PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector); |
735 | PUSHW(ssp, esp, sp_mask, old_eip); | |
736 | if (has_error_code) { | |
737 | PUSHW(ssp, esp, sp_mask, error_code); | |
738 | } | |
739 | } | |
740 | ||
741 | if (new_stack) { | |
742 | if (env->eflags & VM_MASK) { | |
743 | cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0); | |
744 | cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0); | |
745 | cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0); | |
746 | cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0); | |
747 | } | |
748 | ss = (ss & ~3) | dpl; | |
749 | cpu_x86_load_seg_cache(env, R_SS, ss, | |
750 | ssp, get_seg_limit(ss_e1, ss_e2), ss_e2); | |
751 | } | |
752 | SET_ESP(esp, sp_mask); | |
753 | ||
754 | selector = (selector & ~3) | dpl; | |
755 | cpu_x86_load_seg_cache(env, R_CS, selector, | |
756 | get_seg_base(e1, e2), | |
757 | get_seg_limit(e1, e2), | |
758 | e2); | |
759 | cpu_x86_set_cpl(env, dpl); | |
760 | env->eip = offset; | |
761 | ||
762 | /* interrupt gate clear IF mask */ | |
763 | if ((type & 1) == 0) { | |
764 | env->eflags &= ~IF_MASK; | |
765 | } | |
766 | env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); | |
767 | } | |
768 | ||
769 | #ifdef TARGET_X86_64 | |
770 | ||
20054ef0 BS |
771 | #define PUSHQ(sp, val) \ |
772 | { \ | |
773 | sp -= 8; \ | |
329e607d | 774 | cpu_stq_kernel(env, sp, (val)); \ |
20054ef0 | 775 | } |
eaa728ee | 776 | |
20054ef0 BS |
777 | #define POPQ(sp, val) \ |
778 | { \ | |
329e607d | 779 | val = cpu_ldq_kernel(env, sp); \ |
20054ef0 BS |
780 | sp += 8; \ |
781 | } | |
eaa728ee | 782 | |
2999a0b2 | 783 | static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) |
eaa728ee FB |
784 | { |
785 | int index; | |
786 | ||
787 | #if 0 | |
788 | printf("TR: base=" TARGET_FMT_lx " limit=%x\n", | |
789 | env->tr.base, env->tr.limit); | |
790 | #endif | |
791 | ||
20054ef0 | 792 | if (!(env->tr.flags & DESC_P_MASK)) { |
eaa728ee | 793 | cpu_abort(env, "invalid tss"); |
20054ef0 | 794 | } |
eaa728ee | 795 | index = 8 * level + 4; |
20054ef0 | 796 | if ((index + 7) > env->tr.limit) { |
77b2bc2c | 797 | raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc); |
20054ef0 | 798 | } |
329e607d | 799 | return cpu_ldq_kernel(env, env->tr.base + index); |
eaa728ee FB |
800 | } |
801 | ||
802 | /* 64 bit interrupt */ | |
2999a0b2 BS |
803 | static void do_interrupt64(CPUX86State *env, int intno, int is_int, |
804 | int error_code, target_ulong next_eip, int is_hw) | |
eaa728ee FB |
805 | { |
806 | SegmentCache *dt; | |
807 | target_ulong ptr; | |
808 | int type, dpl, selector, cpl, ist; | |
809 | int has_error_code, new_stack; | |
810 | uint32_t e1, e2, e3, ss; | |
811 | target_ulong old_eip, esp, offset; | |
eaa728ee | 812 | |
eaa728ee | 813 | has_error_code = 0; |
20054ef0 BS |
814 | if (!is_int && !is_hw) { |
815 | has_error_code = exception_has_error_code(intno); | |
816 | } | |
817 | if (is_int) { | |
eaa728ee | 818 | old_eip = next_eip; |
20054ef0 | 819 | } else { |
eaa728ee | 820 | old_eip = env->eip; |
20054ef0 | 821 | } |
eaa728ee FB |
822 | |
823 | dt = &env->idt; | |
20054ef0 | 824 | if (intno * 16 + 15 > dt->limit) { |
77b2bc2c | 825 | raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
20054ef0 | 826 | } |
eaa728ee | 827 | ptr = dt->base + intno * 16; |
329e607d BS |
828 | e1 = cpu_ldl_kernel(env, ptr); |
829 | e2 = cpu_ldl_kernel(env, ptr + 4); | |
830 | e3 = cpu_ldl_kernel(env, ptr + 8); | |
eaa728ee FB |
831 | /* check gate type */ |
832 | type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; | |
20054ef0 | 833 | switch (type) { |
eaa728ee FB |
834 | case 14: /* 386 interrupt gate */ |
835 | case 15: /* 386 trap gate */ | |
836 | break; | |
837 | default: | |
77b2bc2c | 838 | raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
eaa728ee FB |
839 | break; |
840 | } | |
841 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
842 | cpl = env->hflags & HF_CPL_MASK; | |
1235fc06 | 843 | /* check privilege if software int */ |
20054ef0 | 844 | if (is_int && dpl < cpl) { |
77b2bc2c | 845 | raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
20054ef0 | 846 | } |
eaa728ee | 847 | /* check valid bit */ |
20054ef0 | 848 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 849 | raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2); |
20054ef0 | 850 | } |
eaa728ee FB |
851 | selector = e1 >> 16; |
852 | offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff); | |
853 | ist = e2 & 7; | |
20054ef0 | 854 | if ((selector & 0xfffc) == 0) { |
77b2bc2c | 855 | raise_exception_err(env, EXCP0D_GPF, 0); |
20054ef0 | 856 | } |
eaa728ee | 857 | |
2999a0b2 | 858 | if (load_segment(env, &e1, &e2, selector) != 0) { |
77b2bc2c | 859 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 BS |
860 | } |
861 | if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) { | |
77b2bc2c | 862 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 863 | } |
eaa728ee | 864 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; |
20054ef0 | 865 | if (dpl > cpl) { |
77b2bc2c | 866 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 BS |
867 | } |
868 | if (!(e2 & DESC_P_MASK)) { | |
77b2bc2c | 869 | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc); |
20054ef0 BS |
870 | } |
871 | if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) { | |
77b2bc2c | 872 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 873 | } |
eaa728ee FB |
874 | if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) { |
875 | /* to inner privilege */ | |
20054ef0 | 876 | if (ist != 0) { |
2999a0b2 | 877 | esp = get_rsp_from_tss(env, ist + 3); |
20054ef0 | 878 | } else { |
2999a0b2 | 879 | esp = get_rsp_from_tss(env, dpl); |
20054ef0 | 880 | } |
eaa728ee FB |
881 | esp &= ~0xfLL; /* align stack */ |
882 | ss = 0; | |
883 | new_stack = 1; | |
884 | } else if ((e2 & DESC_C_MASK) || dpl == cpl) { | |
885 | /* to same privilege */ | |
20054ef0 | 886 | if (env->eflags & VM_MASK) { |
77b2bc2c | 887 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 888 | } |
eaa728ee | 889 | new_stack = 0; |
20054ef0 | 890 | if (ist != 0) { |
2999a0b2 | 891 | esp = get_rsp_from_tss(env, ist + 3); |
20054ef0 | 892 | } else { |
08b3ded6 | 893 | esp = env->regs[R_ESP]; |
20054ef0 | 894 | } |
eaa728ee FB |
895 | esp &= ~0xfLL; /* align stack */ |
896 | dpl = cpl; | |
897 | } else { | |
77b2bc2c | 898 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
eaa728ee FB |
899 | new_stack = 0; /* avoid warning */ |
900 | esp = 0; /* avoid warning */ | |
901 | } | |
902 | ||
903 | PUSHQ(esp, env->segs[R_SS].selector); | |
08b3ded6 | 904 | PUSHQ(esp, env->regs[R_ESP]); |
997ff0d9 | 905 | PUSHQ(esp, cpu_compute_eflags(env)); |
eaa728ee FB |
906 | PUSHQ(esp, env->segs[R_CS].selector); |
907 | PUSHQ(esp, old_eip); | |
908 | if (has_error_code) { | |
909 | PUSHQ(esp, error_code); | |
910 | } | |
911 | ||
912 | if (new_stack) { | |
913 | ss = 0 | dpl; | |
914 | cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0); | |
915 | } | |
08b3ded6 | 916 | env->regs[R_ESP] = esp; |
eaa728ee FB |
917 | |
918 | selector = (selector & ~3) | dpl; | |
919 | cpu_x86_load_seg_cache(env, R_CS, selector, | |
920 | get_seg_base(e1, e2), | |
921 | get_seg_limit(e1, e2), | |
922 | e2); | |
923 | cpu_x86_set_cpl(env, dpl); | |
924 | env->eip = offset; | |
925 | ||
926 | /* interrupt gate clear IF mask */ | |
927 | if ((type & 1) == 0) { | |
928 | env->eflags &= ~IF_MASK; | |
929 | } | |
930 | env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); | |
931 | } | |
932 | #endif | |
933 | ||
d9957a8b | 934 | #ifdef TARGET_X86_64 |
eaa728ee | 935 | #if defined(CONFIG_USER_ONLY) |
2999a0b2 | 936 | void helper_syscall(CPUX86State *env, int next_eip_addend) |
eaa728ee FB |
937 | { |
938 | env->exception_index = EXCP_SYSCALL; | |
939 | env->exception_next_eip = env->eip + next_eip_addend; | |
1162c041 | 940 | cpu_loop_exit(env); |
eaa728ee FB |
941 | } |
942 | #else | |
2999a0b2 | 943 | void helper_syscall(CPUX86State *env, int next_eip_addend) |
eaa728ee FB |
944 | { |
945 | int selector; | |
946 | ||
947 | if (!(env->efer & MSR_EFER_SCE)) { | |
77b2bc2c | 948 | raise_exception_err(env, EXCP06_ILLOP, 0); |
eaa728ee FB |
949 | } |
950 | selector = (env->star >> 32) & 0xffff; | |
eaa728ee FB |
951 | if (env->hflags & HF_LMA_MASK) { |
952 | int code64; | |
953 | ||
a4165610 | 954 | env->regs[R_ECX] = env->eip + next_eip_addend; |
997ff0d9 | 955 | env->regs[11] = cpu_compute_eflags(env); |
eaa728ee FB |
956 | |
957 | code64 = env->hflags & HF_CS64_MASK; | |
958 | ||
959 | cpu_x86_set_cpl(env, 0); | |
960 | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, | |
961 | 0, 0xffffffff, | |
962 | DESC_G_MASK | DESC_P_MASK | | |
963 | DESC_S_MASK | | |
20054ef0 BS |
964 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
965 | DESC_L_MASK); | |
eaa728ee FB |
966 | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
967 | 0, 0xffffffff, | |
968 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
969 | DESC_S_MASK | | |
970 | DESC_W_MASK | DESC_A_MASK); | |
971 | env->eflags &= ~env->fmask; | |
997ff0d9 | 972 | cpu_load_eflags(env, env->eflags, 0); |
20054ef0 | 973 | if (code64) { |
eaa728ee | 974 | env->eip = env->lstar; |
20054ef0 | 975 | } else { |
eaa728ee | 976 | env->eip = env->cstar; |
20054ef0 | 977 | } |
d9957a8b | 978 | } else { |
a4165610 | 979 | env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend); |
eaa728ee FB |
980 | |
981 | cpu_x86_set_cpl(env, 0); | |
982 | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, | |
983 | 0, 0xffffffff, | |
984 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
985 | DESC_S_MASK | | |
986 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
987 | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, | |
988 | 0, 0xffffffff, | |
989 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
990 | DESC_S_MASK | | |
991 | DESC_W_MASK | DESC_A_MASK); | |
992 | env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK); | |
993 | env->eip = (uint32_t)env->star; | |
994 | } | |
995 | } | |
996 | #endif | |
d9957a8b | 997 | #endif |
eaa728ee | 998 | |
d9957a8b | 999 | #ifdef TARGET_X86_64 |
2999a0b2 | 1000 | void helper_sysret(CPUX86State *env, int dflag) |
eaa728ee FB |
1001 | { |
1002 | int cpl, selector; | |
1003 | ||
1004 | if (!(env->efer & MSR_EFER_SCE)) { | |
77b2bc2c | 1005 | raise_exception_err(env, EXCP06_ILLOP, 0); |
eaa728ee FB |
1006 | } |
1007 | cpl = env->hflags & HF_CPL_MASK; | |
1008 | if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) { | |
77b2bc2c | 1009 | raise_exception_err(env, EXCP0D_GPF, 0); |
eaa728ee FB |
1010 | } |
1011 | selector = (env->star >> 48) & 0xffff; | |
eaa728ee FB |
1012 | if (env->hflags & HF_LMA_MASK) { |
1013 | if (dflag == 2) { | |
1014 | cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3, | |
1015 | 0, 0xffffffff, | |
1016 | DESC_G_MASK | DESC_P_MASK | | |
1017 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1018 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | | |
1019 | DESC_L_MASK); | |
a4165610 | 1020 | env->eip = env->regs[R_ECX]; |
eaa728ee FB |
1021 | } else { |
1022 | cpu_x86_load_seg_cache(env, R_CS, selector | 3, | |
1023 | 0, 0xffffffff, | |
1024 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
1025 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1026 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
a4165610 | 1027 | env->eip = (uint32_t)env->regs[R_ECX]; |
eaa728ee FB |
1028 | } |
1029 | cpu_x86_load_seg_cache(env, R_SS, selector + 8, | |
1030 | 0, 0xffffffff, | |
1031 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
1032 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1033 | DESC_W_MASK | DESC_A_MASK); | |
997ff0d9 BS |
1034 | cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK |
1035 | | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | | |
1036 | NT_MASK); | |
eaa728ee | 1037 | cpu_x86_set_cpl(env, 3); |
d9957a8b | 1038 | } else { |
eaa728ee FB |
1039 | cpu_x86_load_seg_cache(env, R_CS, selector | 3, |
1040 | 0, 0xffffffff, | |
1041 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
1042 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1043 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
a4165610 | 1044 | env->eip = (uint32_t)env->regs[R_ECX]; |
eaa728ee FB |
1045 | cpu_x86_load_seg_cache(env, R_SS, selector + 8, |
1046 | 0, 0xffffffff, | |
1047 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
1048 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1049 | DESC_W_MASK | DESC_A_MASK); | |
1050 | env->eflags |= IF_MASK; | |
1051 | cpu_x86_set_cpl(env, 3); | |
1052 | } | |
eaa728ee | 1053 | } |
d9957a8b | 1054 | #endif |
eaa728ee FB |
1055 | |
1056 | /* real mode interrupt */ | |
2999a0b2 BS |
1057 | static void do_interrupt_real(CPUX86State *env, int intno, int is_int, |
1058 | int error_code, unsigned int next_eip) | |
eaa728ee FB |
1059 | { |
1060 | SegmentCache *dt; | |
1061 | target_ulong ptr, ssp; | |
1062 | int selector; | |
1063 | uint32_t offset, esp; | |
1064 | uint32_t old_cs, old_eip; | |
eaa728ee | 1065 | |
20054ef0 | 1066 | /* real mode (simpler!) */ |
eaa728ee | 1067 | dt = &env->idt; |
20054ef0 | 1068 | if (intno * 4 + 3 > dt->limit) { |
77b2bc2c | 1069 | raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
20054ef0 | 1070 | } |
eaa728ee | 1071 | ptr = dt->base + intno * 4; |
329e607d BS |
1072 | offset = cpu_lduw_kernel(env, ptr); |
1073 | selector = cpu_lduw_kernel(env, ptr + 2); | |
08b3ded6 | 1074 | esp = env->regs[R_ESP]; |
eaa728ee | 1075 | ssp = env->segs[R_SS].base; |
20054ef0 | 1076 | if (is_int) { |
eaa728ee | 1077 | old_eip = next_eip; |
20054ef0 | 1078 | } else { |
eaa728ee | 1079 | old_eip = env->eip; |
20054ef0 | 1080 | } |
eaa728ee | 1081 | old_cs = env->segs[R_CS].selector; |
20054ef0 | 1082 | /* XXX: use SS segment size? */ |
997ff0d9 | 1083 | PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env)); |
eaa728ee FB |
1084 | PUSHW(ssp, esp, 0xffff, old_cs); |
1085 | PUSHW(ssp, esp, 0xffff, old_eip); | |
1086 | ||
1087 | /* update processor state */ | |
08b3ded6 | 1088 | env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff); |
eaa728ee FB |
1089 | env->eip = offset; |
1090 | env->segs[R_CS].selector = selector; | |
1091 | env->segs[R_CS].base = (selector << 4); | |
1092 | env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK); | |
1093 | } | |
1094 | ||
e694d4e2 | 1095 | #if defined(CONFIG_USER_ONLY) |
eaa728ee | 1096 | /* fake user mode interrupt */ |
2999a0b2 BS |
1097 | static void do_interrupt_user(CPUX86State *env, int intno, int is_int, |
1098 | int error_code, target_ulong next_eip) | |
eaa728ee FB |
1099 | { |
1100 | SegmentCache *dt; | |
1101 | target_ulong ptr; | |
1102 | int dpl, cpl, shift; | |
1103 | uint32_t e2; | |
1104 | ||
1105 | dt = &env->idt; | |
1106 | if (env->hflags & HF_LMA_MASK) { | |
1107 | shift = 4; | |
1108 | } else { | |
1109 | shift = 3; | |
1110 | } | |
1111 | ptr = dt->base + (intno << shift); | |
329e607d | 1112 | e2 = cpu_ldl_kernel(env, ptr + 4); |
eaa728ee FB |
1113 | |
1114 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1115 | cpl = env->hflags & HF_CPL_MASK; | |
1235fc06 | 1116 | /* check privilege if software int */ |
20054ef0 | 1117 | if (is_int && dpl < cpl) { |
77b2bc2c | 1118 | raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2); |
20054ef0 | 1119 | } |
eaa728ee FB |
1120 | |
1121 | /* Since we emulate only user space, we cannot do more than | |
1122 | exiting the emulation with the suitable exception and error | |
1123 | code */ | |
20054ef0 | 1124 | if (is_int) { |
a78d0eab | 1125 | env->eip = next_eip; |
20054ef0 | 1126 | } |
eaa728ee FB |
1127 | } |
1128 | ||
e694d4e2 BS |
1129 | #else |
1130 | ||
2999a0b2 BS |
1131 | static void handle_even_inj(CPUX86State *env, int intno, int is_int, |
1132 | int error_code, int is_hw, int rm) | |
2ed51f5b | 1133 | { |
20054ef0 BS |
1134 | uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, |
1135 | control.event_inj)); | |
1136 | ||
2ed51f5b | 1137 | if (!(event_inj & SVM_EVTINJ_VALID)) { |
20054ef0 BS |
1138 | int type; |
1139 | ||
1140 | if (is_int) { | |
1141 | type = SVM_EVTINJ_TYPE_SOFT; | |
1142 | } else { | |
1143 | type = SVM_EVTINJ_TYPE_EXEPT; | |
1144 | } | |
1145 | event_inj = intno | type | SVM_EVTINJ_VALID; | |
1146 | if (!rm && exception_has_error_code(intno)) { | |
1147 | event_inj |= SVM_EVTINJ_VALID_ERR; | |
1148 | stl_phys(env->vm_vmcb + offsetof(struct vmcb, | |
1149 | control.event_inj_err), | |
1150 | error_code); | |
1151 | } | |
1152 | stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), | |
1153 | event_inj); | |
2ed51f5b AL |
1154 | } |
1155 | } | |
00ea18d1 | 1156 | #endif |
2ed51f5b | 1157 | |
eaa728ee FB |
1158 | /* |
1159 | * Begin execution of an interruption. is_int is TRUE if coming from | |
a78d0eab | 1160 | * the int instruction. next_eip is the env->eip value AFTER the interrupt |
eaa728ee FB |
1161 | * instruction. It is only relevant if is_int is TRUE. |
1162 | */ | |
ca4c810a | 1163 | static void do_interrupt_all(X86CPU *cpu, int intno, int is_int, |
2999a0b2 | 1164 | int error_code, target_ulong next_eip, int is_hw) |
eaa728ee | 1165 | { |
ca4c810a AF |
1166 | CPUX86State *env = &cpu->env; |
1167 | ||
8fec2b8c | 1168 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
eaa728ee FB |
1169 | if ((env->cr[0] & CR0_PE_MASK)) { |
1170 | static int count; | |
20054ef0 BS |
1171 | |
1172 | qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx | |
1173 | " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx, | |
1174 | count, intno, error_code, is_int, | |
1175 | env->hflags & HF_CPL_MASK, | |
a78d0eab LG |
1176 | env->segs[R_CS].selector, env->eip, |
1177 | (int)env->segs[R_CS].base + env->eip, | |
08b3ded6 | 1178 | env->segs[R_SS].selector, env->regs[R_ESP]); |
eaa728ee | 1179 | if (intno == 0x0e) { |
93fcfe39 | 1180 | qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]); |
eaa728ee | 1181 | } else { |
4b34e3ad | 1182 | qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]); |
eaa728ee | 1183 | } |
93fcfe39 | 1184 | qemu_log("\n"); |
a0762859 | 1185 | log_cpu_state(CPU(cpu), CPU_DUMP_CCOP); |
eaa728ee FB |
1186 | #if 0 |
1187 | { | |
1188 | int i; | |
9bd5494e | 1189 | target_ulong ptr; |
20054ef0 | 1190 | |
93fcfe39 | 1191 | qemu_log(" code="); |
eaa728ee | 1192 | ptr = env->segs[R_CS].base + env->eip; |
20054ef0 | 1193 | for (i = 0; i < 16; i++) { |
93fcfe39 | 1194 | qemu_log(" %02x", ldub(ptr + i)); |
eaa728ee | 1195 | } |
93fcfe39 | 1196 | qemu_log("\n"); |
eaa728ee FB |
1197 | } |
1198 | #endif | |
1199 | count++; | |
1200 | } | |
1201 | } | |
1202 | if (env->cr[0] & CR0_PE_MASK) { | |
00ea18d1 | 1203 | #if !defined(CONFIG_USER_ONLY) |
20054ef0 | 1204 | if (env->hflags & HF_SVMI_MASK) { |
2999a0b2 | 1205 | handle_even_inj(env, intno, is_int, error_code, is_hw, 0); |
20054ef0 | 1206 | } |
00ea18d1 | 1207 | #endif |
eb38c52c | 1208 | #ifdef TARGET_X86_64 |
eaa728ee | 1209 | if (env->hflags & HF_LMA_MASK) { |
2999a0b2 | 1210 | do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw); |
eaa728ee FB |
1211 | } else |
1212 | #endif | |
1213 | { | |
2999a0b2 BS |
1214 | do_interrupt_protected(env, intno, is_int, error_code, next_eip, |
1215 | is_hw); | |
eaa728ee FB |
1216 | } |
1217 | } else { | |
00ea18d1 | 1218 | #if !defined(CONFIG_USER_ONLY) |
20054ef0 | 1219 | if (env->hflags & HF_SVMI_MASK) { |
2999a0b2 | 1220 | handle_even_inj(env, intno, is_int, error_code, is_hw, 1); |
20054ef0 | 1221 | } |
00ea18d1 | 1222 | #endif |
2999a0b2 | 1223 | do_interrupt_real(env, intno, is_int, error_code, next_eip); |
eaa728ee | 1224 | } |
2ed51f5b | 1225 | |
00ea18d1 | 1226 | #if !defined(CONFIG_USER_ONLY) |
2ed51f5b | 1227 | if (env->hflags & HF_SVMI_MASK) { |
20054ef0 BS |
1228 | uint32_t event_inj = ldl_phys(env->vm_vmcb + |
1229 | offsetof(struct vmcb, | |
1230 | control.event_inj)); | |
1231 | ||
1232 | stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), | |
1233 | event_inj & ~SVM_EVTINJ_VALID); | |
2ed51f5b | 1234 | } |
00ea18d1 | 1235 | #endif |
eaa728ee FB |
1236 | } |
1237 | ||
97a8ea5a | 1238 | void x86_cpu_do_interrupt(CPUState *cs) |
e694d4e2 | 1239 | { |
97a8ea5a AF |
1240 | X86CPU *cpu = X86_CPU(cs); |
1241 | CPUX86State *env = &cpu->env; | |
1242 | ||
e694d4e2 BS |
1243 | #if defined(CONFIG_USER_ONLY) |
1244 | /* if user mode only, we simulate a fake exception | |
1245 | which will be handled outside the cpu execution | |
1246 | loop */ | |
2999a0b2 | 1247 | do_interrupt_user(env, env->exception_index, |
e694d4e2 BS |
1248 | env->exception_is_int, |
1249 | env->error_code, | |
1250 | env->exception_next_eip); | |
1251 | /* successfully delivered */ | |
1252 | env->old_exception = -1; | |
1253 | #else | |
1254 | /* simulate a real cpu exception. On i386, it can | |
1255 | trigger new exceptions, but we do not handle | |
1256 | double or triple faults yet. */ | |
ca4c810a | 1257 | do_interrupt_all(cpu, env->exception_index, |
e694d4e2 BS |
1258 | env->exception_is_int, |
1259 | env->error_code, | |
1260 | env->exception_next_eip, 0); | |
1261 | /* successfully delivered */ | |
1262 | env->old_exception = -1; | |
1263 | #endif | |
e694d4e2 BS |
1264 | } |
1265 | ||
2999a0b2 | 1266 | void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) |
e694d4e2 | 1267 | { |
ca4c810a | 1268 | do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw); |
e694d4e2 BS |
1269 | } |
1270 | ||
2999a0b2 BS |
1271 | void helper_enter_level(CPUX86State *env, int level, int data32, |
1272 | target_ulong t1) | |
eaa728ee FB |
1273 | { |
1274 | target_ulong ssp; | |
1275 | uint32_t esp_mask, esp, ebp; | |
1276 | ||
1277 | esp_mask = get_sp_mask(env->segs[R_SS].flags); | |
1278 | ssp = env->segs[R_SS].base; | |
c12dddd7 | 1279 | ebp = env->regs[R_EBP]; |
08b3ded6 | 1280 | esp = env->regs[R_ESP]; |
eaa728ee FB |
1281 | if (data32) { |
1282 | /* 32 bit */ | |
1283 | esp -= 4; | |
1284 | while (--level) { | |
1285 | esp -= 4; | |
1286 | ebp -= 4; | |
329e607d BS |
1287 | cpu_stl_data(env, ssp + (esp & esp_mask), |
1288 | cpu_ldl_data(env, ssp + (ebp & esp_mask))); | |
eaa728ee FB |
1289 | } |
1290 | esp -= 4; | |
329e607d | 1291 | cpu_stl_data(env, ssp + (esp & esp_mask), t1); |
eaa728ee FB |
1292 | } else { |
1293 | /* 16 bit */ | |
1294 | esp -= 2; | |
1295 | while (--level) { | |
1296 | esp -= 2; | |
1297 | ebp -= 2; | |
329e607d BS |
1298 | cpu_stw_data(env, ssp + (esp & esp_mask), |
1299 | cpu_lduw_data(env, ssp + (ebp & esp_mask))); | |
eaa728ee FB |
1300 | } |
1301 | esp -= 2; | |
329e607d | 1302 | cpu_stw_data(env, ssp + (esp & esp_mask), t1); |
eaa728ee FB |
1303 | } |
1304 | } | |
1305 | ||
1306 | #ifdef TARGET_X86_64 | |
2999a0b2 BS |
1307 | void helper_enter64_level(CPUX86State *env, int level, int data64, |
1308 | target_ulong t1) | |
eaa728ee FB |
1309 | { |
1310 | target_ulong esp, ebp; | |
20054ef0 | 1311 | |
c12dddd7 | 1312 | ebp = env->regs[R_EBP]; |
08b3ded6 | 1313 | esp = env->regs[R_ESP]; |
eaa728ee FB |
1314 | |
1315 | if (data64) { | |
1316 | /* 64 bit */ | |
1317 | esp -= 8; | |
1318 | while (--level) { | |
1319 | esp -= 8; | |
1320 | ebp -= 8; | |
329e607d | 1321 | cpu_stq_data(env, esp, cpu_ldq_data(env, ebp)); |
eaa728ee FB |
1322 | } |
1323 | esp -= 8; | |
329e607d | 1324 | cpu_stq_data(env, esp, t1); |
eaa728ee FB |
1325 | } else { |
1326 | /* 16 bit */ | |
1327 | esp -= 2; | |
1328 | while (--level) { | |
1329 | esp -= 2; | |
1330 | ebp -= 2; | |
329e607d | 1331 | cpu_stw_data(env, esp, cpu_lduw_data(env, ebp)); |
eaa728ee FB |
1332 | } |
1333 | esp -= 2; | |
329e607d | 1334 | cpu_stw_data(env, esp, t1); |
eaa728ee FB |
1335 | } |
1336 | } | |
1337 | #endif | |
1338 | ||
2999a0b2 | 1339 | void helper_lldt(CPUX86State *env, int selector) |
eaa728ee FB |
1340 | { |
1341 | SegmentCache *dt; | |
1342 | uint32_t e1, e2; | |
1343 | int index, entry_limit; | |
1344 | target_ulong ptr; | |
1345 | ||
1346 | selector &= 0xffff; | |
1347 | if ((selector & 0xfffc) == 0) { | |
1348 | /* XXX: NULL selector case: invalid LDT */ | |
1349 | env->ldt.base = 0; | |
1350 | env->ldt.limit = 0; | |
1351 | } else { | |
20054ef0 | 1352 | if (selector & 0x4) { |
77b2bc2c | 1353 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1354 | } |
eaa728ee FB |
1355 | dt = &env->gdt; |
1356 | index = selector & ~7; | |
1357 | #ifdef TARGET_X86_64 | |
20054ef0 | 1358 | if (env->hflags & HF_LMA_MASK) { |
eaa728ee | 1359 | entry_limit = 15; |
20054ef0 | 1360 | } else |
eaa728ee | 1361 | #endif |
20054ef0 | 1362 | { |
eaa728ee | 1363 | entry_limit = 7; |
20054ef0 BS |
1364 | } |
1365 | if ((index + entry_limit) > dt->limit) { | |
77b2bc2c | 1366 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1367 | } |
eaa728ee | 1368 | ptr = dt->base + index; |
329e607d BS |
1369 | e1 = cpu_ldl_kernel(env, ptr); |
1370 | e2 = cpu_ldl_kernel(env, ptr + 4); | |
20054ef0 | 1371 | if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { |
77b2bc2c | 1372 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 BS |
1373 | } |
1374 | if (!(e2 & DESC_P_MASK)) { | |
77b2bc2c | 1375 | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc); |
20054ef0 | 1376 | } |
eaa728ee FB |
1377 | #ifdef TARGET_X86_64 |
1378 | if (env->hflags & HF_LMA_MASK) { | |
1379 | uint32_t e3; | |
20054ef0 | 1380 | |
329e607d | 1381 | e3 = cpu_ldl_kernel(env, ptr + 8); |
eaa728ee FB |
1382 | load_seg_cache_raw_dt(&env->ldt, e1, e2); |
1383 | env->ldt.base |= (target_ulong)e3 << 32; | |
1384 | } else | |
1385 | #endif | |
1386 | { | |
1387 | load_seg_cache_raw_dt(&env->ldt, e1, e2); | |
1388 | } | |
1389 | } | |
1390 | env->ldt.selector = selector; | |
1391 | } | |
1392 | ||
2999a0b2 | 1393 | void helper_ltr(CPUX86State *env, int selector) |
eaa728ee FB |
1394 | { |
1395 | SegmentCache *dt; | |
1396 | uint32_t e1, e2; | |
1397 | int index, type, entry_limit; | |
1398 | target_ulong ptr; | |
1399 | ||
1400 | selector &= 0xffff; | |
1401 | if ((selector & 0xfffc) == 0) { | |
1402 | /* NULL selector case: invalid TR */ | |
1403 | env->tr.base = 0; | |
1404 | env->tr.limit = 0; | |
1405 | env->tr.flags = 0; | |
1406 | } else { | |
20054ef0 | 1407 | if (selector & 0x4) { |
77b2bc2c | 1408 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1409 | } |
eaa728ee FB |
1410 | dt = &env->gdt; |
1411 | index = selector & ~7; | |
1412 | #ifdef TARGET_X86_64 | |
20054ef0 | 1413 | if (env->hflags & HF_LMA_MASK) { |
eaa728ee | 1414 | entry_limit = 15; |
20054ef0 | 1415 | } else |
eaa728ee | 1416 | #endif |
20054ef0 | 1417 | { |
eaa728ee | 1418 | entry_limit = 7; |
20054ef0 BS |
1419 | } |
1420 | if ((index + entry_limit) > dt->limit) { | |
77b2bc2c | 1421 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1422 | } |
eaa728ee | 1423 | ptr = dt->base + index; |
329e607d BS |
1424 | e1 = cpu_ldl_kernel(env, ptr); |
1425 | e2 = cpu_ldl_kernel(env, ptr + 4); | |
eaa728ee FB |
1426 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; |
1427 | if ((e2 & DESC_S_MASK) || | |
20054ef0 | 1428 | (type != 1 && type != 9)) { |
77b2bc2c | 1429 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 BS |
1430 | } |
1431 | if (!(e2 & DESC_P_MASK)) { | |
77b2bc2c | 1432 | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc); |
20054ef0 | 1433 | } |
eaa728ee FB |
1434 | #ifdef TARGET_X86_64 |
1435 | if (env->hflags & HF_LMA_MASK) { | |
1436 | uint32_t e3, e4; | |
20054ef0 | 1437 | |
329e607d BS |
1438 | e3 = cpu_ldl_kernel(env, ptr + 8); |
1439 | e4 = cpu_ldl_kernel(env, ptr + 12); | |
20054ef0 | 1440 | if ((e4 >> DESC_TYPE_SHIFT) & 0xf) { |
77b2bc2c | 1441 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1442 | } |
eaa728ee FB |
1443 | load_seg_cache_raw_dt(&env->tr, e1, e2); |
1444 | env->tr.base |= (target_ulong)e3 << 32; | |
1445 | } else | |
1446 | #endif | |
1447 | { | |
1448 | load_seg_cache_raw_dt(&env->tr, e1, e2); | |
1449 | } | |
1450 | e2 |= DESC_TSS_BUSY_MASK; | |
329e607d | 1451 | cpu_stl_kernel(env, ptr + 4, e2); |
eaa728ee FB |
1452 | } |
1453 | env->tr.selector = selector; | |
1454 | } | |
1455 | ||
1456 | /* only works if protected mode and not VM86. seg_reg must be != R_CS */ | |
2999a0b2 | 1457 | void helper_load_seg(CPUX86State *env, int seg_reg, int selector) |
eaa728ee FB |
1458 | { |
1459 | uint32_t e1, e2; | |
1460 | int cpl, dpl, rpl; | |
1461 | SegmentCache *dt; | |
1462 | int index; | |
1463 | target_ulong ptr; | |
1464 | ||
1465 | selector &= 0xffff; | |
1466 | cpl = env->hflags & HF_CPL_MASK; | |
1467 | if ((selector & 0xfffc) == 0) { | |
1468 | /* null selector case */ | |
1469 | if (seg_reg == R_SS | |
1470 | #ifdef TARGET_X86_64 | |
1471 | && (!(env->hflags & HF_CS64_MASK) || cpl == 3) | |
1472 | #endif | |
20054ef0 | 1473 | ) { |
77b2bc2c | 1474 | raise_exception_err(env, EXCP0D_GPF, 0); |
20054ef0 | 1475 | } |
eaa728ee FB |
1476 | cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0); |
1477 | } else { | |
1478 | ||
20054ef0 | 1479 | if (selector & 0x4) { |
eaa728ee | 1480 | dt = &env->ldt; |
20054ef0 | 1481 | } else { |
eaa728ee | 1482 | dt = &env->gdt; |
20054ef0 | 1483 | } |
eaa728ee | 1484 | index = selector & ~7; |
20054ef0 | 1485 | if ((index + 7) > dt->limit) { |
77b2bc2c | 1486 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1487 | } |
eaa728ee | 1488 | ptr = dt->base + index; |
329e607d BS |
1489 | e1 = cpu_ldl_kernel(env, ptr); |
1490 | e2 = cpu_ldl_kernel(env, ptr + 4); | |
eaa728ee | 1491 | |
20054ef0 | 1492 | if (!(e2 & DESC_S_MASK)) { |
77b2bc2c | 1493 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1494 | } |
eaa728ee FB |
1495 | rpl = selector & 3; |
1496 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1497 | if (seg_reg == R_SS) { | |
1498 | /* must be writable segment */ | |
20054ef0 | 1499 | if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) { |
77b2bc2c | 1500 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 BS |
1501 | } |
1502 | if (rpl != cpl || dpl != cpl) { | |
77b2bc2c | 1503 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1504 | } |
eaa728ee FB |
1505 | } else { |
1506 | /* must be readable segment */ | |
20054ef0 | 1507 | if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) { |
77b2bc2c | 1508 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1509 | } |
eaa728ee FB |
1510 | |
1511 | if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) { | |
1512 | /* if not conforming code, test rights */ | |
20054ef0 | 1513 | if (dpl < cpl || dpl < rpl) { |
77b2bc2c | 1514 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1515 | } |
eaa728ee FB |
1516 | } |
1517 | } | |
1518 | ||
1519 | if (!(e2 & DESC_P_MASK)) { | |
20054ef0 | 1520 | if (seg_reg == R_SS) { |
77b2bc2c | 1521 | raise_exception_err(env, EXCP0C_STACK, selector & 0xfffc); |
20054ef0 | 1522 | } else { |
77b2bc2c | 1523 | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc); |
20054ef0 | 1524 | } |
eaa728ee FB |
1525 | } |
1526 | ||
1527 | /* set the access bit if not already set */ | |
1528 | if (!(e2 & DESC_A_MASK)) { | |
1529 | e2 |= DESC_A_MASK; | |
329e607d | 1530 | cpu_stl_kernel(env, ptr + 4, e2); |
eaa728ee FB |
1531 | } |
1532 | ||
1533 | cpu_x86_load_seg_cache(env, seg_reg, selector, | |
1534 | get_seg_base(e1, e2), | |
1535 | get_seg_limit(e1, e2), | |
1536 | e2); | |
1537 | #if 0 | |
93fcfe39 | 1538 | qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n", |
eaa728ee FB |
1539 | selector, (unsigned long)sc->base, sc->limit, sc->flags); |
1540 | #endif | |
1541 | } | |
1542 | } | |
1543 | ||
1544 | /* protected mode jump */ | |
2999a0b2 | 1545 | void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip, |
eaa728ee FB |
1546 | int next_eip_addend) |
1547 | { | |
1548 | int gate_cs, type; | |
1549 | uint32_t e1, e2, cpl, dpl, rpl, limit; | |
1550 | target_ulong next_eip; | |
1551 | ||
20054ef0 | 1552 | if ((new_cs & 0xfffc) == 0) { |
77b2bc2c | 1553 | raise_exception_err(env, EXCP0D_GPF, 0); |
20054ef0 | 1554 | } |
2999a0b2 | 1555 | if (load_segment(env, &e1, &e2, new_cs) != 0) { |
77b2bc2c | 1556 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1557 | } |
eaa728ee FB |
1558 | cpl = env->hflags & HF_CPL_MASK; |
1559 | if (e2 & DESC_S_MASK) { | |
20054ef0 | 1560 | if (!(e2 & DESC_CS_MASK)) { |
77b2bc2c | 1561 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1562 | } |
eaa728ee FB |
1563 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; |
1564 | if (e2 & DESC_C_MASK) { | |
1565 | /* conforming code segment */ | |
20054ef0 | 1566 | if (dpl > cpl) { |
77b2bc2c | 1567 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1568 | } |
eaa728ee FB |
1569 | } else { |
1570 | /* non conforming code segment */ | |
1571 | rpl = new_cs & 3; | |
20054ef0 | 1572 | if (rpl > cpl) { |
77b2bc2c | 1573 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 BS |
1574 | } |
1575 | if (dpl != cpl) { | |
77b2bc2c | 1576 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1577 | } |
eaa728ee | 1578 | } |
20054ef0 | 1579 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 1580 | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc); |
20054ef0 | 1581 | } |
eaa728ee FB |
1582 | limit = get_seg_limit(e1, e2); |
1583 | if (new_eip > limit && | |
20054ef0 | 1584 | !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) { |
77b2bc2c | 1585 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1586 | } |
eaa728ee FB |
1587 | cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl, |
1588 | get_seg_base(e1, e2), limit, e2); | |
a78d0eab | 1589 | env->eip = new_eip; |
eaa728ee FB |
1590 | } else { |
1591 | /* jump to call or task gate */ | |
1592 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1593 | rpl = new_cs & 3; | |
1594 | cpl = env->hflags & HF_CPL_MASK; | |
1595 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; | |
20054ef0 | 1596 | switch (type) { |
eaa728ee FB |
1597 | case 1: /* 286 TSS */ |
1598 | case 9: /* 386 TSS */ | |
1599 | case 5: /* task gate */ | |
20054ef0 | 1600 | if (dpl < cpl || dpl < rpl) { |
77b2bc2c | 1601 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1602 | } |
eaa728ee | 1603 | next_eip = env->eip + next_eip_addend; |
2999a0b2 | 1604 | switch_tss(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip); |
eaa728ee FB |
1605 | CC_OP = CC_OP_EFLAGS; |
1606 | break; | |
1607 | case 4: /* 286 call gate */ | |
1608 | case 12: /* 386 call gate */ | |
20054ef0 | 1609 | if ((dpl < cpl) || (dpl < rpl)) { |
77b2bc2c | 1610 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 BS |
1611 | } |
1612 | if (!(e2 & DESC_P_MASK)) { | |
77b2bc2c | 1613 | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc); |
20054ef0 | 1614 | } |
eaa728ee FB |
1615 | gate_cs = e1 >> 16; |
1616 | new_eip = (e1 & 0xffff); | |
20054ef0 | 1617 | if (type == 12) { |
eaa728ee | 1618 | new_eip |= (e2 & 0xffff0000); |
20054ef0 | 1619 | } |
2999a0b2 | 1620 | if (load_segment(env, &e1, &e2, gate_cs) != 0) { |
77b2bc2c | 1621 | raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc); |
20054ef0 | 1622 | } |
eaa728ee FB |
1623 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; |
1624 | /* must be code segment */ | |
1625 | if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) != | |
20054ef0 | 1626 | (DESC_S_MASK | DESC_CS_MASK))) { |
77b2bc2c | 1627 | raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc); |
20054ef0 | 1628 | } |
eaa728ee | 1629 | if (((e2 & DESC_C_MASK) && (dpl > cpl)) || |
20054ef0 | 1630 | (!(e2 & DESC_C_MASK) && (dpl != cpl))) { |
77b2bc2c | 1631 | raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc); |
20054ef0 BS |
1632 | } |
1633 | if (!(e2 & DESC_P_MASK)) { | |
77b2bc2c | 1634 | raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc); |
20054ef0 | 1635 | } |
eaa728ee | 1636 | limit = get_seg_limit(e1, e2); |
20054ef0 | 1637 | if (new_eip > limit) { |
77b2bc2c | 1638 | raise_exception_err(env, EXCP0D_GPF, 0); |
20054ef0 | 1639 | } |
eaa728ee FB |
1640 | cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl, |
1641 | get_seg_base(e1, e2), limit, e2); | |
a78d0eab | 1642 | env->eip = new_eip; |
eaa728ee FB |
1643 | break; |
1644 | default: | |
77b2bc2c | 1645 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
eaa728ee FB |
1646 | break; |
1647 | } | |
1648 | } | |
1649 | } | |
1650 | ||
1651 | /* real mode call */ | |
2999a0b2 | 1652 | void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1, |
eaa728ee FB |
1653 | int shift, int next_eip) |
1654 | { | |
1655 | int new_eip; | |
1656 | uint32_t esp, esp_mask; | |
1657 | target_ulong ssp; | |
1658 | ||
1659 | new_eip = new_eip1; | |
08b3ded6 | 1660 | esp = env->regs[R_ESP]; |
eaa728ee FB |
1661 | esp_mask = get_sp_mask(env->segs[R_SS].flags); |
1662 | ssp = env->segs[R_SS].base; | |
1663 | if (shift) { | |
1664 | PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector); | |
1665 | PUSHL(ssp, esp, esp_mask, next_eip); | |
1666 | } else { | |
1667 | PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector); | |
1668 | PUSHW(ssp, esp, esp_mask, next_eip); | |
1669 | } | |
1670 | ||
1671 | SET_ESP(esp, esp_mask); | |
1672 | env->eip = new_eip; | |
1673 | env->segs[R_CS].selector = new_cs; | |
1674 | env->segs[R_CS].base = (new_cs << 4); | |
1675 | } | |
1676 | ||
1677 | /* protected mode call */ | |
2999a0b2 | 1678 | void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, |
eaa728ee FB |
1679 | int shift, int next_eip_addend) |
1680 | { | |
1681 | int new_stack, i; | |
1682 | uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count; | |
1c918eba | 1683 | uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask; |
eaa728ee FB |
1684 | uint32_t val, limit, old_sp_mask; |
1685 | target_ulong ssp, old_ssp, next_eip; | |
1686 | ||
1687 | next_eip = env->eip + next_eip_addend; | |
d12d51d5 | 1688 | LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift); |
8995b7a0 | 1689 | LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); |
20054ef0 | 1690 | if ((new_cs & 0xfffc) == 0) { |
77b2bc2c | 1691 | raise_exception_err(env, EXCP0D_GPF, 0); |
20054ef0 | 1692 | } |
2999a0b2 | 1693 | if (load_segment(env, &e1, &e2, new_cs) != 0) { |
77b2bc2c | 1694 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1695 | } |
eaa728ee | 1696 | cpl = env->hflags & HF_CPL_MASK; |
d12d51d5 | 1697 | LOG_PCALL("desc=%08x:%08x\n", e1, e2); |
eaa728ee | 1698 | if (e2 & DESC_S_MASK) { |
20054ef0 | 1699 | if (!(e2 & DESC_CS_MASK)) { |
77b2bc2c | 1700 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1701 | } |
eaa728ee FB |
1702 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; |
1703 | if (e2 & DESC_C_MASK) { | |
1704 | /* conforming code segment */ | |
20054ef0 | 1705 | if (dpl > cpl) { |
77b2bc2c | 1706 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1707 | } |
eaa728ee FB |
1708 | } else { |
1709 | /* non conforming code segment */ | |
1710 | rpl = new_cs & 3; | |
20054ef0 | 1711 | if (rpl > cpl) { |
77b2bc2c | 1712 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 BS |
1713 | } |
1714 | if (dpl != cpl) { | |
77b2bc2c | 1715 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1716 | } |
eaa728ee | 1717 | } |
20054ef0 | 1718 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 1719 | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc); |
20054ef0 | 1720 | } |
eaa728ee FB |
1721 | |
1722 | #ifdef TARGET_X86_64 | |
1723 | /* XXX: check 16/32 bit cases in long mode */ | |
1724 | if (shift == 2) { | |
1725 | target_ulong rsp; | |
20054ef0 | 1726 | |
eaa728ee | 1727 | /* 64 bit case */ |
08b3ded6 | 1728 | rsp = env->regs[R_ESP]; |
eaa728ee FB |
1729 | PUSHQ(rsp, env->segs[R_CS].selector); |
1730 | PUSHQ(rsp, next_eip); | |
1731 | /* from this point, not restartable */ | |
08b3ded6 | 1732 | env->regs[R_ESP] = rsp; |
eaa728ee FB |
1733 | cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl, |
1734 | get_seg_base(e1, e2), | |
1735 | get_seg_limit(e1, e2), e2); | |
a78d0eab | 1736 | env->eip = new_eip; |
eaa728ee FB |
1737 | } else |
1738 | #endif | |
1739 | { | |
08b3ded6 | 1740 | sp = env->regs[R_ESP]; |
eaa728ee FB |
1741 | sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1742 | ssp = env->segs[R_SS].base; | |
1743 | if (shift) { | |
1744 | PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); | |
1745 | PUSHL(ssp, sp, sp_mask, next_eip); | |
1746 | } else { | |
1747 | PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); | |
1748 | PUSHW(ssp, sp, sp_mask, next_eip); | |
1749 | } | |
1750 | ||
1751 | limit = get_seg_limit(e1, e2); | |
20054ef0 | 1752 | if (new_eip > limit) { |
77b2bc2c | 1753 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1754 | } |
eaa728ee FB |
1755 | /* from this point, not restartable */ |
1756 | SET_ESP(sp, sp_mask); | |
1757 | cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl, | |
1758 | get_seg_base(e1, e2), limit, e2); | |
a78d0eab | 1759 | env->eip = new_eip; |
eaa728ee FB |
1760 | } |
1761 | } else { | |
1762 | /* check gate type */ | |
1763 | type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; | |
1764 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1765 | rpl = new_cs & 3; | |
20054ef0 | 1766 | switch (type) { |
eaa728ee FB |
1767 | case 1: /* available 286 TSS */ |
1768 | case 9: /* available 386 TSS */ | |
1769 | case 5: /* task gate */ | |
20054ef0 | 1770 | if (dpl < cpl || dpl < rpl) { |
77b2bc2c | 1771 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1772 | } |
2999a0b2 | 1773 | switch_tss(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip); |
eaa728ee FB |
1774 | CC_OP = CC_OP_EFLAGS; |
1775 | return; | |
1776 | case 4: /* 286 call gate */ | |
1777 | case 12: /* 386 call gate */ | |
1778 | break; | |
1779 | default: | |
77b2bc2c | 1780 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
eaa728ee FB |
1781 | break; |
1782 | } | |
1783 | shift = type >> 3; | |
1784 | ||
20054ef0 | 1785 | if (dpl < cpl || dpl < rpl) { |
77b2bc2c | 1786 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 1787 | } |
eaa728ee | 1788 | /* check valid bit */ |
20054ef0 | 1789 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 1790 | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc); |
20054ef0 | 1791 | } |
eaa728ee FB |
1792 | selector = e1 >> 16; |
1793 | offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); | |
1794 | param_count = e2 & 0x1f; | |
20054ef0 | 1795 | if ((selector & 0xfffc) == 0) { |
77b2bc2c | 1796 | raise_exception_err(env, EXCP0D_GPF, 0); |
20054ef0 | 1797 | } |
eaa728ee | 1798 | |
2999a0b2 | 1799 | if (load_segment(env, &e1, &e2, selector) != 0) { |
77b2bc2c | 1800 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 BS |
1801 | } |
1802 | if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) { | |
77b2bc2c | 1803 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 | 1804 | } |
eaa728ee | 1805 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; |
20054ef0 | 1806 | if (dpl > cpl) { |
77b2bc2c | 1807 | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); |
20054ef0 BS |
1808 | } |
1809 | if (!(e2 & DESC_P_MASK)) { | |
77b2bc2c | 1810 | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc); |
20054ef0 | 1811 | } |
eaa728ee FB |
1812 | |
1813 | if (!(e2 & DESC_C_MASK) && dpl < cpl) { | |
1814 | /* to inner privilege */ | |
2999a0b2 | 1815 | get_ss_esp_from_tss(env, &ss, &sp, dpl); |
90a2541b LG |
1816 | LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" |
1817 | TARGET_FMT_lx "\n", ss, sp, param_count, | |
1818 | env->regs[R_ESP]); | |
20054ef0 | 1819 | if ((ss & 0xfffc) == 0) { |
77b2bc2c | 1820 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 BS |
1821 | } |
1822 | if ((ss & 3) != dpl) { | |
77b2bc2c | 1823 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 | 1824 | } |
2999a0b2 | 1825 | if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) { |
77b2bc2c | 1826 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 | 1827 | } |
eaa728ee | 1828 | ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3; |
20054ef0 | 1829 | if (ss_dpl != dpl) { |
77b2bc2c | 1830 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 | 1831 | } |
eaa728ee FB |
1832 | if (!(ss_e2 & DESC_S_MASK) || |
1833 | (ss_e2 & DESC_CS_MASK) || | |
20054ef0 | 1834 | !(ss_e2 & DESC_W_MASK)) { |
77b2bc2c | 1835 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 BS |
1836 | } |
1837 | if (!(ss_e2 & DESC_P_MASK)) { | |
77b2bc2c | 1838 | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); |
20054ef0 | 1839 | } |
eaa728ee | 1840 | |
20054ef0 | 1841 | /* push_size = ((param_count * 2) + 8) << shift; */ |
eaa728ee FB |
1842 | |
1843 | old_sp_mask = get_sp_mask(env->segs[R_SS].flags); | |
1844 | old_ssp = env->segs[R_SS].base; | |
1845 | ||
1846 | sp_mask = get_sp_mask(ss_e2); | |
1847 | ssp = get_seg_base(ss_e1, ss_e2); | |
1848 | if (shift) { | |
1849 | PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector); | |
08b3ded6 | 1850 | PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]); |
20054ef0 | 1851 | for (i = param_count - 1; i >= 0; i--) { |
90a2541b LG |
1852 | val = cpu_ldl_kernel(env, old_ssp + |
1853 | ((env->regs[R_ESP] + i * 4) & | |
1854 | old_sp_mask)); | |
eaa728ee FB |
1855 | PUSHL(ssp, sp, sp_mask, val); |
1856 | } | |
1857 | } else { | |
1858 | PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector); | |
08b3ded6 | 1859 | PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]); |
20054ef0 | 1860 | for (i = param_count - 1; i >= 0; i--) { |
90a2541b LG |
1861 | val = cpu_lduw_kernel(env, old_ssp + |
1862 | ((env->regs[R_ESP] + i * 2) & | |
1863 | old_sp_mask)); | |
eaa728ee FB |
1864 | PUSHW(ssp, sp, sp_mask, val); |
1865 | } | |
1866 | } | |
1867 | new_stack = 1; | |
1868 | } else { | |
1869 | /* to same privilege */ | |
08b3ded6 | 1870 | sp = env->regs[R_ESP]; |
eaa728ee FB |
1871 | sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1872 | ssp = env->segs[R_SS].base; | |
20054ef0 | 1873 | /* push_size = (4 << shift); */ |
eaa728ee FB |
1874 | new_stack = 0; |
1875 | } | |
1876 | ||
1877 | if (shift) { | |
1878 | PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); | |
1879 | PUSHL(ssp, sp, sp_mask, next_eip); | |
1880 | } else { | |
1881 | PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); | |
1882 | PUSHW(ssp, sp, sp_mask, next_eip); | |
1883 | } | |
1884 | ||
1885 | /* from this point, not restartable */ | |
1886 | ||
1887 | if (new_stack) { | |
1888 | ss = (ss & ~3) | dpl; | |
1889 | cpu_x86_load_seg_cache(env, R_SS, ss, | |
1890 | ssp, | |
1891 | get_seg_limit(ss_e1, ss_e2), | |
1892 | ss_e2); | |
1893 | } | |
1894 | ||
1895 | selector = (selector & ~3) | dpl; | |
1896 | cpu_x86_load_seg_cache(env, R_CS, selector, | |
1897 | get_seg_base(e1, e2), | |
1898 | get_seg_limit(e1, e2), | |
1899 | e2); | |
1900 | cpu_x86_set_cpl(env, dpl); | |
1901 | SET_ESP(sp, sp_mask); | |
a78d0eab | 1902 | env->eip = offset; |
eaa728ee | 1903 | } |
eaa728ee FB |
1904 | } |
1905 | ||
1906 | /* real and vm86 mode iret */ | |
2999a0b2 | 1907 | void helper_iret_real(CPUX86State *env, int shift) |
eaa728ee FB |
1908 | { |
1909 | uint32_t sp, new_cs, new_eip, new_eflags, sp_mask; | |
1910 | target_ulong ssp; | |
1911 | int eflags_mask; | |
1912 | ||
20054ef0 | 1913 | sp_mask = 0xffff; /* XXXX: use SS segment size? */ |
08b3ded6 | 1914 | sp = env->regs[R_ESP]; |
eaa728ee FB |
1915 | ssp = env->segs[R_SS].base; |
1916 | if (shift == 1) { | |
1917 | /* 32 bits */ | |
1918 | POPL(ssp, sp, sp_mask, new_eip); | |
1919 | POPL(ssp, sp, sp_mask, new_cs); | |
1920 | new_cs &= 0xffff; | |
1921 | POPL(ssp, sp, sp_mask, new_eflags); | |
1922 | } else { | |
1923 | /* 16 bits */ | |
1924 | POPW(ssp, sp, sp_mask, new_eip); | |
1925 | POPW(ssp, sp, sp_mask, new_cs); | |
1926 | POPW(ssp, sp, sp_mask, new_eflags); | |
1927 | } | |
08b3ded6 | 1928 | env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask); |
bdadc0b5 | 1929 | env->segs[R_CS].selector = new_cs; |
1930 | env->segs[R_CS].base = (new_cs << 4); | |
eaa728ee | 1931 | env->eip = new_eip; |
20054ef0 BS |
1932 | if (env->eflags & VM_MASK) { |
1933 | eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | | |
1934 | NT_MASK; | |
1935 | } else { | |
1936 | eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | | |
1937 | RF_MASK | NT_MASK; | |
1938 | } | |
1939 | if (shift == 0) { | |
eaa728ee | 1940 | eflags_mask &= 0xffff; |
20054ef0 | 1941 | } |
997ff0d9 | 1942 | cpu_load_eflags(env, new_eflags, eflags_mask); |
db620f46 | 1943 | env->hflags2 &= ~HF2_NMI_MASK; |
eaa728ee FB |
1944 | } |
1945 | ||
2999a0b2 | 1946 | static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl) |
eaa728ee FB |
1947 | { |
1948 | int dpl; | |
1949 | uint32_t e2; | |
1950 | ||
1951 | /* XXX: on x86_64, we do not want to nullify FS and GS because | |
1952 | they may still contain a valid base. I would be interested to | |
1953 | know how a real x86_64 CPU behaves */ | |
1954 | if ((seg_reg == R_FS || seg_reg == R_GS) && | |
20054ef0 | 1955 | (env->segs[seg_reg].selector & 0xfffc) == 0) { |
eaa728ee | 1956 | return; |
20054ef0 | 1957 | } |
eaa728ee FB |
1958 | |
1959 | e2 = env->segs[seg_reg].flags; | |
1960 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1961 | if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) { | |
1962 | /* data or non conforming code segment */ | |
1963 | if (dpl < cpl) { | |
1964 | cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0); | |
1965 | } | |
1966 | } | |
1967 | } | |
1968 | ||
1969 | /* protected mode iret */ | |
2999a0b2 BS |
1970 | static inline void helper_ret_protected(CPUX86State *env, int shift, |
1971 | int is_iret, int addend) | |
eaa728ee FB |
1972 | { |
1973 | uint32_t new_cs, new_eflags, new_ss; | |
1974 | uint32_t new_es, new_ds, new_fs, new_gs; | |
1975 | uint32_t e1, e2, ss_e1, ss_e2; | |
1976 | int cpl, dpl, rpl, eflags_mask, iopl; | |
1977 | target_ulong ssp, sp, new_eip, new_esp, sp_mask; | |
1978 | ||
1979 | #ifdef TARGET_X86_64 | |
20054ef0 | 1980 | if (shift == 2) { |
eaa728ee | 1981 | sp_mask = -1; |
20054ef0 | 1982 | } else |
eaa728ee | 1983 | #endif |
20054ef0 | 1984 | { |
eaa728ee | 1985 | sp_mask = get_sp_mask(env->segs[R_SS].flags); |
20054ef0 | 1986 | } |
08b3ded6 | 1987 | sp = env->regs[R_ESP]; |
eaa728ee FB |
1988 | ssp = env->segs[R_SS].base; |
1989 | new_eflags = 0; /* avoid warning */ | |
1990 | #ifdef TARGET_X86_64 | |
1991 | if (shift == 2) { | |
1992 | POPQ(sp, new_eip); | |
1993 | POPQ(sp, new_cs); | |
1994 | new_cs &= 0xffff; | |
1995 | if (is_iret) { | |
1996 | POPQ(sp, new_eflags); | |
1997 | } | |
1998 | } else | |
1999 | #endif | |
20054ef0 BS |
2000 | { |
2001 | if (shift == 1) { | |
2002 | /* 32 bits */ | |
2003 | POPL(ssp, sp, sp_mask, new_eip); | |
2004 | POPL(ssp, sp, sp_mask, new_cs); | |
2005 | new_cs &= 0xffff; | |
2006 | if (is_iret) { | |
2007 | POPL(ssp, sp, sp_mask, new_eflags); | |
2008 | if (new_eflags & VM_MASK) { | |
2009 | goto return_to_vm86; | |
2010 | } | |
2011 | } | |
2012 | } else { | |
2013 | /* 16 bits */ | |
2014 | POPW(ssp, sp, sp_mask, new_eip); | |
2015 | POPW(ssp, sp, sp_mask, new_cs); | |
2016 | if (is_iret) { | |
2017 | POPW(ssp, sp, sp_mask, new_eflags); | |
2018 | } | |
eaa728ee | 2019 | } |
eaa728ee | 2020 | } |
d12d51d5 AL |
2021 | LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n", |
2022 | new_cs, new_eip, shift, addend); | |
8995b7a0 | 2023 | LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); |
20054ef0 | 2024 | if ((new_cs & 0xfffc) == 0) { |
77b2bc2c | 2025 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 2026 | } |
2999a0b2 | 2027 | if (load_segment(env, &e1, &e2, new_cs) != 0) { |
77b2bc2c | 2028 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 2029 | } |
eaa728ee | 2030 | if (!(e2 & DESC_S_MASK) || |
20054ef0 | 2031 | !(e2 & DESC_CS_MASK)) { |
77b2bc2c | 2032 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 2033 | } |
eaa728ee FB |
2034 | cpl = env->hflags & HF_CPL_MASK; |
2035 | rpl = new_cs & 3; | |
20054ef0 | 2036 | if (rpl < cpl) { |
77b2bc2c | 2037 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 2038 | } |
eaa728ee FB |
2039 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; |
2040 | if (e2 & DESC_C_MASK) { | |
20054ef0 | 2041 | if (dpl > rpl) { |
77b2bc2c | 2042 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 2043 | } |
eaa728ee | 2044 | } else { |
20054ef0 | 2045 | if (dpl != rpl) { |
77b2bc2c | 2046 | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc); |
20054ef0 | 2047 | } |
eaa728ee | 2048 | } |
20054ef0 | 2049 | if (!(e2 & DESC_P_MASK)) { |
77b2bc2c | 2050 | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc); |
20054ef0 | 2051 | } |
eaa728ee FB |
2052 | |
2053 | sp += addend; | |
2054 | if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) || | |
2055 | ((env->hflags & HF_CS64_MASK) && !is_iret))) { | |
1235fc06 | 2056 | /* return to same privilege level */ |
eaa728ee FB |
2057 | cpu_x86_load_seg_cache(env, R_CS, new_cs, |
2058 | get_seg_base(e1, e2), | |
2059 | get_seg_limit(e1, e2), | |
2060 | e2); | |
2061 | } else { | |
2062 | /* return to different privilege level */ | |
2063 | #ifdef TARGET_X86_64 | |
2064 | if (shift == 2) { | |
2065 | POPQ(sp, new_esp); | |
2066 | POPQ(sp, new_ss); | |
2067 | new_ss &= 0xffff; | |
2068 | } else | |
2069 | #endif | |
20054ef0 BS |
2070 | { |
2071 | if (shift == 1) { | |
2072 | /* 32 bits */ | |
2073 | POPL(ssp, sp, sp_mask, new_esp); | |
2074 | POPL(ssp, sp, sp_mask, new_ss); | |
2075 | new_ss &= 0xffff; | |
2076 | } else { | |
2077 | /* 16 bits */ | |
2078 | POPW(ssp, sp, sp_mask, new_esp); | |
2079 | POPW(ssp, sp, sp_mask, new_ss); | |
2080 | } | |
eaa728ee | 2081 | } |
d12d51d5 | 2082 | LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n", |
20054ef0 | 2083 | new_ss, new_esp); |
eaa728ee FB |
2084 | if ((new_ss & 0xfffc) == 0) { |
2085 | #ifdef TARGET_X86_64 | |
20054ef0 BS |
2086 | /* NULL ss is allowed in long mode if cpl != 3 */ |
2087 | /* XXX: test CS64? */ | |
eaa728ee FB |
2088 | if ((env->hflags & HF_LMA_MASK) && rpl != 3) { |
2089 | cpu_x86_load_seg_cache(env, R_SS, new_ss, | |
2090 | 0, 0xffffffff, | |
2091 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
2092 | DESC_S_MASK | (rpl << DESC_DPL_SHIFT) | | |
2093 | DESC_W_MASK | DESC_A_MASK); | |
20054ef0 | 2094 | ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */ |
eaa728ee FB |
2095 | } else |
2096 | #endif | |
2097 | { | |
77b2bc2c | 2098 | raise_exception_err(env, EXCP0D_GPF, 0); |
eaa728ee FB |
2099 | } |
2100 | } else { | |
20054ef0 | 2101 | if ((new_ss & 3) != rpl) { |
77b2bc2c | 2102 | raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc); |
20054ef0 | 2103 | } |
2999a0b2 | 2104 | if (load_segment(env, &ss_e1, &ss_e2, new_ss) != 0) { |
77b2bc2c | 2105 | raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc); |
20054ef0 | 2106 | } |
eaa728ee FB |
2107 | if (!(ss_e2 & DESC_S_MASK) || |
2108 | (ss_e2 & DESC_CS_MASK) || | |
20054ef0 | 2109 | !(ss_e2 & DESC_W_MASK)) { |
77b2bc2c | 2110 | raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc); |
20054ef0 | 2111 | } |
eaa728ee | 2112 | dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3; |
20054ef0 | 2113 | if (dpl != rpl) { |
77b2bc2c | 2114 | raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc); |
20054ef0 BS |
2115 | } |
2116 | if (!(ss_e2 & DESC_P_MASK)) { | |
77b2bc2c | 2117 | raise_exception_err(env, EXCP0B_NOSEG, new_ss & 0xfffc); |
20054ef0 | 2118 | } |
eaa728ee FB |
2119 | cpu_x86_load_seg_cache(env, R_SS, new_ss, |
2120 | get_seg_base(ss_e1, ss_e2), | |
2121 | get_seg_limit(ss_e1, ss_e2), | |
2122 | ss_e2); | |
2123 | } | |
2124 | ||
2125 | cpu_x86_load_seg_cache(env, R_CS, new_cs, | |
2126 | get_seg_base(e1, e2), | |
2127 | get_seg_limit(e1, e2), | |
2128 | e2); | |
2129 | cpu_x86_set_cpl(env, rpl); | |
2130 | sp = new_esp; | |
2131 | #ifdef TARGET_X86_64 | |
20054ef0 | 2132 | if (env->hflags & HF_CS64_MASK) { |
eaa728ee | 2133 | sp_mask = -1; |
20054ef0 | 2134 | } else |
eaa728ee | 2135 | #endif |
20054ef0 | 2136 | { |
eaa728ee | 2137 | sp_mask = get_sp_mask(ss_e2); |
20054ef0 | 2138 | } |
eaa728ee FB |
2139 | |
2140 | /* validate data segments */ | |
2999a0b2 BS |
2141 | validate_seg(env, R_ES, rpl); |
2142 | validate_seg(env, R_DS, rpl); | |
2143 | validate_seg(env, R_FS, rpl); | |
2144 | validate_seg(env, R_GS, rpl); | |
eaa728ee FB |
2145 | |
2146 | sp += addend; | |
2147 | } | |
2148 | SET_ESP(sp, sp_mask); | |
2149 | env->eip = new_eip; | |
2150 | if (is_iret) { | |
2151 | /* NOTE: 'cpl' is the _old_ CPL */ | |
2152 | eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK; | |
20054ef0 | 2153 | if (cpl == 0) { |
eaa728ee | 2154 | eflags_mask |= IOPL_MASK; |
20054ef0 | 2155 | } |
eaa728ee | 2156 | iopl = (env->eflags >> IOPL_SHIFT) & 3; |
20054ef0 | 2157 | if (cpl <= iopl) { |
eaa728ee | 2158 | eflags_mask |= IF_MASK; |
20054ef0 BS |
2159 | } |
2160 | if (shift == 0) { | |
eaa728ee | 2161 | eflags_mask &= 0xffff; |
20054ef0 | 2162 | } |
997ff0d9 | 2163 | cpu_load_eflags(env, new_eflags, eflags_mask); |
eaa728ee FB |
2164 | } |
2165 | return; | |
2166 | ||
2167 | return_to_vm86: | |
2168 | POPL(ssp, sp, sp_mask, new_esp); | |
2169 | POPL(ssp, sp, sp_mask, new_ss); | |
2170 | POPL(ssp, sp, sp_mask, new_es); | |
2171 | POPL(ssp, sp, sp_mask, new_ds); | |
2172 | POPL(ssp, sp, sp_mask, new_fs); | |
2173 | POPL(ssp, sp, sp_mask, new_gs); | |
2174 | ||
2175 | /* modify processor state */ | |
997ff0d9 BS |
2176 | cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK | |
2177 | IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | | |
2178 | VIP_MASK); | |
2999a0b2 | 2179 | load_seg_vm(env, R_CS, new_cs & 0xffff); |
eaa728ee | 2180 | cpu_x86_set_cpl(env, 3); |
2999a0b2 BS |
2181 | load_seg_vm(env, R_SS, new_ss & 0xffff); |
2182 | load_seg_vm(env, R_ES, new_es & 0xffff); | |
2183 | load_seg_vm(env, R_DS, new_ds & 0xffff); | |
2184 | load_seg_vm(env, R_FS, new_fs & 0xffff); | |
2185 | load_seg_vm(env, R_GS, new_gs & 0xffff); | |
eaa728ee FB |
2186 | |
2187 | env->eip = new_eip & 0xffff; | |
08b3ded6 | 2188 | env->regs[R_ESP] = new_esp; |
eaa728ee FB |
2189 | } |
2190 | ||
2999a0b2 | 2191 | void helper_iret_protected(CPUX86State *env, int shift, int next_eip) |
eaa728ee FB |
2192 | { |
2193 | int tss_selector, type; | |
2194 | uint32_t e1, e2; | |
2195 | ||
2196 | /* specific case for TSS */ | |
2197 | if (env->eflags & NT_MASK) { | |
2198 | #ifdef TARGET_X86_64 | |
20054ef0 | 2199 | if (env->hflags & HF_LMA_MASK) { |
77b2bc2c | 2200 | raise_exception_err(env, EXCP0D_GPF, 0); |
20054ef0 | 2201 | } |
eaa728ee | 2202 | #endif |
329e607d | 2203 | tss_selector = cpu_lduw_kernel(env, env->tr.base + 0); |
20054ef0 | 2204 | if (tss_selector & 4) { |
77b2bc2c | 2205 | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc); |
20054ef0 | 2206 | } |
2999a0b2 | 2207 | if (load_segment(env, &e1, &e2, tss_selector) != 0) { |
77b2bc2c | 2208 | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc); |
20054ef0 | 2209 | } |
eaa728ee FB |
2210 | type = (e2 >> DESC_TYPE_SHIFT) & 0x17; |
2211 | /* NOTE: we check both segment and busy TSS */ | |
20054ef0 | 2212 | if (type != 3) { |
77b2bc2c | 2213 | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc); |
20054ef0 | 2214 | } |
2999a0b2 | 2215 | switch_tss(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip); |
eaa728ee | 2216 | } else { |
2999a0b2 | 2217 | helper_ret_protected(env, shift, 1, 0); |
eaa728ee | 2218 | } |
db620f46 | 2219 | env->hflags2 &= ~HF2_NMI_MASK; |
eaa728ee FB |
2220 | } |
2221 | ||
2999a0b2 | 2222 | void helper_lret_protected(CPUX86State *env, int shift, int addend) |
eaa728ee | 2223 | { |
2999a0b2 | 2224 | helper_ret_protected(env, shift, 0, addend); |
eaa728ee FB |
2225 | } |
2226 | ||
2999a0b2 | 2227 | void helper_sysenter(CPUX86State *env) |
eaa728ee FB |
2228 | { |
2229 | if (env->sysenter_cs == 0) { | |
77b2bc2c | 2230 | raise_exception_err(env, EXCP0D_GPF, 0); |
eaa728ee FB |
2231 | } |
2232 | env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK); | |
2233 | cpu_x86_set_cpl(env, 0); | |
2436b61a AZ |
2234 | |
2235 | #ifdef TARGET_X86_64 | |
2236 | if (env->hflags & HF_LMA_MASK) { | |
2237 | cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc, | |
2238 | 0, 0xffffffff, | |
2239 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
2240 | DESC_S_MASK | | |
20054ef0 BS |
2241 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
2242 | DESC_L_MASK); | |
2436b61a AZ |
2243 | } else |
2244 | #endif | |
2245 | { | |
2246 | cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc, | |
2247 | 0, 0xffffffff, | |
2248 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
2249 | DESC_S_MASK | | |
2250 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
2251 | } | |
eaa728ee FB |
2252 | cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc, |
2253 | 0, 0xffffffff, | |
2254 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
2255 | DESC_S_MASK | | |
2256 | DESC_W_MASK | DESC_A_MASK); | |
08b3ded6 | 2257 | env->regs[R_ESP] = env->sysenter_esp; |
a78d0eab | 2258 | env->eip = env->sysenter_eip; |
eaa728ee FB |
2259 | } |
2260 | ||
2999a0b2 | 2261 | void helper_sysexit(CPUX86State *env, int dflag) |
eaa728ee FB |
2262 | { |
2263 | int cpl; | |
2264 | ||
2265 | cpl = env->hflags & HF_CPL_MASK; | |
2266 | if (env->sysenter_cs == 0 || cpl != 0) { | |
77b2bc2c | 2267 | raise_exception_err(env, EXCP0D_GPF, 0); |
eaa728ee FB |
2268 | } |
2269 | cpu_x86_set_cpl(env, 3); | |
2436b61a AZ |
2270 | #ifdef TARGET_X86_64 |
2271 | if (dflag == 2) { | |
20054ef0 BS |
2272 | cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) | |
2273 | 3, 0, 0xffffffff, | |
2436b61a AZ |
2274 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2275 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
20054ef0 BS |
2276 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
2277 | DESC_L_MASK); | |
2278 | cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) | | |
2279 | 3, 0, 0xffffffff, | |
2436b61a AZ |
2280 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2281 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
2282 | DESC_W_MASK | DESC_A_MASK); | |
2283 | } else | |
2284 | #endif | |
2285 | { | |
20054ef0 BS |
2286 | cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | |
2287 | 3, 0, 0xffffffff, | |
2436b61a AZ |
2288 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2289 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
2290 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
20054ef0 BS |
2291 | cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | |
2292 | 3, 0, 0xffffffff, | |
2436b61a AZ |
2293 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2294 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
2295 | DESC_W_MASK | DESC_A_MASK); | |
2296 | } | |
08b3ded6 | 2297 | env->regs[R_ESP] = env->regs[R_ECX]; |
a78d0eab | 2298 | env->eip = env->regs[R_EDX]; |
eaa728ee FB |
2299 | } |
2300 | ||
2999a0b2 | 2301 | target_ulong helper_lsl(CPUX86State *env, target_ulong selector1) |
eaa728ee FB |
2302 | { |
2303 | unsigned int limit; | |
2304 | uint32_t e1, e2, eflags, selector; | |
2305 | int rpl, dpl, cpl, type; | |
2306 | ||
2307 | selector = selector1 & 0xffff; | |
f0967a1a | 2308 | eflags = cpu_cc_compute_all(env, CC_OP); |
20054ef0 | 2309 | if ((selector & 0xfffc) == 0) { |
dc1ded53 | 2310 | goto fail; |
20054ef0 | 2311 | } |
2999a0b2 | 2312 | if (load_segment(env, &e1, &e2, selector) != 0) { |
eaa728ee | 2313 | goto fail; |
20054ef0 | 2314 | } |
eaa728ee FB |
2315 | rpl = selector & 3; |
2316 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
2317 | cpl = env->hflags & HF_CPL_MASK; | |
2318 | if (e2 & DESC_S_MASK) { | |
2319 | if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) { | |
2320 | /* conforming */ | |
2321 | } else { | |
20054ef0 | 2322 | if (dpl < cpl || dpl < rpl) { |
eaa728ee | 2323 | goto fail; |
20054ef0 | 2324 | } |
eaa728ee FB |
2325 | } |
2326 | } else { | |
2327 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; | |
20054ef0 | 2328 | switch (type) { |
eaa728ee FB |
2329 | case 1: |
2330 | case 2: | |
2331 | case 3: | |
2332 | case 9: | |
2333 | case 11: | |
2334 | break; | |
2335 | default: | |
2336 | goto fail; | |
2337 | } | |
2338 | if (dpl < cpl || dpl < rpl) { | |
2339 | fail: | |
2340 | CC_SRC = eflags & ~CC_Z; | |
2341 | return 0; | |
2342 | } | |
2343 | } | |
2344 | limit = get_seg_limit(e1, e2); | |
2345 | CC_SRC = eflags | CC_Z; | |
2346 | return limit; | |
2347 | } | |
2348 | ||
2999a0b2 | 2349 | target_ulong helper_lar(CPUX86State *env, target_ulong selector1) |
eaa728ee FB |
2350 | { |
2351 | uint32_t e1, e2, eflags, selector; | |
2352 | int rpl, dpl, cpl, type; | |
2353 | ||
2354 | selector = selector1 & 0xffff; | |
f0967a1a | 2355 | eflags = cpu_cc_compute_all(env, CC_OP); |
20054ef0 | 2356 | if ((selector & 0xfffc) == 0) { |
eaa728ee | 2357 | goto fail; |
20054ef0 | 2358 | } |
2999a0b2 | 2359 | if (load_segment(env, &e1, &e2, selector) != 0) { |
eaa728ee | 2360 | goto fail; |
20054ef0 | 2361 | } |
eaa728ee FB |
2362 | rpl = selector & 3; |
2363 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
2364 | cpl = env->hflags & HF_CPL_MASK; | |
2365 | if (e2 & DESC_S_MASK) { | |
2366 | if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) { | |
2367 | /* conforming */ | |
2368 | } else { | |
20054ef0 | 2369 | if (dpl < cpl || dpl < rpl) { |
eaa728ee | 2370 | goto fail; |
20054ef0 | 2371 | } |
eaa728ee FB |
2372 | } |
2373 | } else { | |
2374 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; | |
20054ef0 | 2375 | switch (type) { |
eaa728ee FB |
2376 | case 1: |
2377 | case 2: | |
2378 | case 3: | |
2379 | case 4: | |
2380 | case 5: | |
2381 | case 9: | |
2382 | case 11: | |
2383 | case 12: | |
2384 | break; | |
2385 | default: | |
2386 | goto fail; | |
2387 | } | |
2388 | if (dpl < cpl || dpl < rpl) { | |
2389 | fail: | |
2390 | CC_SRC = eflags & ~CC_Z; | |
2391 | return 0; | |
2392 | } | |
2393 | } | |
2394 | CC_SRC = eflags | CC_Z; | |
2395 | return e2 & 0x00f0ff00; | |
2396 | } | |
2397 | ||
2999a0b2 | 2398 | void helper_verr(CPUX86State *env, target_ulong selector1) |
eaa728ee FB |
2399 | { |
2400 | uint32_t e1, e2, eflags, selector; | |
2401 | int rpl, dpl, cpl; | |
2402 | ||
2403 | selector = selector1 & 0xffff; | |
f0967a1a | 2404 | eflags = cpu_cc_compute_all(env, CC_OP); |
20054ef0 | 2405 | if ((selector & 0xfffc) == 0) { |
eaa728ee | 2406 | goto fail; |
20054ef0 | 2407 | } |
2999a0b2 | 2408 | if (load_segment(env, &e1, &e2, selector) != 0) { |
eaa728ee | 2409 | goto fail; |
20054ef0 BS |
2410 | } |
2411 | if (!(e2 & DESC_S_MASK)) { | |
eaa728ee | 2412 | goto fail; |
20054ef0 | 2413 | } |
eaa728ee FB |
2414 | rpl = selector & 3; |
2415 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
2416 | cpl = env->hflags & HF_CPL_MASK; | |
2417 | if (e2 & DESC_CS_MASK) { | |
20054ef0 | 2418 | if (!(e2 & DESC_R_MASK)) { |
eaa728ee | 2419 | goto fail; |
20054ef0 | 2420 | } |
eaa728ee | 2421 | if (!(e2 & DESC_C_MASK)) { |
20054ef0 | 2422 | if (dpl < cpl || dpl < rpl) { |
eaa728ee | 2423 | goto fail; |
20054ef0 | 2424 | } |
eaa728ee FB |
2425 | } |
2426 | } else { | |
2427 | if (dpl < cpl || dpl < rpl) { | |
2428 | fail: | |
2429 | CC_SRC = eflags & ~CC_Z; | |
2430 | return; | |
2431 | } | |
2432 | } | |
2433 | CC_SRC = eflags | CC_Z; | |
2434 | } | |
2435 | ||
2999a0b2 | 2436 | void helper_verw(CPUX86State *env, target_ulong selector1) |
eaa728ee FB |
2437 | { |
2438 | uint32_t e1, e2, eflags, selector; | |
2439 | int rpl, dpl, cpl; | |
2440 | ||
2441 | selector = selector1 & 0xffff; | |
f0967a1a | 2442 | eflags = cpu_cc_compute_all(env, CC_OP); |
20054ef0 | 2443 | if ((selector & 0xfffc) == 0) { |
eaa728ee | 2444 | goto fail; |
20054ef0 | 2445 | } |
2999a0b2 | 2446 | if (load_segment(env, &e1, &e2, selector) != 0) { |
eaa728ee | 2447 | goto fail; |
20054ef0 BS |
2448 | } |
2449 | if (!(e2 & DESC_S_MASK)) { | |
eaa728ee | 2450 | goto fail; |
20054ef0 | 2451 | } |
eaa728ee FB |
2452 | rpl = selector & 3; |
2453 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
2454 | cpl = env->hflags & HF_CPL_MASK; | |
2455 | if (e2 & DESC_CS_MASK) { | |
2456 | goto fail; | |
2457 | } else { | |
20054ef0 | 2458 | if (dpl < cpl || dpl < rpl) { |
eaa728ee | 2459 | goto fail; |
20054ef0 | 2460 | } |
eaa728ee FB |
2461 | if (!(e2 & DESC_W_MASK)) { |
2462 | fail: | |
2463 | CC_SRC = eflags & ~CC_Z; | |
2464 | return; | |
2465 | } | |
2466 | } | |
2467 | CC_SRC = eflags | CC_Z; | |
2468 | } | |
2469 | ||
f299f437 | 2470 | #if defined(CONFIG_USER_ONLY) |
2999a0b2 | 2471 | void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector) |
eaa728ee | 2472 | { |
f299f437 BS |
2473 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
2474 | selector &= 0xffff; | |
2475 | cpu_x86_load_seg_cache(env, seg_reg, selector, | |
2476 | (selector << 4), 0xffff, 0); | |
2477 | } else { | |
2999a0b2 | 2478 | helper_load_seg(env, seg_reg, selector); |
13822781 | 2479 | } |
eaa728ee | 2480 | } |
eaa728ee | 2481 | #endif |