[mirror_qemu.git] / target-i386 / smm_helper.c

/*
 *  x86 SMM helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "exec/helper-proto.h"

/* SMM support */

#if defined(CONFIG_USER_ONLY)

void do_smm_enter(X86CPU *cpu)
{
}

void helper_rsm(CPUX86State *env)
{
}

#else

#ifdef TARGET_X86_64
#define SMM_REVISION_ID 0x00020064
#else
#define SMM_REVISION_ID 0x00020000
#endif

void do_smm_enter(X86CPU *cpu)
{
    CPUX86State *env = &cpu->env;
    CPUState *cs = CPU(cpu);
    target_ulong sm_state;
    SegmentCache *dt;
    int i, offset;

    qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
    log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);

    env->hflags |= HF_SMM_MASK;
    cpu_smm_update(env);

    sm_state = env->smbase + 0x8000;

#ifdef TARGET_X86_64
    for (i = 0; i < 6; i++) {
        dt = &env->segs[i];
        offset = 0x7e00 + i * 16;
        x86_stw_phys(cs, sm_state + offset, dt->selector);
        x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
        x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
        x86_stq_phys(cs, sm_state + offset + 8, dt->base);
    }

    x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
    x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);

    x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
    x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
    x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
    x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);

    x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
    x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);

    x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
    x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
    x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
    x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);

    x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);

    x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
    x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
    x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
    x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
    x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
    x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
    x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
    x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
    for (i = 8; i < 16; i++) {
        x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
    }
    x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
    x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
    x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
    x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);

    x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
    x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
    x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);

    x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
    x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
#else
    x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
    x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
    x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
    x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
    x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
    x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
    x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
    x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
    x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
    x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
    x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
    x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
    x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
    x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);

    x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
    x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
    x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
    x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);

    x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
    x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
    x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
    x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);

    x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
    x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);

    x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
    x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);

    for (i = 0; i < 6; i++) {
        dt = &env->segs[i];
        if (i < 3) {
            offset = 0x7f84 + i * 12;
        } else {
            offset = 0x7f2c + (i - 3) * 12;
        }
        x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
        x86_stl_phys(cs, sm_state + offset + 8, dt->base);
        x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
        x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
    }
    x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);

    x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
    x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
#endif
    /* init SMM cpu state */

#ifdef TARGET_X86_64
    cpu_load_efer(env, 0);
#endif
    cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
                              DF_MASK));
    env->eip = 0x00008000;
    cpu_x86_update_cr0(env,
                       env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
                                      CR0_PG_MASK));
    cpu_x86_update_cr4(env, 0);
    env->dr[7] = 0x00000400;

    cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
                           0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_A_MASK);
}

void helper_rsm(CPUX86State *env)
{
    X86CPU *cpu = x86_env_get_cpu(env);
    CPUState *cs = CPU(cpu);
    target_ulong sm_state;
    int i, offset;
    uint32_t val;

    sm_state = env->smbase + 0x8000;
#ifdef TARGET_X86_64
    cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));

    env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
    env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);

    env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
    env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
    env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
    env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;

    env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
    env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);

    env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
    env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
    env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
    env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;

    env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
    env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
    env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
    env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
    env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
    env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
    env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
    env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
    for (i = 8; i < 16; i++) {
        env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
    }
    env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
    cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
    env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
    env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);

    cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
    cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
    cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));

    for (i = 0; i < 6; i++) {
        offset = 0x7e00 + i * 16;
        cpu_x86_load_seg_cache(env, i,
                               x86_lduw_phys(cs, sm_state + offset),
                               x86_ldq_phys(cs, sm_state + offset + 8),
                               x86_ldl_phys(cs, sm_state + offset + 4),
                               (x86_lduw_phys(cs, sm_state + offset + 2) &
                                0xf0ff) << 8);
    }

    val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
    if (val & 0x20000) {
        env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00) & ~0x7fff;
    }
#else
    cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
    cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
    cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
    env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
    env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
    env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
    env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
    env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
    env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
    env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
    env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
    env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
    env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
    env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);

    env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
    env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
    env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
    env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;

    env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
    env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
    env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
    env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;

    env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
    env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);

    env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
    env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);

    for (i = 0; i < 6; i++) {
        if (i < 3) {
            offset = 0x7f84 + i * 12;
        } else {
            offset = 0x7f2c + (i - 3) * 12;
        }
        cpu_x86_load_seg_cache(env, i,
                               x86_ldl_phys(cs,
                                        sm_state + 0x7fa8 + i * 4) & 0xffff,
                               x86_ldl_phys(cs, sm_state + offset + 8),
                               x86_ldl_phys(cs, sm_state + offset + 4),
                               (x86_ldl_phys(cs,
                                         sm_state + offset) & 0xf0ff) << 8);
    }
    cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));

    val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
    if (val & 0x20000) {
        env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8) & ~0x7fff;
    }
#endif
    env->hflags &= ~HF_SMM_MASK;
    cpu_smm_update(env);

    qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
    log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
}

#endif /* !CONFIG_USER_ONLY */
Commit	Line	Data
ab109e59 BS	1	/*
	2	* x86 SMM helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "cpu.h"
2ef6175a	21	#include "exec/helper-proto.h"
ab109e59 BS	22
	23	/* SMM support */
	24
	25	#if defined(CONFIG_USER_ONLY)
	26
518e9d7d	27	void do_smm_enter(X86CPU *cpu)
ab109e59 BS	28	{
	29	}
	30
608badfc	31	void helper_rsm(CPUX86State *env)
ab109e59 BS	32	{
	33	}
	34
	35	#else
	36
	37	#ifdef TARGET_X86_64
	38	#define SMM_REVISION_ID 0x00020064
	39	#else
	40	#define SMM_REVISION_ID 0x00020000
	41	#endif
	42
518e9d7d	43	void do_smm_enter(X86CPU *cpu)
ab109e59	44	{
518e9d7d	45	CPUX86State *env = &cpu->env;
f606604f	46	CPUState *cs = CPU(cpu);
ab109e59 BS	47	target_ulong sm_state;
	48	SegmentCache *dt;
	49	int i, offset;
ab109e59 BS	50
ab109e59 BS	51	qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
a0762859	52	log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
ab109e59 BS	53
	54	env->hflags \|= HF_SMM_MASK;
	55	cpu_smm_update(env);
	56
	57	sm_state = env->smbase + 0x8000;
	58
	59	#ifdef TARGET_X86_64
	60	for (i = 0; i < 6; i++) {
	61	dt = &env->segs[i];
	62	offset = 0x7e00 + i * 16;
b216aa6c PB	63	x86_stw_phys(cs, sm_state + offset, dt->selector);
	64	x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
	65	x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
	66	x86_stq_phys(cs, sm_state + offset + 8, dt->base);
ab109e59 BS	67	}
ab109e59 BS	68
b216aa6c PB	69	x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
b216aa6c PB	70	x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);
ab109e59	71
b216aa6c PB	72	x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
	73	x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
	74	x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
	75	x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
ab109e59	76
b216aa6c PB	77	x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
b216aa6c PB	78	x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);
ab109e59	79
b216aa6c PB	80	x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
	81	x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
	82	x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
	83	x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
ab109e59	84
b216aa6c	85	x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);
ab109e59	86
b216aa6c PB	87	x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
	88	x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
	89	x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
	90	x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
	91	x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
	92	x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
	93	x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
	94	x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
ab109e59	95	for (i = 8; i < 16; i++) {
b216aa6c	96	x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
ab109e59	97	}
b216aa6c PB	98	x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
	99	x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
	100	x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
	101	x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);
ab109e59	102
b216aa6c PB	103	x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
	104	x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
	105	x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);
ab109e59	106
b216aa6c PB	107	x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
b216aa6c PB	108	x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
ab109e59	109	#else
b216aa6c PB	110	x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
	111	x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
	112	x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
	113	x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
	114	x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
	115	x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
	116	x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
	117	x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
	118	x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
	119	x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
	120	x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
	121	x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
	122	x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
	123	x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);
	124
	125	x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
	126	x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
	127	x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
	128	x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
	129
	130	x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
	131	x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
	132	x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
	133	x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
	134
	135	x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
	136	x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);
	137
	138	x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
	139	x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);
ab109e59 BS	140
	141	for (i = 0; i < 6; i++) {
	142	dt = &env->segs[i];
	143	if (i < 3) {
	144	offset = 0x7f84 + i * 12;
	145	} else {
	146	offset = 0x7f2c + (i - 3) * 12;
	147	}
b216aa6c PB	148	x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
	149	x86_stl_phys(cs, sm_state + offset + 8, dt->base);
	150	x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
	151	x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
ab109e59	152	}
b216aa6c	153	x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);
ab109e59	154
b216aa6c PB	155	x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
b216aa6c PB	156	x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
ab109e59 BS	157	#endif
	158	/* init SMM cpu state */
	159
	160	#ifdef TARGET_X86_64
	161	cpu_load_efer(env, 0);
	162	#endif
	163	cpu_load_eflags(env, 0, ~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \|
	164	DF_MASK));
	165	env->eip = 0x00008000;
010e639a KC	166	cpu_x86_update_cr0(env,
	167	env->cr[0] & ~(CR0_PE_MASK \| CR0_EM_MASK \| CR0_TS_MASK \|
	168	CR0_PG_MASK));
	169	cpu_x86_update_cr4(env, 0);
	170	env->dr[7] = 0x00000400;
010e639a	171
ab109e59	172	cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
b98dbc90 PB	173	0xffffffff,
	174	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
	175	DESC_A_MASK);
	176	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
	177	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
	178	DESC_A_MASK);
	179	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
	180	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
	181	DESC_A_MASK);
	182	cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
	183	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
	184	DESC_A_MASK);
	185	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
	186	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
	187	DESC_A_MASK);
	188	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
	189	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
	190	DESC_A_MASK);
ab109e59 BS	191	}
ab109e59 BS	192
608badfc	193	void helper_rsm(CPUX86State *env)
ab109e59	194	{
a0762859	195	X86CPU *cpu = x86_env_get_cpu(env);
19d6ca16	196	CPUState *cs = CPU(cpu);
ab109e59 BS	197	target_ulong sm_state;
	198	int i, offset;
	199	uint32_t val;
	200
	201	sm_state = env->smbase + 0x8000;
	202	#ifdef TARGET_X86_64
b216aa6c PB	203	cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));
	204
	205	env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
	206	env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);
	207
	208	env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
	209	env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
	210	env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
	211	env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;
	212
	213	env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
	214	env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);
	215
	216	env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
	217	env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
	218	env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
	219	env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;
	220
	221	env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
	222	env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
	223	env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
	224	env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
	225	env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
	226	env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
	227	env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
	228	env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
ab109e59	229	for (i = 8; i < 16; i++) {
b216aa6c	230	env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
ab109e59	231	}
b216aa6c PB	232	env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
b216aa6c PB	233	cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
ab109e59	234	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
b216aa6c PB	235	env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
b216aa6c PB	236	env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);
ab109e59	237
b216aa6c PB	238	cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
	239	cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
	240	cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));
ab109e59	241
010e639a KC	242	for (i = 0; i < 6; i++) {
	243	offset = 0x7e00 + i * 16;
	244	cpu_x86_load_seg_cache(env, i,
b216aa6c PB	245	x86_lduw_phys(cs, sm_state + offset),
	246	x86_ldq_phys(cs, sm_state + offset + 8),
	247	x86_ldl_phys(cs, sm_state + offset + 4),
	248	(x86_lduw_phys(cs, sm_state + offset + 2) &
010e639a KC	249	0xf0ff) << 8);
	250	}
	251
b216aa6c	252	val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
ab109e59	253	if (val & 0x20000) {
b216aa6c	254	env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00) & ~0x7fff;
ab109e59 BS	255	}
ab109e59 BS	256	#else
b216aa6c PB	257	cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
	258	cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
	259	cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
ab109e59	260	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
b216aa6c PB	261	env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
	262	env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
	263	env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
	264	env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
	265	env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
	266	env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
	267	env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
	268	env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
	269	env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
	270	env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
	271	env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);
	272
	273	env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
	274	env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
	275	env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
	276	env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;
	277
	278	env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
	279	env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
	280	env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
	281	env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;
	282
	283	env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
	284	env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);
	285
	286	env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
	287	env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);
ab109e59 BS	288
	289	for (i = 0; i < 6; i++) {
	290	if (i < 3) {
	291	offset = 0x7f84 + i * 12;
	292	} else {
	293	offset = 0x7f2c + (i - 3) * 12;
	294	}
	295	cpu_x86_load_seg_cache(env, i,
b216aa6c	296	x86_ldl_phys(cs,
fdfba1a2	297	sm_state + 0x7fa8 + i * 4) & 0xffff,
b216aa6c PB	298	x86_ldl_phys(cs, sm_state + offset + 8),
	299	x86_ldl_phys(cs, sm_state + offset + 4),
	300	(x86_ldl_phys(cs,
fdfba1a2	301	sm_state + offset) & 0xf0ff) << 8);
ab109e59	302	}
b216aa6c	303	cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));
ab109e59	304
b216aa6c	305	val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
ab109e59	306	if (val & 0x20000) {
b216aa6c	307	env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8) & ~0x7fff;
ab109e59 BS	308	}
ab109e59 BS	309	#endif
ab109e59 BS	310	env->hflags &= ~HF_SMM_MASK;
	311	cpu_smm_update(env);
	312
	313	qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
a0762859	314	log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
ab109e59 BS	315	}
	316
	317	#endif /* !CONFIG_USER_ONLY */