[mirror_qemu.git] / target-i386 / smm_helper.c

/*
 *  x86 SMM helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/log.h"

/* SMM support */

#if defined(CONFIG_USER_ONLY)

void do_smm_enter(X86CPU *cpu)
{
}

void helper_rsm(CPUX86State *env)
{
}

#else

#ifdef TARGET_X86_64
#define SMM_REVISION_ID 0x00020064
#else
#define SMM_REVISION_ID 0x00020000
#endif

void cpu_smm_update(X86CPU *cpu)
{
    CPUX86State *env = &cpu->env;
    bool smm_enabled = (env->hflags & HF_SMM_MASK);

    if (cpu->smram) {
        memory_region_set_enabled(cpu->smram, smm_enabled);
    }
}

void do_smm_enter(X86CPU *cpu)
{
    CPUX86State *env = &cpu->env;
    CPUState *cs = CPU(cpu);
    target_ulong sm_state;
    SegmentCache *dt;
    int i, offset;

    qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
    log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);

    env->hflags |= HF_SMM_MASK;
    if (env->hflags2 & HF2_NMI_MASK) {
        env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
    } else {
        env->hflags2 |= HF2_NMI_MASK;
    }
    cpu_smm_update(cpu);

    sm_state = env->smbase + 0x8000;

#ifdef TARGET_X86_64
    for (i = 0; i < 6; i++) {
        dt = &env->segs[i];
        offset = 0x7e00 + i * 16;
        x86_stw_phys(cs, sm_state + offset, dt->selector);
        x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
        x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
        x86_stq_phys(cs, sm_state + offset + 8, dt->base);
    }

    x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
    x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);

    x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
    x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
    x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
    x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);

    x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
    x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);

    x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
    x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
    x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
    x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);

    /* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS
       is saved at offset 7ED0.  Vol 3, 34.4.1.1, Table 32-2, has
       7EA0-7ED7 as "reserved".  What's this, and what's really
       supposed to happen?  */
    x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);

    x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
    x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
    x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
    x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
    x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
    x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
    x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
    x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
    for (i = 8; i < 16; i++) {
        x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
    }
    x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
    x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
    x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
    x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);

    x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
    x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
    x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);

    x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
    x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
#else
    x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
    x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
    x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
    x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
    x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
    x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
    x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
    x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
    x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
    x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
    x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
    x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
    x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
    x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);

    x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
    x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
    x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
    x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);

    x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
    x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
    x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
    x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);

    x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
    x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);

    x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
    x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);

    for (i = 0; i < 6; i++) {
        dt = &env->segs[i];
        if (i < 3) {
            offset = 0x7f84 + i * 12;
        } else {
            offset = 0x7f2c + (i - 3) * 12;
        }
        x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
        x86_stl_phys(cs, sm_state + offset + 8, dt->base);
        x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
        x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
    }
    x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);

    x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
    x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
#endif
    /* init SMM cpu state */

#ifdef TARGET_X86_64
    cpu_load_efer(env, 0);
#endif
    cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
                              DF_MASK));
    env->eip = 0x00008000;
    cpu_x86_update_cr0(env,
                       env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
                                      CR0_PG_MASK));
    cpu_x86_update_cr4(env, 0);
    env->dr[7] = 0x00000400;

    cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
                           0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_G_MASK | DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_G_MASK | DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_G_MASK | DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_G_MASK | DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_G_MASK | DESC_A_MASK);
    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                           DESC_G_MASK | DESC_A_MASK);
}

void helper_rsm(CPUX86State *env)
{
    X86CPU *cpu = x86_env_get_cpu(env);
    CPUState *cs = CPU(cpu);
    target_ulong sm_state;
    int i, offset;
    uint32_t val;

    sm_state = env->smbase + 0x8000;
#ifdef TARGET_X86_64
    cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));

    env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
    env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);

    env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
    env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
    env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
    env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;

    env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
    env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);

    env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
    env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
    env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
    env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;

    env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
    env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
    env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
    env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
    env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
    env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
    env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
    env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
    for (i = 8; i < 16; i++) {
        env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
    }
    env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
    cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
    env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
    env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);

    cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
    cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
    cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));

    for (i = 0; i < 6; i++) {
        offset = 0x7e00 + i * 16;
        cpu_x86_load_seg_cache(env, i,
                               x86_lduw_phys(cs, sm_state + offset),
                               x86_ldq_phys(cs, sm_state + offset + 8),
                               x86_ldl_phys(cs, sm_state + offset + 4),
                               (x86_lduw_phys(cs, sm_state + offset + 2) &
                                0xf0ff) << 8);
    }

    val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
    if (val & 0x20000) {
        env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
    }
#else
    cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
    cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
    cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
    env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
    env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
    env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
    env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
    env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
    env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
    env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
    env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
    env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
    env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
    env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);

    env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
    env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
    env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
    env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;

    env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
    env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
    env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
    env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;

    env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
    env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);

    env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
    env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);

    for (i = 0; i < 6; i++) {
        if (i < 3) {
            offset = 0x7f84 + i * 12;
        } else {
            offset = 0x7f2c + (i - 3) * 12;
        }
        cpu_x86_load_seg_cache(env, i,
                               x86_ldl_phys(cs,
                                        sm_state + 0x7fa8 + i * 4) & 0xffff,
                               x86_ldl_phys(cs, sm_state + offset + 8),
                               x86_ldl_phys(cs, sm_state + offset + 4),
                               (x86_ldl_phys(cs,
                                         sm_state + offset) & 0xf0ff) << 8);
    }
    cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));

    val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
    if (val & 0x20000) {
        env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
    }
#endif
    if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
        env->hflags2 &= ~HF2_NMI_MASK;
    }
    env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
    env->hflags &= ~HF_SMM_MASK;
    cpu_smm_update(cpu);

    qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
    log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
}

#endif /* !CONFIG_USER_ONLY */
Commit	Line	Data
ab109e59 BS	1	/*
	2	* x86 SMM helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
b6a0aa05	20	#include "qemu/osdep.h"
ab109e59	21	#include "cpu.h"
2ef6175a	22	#include "exec/helper-proto.h"
508127e2	23	#include "exec/log.h"
ab109e59 BS	24
	25	/* SMM support */
	26
	27	#if defined(CONFIG_USER_ONLY)
	28
518e9d7d	29	void do_smm_enter(X86CPU *cpu)
ab109e59 BS	30	{
	31	}
	32
608badfc	33	void helper_rsm(CPUX86State *env)
ab109e59 BS	34	{
	35	}
	36
	37	#else
	38
	39	#ifdef TARGET_X86_64
	40	#define SMM_REVISION_ID 0x00020064
	41	#else
	42	#define SMM_REVISION_ID 0x00020000
	43	#endif
	44
f809c605 PB	45	void cpu_smm_update(X86CPU *cpu)
	46	{
	47	CPUX86State *env = &cpu->env;
	48	bool smm_enabled = (env->hflags & HF_SMM_MASK);
	49
	50	if (cpu->smram) {
	51	memory_region_set_enabled(cpu->smram, smm_enabled);
	52	}
	53	}
	54
518e9d7d	55	void do_smm_enter(X86CPU *cpu)
ab109e59	56	{
518e9d7d	57	CPUX86State *env = &cpu->env;
f606604f	58	CPUState *cs = CPU(cpu);
ab109e59 BS	59	target_ulong sm_state;
	60	SegmentCache *dt;
	61	int i, offset;
ab109e59 BS	62
ab109e59 BS	63	qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
a0762859	64	log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
ab109e59 BS	65
ab109e59 BS	66	env->hflags \|= HF_SMM_MASK;
9982f74b PB	67	if (env->hflags2 & HF2_NMI_MASK) {
	68	env->hflags2 \|= HF2_SMM_INSIDE_NMI_MASK;
	69	} else {
	70	env->hflags2 \|= HF2_NMI_MASK;
	71	}
f809c605	72	cpu_smm_update(cpu);
ab109e59 BS	73
	74	sm_state = env->smbase + 0x8000;
	75
	76	#ifdef TARGET_X86_64
	77	for (i = 0; i < 6; i++) {
	78	dt = &env->segs[i];
	79	offset = 0x7e00 + i * 16;
b216aa6c PB	80	x86_stw_phys(cs, sm_state + offset, dt->selector);
	81	x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
	82	x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
	83	x86_stq_phys(cs, sm_state + offset + 8, dt->base);
ab109e59 BS	84	}
ab109e59 BS	85
b216aa6c PB	86	x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
b216aa6c PB	87	x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);
ab109e59	88
b216aa6c PB	89	x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
	90	x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
	91	x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
	92	x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
ab109e59	93
b216aa6c PB	94	x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
b216aa6c PB	95	x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);
ab109e59	96
b216aa6c PB	97	x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
	98	x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
	99	x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
	100	x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
ab109e59	101
f4f1110e RH	102	/* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS
	103	is saved at offset 7ED0. Vol 3, 34.4.1.1, Table 32-2, has
	104	7EA0-7ED7 as "reserved". What's this, and what's really
	105	supposed to happen? */
b216aa6c	106	x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);
ab109e59	107
b216aa6c PB	108	x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
	109	x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
	110	x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
	111	x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
	112	x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
	113	x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
	114	x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
	115	x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
ab109e59	116	for (i = 8; i < 16; i++) {
b216aa6c	117	x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
ab109e59	118	}
b216aa6c PB	119	x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
	120	x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
	121	x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
	122	x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);
ab109e59	123
b216aa6c PB	124	x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
	125	x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
	126	x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);
ab109e59	127
b216aa6c PB	128	x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
b216aa6c PB	129	x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
ab109e59	130	#else
b216aa6c PB	131	x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
	132	x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
	133	x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
	134	x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
	135	x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
	136	x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
	137	x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
	138	x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
	139	x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
	140	x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
	141	x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
	142	x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
	143	x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
	144	x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);
	145
	146	x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
	147	x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
	148	x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
	149	x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
	150
	151	x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
	152	x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
	153	x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
	154	x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
	155
	156	x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
	157	x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);
	158
	159	x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
	160	x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);
ab109e59 BS	161
	162	for (i = 0; i < 6; i++) {
	163	dt = &env->segs[i];
	164	if (i < 3) {
	165	offset = 0x7f84 + i * 12;
	166	} else {
	167	offset = 0x7f2c + (i - 3) * 12;
	168	}
b216aa6c PB	169	x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
	170	x86_stl_phys(cs, sm_state + offset + 8, dt->base);
	171	x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
	172	x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
ab109e59	173	}
b216aa6c	174	x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);
ab109e59	175
b216aa6c PB	176	x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
b216aa6c PB	177	x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
ab109e59 BS	178	#endif
	179	/* init SMM cpu state */
	180
	181	#ifdef TARGET_X86_64
	182	cpu_load_efer(env, 0);
	183	#endif
	184	cpu_load_eflags(env, 0, ~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \|
	185	DF_MASK));
	186	env->eip = 0x00008000;
010e639a KC	187	cpu_x86_update_cr0(env,
	188	env->cr[0] & ~(CR0_PE_MASK \| CR0_EM_MASK \| CR0_TS_MASK \|
	189	CR0_PG_MASK));
	190	cpu_x86_update_cr4(env, 0);
	191	env->dr[7] = 0x00000400;
010e639a	192
ab109e59	193	cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
b98dbc90 PB	194	0xffffffff,
b98dbc90 PB	195	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
b4854f13	196	DESC_G_MASK \| DESC_A_MASK);
b98dbc90 PB	197	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
b98dbc90 PB	198	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
b4854f13	199	DESC_G_MASK \| DESC_A_MASK);
b98dbc90 PB	200	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
b98dbc90 PB	201	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
b4854f13	202	DESC_G_MASK \| DESC_A_MASK);
b98dbc90 PB	203	cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
b98dbc90 PB	204	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
b4854f13	205	DESC_G_MASK \| DESC_A_MASK);
b98dbc90 PB	206	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
b98dbc90 PB	207	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
b4854f13	208	DESC_G_MASK \| DESC_A_MASK);
b98dbc90 PB	209	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
b98dbc90 PB	210	DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
b4854f13	211	DESC_G_MASK \| DESC_A_MASK);
ab109e59 BS	212	}
ab109e59 BS	213
608badfc	214	void helper_rsm(CPUX86State *env)
ab109e59	215	{
a0762859	216	X86CPU *cpu = x86_env_get_cpu(env);
19d6ca16	217	CPUState *cs = CPU(cpu);
ab109e59 BS	218	target_ulong sm_state;
	219	int i, offset;
	220	uint32_t val;
	221
	222	sm_state = env->smbase + 0x8000;
	223	#ifdef TARGET_X86_64
b216aa6c PB	224	cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));
	225
	226	env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
	227	env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);
	228
	229	env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
	230	env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
	231	env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
	232	env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;
	233
	234	env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
	235	env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);
	236
	237	env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
	238	env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
	239	env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
	240	env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;
	241
	242	env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
	243	env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
	244	env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
	245	env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
	246	env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
	247	env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
	248	env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
	249	env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
ab109e59	250	for (i = 8; i < 16; i++) {
b216aa6c	251	env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
ab109e59	252	}
b216aa6c PB	253	env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
b216aa6c PB	254	cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
ab109e59	255	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
b216aa6c PB	256	env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
b216aa6c PB	257	env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);
ab109e59	258
b216aa6c PB	259	cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
	260	cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
	261	cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));
ab109e59	262
010e639a KC	263	for (i = 0; i < 6; i++) {
	264	offset = 0x7e00 + i * 16;
	265	cpu_x86_load_seg_cache(env, i,
b216aa6c PB	266	x86_lduw_phys(cs, sm_state + offset),
	267	x86_ldq_phys(cs, sm_state + offset + 8),
	268	x86_ldl_phys(cs, sm_state + offset + 4),
	269	(x86_lduw_phys(cs, sm_state + offset + 2) &
010e639a KC	270	0xf0ff) << 8);
	271	}
	272
b216aa6c	273	val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
ab109e59	274	if (val & 0x20000) {
dd75d4fc	275	env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
ab109e59 BS	276	}
ab109e59 BS	277	#else
b216aa6c PB	278	cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
	279	cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
	280	cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
ab109e59	281	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
b216aa6c PB	282	env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
	283	env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
	284	env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
	285	env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
	286	env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
	287	env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
	288	env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
	289	env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
	290	env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
	291	env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
	292	env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);
	293
	294	env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
	295	env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
	296	env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
	297	env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;
	298
	299	env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
	300	env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
	301	env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
	302	env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;
	303
	304	env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
	305	env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);
	306
	307	env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
	308	env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);
ab109e59 BS	309
	310	for (i = 0; i < 6; i++) {
	311	if (i < 3) {
	312	offset = 0x7f84 + i * 12;
	313	} else {
	314	offset = 0x7f2c + (i - 3) * 12;
	315	}
	316	cpu_x86_load_seg_cache(env, i,
b216aa6c	317	x86_ldl_phys(cs,
fdfba1a2	318	sm_state + 0x7fa8 + i * 4) & 0xffff,
b216aa6c PB	319	x86_ldl_phys(cs, sm_state + offset + 8),
	320	x86_ldl_phys(cs, sm_state + offset + 4),
	321	(x86_ldl_phys(cs,
fdfba1a2	322	sm_state + offset) & 0xf0ff) << 8);
ab109e59	323	}
b216aa6c	324	cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));
ab109e59	325
b216aa6c	326	val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
ab109e59	327	if (val & 0x20000) {
dd75d4fc	328	env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
ab109e59 BS	329	}
ab109e59 BS	330	#endif
9982f74b PB	331	if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
	332	env->hflags2 &= ~HF2_NMI_MASK;
	333	}
	334	env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
ab109e59	335	env->hflags &= ~HF_SMM_MASK;
f809c605	336	cpu_smm_update(cpu);
ab109e59 BS	337
ab109e59 BS	338	qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
a0762859	339	log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
ab109e59 BS	340	}
	341
	342	#endif /* !CONFIG_USER_ONLY */