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2c0262af
FB		 1/*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
27#include <sys/mman.h>
28
29#include "cpu.h"
30#include "exec-all.h"
31#include "disas.h"
32
33/* XXX: move that elsewhere */
34static uint16_t *gen_opc_ptr;
35static uint32_t *gen_opparam_ptr;
36
37#define PREFIX_REPZ 0x01
38#define PREFIX_REPNZ 0x02
39#define PREFIX_LOCK 0x04
40#define PREFIX_DATA 0x08
41#define PREFIX_ADR 0x10
42
43typedef struct DisasContext {
44 /* current insn context */
45 int override; /* -1 if no override */
46 int prefix;
47 int aflag, dflag;
48 uint8_t *pc; /* pc = eip + cs_base */
49 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
50 static state change (stop translation) */
51 /* current block context */
52 uint8_t *cs_base; /* base of CS segment */
53 int pe; /* protected mode */
54 int code32; /* 32 bit code segment */
55 int ss32; /* 32 bit stack segment */
56 int cc_op; /* current CC operation */
57 int addseg; /* non zero if either DS/ES/SS have a non zero base */
58 int f_st; /* currently unused */
59 int vm86; /* vm86 mode */
60 int cpl;
61 int iopl;
62 int tf; /* TF cpu flag */
34865134 63 int singlestep_enabled; /* "hardware" single step enabled */
2c0262af
FB		 64 int jmp_opt; /* use direct block chaining for direct jumps */
65 int mem_index; /* select memory access functions */
66 struct TranslationBlock *tb;
67 int popl_esp_hack; /* for correct popl with esp base handling */
68} DisasContext;
69
70static void gen_eob(DisasContext *s);
71static void gen_jmp(DisasContext *s, unsigned int eip);
72
73/* i386 arith/logic operations */
74enum {
75 OP_ADDL,
76 OP_ORL,
77 OP_ADCL,
78 OP_SBBL,
79 OP_ANDL,
80 OP_SUBL,
81 OP_XORL,
82 OP_CMPL,
83};
84
85/* i386 shift ops */
86enum {
87 OP_ROL,
88 OP_ROR,
89 OP_RCL,
90 OP_RCR,
91 OP_SHL,
92 OP_SHR,
93 OP_SHL1, /* undocumented */
94 OP_SAR = 7,
95};
96
97enum {
98#define DEF(s, n, copy_size) INDEX_op_ ## s,
99#include "opc.h"
100#undef DEF
101 NB_OPS,
102};
103
104#include "gen-op.h"
105
106/* operand size */
107enum {
108 OT_BYTE = 0,
109 OT_WORD,
110 OT_LONG,
111 OT_QUAD,
112};
113
114enum {
115 /* I386 int registers */
116 OR_EAX, /* MUST be even numbered */
117 OR_ECX,
118 OR_EDX,
119 OR_EBX,
120 OR_ESP,
121 OR_EBP,
122 OR_ESI,
123 OR_EDI,
124 OR_TMP0, /* temporary operand register */
125 OR_TMP1,
126 OR_A0, /* temporary register used when doing address evaluation */
127 OR_ZERO, /* fixed zero register */
128 NB_OREGS,
129};
130
131typedef void (GenOpFunc)(void);
132typedef void (GenOpFunc1)(long);
133typedef void (GenOpFunc2)(long, long);
134typedef void (GenOpFunc3)(long, long, long);
135
136static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
137 [OT_BYTE] = {
138 gen_op_movb_EAX_T0,
139 gen_op_movb_ECX_T0,
140 gen_op_movb_EDX_T0,
141 gen_op_movb_EBX_T0,
142 gen_op_movh_EAX_T0,
143 gen_op_movh_ECX_T0,
144 gen_op_movh_EDX_T0,
145 gen_op_movh_EBX_T0,
146 },
147 [OT_WORD] = {
148 gen_op_movw_EAX_T0,
149 gen_op_movw_ECX_T0,
150 gen_op_movw_EDX_T0,
151 gen_op_movw_EBX_T0,
152 gen_op_movw_ESP_T0,
153 gen_op_movw_EBP_T0,
154 gen_op_movw_ESI_T0,
155 gen_op_movw_EDI_T0,
156 },
157 [OT_LONG] = {
158 gen_op_movl_EAX_T0,
159 gen_op_movl_ECX_T0,
160 gen_op_movl_EDX_T0,
161 gen_op_movl_EBX_T0,
162 gen_op_movl_ESP_T0,
163 gen_op_movl_EBP_T0,
164 gen_op_movl_ESI_T0,
165 gen_op_movl_EDI_T0,
166 },
167};
168
169static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
170 [OT_BYTE] = {
171 gen_op_movb_EAX_T1,
172 gen_op_movb_ECX_T1,
173 gen_op_movb_EDX_T1,
174 gen_op_movb_EBX_T1,
175 gen_op_movh_EAX_T1,
176 gen_op_movh_ECX_T1,
177 gen_op_movh_EDX_T1,
178 gen_op_movh_EBX_T1,
179 },
180 [OT_WORD] = {
181 gen_op_movw_EAX_T1,
182 gen_op_movw_ECX_T1,
183 gen_op_movw_EDX_T1,
184 gen_op_movw_EBX_T1,
185 gen_op_movw_ESP_T1,
186 gen_op_movw_EBP_T1,
187 gen_op_movw_ESI_T1,
188 gen_op_movw_EDI_T1,
189 },
190 [OT_LONG] = {
191 gen_op_movl_EAX_T1,
192 gen_op_movl_ECX_T1,
193 gen_op_movl_EDX_T1,
194 gen_op_movl_EBX_T1,
195 gen_op_movl_ESP_T1,
196 gen_op_movl_EBP_T1,
197 gen_op_movl_ESI_T1,
198 gen_op_movl_EDI_T1,
199 },
200};
201
202static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
203 [0] = {
204 gen_op_movw_EAX_A0,
205 gen_op_movw_ECX_A0,
206 gen_op_movw_EDX_A0,
207 gen_op_movw_EBX_A0,
208 gen_op_movw_ESP_A0,
209 gen_op_movw_EBP_A0,
210 gen_op_movw_ESI_A0,
211 gen_op_movw_EDI_A0,
212 },
213 [1] = {
214 gen_op_movl_EAX_A0,
215 gen_op_movl_ECX_A0,
216 gen_op_movl_EDX_A0,
217 gen_op_movl_EBX_A0,
218 gen_op_movl_ESP_A0,
219 gen_op_movl_EBP_A0,
220 gen_op_movl_ESI_A0,
221 gen_op_movl_EDI_A0,
222 },
223};
224
225static GenOpFunc *gen_op_mov_TN_reg[3][2][8] =
226{
227 [OT_BYTE] = {
228 {
229 gen_op_movl_T0_EAX,
230 gen_op_movl_T0_ECX,
231 gen_op_movl_T0_EDX,
232 gen_op_movl_T0_EBX,
233 gen_op_movh_T0_EAX,
234 gen_op_movh_T0_ECX,
235 gen_op_movh_T0_EDX,
236 gen_op_movh_T0_EBX,
237 },
238 {
239 gen_op_movl_T1_EAX,
240 gen_op_movl_T1_ECX,
241 gen_op_movl_T1_EDX,
242 gen_op_movl_T1_EBX,
243 gen_op_movh_T1_EAX,
244 gen_op_movh_T1_ECX,
245 gen_op_movh_T1_EDX,
246 gen_op_movh_T1_EBX,
247 },
248 },
249 [OT_WORD] = {
250 {
251 gen_op_movl_T0_EAX,
252 gen_op_movl_T0_ECX,
253 gen_op_movl_T0_EDX,
254 gen_op_movl_T0_EBX,
255 gen_op_movl_T0_ESP,
256 gen_op_movl_T0_EBP,
257 gen_op_movl_T0_ESI,
258 gen_op_movl_T0_EDI,
259 },
260 {
261 gen_op_movl_T1_EAX,
262 gen_op_movl_T1_ECX,
263 gen_op_movl_T1_EDX,
264 gen_op_movl_T1_EBX,
265 gen_op_movl_T1_ESP,
266 gen_op_movl_T1_EBP,
267 gen_op_movl_T1_ESI,
268 gen_op_movl_T1_EDI,
269 },
270 },
271 [OT_LONG] = {
272 {
273 gen_op_movl_T0_EAX,
274 gen_op_movl_T0_ECX,
275 gen_op_movl_T0_EDX,
276 gen_op_movl_T0_EBX,
277 gen_op_movl_T0_ESP,
278 gen_op_movl_T0_EBP,
279 gen_op_movl_T0_ESI,
280 gen_op_movl_T0_EDI,
281 },
282 {
283 gen_op_movl_T1_EAX,
284 gen_op_movl_T1_ECX,
285 gen_op_movl_T1_EDX,
286 gen_op_movl_T1_EBX,
287 gen_op_movl_T1_ESP,
288 gen_op_movl_T1_EBP,
289 gen_op_movl_T1_ESI,
290 gen_op_movl_T1_EDI,
291 },
292 },
293};
294
295static GenOpFunc *gen_op_movl_A0_reg[8] = {
296 gen_op_movl_A0_EAX,
297 gen_op_movl_A0_ECX,
298 gen_op_movl_A0_EDX,
299 gen_op_movl_A0_EBX,
300 gen_op_movl_A0_ESP,
301 gen_op_movl_A0_EBP,
302 gen_op_movl_A0_ESI,
303 gen_op_movl_A0_EDI,
304};
305
306static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
307 [0] = {
308 gen_op_addl_A0_EAX,
309 gen_op_addl_A0_ECX,
310 gen_op_addl_A0_EDX,
311 gen_op_addl_A0_EBX,
312 gen_op_addl_A0_ESP,
313 gen_op_addl_A0_EBP,
314 gen_op_addl_A0_ESI,
315 gen_op_addl_A0_EDI,
316 },
317 [1] = {
318 gen_op_addl_A0_EAX_s1,
319 gen_op_addl_A0_ECX_s1,
320 gen_op_addl_A0_EDX_s1,
321 gen_op_addl_A0_EBX_s1,
322 gen_op_addl_A0_ESP_s1,
323 gen_op_addl_A0_EBP_s1,
324 gen_op_addl_A0_ESI_s1,
325 gen_op_addl_A0_EDI_s1,
326 },
327 [2] = {
328 gen_op_addl_A0_EAX_s2,
329 gen_op_addl_A0_ECX_s2,
330 gen_op_addl_A0_EDX_s2,
331 gen_op_addl_A0_EBX_s2,
332 gen_op_addl_A0_ESP_s2,
333 gen_op_addl_A0_EBP_s2,
334 gen_op_addl_A0_ESI_s2,
335 gen_op_addl_A0_EDI_s2,
336 },
337 [3] = {
338 gen_op_addl_A0_EAX_s3,
339 gen_op_addl_A0_ECX_s3,
340 gen_op_addl_A0_EDX_s3,
341 gen_op_addl_A0_EBX_s3,
342 gen_op_addl_A0_ESP_s3,
343 gen_op_addl_A0_EBP_s3,
344 gen_op_addl_A0_ESI_s3,
345 gen_op_addl_A0_EDI_s3,
346 },
347};
348
349static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
350 [0] = {
351 gen_op_cmovw_EAX_T1_T0,
352 gen_op_cmovw_ECX_T1_T0,
353 gen_op_cmovw_EDX_T1_T0,
354 gen_op_cmovw_EBX_T1_T0,
355 gen_op_cmovw_ESP_T1_T0,
356 gen_op_cmovw_EBP_T1_T0,
357 gen_op_cmovw_ESI_T1_T0,
358 gen_op_cmovw_EDI_T1_T0,
359 },
360 [1] = {
361 gen_op_cmovl_EAX_T1_T0,
362 gen_op_cmovl_ECX_T1_T0,
363 gen_op_cmovl_EDX_T1_T0,
364 gen_op_cmovl_EBX_T1_T0,
365 gen_op_cmovl_ESP_T1_T0,
366 gen_op_cmovl_EBP_T1_T0,
367 gen_op_cmovl_ESI_T1_T0,
368 gen_op_cmovl_EDI_T1_T0,
369 },
370};
371
372static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
373 NULL,
374 gen_op_orl_T0_T1,
375 NULL,
376 NULL,
377 gen_op_andl_T0_T1,
378 NULL,
379 gen_op_xorl_T0_T1,
380 NULL,
381};
382
383static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
384 [OT_BYTE] = {
385 gen_op_adcb_T0_T1_cc,
386 gen_op_sbbb_T0_T1_cc,
387 },
388 [OT_WORD] = {
389 gen_op_adcw_T0_T1_cc,
390 gen_op_sbbw_T0_T1_cc,
391 },
392 [OT_LONG] = {
393 gen_op_adcl_T0_T1_cc,
394 gen_op_sbbl_T0_T1_cc,
395 },
396};
397
398static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[3][2] = {
399 [OT_BYTE] = {
400 gen_op_adcb_mem_T0_T1_cc,
401 gen_op_sbbb_mem_T0_T1_cc,
402 },
403 [OT_WORD] = {
404 gen_op_adcw_mem_T0_T1_cc,
405 gen_op_sbbw_mem_T0_T1_cc,
406 },
407 [OT_LONG] = {
408 gen_op_adcl_mem_T0_T1_cc,
409 gen_op_sbbl_mem_T0_T1_cc,
410 },
411};
412
413static const int cc_op_arithb[8] = {
414 CC_OP_ADDB,
415 CC_OP_LOGICB,
416 CC_OP_ADDB,
417 CC_OP_SUBB,
418 CC_OP_LOGICB,
419 CC_OP_SUBB,
420 CC_OP_LOGICB,
421 CC_OP_SUBB,
422};
423
424static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
425 gen_op_cmpxchgb_T0_T1_EAX_cc,
426 gen_op_cmpxchgw_T0_T1_EAX_cc,
427 gen_op_cmpxchgl_T0_T1_EAX_cc,
428};
429
430static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[3] = {
431 gen_op_cmpxchgb_mem_T0_T1_EAX_cc,
432 gen_op_cmpxchgw_mem_T0_T1_EAX_cc,
433 gen_op_cmpxchgl_mem_T0_T1_EAX_cc,
434};
435
436static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
437 [OT_BYTE] = {
438 gen_op_rolb_T0_T1_cc,
439 gen_op_rorb_T0_T1_cc,
440 gen_op_rclb_T0_T1_cc,
441 gen_op_rcrb_T0_T1_cc,
442 gen_op_shlb_T0_T1_cc,
443 gen_op_shrb_T0_T1_cc,
444 gen_op_shlb_T0_T1_cc,
445 gen_op_sarb_T0_T1_cc,
446 },
447 [OT_WORD] = {
448 gen_op_rolw_T0_T1_cc,
449 gen_op_rorw_T0_T1_cc,
450 gen_op_rclw_T0_T1_cc,
451 gen_op_rcrw_T0_T1_cc,
452 gen_op_shlw_T0_T1_cc,
453 gen_op_shrw_T0_T1_cc,
454 gen_op_shlw_T0_T1_cc,
455 gen_op_sarw_T0_T1_cc,
456 },
457 [OT_LONG] = {
458 gen_op_roll_T0_T1_cc,
459 gen_op_rorl_T0_T1_cc,
460 gen_op_rcll_T0_T1_cc,
461 gen_op_rcrl_T0_T1_cc,
462 gen_op_shll_T0_T1_cc,
463 gen_op_shrl_T0_T1_cc,
464 gen_op_shll_T0_T1_cc,
465 gen_op_sarl_T0_T1_cc,
466 },
467};
468
469static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3][8] = {
470 [OT_BYTE] = {
471 gen_op_rolb_mem_T0_T1_cc,
472 gen_op_rorb_mem_T0_T1_cc,
473 gen_op_rclb_mem_T0_T1_cc,
474 gen_op_rcrb_mem_T0_T1_cc,
475 gen_op_shlb_mem_T0_T1_cc,
476 gen_op_shrb_mem_T0_T1_cc,
477 gen_op_shlb_mem_T0_T1_cc,
478 gen_op_sarb_mem_T0_T1_cc,
479 },
480 [OT_WORD] = {
481 gen_op_rolw_mem_T0_T1_cc,
482 gen_op_rorw_mem_T0_T1_cc,
483 gen_op_rclw_mem_T0_T1_cc,
484 gen_op_rcrw_mem_T0_T1_cc,
485 gen_op_shlw_mem_T0_T1_cc,
486 gen_op_shrw_mem_T0_T1_cc,
487 gen_op_shlw_mem_T0_T1_cc,
488 gen_op_sarw_mem_T0_T1_cc,
489 },
490 [OT_LONG] = {
491 gen_op_roll_mem_T0_T1_cc,
492 gen_op_rorl_mem_T0_T1_cc,
493 gen_op_rcll_mem_T0_T1_cc,
494 gen_op_rcrl_mem_T0_T1_cc,
495 gen_op_shll_mem_T0_T1_cc,
496 gen_op_shrl_mem_T0_T1_cc,
497 gen_op_shll_mem_T0_T1_cc,
498 gen_op_sarl_mem_T0_T1_cc,
499 },
500};
501
502static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {
503 [0] = {
504 gen_op_shldw_T0_T1_im_cc,
505 gen_op_shrdw_T0_T1_im_cc,
506 },
507 [1] = {
508 gen_op_shldl_T0_T1_im_cc,
509 gen_op_shrdl_T0_T1_im_cc,
510 },
511};
512
513static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[2][2] = {
514 [0] = {
515 gen_op_shldw_T0_T1_ECX_cc,
516 gen_op_shrdw_T0_T1_ECX_cc,
517 },
518 [1] = {
519 gen_op_shldl_T0_T1_ECX_cc,
520 gen_op_shrdl_T0_T1_ECX_cc,
521 },
522};
523
524static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[2][2] = {
525 [0] = {
526 gen_op_shldw_mem_T0_T1_im_cc,
527 gen_op_shrdw_mem_T0_T1_im_cc,
528 },
529 [1] = {
530 gen_op_shldl_mem_T0_T1_im_cc,
531 gen_op_shrdl_mem_T0_T1_im_cc,
532 },
533};
534
535static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[2][2] = {
536 [0] = {
537 gen_op_shldw_mem_T0_T1_ECX_cc,
538 gen_op_shrdw_mem_T0_T1_ECX_cc,
539 },
540 [1] = {
541 gen_op_shldl_mem_T0_T1_ECX_cc,
542 gen_op_shrdl_mem_T0_T1_ECX_cc,
543 },
544};
545
546static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
547 [0] = {
548 gen_op_btw_T0_T1_cc,
549 gen_op_btsw_T0_T1_cc,
550 gen_op_btrw_T0_T1_cc,
551 gen_op_btcw_T0_T1_cc,
552 },
553 [1] = {
554 gen_op_btl_T0_T1_cc,
555 gen_op_btsl_T0_T1_cc,
556 gen_op_btrl_T0_T1_cc,
557 gen_op_btcl_T0_T1_cc,
558 },
559};
560
561static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
562 [0] = {
563 gen_op_bsfw_T0_cc,
564 gen_op_bsrw_T0_cc,
565 },
566 [1] = {
567 gen_op_bsfl_T0_cc,
568 gen_op_bsrl_T0_cc,
569 },
570};
571
572static GenOpFunc *gen_op_lds_T0_A0[3 * 3] = {
61382a50
FB		 573 gen_op_ldsb_raw_T0_A0,
574 gen_op_ldsw_raw_T0_A0,
2c0262af 575 NULL,
61382a50 576#ifndef CONFIG_USER_ONLY
2c0262af
FB		 577 gen_op_ldsb_kernel_T0_A0,
578 gen_op_ldsw_kernel_T0_A0,
579 NULL,
580
581 gen_op_ldsb_user_T0_A0,
582 gen_op_ldsw_user_T0_A0,
583 NULL,
61382a50 584#endif
2c0262af
FB		 585};
586
587static GenOpFunc *gen_op_ldu_T0_A0[3 * 3] = {
61382a50
FB		 588 gen_op_ldub_raw_T0_A0,
589 gen_op_lduw_raw_T0_A0,
2c0262af
FB		 590 NULL,
591
61382a50 592#ifndef CONFIG_USER_ONLY
2c0262af
FB		 593 gen_op_ldub_kernel_T0_A0,
594 gen_op_lduw_kernel_T0_A0,
595 NULL,
596
597 gen_op_ldub_user_T0_A0,
598 gen_op_lduw_user_T0_A0,
599 NULL,
61382a50 600#endif
2c0262af
FB		 601};
602
603/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
604static GenOpFunc *gen_op_ld_T0_A0[3 * 3] = {
61382a50
FB		 605 gen_op_ldub_raw_T0_A0,
606 gen_op_lduw_raw_T0_A0,
607 gen_op_ldl_raw_T0_A0,
2c0262af 608
61382a50 609#ifndef CONFIG_USER_ONLY
2c0262af
FB		 610 gen_op_ldub_kernel_T0_A0,
611 gen_op_lduw_kernel_T0_A0,
612 gen_op_ldl_kernel_T0_A0,
613
614 gen_op_ldub_user_T0_A0,
615 gen_op_lduw_user_T0_A0,
616 gen_op_ldl_user_T0_A0,
61382a50 617#endif
2c0262af
FB		 618};
619
620static GenOpFunc *gen_op_ld_T1_A0[3 * 3] = {
61382a50
FB		 621 gen_op_ldub_raw_T1_A0,
622 gen_op_lduw_raw_T1_A0,
623 gen_op_ldl_raw_T1_A0,
2c0262af 624
61382a50 625#ifndef CONFIG_USER_ONLY
2c0262af
FB		 626 gen_op_ldub_kernel_T1_A0,
627 gen_op_lduw_kernel_T1_A0,
628 gen_op_ldl_kernel_T1_A0,
629
630 gen_op_ldub_user_T1_A0,
631 gen_op_lduw_user_T1_A0,
632 gen_op_ldl_user_T1_A0,
61382a50 633#endif
2c0262af
FB		 634};
635
636static GenOpFunc *gen_op_st_T0_A0[3 * 3] = {
61382a50
FB		 637 gen_op_stb_raw_T0_A0,
638 gen_op_stw_raw_T0_A0,
639 gen_op_stl_raw_T0_A0,
2c0262af 640
61382a50 641#ifndef CONFIG_USER_ONLY
2c0262af
FB		 642 gen_op_stb_kernel_T0_A0,
643 gen_op_stw_kernel_T0_A0,
644 gen_op_stl_kernel_T0_A0,
645
646 gen_op_stb_user_T0_A0,
647 gen_op_stw_user_T0_A0,
648 gen_op_stl_user_T0_A0,
61382a50 649#endif
2c0262af
FB		 650};
651
652static inline void gen_string_movl_A0_ESI(DisasContext *s)
653{
654 int override;
655
656 override = s->override;
657 if (s->aflag) {
658 /* 32 bit address */
659 if (s->addseg && override < 0)
660 override = R_DS;
661 if (override >= 0) {
662 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
663 gen_op_addl_A0_reg_sN[0][R_ESI]();
664 } else {
665 gen_op_movl_A0_reg[R_ESI]();
666 }
667 } else {
668 /* 16 address, always override */
669 if (override < 0)
670 override = R_DS;
671 gen_op_movl_A0_reg[R_ESI]();
672 gen_op_andl_A0_ffff();
673 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
674 }
675}
676
677static inline void gen_string_movl_A0_EDI(DisasContext *s)
678{
679 if (s->aflag) {
680 if (s->addseg) {
681 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
682 gen_op_addl_A0_reg_sN[0][R_EDI]();
683 } else {
684 gen_op_movl_A0_reg[R_EDI]();
685 }
686 } else {
687 gen_op_movl_A0_reg[R_EDI]();
688 gen_op_andl_A0_ffff();
689 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
690 }
691}
692
693static GenOpFunc *gen_op_movl_T0_Dshift[3] = {
694 gen_op_movl_T0_Dshiftb,
695 gen_op_movl_T0_Dshiftw,
696 gen_op_movl_T0_Dshiftl,
697};
698
699static GenOpFunc2 *gen_op_jz_ecx[2] = {
700 gen_op_jz_ecxw,
701 gen_op_jz_ecxl,
702};
703
704static GenOpFunc1 *gen_op_jz_ecx_im[2] = {
705 gen_op_jz_ecxw_im,
706 gen_op_jz_ecxl_im,
707};
708
709static GenOpFunc *gen_op_dec_ECX[2] = {
710 gen_op_decw_ECX,
711 gen_op_decl_ECX,
712};
713
714static GenOpFunc1 *gen_op_string_jnz_sub[2][3] = {
715 {
716 gen_op_string_jnz_subb,
717 gen_op_string_jnz_subw,
718 gen_op_string_jnz_subl,
719 },
720 {
721 gen_op_string_jz_subb,
722 gen_op_string_jz_subw,
723 gen_op_string_jz_subl,
724 },
725};
726
727static GenOpFunc1 *gen_op_string_jnz_sub_im[2][3] = {
728 {
729 gen_op_string_jnz_subb_im,
730 gen_op_string_jnz_subw_im,
731 gen_op_string_jnz_subl_im,
732 },
733 {
734 gen_op_string_jz_subb_im,
735 gen_op_string_jz_subw_im,
736 gen_op_string_jz_subl_im,
737 },
738};
739
740static GenOpFunc *gen_op_in_DX_T0[3] = {
741 gen_op_inb_DX_T0,
742 gen_op_inw_DX_T0,
743 gen_op_inl_DX_T0,
744};
745
746static GenOpFunc *gen_op_out_DX_T0[3] = {
747 gen_op_outb_DX_T0,
748 gen_op_outw_DX_T0,
749 gen_op_outl_DX_T0,
750};
751
f115e911
FB		 752static GenOpFunc *gen_op_in[3] = {
753 gen_op_inb_T0_T1,
754 gen_op_inw_T0_T1,
755 gen_op_inl_T0_T1,
756};
757
758static GenOpFunc *gen_op_out[3] = {
759 gen_op_outb_T0_T1,
760 gen_op_outw_T0_T1,
761 gen_op_outl_T0_T1,
762};
763
764static GenOpFunc *gen_check_io_T0[3] = {
765 gen_op_check_iob_T0,
766 gen_op_check_iow_T0,
767 gen_op_check_iol_T0,
768};
769
770static GenOpFunc *gen_check_io_DX[3] = {
771 gen_op_check_iob_DX,
772 gen_op_check_iow_DX,
773 gen_op_check_iol_DX,
774};
775
776static void gen_check_io(DisasContext *s, int ot, int use_dx, int cur_eip)
777{
778 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
779 if (s->cc_op != CC_OP_DYNAMIC)
780 gen_op_set_cc_op(s->cc_op);
781 gen_op_jmp_im(cur_eip);
782 if (use_dx)
783 gen_check_io_DX[ot]();
784 else
785 gen_check_io_T0[ot]();
786 }
787}
788
2c0262af
FB		 789static inline void gen_movs(DisasContext *s, int ot)
790{
791 gen_string_movl_A0_ESI(s);
792 gen_op_ld_T0_A0[ot + s->mem_index]();
793 gen_string_movl_A0_EDI(s);
794 gen_op_st_T0_A0[ot + s->mem_index]();
795 gen_op_movl_T0_Dshift[ot]();
796 if (s->aflag) {
797 gen_op_addl_ESI_T0();
798 gen_op_addl_EDI_T0();
799 } else {
800 gen_op_addw_ESI_T0();
801 gen_op_addw_EDI_T0();
802 }
803}
804
805static inline void gen_update_cc_op(DisasContext *s)
806{
807 if (s->cc_op != CC_OP_DYNAMIC) {
808 gen_op_set_cc_op(s->cc_op);
809 s->cc_op = CC_OP_DYNAMIC;
810 }
811}
812
813static inline void gen_jz_ecx_string(DisasContext *s, unsigned int next_eip)
814{
815 if (s->jmp_opt) {
816 gen_op_jz_ecx[s->aflag]((long)s->tb, next_eip);
817 } else {
818 /* XXX: does not work with gdbstub "ice" single step - not a
819 serious problem */
820 gen_op_jz_ecx_im[s->aflag](next_eip);
821 }
822}
823
824static inline void gen_stos(DisasContext *s, int ot)
825{
826 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
827 gen_string_movl_A0_EDI(s);
828 gen_op_st_T0_A0[ot + s->mem_index]();
829 gen_op_movl_T0_Dshift[ot]();
830 if (s->aflag) {
831 gen_op_addl_EDI_T0();
832 } else {
833 gen_op_addw_EDI_T0();
834 }
835}
836
837static inline void gen_lods(DisasContext *s, int ot)
838{
839 gen_string_movl_A0_ESI(s);
840 gen_op_ld_T0_A0[ot + s->mem_index]();
841 gen_op_mov_reg_T0[ot][R_EAX]();
842 gen_op_movl_T0_Dshift[ot]();
843 if (s->aflag) {
844 gen_op_addl_ESI_T0();
845 } else {
846 gen_op_addw_ESI_T0();
847 }
848}
849
850static inline void gen_scas(DisasContext *s, int ot)
851{
852 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
853 gen_string_movl_A0_EDI(s);
854 gen_op_ld_T1_A0[ot + s->mem_index]();
855 gen_op_cmpl_T0_T1_cc();
856 gen_op_movl_T0_Dshift[ot]();
857 if (s->aflag) {
858 gen_op_addl_EDI_T0();
859 } else {
860 gen_op_addw_EDI_T0();
861 }
862}
863
864static inline void gen_cmps(DisasContext *s, int ot)
865{
866 gen_string_movl_A0_ESI(s);
867 gen_op_ld_T0_A0[ot + s->mem_index]();
868 gen_string_movl_A0_EDI(s);
869 gen_op_ld_T1_A0[ot + s->mem_index]();
870 gen_op_cmpl_T0_T1_cc();
871 gen_op_movl_T0_Dshift[ot]();
872 if (s->aflag) {
873 gen_op_addl_ESI_T0();
874 gen_op_addl_EDI_T0();
875 } else {
876 gen_op_addw_ESI_T0();
877 gen_op_addw_EDI_T0();
878 }
879}
880
881static inline void gen_ins(DisasContext *s, int ot)
882{
883 gen_op_in_DX_T0[ot]();
884 gen_string_movl_A0_EDI(s);
885 gen_op_st_T0_A0[ot + s->mem_index]();
886 gen_op_movl_T0_Dshift[ot]();
887 if (s->aflag) {
888 gen_op_addl_EDI_T0();
889 } else {
890 gen_op_addw_EDI_T0();
891 }
892}
893
894static inline void gen_outs(DisasContext *s, int ot)
895{
896 gen_string_movl_A0_ESI(s);
897 gen_op_ld_T0_A0[ot + s->mem_index]();
898 gen_op_out_DX_T0[ot]();
899 gen_op_movl_T0_Dshift[ot]();
900 if (s->aflag) {
901 gen_op_addl_ESI_T0();
902 } else {
903 gen_op_addw_ESI_T0();
904 }
905}
906
907/* same method as Valgrind : we generate jumps to current or next
908 instruction */
909#define GEN_REPZ(op) \
910static inline void gen_repz_ ## op(DisasContext *s, int ot, \
911 unsigned int cur_eip, unsigned int next_eip) \
912{ \
913 gen_update_cc_op(s); \
914 gen_jz_ecx_string(s, next_eip); \
915 gen_ ## op(s, ot); \
916 gen_op_dec_ECX[s->aflag](); \
917 /* a loop would cause two single step exceptions if ECX = 1 \
918 before rep string_insn */ \
919 if (!s->jmp_opt) \
920 gen_op_jz_ecx_im[s->aflag](next_eip); \
921 gen_jmp(s, cur_eip); \
922}
923
924#define GEN_REPZ2(op) \
925static inline void gen_repz_ ## op(DisasContext *s, int ot, \
926 unsigned int cur_eip, \
927 unsigned int next_eip, \
928 int nz) \
929{ \
930 gen_update_cc_op(s); \
931 gen_jz_ecx_string(s, next_eip); \
932 gen_ ## op(s, ot); \
933 gen_op_dec_ECX[s->aflag](); \
934 gen_op_set_cc_op(CC_OP_SUBB + ot); \
935 if (!s->jmp_opt) \
936 gen_op_string_jnz_sub_im[nz][ot](next_eip); \
937 else \
938 gen_op_string_jnz_sub[nz][ot]((long)s->tb); \
939 if (!s->jmp_opt) \
940 gen_op_jz_ecx_im[s->aflag](next_eip); \
941 gen_jmp(s, cur_eip); \
942}
943
944GEN_REPZ(movs)
945GEN_REPZ(stos)
946GEN_REPZ(lods)
947GEN_REPZ(ins)
948GEN_REPZ(outs)
949GEN_REPZ2(scas)
950GEN_REPZ2(cmps)
951
2c0262af
FB		 952enum {
953 JCC_O,
954 JCC_B,
955 JCC_Z,
956 JCC_BE,
957 JCC_S,
958 JCC_P,
959 JCC_L,
960 JCC_LE,
961};
962
963static GenOpFunc3 *gen_jcc_sub[3][8] = {
964 [OT_BYTE] = {
965 NULL,
966 gen_op_jb_subb,
967 gen_op_jz_subb,
968 gen_op_jbe_subb,
969 gen_op_js_subb,
970 NULL,
971 gen_op_jl_subb,
972 gen_op_jle_subb,
973 },
974 [OT_WORD] = {
975 NULL,
976 gen_op_jb_subw,
977 gen_op_jz_subw,
978 gen_op_jbe_subw,
979 gen_op_js_subw,
980 NULL,
981 gen_op_jl_subw,
982 gen_op_jle_subw,
983 },
984 [OT_LONG] = {
985 NULL,
986 gen_op_jb_subl,
987 gen_op_jz_subl,
988 gen_op_jbe_subl,
989 gen_op_js_subl,
990 NULL,
991 gen_op_jl_subl,
992 gen_op_jle_subl,
993 },
994};
995static GenOpFunc2 *gen_op_loop[2][4] = {
996 [0] = {
997 gen_op_loopnzw,
998 gen_op_loopzw,
999 gen_op_loopw,
1000 gen_op_jecxzw,
1001 },
1002 [1] = {
1003 gen_op_loopnzl,
1004 gen_op_loopzl,
1005 gen_op_loopl,
1006 gen_op_jecxzl,
1007 },
1008};
1009
1010static GenOpFunc *gen_setcc_slow[8] = {
1011 gen_op_seto_T0_cc,
1012 gen_op_setb_T0_cc,
1013 gen_op_setz_T0_cc,
1014 gen_op_setbe_T0_cc,
1015 gen_op_sets_T0_cc,
1016 gen_op_setp_T0_cc,
1017 gen_op_setl_T0_cc,
1018 gen_op_setle_T0_cc,
1019};
1020
1021static GenOpFunc *gen_setcc_sub[3][8] = {
1022 [OT_BYTE] = {
1023 NULL,
1024 gen_op_setb_T0_subb,
1025 gen_op_setz_T0_subb,
1026 gen_op_setbe_T0_subb,
1027 gen_op_sets_T0_subb,
1028 NULL,
1029 gen_op_setl_T0_subb,
1030 gen_op_setle_T0_subb,
1031 },
1032 [OT_WORD] = {
1033 NULL,
1034 gen_op_setb_T0_subw,
1035 gen_op_setz_T0_subw,
1036 gen_op_setbe_T0_subw,
1037 gen_op_sets_T0_subw,
1038 NULL,
1039 gen_op_setl_T0_subw,
1040 gen_op_setle_T0_subw,
1041 },
1042 [OT_LONG] = {
1043 NULL,
1044 gen_op_setb_T0_subl,
1045 gen_op_setz_T0_subl,
1046 gen_op_setbe_T0_subl,
1047 gen_op_sets_T0_subl,
1048 NULL,
1049 gen_op_setl_T0_subl,
1050 gen_op_setle_T0_subl,
1051 },
1052};
1053
1054static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1055 gen_op_fadd_ST0_FT0,
1056 gen_op_fmul_ST0_FT0,
1057 gen_op_fcom_ST0_FT0,
1058 gen_op_fcom_ST0_FT0,
1059 gen_op_fsub_ST0_FT0,
1060 gen_op_fsubr_ST0_FT0,
1061 gen_op_fdiv_ST0_FT0,
1062 gen_op_fdivr_ST0_FT0,
1063};
1064
1065/* NOTE the exception in "r" op ordering */
1066static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1067 gen_op_fadd_STN_ST0,
1068 gen_op_fmul_STN_ST0,
1069 NULL,
1070 NULL,
1071 gen_op_fsubr_STN_ST0,
1072 gen_op_fsub_STN_ST0,
1073 gen_op_fdivr_STN_ST0,
1074 gen_op_fdiv_STN_ST0,
1075};
1076
1077/* if d == OR_TMP0, it means memory operand (address in A0) */
1078static void gen_op(DisasContext *s1, int op, int ot, int d)
1079{
1080 GenOpFunc *gen_update_cc;
1081
1082 if (d != OR_TMP0) {
1083 gen_op_mov_TN_reg[ot][0][d]();
1084 } else {
1085 gen_op_ld_T0_A0[ot + s1->mem_index]();
1086 }
1087 switch(op) {
1088 case OP_ADCL:
1089 case OP_SBBL:
1090 if (s1->cc_op != CC_OP_DYNAMIC)
1091 gen_op_set_cc_op(s1->cc_op);
1092 if (d != OR_TMP0) {
1093 gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1094 gen_op_mov_reg_T0[ot][d]();
1095 } else {
1096 gen_op_arithc_mem_T0_T1_cc[ot][op - OP_ADCL]();
1097 }
1098 s1->cc_op = CC_OP_DYNAMIC;
1099 goto the_end;
1100 case OP_ADDL:
1101 gen_op_addl_T0_T1();
1102 s1->cc_op = CC_OP_ADDB + ot;
1103 gen_update_cc = gen_op_update2_cc;
1104 break;
1105 case OP_SUBL:
1106 gen_op_subl_T0_T1();
1107 s1->cc_op = CC_OP_SUBB + ot;
1108 gen_update_cc = gen_op_update2_cc;
1109 break;
1110 default:
1111 case OP_ANDL:
1112 case OP_ORL:
1113 case OP_XORL:
1114 gen_op_arith_T0_T1_cc[op]();
1115 s1->cc_op = CC_OP_LOGICB + ot;
1116 gen_update_cc = gen_op_update1_cc;
1117 break;
1118 case OP_CMPL:
1119 gen_op_cmpl_T0_T1_cc();
1120 s1->cc_op = CC_OP_SUBB + ot;
1121 gen_update_cc = NULL;
1122 break;
1123 }
1124 if (op != OP_CMPL) {
1125 if (d != OR_TMP0)
1126 gen_op_mov_reg_T0[ot][d]();
1127 else
1128 gen_op_st_T0_A0[ot + s1->mem_index]();
1129 }
1130 /* the flags update must happen after the memory write (precise
1131 exception support) */
1132 if (gen_update_cc)
1133 gen_update_cc();
1134 the_end: ;
1135}
1136
1137/* if d == OR_TMP0, it means memory operand (address in A0) */
1138static void gen_inc(DisasContext *s1, int ot, int d, int c)
1139{
1140 if (d != OR_TMP0)
1141 gen_op_mov_TN_reg[ot][0][d]();
1142 else
1143 gen_op_ld_T0_A0[ot + s1->mem_index]();
1144 if (s1->cc_op != CC_OP_DYNAMIC)
1145 gen_op_set_cc_op(s1->cc_op);
1146 if (c > 0) {
1147 gen_op_incl_T0();
1148 s1->cc_op = CC_OP_INCB + ot;
1149 } else {
1150 gen_op_decl_T0();
1151 s1->cc_op = CC_OP_DECB + ot;
1152 }
1153 if (d != OR_TMP0)
1154 gen_op_mov_reg_T0[ot][d]();
1155 else
1156 gen_op_st_T0_A0[ot + s1->mem_index]();
1157 gen_op_update_inc_cc();
1158}
1159
1160static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1161{
1162 if (d != OR_TMP0)
1163 gen_op_mov_TN_reg[ot][0][d]();
1164 else
1165 gen_op_ld_T0_A0[ot + s1->mem_index]();
1166 if (s != OR_TMP1)
1167 gen_op_mov_TN_reg[ot][1][s]();
1168 /* for zero counts, flags are not updated, so must do it dynamically */
1169 if (s1->cc_op != CC_OP_DYNAMIC)
1170 gen_op_set_cc_op(s1->cc_op);
1171
1172 if (d != OR_TMP0)
1173 gen_op_shift_T0_T1_cc[ot][op]();
1174 else
1175 gen_op_shift_mem_T0_T1_cc[ot][op]();
1176 if (d != OR_TMP0)
1177 gen_op_mov_reg_T0[ot][d]();
1178 s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1179}
1180
1181static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1182{
1183 /* currently not optimized */
1184 gen_op_movl_T1_im(c);
1185 gen_shift(s1, op, ot, d, OR_TMP1);
1186}
1187
1188static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1189{
1190 int havesib;
1191 int base, disp;
1192 int index;
1193 int scale;
1194 int opreg;
1195 int mod, rm, code, override, must_add_seg;
1196
1197 override = s->override;
1198 must_add_seg = s->addseg;
1199 if (override >= 0)
1200 must_add_seg = 1;
1201 mod = (modrm >> 6) & 3;
1202 rm = modrm & 7;
1203
1204 if (s->aflag) {
1205
1206 havesib = 0;
1207 base = rm;
1208 index = 0;
1209 scale = 0;
1210
1211 if (base == 4) {
1212 havesib = 1;
61382a50 1213 code = ldub_code(s->pc++);
2c0262af
FB		 1214 scale = (code >> 6) & 3;
1215 index = (code >> 3) & 7;
1216 base = code & 7;
1217 }
1218
1219 switch (mod) {
1220 case 0:
1221 if (base == 5) {
1222 base = -1;
61382a50 1223 disp = ldl_code(s->pc);
2c0262af
FB		 1224 s->pc += 4;
1225 } else {
1226 disp = 0;
1227 }
1228 break;
1229 case 1:
61382a50 1230 disp = (int8_t)ldub_code(s->pc++);
2c0262af
FB		 1231 break;
1232 default:
1233 case 2:
61382a50 1234 disp = ldl_code(s->pc);
2c0262af
FB		 1235 s->pc += 4;
1236 break;
1237 }
1238
1239 if (base >= 0) {
1240 /* for correct popl handling with esp */
1241 if (base == 4 && s->popl_esp_hack)
1242 disp += s->popl_esp_hack;
1243 gen_op_movl_A0_reg[base]();
1244 if (disp != 0)
1245 gen_op_addl_A0_im(disp);
1246 } else {
1247 gen_op_movl_A0_im(disp);
1248 }
1249 /* XXX: index == 4 is always invalid */
1250 if (havesib && (index != 4 || scale != 0)) {
1251 gen_op_addl_A0_reg_sN[scale][index]();
1252 }
1253 if (must_add_seg) {
1254 if (override < 0) {
1255 if (base == R_EBP || base == R_ESP)
1256 override = R_SS;
1257 else
1258 override = R_DS;
1259 }
1260 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1261 }
1262 } else {
1263 switch (mod) {
1264 case 0:
1265 if (rm == 6) {
61382a50 1266 disp = lduw_code(s->pc);
2c0262af
FB		 1267 s->pc += 2;
1268 gen_op_movl_A0_im(disp);
1269 rm = 0; /* avoid SS override */
1270 goto no_rm;
1271 } else {
1272 disp = 0;
1273 }
1274 break;
1275 case 1:
61382a50 1276 disp = (int8_t)ldub_code(s->pc++);
2c0262af
FB		 1277 break;
1278 default:
1279 case 2:
61382a50 1280 disp = lduw_code(s->pc);
2c0262af
FB		 1281 s->pc += 2;
1282 break;
1283 }
1284 switch(rm) {
1285 case 0:
1286 gen_op_movl_A0_reg[R_EBX]();
1287 gen_op_addl_A0_reg_sN[0][R_ESI]();
1288 break;
1289 case 1:
1290 gen_op_movl_A0_reg[R_EBX]();
1291 gen_op_addl_A0_reg_sN[0][R_EDI]();
1292 break;
1293 case 2:
1294 gen_op_movl_A0_reg[R_EBP]();
1295 gen_op_addl_A0_reg_sN[0][R_ESI]();
1296 break;
1297 case 3:
1298 gen_op_movl_A0_reg[R_EBP]();
1299 gen_op_addl_A0_reg_sN[0][R_EDI]();
1300 break;
1301 case 4:
1302 gen_op_movl_A0_reg[R_ESI]();
1303 break;
1304 case 5:
1305 gen_op_movl_A0_reg[R_EDI]();
1306 break;
1307 case 6:
1308 gen_op_movl_A0_reg[R_EBP]();
1309 break;
1310 default:
1311 case 7:
1312 gen_op_movl_A0_reg[R_EBX]();
1313 break;
1314 }
1315 if (disp != 0)
1316 gen_op_addl_A0_im(disp);
1317 gen_op_andl_A0_ffff();
1318 no_rm:
1319 if (must_add_seg) {
1320 if (override < 0) {
1321 if (rm == 2 || rm == 3 || rm == 6)
1322 override = R_SS;
1323 else
1324 override = R_DS;
1325 }
1326 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1327 }
1328 }
1329
1330 opreg = OR_A0;
1331 disp = 0;
1332 *reg_ptr = opreg;
1333 *offset_ptr = disp;
1334}
1335
1336/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1337 OR_TMP0 */
1338static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1339{
1340 int mod, rm, opreg, disp;
1341
1342 mod = (modrm >> 6) & 3;
1343 rm = modrm & 7;
1344 if (mod == 3) {
1345 if (is_store) {
1346 if (reg != OR_TMP0)
1347 gen_op_mov_TN_reg[ot][0][reg]();
1348 gen_op_mov_reg_T0[ot][rm]();
1349 } else {
1350 gen_op_mov_TN_reg[ot][0][rm]();
1351 if (reg != OR_TMP0)
1352 gen_op_mov_reg_T0[ot][reg]();
1353 }
1354 } else {
1355 gen_lea_modrm(s, modrm, &opreg, &disp);
1356 if (is_store) {
1357 if (reg != OR_TMP0)
1358 gen_op_mov_TN_reg[ot][0][reg]();
1359 gen_op_st_T0_A0[ot + s->mem_index]();
1360 } else {
1361 gen_op_ld_T0_A0[ot + s->mem_index]();
1362 if (reg != OR_TMP0)
1363 gen_op_mov_reg_T0[ot][reg]();
1364 }
1365 }
1366}
1367
1368static inline uint32_t insn_get(DisasContext *s, int ot)
1369{
1370 uint32_t ret;
1371
1372 switch(ot) {
1373 case OT_BYTE:
61382a50 1374 ret = ldub_code(s->pc);
2c0262af
FB		 1375 s->pc++;
1376 break;
1377 case OT_WORD:
61382a50 1378 ret = lduw_code(s->pc);
2c0262af
FB		 1379 s->pc += 2;
1380 break;
1381 default:
1382 case OT_LONG:
61382a50 1383 ret = ldl_code(s->pc);
2c0262af
FB		 1384 s->pc += 4;
1385 break;
1386 }
1387 return ret;
1388}
1389
1390static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
1391{
1392 TranslationBlock *tb;
1393 int inv, jcc_op;
1394 GenOpFunc3 *func;
1395
1396 inv = b & 1;
1397 jcc_op = (b >> 1) & 7;
1398
1399 if (s->jmp_opt) {
1400 switch(s->cc_op) {
1401 /* we optimize the cmp/jcc case */
1402 case CC_OP_SUBB:
1403 case CC_OP_SUBW:
1404 case CC_OP_SUBL:
1405 func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1406 break;
1407
1408 /* some jumps are easy to compute */
1409 case CC_OP_ADDB:
1410 case CC_OP_ADDW:
1411 case CC_OP_ADDL:
1412 case CC_OP_ADCB:
1413 case CC_OP_ADCW:
1414 case CC_OP_ADCL:
1415 case CC_OP_SBBB:
1416 case CC_OP_SBBW:
1417 case CC_OP_SBBL:
1418 case CC_OP_LOGICB:
1419 case CC_OP_LOGICW:
1420 case CC_OP_LOGICL:
1421 case CC_OP_INCB:
1422 case CC_OP_INCW:
1423 case CC_OP_INCL:
1424 case CC_OP_DECB:
1425 case CC_OP_DECW:
1426 case CC_OP_DECL:
1427 case CC_OP_SHLB:
1428 case CC_OP_SHLW:
1429 case CC_OP_SHLL:
1430 case CC_OP_SARB:
1431 case CC_OP_SARW:
1432 case CC_OP_SARL:
1433 switch(jcc_op) {
1434 case JCC_Z:
1435 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1436 break;
1437 case JCC_S:
1438 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1439 break;
1440 default:
1441 func = NULL;
1442 break;
1443 }
1444 break;
1445 default:
1446 func = NULL;
1447 break;
1448 }
1449
1450 if (s->cc_op != CC_OP_DYNAMIC)
1451 gen_op_set_cc_op(s->cc_op);
1452
1453 if (!func) {
1454 gen_setcc_slow[jcc_op]();
1455 func = gen_op_jcc;
1456 }
1457
1458 tb = s->tb;
1459 if (!inv) {
1460 func((long)tb, val, next_eip);
1461 } else {
1462 func((long)tb, next_eip, val);
1463 }
1464 s->is_jmp = 3;
1465 } else {
1466 if (s->cc_op != CC_OP_DYNAMIC) {
1467 gen_op_set_cc_op(s->cc_op);
1468 s->cc_op = CC_OP_DYNAMIC;
1469 }
1470 gen_setcc_slow[jcc_op]();
1471 if (!inv) {
1472 gen_op_jcc_im(val, next_eip);
1473 } else {
1474 gen_op_jcc_im(next_eip, val);
1475 }
1476 gen_eob(s);
1477 }
1478}
1479
1480static void gen_setcc(DisasContext *s, int b)
1481{
1482 int inv, jcc_op;
1483 GenOpFunc *func;
1484
1485 inv = b & 1;
1486 jcc_op = (b >> 1) & 7;
1487 switch(s->cc_op) {
1488 /* we optimize the cmp/jcc case */
1489 case CC_OP_SUBB:
1490 case CC_OP_SUBW:
1491 case CC_OP_SUBL:
1492 func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1493 if (!func)
1494 goto slow_jcc;
1495 break;
1496
1497 /* some jumps are easy to compute */
1498 case CC_OP_ADDB:
1499 case CC_OP_ADDW:
1500 case CC_OP_ADDL:
1501 case CC_OP_LOGICB:
1502 case CC_OP_LOGICW:
1503 case CC_OP_LOGICL:
1504 case CC_OP_INCB:
1505 case CC_OP_INCW:
1506 case CC_OP_INCL:
1507 case CC_OP_DECB:
1508 case CC_OP_DECW:
1509 case CC_OP_DECL:
1510 case CC_OP_SHLB:
1511 case CC_OP_SHLW:
1512 case CC_OP_SHLL:
1513 switch(jcc_op) {
1514 case JCC_Z:
1515 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1516 break;
1517 case JCC_S:
1518 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1519 break;
1520 default:
1521 goto slow_jcc;
1522 }
1523 break;
1524 default:
1525 slow_jcc:
1526 if (s->cc_op != CC_OP_DYNAMIC)
1527 gen_op_set_cc_op(s->cc_op);
1528 func = gen_setcc_slow[jcc_op];
1529 break;
1530 }
1531 func();
1532 if (inv) {
1533 gen_op_xor_T0_1();
1534 }
1535}
1536
1537/* move T0 to seg_reg and compute if the CPU state may change. Never
1538 call this function with seg_reg == R_CS */
1539static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
1540{
1541 if (s->pe && !s->vm86)
1542 gen_op_movl_seg_T0(seg_reg, cur_eip);
1543 else
1544 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1545 /* abort translation because the register may have a non zero base
1546 or because ss32 may change. For R_SS, translation must always
1547 stop as a special handling must be done to disable hardware
1548 interrupts for the next instruction */
1549 if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS))
1550 s->is_jmp = 3;
1551}
1552
1553/* generate a push. It depends on ss32, addseg and dflag */
1554static void gen_push_T0(DisasContext *s)
1555{
1556 if (s->ss32) {
1557 if (!s->addseg) {
1558 if (s->dflag)
1559 gen_op_pushl_T0();
1560 else
1561 gen_op_pushw_T0();
1562 } else {
1563 if (s->dflag)
1564 gen_op_pushl_ss32_T0();
1565 else
1566 gen_op_pushw_ss32_T0();
1567 }
1568 } else {
1569 if (s->dflag)
1570 gen_op_pushl_ss16_T0();
1571 else
1572 gen_op_pushw_ss16_T0();
1573 }
1574}
1575
1576/* two step pop is necessary for precise exceptions */
1577static void gen_pop_T0(DisasContext *s)
1578{
1579 if (s->ss32) {
1580 if (!s->addseg) {
1581 if (s->dflag)
1582 gen_op_popl_T0();
1583 else
1584 gen_op_popw_T0();
1585 } else {
1586 if (s->dflag)
1587 gen_op_popl_ss32_T0();
1588 else
1589 gen_op_popw_ss32_T0();
1590 }
1591 } else {
1592 if (s->dflag)
1593 gen_op_popl_ss16_T0();
1594 else
1595 gen_op_popw_ss16_T0();
1596 }
1597}
1598
1599static inline void gen_stack_update(DisasContext *s, int addend)
1600{
1601 if (s->ss32) {
1602 if (addend == 2)
1603 gen_op_addl_ESP_2();
1604 else if (addend == 4)
1605 gen_op_addl_ESP_4();
1606 else
1607 gen_op_addl_ESP_im(addend);
1608 } else {
1609 if (addend == 2)
1610 gen_op_addw_ESP_2();
1611 else if (addend == 4)
1612 gen_op_addw_ESP_4();
1613 else
1614 gen_op_addw_ESP_im(addend);
1615 }
1616}
1617
1618static void gen_pop_update(DisasContext *s)
1619{
1620 gen_stack_update(s, 2 << s->dflag);
1621}
1622
1623static void gen_stack_A0(DisasContext *s)
1624{
1625 gen_op_movl_A0_ESP();
1626 if (!s->ss32)
1627 gen_op_andl_A0_ffff();
1628 gen_op_movl_T1_A0();
1629 if (s->addseg)
1630 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1631}
1632
1633/* NOTE: wrap around in 16 bit not fully handled */
1634static void gen_pusha(DisasContext *s)
1635{
1636 int i;
1637 gen_op_movl_A0_ESP();
1638 gen_op_addl_A0_im(-16 << s->dflag);
1639 if (!s->ss32)
1640 gen_op_andl_A0_ffff();
1641 gen_op_movl_T1_A0();
1642 if (s->addseg)
1643 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1644 for(i = 0;i < 8; i++) {
1645 gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
1646 gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1647 gen_op_addl_A0_im(2 << s->dflag);
1648 }
1649 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1650}
1651
1652/* NOTE: wrap around in 16 bit not fully handled */
1653static void gen_popa(DisasContext *s)
1654{
1655 int i;
1656 gen_op_movl_A0_ESP();
1657 if (!s->ss32)
1658 gen_op_andl_A0_ffff();
1659 gen_op_movl_T1_A0();
1660 gen_op_addl_T1_im(16 << s->dflag);
1661 if (s->addseg)
1662 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1663 for(i = 0;i < 8; i++) {
1664 /* ESP is not reloaded */
1665 if (i != 3) {
1666 gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1667 gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1668 }
1669 gen_op_addl_A0_im(2 << s->dflag);
1670 }
1671 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1672}
1673
1674/* NOTE: wrap around in 16 bit not fully handled */
1675/* XXX: check this */
1676static void gen_enter(DisasContext *s, int esp_addend, int level)
1677{
1678 int ot, level1, addend, opsize;
1679
1680 ot = s->dflag + OT_WORD;
1681 level &= 0x1f;
1682 level1 = level;
1683 opsize = 2 << s->dflag;
1684
1685 gen_op_movl_A0_ESP();
1686 gen_op_addl_A0_im(-opsize);
1687 if (!s->ss32)
1688 gen_op_andl_A0_ffff();
1689 gen_op_movl_T1_A0();
1690 if (s->addseg)
1691 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1692 /* push bp */
1693 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1694 gen_op_st_T0_A0[ot + s->mem_index]();
1695 if (level) {
1696 while (level--) {
1697 gen_op_addl_A0_im(-opsize);
1698 gen_op_addl_T0_im(-opsize);
1699 gen_op_st_T0_A0[ot + s->mem_index]();
1700 }
1701 gen_op_addl_A0_im(-opsize);
1702 /* XXX: add st_T1_A0 ? */
1703 gen_op_movl_T0_T1();
1704 gen_op_st_T0_A0[ot + s->mem_index]();
1705 }
1706 gen_op_mov_reg_T1[ot][R_EBP]();
1707 addend = -esp_addend;
1708 if (level1)
1709 addend -= opsize * (level1 + 1);
1710 gen_op_addl_T1_im(addend);
1711 gen_op_mov_reg_T1[ot][R_ESP]();
1712}
1713
1714static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1715{
1716 if (s->cc_op != CC_OP_DYNAMIC)
1717 gen_op_set_cc_op(s->cc_op);
1718 gen_op_jmp_im(cur_eip);
1719 gen_op_raise_exception(trapno);
1720 s->is_jmp = 3;
1721}
1722
1723/* an interrupt is different from an exception because of the
1724 priviledge checks */
1725static void gen_interrupt(DisasContext *s, int intno,
1726 unsigned int cur_eip, unsigned int next_eip)
1727{
1728 if (s->cc_op != CC_OP_DYNAMIC)
1729 gen_op_set_cc_op(s->cc_op);
1730 gen_op_jmp_im(cur_eip);
1731 gen_op_raise_interrupt(intno, next_eip);
1732 s->is_jmp = 3;
1733}
1734
1735static void gen_debug(DisasContext *s, unsigned int cur_eip)
1736{
1737 if (s->cc_op != CC_OP_DYNAMIC)
1738 gen_op_set_cc_op(s->cc_op);
1739 gen_op_jmp_im(cur_eip);
1740 gen_op_debug();
1741 s->is_jmp = 3;
1742}
1743
1744/* generate a generic end of block. Trace exception is also generated
1745 if needed */
1746static void gen_eob(DisasContext *s)
1747{
1748 if (s->cc_op != CC_OP_DYNAMIC)
1749 gen_op_set_cc_op(s->cc_op);
34865134
FB		 1750 if (s->singlestep_enabled) {
1751 gen_op_debug();
1752 } else if (s->tf) {
2c0262af
FB		 1753 gen_op_raise_exception(EXCP01_SSTP);
1754 } else {
1755 gen_op_movl_T0_0();
1756 gen_op_exit_tb();
1757 }
1758 s->is_jmp = 3;
1759}
1760
1761/* generate a jump to eip. No segment change must happen before as a
1762 direct call to the next block may occur */
1763static void gen_jmp(DisasContext *s, unsigned int eip)
1764{
1765 TranslationBlock *tb = s->tb;
1766
1767 if (s->jmp_opt) {
1768 if (s->cc_op != CC_OP_DYNAMIC)
1769 gen_op_set_cc_op(s->cc_op);
1770 gen_op_jmp((long)tb, eip);
1771 s->is_jmp = 3;
1772 } else {
1773 gen_op_jmp_im(eip);
1774 gen_eob(s);
1775 }
1776}
1777
1778/* convert one instruction. s->is_jmp is set if the translation must
1779 be stopped. Return the next pc value */
1780static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
1781{
1782 int b, prefixes, aflag, dflag;
1783 int shift, ot;
1784 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
1785 unsigned int next_eip;
1786
1787 s->pc = pc_start;
1788 prefixes = 0;
1789 aflag = s->code32;
1790 dflag = s->code32;
1791 s->override = -1;
1792 next_byte:
61382a50 1793 b = ldub_code(s->pc);
2c0262af
FB		 1794 s->pc++;
1795 /* check prefixes */
1796 switch (b) {
1797 case 0xf3:
1798 prefixes |= PREFIX_REPZ;
1799 goto next_byte;
1800 case 0xf2:
1801 prefixes |= PREFIX_REPNZ;
1802 goto next_byte;
1803 case 0xf0:
1804 prefixes |= PREFIX_LOCK;
1805 goto next_byte;
1806 case 0x2e:
1807 s->override = R_CS;
1808 goto next_byte;
1809 case 0x36:
1810 s->override = R_SS;
1811 goto next_byte;
1812 case 0x3e:
1813 s->override = R_DS;
1814 goto next_byte;
1815 case 0x26:
1816 s->override = R_ES;
1817 goto next_byte;
1818 case 0x64:
1819 s->override = R_FS;
1820 goto next_byte;
1821 case 0x65:
1822 s->override = R_GS;
1823 goto next_byte;
1824 case 0x66:
1825 prefixes |= PREFIX_DATA;
1826 goto next_byte;
1827 case 0x67:
1828 prefixes |= PREFIX_ADR;
1829 goto next_byte;
1830 }
1831
1832 if (prefixes & PREFIX_DATA)
1833 dflag ^= 1;
1834 if (prefixes & PREFIX_ADR)
1835 aflag ^= 1;
1836
1837 s->prefix = prefixes;
1838 s->aflag = aflag;
1839 s->dflag = dflag;
1840
1841 /* lock generation */
1842 if (prefixes & PREFIX_LOCK)
1843 gen_op_lock();
1844
1845 /* now check op code */
1846 reswitch:
1847 switch(b) {
1848 case 0x0f:
1849 /**************************/
1850 /* extended op code */
61382a50 1851 b = ldub_code(s->pc++) | 0x100;
2c0262af
FB		 1852 goto reswitch;
1853
1854 /**************************/
1855 /* arith & logic */
1856 case 0x00 ... 0x05:
1857 case 0x08 ... 0x0d:
1858 case 0x10 ... 0x15:
1859 case 0x18 ... 0x1d:
1860 case 0x20 ... 0x25:
1861 case 0x28 ... 0x2d:
1862 case 0x30 ... 0x35:
1863 case 0x38 ... 0x3d:
1864 {
1865 int op, f, val;
1866 op = (b >> 3) & 7;
1867 f = (b >> 1) & 3;
1868
1869 if ((b & 1) == 0)
1870 ot = OT_BYTE;
1871 else
1872 ot = dflag ? OT_LONG : OT_WORD;
1873
1874 switch(f) {
1875 case 0: /* OP Ev, Gv */
61382a50 1876 modrm = ldub_code(s->pc++);
2c0262af
FB		 1877 reg = ((modrm >> 3) & 7);
1878 mod = (modrm >> 6) & 3;
1879 rm = modrm & 7;
1880 if (mod != 3) {
1881 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1882 opreg = OR_TMP0;
1883 } else if (op == OP_XORL && rm == reg) {
1884 xor_zero:
1885 /* xor reg, reg optimisation */
1886 gen_op_movl_T0_0();
1887 s->cc_op = CC_OP_LOGICB + ot;
1888 gen_op_mov_reg_T0[ot][reg]();
1889 gen_op_update1_cc();
1890 break;
1891 } else {
1892 opreg = rm;
1893 }
1894 gen_op_mov_TN_reg[ot][1][reg]();
1895 gen_op(s, op, ot, opreg);
1896 break;
1897 case 1: /* OP Gv, Ev */
61382a50 1898 modrm = ldub_code(s->pc++);
2c0262af
FB		 1899 mod = (modrm >> 6) & 3;
1900 reg = ((modrm >> 3) & 7);
1901 rm = modrm & 7;
1902 if (mod != 3) {
1903 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1904 gen_op_ld_T1_A0[ot + s->mem_index]();
1905 } else if (op == OP_XORL && rm == reg) {
1906 goto xor_zero;
1907 } else {
1908 gen_op_mov_TN_reg[ot][1][rm]();
1909 }
1910 gen_op(s, op, ot, reg);
1911 break;
1912 case 2: /* OP A, Iv */
1913 val = insn_get(s, ot);
1914 gen_op_movl_T1_im(val);
1915 gen_op(s, op, ot, OR_EAX);
1916 break;
1917 }
1918 }
1919 break;
1920
1921 case 0x80: /* GRP1 */
1922 case 0x81:
1923 case 0x83:
1924 {
1925 int val;
1926
1927 if ((b & 1) == 0)
1928 ot = OT_BYTE;
1929 else
1930 ot = dflag ? OT_LONG : OT_WORD;
1931
61382a50 1932 modrm = ldub_code(s->pc++);
2c0262af
FB		 1933 mod = (modrm >> 6) & 3;
1934 rm = modrm & 7;
1935 op = (modrm >> 3) & 7;
1936
1937 if (mod != 3) {
1938 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1939 opreg = OR_TMP0;
1940 } else {
1941 opreg = rm + OR_EAX;
1942 }
1943
1944 switch(b) {
1945 default:
1946 case 0x80:
1947 case 0x81:
1948 val = insn_get(s, ot);
1949 break;
1950 case 0x83:
1951 val = (int8_t)insn_get(s, OT_BYTE);
1952 break;
1953 }
1954 gen_op_movl_T1_im(val);
1955 gen_op(s, op, ot, opreg);
1956 }
1957 break;
1958
1959 /**************************/
1960 /* inc, dec, and other misc arith */
1961 case 0x40 ... 0x47: /* inc Gv */
1962 ot = dflag ? OT_LONG : OT_WORD;
1963 gen_inc(s, ot, OR_EAX + (b & 7), 1);
1964 break;
1965 case 0x48 ... 0x4f: /* dec Gv */
1966 ot = dflag ? OT_LONG : OT_WORD;
1967 gen_inc(s, ot, OR_EAX + (b & 7), -1);
1968 break;
1969 case 0xf6: /* GRP3 */
1970 case 0xf7:
1971 if ((b & 1) == 0)
1972 ot = OT_BYTE;
1973 else
1974 ot = dflag ? OT_LONG : OT_WORD;
1975
61382a50 1976 modrm = ldub_code(s->pc++);
2c0262af
FB		 1977 mod = (modrm >> 6) & 3;
1978 rm = modrm & 7;
1979 op = (modrm >> 3) & 7;
1980 if (mod != 3) {
1981 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1982 gen_op_ld_T0_A0[ot + s->mem_index]();
1983 } else {
1984 gen_op_mov_TN_reg[ot][0][rm]();
1985 }
1986
1987 switch(op) {
1988 case 0: /* test */
1989 val = insn_get(s, ot);
1990 gen_op_movl_T1_im(val);
1991 gen_op_testl_T0_T1_cc();
1992 s->cc_op = CC_OP_LOGICB + ot;
1993 break;
1994 case 2: /* not */
1995 gen_op_notl_T0();
1996 if (mod != 3) {
1997 gen_op_st_T0_A0[ot + s->mem_index]();
1998 } else {
1999 gen_op_mov_reg_T0[ot][rm]();
2000 }
2001 break;
2002 case 3: /* neg */
2003 gen_op_negl_T0();
2004 if (mod != 3) {
2005 gen_op_st_T0_A0[ot + s->mem_index]();
2006 } else {
2007 gen_op_mov_reg_T0[ot][rm]();
2008 }
2009 gen_op_update_neg_cc();
2010 s->cc_op = CC_OP_SUBB + ot;
2011 break;
2012 case 4: /* mul */
2013 switch(ot) {
2014 case OT_BYTE:
2015 gen_op_mulb_AL_T0();
2016 break;
2017 case OT_WORD:
2018 gen_op_mulw_AX_T0();
2019 break;
2020 default:
2021 case OT_LONG:
2022 gen_op_mull_EAX_T0();
2023 break;
2024 }
2025 s->cc_op = CC_OP_MUL;
2026 break;
2027 case 5: /* imul */
2028 switch(ot) {
2029 case OT_BYTE:
2030 gen_op_imulb_AL_T0();
2031 break;
2032 case OT_WORD:
2033 gen_op_imulw_AX_T0();
2034 break;
2035 default:
2036 case OT_LONG:
2037 gen_op_imull_EAX_T0();
2038 break;
2039 }
2040 s->cc_op = CC_OP_MUL;
2041 break;
2042 case 6: /* div */
2043 switch(ot) {
2044 case OT_BYTE:
2045 gen_op_divb_AL_T0(pc_start - s->cs_base);
2046 break;
2047 case OT_WORD:
2048 gen_op_divw_AX_T0(pc_start - s->cs_base);
2049 break;
2050 default:
2051 case OT_LONG:
2052 gen_op_divl_EAX_T0(pc_start - s->cs_base);
2053 break;
2054 }
2055 break;
2056 case 7: /* idiv */
2057 switch(ot) {
2058 case OT_BYTE:
2059 gen_op_idivb_AL_T0(pc_start - s->cs_base);
2060 break;
2061 case OT_WORD:
2062 gen_op_idivw_AX_T0(pc_start - s->cs_base);
2063 break;
2064 default:
2065 case OT_LONG:
2066 gen_op_idivl_EAX_T0(pc_start - s->cs_base);
2067 break;
2068 }
2069 break;
2070 default:
2071 goto illegal_op;
2072 }
2073 break;
2074
2075 case 0xfe: /* GRP4 */
2076 case 0xff: /* GRP5 */
2077 if ((b & 1) == 0)
2078 ot = OT_BYTE;
2079 else
2080 ot = dflag ? OT_LONG : OT_WORD;
2081
61382a50 2082 modrm = ldub_code(s->pc++);
2c0262af
FB		 2083 mod = (modrm >> 6) & 3;
2084 rm = modrm & 7;
2085 op = (modrm >> 3) & 7;
2086 if (op >= 2 && b == 0xfe) {
2087 goto illegal_op;
2088 }
2089 if (mod != 3) {
2090 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2091 if (op >= 2 && op != 3 && op != 5)
2092 gen_op_ld_T0_A0[ot + s->mem_index]();
2093 } else {
2094 gen_op_mov_TN_reg[ot][0][rm]();
2095 }
2096
2097 switch(op) {
2098 case 0: /* inc Ev */
2099 if (mod != 3)
2100 opreg = OR_TMP0;
2101 else
2102 opreg = rm;
2103 gen_inc(s, ot, opreg, 1);
2104 break;
2105 case 1: /* dec Ev */
2106 if (mod != 3)
2107 opreg = OR_TMP0;
2108 else
2109 opreg = rm;
2110 gen_inc(s, ot, opreg, -1);
2111 break;
2112 case 2: /* call Ev */
2113 /* XXX: optimize if memory (no and is necessary) */
2114 if (s->dflag == 0)
2115 gen_op_andl_T0_ffff();
2116 gen_op_jmp_T0();
2117 next_eip = s->pc - s->cs_base;
2118 gen_op_movl_T0_im(next_eip);
2119 gen_push_T0(s);
2120 gen_eob(s);
2121 break;
61382a50 2122 case 3: /* lcall Ev */
2c0262af
FB		 2123 gen_op_ld_T1_A0[ot + s->mem_index]();
2124 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
61382a50 2125 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2c0262af
FB		 2126 do_lcall:
2127 if (s->pe && !s->vm86) {
2128 if (s->cc_op != CC_OP_DYNAMIC)
2129 gen_op_set_cc_op(s->cc_op);
2130 gen_op_jmp_im(pc_start - s->cs_base);
2131 gen_op_lcall_protected_T0_T1(dflag, s->pc - s->cs_base);
2132 } else {
2133 gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
2134 }
2135 gen_eob(s);
2136 break;
2137 case 4: /* jmp Ev */
2138 if (s->dflag == 0)
2139 gen_op_andl_T0_ffff();
2140 gen_op_jmp_T0();
2141 gen_eob(s);
2142 break;
2143 case 5: /* ljmp Ev */
2144 gen_op_ld_T1_A0[ot + s->mem_index]();
2145 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
61382a50 2146 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2c0262af
FB		 2147 do_ljmp:
2148 if (s->pe && !s->vm86) {
2149 if (s->cc_op != CC_OP_DYNAMIC)
2150 gen_op_set_cc_op(s->cc_op);
2151 gen_op_jmp_im(pc_start - s->cs_base);
2152 gen_op_ljmp_protected_T0_T1();
2153 } else {
2154 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
2155 gen_op_movl_T0_T1();
2156 gen_op_jmp_T0();
2157 }
2158 gen_eob(s);
2159 break;
2160 case 6: /* push Ev */
2161 gen_push_T0(s);
2162 break;
2163 default:
2164 goto illegal_op;
2165 }
2166 break;
2167
2168 case 0x84: /* test Ev, Gv */
2169 case 0x85:
2170 if ((b & 1) == 0)
2171 ot = OT_BYTE;
2172 else
2173 ot = dflag ? OT_LONG : OT_WORD;
2174
61382a50 2175 modrm = ldub_code(s->pc++);
2c0262af
FB		 2176 mod = (modrm >> 6) & 3;
2177 rm = modrm & 7;
2178 reg = (modrm >> 3) & 7;
2179
2180 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2181 gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
2182 gen_op_testl_T0_T1_cc();
2183 s->cc_op = CC_OP_LOGICB + ot;
2184 break;
2185
2186 case 0xa8: /* test eAX, Iv */
2187 case 0xa9:
2188 if ((b & 1) == 0)
2189 ot = OT_BYTE;
2190 else
2191 ot = dflag ? OT_LONG : OT_WORD;
2192 val = insn_get(s, ot);
2193
2194 gen_op_mov_TN_reg[ot][0][OR_EAX]();
2195 gen_op_movl_T1_im(val);
2196 gen_op_testl_T0_T1_cc();
2197 s->cc_op = CC_OP_LOGICB + ot;
2198 break;
2199
2200 case 0x98: /* CWDE/CBW */
2201 if (dflag)
2202 gen_op_movswl_EAX_AX();
2203 else
2204 gen_op_movsbw_AX_AL();
2205 break;
2206 case 0x99: /* CDQ/CWD */
2207 if (dflag)
2208 gen_op_movslq_EDX_EAX();
2209 else
2210 gen_op_movswl_DX_AX();
2211 break;
2212 case 0x1af: /* imul Gv, Ev */
2213 case 0x69: /* imul Gv, Ev, I */
2214 case 0x6b:
2215 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2216 modrm = ldub_code(s->pc++);
2c0262af
FB		 2217 reg = ((modrm >> 3) & 7) + OR_EAX;
2218 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2219 if (b == 0x69) {
2220 val = insn_get(s, ot);
2221 gen_op_movl_T1_im(val);
2222 } else if (b == 0x6b) {
2223 val = insn_get(s, OT_BYTE);
2224 gen_op_movl_T1_im(val);
2225 } else {
2226 gen_op_mov_TN_reg[ot][1][reg]();
2227 }
2228
2229 if (ot == OT_LONG) {
2230 gen_op_imull_T0_T1();
2231 } else {
2232 gen_op_imulw_T0_T1();
2233 }
2234 gen_op_mov_reg_T0[ot][reg]();
2235 s->cc_op = CC_OP_MUL;
2236 break;
2237 case 0x1c0:
2238 case 0x1c1: /* xadd Ev, Gv */
2239 if ((b & 1) == 0)
2240 ot = OT_BYTE;
2241 else
2242 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2243 modrm = ldub_code(s->pc++);
2c0262af
FB		 2244 reg = (modrm >> 3) & 7;
2245 mod = (modrm >> 6) & 3;
2246 if (mod == 3) {
2247 rm = modrm & 7;
2248 gen_op_mov_TN_reg[ot][0][reg]();
2249 gen_op_mov_TN_reg[ot][1][rm]();
2250 gen_op_addl_T0_T1();
2251 gen_op_mov_reg_T0[ot][rm]();
2252 gen_op_mov_reg_T1[ot][reg]();
2253 } else {
2254 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2255 gen_op_mov_TN_reg[ot][0][reg]();
2256 gen_op_ld_T1_A0[ot + s->mem_index]();
2257 gen_op_addl_T0_T1();
2258 gen_op_st_T0_A0[ot + s->mem_index]();
2259 gen_op_mov_reg_T1[ot][reg]();
2260 }
2261 gen_op_update2_cc();
2262 s->cc_op = CC_OP_ADDB + ot;
2263 break;
2264 case 0x1b0:
2265 case 0x1b1: /* cmpxchg Ev, Gv */
2266 if ((b & 1) == 0)
2267 ot = OT_BYTE;
2268 else
2269 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2270 modrm = ldub_code(s->pc++);
2c0262af
FB		 2271 reg = (modrm >> 3) & 7;
2272 mod = (modrm >> 6) & 3;
2273 gen_op_mov_TN_reg[ot][1][reg]();
2274 if (mod == 3) {
2275 rm = modrm & 7;
2276 gen_op_mov_TN_reg[ot][0][rm]();
2277 gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
2278 gen_op_mov_reg_T0[ot][rm]();
2279 } else {
2280 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2281 gen_op_ld_T0_A0[ot + s->mem_index]();
2282 gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot]();
2283 }
2284 s->cc_op = CC_OP_SUBB + ot;
2285 break;
2286 case 0x1c7: /* cmpxchg8b */
61382a50 2287 modrm = ldub_code(s->pc++);
2c0262af
FB		 2288 mod = (modrm >> 6) & 3;
2289 if (mod == 3)
2290 goto illegal_op;
2291 if (s->cc_op != CC_OP_DYNAMIC)
2292 gen_op_set_cc_op(s->cc_op);
2293 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2294 gen_op_cmpxchg8b();
2295 s->cc_op = CC_OP_EFLAGS;
2296 break;
2297
2298 /**************************/
2299 /* push/pop */
2300 case 0x50 ... 0x57: /* push */
2301 gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
2302 gen_push_T0(s);
2303 break;
2304 case 0x58 ... 0x5f: /* pop */
2305 ot = dflag ? OT_LONG : OT_WORD;
2306 gen_pop_T0(s);
2307 gen_op_mov_reg_T0[ot][b & 7]();
2308 gen_pop_update(s);
2309 break;
2310 case 0x60: /* pusha */
2311 gen_pusha(s);
2312 break;
2313 case 0x61: /* popa */
2314 gen_popa(s);
2315 break;
2316 case 0x68: /* push Iv */
2317 case 0x6a:
2318 ot = dflag ? OT_LONG : OT_WORD;
2319 if (b == 0x68)
2320 val = insn_get(s, ot);
2321 else
2322 val = (int8_t)insn_get(s, OT_BYTE);
2323 gen_op_movl_T0_im(val);
2324 gen_push_T0(s);
2325 break;
2326 case 0x8f: /* pop Ev */
2327 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2328 modrm = ldub_code(s->pc++);
2c0262af
FB		 2329 gen_pop_T0(s);
2330 s->popl_esp_hack = 2 << dflag;
2331 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2332 s->popl_esp_hack = 0;
2333 gen_pop_update(s);
2334 break;
2335 case 0xc8: /* enter */
2336 {
2337 int level;
61382a50 2338 val = lduw_code(s->pc);
2c0262af 2339 s->pc += 2;
61382a50 2340 level = ldub_code(s->pc++);
2c0262af
FB		 2341 gen_enter(s, val, level);
2342 }
2343 break;
2344 case 0xc9: /* leave */
2345 /* XXX: exception not precise (ESP is updated before potential exception) */
2346 if (s->ss32) {
2347 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2348 gen_op_mov_reg_T0[OT_LONG][R_ESP]();
2349 } else {
2350 gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
2351 gen_op_mov_reg_T0[OT_WORD][R_ESP]();
2352 }
2353 gen_pop_T0(s);
2354 ot = dflag ? OT_LONG : OT_WORD;
2355 gen_op_mov_reg_T0[ot][R_EBP]();
2356 gen_pop_update(s);
2357 break;
2358 case 0x06: /* push es */
2359 case 0x0e: /* push cs */
2360 case 0x16: /* push ss */
2361 case 0x1e: /* push ds */
2362 gen_op_movl_T0_seg(b >> 3);
2363 gen_push_T0(s);
2364 break;
2365 case 0x1a0: /* push fs */
2366 case 0x1a8: /* push gs */
2367 gen_op_movl_T0_seg((b >> 3) & 7);
2368 gen_push_T0(s);
2369 break;
2370 case 0x07: /* pop es */
2371 case 0x17: /* pop ss */
2372 case 0x1f: /* pop ds */
2373 reg = b >> 3;
2374 gen_pop_T0(s);
2375 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2376 gen_pop_update(s);
2377 if (reg == R_SS) {
2378 /* if reg == SS, inhibit interrupts/trace */
2379 gen_op_set_inhibit_irq();
2380 s->tf = 0;
2381 }
2382 if (s->is_jmp) {
2383 gen_op_jmp_im(s->pc - s->cs_base);
2384 gen_eob(s);
2385 }
2386 break;
2387 case 0x1a1: /* pop fs */
2388 case 0x1a9: /* pop gs */
2389 gen_pop_T0(s);
2390 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
2391 gen_pop_update(s);
2392 if (s->is_jmp) {
2393 gen_op_jmp_im(s->pc - s->cs_base);
2394 gen_eob(s);
2395 }
2396 break;
2397
2398 /**************************/
2399 /* mov */
2400 case 0x88:
2401 case 0x89: /* mov Gv, Ev */
2402 if ((b & 1) == 0)
2403 ot = OT_BYTE;
2404 else
2405 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2406 modrm = ldub_code(s->pc++);
2c0262af
FB		 2407 reg = (modrm >> 3) & 7;
2408
2409 /* generate a generic store */
2410 gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
2411 break;
2412 case 0xc6:
2413 case 0xc7: /* mov Ev, Iv */
2414 if ((b & 1) == 0)
2415 ot = OT_BYTE;
2416 else
2417 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2418 modrm = ldub_code(s->pc++);
2c0262af
FB		 2419 mod = (modrm >> 6) & 3;
2420 if (mod != 3)
2421 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2422 val = insn_get(s, ot);
2423 gen_op_movl_T0_im(val);
2424 if (mod != 3)
2425 gen_op_st_T0_A0[ot + s->mem_index]();
2426 else
2427 gen_op_mov_reg_T0[ot][modrm & 7]();
2428 break;
2429 case 0x8a:
2430 case 0x8b: /* mov Ev, Gv */
2431 if ((b & 1) == 0)
2432 ot = OT_BYTE;
2433 else
2434 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2435 modrm = ldub_code(s->pc++);
2c0262af
FB		 2436 reg = (modrm >> 3) & 7;
2437
2438 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2439 gen_op_mov_reg_T0[ot][reg]();
2440 break;
2441 case 0x8e: /* mov seg, Gv */
61382a50 2442 modrm = ldub_code(s->pc++);
2c0262af
FB		 2443 reg = (modrm >> 3) & 7;
2444 if (reg >= 6 || reg == R_CS)
2445 goto illegal_op;
2446 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2447 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2448 if (reg == R_SS) {
2449 /* if reg == SS, inhibit interrupts/trace */
2450 gen_op_set_inhibit_irq();
2451 s->tf = 0;
2452 }
2453 if (s->is_jmp) {
2454 gen_op_jmp_im(s->pc - s->cs_base);
2455 gen_eob(s);
2456 }
2457 break;
2458 case 0x8c: /* mov Gv, seg */
61382a50 2459 modrm = ldub_code(s->pc++);
2c0262af
FB		 2460 reg = (modrm >> 3) & 7;
2461 mod = (modrm >> 6) & 3;
2462 if (reg >= 6)
2463 goto illegal_op;
2464 gen_op_movl_T0_seg(reg);
2465 ot = OT_WORD;
2466 if (mod == 3 && dflag)
2467 ot = OT_LONG;
2468 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2469 break;
2470
2471 case 0x1b6: /* movzbS Gv, Eb */
2472 case 0x1b7: /* movzwS Gv, Eb */
2473 case 0x1be: /* movsbS Gv, Eb */
2474 case 0x1bf: /* movswS Gv, Eb */
2475 {
2476 int d_ot;
2477 /* d_ot is the size of destination */
2478 d_ot = dflag + OT_WORD;
2479 /* ot is the size of source */
2480 ot = (b & 1) + OT_BYTE;
61382a50 2481 modrm = ldub_code(s->pc++);
2c0262af
FB		 2482 reg = ((modrm >> 3) & 7) + OR_EAX;
2483 mod = (modrm >> 6) & 3;
2484 rm = modrm & 7;
2485
2486 if (mod == 3) {
2487 gen_op_mov_TN_reg[ot][0][rm]();
2488 switch(ot | (b & 8)) {
2489 case OT_BYTE:
2490 gen_op_movzbl_T0_T0();
2491 break;
2492 case OT_BYTE | 8:
2493 gen_op_movsbl_T0_T0();
2494 break;
2495 case OT_WORD:
2496 gen_op_movzwl_T0_T0();
2497 break;
2498 default:
2499 case OT_WORD | 8:
2500 gen_op_movswl_T0_T0();
2501 break;
2502 }
2503 gen_op_mov_reg_T0[d_ot][reg]();
2504 } else {
2505 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2506 if (b & 8) {
2507 gen_op_lds_T0_A0[ot + s->mem_index]();
2508 } else {
2509 gen_op_ldu_T0_A0[ot + s->mem_index]();
2510 }
2511 gen_op_mov_reg_T0[d_ot][reg]();
2512 }
2513 }
2514 break;
2515
2516 case 0x8d: /* lea */
2517 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2518 modrm = ldub_code(s->pc++);
2c0262af
FB		 2519 reg = (modrm >> 3) & 7;
2520 /* we must ensure that no segment is added */
2521 s->override = -1;
2522 val = s->addseg;
2523 s->addseg = 0;
2524 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2525 s->addseg = val;
2526 gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2527 break;
2528
2529 case 0xa0: /* mov EAX, Ov */
2530 case 0xa1:
2531 case 0xa2: /* mov Ov, EAX */
2532 case 0xa3:
2533 if ((b & 1) == 0)
2534 ot = OT_BYTE;
2535 else
2536 ot = dflag ? OT_LONG : OT_WORD;
2537 if (s->aflag)
2538 offset_addr = insn_get(s, OT_LONG);
2539 else
2540 offset_addr = insn_get(s, OT_WORD);
2541 gen_op_movl_A0_im(offset_addr);
2542 /* handle override */
2543 {
2544 int override, must_add_seg;
2545 must_add_seg = s->addseg;
2546 if (s->override >= 0) {
2547 override = s->override;
2548 must_add_seg = 1;
2549 } else {
2550 override = R_DS;
2551 }
2552 if (must_add_seg) {
2553 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2554 }
2555 }
2556 if ((b & 2) == 0) {
2557 gen_op_ld_T0_A0[ot + s->mem_index]();
2558 gen_op_mov_reg_T0[ot][R_EAX]();
2559 } else {
2560 gen_op_mov_TN_reg[ot][0][R_EAX]();
2561 gen_op_st_T0_A0[ot + s->mem_index]();
2562 }
2563 break;
2564 case 0xd7: /* xlat */
2565 gen_op_movl_A0_reg[R_EBX]();
2566 gen_op_addl_A0_AL();
2567 if (s->aflag == 0)
2568 gen_op_andl_A0_ffff();
2569 /* handle override */
2570 {
2571 int override, must_add_seg;
2572 must_add_seg = s->addseg;
2573 override = R_DS;
2574 if (s->override >= 0) {
2575 override = s->override;
2576 must_add_seg = 1;
2577 } else {
2578 override = R_DS;
2579 }
2580 if (must_add_seg) {
2581 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2582 }
2583 }
2584 gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
2585 gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2586 break;
2587 case 0xb0 ... 0xb7: /* mov R, Ib */
2588 val = insn_get(s, OT_BYTE);
2589 gen_op_movl_T0_im(val);
2590 gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2591 break;
2592 case 0xb8 ... 0xbf: /* mov R, Iv */
2593 ot = dflag ? OT_LONG : OT_WORD;
2594 val = insn_get(s, ot);
2595 reg = OR_EAX + (b & 7);
2596 gen_op_movl_T0_im(val);
2597 gen_op_mov_reg_T0[ot][reg]();
2598 break;
2599
2600 case 0x91 ... 0x97: /* xchg R, EAX */
2601 ot = dflag ? OT_LONG : OT_WORD;
2602 reg = b & 7;
2603 rm = R_EAX;
2604 goto do_xchg_reg;
2605 case 0x86:
2606 case 0x87: /* xchg Ev, Gv */
2607 if ((b & 1) == 0)
2608 ot = OT_BYTE;
2609 else
2610 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2611 modrm = ldub_code(s->pc++);
2c0262af
FB		 2612 reg = (modrm >> 3) & 7;
2613 mod = (modrm >> 6) & 3;
2614 if (mod == 3) {
2615 rm = modrm & 7;
2616 do_xchg_reg:
2617 gen_op_mov_TN_reg[ot][0][reg]();
2618 gen_op_mov_TN_reg[ot][1][rm]();
2619 gen_op_mov_reg_T0[ot][rm]();
2620 gen_op_mov_reg_T1[ot][reg]();
2621 } else {
2622 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2623 gen_op_mov_TN_reg[ot][0][reg]();
2624 /* for xchg, lock is implicit */
2625 if (!(prefixes & PREFIX_LOCK))
2626 gen_op_lock();
2627 gen_op_ld_T1_A0[ot + s->mem_index]();
2628 gen_op_st_T0_A0[ot + s->mem_index]();
2629 if (!(prefixes & PREFIX_LOCK))
2630 gen_op_unlock();
2631 gen_op_mov_reg_T1[ot][reg]();
2632 }
2633 break;
2634 case 0xc4: /* les Gv */
2635 op = R_ES;
2636 goto do_lxx;
2637 case 0xc5: /* lds Gv */
2638 op = R_DS;
2639 goto do_lxx;
2640 case 0x1b2: /* lss Gv */
2641 op = R_SS;
2642 goto do_lxx;
2643 case 0x1b4: /* lfs Gv */
2644 op = R_FS;
2645 goto do_lxx;
2646 case 0x1b5: /* lgs Gv */
2647 op = R_GS;
2648 do_lxx:
2649 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2650 modrm = ldub_code(s->pc++);
2c0262af
FB		 2651 reg = (modrm >> 3) & 7;
2652 mod = (modrm >> 6) & 3;
2653 if (mod == 3)
2654 goto illegal_op;
2655 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2656 gen_op_ld_T1_A0[ot + s->mem_index]();
2657 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2658 /* load the segment first to handle exceptions properly */
61382a50 2659 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2c0262af
FB		 2660 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
2661 /* then put the data */
2662 gen_op_mov_reg_T1[ot][reg]();
2663 if (s->is_jmp) {
2664 gen_op_jmp_im(s->pc - s->cs_base);
2665 gen_eob(s);
2666 }
2667 break;
2668
2669 /************************/
2670 /* shifts */
2671 case 0xc0:
2672 case 0xc1:
2673 /* shift Ev,Ib */
2674 shift = 2;
2675 grp2:
2676 {
2677 if ((b & 1) == 0)
2678 ot = OT_BYTE;
2679 else
2680 ot = dflag ? OT_LONG : OT_WORD;
2681
61382a50 2682 modrm = ldub_code(s->pc++);
2c0262af
FB		 2683 mod = (modrm >> 6) & 3;
2684 rm = modrm & 7;
2685 op = (modrm >> 3) & 7;
2686
2687 if (mod != 3) {
2688 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2689 opreg = OR_TMP0;
2690 } else {
2691 opreg = rm + OR_EAX;
2692 }
2693
2694 /* simpler op */
2695 if (shift == 0) {
2696 gen_shift(s, op, ot, opreg, OR_ECX);
2697 } else {
2698 if (shift == 2) {
61382a50 2699 shift = ldub_code(s->pc++);
2c0262af
FB		 2700 }
2701 gen_shifti(s, op, ot, opreg, shift);
2702 }
2703 }
2704 break;
2705 case 0xd0:
2706 case 0xd1:
2707 /* shift Ev,1 */
2708 shift = 1;
2709 goto grp2;
2710 case 0xd2:
2711 case 0xd3:
2712 /* shift Ev,cl */
2713 shift = 0;
2714 goto grp2;
2715
2716 case 0x1a4: /* shld imm */
2717 op = 0;
2718 shift = 1;
2719 goto do_shiftd;
2720 case 0x1a5: /* shld cl */
2721 op = 0;
2722 shift = 0;
2723 goto do_shiftd;
2724 case 0x1ac: /* shrd imm */
2725 op = 1;
2726 shift = 1;
2727 goto do_shiftd;
2728 case 0x1ad: /* shrd cl */
2729 op = 1;
2730 shift = 0;
2731 do_shiftd:
2732 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2733 modrm = ldub_code(s->pc++);
2c0262af
FB		 2734 mod = (modrm >> 6) & 3;
2735 rm = modrm & 7;
2736 reg = (modrm >> 3) & 7;
2737
2738 if (mod != 3) {
2739 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2740 gen_op_ld_T0_A0[ot + s->mem_index]();
2741 } else {
2742 gen_op_mov_TN_reg[ot][0][rm]();
2743 }
2744 gen_op_mov_TN_reg[ot][1][reg]();
2745
2746 if (shift) {
61382a50 2747 val = ldub_code(s->pc++);
2c0262af
FB		 2748 val &= 0x1f;
2749 if (val) {
2750 if (mod == 3)
2751 gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val);
2752 else
2753 gen_op_shiftd_mem_T0_T1_im_cc[ot - OT_WORD][op](val);
2754 if (op == 0 && ot != OT_WORD)
2755 s->cc_op = CC_OP_SHLB + ot;
2756 else
2757 s->cc_op = CC_OP_SARB + ot;
2758 }
2759 } else {
2760 if (s->cc_op != CC_OP_DYNAMIC)
2761 gen_op_set_cc_op(s->cc_op);
2762 if (mod == 3)
2763 gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op]();
2764 else
2765 gen_op_shiftd_mem_T0_T1_ECX_cc[ot - OT_WORD][op]();
2766 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2767 }
2768 if (mod == 3) {
2769 gen_op_mov_reg_T0[ot][rm]();
2770 }
2771 break;
2772
2773 /************************/
2774 /* floats */
2775 case 0xd8 ... 0xdf:
61382a50 2776 modrm = ldub_code(s->pc++);
2c0262af
FB		 2777 mod = (modrm >> 6) & 3;
2778 rm = modrm & 7;
2779 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2780
2781 if (mod != 3) {
2782 /* memory op */
2783 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2784 switch(op) {
2785 case 0x00 ... 0x07: /* fxxxs */
2786 case 0x10 ... 0x17: /* fixxxl */
2787 case 0x20 ... 0x27: /* fxxxl */
2788 case 0x30 ... 0x37: /* fixxx */
2789 {
2790 int op1;
2791 op1 = op & 7;
2792
2793 switch(op >> 4) {
2794 case 0:
2795 gen_op_flds_FT0_A0();
2796 break;
2797 case 1:
2798 gen_op_fildl_FT0_A0();
2799 break;
2800 case 2:
2801 gen_op_fldl_FT0_A0();
2802 break;
2803 case 3:
2804 default:
2805 gen_op_fild_FT0_A0();
2806 break;
2807 }
2808
2809 gen_op_fp_arith_ST0_FT0[op1]();
2810 if (op1 == 3) {
2811 /* fcomp needs pop */
2812 gen_op_fpop();
2813 }
2814 }
2815 break;
2816 case 0x08: /* flds */
2817 case 0x0a: /* fsts */
2818 case 0x0b: /* fstps */
2819 case 0x18: /* fildl */
2820 case 0x1a: /* fistl */
2821 case 0x1b: /* fistpl */
2822 case 0x28: /* fldl */
2823 case 0x2a: /* fstl */
2824 case 0x2b: /* fstpl */
2825 case 0x38: /* filds */
2826 case 0x3a: /* fists */
2827 case 0x3b: /* fistps */
2828
2829 switch(op & 7) {
2830 case 0:
2831 switch(op >> 4) {
2832 case 0:
2833 gen_op_flds_ST0_A0();
2834 break;
2835 case 1:
2836 gen_op_fildl_ST0_A0();
2837 break;
2838 case 2:
2839 gen_op_fldl_ST0_A0();
2840 break;
2841 case 3:
2842 default:
2843 gen_op_fild_ST0_A0();
2844 break;
2845 }
2846 break;
2847 default:
2848 switch(op >> 4) {
2849 case 0:
2850 gen_op_fsts_ST0_A0();
2851 break;
2852 case 1:
2853 gen_op_fistl_ST0_A0();
2854 break;
2855 case 2:
2856 gen_op_fstl_ST0_A0();
2857 break;
2858 case 3:
2859 default:
2860 gen_op_fist_ST0_A0();
2861 break;
2862 }
2863 if ((op & 7) == 3)
2864 gen_op_fpop();
2865 break;
2866 }
2867 break;
2868 case 0x0c: /* fldenv mem */
2869 gen_op_fldenv_A0(s->dflag);
2870 break;
2871 case 0x0d: /* fldcw mem */
2872 gen_op_fldcw_A0();
2873 break;
2874 case 0x0e: /* fnstenv mem */
2875 gen_op_fnstenv_A0(s->dflag);
2876 break;
2877 case 0x0f: /* fnstcw mem */
2878 gen_op_fnstcw_A0();
2879 break;
2880 case 0x1d: /* fldt mem */
2881 gen_op_fldt_ST0_A0();
2882 break;
2883 case 0x1f: /* fstpt mem */
2884 gen_op_fstt_ST0_A0();
2885 gen_op_fpop();
2886 break;
2887 case 0x2c: /* frstor mem */
2888 gen_op_frstor_A0(s->dflag);
2889 break;
2890 case 0x2e: /* fnsave mem */
2891 gen_op_fnsave_A0(s->dflag);
2892 break;
2893 case 0x2f: /* fnstsw mem */
2894 gen_op_fnstsw_A0();
2895 break;
2896 case 0x3c: /* fbld */
2897 gen_op_fbld_ST0_A0();
2898 break;
2899 case 0x3e: /* fbstp */
2900 gen_op_fbst_ST0_A0();
2901 gen_op_fpop();
2902 break;
2903 case 0x3d: /* fildll */
2904 gen_op_fildll_ST0_A0();
2905 break;
2906 case 0x3f: /* fistpll */
2907 gen_op_fistll_ST0_A0();
2908 gen_op_fpop();
2909 break;
2910 default:
2911 goto illegal_op;
2912 }
2913 } else {
2914 /* register float ops */
2915 opreg = rm;
2916
2917 switch(op) {
2918 case 0x08: /* fld sti */
2919 gen_op_fpush();
2920 gen_op_fmov_ST0_STN((opreg + 1) & 7);
2921 break;
2922 case 0x09: /* fxchg sti */
2923 gen_op_fxchg_ST0_STN(opreg);
2924 break;
2925 case 0x0a: /* grp d9/2 */
2926 switch(rm) {
2927 case 0: /* fnop */
2928 break;
2929 default:
2930 goto illegal_op;
2931 }
2932 break;
2933 case 0x0c: /* grp d9/4 */
2934 switch(rm) {
2935 case 0: /* fchs */
2936 gen_op_fchs_ST0();
2937 break;
2938 case 1: /* fabs */
2939 gen_op_fabs_ST0();
2940 break;
2941 case 4: /* ftst */
2942 gen_op_fldz_FT0();
2943 gen_op_fcom_ST0_FT0();
2944 break;
2945 case 5: /* fxam */
2946 gen_op_fxam_ST0();
2947 break;
2948 default:
2949 goto illegal_op;
2950 }
2951 break;
2952 case 0x0d: /* grp d9/5 */
2953 {
2954 switch(rm) {
2955 case 0:
2956 gen_op_fpush();
2957 gen_op_fld1_ST0();
2958 break;
2959 case 1:
2960 gen_op_fpush();
2961 gen_op_fldl2t_ST0();
2962 break;
2963 case 2:
2964 gen_op_fpush();
2965 gen_op_fldl2e_ST0();
2966 break;
2967 case 3:
2968 gen_op_fpush();
2969 gen_op_fldpi_ST0();
2970 break;
2971 case 4:
2972 gen_op_fpush();
2973 gen_op_fldlg2_ST0();
2974 break;
2975 case 5:
2976 gen_op_fpush();
2977 gen_op_fldln2_ST0();
2978 break;
2979 case 6:
2980 gen_op_fpush();
2981 gen_op_fldz_ST0();
2982 break;
2983 default:
2984 goto illegal_op;
2985 }
2986 }
2987 break;
2988 case 0x0e: /* grp d9/6 */
2989 switch(rm) {
2990 case 0: /* f2xm1 */
2991 gen_op_f2xm1();
2992 break;
2993 case 1: /* fyl2x */
2994 gen_op_fyl2x();
2995 break;
2996 case 2: /* fptan */
2997 gen_op_fptan();
2998 break;
2999 case 3: /* fpatan */
3000 gen_op_fpatan();
3001 break;
3002 case 4: /* fxtract */
3003 gen_op_fxtract();
3004 break;
3005 case 5: /* fprem1 */
3006 gen_op_fprem1();
3007 break;
3008 case 6: /* fdecstp */
3009 gen_op_fdecstp();
3010 break;
3011 default:
3012 case 7: /* fincstp */
3013 gen_op_fincstp();
3014 break;
3015 }
3016 break;
3017 case 0x0f: /* grp d9/7 */
3018 switch(rm) {
3019 case 0: /* fprem */
3020 gen_op_fprem();
3021 break;
3022 case 1: /* fyl2xp1 */
3023 gen_op_fyl2xp1();
3024 break;
3025 case 2: /* fsqrt */
3026 gen_op_fsqrt();
3027 break;
3028 case 3: /* fsincos */
3029 gen_op_fsincos();
3030 break;
3031 case 5: /* fscale */
3032 gen_op_fscale();
3033 break;
3034 case 4: /* frndint */
3035 gen_op_frndint();
3036 break;
3037 case 6: /* fsin */
3038 gen_op_fsin();
3039 break;
3040 default:
3041 case 7: /* fcos */
3042 gen_op_fcos();
3043 break;
3044 }
3045 break;
3046 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
3047 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
3048 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
3049 {
3050 int op1;
3051
3052 op1 = op & 7;
3053 if (op >= 0x20) {
3054 gen_op_fp_arith_STN_ST0[op1](opreg);
3055 if (op >= 0x30)
3056 gen_op_fpop();
3057 } else {
3058 gen_op_fmov_FT0_STN(opreg);
3059 gen_op_fp_arith_ST0_FT0[op1]();
3060 }
3061 }
3062 break;
3063 case 0x02: /* fcom */
3064 gen_op_fmov_FT0_STN(opreg);
3065 gen_op_fcom_ST0_FT0();
3066 break;
3067 case 0x03: /* fcomp */
3068 gen_op_fmov_FT0_STN(opreg);
3069 gen_op_fcom_ST0_FT0();
3070 gen_op_fpop();
3071 break;
3072 case 0x15: /* da/5 */
3073 switch(rm) {
3074 case 1: /* fucompp */
3075 gen_op_fmov_FT0_STN(1);
3076 gen_op_fucom_ST0_FT0();
3077 gen_op_fpop();
3078 gen_op_fpop();
3079 break;
3080 default:
3081 goto illegal_op;
3082 }
3083 break;
3084 case 0x1c:
3085 switch(rm) {
3086 case 0: /* feni (287 only, just do nop here) */
3087 break;
3088 case 1: /* fdisi (287 only, just do nop here) */
3089 break;
3090 case 2: /* fclex */
3091 gen_op_fclex();
3092 break;
3093 case 3: /* fninit */
3094 gen_op_fninit();
3095 break;
3096 case 4: /* fsetpm (287 only, just do nop here) */
3097 break;
3098 default:
3099 goto illegal_op;
3100 }
3101 break;
3102 case 0x1d: /* fucomi */
3103 if (s->cc_op != CC_OP_DYNAMIC)
3104 gen_op_set_cc_op(s->cc_op);
3105 gen_op_fmov_FT0_STN(opreg);
3106 gen_op_fucomi_ST0_FT0();
3107 s->cc_op = CC_OP_EFLAGS;
3108 break;
3109 case 0x1e: /* fcomi */
3110 if (s->cc_op != CC_OP_DYNAMIC)
3111 gen_op_set_cc_op(s->cc_op);
3112 gen_op_fmov_FT0_STN(opreg);
3113 gen_op_fcomi_ST0_FT0();
3114 s->cc_op = CC_OP_EFLAGS;
3115 break;
3116 case 0x2a: /* fst sti */
3117 gen_op_fmov_STN_ST0(opreg);
3118 break;
3119 case 0x2b: /* fstp sti */
3120 gen_op_fmov_STN_ST0(opreg);
3121 gen_op_fpop();
3122 break;
3123 case 0x2c: /* fucom st(i) */
3124 gen_op_fmov_FT0_STN(opreg);
3125 gen_op_fucom_ST0_FT0();
3126 break;
3127 case 0x2d: /* fucomp st(i) */
3128 gen_op_fmov_FT0_STN(opreg);
3129 gen_op_fucom_ST0_FT0();
3130 gen_op_fpop();
3131 break;
3132 case 0x33: /* de/3 */
3133 switch(rm) {
3134 case 1: /* fcompp */
3135 gen_op_fmov_FT0_STN(1);
3136 gen_op_fcom_ST0_FT0();
3137 gen_op_fpop();
3138 gen_op_fpop();
3139 break;
3140 default:
3141 goto illegal_op;
3142 }
3143 break;
3144 case 0x3c: /* df/4 */
3145 switch(rm) {
3146 case 0:
3147 gen_op_fnstsw_EAX();
3148 break;
3149 default:
3150 goto illegal_op;
3151 }
3152 break;
3153 case 0x3d: /* fucomip */
3154 if (s->cc_op != CC_OP_DYNAMIC)
3155 gen_op_set_cc_op(s->cc_op);
3156 gen_op_fmov_FT0_STN(opreg);
3157 gen_op_fucomi_ST0_FT0();
3158 gen_op_fpop();
3159 s->cc_op = CC_OP_EFLAGS;
3160 break;
3161 case 0x3e: /* fcomip */
3162 if (s->cc_op != CC_OP_DYNAMIC)
3163 gen_op_set_cc_op(s->cc_op);
3164 gen_op_fmov_FT0_STN(opreg);
3165 gen_op_fcomi_ST0_FT0();
3166 gen_op_fpop();
3167 s->cc_op = CC_OP_EFLAGS;
3168 break;
3169 default:
3170 goto illegal_op;
3171 }
3172 }
3173 break;
3174 /************************/
3175 /* string ops */
3176
3177 case 0xa4: /* movsS */
3178 case 0xa5:
3179 if ((b & 1) == 0)
3180 ot = OT_BYTE;
3181 else
3182 ot = dflag ? OT_LONG : OT_WORD;
3183
3184 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3185 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3186 } else {
3187 gen_movs(s, ot);
3188 }
3189 break;
3190
3191 case 0xaa: /* stosS */
3192 case 0xab:
3193 if ((b & 1) == 0)
3194 ot = OT_BYTE;
3195 else
3196 ot = dflag ? OT_LONG : OT_WORD;
3197
3198 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3199 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3200 } else {
3201 gen_stos(s, ot);
3202 }
3203 break;
3204 case 0xac: /* lodsS */
3205 case 0xad:
3206 if ((b & 1) == 0)
3207 ot = OT_BYTE;
3208 else
3209 ot = dflag ? OT_LONG : OT_WORD;
3210 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3211 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3212 } else {
3213 gen_lods(s, ot);
3214 }
3215 break;
3216 case 0xae: /* scasS */
3217 case 0xaf:
3218 if ((b & 1) == 0)
3219 ot = OT_BYTE;
3220 else
3221 ot = dflag ? OT_LONG : OT_WORD;
3222 if (prefixes & PREFIX_REPNZ) {
3223 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3224 } else if (prefixes & PREFIX_REPZ) {
3225 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3226 } else {
3227 gen_scas(s, ot);
3228 s->cc_op = CC_OP_SUBB + ot;
3229 }
3230 break;
3231
3232 case 0xa6: /* cmpsS */
3233 case 0xa7:
3234 if ((b & 1) == 0)
3235 ot = OT_BYTE;
3236 else
3237 ot = dflag ? OT_LONG : OT_WORD;
3238 if (prefixes & PREFIX_REPNZ) {
3239 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3240 } else if (prefixes & PREFIX_REPZ) {
3241 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3242 } else {
3243 gen_cmps(s, ot);
3244 s->cc_op = CC_OP_SUBB + ot;
3245 }
3246 break;
3247 case 0x6c: /* insS */
3248 case 0x6d:
f115e911
FB		 3249 if ((b & 1) == 0)
3250 ot = OT_BYTE;
3251 else
3252 ot = dflag ? OT_LONG : OT_WORD;
3253 gen_check_io(s, ot, 1, pc_start - s->cs_base);
3254 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3255 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
2c0262af 3256 } else {
f115e911 3257 gen_ins(s, ot);
2c0262af
FB		 3258 }
3259 break;
3260 case 0x6e: /* outsS */
3261 case 0x6f:
f115e911
FB		 3262 if ((b & 1) == 0)
3263 ot = OT_BYTE;
3264 else
3265 ot = dflag ? OT_LONG : OT_WORD;
3266 gen_check_io(s, ot, 1, pc_start - s->cs_base);
3267 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3268 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
2c0262af 3269 } else {
f115e911 3270 gen_outs(s, ot);
2c0262af
FB		 3271 }
3272 break;
3273
3274 /************************/
3275 /* port I/O */
3276 case 0xe4:
3277 case 0xe5:
f115e911
FB		 3278 if ((b & 1) == 0)
3279 ot = OT_BYTE;
3280 else
3281 ot = dflag ? OT_LONG : OT_WORD;
3282 val = ldub_code(s->pc++);
3283 gen_op_movl_T0_im(val);
3284 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3285 gen_op_in[ot]();
3286 gen_op_mov_reg_T1[ot][R_EAX]();
2c0262af
FB		 3287 break;
3288 case 0xe6:
3289 case 0xe7:
f115e911
FB		 3290 if ((b & 1) == 0)
3291 ot = OT_BYTE;
3292 else
3293 ot = dflag ? OT_LONG : OT_WORD;
3294 val = ldub_code(s->pc++);
3295 gen_op_movl_T0_im(val);
3296 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3297 gen_op_mov_TN_reg[ot][1][R_EAX]();
3298 gen_op_out[ot]();
2c0262af
FB		 3299 break;
3300 case 0xec:
3301 case 0xed:
f115e911
FB		 3302 if ((b & 1) == 0)
3303 ot = OT_BYTE;
3304 else
3305 ot = dflag ? OT_LONG : OT_WORD;
3306 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3307 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3308 gen_op_in[ot]();
3309 gen_op_mov_reg_T1[ot][R_EAX]();
2c0262af
FB		 3310 break;
3311 case 0xee:
3312 case 0xef:
f115e911
FB		 3313 if ((b & 1) == 0)
3314 ot = OT_BYTE;
3315 else
3316 ot = dflag ? OT_LONG : OT_WORD;
3317 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3318 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3319 gen_op_mov_TN_reg[ot][1][R_EAX]();
3320 gen_op_out[ot]();
2c0262af
FB		 3321 break;
3322
3323 /************************/
3324 /* control */
3325 case 0xc2: /* ret im */
61382a50 3326 val = ldsw_code(s->pc);
2c0262af
FB		 3327 s->pc += 2;
3328 gen_pop_T0(s);
3329 gen_stack_update(s, val + (2 << s->dflag));
3330 if (s->dflag == 0)
3331 gen_op_andl_T0_ffff();
3332 gen_op_jmp_T0();
3333 gen_eob(s);
3334 break;
3335 case 0xc3: /* ret */
3336 gen_pop_T0(s);
3337 gen_pop_update(s);
3338 if (s->dflag == 0)
3339 gen_op_andl_T0_ffff();
3340 gen_op_jmp_T0();
3341 gen_eob(s);
3342 break;
3343 case 0xca: /* lret im */
61382a50 3344 val = ldsw_code(s->pc);
2c0262af
FB		 3345 s->pc += 2;
3346 do_lret:
3347 if (s->pe && !s->vm86) {
3348 if (s->cc_op != CC_OP_DYNAMIC)
3349 gen_op_set_cc_op(s->cc_op);
3350 gen_op_jmp_im(pc_start - s->cs_base);
3351 gen_op_lret_protected(s->dflag, val);
3352 } else {
3353 gen_stack_A0(s);
3354 /* pop offset */
3355 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3356 if (s->dflag == 0)
3357 gen_op_andl_T0_ffff();
3358 /* NOTE: keeping EIP updated is not a problem in case of
3359 exception */
3360 gen_op_jmp_T0();
3361 /* pop selector */
3362 gen_op_addl_A0_im(2 << s->dflag);
3363 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3364 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3365 /* add stack offset */
3366 gen_stack_update(s, val + (4 << s->dflag));
3367 }
3368 gen_eob(s);
3369 break;
3370 case 0xcb: /* lret */
3371 val = 0;
3372 goto do_lret;
3373 case 0xcf: /* iret */
3374 if (!s->pe) {
3375 /* real mode */
3376 gen_op_iret_real(s->dflag);
3377 s->cc_op = CC_OP_EFLAGS;
f115e911
FB		 3378 } else if (s->vm86) {
3379 if (s->iopl != 3) {
3380 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3381 } else {
3382 gen_op_iret_real(s->dflag);
3383 s->cc_op = CC_OP_EFLAGS;
3384 }
2c0262af
FB		 3385 } else {
3386 if (s->cc_op != CC_OP_DYNAMIC)
3387 gen_op_set_cc_op(s->cc_op);
3388 gen_op_jmp_im(pc_start - s->cs_base);
3389 gen_op_iret_protected(s->dflag);
3390 s->cc_op = CC_OP_EFLAGS;
3391 }
3392 gen_eob(s);
3393 break;
3394 case 0xe8: /* call im */
3395 {
3396 unsigned int next_eip;
3397 ot = dflag ? OT_LONG : OT_WORD;
3398 val = insn_get(s, ot);
3399 next_eip = s->pc - s->cs_base;
3400 val += next_eip;
3401 if (s->dflag == 0)
3402 val &= 0xffff;
3403 gen_op_movl_T0_im(next_eip);
3404 gen_push_T0(s);
3405 gen_jmp(s, val);
3406 }
3407 break;
3408 case 0x9a: /* lcall im */
3409 {
3410 unsigned int selector, offset;
3411
3412 ot = dflag ? OT_LONG : OT_WORD;
3413 offset = insn_get(s, ot);
3414 selector = insn_get(s, OT_WORD);
3415
3416 gen_op_movl_T0_im(selector);
3417 gen_op_movl_T1_im(offset);
3418 }
3419 goto do_lcall;
3420 case 0xe9: /* jmp */
3421 ot = dflag ? OT_LONG : OT_WORD;
3422 val = insn_get(s, ot);
3423 val += s->pc - s->cs_base;
3424 if (s->dflag == 0)
3425 val = val & 0xffff;
3426 gen_jmp(s, val);
3427 break;
3428 case 0xea: /* ljmp im */
3429 {
3430 unsigned int selector, offset;
3431
3432 ot = dflag ? OT_LONG : OT_WORD;
3433 offset = insn_get(s, ot);
3434 selector = insn_get(s, OT_WORD);
3435
3436 gen_op_movl_T0_im(selector);
3437 gen_op_movl_T1_im(offset);
3438 }
3439 goto do_ljmp;
3440 case 0xeb: /* jmp Jb */
3441 val = (int8_t)insn_get(s, OT_BYTE);
3442 val += s->pc - s->cs_base;
3443 if (s->dflag == 0)
3444 val = val & 0xffff;
3445 gen_jmp(s, val);
3446 break;
3447 case 0x70 ... 0x7f: /* jcc Jb */
3448 val = (int8_t)insn_get(s, OT_BYTE);
3449 goto do_jcc;
3450 case 0x180 ... 0x18f: /* jcc Jv */
3451 if (dflag) {
3452 val = insn_get(s, OT_LONG);
3453 } else {
3454 val = (int16_t)insn_get(s, OT_WORD);
3455 }
3456 do_jcc:
3457 next_eip = s->pc - s->cs_base;
3458 val += next_eip;
3459 if (s->dflag == 0)
3460 val &= 0xffff;
3461 gen_jcc(s, b, val, next_eip);
3462 break;
3463
3464 case 0x190 ... 0x19f: /* setcc Gv */
61382a50 3465 modrm = ldub_code(s->pc++);
2c0262af
FB		 3466 gen_setcc(s, b);
3467 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3468 break;
3469 case 0x140 ... 0x14f: /* cmov Gv, Ev */
3470 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3471 modrm = ldub_code(s->pc++);
2c0262af
FB		 3472 reg = (modrm >> 3) & 7;
3473 mod = (modrm >> 6) & 3;
3474 gen_setcc(s, b);
3475 if (mod != 3) {
3476 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3477 gen_op_ld_T1_A0[ot + s->mem_index]();
3478 } else {
3479 rm = modrm & 7;
3480 gen_op_mov_TN_reg[ot][1][rm]();
3481 }
3482 gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3483 break;
3484
3485 /************************/
3486 /* flags */
3487 case 0x9c: /* pushf */
3488 if (s->vm86 && s->iopl != 3) {
3489 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3490 } else {
3491 if (s->cc_op != CC_OP_DYNAMIC)
3492 gen_op_set_cc_op(s->cc_op);
3493 gen_op_movl_T0_eflags();
3494 gen_push_T0(s);
3495 }
3496 break;
3497 case 0x9d: /* popf */
3498 if (s->vm86 && s->iopl != 3) {
3499 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3500 } else {
3501 gen_pop_T0(s);
3502 if (s->cpl == 0) {
3503 if (s->dflag) {
3504 gen_op_movl_eflags_T0_cpl0();
3505 } else {
3506 gen_op_movw_eflags_T0_cpl0();
3507 }
3508 } else {
3509 if (s->dflag) {
3510 gen_op_movl_eflags_T0();
3511 } else {
3512 gen_op_movw_eflags_T0();
3513 }
3514 }
3515 gen_pop_update(s);
3516 s->cc_op = CC_OP_EFLAGS;
3517 /* abort translation because TF flag may change */
3518 gen_op_jmp_im(s->pc - s->cs_base);
3519 gen_eob(s);
3520 }
3521 break;
3522 case 0x9e: /* sahf */
3523 gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3524 if (s->cc_op != CC_OP_DYNAMIC)
3525 gen_op_set_cc_op(s->cc_op);
3526 gen_op_movb_eflags_T0();
3527 s->cc_op = CC_OP_EFLAGS;
3528 break;
3529 case 0x9f: /* lahf */
3530 if (s->cc_op != CC_OP_DYNAMIC)
3531 gen_op_set_cc_op(s->cc_op);
3532 gen_op_movl_T0_eflags();
3533 gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3534 break;
3535 case 0xf5: /* cmc */
3536 if (s->cc_op != CC_OP_DYNAMIC)
3537 gen_op_set_cc_op(s->cc_op);
3538 gen_op_cmc();
3539 s->cc_op = CC_OP_EFLAGS;
3540 break;
3541 case 0xf8: /* clc */
3542 if (s->cc_op != CC_OP_DYNAMIC)
3543 gen_op_set_cc_op(s->cc_op);
3544 gen_op_clc();
3545 s->cc_op = CC_OP_EFLAGS;
3546 break;
3547 case 0xf9: /* stc */
3548 if (s->cc_op != CC_OP_DYNAMIC)
3549 gen_op_set_cc_op(s->cc_op);
3550 gen_op_stc();
3551 s->cc_op = CC_OP_EFLAGS;
3552 break;
3553 case 0xfc: /* cld */
3554 gen_op_cld();
3555 break;
3556 case 0xfd: /* std */
3557 gen_op_std();
3558 break;
3559
3560 /************************/
3561 /* bit operations */
3562 case 0x1ba: /* bt/bts/btr/btc Gv, im */
3563 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3564 modrm = ldub_code(s->pc++);
2c0262af
FB		 3565 op = (modrm >> 3) & 7;
3566 mod = (modrm >> 6) & 3;
3567 rm = modrm & 7;
3568 if (mod != 3) {
3569 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3570 gen_op_ld_T0_A0[ot + s->mem_index]();
3571 } else {
3572 gen_op_mov_TN_reg[ot][0][rm]();
3573 }
3574 /* load shift */
61382a50 3575 val = ldub_code(s->pc++);
2c0262af
FB		 3576 gen_op_movl_T1_im(val);
3577 if (op < 4)
3578 goto illegal_op;
3579 op -= 4;
3580 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3581 s->cc_op = CC_OP_SARB + ot;
3582 if (op != 0) {
3583 if (mod != 3)
3584 gen_op_st_T0_A0[ot + s->mem_index]();
3585 else
3586 gen_op_mov_reg_T0[ot][rm]();
3587 gen_op_update_bt_cc();
3588 }
3589 break;
3590 case 0x1a3: /* bt Gv, Ev */
3591 op = 0;
3592 goto do_btx;
3593 case 0x1ab: /* bts */
3594 op = 1;
3595 goto do_btx;
3596 case 0x1b3: /* btr */
3597 op = 2;
3598 goto do_btx;
3599 case 0x1bb: /* btc */
3600 op = 3;
3601 do_btx:
3602 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3603 modrm = ldub_code(s->pc++);
2c0262af
FB		 3604 reg = (modrm >> 3) & 7;
3605 mod = (modrm >> 6) & 3;
3606 rm = modrm & 7;
3607 gen_op_mov_TN_reg[OT_LONG][1][reg]();
3608 if (mod != 3) {
3609 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3610 /* specific case: we need to add a displacement */
3611 if (ot == OT_WORD)
3612 gen_op_add_bitw_A0_T1();
3613 else
3614 gen_op_add_bitl_A0_T1();
3615 gen_op_ld_T0_A0[ot + s->mem_index]();
3616 } else {
3617 gen_op_mov_TN_reg[ot][0][rm]();
3618 }
3619 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3620 s->cc_op = CC_OP_SARB + ot;
3621 if (op != 0) {
3622 if (mod != 3)
3623 gen_op_st_T0_A0[ot + s->mem_index]();
3624 else
3625 gen_op_mov_reg_T0[ot][rm]();
3626 gen_op_update_bt_cc();
3627 }
3628 break;
3629 case 0x1bc: /* bsf */
3630 case 0x1bd: /* bsr */
3631 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3632 modrm = ldub_code(s->pc++);
2c0262af
FB		 3633 reg = (modrm >> 3) & 7;
3634 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3635 gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
3636 /* NOTE: we always write back the result. Intel doc says it is
3637 undefined if T0 == 0 */
3638 gen_op_mov_reg_T0[ot][reg]();
3639 s->cc_op = CC_OP_LOGICB + ot;
3640 break;
3641 /************************/
3642 /* bcd */
3643 case 0x27: /* daa */
3644 if (s->cc_op != CC_OP_DYNAMIC)
3645 gen_op_set_cc_op(s->cc_op);
3646 gen_op_daa();
3647 s->cc_op = CC_OP_EFLAGS;
3648 break;
3649 case 0x2f: /* das */
3650 if (s->cc_op != CC_OP_DYNAMIC)
3651 gen_op_set_cc_op(s->cc_op);
3652 gen_op_das();
3653 s->cc_op = CC_OP_EFLAGS;
3654 break;
3655 case 0x37: /* aaa */
3656 if (s->cc_op != CC_OP_DYNAMIC)
3657 gen_op_set_cc_op(s->cc_op);
3658 gen_op_aaa();
3659 s->cc_op = CC_OP_EFLAGS;
3660 break;
3661 case 0x3f: /* aas */
3662 if (s->cc_op != CC_OP_DYNAMIC)
3663 gen_op_set_cc_op(s->cc_op);
3664 gen_op_aas();
3665 s->cc_op = CC_OP_EFLAGS;
3666 break;
3667 case 0xd4: /* aam */
61382a50 3668 val = ldub_code(s->pc++);
2c0262af
FB		 3669 gen_op_aam(val);
3670 s->cc_op = CC_OP_LOGICB;
3671 break;
3672 case 0xd5: /* aad */
61382a50 3673 val = ldub_code(s->pc++);
2c0262af
FB		 3674 gen_op_aad(val);
3675 s->cc_op = CC_OP_LOGICB;
3676 break;
3677 /************************/
3678 /* misc */
3679 case 0x90: /* nop */
3680 break;
3681 case 0x9b: /* fwait */
3682 break;
3683 case 0xcc: /* int3 */
3684 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
3685 break;
3686 case 0xcd: /* int N */
61382a50 3687 val = ldub_code(s->pc++);
f115e911 3688 if (s->vm86 && s->iopl != 3) {
2c0262af 3689 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
f115e911
FB		 3690 } else {
3691 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
3692 }
2c0262af
FB		 3693 break;
3694 case 0xce: /* into */
3695 if (s->cc_op != CC_OP_DYNAMIC)
3696 gen_op_set_cc_op(s->cc_op);
3697 gen_op_into(s->pc - s->cs_base);
3698 break;
3699 case 0xf1: /* icebp (undocumented, exits to external debugger) */
3700 gen_debug(s, pc_start - s->cs_base);
3701 break;
3702 case 0xfa: /* cli */
3703 if (!s->vm86) {
3704 if (s->cpl <= s->iopl) {
3705 gen_op_cli();
3706 } else {
3707 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3708 }
3709 } else {
3710 if (s->iopl == 3) {
3711 gen_op_cli();
3712 } else {
3713 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3714 }
3715 }
3716 break;
3717 case 0xfb: /* sti */
3718 if (!s->vm86) {
3719 if (s->cpl <= s->iopl) {
3720 gen_sti:
3721 gen_op_sti();
3722 /* interruptions are enabled only the first insn after sti */
3723 gen_op_set_inhibit_irq();
3724 /* give a chance to handle pending irqs */
3725 gen_op_jmp_im(s->pc - s->cs_base);
3726 gen_eob(s);
3727 } else {
3728 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3729 }
3730 } else {
3731 if (s->iopl == 3) {
3732 goto gen_sti;
3733 } else {
3734 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3735 }
3736 }
3737 break;
3738 case 0x62: /* bound */
3739 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3740 modrm = ldub_code(s->pc++);
2c0262af
FB		 3741 reg = (modrm >> 3) & 7;
3742 mod = (modrm >> 6) & 3;
3743 if (mod == 3)
3744 goto illegal_op;
3745 gen_op_mov_reg_T0[ot][reg]();
3746 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3747 if (ot == OT_WORD)
3748 gen_op_boundw(pc_start - s->cs_base);
3749 else
3750 gen_op_boundl(pc_start - s->cs_base);
3751 break;
3752 case 0x1c8 ... 0x1cf: /* bswap reg */
3753 reg = b & 7;
3754 gen_op_mov_TN_reg[OT_LONG][0][reg]();
3755 gen_op_bswapl_T0();
3756 gen_op_mov_reg_T0[OT_LONG][reg]();
3757 break;
3758 case 0xd6: /* salc */
3759 if (s->cc_op != CC_OP_DYNAMIC)
3760 gen_op_set_cc_op(s->cc_op);
3761 gen_op_salc();
3762 break;
3763 case 0xe0: /* loopnz */
3764 case 0xe1: /* loopz */
3765 if (s->cc_op != CC_OP_DYNAMIC)
3766 gen_op_set_cc_op(s->cc_op);
3767 /* FALL THRU */
3768 case 0xe2: /* loop */
3769 case 0xe3: /* jecxz */
3770 val = (int8_t)insn_get(s, OT_BYTE);
3771 next_eip = s->pc - s->cs_base;
3772 val += next_eip;
3773 if (s->dflag == 0)
3774 val &= 0xffff;
3775 gen_op_loop[s->aflag][b & 3](val, next_eip);
3776 gen_eob(s);
3777 break;
3778 case 0x130: /* wrmsr */
3779 case 0x132: /* rdmsr */
3780 if (s->cpl != 0) {
3781 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3782 } else {
3783 if (b & 2)
3784 gen_op_rdmsr();
3785 else
3786 gen_op_wrmsr();
3787 }
3788 break;
3789 case 0x131: /* rdtsc */
3790 gen_op_rdtsc();
3791 break;
3792 case 0x1a2: /* cpuid */
3793 gen_op_cpuid();
3794 break;
3795 case 0xf4: /* hlt */
3796 if (s->cpl != 0) {
3797 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3798 } else {
3799 if (s->cc_op != CC_OP_DYNAMIC)
3800 gen_op_set_cc_op(s->cc_op);
3801 gen_op_jmp_im(s->pc - s->cs_base);
3802 gen_op_hlt();
3803 s->is_jmp = 3;
3804 }
3805 break;
3806 case 0x100:
61382a50 3807 modrm = ldub_code(s->pc++);
2c0262af
FB		 3808 mod = (modrm >> 6) & 3;
3809 op = (modrm >> 3) & 7;
3810 switch(op) {
3811 case 0: /* sldt */
f115e911
FB		 3812 if (!s->pe || s->vm86)
3813 goto illegal_op;
2c0262af
FB		 3814 gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
3815 ot = OT_WORD;
3816 if (mod == 3)
3817 ot += s->dflag;
3818 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3819 break;
3820 case 2: /* lldt */
f115e911
FB		 3821 if (!s->pe || s->vm86)
3822 goto illegal_op;
2c0262af
FB		 3823 if (s->cpl != 0) {
3824 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3825 } else {
3826 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3827 gen_op_jmp_im(pc_start - s->cs_base);
3828 gen_op_lldt_T0();
3829 }
3830 break;
3831 case 1: /* str */
f115e911
FB		 3832 if (!s->pe || s->vm86)
3833 goto illegal_op;
2c0262af
FB		 3834 gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
3835 ot = OT_WORD;
3836 if (mod == 3)
3837 ot += s->dflag;
3838 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3839 break;
3840 case 3: /* ltr */
f115e911
FB		 3841 if (!s->pe || s->vm86)
3842 goto illegal_op;
2c0262af
FB		 3843 if (s->cpl != 0) {
3844 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3845 } else {
3846 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3847 gen_op_jmp_im(pc_start - s->cs_base);
3848 gen_op_ltr_T0();
3849 }
3850 break;
3851 case 4: /* verr */
3852 case 5: /* verw */
f115e911
FB		 3853 if (!s->pe || s->vm86)
3854 goto illegal_op;
3855 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3856 if (s->cc_op != CC_OP_DYNAMIC)
3857 gen_op_set_cc_op(s->cc_op);
3858 if (op == 4)
3859 gen_op_verr();
3860 else
3861 gen_op_verw();
3862 s->cc_op = CC_OP_EFLAGS;
3863 break;
2c0262af
FB		 3864 default:
3865 goto illegal_op;
3866 }
3867 break;
3868 case 0x101:
61382a50 3869 modrm = ldub_code(s->pc++);
2c0262af
FB		 3870 mod = (modrm >> 6) & 3;
3871 op = (modrm >> 3) & 7;
3872 switch(op) {
3873 case 0: /* sgdt */
3874 case 1: /* sidt */
3875 if (mod == 3)
3876 goto illegal_op;
3877 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3878 if (op == 0)
3879 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
3880 else
3881 gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
3882 gen_op_st_T0_A0[OT_WORD + s->mem_index]();
3883 gen_op_addl_A0_im(2);
3884 if (op == 0)
3885 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
3886 else
3887 gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
3888 if (!s->dflag)
3889 gen_op_andl_T0_im(0xffffff);
3890 gen_op_st_T0_A0[OT_LONG + s->mem_index]();
3891 break;
3892 case 2: /* lgdt */
3893 case 3: /* lidt */
3894 if (mod == 3)
3895 goto illegal_op;
3896 if (s->cpl != 0) {
3897 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3898 } else {
3899 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3900 gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
3901 gen_op_addl_A0_im(2);
3902 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
3903 if (!s->dflag)
3904 gen_op_andl_T0_im(0xffffff);
3905 if (op == 2) {
3906 gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
3907 gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
3908 } else {
3909 gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
3910 gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
3911 }
3912 }
3913 break;
3914 case 4: /* smsw */
3915 gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
3916 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
3917 break;
3918 case 6: /* lmsw */
3919 if (s->cpl != 0) {
3920 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3921 } else {
3922 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3923 gen_op_lmsw_T0();
3924 }
3925 break;
3926 case 7: /* invlpg */
3927 if (s->cpl != 0) {
3928 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3929 } else {
3930 if (mod == 3)
3931 goto illegal_op;
3932 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3933 gen_op_invlpg_A0();
3934 }
3935 break;
3936 default:
3937 goto illegal_op;
3938 }
3939 break;
f115e911
FB		 3940 case 0x63: /* arpl */
3941 if (!s->pe || s->vm86)
3942 goto illegal_op;
3943 ot = dflag ? OT_LONG : OT_WORD;
3944 modrm = ldub_code(s->pc++);
3945 reg = (modrm >> 3) & 7;
3946 mod = (modrm >> 6) & 3;
3947 rm = modrm & 7;
3948 if (mod != 3) {
3949 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3950 gen_op_ld_T0_A0[ot + s->mem_index]();
3951 } else {
3952 gen_op_mov_TN_reg[ot][0][rm]();
3953 }
3954 if (s->cc_op != CC_OP_DYNAMIC)
3955 gen_op_set_cc_op(s->cc_op);
3956 gen_op_arpl();
3957 s->cc_op = CC_OP_EFLAGS;
3958 if (mod != 3) {
3959 gen_op_st_T0_A0[ot + s->mem_index]();
3960 } else {
3961 gen_op_mov_reg_T0[ot][rm]();
3962 }
3963 gen_op_arpl_update();
3964 break;
2c0262af
FB		 3965 case 0x102: /* lar */
3966 case 0x103: /* lsl */
3967 if (!s->pe || s->vm86)
3968 goto illegal_op;
3969 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3970 modrm = ldub_code(s->pc++);
2c0262af
FB		 3971 reg = (modrm >> 3) & 7;
3972 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3973 gen_op_mov_TN_reg[ot][1][reg]();
3974 if (s->cc_op != CC_OP_DYNAMIC)
3975 gen_op_set_cc_op(s->cc_op);
3976 if (b == 0x102)
3977 gen_op_lar();
3978 else
3979 gen_op_lsl();
3980 s->cc_op = CC_OP_EFLAGS;
3981 gen_op_mov_reg_T1[ot][reg]();
3982 break;
3983 case 0x118:
61382a50 3984 modrm = ldub_code(s->pc++);
2c0262af
FB		 3985 mod = (modrm >> 6) & 3;
3986 op = (modrm >> 3) & 7;
3987 switch(op) {
3988 case 0: /* prefetchnta */
3989 case 1: /* prefetchnt0 */
3990 case 2: /* prefetchnt0 */
3991 case 3: /* prefetchnt0 */
3992 if (mod == 3)
3993 goto illegal_op;
3994 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3995 /* nothing more to do */
3996 break;
3997 default:
3998 goto illegal_op;
3999 }
4000 break;
4001 case 0x120: /* mov reg, crN */
4002 case 0x122: /* mov crN, reg */
4003 if (s->cpl != 0) {
4004 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4005 } else {
61382a50 4006 modrm = ldub_code(s->pc++);
2c0262af
FB		 4007 if ((modrm & 0xc0) != 0xc0)
4008 goto illegal_op;
4009 rm = modrm & 7;
4010 reg = (modrm >> 3) & 7;
4011 switch(reg) {
4012 case 0:
4013 case 2:
4014 case 3:
4015 case 4:
4016 if (b & 2) {
4017 gen_op_mov_TN_reg[OT_LONG][0][rm]();
4018 gen_op_movl_crN_T0(reg);
4019 gen_op_jmp_im(s->pc - s->cs_base);
4020 gen_eob(s);
4021 } else {
4022 gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
4023 gen_op_mov_reg_T0[OT_LONG][rm]();
4024 }
4025 break;
4026 default:
4027 goto illegal_op;
4028 }
4029 }
4030 break;
4031 case 0x121: /* mov reg, drN */
4032 case 0x123: /* mov drN, reg */
4033 if (s->cpl != 0) {
4034 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4035 } else {
61382a50 4036 modrm = ldub_code(s->pc++);
2c0262af
FB		 4037 if ((modrm & 0xc0) != 0xc0)
4038 goto illegal_op;
4039 rm = modrm & 7;
4040 reg = (modrm >> 3) & 7;
4041 /* XXX: do it dynamically with CR4.DE bit */
4042 if (reg == 4 || reg == 5)
4043 goto illegal_op;
4044 if (b & 2) {
4045 gen_op_mov_TN_reg[OT_LONG][0][rm]();
4046 gen_op_movl_drN_T0(reg);
4047 gen_op_jmp_im(s->pc - s->cs_base);
4048 gen_eob(s);
4049 } else {
4050 gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
4051 gen_op_mov_reg_T0[OT_LONG][rm]();
4052 }
4053 }
4054 break;
4055 case 0x106: /* clts */
4056 if (s->cpl != 0) {
4057 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4058 } else {
4059 gen_op_clts();
4060 }
4061 break;
4062 default:
4063 goto illegal_op;
4064 }
4065 /* lock generation */
4066 if (s->prefix & PREFIX_LOCK)
4067 gen_op_unlock();
4068 return s->pc;
4069 illegal_op:
4070 /* XXX: ensure that no lock was generated */
4071 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
4072 return s->pc;
4073}
4074
4075#define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
4076#define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
4077
4078/* flags read by an operation */
4079static uint16_t opc_read_flags[NB_OPS] = {
4080 [INDEX_op_aas] = CC_A,
4081 [INDEX_op_aaa] = CC_A,
4082 [INDEX_op_das] = CC_A | CC_C,
4083 [INDEX_op_daa] = CC_A | CC_C,
4084
4085 [INDEX_op_adcb_T0_T1_cc] = CC_C,
4086 [INDEX_op_adcw_T0_T1_cc] = CC_C,
4087 [INDEX_op_adcl_T0_T1_cc] = CC_C,
4088 [INDEX_op_sbbb_T0_T1_cc] = CC_C,
4089 [INDEX_op_sbbw_T0_T1_cc] = CC_C,
4090 [INDEX_op_sbbl_T0_T1_cc] = CC_C,
4091
4092 [INDEX_op_adcb_mem_T0_T1_cc] = CC_C,
4093 [INDEX_op_adcw_mem_T0_T1_cc] = CC_C,
4094 [INDEX_op_adcl_mem_T0_T1_cc] = CC_C,
4095 [INDEX_op_sbbb_mem_T0_T1_cc] = CC_C,
4096 [INDEX_op_sbbw_mem_T0_T1_cc] = CC_C,
4097 [INDEX_op_sbbl_mem_T0_T1_cc] = CC_C,
4098
4099 /* subtle: due to the incl/decl implementation, C is used */
4100 [INDEX_op_update_inc_cc] = CC_C,
4101
4102 [INDEX_op_into] = CC_O,
4103
4104 [INDEX_op_jb_subb] = CC_C,
4105 [INDEX_op_jb_subw] = CC_C,
4106 [INDEX_op_jb_subl] = CC_C,
4107
4108 [INDEX_op_jz_subb] = CC_Z,
4109 [INDEX_op_jz_subw] = CC_Z,
4110 [INDEX_op_jz_subl] = CC_Z,
4111
4112 [INDEX_op_jbe_subb] = CC_Z | CC_C,
4113 [INDEX_op_jbe_subw] = CC_Z | CC_C,
4114 [INDEX_op_jbe_subl] = CC_Z | CC_C,
4115
4116 [INDEX_op_js_subb] = CC_S,
4117 [INDEX_op_js_subw] = CC_S,
4118 [INDEX_op_js_subl] = CC_S,
4119
4120 [INDEX_op_jl_subb] = CC_O | CC_S,
4121 [INDEX_op_jl_subw] = CC_O | CC_S,
4122 [INDEX_op_jl_subl] = CC_O | CC_S,
4123
4124 [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
4125 [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
4126 [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
4127
4128 [INDEX_op_loopnzw] = CC_Z,
4129 [INDEX_op_loopnzl] = CC_Z,
4130 [INDEX_op_loopzw] = CC_Z,
4131 [INDEX_op_loopzl] = CC_Z,
4132
4133 [INDEX_op_seto_T0_cc] = CC_O,
4134 [INDEX_op_setb_T0_cc] = CC_C,
4135 [INDEX_op_setz_T0_cc] = CC_Z,
4136 [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
4137 [INDEX_op_sets_T0_cc] = CC_S,
4138 [INDEX_op_setp_T0_cc] = CC_P,
4139 [INDEX_op_setl_T0_cc] = CC_O | CC_S,
4140 [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
4141
4142 [INDEX_op_setb_T0_subb] = CC_C,
4143 [INDEX_op_setb_T0_subw] = CC_C,
4144 [INDEX_op_setb_T0_subl] = CC_C,
4145
4146 [INDEX_op_setz_T0_subb] = CC_Z,
4147 [INDEX_op_setz_T0_subw] = CC_Z,
4148 [INDEX_op_setz_T0_subl] = CC_Z,
4149
4150 [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
4151 [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
4152 [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
4153
4154 [INDEX_op_sets_T0_subb] = CC_S,
4155 [INDEX_op_sets_T0_subw] = CC_S,
4156 [INDEX_op_sets_T0_subl] = CC_S,
4157
4158 [INDEX_op_setl_T0_subb] = CC_O | CC_S,
4159 [INDEX_op_setl_T0_subw] = CC_O | CC_S,
4160 [INDEX_op_setl_T0_subl] = CC_O | CC_S,
4161
4162 [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
4163 [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
4164 [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
4165
4166 [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
4167 [INDEX_op_cmc] = CC_C,
4168 [INDEX_op_salc] = CC_C,
4169
4170 [INDEX_op_rclb_T0_T1_cc] = CC_C,
4171 [INDEX_op_rclw_T0_T1_cc] = CC_C,
4172 [INDEX_op_rcll_T0_T1_cc] = CC_C,
4173 [INDEX_op_rcrb_T0_T1_cc] = CC_C,
4174 [INDEX_op_rcrw_T0_T1_cc] = CC_C,
4175 [INDEX_op_rcrl_T0_T1_cc] = CC_C,
4176
4177 [INDEX_op_rclb_mem_T0_T1_cc] = CC_C,
4178 [INDEX_op_rclw_mem_T0_T1_cc] = CC_C,
4179 [INDEX_op_rcll_mem_T0_T1_cc] = CC_C,
4180 [INDEX_op_rcrb_mem_T0_T1_cc] = CC_C,
4181 [INDEX_op_rcrw_mem_T0_T1_cc] = CC_C,
4182 [INDEX_op_rcrl_mem_T0_T1_cc] = CC_C,
4183};
4184
4185/* flags written by an operation */
4186static uint16_t opc_write_flags[NB_OPS] = {
4187 [INDEX_op_update2_cc] = CC_OSZAPC,
4188 [INDEX_op_update1_cc] = CC_OSZAPC,
4189 [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
4190 [INDEX_op_update_neg_cc] = CC_OSZAPC,
4191 /* subtle: due to the incl/decl implementation, C is used */
4192 [INDEX_op_update_inc_cc] = CC_OSZAPC,
4193 [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
4194
4195 [INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,
4196 [INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,
4197 [INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,
4198 [INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,
4199 [INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,
4200 [INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,
4201
4202 [INDEX_op_adcb_mem_T0_T1_cc] = CC_OSZAPC,
4203 [INDEX_op_adcw_mem_T0_T1_cc] = CC_OSZAPC,
4204 [INDEX_op_adcl_mem_T0_T1_cc] = CC_OSZAPC,
4205 [INDEX_op_sbbb_mem_T0_T1_cc] = CC_OSZAPC,
4206 [INDEX_op_sbbw_mem_T0_T1_cc] = CC_OSZAPC,
4207 [INDEX_op_sbbl_mem_T0_T1_cc] = CC_OSZAPC,
4208
4209 [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
4210 [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
4211 [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
4212 [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
4213 [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
4214 [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
4215 [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
4216 [INDEX_op_imull_T0_T1] = CC_OSZAPC,
4217
4218 /* bcd */
4219 [INDEX_op_aam] = CC_OSZAPC,
4220 [INDEX_op_aad] = CC_OSZAPC,
4221 [INDEX_op_aas] = CC_OSZAPC,
4222 [INDEX_op_aaa] = CC_OSZAPC,
4223 [INDEX_op_das] = CC_OSZAPC,
4224 [INDEX_op_daa] = CC_OSZAPC,
4225
4226 [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
4227 [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
4228 [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
4229 [INDEX_op_clc] = CC_C,
4230 [INDEX_op_stc] = CC_C,
4231 [INDEX_op_cmc] = CC_C,
4232
4233 [INDEX_op_rolb_T0_T1_cc] = CC_O | CC_C,
4234 [INDEX_op_rolw_T0_T1_cc] = CC_O | CC_C,
4235 [INDEX_op_roll_T0_T1_cc] = CC_O | CC_C,
4236 [INDEX_op_rorb_T0_T1_cc] = CC_O | CC_C,
4237 [INDEX_op_rorw_T0_T1_cc] = CC_O | CC_C,
4238 [INDEX_op_rorl_T0_T1_cc] = CC_O | CC_C,
4239
4240 [INDEX_op_rclb_T0_T1_cc] = CC_O | CC_C,
4241 [INDEX_op_rclw_T0_T1_cc] = CC_O | CC_C,
4242 [INDEX_op_rcll_T0_T1_cc] = CC_O | CC_C,
4243 [INDEX_op_rcrb_T0_T1_cc] = CC_O | CC_C,
4244 [INDEX_op_rcrw_T0_T1_cc] = CC_O | CC_C,
4245 [INDEX_op_rcrl_T0_T1_cc] = CC_O | CC_C,
4246
4247 [INDEX_op_shlb_T0_T1_cc] = CC_OSZAPC,
4248 [INDEX_op_shlw_T0_T1_cc] = CC_OSZAPC,
4249 [INDEX_op_shll_T0_T1_cc] = CC_OSZAPC,
4250
4251 [INDEX_op_shrb_T0_T1_cc] = CC_OSZAPC,
4252 [INDEX_op_shrw_T0_T1_cc] = CC_OSZAPC,
4253 [INDEX_op_shrl_T0_T1_cc] = CC_OSZAPC,
4254
4255 [INDEX_op_sarb_T0_T1_cc] = CC_OSZAPC,
4256 [INDEX_op_sarw_T0_T1_cc] = CC_OSZAPC,
4257 [INDEX_op_sarl_T0_T1_cc] = CC_OSZAPC,
4258
4259 [INDEX_op_shldw_T0_T1_ECX_cc] = CC_OSZAPC,
4260 [INDEX_op_shldl_T0_T1_ECX_cc] = CC_OSZAPC,
4261 [INDEX_op_shldw_T0_T1_im_cc] = CC_OSZAPC,
4262 [INDEX_op_shldl_T0_T1_im_cc] = CC_OSZAPC,
4263
4264 [INDEX_op_shrdw_T0_T1_ECX_cc] = CC_OSZAPC,
4265 [INDEX_op_shrdl_T0_T1_ECX_cc] = CC_OSZAPC,
4266 [INDEX_op_shrdw_T0_T1_im_cc] = CC_OSZAPC,
4267 [INDEX_op_shrdl_T0_T1_im_cc] = CC_OSZAPC,
4268
4269 [INDEX_op_rolb_mem_T0_T1_cc] = CC_O | CC_C,
4270 [INDEX_op_rolw_mem_T0_T1_cc] = CC_O | CC_C,
4271 [INDEX_op_roll_mem_T0_T1_cc] = CC_O | CC_C,
4272 [INDEX_op_rorb_mem_T0_T1_cc] = CC_O | CC_C,
4273 [INDEX_op_rorw_mem_T0_T1_cc] = CC_O | CC_C,
4274 [INDEX_op_rorl_mem_T0_T1_cc] = CC_O | CC_C,
4275
4276 [INDEX_op_rclb_mem_T0_T1_cc] = CC_O | CC_C,
4277 [INDEX_op_rclw_mem_T0_T1_cc] = CC_O | CC_C,
4278 [INDEX_op_rcll_mem_T0_T1_cc] = CC_O | CC_C,
4279 [INDEX_op_rcrb_mem_T0_T1_cc] = CC_O | CC_C,
4280 [INDEX_op_rcrw_mem_T0_T1_cc] = CC_O | CC_C,
4281 [INDEX_op_rcrl_mem_T0_T1_cc] = CC_O | CC_C,
4282
4283 [INDEX_op_shlb_mem_T0_T1_cc] = CC_OSZAPC,
4284 [INDEX_op_shlw_mem_T0_T1_cc] = CC_OSZAPC,
4285 [INDEX_op_shll_mem_T0_T1_cc] = CC_OSZAPC,
4286
4287 [INDEX_op_shrb_mem_T0_T1_cc] = CC_OSZAPC,
4288 [INDEX_op_shrw_mem_T0_T1_cc] = CC_OSZAPC,
4289 [INDEX_op_shrl_mem_T0_T1_cc] = CC_OSZAPC,
4290
4291 [INDEX_op_sarb_mem_T0_T1_cc] = CC_OSZAPC,
4292 [INDEX_op_sarw_mem_T0_T1_cc] = CC_OSZAPC,
4293 [INDEX_op_sarl_mem_T0_T1_cc] = CC_OSZAPC,
4294
4295 [INDEX_op_shldw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4296 [INDEX_op_shldl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4297 [INDEX_op_shldw_mem_T0_T1_im_cc] = CC_OSZAPC,
4298 [INDEX_op_shldl_mem_T0_T1_im_cc] = CC_OSZAPC,
4299
4300 [INDEX_op_shrdw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4301 [INDEX_op_shrdl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4302 [INDEX_op_shrdw_mem_T0_T1_im_cc] = CC_OSZAPC,
4303 [INDEX_op_shrdl_mem_T0_T1_im_cc] = CC_OSZAPC,
4304
4305 [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
4306 [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
4307 [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
4308 [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
4309 [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
4310 [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
4311 [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
4312 [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
4313
4314 [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
4315 [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
4316 [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
4317 [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
4318
4319 [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
4320 [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
4321 [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
4322
4323 [INDEX_op_cmpxchgb_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4324 [INDEX_op_cmpxchgw_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4325 [INDEX_op_cmpxchgl_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4326
4327 [INDEX_op_cmpxchg8b] = CC_Z,
4328 [INDEX_op_lar] = CC_Z,
4329 [INDEX_op_lsl] = CC_Z,
4330 [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4331 [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4332};
4333
4334/* simpler form of an operation if no flags need to be generated */
4335static uint16_t opc_simpler[NB_OPS] = {
4336 [INDEX_op_update2_cc] = INDEX_op_nop,
4337 [INDEX_op_update1_cc] = INDEX_op_nop,
4338 [INDEX_op_update_neg_cc] = INDEX_op_nop,
4339#if 0
4340 /* broken: CC_OP logic must be rewritten */
4341 [INDEX_op_update_inc_cc] = INDEX_op_nop,
4342#endif
4343 [INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,
4344 [INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,
4345 [INDEX_op_roll_T0_T1_cc] = INDEX_op_roll_T0_T1,
4346
4347 [INDEX_op_rorb_T0_T1_cc] = INDEX_op_rorb_T0_T1,
4348 [INDEX_op_rorw_T0_T1_cc] = INDEX_op_rorw_T0_T1,
4349 [INDEX_op_rorl_T0_T1_cc] = INDEX_op_rorl_T0_T1,
4350
4351 [INDEX_op_rolb_mem_T0_T1_cc] = INDEX_op_rolb_mem_T0_T1,
4352 [INDEX_op_rolw_mem_T0_T1_cc] = INDEX_op_rolw_mem_T0_T1,
4353 [INDEX_op_roll_mem_T0_T1_cc] = INDEX_op_roll_mem_T0_T1,
4354
4355 [INDEX_op_rorb_mem_T0_T1_cc] = INDEX_op_rorb_mem_T0_T1,
4356 [INDEX_op_rorw_mem_T0_T1_cc] = INDEX_op_rorw_mem_T0_T1,
4357 [INDEX_op_rorl_mem_T0_T1_cc] = INDEX_op_rorl_mem_T0_T1,
4358
4359 [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
4360 [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
4361 [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
4362
4363 [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
4364 [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
4365 [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
4366
4367 [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
4368 [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
4369 [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
4370};
4371
4372void optimize_flags_init(void)
4373{
4374 int i;
4375 /* put default values in arrays */
4376 for(i = 0; i < NB_OPS; i++) {
4377 if (opc_simpler[i] == 0)
4378 opc_simpler[i] = i;
4379 }
4380}
4381
4382/* CPU flags computation optimization: we move backward thru the
4383 generated code to see which flags are needed. The operation is
4384 modified if suitable */
4385static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
4386{
4387 uint16_t *opc_ptr;
4388 int live_flags, write_flags, op;
4389
4390 opc_ptr = opc_buf + opc_buf_len;
4391 /* live_flags contains the flags needed by the next instructions
4392 in the code. At the end of the bloc, we consider that all the
4393 flags are live. */
4394 live_flags = CC_OSZAPC;
4395 while (opc_ptr > opc_buf) {
4396 op = *--opc_ptr;
4397 /* if none of the flags written by the instruction is used,
4398 then we can try to find a simpler instruction */
4399 write_flags = opc_write_flags[op];
4400 if ((live_flags & write_flags) == 0) {
4401 *opc_ptr = opc_simpler[op];
4402 }
4403 /* compute the live flags before the instruction */
4404 live_flags &= ~write_flags;
4405 live_flags |= opc_read_flags[op];
4406 }
4407}
4408
4409/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
4410 basic block 'tb'. If search_pc is TRUE, also generate PC
4411 information for each intermediate instruction. */
4412static inline int gen_intermediate_code_internal(CPUState *env,
4413 TranslationBlock *tb,
4414 int search_pc)
4415{
4416 DisasContext dc1, *dc = &dc1;
4417 uint8_t *pc_ptr;
4418 uint16_t *gen_opc_end;
4419 int flags, j, lj;
4420 uint8_t *pc_start;
4421 uint8_t *cs_base;
4422
4423 /* generate intermediate code */
4424 pc_start = (uint8_t *)tb->pc;
4425 cs_base = (uint8_t *)tb->cs_base;
4426 flags = tb->flags;
4427
4428 dc->pe = env->cr[0] & CR0_PE_MASK;
4429 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
4430 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
4431 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
4432 dc->f_st = 0;
4433 dc->vm86 = (flags >> VM_SHIFT) & 1;
4434 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
4435 dc->iopl = (flags >> IOPL_SHIFT) & 3;
4436 dc->tf = (flags >> TF_SHIFT) & 1;
34865134 4437 dc->singlestep_enabled = env->singlestep_enabled;
2c0262af
FB		 4438 dc->cc_op = CC_OP_DYNAMIC;
4439 dc->cs_base = cs_base;
4440 dc->tb = tb;
4441 dc->popl_esp_hack = 0;
4442 /* select memory access functions */
4443 dc->mem_index = 0;
4444 if (flags & HF_SOFTMMU_MASK) {
4445 if (dc->cpl == 3)
4446 dc->mem_index = 6;
4447 else
4448 dc->mem_index = 3;
4449 }
4450 dc->jmp_opt = !(dc->tf || env->singlestep_enabled
415fa2ea 4451#ifndef CONFIG_SOFTMMU
2c0262af
FB		 4452 || (flags & HF_SOFTMMU_MASK)
4453#endif
4454 );
4455 gen_opc_ptr = gen_opc_buf;
4456 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4457 gen_opparam_ptr = gen_opparam_buf;
4458
4459 dc->is_jmp = DISAS_NEXT;
4460 pc_ptr = pc_start;
4461 lj = -1;
4462
4463 /* if irq were inhibited for the next instruction, we can disable
4464 them here as it is simpler (otherwise jumps would have to
4465 handled as special case) */
4466 if (flags & HF_INHIBIT_IRQ_MASK) {
4467 gen_op_reset_inhibit_irq();
4468 }
4469 for(;;) {
4470 if (env->nb_breakpoints > 0) {
4471 for(j = 0; j < env->nb_breakpoints; j++) {
4472 if (env->breakpoints[j] == (unsigned long)pc_ptr) {
4473 gen_debug(dc, pc_ptr - dc->cs_base);
4474 break;
4475 }
4476 }
4477 }
4478 if (search_pc) {
4479 j = gen_opc_ptr - gen_opc_buf;
4480 if (lj < j) {
4481 lj++;
4482 while (lj < j)
4483 gen_opc_instr_start[lj++] = 0;
4484 }
4485 gen_opc_pc[lj] = (uint32_t)pc_ptr;
4486 gen_opc_cc_op[lj] = dc->cc_op;
4487 gen_opc_instr_start[lj] = 1;
4488 }
4489 pc_ptr = disas_insn(dc, pc_ptr);
4490 /* stop translation if indicated */
4491 if (dc->is_jmp)
4492 break;
4493 /* if single step mode, we generate only one instruction and
4494 generate an exception */
34865134 4495 if (dc->tf || dc->singlestep_enabled) {
2c0262af
FB		 4496 gen_op_jmp_im(pc_ptr - dc->cs_base);
4497 gen_eob(dc);
4498 break;
4499 }
4500 /* if too long translation, stop generation too */
4501 if (gen_opc_ptr >= gen_opc_end ||
4502 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
4503 gen_op_jmp_im(pc_ptr - dc->cs_base);
4504 gen_eob(dc);
4505 break;
4506 }
4507 }
4508 *gen_opc_ptr = INDEX_op_end;
4509 /* we don't forget to fill the last values */
4510 if (search_pc) {
4511 j = gen_opc_ptr - gen_opc_buf;
4512 lj++;
4513 while (lj <= j)
4514 gen_opc_instr_start[lj++] = 0;
4515 }
4516
4517#ifdef DEBUG_DISAS
4518 if (loglevel) {
4519 fprintf(logfile, "----------------\n");
4520 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4521 disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
4522 fprintf(logfile, "\n");
4523
4524 fprintf(logfile, "OP:\n");
4525 dump_ops(gen_opc_buf, gen_opparam_buf);
4526 fprintf(logfile, "\n");
4527 }
4528#endif
4529
4530 /* optimize flag computations */
4531 optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
4532
4533#ifdef DEBUG_DISAS
4534 if (loglevel) {
4535 fprintf(logfile, "AFTER FLAGS OPT:\n");
4536 dump_ops(gen_opc_buf, gen_opparam_buf);
4537 fprintf(logfile, "\n");
4538 }
4539#endif
4540 if (!search_pc)
4541 tb->size = pc_ptr - pc_start;
4542 return 0;
4543}
4544
4545int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
4546{
4547 return gen_intermediate_code_internal(env, tb, 0);
4548}
4549
4550int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
4551{
4552 return gen_intermediate_code_internal(env, tb, 1);
4553}
4554
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