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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 translation | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
2c0262af | 25 | |
bec93d72 | 26 | #include "qemu/host-utils.h" |
2c0262af | 27 | #include "cpu.h" |
76cad711 | 28 | #include "disas/disas.h" |
57fec1fe | 29 | #include "tcg-op.h" |
2c0262af | 30 | |
a7812ae4 PB |
31 | #include "helper.h" |
32 | #define GEN_HELPER 1 | |
33 | #include "helper.h" | |
34 | ||
2c0262af FB |
35 | #define PREFIX_REPZ 0x01 |
36 | #define PREFIX_REPNZ 0x02 | |
37 | #define PREFIX_LOCK 0x04 | |
38 | #define PREFIX_DATA 0x08 | |
39 | #define PREFIX_ADR 0x10 | |
701ed211 | 40 | #define PREFIX_VEX 0x20 |
2c0262af | 41 | |
14ce26e7 | 42 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
43 | #define CODE64(s) ((s)->code64) |
44 | #define REX_X(s) ((s)->rex_x) | |
45 | #define REX_B(s) ((s)->rex_b) | |
14ce26e7 | 46 | #else |
14ce26e7 FB |
47 | #define CODE64(s) 0 |
48 | #define REX_X(s) 0 | |
49 | #define REX_B(s) 0 | |
50 | #endif | |
51 | ||
bec93d72 RH |
52 | #ifdef TARGET_X86_64 |
53 | # define ctztl ctz64 | |
54 | # define clztl clz64 | |
55 | #else | |
56 | # define ctztl ctz32 | |
57 | # define clztl clz32 | |
58 | #endif | |
59 | ||
57fec1fe FB |
60 | //#define MACRO_TEST 1 |
61 | ||
57fec1fe | 62 | /* global register indexes */ |
a7812ae4 | 63 | static TCGv_ptr cpu_env; |
a3251186 | 64 | static TCGv cpu_A0; |
988c3eb0 | 65 | static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT; |
a7812ae4 | 66 | static TCGv_i32 cpu_cc_op; |
cc739bb0 | 67 | static TCGv cpu_regs[CPU_NB_REGS]; |
1e4840bf | 68 | /* local temps */ |
3b9d3cf1 | 69 | static TCGv cpu_T[2]; |
57fec1fe | 70 | /* local register indexes (only used inside old micro ops) */ |
a7812ae4 PB |
71 | static TCGv cpu_tmp0, cpu_tmp4; |
72 | static TCGv_ptr cpu_ptr0, cpu_ptr1; | |
73 | static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; | |
74 | static TCGv_i64 cpu_tmp1_i64; | |
57fec1fe | 75 | |
1a7ff922 PB |
76 | static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
77 | ||
022c62cb | 78 | #include "exec/gen-icount.h" |
2e70f6ef | 79 | |
57fec1fe FB |
80 | #ifdef TARGET_X86_64 |
81 | static int x86_64_hregs; | |
ae063a68 FB |
82 | #endif |
83 | ||
2c0262af FB |
84 | typedef struct DisasContext { |
85 | /* current insn context */ | |
86 | int override; /* -1 if no override */ | |
87 | int prefix; | |
88 | int aflag, dflag; | |
14ce26e7 | 89 | target_ulong pc; /* pc = eip + cs_base */ |
2c0262af FB |
90 | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
91 | static state change (stop translation) */ | |
92 | /* current block context */ | |
14ce26e7 | 93 | target_ulong cs_base; /* base of CS segment */ |
2c0262af FB |
94 | int pe; /* protected mode */ |
95 | int code32; /* 32 bit code segment */ | |
14ce26e7 FB |
96 | #ifdef TARGET_X86_64 |
97 | int lma; /* long mode active */ | |
98 | int code64; /* 64 bit code segment */ | |
99 | int rex_x, rex_b; | |
100 | #endif | |
701ed211 RH |
101 | int vex_l; /* vex vector length */ |
102 | int vex_v; /* vex vvvv register, without 1's compliment. */ | |
2c0262af | 103 | int ss32; /* 32 bit stack segment */ |
fee71888 | 104 | CCOp cc_op; /* current CC operation */ |
e207582f | 105 | bool cc_op_dirty; |
2c0262af FB |
106 | int addseg; /* non zero if either DS/ES/SS have a non zero base */ |
107 | int f_st; /* currently unused */ | |
108 | int vm86; /* vm86 mode */ | |
109 | int cpl; | |
110 | int iopl; | |
111 | int tf; /* TF cpu flag */ | |
34865134 | 112 | int singlestep_enabled; /* "hardware" single step enabled */ |
2c0262af FB |
113 | int jmp_opt; /* use direct block chaining for direct jumps */ |
114 | int mem_index; /* select memory access functions */ | |
c068688b | 115 | uint64_t flags; /* all execution flags */ |
2c0262af FB |
116 | struct TranslationBlock *tb; |
117 | int popl_esp_hack; /* for correct popl with esp base handling */ | |
14ce26e7 FB |
118 | int rip_offset; /* only used in x86_64, but left for simplicity */ |
119 | int cpuid_features; | |
3d7374c5 | 120 | int cpuid_ext_features; |
e771edab | 121 | int cpuid_ext2_features; |
12e26b75 | 122 | int cpuid_ext3_features; |
a9321a4d | 123 | int cpuid_7_0_ebx_features; |
2c0262af FB |
124 | } DisasContext; |
125 | ||
126 | static void gen_eob(DisasContext *s); | |
14ce26e7 FB |
127 | static void gen_jmp(DisasContext *s, target_ulong eip); |
128 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); | |
63633fe6 | 129 | static void gen_op(DisasContext *s1, int op, int ot, int d); |
2c0262af FB |
130 | |
131 | /* i386 arith/logic operations */ | |
132 | enum { | |
5fafdf24 TS |
133 | OP_ADDL, |
134 | OP_ORL, | |
135 | OP_ADCL, | |
2c0262af | 136 | OP_SBBL, |
5fafdf24 TS |
137 | OP_ANDL, |
138 | OP_SUBL, | |
139 | OP_XORL, | |
2c0262af FB |
140 | OP_CMPL, |
141 | }; | |
142 | ||
143 | /* i386 shift ops */ | |
144 | enum { | |
5fafdf24 TS |
145 | OP_ROL, |
146 | OP_ROR, | |
147 | OP_RCL, | |
148 | OP_RCR, | |
149 | OP_SHL, | |
150 | OP_SHR, | |
2c0262af FB |
151 | OP_SHL1, /* undocumented */ |
152 | OP_SAR = 7, | |
153 | }; | |
154 | ||
8e1c85e3 FB |
155 | enum { |
156 | JCC_O, | |
157 | JCC_B, | |
158 | JCC_Z, | |
159 | JCC_BE, | |
160 | JCC_S, | |
161 | JCC_P, | |
162 | JCC_L, | |
163 | JCC_LE, | |
164 | }; | |
165 | ||
2c0262af FB |
166 | enum { |
167 | /* I386 int registers */ | |
168 | OR_EAX, /* MUST be even numbered */ | |
169 | OR_ECX, | |
170 | OR_EDX, | |
171 | OR_EBX, | |
172 | OR_ESP, | |
173 | OR_EBP, | |
174 | OR_ESI, | |
175 | OR_EDI, | |
14ce26e7 FB |
176 | |
177 | OR_TMP0 = 16, /* temporary operand register */ | |
2c0262af FB |
178 | OR_TMP1, |
179 | OR_A0, /* temporary register used when doing address evaluation */ | |
2c0262af FB |
180 | }; |
181 | ||
b666265b | 182 | enum { |
a3251186 RH |
183 | USES_CC_DST = 1, |
184 | USES_CC_SRC = 2, | |
988c3eb0 RH |
185 | USES_CC_SRC2 = 4, |
186 | USES_CC_SRCT = 8, | |
b666265b RH |
187 | }; |
188 | ||
189 | /* Bit set if the global variable is live after setting CC_OP to X. */ | |
190 | static const uint8_t cc_op_live[CC_OP_NB] = { | |
988c3eb0 | 191 | [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, |
b666265b RH |
192 | [CC_OP_EFLAGS] = USES_CC_SRC, |
193 | [CC_OP_MULB ... CC_OP_MULQ] = USES_CC_DST | USES_CC_SRC, | |
194 | [CC_OP_ADDB ... CC_OP_ADDQ] = USES_CC_DST | USES_CC_SRC, | |
988c3eb0 | 195 | [CC_OP_ADCB ... CC_OP_ADCQ] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, |
a3251186 | 196 | [CC_OP_SUBB ... CC_OP_SUBQ] = USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, |
988c3eb0 | 197 | [CC_OP_SBBB ... CC_OP_SBBQ] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, |
b666265b RH |
198 | [CC_OP_LOGICB ... CC_OP_LOGICQ] = USES_CC_DST, |
199 | [CC_OP_INCB ... CC_OP_INCQ] = USES_CC_DST | USES_CC_SRC, | |
200 | [CC_OP_DECB ... CC_OP_DECQ] = USES_CC_DST | USES_CC_SRC, | |
201 | [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC, | |
202 | [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC, | |
bc4b43dc | 203 | [CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC, |
cd7f97ca RH |
204 | [CC_OP_ADCX] = USES_CC_DST | USES_CC_SRC, |
205 | [CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2, | |
206 | [CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, | |
436ff2d2 | 207 | [CC_OP_CLR] = 0, |
b666265b RH |
208 | }; |
209 | ||
e207582f | 210 | static void set_cc_op(DisasContext *s, CCOp op) |
3ca51d07 | 211 | { |
b666265b RH |
212 | int dead; |
213 | ||
214 | if (s->cc_op == op) { | |
215 | return; | |
216 | } | |
217 | ||
218 | /* Discard CC computation that will no longer be used. */ | |
219 | dead = cc_op_live[s->cc_op] & ~cc_op_live[op]; | |
220 | if (dead & USES_CC_DST) { | |
221 | tcg_gen_discard_tl(cpu_cc_dst); | |
e207582f | 222 | } |
b666265b RH |
223 | if (dead & USES_CC_SRC) { |
224 | tcg_gen_discard_tl(cpu_cc_src); | |
225 | } | |
988c3eb0 RH |
226 | if (dead & USES_CC_SRC2) { |
227 | tcg_gen_discard_tl(cpu_cc_src2); | |
228 | } | |
a3251186 RH |
229 | if (dead & USES_CC_SRCT) { |
230 | tcg_gen_discard_tl(cpu_cc_srcT); | |
231 | } | |
b666265b | 232 | |
e2f515cf RH |
233 | if (op == CC_OP_DYNAMIC) { |
234 | /* The DYNAMIC setting is translator only, and should never be | |
235 | stored. Thus we always consider it clean. */ | |
236 | s->cc_op_dirty = false; | |
237 | } else { | |
238 | /* Discard any computed CC_OP value (see shifts). */ | |
239 | if (s->cc_op == CC_OP_DYNAMIC) { | |
240 | tcg_gen_discard_i32(cpu_cc_op); | |
241 | } | |
242 | s->cc_op_dirty = true; | |
243 | } | |
b666265b | 244 | s->cc_op = op; |
e207582f RH |
245 | } |
246 | ||
e207582f RH |
247 | static void gen_update_cc_op(DisasContext *s) |
248 | { | |
249 | if (s->cc_op_dirty) { | |
773cdfcc | 250 | tcg_gen_movi_i32(cpu_cc_op, s->cc_op); |
e207582f RH |
251 | s->cc_op_dirty = false; |
252 | } | |
3ca51d07 RH |
253 | } |
254 | ||
57fec1fe FB |
255 | static inline void gen_op_movl_T0_0(void) |
256 | { | |
257 | tcg_gen_movi_tl(cpu_T[0], 0); | |
258 | } | |
259 | ||
260 | static inline void gen_op_movl_T0_im(int32_t val) | |
261 | { | |
262 | tcg_gen_movi_tl(cpu_T[0], val); | |
263 | } | |
264 | ||
265 | static inline void gen_op_movl_T0_imu(uint32_t val) | |
266 | { | |
267 | tcg_gen_movi_tl(cpu_T[0], val); | |
268 | } | |
269 | ||
270 | static inline void gen_op_movl_T1_im(int32_t val) | |
271 | { | |
272 | tcg_gen_movi_tl(cpu_T[1], val); | |
273 | } | |
274 | ||
275 | static inline void gen_op_movl_T1_imu(uint32_t val) | |
276 | { | |
277 | tcg_gen_movi_tl(cpu_T[1], val); | |
278 | } | |
279 | ||
280 | static inline void gen_op_movl_A0_im(uint32_t val) | |
281 | { | |
282 | tcg_gen_movi_tl(cpu_A0, val); | |
283 | } | |
284 | ||
285 | #ifdef TARGET_X86_64 | |
286 | static inline void gen_op_movq_A0_im(int64_t val) | |
287 | { | |
288 | tcg_gen_movi_tl(cpu_A0, val); | |
289 | } | |
290 | #endif | |
291 | ||
292 | static inline void gen_movtl_T0_im(target_ulong val) | |
293 | { | |
294 | tcg_gen_movi_tl(cpu_T[0], val); | |
295 | } | |
296 | ||
297 | static inline void gen_movtl_T1_im(target_ulong val) | |
298 | { | |
299 | tcg_gen_movi_tl(cpu_T[1], val); | |
300 | } | |
301 | ||
302 | static inline void gen_op_andl_T0_ffff(void) | |
303 | { | |
304 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
305 | } | |
306 | ||
307 | static inline void gen_op_andl_T0_im(uint32_t val) | |
308 | { | |
309 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); | |
310 | } | |
311 | ||
312 | static inline void gen_op_movl_T0_T1(void) | |
313 | { | |
314 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); | |
315 | } | |
316 | ||
317 | static inline void gen_op_andl_A0_ffff(void) | |
318 | { | |
319 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff); | |
320 | } | |
321 | ||
14ce26e7 FB |
322 | #ifdef TARGET_X86_64 |
323 | ||
324 | #define NB_OP_SIZES 4 | |
325 | ||
14ce26e7 FB |
326 | #else /* !TARGET_X86_64 */ |
327 | ||
328 | #define NB_OP_SIZES 3 | |
329 | ||
14ce26e7 FB |
330 | #endif /* !TARGET_X86_64 */ |
331 | ||
e2542fe2 | 332 | #if defined(HOST_WORDS_BIGENDIAN) |
57fec1fe FB |
333 | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
334 | #define REG_H_OFFSET (sizeof(target_ulong) - 2) | |
335 | #define REG_W_OFFSET (sizeof(target_ulong) - 2) | |
336 | #define REG_L_OFFSET (sizeof(target_ulong) - 4) | |
337 | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) | |
14ce26e7 | 338 | #else |
57fec1fe FB |
339 | #define REG_B_OFFSET 0 |
340 | #define REG_H_OFFSET 1 | |
341 | #define REG_W_OFFSET 0 | |
342 | #define REG_L_OFFSET 0 | |
343 | #define REG_LH_OFFSET 4 | |
14ce26e7 | 344 | #endif |
57fec1fe | 345 | |
96d7073f PM |
346 | /* In instruction encodings for byte register accesses the |
347 | * register number usually indicates "low 8 bits of register N"; | |
348 | * however there are some special cases where N 4..7 indicates | |
349 | * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return | |
350 | * true for this special case, false otherwise. | |
351 | */ | |
352 | static inline bool byte_reg_is_xH(int reg) | |
353 | { | |
354 | if (reg < 4) { | |
355 | return false; | |
356 | } | |
357 | #ifdef TARGET_X86_64 | |
358 | if (reg >= 8 || x86_64_hregs) { | |
359 | return false; | |
360 | } | |
361 | #endif | |
362 | return true; | |
363 | } | |
364 | ||
1e4840bf | 365 | static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) |
57fec1fe FB |
366 | { |
367 | switch(ot) { | |
4ba9938c | 368 | case MO_8: |
96d7073f | 369 | if (!byte_reg_is_xH(reg)) { |
c832e3de | 370 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); |
57fec1fe | 371 | } else { |
c832e3de | 372 | tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); |
57fec1fe FB |
373 | } |
374 | break; | |
4ba9938c | 375 | case MO_16: |
c832e3de | 376 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16); |
57fec1fe | 377 | break; |
cc739bb0 | 378 | default: /* XXX this shouldn't be reached; abort? */ |
4ba9938c | 379 | case MO_32: |
cc739bb0 LD |
380 | /* For x86_64, this sets the higher half of register to zero. |
381 | For i386, this is equivalent to a mov. */ | |
382 | tcg_gen_ext32u_tl(cpu_regs[reg], t0); | |
57fec1fe | 383 | break; |
cc739bb0 | 384 | #ifdef TARGET_X86_64 |
4ba9938c | 385 | case MO_64: |
cc739bb0 | 386 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
57fec1fe | 387 | break; |
14ce26e7 | 388 | #endif |
57fec1fe FB |
389 | } |
390 | } | |
2c0262af | 391 | |
57fec1fe FB |
392 | static inline void gen_op_mov_reg_T0(int ot, int reg) |
393 | { | |
1e4840bf | 394 | gen_op_mov_reg_v(ot, reg, cpu_T[0]); |
57fec1fe FB |
395 | } |
396 | ||
397 | static inline void gen_op_mov_reg_T1(int ot, int reg) | |
398 | { | |
1e4840bf | 399 | gen_op_mov_reg_v(ot, reg, cpu_T[1]); |
57fec1fe FB |
400 | } |
401 | ||
402 | static inline void gen_op_mov_reg_A0(int size, int reg) | |
403 | { | |
404 | switch(size) { | |
4ba9938c | 405 | case MO_8: |
c832e3de | 406 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16); |
57fec1fe | 407 | break; |
cc739bb0 | 408 | default: /* XXX this shouldn't be reached; abort? */ |
4ba9938c | 409 | case MO_16: |
cc739bb0 LD |
410 | /* For x86_64, this sets the higher half of register to zero. |
411 | For i386, this is equivalent to a mov. */ | |
412 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0); | |
57fec1fe | 413 | break; |
cc739bb0 | 414 | #ifdef TARGET_X86_64 |
4ba9938c | 415 | case MO_32: |
cc739bb0 | 416 | tcg_gen_mov_tl(cpu_regs[reg], cpu_A0); |
57fec1fe | 417 | break; |
14ce26e7 | 418 | #endif |
57fec1fe FB |
419 | } |
420 | } | |
421 | ||
1e4840bf | 422 | static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) |
57fec1fe | 423 | { |
4ba9938c | 424 | if (ot == MO_8 && byte_reg_is_xH(reg)) { |
96d7073f PM |
425 | tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); |
426 | tcg_gen_ext8u_tl(t0, t0); | |
427 | } else { | |
cc739bb0 | 428 | tcg_gen_mov_tl(t0, cpu_regs[reg]); |
57fec1fe FB |
429 | } |
430 | } | |
431 | ||
1e4840bf FB |
432 | static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) |
433 | { | |
434 | gen_op_mov_v_reg(ot, cpu_T[t_index], reg); | |
435 | } | |
436 | ||
57fec1fe FB |
437 | static inline void gen_op_movl_A0_reg(int reg) |
438 | { | |
cc739bb0 | 439 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
440 | } |
441 | ||
442 | static inline void gen_op_addl_A0_im(int32_t val) | |
443 | { | |
444 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
14ce26e7 | 445 | #ifdef TARGET_X86_64 |
57fec1fe | 446 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); |
14ce26e7 | 447 | #endif |
57fec1fe | 448 | } |
2c0262af | 449 | |
14ce26e7 | 450 | #ifdef TARGET_X86_64 |
57fec1fe FB |
451 | static inline void gen_op_addq_A0_im(int64_t val) |
452 | { | |
453 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
454 | } | |
14ce26e7 | 455 | #endif |
57fec1fe FB |
456 | |
457 | static void gen_add_A0_im(DisasContext *s, int val) | |
458 | { | |
459 | #ifdef TARGET_X86_64 | |
460 | if (CODE64(s)) | |
461 | gen_op_addq_A0_im(val); | |
462 | else | |
463 | #endif | |
464 | gen_op_addl_A0_im(val); | |
465 | } | |
2c0262af | 466 | |
57fec1fe | 467 | static inline void gen_op_addl_T0_T1(void) |
2c0262af | 468 | { |
57fec1fe FB |
469 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
470 | } | |
471 | ||
472 | static inline void gen_op_jmp_T0(void) | |
473 | { | |
317ac620 | 474 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip)); |
57fec1fe FB |
475 | } |
476 | ||
6e0d8677 | 477 | static inline void gen_op_add_reg_im(int size, int reg, int32_t val) |
57fec1fe | 478 | { |
6e0d8677 | 479 | switch(size) { |
4ba9938c | 480 | case MO_8: |
cc739bb0 | 481 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
c832e3de | 482 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 | 483 | break; |
4ba9938c | 484 | case MO_16: |
cc739bb0 LD |
485 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
486 | /* For x86_64, this sets the higher half of register to zero. | |
487 | For i386, this is equivalent to a nop. */ | |
488 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
489 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 FB |
490 | break; |
491 | #ifdef TARGET_X86_64 | |
4ba9938c | 492 | case MO_32: |
cc739bb0 | 493 | tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val); |
6e0d8677 FB |
494 | break; |
495 | #endif | |
496 | } | |
57fec1fe FB |
497 | } |
498 | ||
6e0d8677 | 499 | static inline void gen_op_add_reg_T0(int size, int reg) |
57fec1fe | 500 | { |
6e0d8677 | 501 | switch(size) { |
4ba9938c | 502 | case MO_8: |
cc739bb0 | 503 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
c832e3de | 504 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 | 505 | break; |
4ba9938c | 506 | case MO_16: |
cc739bb0 LD |
507 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
508 | /* For x86_64, this sets the higher half of register to zero. | |
509 | For i386, this is equivalent to a nop. */ | |
510 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
511 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 | 512 | break; |
14ce26e7 | 513 | #ifdef TARGET_X86_64 |
4ba9938c | 514 | case MO_32: |
cc739bb0 | 515 | tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]); |
6e0d8677 | 516 | break; |
14ce26e7 | 517 | #endif |
6e0d8677 FB |
518 | } |
519 | } | |
57fec1fe | 520 | |
57fec1fe FB |
521 | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) |
522 | { | |
cc739bb0 LD |
523 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
524 | if (shift != 0) | |
57fec1fe FB |
525 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
526 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
cc739bb0 LD |
527 | /* For x86_64, this sets the higher half of register to zero. |
528 | For i386, this is equivalent to a nop. */ | |
529 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
57fec1fe | 530 | } |
2c0262af | 531 | |
57fec1fe FB |
532 | static inline void gen_op_movl_A0_seg(int reg) |
533 | { | |
317ac620 | 534 | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET); |
57fec1fe | 535 | } |
2c0262af | 536 | |
7162ab21 | 537 | static inline void gen_op_addl_A0_seg(DisasContext *s, int reg) |
57fec1fe | 538 | { |
317ac620 | 539 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 540 | #ifdef TARGET_X86_64 |
7162ab21 VC |
541 | if (CODE64(s)) { |
542 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
543 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
544 | } else { | |
545 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
546 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
547 | } | |
548 | #else | |
549 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe FB |
550 | #endif |
551 | } | |
2c0262af | 552 | |
14ce26e7 | 553 | #ifdef TARGET_X86_64 |
57fec1fe FB |
554 | static inline void gen_op_movq_A0_seg(int reg) |
555 | { | |
317ac620 | 556 | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 557 | } |
14ce26e7 | 558 | |
57fec1fe FB |
559 | static inline void gen_op_addq_A0_seg(int reg) |
560 | { | |
317ac620 | 561 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe FB |
562 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
563 | } | |
564 | ||
565 | static inline void gen_op_movq_A0_reg(int reg) | |
566 | { | |
cc739bb0 | 567 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
568 | } |
569 | ||
570 | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) | |
571 | { | |
cc739bb0 LD |
572 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
573 | if (shift != 0) | |
57fec1fe FB |
574 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
575 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
576 | } | |
14ce26e7 FB |
577 | #endif |
578 | ||
323d1876 | 579 | static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0) |
57fec1fe | 580 | { |
3c5f4116 | 581 | tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE); |
57fec1fe | 582 | } |
2c0262af | 583 | |
323d1876 | 584 | static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0) |
57fec1fe | 585 | { |
3523e4bd | 586 | tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE); |
57fec1fe | 587 | } |
4f31916f | 588 | |
d4faa3e0 RH |
589 | static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) |
590 | { | |
591 | if (d == OR_TMP0) { | |
fd8ca9f6 | 592 | gen_op_st_v(s, idx, cpu_T[0], cpu_A0); |
d4faa3e0 RH |
593 | } else { |
594 | gen_op_mov_reg_T0(idx, d); | |
595 | } | |
596 | } | |
597 | ||
14ce26e7 FB |
598 | static inline void gen_jmp_im(target_ulong pc) |
599 | { | |
57fec1fe | 600 | tcg_gen_movi_tl(cpu_tmp0, pc); |
317ac620 | 601 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip)); |
14ce26e7 FB |
602 | } |
603 | ||
2c0262af FB |
604 | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
605 | { | |
606 | int override; | |
607 | ||
608 | override = s->override; | |
14ce26e7 FB |
609 | #ifdef TARGET_X86_64 |
610 | if (s->aflag == 2) { | |
611 | if (override >= 0) { | |
57fec1fe FB |
612 | gen_op_movq_A0_seg(override); |
613 | gen_op_addq_A0_reg_sN(0, R_ESI); | |
14ce26e7 | 614 | } else { |
57fec1fe | 615 | gen_op_movq_A0_reg(R_ESI); |
14ce26e7 FB |
616 | } |
617 | } else | |
618 | #endif | |
2c0262af FB |
619 | if (s->aflag) { |
620 | /* 32 bit address */ | |
621 | if (s->addseg && override < 0) | |
622 | override = R_DS; | |
623 | if (override >= 0) { | |
57fec1fe FB |
624 | gen_op_movl_A0_seg(override); |
625 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af | 626 | } else { |
57fec1fe | 627 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
628 | } |
629 | } else { | |
630 | /* 16 address, always override */ | |
631 | if (override < 0) | |
632 | override = R_DS; | |
57fec1fe | 633 | gen_op_movl_A0_reg(R_ESI); |
2c0262af | 634 | gen_op_andl_A0_ffff(); |
7162ab21 | 635 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
636 | } |
637 | } | |
638 | ||
639 | static inline void gen_string_movl_A0_EDI(DisasContext *s) | |
640 | { | |
14ce26e7 FB |
641 | #ifdef TARGET_X86_64 |
642 | if (s->aflag == 2) { | |
57fec1fe | 643 | gen_op_movq_A0_reg(R_EDI); |
14ce26e7 FB |
644 | } else |
645 | #endif | |
2c0262af FB |
646 | if (s->aflag) { |
647 | if (s->addseg) { | |
57fec1fe FB |
648 | gen_op_movl_A0_seg(R_ES); |
649 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af | 650 | } else { |
57fec1fe | 651 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
652 | } |
653 | } else { | |
57fec1fe | 654 | gen_op_movl_A0_reg(R_EDI); |
2c0262af | 655 | gen_op_andl_A0_ffff(); |
7162ab21 | 656 | gen_op_addl_A0_seg(s, R_ES); |
2c0262af FB |
657 | } |
658 | } | |
659 | ||
6e0d8677 FB |
660 | static inline void gen_op_movl_T0_Dshift(int ot) |
661 | { | |
317ac620 | 662 | tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df)); |
6e0d8677 | 663 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); |
2c0262af FB |
664 | }; |
665 | ||
d824df34 | 666 | static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign) |
6e0d8677 | 667 | { |
d824df34 | 668 | switch (size) { |
4ba9938c | 669 | case MO_8: |
d824df34 PB |
670 | if (sign) { |
671 | tcg_gen_ext8s_tl(dst, src); | |
672 | } else { | |
673 | tcg_gen_ext8u_tl(dst, src); | |
674 | } | |
675 | return dst; | |
4ba9938c | 676 | case MO_16: |
d824df34 PB |
677 | if (sign) { |
678 | tcg_gen_ext16s_tl(dst, src); | |
679 | } else { | |
680 | tcg_gen_ext16u_tl(dst, src); | |
681 | } | |
682 | return dst; | |
683 | #ifdef TARGET_X86_64 | |
4ba9938c | 684 | case MO_32: |
d824df34 PB |
685 | if (sign) { |
686 | tcg_gen_ext32s_tl(dst, src); | |
687 | } else { | |
688 | tcg_gen_ext32u_tl(dst, src); | |
689 | } | |
690 | return dst; | |
691 | #endif | |
6e0d8677 | 692 | default: |
d824df34 | 693 | return src; |
6e0d8677 FB |
694 | } |
695 | } | |
3b46e624 | 696 | |
d824df34 PB |
697 | static void gen_extu(int ot, TCGv reg) |
698 | { | |
699 | gen_ext_tl(reg, reg, ot, false); | |
700 | } | |
701 | ||
6e0d8677 FB |
702 | static void gen_exts(int ot, TCGv reg) |
703 | { | |
d824df34 | 704 | gen_ext_tl(reg, reg, ot, true); |
6e0d8677 | 705 | } |
2c0262af | 706 | |
6e0d8677 FB |
707 | static inline void gen_op_jnz_ecx(int size, int label1) |
708 | { | |
cc739bb0 | 709 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 710 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 711 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); |
6e0d8677 FB |
712 | } |
713 | ||
714 | static inline void gen_op_jz_ecx(int size, int label1) | |
715 | { | |
cc739bb0 | 716 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 717 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 718 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
6e0d8677 | 719 | } |
2c0262af | 720 | |
a7812ae4 PB |
721 | static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n) |
722 | { | |
723 | switch (ot) { | |
4ba9938c | 724 | case MO_8: |
93ab25d7 PB |
725 | gen_helper_inb(v, n); |
726 | break; | |
4ba9938c | 727 | case MO_16: |
93ab25d7 PB |
728 | gen_helper_inw(v, n); |
729 | break; | |
4ba9938c | 730 | case MO_32: |
93ab25d7 PB |
731 | gen_helper_inl(v, n); |
732 | break; | |
a7812ae4 | 733 | } |
a7812ae4 | 734 | } |
2c0262af | 735 | |
a7812ae4 PB |
736 | static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n) |
737 | { | |
738 | switch (ot) { | |
4ba9938c | 739 | case MO_8: |
93ab25d7 PB |
740 | gen_helper_outb(v, n); |
741 | break; | |
4ba9938c | 742 | case MO_16: |
93ab25d7 PB |
743 | gen_helper_outw(v, n); |
744 | break; | |
4ba9938c | 745 | case MO_32: |
93ab25d7 PB |
746 | gen_helper_outl(v, n); |
747 | break; | |
a7812ae4 | 748 | } |
a7812ae4 | 749 | } |
f115e911 | 750 | |
b8b6a50b FB |
751 | static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, |
752 | uint32_t svm_flags) | |
f115e911 | 753 | { |
b8b6a50b FB |
754 | int state_saved; |
755 | target_ulong next_eip; | |
756 | ||
757 | state_saved = 0; | |
f115e911 | 758 | if (s->pe && (s->cpl > s->iopl || s->vm86)) { |
773cdfcc | 759 | gen_update_cc_op(s); |
14ce26e7 | 760 | gen_jmp_im(cur_eip); |
b8b6a50b | 761 | state_saved = 1; |
b6abf97d | 762 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 763 | switch (ot) { |
4ba9938c | 764 | case MO_8: |
4a7443be BS |
765 | gen_helper_check_iob(cpu_env, cpu_tmp2_i32); |
766 | break; | |
4ba9938c | 767 | case MO_16: |
4a7443be BS |
768 | gen_helper_check_iow(cpu_env, cpu_tmp2_i32); |
769 | break; | |
4ba9938c | 770 | case MO_32: |
4a7443be BS |
771 | gen_helper_check_iol(cpu_env, cpu_tmp2_i32); |
772 | break; | |
a7812ae4 | 773 | } |
b8b6a50b | 774 | } |
872929aa | 775 | if(s->flags & HF_SVMI_MASK) { |
b8b6a50b | 776 | if (!state_saved) { |
773cdfcc | 777 | gen_update_cc_op(s); |
b8b6a50b | 778 | gen_jmp_im(cur_eip); |
b8b6a50b FB |
779 | } |
780 | svm_flags |= (1 << (4 + ot)); | |
781 | next_eip = s->pc - s->cs_base; | |
b6abf97d | 782 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
052e80d5 BS |
783 | gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32, |
784 | tcg_const_i32(svm_flags), | |
a7812ae4 | 785 | tcg_const_i32(next_eip - cur_eip)); |
f115e911 FB |
786 | } |
787 | } | |
788 | ||
2c0262af FB |
789 | static inline void gen_movs(DisasContext *s, int ot) |
790 | { | |
791 | gen_string_movl_A0_ESI(s); | |
909be183 | 792 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 793 | gen_string_movl_A0_EDI(s); |
fd8ca9f6 | 794 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
6e0d8677 FB |
795 | gen_op_movl_T0_Dshift(ot); |
796 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
797 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
798 | } |
799 | ||
b6abf97d FB |
800 | static void gen_op_update1_cc(void) |
801 | { | |
b6abf97d FB |
802 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
803 | } | |
804 | ||
805 | static void gen_op_update2_cc(void) | |
806 | { | |
807 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
808 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
809 | } | |
810 | ||
988c3eb0 RH |
811 | static void gen_op_update3_cc(TCGv reg) |
812 | { | |
813 | tcg_gen_mov_tl(cpu_cc_src2, reg); | |
814 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
815 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
816 | } | |
817 | ||
b6abf97d FB |
818 | static inline void gen_op_testl_T0_T1_cc(void) |
819 | { | |
b6abf97d FB |
820 | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
821 | } | |
822 | ||
823 | static void gen_op_update_neg_cc(void) | |
824 | { | |
b6abf97d | 825 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
a3251186 RH |
826 | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]); |
827 | tcg_gen_movi_tl(cpu_cc_srcT, 0); | |
b6abf97d FB |
828 | } |
829 | ||
d229edce RH |
830 | /* compute all eflags to cc_src */ |
831 | static void gen_compute_eflags(DisasContext *s) | |
8e1c85e3 | 832 | { |
988c3eb0 | 833 | TCGv zero, dst, src1, src2; |
db9f2597 RH |
834 | int live, dead; |
835 | ||
d229edce RH |
836 | if (s->cc_op == CC_OP_EFLAGS) { |
837 | return; | |
838 | } | |
436ff2d2 RH |
839 | if (s->cc_op == CC_OP_CLR) { |
840 | tcg_gen_movi_tl(cpu_cc_src, CC_Z); | |
841 | set_cc_op(s, CC_OP_EFLAGS); | |
842 | return; | |
843 | } | |
db9f2597 RH |
844 | |
845 | TCGV_UNUSED(zero); | |
846 | dst = cpu_cc_dst; | |
847 | src1 = cpu_cc_src; | |
988c3eb0 | 848 | src2 = cpu_cc_src2; |
db9f2597 RH |
849 | |
850 | /* Take care to not read values that are not live. */ | |
851 | live = cc_op_live[s->cc_op] & ~USES_CC_SRCT; | |
988c3eb0 | 852 | dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2); |
db9f2597 RH |
853 | if (dead) { |
854 | zero = tcg_const_tl(0); | |
855 | if (dead & USES_CC_DST) { | |
856 | dst = zero; | |
857 | } | |
858 | if (dead & USES_CC_SRC) { | |
859 | src1 = zero; | |
860 | } | |
988c3eb0 RH |
861 | if (dead & USES_CC_SRC2) { |
862 | src2 = zero; | |
863 | } | |
db9f2597 RH |
864 | } |
865 | ||
773cdfcc | 866 | gen_update_cc_op(s); |
988c3eb0 | 867 | gen_helper_cc_compute_all(cpu_cc_src, dst, src1, src2, cpu_cc_op); |
d229edce | 868 | set_cc_op(s, CC_OP_EFLAGS); |
db9f2597 RH |
869 | |
870 | if (dead) { | |
871 | tcg_temp_free(zero); | |
872 | } | |
8e1c85e3 FB |
873 | } |
874 | ||
bec93d72 RH |
875 | typedef struct CCPrepare { |
876 | TCGCond cond; | |
877 | TCGv reg; | |
878 | TCGv reg2; | |
879 | target_ulong imm; | |
880 | target_ulong mask; | |
881 | bool use_reg2; | |
882 | bool no_setcond; | |
883 | } CCPrepare; | |
884 | ||
06847f1f | 885 | /* compute eflags.C to reg */ |
bec93d72 | 886 | static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) |
06847f1f RH |
887 | { |
888 | TCGv t0, t1; | |
bec93d72 | 889 | int size, shift; |
06847f1f RH |
890 | |
891 | switch (s->cc_op) { | |
892 | case CC_OP_SUBB ... CC_OP_SUBQ: | |
a3251186 | 893 | /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */ |
06847f1f RH |
894 | size = s->cc_op - CC_OP_SUBB; |
895 | t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
896 | /* If no temporary was used, be careful not to alias t1 and t0. */ | |
897 | t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg; | |
a3251186 | 898 | tcg_gen_mov_tl(t0, cpu_cc_srcT); |
06847f1f RH |
899 | gen_extu(size, t0); |
900 | goto add_sub; | |
901 | ||
902 | case CC_OP_ADDB ... CC_OP_ADDQ: | |
903 | /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ | |
904 | size = s->cc_op - CC_OP_ADDB; | |
905 | t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
906 | t0 = gen_ext_tl(reg, cpu_cc_dst, size, false); | |
907 | add_sub: | |
bec93d72 RH |
908 | return (CCPrepare) { .cond = TCG_COND_LTU, .reg = t0, |
909 | .reg2 = t1, .mask = -1, .use_reg2 = true }; | |
06847f1f | 910 | |
06847f1f | 911 | case CC_OP_LOGICB ... CC_OP_LOGICQ: |
436ff2d2 | 912 | case CC_OP_CLR: |
bec93d72 | 913 | return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; |
06847f1f RH |
914 | |
915 | case CC_OP_INCB ... CC_OP_INCQ: | |
916 | case CC_OP_DECB ... CC_OP_DECQ: | |
bec93d72 RH |
917 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
918 | .mask = -1, .no_setcond = true }; | |
06847f1f RH |
919 | |
920 | case CC_OP_SHLB ... CC_OP_SHLQ: | |
921 | /* (CC_SRC >> (DATA_BITS - 1)) & 1 */ | |
922 | size = s->cc_op - CC_OP_SHLB; | |
bec93d72 RH |
923 | shift = (8 << size) - 1; |
924 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, | |
925 | .mask = (target_ulong)1 << shift }; | |
06847f1f RH |
926 | |
927 | case CC_OP_MULB ... CC_OP_MULQ: | |
bec93d72 RH |
928 | return (CCPrepare) { .cond = TCG_COND_NE, |
929 | .reg = cpu_cc_src, .mask = -1 }; | |
06847f1f | 930 | |
bc4b43dc RH |
931 | case CC_OP_BMILGB ... CC_OP_BMILGQ: |
932 | size = s->cc_op - CC_OP_BMILGB; | |
933 | t0 = gen_ext_tl(reg, cpu_cc_src, size, false); | |
934 | return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 }; | |
935 | ||
cd7f97ca RH |
936 | case CC_OP_ADCX: |
937 | case CC_OP_ADCOX: | |
938 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_dst, | |
939 | .mask = -1, .no_setcond = true }; | |
940 | ||
06847f1f RH |
941 | case CC_OP_EFLAGS: |
942 | case CC_OP_SARB ... CC_OP_SARQ: | |
943 | /* CC_SRC & 1 */ | |
bec93d72 RH |
944 | return (CCPrepare) { .cond = TCG_COND_NE, |
945 | .reg = cpu_cc_src, .mask = CC_C }; | |
06847f1f RH |
946 | |
947 | default: | |
948 | /* The need to compute only C from CC_OP_DYNAMIC is important | |
949 | in efficiently implementing e.g. INC at the start of a TB. */ | |
950 | gen_update_cc_op(s); | |
988c3eb0 RH |
951 | gen_helper_cc_compute_c(reg, cpu_cc_dst, cpu_cc_src, |
952 | cpu_cc_src2, cpu_cc_op); | |
bec93d72 RH |
953 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, |
954 | .mask = -1, .no_setcond = true }; | |
06847f1f RH |
955 | } |
956 | } | |
957 | ||
1608ecca | 958 | /* compute eflags.P to reg */ |
bec93d72 | 959 | static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg) |
1608ecca | 960 | { |
d229edce | 961 | gen_compute_eflags(s); |
bec93d72 RH |
962 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
963 | .mask = CC_P }; | |
1608ecca PB |
964 | } |
965 | ||
966 | /* compute eflags.S to reg */ | |
bec93d72 | 967 | static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg) |
1608ecca | 968 | { |
086c4077 RH |
969 | switch (s->cc_op) { |
970 | case CC_OP_DYNAMIC: | |
971 | gen_compute_eflags(s); | |
972 | /* FALLTHRU */ | |
973 | case CC_OP_EFLAGS: | |
cd7f97ca RH |
974 | case CC_OP_ADCX: |
975 | case CC_OP_ADOX: | |
976 | case CC_OP_ADCOX: | |
bec93d72 RH |
977 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
978 | .mask = CC_S }; | |
436ff2d2 RH |
979 | case CC_OP_CLR: |
980 | return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; | |
086c4077 RH |
981 | default: |
982 | { | |
983 | int size = (s->cc_op - CC_OP_ADDB) & 3; | |
984 | TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true); | |
bec93d72 | 985 | return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 }; |
086c4077 | 986 | } |
086c4077 | 987 | } |
1608ecca PB |
988 | } |
989 | ||
990 | /* compute eflags.O to reg */ | |
bec93d72 | 991 | static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg) |
1608ecca | 992 | { |
cd7f97ca RH |
993 | switch (s->cc_op) { |
994 | case CC_OP_ADOX: | |
995 | case CC_OP_ADCOX: | |
996 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src2, | |
997 | .mask = -1, .no_setcond = true }; | |
436ff2d2 RH |
998 | case CC_OP_CLR: |
999 | return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; | |
cd7f97ca RH |
1000 | default: |
1001 | gen_compute_eflags(s); | |
1002 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, | |
1003 | .mask = CC_O }; | |
1004 | } | |
1608ecca PB |
1005 | } |
1006 | ||
1007 | /* compute eflags.Z to reg */ | |
bec93d72 | 1008 | static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) |
1608ecca | 1009 | { |
086c4077 RH |
1010 | switch (s->cc_op) { |
1011 | case CC_OP_DYNAMIC: | |
1012 | gen_compute_eflags(s); | |
1013 | /* FALLTHRU */ | |
1014 | case CC_OP_EFLAGS: | |
cd7f97ca RH |
1015 | case CC_OP_ADCX: |
1016 | case CC_OP_ADOX: | |
1017 | case CC_OP_ADCOX: | |
bec93d72 RH |
1018 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
1019 | .mask = CC_Z }; | |
436ff2d2 RH |
1020 | case CC_OP_CLR: |
1021 | return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 }; | |
086c4077 RH |
1022 | default: |
1023 | { | |
1024 | int size = (s->cc_op - CC_OP_ADDB) & 3; | |
1025 | TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false); | |
bec93d72 | 1026 | return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 }; |
086c4077 | 1027 | } |
bec93d72 RH |
1028 | } |
1029 | } | |
1030 | ||
c365395e PB |
1031 | /* perform a conditional store into register 'reg' according to jump opcode |
1032 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
276e6b5f | 1033 | static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) |
8e1c85e3 | 1034 | { |
c365395e | 1035 | int inv, jcc_op, size, cond; |
276e6b5f | 1036 | CCPrepare cc; |
c365395e PB |
1037 | TCGv t0; |
1038 | ||
1039 | inv = b & 1; | |
8e1c85e3 | 1040 | jcc_op = (b >> 1) & 7; |
c365395e PB |
1041 | |
1042 | switch (s->cc_op) { | |
69d1aa31 RH |
1043 | case CC_OP_SUBB ... CC_OP_SUBQ: |
1044 | /* We optimize relational operators for the cmp/jcc case. */ | |
c365395e PB |
1045 | size = s->cc_op - CC_OP_SUBB; |
1046 | switch (jcc_op) { | |
1047 | case JCC_BE: | |
a3251186 | 1048 | tcg_gen_mov_tl(cpu_tmp4, cpu_cc_srcT); |
c365395e PB |
1049 | gen_extu(size, cpu_tmp4); |
1050 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
276e6b5f RH |
1051 | cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4, |
1052 | .reg2 = t0, .mask = -1, .use_reg2 = true }; | |
c365395e | 1053 | break; |
8e1c85e3 | 1054 | |
c365395e | 1055 | case JCC_L: |
276e6b5f | 1056 | cond = TCG_COND_LT; |
c365395e PB |
1057 | goto fast_jcc_l; |
1058 | case JCC_LE: | |
276e6b5f | 1059 | cond = TCG_COND_LE; |
c365395e | 1060 | fast_jcc_l: |
a3251186 | 1061 | tcg_gen_mov_tl(cpu_tmp4, cpu_cc_srcT); |
c365395e PB |
1062 | gen_exts(size, cpu_tmp4); |
1063 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true); | |
276e6b5f RH |
1064 | cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4, |
1065 | .reg2 = t0, .mask = -1, .use_reg2 = true }; | |
c365395e | 1066 | break; |
8e1c85e3 | 1067 | |
c365395e | 1068 | default: |
8e1c85e3 | 1069 | goto slow_jcc; |
c365395e | 1070 | } |
8e1c85e3 | 1071 | break; |
c365395e | 1072 | |
8e1c85e3 FB |
1073 | default: |
1074 | slow_jcc: | |
69d1aa31 RH |
1075 | /* This actually generates good code for JC, JZ and JS. */ |
1076 | switch (jcc_op) { | |
1077 | case JCC_O: | |
1078 | cc = gen_prepare_eflags_o(s, reg); | |
1079 | break; | |
1080 | case JCC_B: | |
1081 | cc = gen_prepare_eflags_c(s, reg); | |
1082 | break; | |
1083 | case JCC_Z: | |
1084 | cc = gen_prepare_eflags_z(s, reg); | |
1085 | break; | |
1086 | case JCC_BE: | |
1087 | gen_compute_eflags(s); | |
1088 | cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, | |
1089 | .mask = CC_Z | CC_C }; | |
1090 | break; | |
1091 | case JCC_S: | |
1092 | cc = gen_prepare_eflags_s(s, reg); | |
1093 | break; | |
1094 | case JCC_P: | |
1095 | cc = gen_prepare_eflags_p(s, reg); | |
1096 | break; | |
1097 | case JCC_L: | |
1098 | gen_compute_eflags(s); | |
1099 | if (TCGV_EQUAL(reg, cpu_cc_src)) { | |
1100 | reg = cpu_tmp0; | |
1101 | } | |
1102 | tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ | |
1103 | tcg_gen_xor_tl(reg, reg, cpu_cc_src); | |
1104 | cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, | |
1105 | .mask = CC_S }; | |
1106 | break; | |
1107 | default: | |
1108 | case JCC_LE: | |
1109 | gen_compute_eflags(s); | |
1110 | if (TCGV_EQUAL(reg, cpu_cc_src)) { | |
1111 | reg = cpu_tmp0; | |
1112 | } | |
1113 | tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ | |
1114 | tcg_gen_xor_tl(reg, reg, cpu_cc_src); | |
1115 | cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, | |
1116 | .mask = CC_S | CC_Z }; | |
1117 | break; | |
1118 | } | |
c365395e | 1119 | break; |
8e1c85e3 | 1120 | } |
276e6b5f RH |
1121 | |
1122 | if (inv) { | |
1123 | cc.cond = tcg_invert_cond(cc.cond); | |
1124 | } | |
1125 | return cc; | |
8e1c85e3 FB |
1126 | } |
1127 | ||
cc8b6f5b PB |
1128 | static void gen_setcc1(DisasContext *s, int b, TCGv reg) |
1129 | { | |
1130 | CCPrepare cc = gen_prepare_cc(s, b, reg); | |
1131 | ||
1132 | if (cc.no_setcond) { | |
1133 | if (cc.cond == TCG_COND_EQ) { | |
1134 | tcg_gen_xori_tl(reg, cc.reg, 1); | |
1135 | } else { | |
1136 | tcg_gen_mov_tl(reg, cc.reg); | |
1137 | } | |
1138 | return; | |
1139 | } | |
1140 | ||
1141 | if (cc.cond == TCG_COND_NE && !cc.use_reg2 && cc.imm == 0 && | |
1142 | cc.mask != 0 && (cc.mask & (cc.mask - 1)) == 0) { | |
1143 | tcg_gen_shri_tl(reg, cc.reg, ctztl(cc.mask)); | |
1144 | tcg_gen_andi_tl(reg, reg, 1); | |
1145 | return; | |
1146 | } | |
1147 | if (cc.mask != -1) { | |
1148 | tcg_gen_andi_tl(reg, cc.reg, cc.mask); | |
1149 | cc.reg = reg; | |
1150 | } | |
1151 | if (cc.use_reg2) { | |
1152 | tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2); | |
1153 | } else { | |
1154 | tcg_gen_setcondi_tl(cc.cond, reg, cc.reg, cc.imm); | |
1155 | } | |
1156 | } | |
1157 | ||
1158 | static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg) | |
1159 | { | |
1160 | gen_setcc1(s, JCC_B << 1, reg); | |
1161 | } | |
276e6b5f | 1162 | |
8e1c85e3 FB |
1163 | /* generate a conditional jump to label 'l1' according to jump opcode |
1164 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
dc259201 RH |
1165 | static inline void gen_jcc1_noeob(DisasContext *s, int b, int l1) |
1166 | { | |
1167 | CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]); | |
1168 | ||
1169 | if (cc.mask != -1) { | |
1170 | tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask); | |
1171 | cc.reg = cpu_T[0]; | |
1172 | } | |
1173 | if (cc.use_reg2) { | |
1174 | tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); | |
1175 | } else { | |
1176 | tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1); | |
1177 | } | |
1178 | } | |
1179 | ||
1180 | /* Generate a conditional jump to label 'l1' according to jump opcode | |
1181 | value 'b'. In the fast case, T0 is guaranted not to be used. | |
1182 | A translation block must end soon. */ | |
b27fc131 | 1183 | static inline void gen_jcc1(DisasContext *s, int b, int l1) |
8e1c85e3 | 1184 | { |
943131ca | 1185 | CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]); |
8e1c85e3 | 1186 | |
dc259201 | 1187 | gen_update_cc_op(s); |
943131ca PB |
1188 | if (cc.mask != -1) { |
1189 | tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask); | |
1190 | cc.reg = cpu_T[0]; | |
1191 | } | |
dc259201 | 1192 | set_cc_op(s, CC_OP_DYNAMIC); |
943131ca PB |
1193 | if (cc.use_reg2) { |
1194 | tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); | |
1195 | } else { | |
1196 | tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1); | |
8e1c85e3 FB |
1197 | } |
1198 | } | |
1199 | ||
14ce26e7 FB |
1200 | /* XXX: does not work with gdbstub "ice" single step - not a |
1201 | serious problem */ | |
1202 | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) | |
2c0262af | 1203 | { |
14ce26e7 FB |
1204 | int l1, l2; |
1205 | ||
1206 | l1 = gen_new_label(); | |
1207 | l2 = gen_new_label(); | |
6e0d8677 | 1208 | gen_op_jnz_ecx(s->aflag, l1); |
14ce26e7 FB |
1209 | gen_set_label(l2); |
1210 | gen_jmp_tb(s, next_eip, 1); | |
1211 | gen_set_label(l1); | |
1212 | return l2; | |
2c0262af FB |
1213 | } |
1214 | ||
1215 | static inline void gen_stos(DisasContext *s, int ot) | |
1216 | { | |
4ba9938c | 1217 | gen_op_mov_TN_reg(MO_32, 0, R_EAX); |
2c0262af | 1218 | gen_string_movl_A0_EDI(s); |
fd8ca9f6 | 1219 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
6e0d8677 FB |
1220 | gen_op_movl_T0_Dshift(ot); |
1221 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1222 | } |
1223 | ||
1224 | static inline void gen_lods(DisasContext *s, int ot) | |
1225 | { | |
1226 | gen_string_movl_A0_ESI(s); | |
909be183 | 1227 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
57fec1fe | 1228 | gen_op_mov_reg_T0(ot, R_EAX); |
6e0d8677 FB |
1229 | gen_op_movl_T0_Dshift(ot); |
1230 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2c0262af FB |
1231 | } |
1232 | ||
1233 | static inline void gen_scas(DisasContext *s, int ot) | |
1234 | { | |
2c0262af | 1235 | gen_string_movl_A0_EDI(s); |
0f712e10 | 1236 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
63633fe6 | 1237 | gen_op(s, OP_CMPL, ot, R_EAX); |
6e0d8677 FB |
1238 | gen_op_movl_T0_Dshift(ot); |
1239 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1240 | } |
1241 | ||
1242 | static inline void gen_cmps(DisasContext *s, int ot) | |
1243 | { | |
2c0262af | 1244 | gen_string_movl_A0_EDI(s); |
0f712e10 | 1245 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
63633fe6 RH |
1246 | gen_string_movl_A0_ESI(s); |
1247 | gen_op(s, OP_CMPL, ot, OR_TMP0); | |
6e0d8677 FB |
1248 | gen_op_movl_T0_Dshift(ot); |
1249 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
1250 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1251 | } |
1252 | ||
1253 | static inline void gen_ins(DisasContext *s, int ot) | |
1254 | { | |
2e70f6ef PB |
1255 | if (use_icount) |
1256 | gen_io_start(); | |
2c0262af | 1257 | gen_string_movl_A0_EDI(s); |
6e0d8677 FB |
1258 | /* Note: we must do this dummy write first to be restartable in |
1259 | case of page fault. */ | |
9772c73b | 1260 | gen_op_movl_T0_0(); |
fd8ca9f6 | 1261 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
4ba9938c | 1262 | gen_op_mov_TN_reg(MO_16, 1, R_EDX); |
b6abf97d FB |
1263 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1264 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
a7812ae4 | 1265 | gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); |
fd8ca9f6 | 1266 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
6e0d8677 FB |
1267 | gen_op_movl_T0_Dshift(ot); |
1268 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2e70f6ef PB |
1269 | if (use_icount) |
1270 | gen_io_end(); | |
2c0262af FB |
1271 | } |
1272 | ||
1273 | static inline void gen_outs(DisasContext *s, int ot) | |
1274 | { | |
2e70f6ef PB |
1275 | if (use_icount) |
1276 | gen_io_start(); | |
2c0262af | 1277 | gen_string_movl_A0_ESI(s); |
909be183 | 1278 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
b8b6a50b | 1279 | |
4ba9938c | 1280 | gen_op_mov_TN_reg(MO_16, 1, R_EDX); |
b6abf97d FB |
1281 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1282 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
1283 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); | |
a7812ae4 | 1284 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
b8b6a50b | 1285 | |
6e0d8677 FB |
1286 | gen_op_movl_T0_Dshift(ot); |
1287 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2e70f6ef PB |
1288 | if (use_icount) |
1289 | gen_io_end(); | |
2c0262af FB |
1290 | } |
1291 | ||
1292 | /* same method as Valgrind : we generate jumps to current or next | |
1293 | instruction */ | |
1294 | #define GEN_REPZ(op) \ | |
1295 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 | 1296 | target_ulong cur_eip, target_ulong next_eip) \ |
2c0262af | 1297 | { \ |
14ce26e7 | 1298 | int l2;\ |
2c0262af | 1299 | gen_update_cc_op(s); \ |
14ce26e7 | 1300 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1301 | gen_ ## op(s, ot); \ |
6e0d8677 | 1302 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af FB |
1303 | /* a loop would cause two single step exceptions if ECX = 1 \ |
1304 | before rep string_insn */ \ | |
1305 | if (!s->jmp_opt) \ | |
6e0d8677 | 1306 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1307 | gen_jmp(s, cur_eip); \ |
1308 | } | |
1309 | ||
1310 | #define GEN_REPZ2(op) \ | |
1311 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 FB |
1312 | target_ulong cur_eip, \ |
1313 | target_ulong next_eip, \ | |
2c0262af FB |
1314 | int nz) \ |
1315 | { \ | |
14ce26e7 | 1316 | int l2;\ |
2c0262af | 1317 | gen_update_cc_op(s); \ |
14ce26e7 | 1318 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1319 | gen_ ## op(s, ot); \ |
6e0d8677 | 1320 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
773cdfcc | 1321 | gen_update_cc_op(s); \ |
b27fc131 | 1322 | gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \ |
2c0262af | 1323 | if (!s->jmp_opt) \ |
6e0d8677 | 1324 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1325 | gen_jmp(s, cur_eip); \ |
1326 | } | |
1327 | ||
1328 | GEN_REPZ(movs) | |
1329 | GEN_REPZ(stos) | |
1330 | GEN_REPZ(lods) | |
1331 | GEN_REPZ(ins) | |
1332 | GEN_REPZ(outs) | |
1333 | GEN_REPZ2(scas) | |
1334 | GEN_REPZ2(cmps) | |
1335 | ||
a7812ae4 PB |
1336 | static void gen_helper_fp_arith_ST0_FT0(int op) |
1337 | { | |
1338 | switch (op) { | |
d3eb5eae BS |
1339 | case 0: |
1340 | gen_helper_fadd_ST0_FT0(cpu_env); | |
1341 | break; | |
1342 | case 1: | |
1343 | gen_helper_fmul_ST0_FT0(cpu_env); | |
1344 | break; | |
1345 | case 2: | |
1346 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1347 | break; | |
1348 | case 3: | |
1349 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1350 | break; | |
1351 | case 4: | |
1352 | gen_helper_fsub_ST0_FT0(cpu_env); | |
1353 | break; | |
1354 | case 5: | |
1355 | gen_helper_fsubr_ST0_FT0(cpu_env); | |
1356 | break; | |
1357 | case 6: | |
1358 | gen_helper_fdiv_ST0_FT0(cpu_env); | |
1359 | break; | |
1360 | case 7: | |
1361 | gen_helper_fdivr_ST0_FT0(cpu_env); | |
1362 | break; | |
a7812ae4 PB |
1363 | } |
1364 | } | |
2c0262af FB |
1365 | |
1366 | /* NOTE the exception in "r" op ordering */ | |
a7812ae4 PB |
1367 | static void gen_helper_fp_arith_STN_ST0(int op, int opreg) |
1368 | { | |
1369 | TCGv_i32 tmp = tcg_const_i32(opreg); | |
1370 | switch (op) { | |
d3eb5eae BS |
1371 | case 0: |
1372 | gen_helper_fadd_STN_ST0(cpu_env, tmp); | |
1373 | break; | |
1374 | case 1: | |
1375 | gen_helper_fmul_STN_ST0(cpu_env, tmp); | |
1376 | break; | |
1377 | case 4: | |
1378 | gen_helper_fsubr_STN_ST0(cpu_env, tmp); | |
1379 | break; | |
1380 | case 5: | |
1381 | gen_helper_fsub_STN_ST0(cpu_env, tmp); | |
1382 | break; | |
1383 | case 6: | |
1384 | gen_helper_fdivr_STN_ST0(cpu_env, tmp); | |
1385 | break; | |
1386 | case 7: | |
1387 | gen_helper_fdiv_STN_ST0(cpu_env, tmp); | |
1388 | break; | |
a7812ae4 PB |
1389 | } |
1390 | } | |
2c0262af FB |
1391 | |
1392 | /* if d == OR_TMP0, it means memory operand (address in A0) */ | |
1393 | static void gen_op(DisasContext *s1, int op, int ot, int d) | |
1394 | { | |
2c0262af | 1395 | if (d != OR_TMP0) { |
57fec1fe | 1396 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1397 | } else { |
909be183 | 1398 | gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0); |
2c0262af FB |
1399 | } |
1400 | switch(op) { | |
1401 | case OP_ADCL: | |
cc8b6f5b | 1402 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1403 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1404 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
d4faa3e0 | 1405 | gen_op_st_rm_T0_A0(s1, ot, d); |
988c3eb0 RH |
1406 | gen_op_update3_cc(cpu_tmp4); |
1407 | set_cc_op(s1, CC_OP_ADCB + ot); | |
cad3a37d | 1408 | break; |
2c0262af | 1409 | case OP_SBBL: |
cc8b6f5b | 1410 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1411 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1412 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
d4faa3e0 | 1413 | gen_op_st_rm_T0_A0(s1, ot, d); |
988c3eb0 RH |
1414 | gen_op_update3_cc(cpu_tmp4); |
1415 | set_cc_op(s1, CC_OP_SBBB + ot); | |
cad3a37d | 1416 | break; |
2c0262af FB |
1417 | case OP_ADDL: |
1418 | gen_op_addl_T0_T1(); | |
d4faa3e0 | 1419 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1420 | gen_op_update2_cc(); |
3ca51d07 | 1421 | set_cc_op(s1, CC_OP_ADDB + ot); |
2c0262af FB |
1422 | break; |
1423 | case OP_SUBL: | |
a3251186 | 1424 | tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]); |
57fec1fe | 1425 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
d4faa3e0 | 1426 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1427 | gen_op_update2_cc(); |
3ca51d07 | 1428 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1429 | break; |
1430 | default: | |
1431 | case OP_ANDL: | |
57fec1fe | 1432 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
d4faa3e0 | 1433 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1434 | gen_op_update1_cc(); |
3ca51d07 | 1435 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1436 | break; |
2c0262af | 1437 | case OP_ORL: |
57fec1fe | 1438 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
d4faa3e0 | 1439 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1440 | gen_op_update1_cc(); |
3ca51d07 | 1441 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1442 | break; |
2c0262af | 1443 | case OP_XORL: |
57fec1fe | 1444 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
d4faa3e0 | 1445 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1446 | gen_op_update1_cc(); |
3ca51d07 | 1447 | set_cc_op(s1, CC_OP_LOGICB + ot); |
2c0262af FB |
1448 | break; |
1449 | case OP_CMPL: | |
63633fe6 | 1450 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); |
a3251186 | 1451 | tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]); |
63633fe6 | 1452 | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
3ca51d07 | 1453 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1454 | break; |
1455 | } | |
b6abf97d FB |
1456 | } |
1457 | ||
2c0262af FB |
1458 | /* if d == OR_TMP0, it means memory operand (address in A0) */ |
1459 | static void gen_inc(DisasContext *s1, int ot, int d, int c) | |
1460 | { | |
909be183 | 1461 | if (d != OR_TMP0) { |
57fec1fe | 1462 | gen_op_mov_TN_reg(ot, 0, d); |
909be183 RH |
1463 | } else { |
1464 | gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0); | |
1465 | } | |
cc8b6f5b | 1466 | gen_compute_eflags_c(s1, cpu_cc_src); |
2c0262af | 1467 | if (c > 0) { |
b6abf97d | 1468 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
3ca51d07 | 1469 | set_cc_op(s1, CC_OP_INCB + ot); |
2c0262af | 1470 | } else { |
b6abf97d | 1471 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
3ca51d07 | 1472 | set_cc_op(s1, CC_OP_DECB + ot); |
2c0262af | 1473 | } |
d4faa3e0 | 1474 | gen_op_st_rm_T0_A0(s1, ot, d); |
cd31fefa | 1475 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
2c0262af FB |
1476 | } |
1477 | ||
f437d0a3 RH |
1478 | static void gen_shift_flags(DisasContext *s, int ot, TCGv result, TCGv shm1, |
1479 | TCGv count, bool is_right) | |
1480 | { | |
1481 | TCGv_i32 z32, s32, oldop; | |
1482 | TCGv z_tl; | |
1483 | ||
1484 | /* Store the results into the CC variables. If we know that the | |
1485 | variable must be dead, store unconditionally. Otherwise we'll | |
1486 | need to not disrupt the current contents. */ | |
1487 | z_tl = tcg_const_tl(0); | |
1488 | if (cc_op_live[s->cc_op] & USES_CC_DST) { | |
1489 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl, | |
1490 | result, cpu_cc_dst); | |
1491 | } else { | |
1492 | tcg_gen_mov_tl(cpu_cc_dst, result); | |
1493 | } | |
1494 | if (cc_op_live[s->cc_op] & USES_CC_SRC) { | |
1495 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_src, count, z_tl, | |
1496 | shm1, cpu_cc_src); | |
1497 | } else { | |
1498 | tcg_gen_mov_tl(cpu_cc_src, shm1); | |
1499 | } | |
1500 | tcg_temp_free(z_tl); | |
1501 | ||
1502 | /* Get the two potential CC_OP values into temporaries. */ | |
1503 | tcg_gen_movi_i32(cpu_tmp2_i32, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot); | |
1504 | if (s->cc_op == CC_OP_DYNAMIC) { | |
1505 | oldop = cpu_cc_op; | |
1506 | } else { | |
1507 | tcg_gen_movi_i32(cpu_tmp3_i32, s->cc_op); | |
1508 | oldop = cpu_tmp3_i32; | |
1509 | } | |
1510 | ||
1511 | /* Conditionally store the CC_OP value. */ | |
1512 | z32 = tcg_const_i32(0); | |
1513 | s32 = tcg_temp_new_i32(); | |
1514 | tcg_gen_trunc_tl_i32(s32, count); | |
1515 | tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, cpu_tmp2_i32, oldop); | |
1516 | tcg_temp_free_i32(z32); | |
1517 | tcg_temp_free_i32(s32); | |
1518 | ||
1519 | /* The CC_OP value is no longer predictable. */ | |
1520 | set_cc_op(s, CC_OP_DYNAMIC); | |
1521 | } | |
1522 | ||
b6abf97d FB |
1523 | static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
1524 | int is_right, int is_arith) | |
2c0262af | 1525 | { |
4ba9938c | 1526 | target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f); |
3b46e624 | 1527 | |
b6abf97d | 1528 | /* load */ |
82786041 | 1529 | if (op1 == OR_TMP0) { |
909be183 | 1530 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
82786041 | 1531 | } else { |
b6abf97d | 1532 | gen_op_mov_TN_reg(ot, 0, op1); |
82786041 | 1533 | } |
b6abf97d | 1534 | |
a41f62f5 RH |
1535 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); |
1536 | tcg_gen_subi_tl(cpu_tmp0, cpu_T[1], 1); | |
b6abf97d FB |
1537 | |
1538 | if (is_right) { | |
1539 | if (is_arith) { | |
f484d386 | 1540 | gen_exts(ot, cpu_T[0]); |
a41f62f5 RH |
1541 | tcg_gen_sar_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); |
1542 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
b6abf97d | 1543 | } else { |
cad3a37d | 1544 | gen_extu(ot, cpu_T[0]); |
a41f62f5 RH |
1545 | tcg_gen_shr_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); |
1546 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
b6abf97d FB |
1547 | } |
1548 | } else { | |
a41f62f5 RH |
1549 | tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); |
1550 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
b6abf97d FB |
1551 | } |
1552 | ||
1553 | /* store */ | |
d4faa3e0 | 1554 | gen_op_st_rm_T0_A0(s, ot, op1); |
82786041 | 1555 | |
f437d0a3 | 1556 | gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, cpu_T[1], is_right); |
b6abf97d FB |
1557 | } |
1558 | ||
c1c37968 FB |
1559 | static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, |
1560 | int is_right, int is_arith) | |
1561 | { | |
4ba9938c | 1562 | int mask = (ot == MO_64 ? 0x3f : 0x1f); |
c1c37968 FB |
1563 | |
1564 | /* load */ | |
1565 | if (op1 == OR_TMP0) | |
909be183 | 1566 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
c1c37968 FB |
1567 | else |
1568 | gen_op_mov_TN_reg(ot, 0, op1); | |
1569 | ||
1570 | op2 &= mask; | |
1571 | if (op2 != 0) { | |
1572 | if (is_right) { | |
1573 | if (is_arith) { | |
1574 | gen_exts(ot, cpu_T[0]); | |
2a449d14 | 1575 | tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1576 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
1577 | } else { | |
1578 | gen_extu(ot, cpu_T[0]); | |
2a449d14 | 1579 | tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1580 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
1581 | } | |
1582 | } else { | |
2a449d14 | 1583 | tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1584 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
1585 | } | |
1586 | } | |
1587 | ||
1588 | /* store */ | |
d4faa3e0 RH |
1589 | gen_op_st_rm_T0_A0(s, ot, op1); |
1590 | ||
c1c37968 FB |
1591 | /* update eflags if non zero shift */ |
1592 | if (op2 != 0) { | |
2a449d14 | 1593 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
c1c37968 | 1594 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
3ca51d07 | 1595 | set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot); |
c1c37968 FB |
1596 | } |
1597 | } | |
1598 | ||
b6abf97d FB |
1599 | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1600 | { | |
1601 | if (arg2 >= 0) | |
1602 | tcg_gen_shli_tl(ret, arg1, arg2); | |
1603 | else | |
1604 | tcg_gen_shri_tl(ret, arg1, -arg2); | |
1605 | } | |
1606 | ||
34d80a55 | 1607 | static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right) |
b6abf97d | 1608 | { |
4ba9938c | 1609 | target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f); |
34d80a55 | 1610 | TCGv_i32 t0, t1; |
b6abf97d FB |
1611 | |
1612 | /* load */ | |
1e4840bf | 1613 | if (op1 == OR_TMP0) { |
909be183 | 1614 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
1e4840bf | 1615 | } else { |
34d80a55 | 1616 | gen_op_mov_TN_reg(ot, 0, op1); |
1e4840bf | 1617 | } |
b6abf97d | 1618 | |
34d80a55 | 1619 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); |
b6abf97d | 1620 | |
34d80a55 | 1621 | switch (ot) { |
4ba9938c | 1622 | case MO_8: |
34d80a55 RH |
1623 | /* Replicate the 8-bit input so that a 32-bit rotate works. */ |
1624 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); | |
1625 | tcg_gen_muli_tl(cpu_T[0], cpu_T[0], 0x01010101); | |
1626 | goto do_long; | |
4ba9938c | 1627 | case MO_16: |
34d80a55 RH |
1628 | /* Replicate the 16-bit input so that a 32-bit rotate works. */ |
1629 | tcg_gen_deposit_tl(cpu_T[0], cpu_T[0], cpu_T[0], 16, 16); | |
1630 | goto do_long; | |
1631 | do_long: | |
1632 | #ifdef TARGET_X86_64 | |
4ba9938c | 1633 | case MO_32: |
34d80a55 RH |
1634 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
1635 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); | |
1636 | if (is_right) { | |
1637 | tcg_gen_rotr_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); | |
1638 | } else { | |
1639 | tcg_gen_rotl_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); | |
1640 | } | |
1641 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); | |
1642 | break; | |
1643 | #endif | |
1644 | default: | |
1645 | if (is_right) { | |
1646 | tcg_gen_rotr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1647 | } else { | |
1648 | tcg_gen_rotl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1649 | } | |
1650 | break; | |
b6abf97d | 1651 | } |
b6abf97d | 1652 | |
b6abf97d | 1653 | /* store */ |
d4faa3e0 | 1654 | gen_op_st_rm_T0_A0(s, ot, op1); |
b6abf97d | 1655 | |
34d80a55 RH |
1656 | /* We'll need the flags computed into CC_SRC. */ |
1657 | gen_compute_eflags(s); | |
b6abf97d | 1658 | |
34d80a55 RH |
1659 | /* The value that was "rotated out" is now present at the other end |
1660 | of the word. Compute C into CC_DST and O into CC_SRC2. Note that | |
1661 | since we've computed the flags into CC_SRC, these variables are | |
1662 | currently dead. */ | |
b6abf97d | 1663 | if (is_right) { |
34d80a55 RH |
1664 | tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1); |
1665 | tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask); | |
089305ac | 1666 | tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1); |
34d80a55 RH |
1667 | } else { |
1668 | tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask); | |
1669 | tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1); | |
b6abf97d | 1670 | } |
34d80a55 RH |
1671 | tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1); |
1672 | tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst); | |
1673 | ||
1674 | /* Now conditionally store the new CC_OP value. If the shift count | |
1675 | is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live. | |
1676 | Otherwise reuse CC_OP_ADCOX which have the C and O flags split out | |
1677 | exactly as we computed above. */ | |
1678 | t0 = tcg_const_i32(0); | |
1679 | t1 = tcg_temp_new_i32(); | |
1680 | tcg_gen_trunc_tl_i32(t1, cpu_T[1]); | |
1681 | tcg_gen_movi_i32(cpu_tmp2_i32, CC_OP_ADCOX); | |
1682 | tcg_gen_movi_i32(cpu_tmp3_i32, CC_OP_EFLAGS); | |
1683 | tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, t1, t0, | |
1684 | cpu_tmp2_i32, cpu_tmp3_i32); | |
1685 | tcg_temp_free_i32(t0); | |
1686 | tcg_temp_free_i32(t1); | |
1687 | ||
1688 | /* The CC_OP value is no longer predictable. */ | |
1689 | set_cc_op(s, CC_OP_DYNAMIC); | |
b6abf97d FB |
1690 | } |
1691 | ||
8cd6345d | 1692 | static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, |
1693 | int is_right) | |
1694 | { | |
4ba9938c | 1695 | int mask = (ot == MO_64 ? 0x3f : 0x1f); |
34d80a55 | 1696 | int shift; |
8cd6345d | 1697 | |
1698 | /* load */ | |
1699 | if (op1 == OR_TMP0) { | |
909be183 | 1700 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
8cd6345d | 1701 | } else { |
34d80a55 | 1702 | gen_op_mov_TN_reg(ot, 0, op1); |
8cd6345d | 1703 | } |
1704 | ||
8cd6345d | 1705 | op2 &= mask; |
8cd6345d | 1706 | if (op2 != 0) { |
34d80a55 RH |
1707 | switch (ot) { |
1708 | #ifdef TARGET_X86_64 | |
4ba9938c | 1709 | case MO_32: |
34d80a55 RH |
1710 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
1711 | if (is_right) { | |
1712 | tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2); | |
1713 | } else { | |
1714 | tcg_gen_rotli_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2); | |
1715 | } | |
1716 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); | |
1717 | break; | |
1718 | #endif | |
1719 | default: | |
1720 | if (is_right) { | |
1721 | tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], op2); | |
1722 | } else { | |
1723 | tcg_gen_rotli_tl(cpu_T[0], cpu_T[0], op2); | |
1724 | } | |
1725 | break; | |
4ba9938c | 1726 | case MO_8: |
34d80a55 RH |
1727 | mask = 7; |
1728 | goto do_shifts; | |
4ba9938c | 1729 | case MO_16: |
34d80a55 RH |
1730 | mask = 15; |
1731 | do_shifts: | |
1732 | shift = op2 & mask; | |
1733 | if (is_right) { | |
1734 | shift = mask + 1 - shift; | |
1735 | } | |
1736 | gen_extu(ot, cpu_T[0]); | |
1737 | tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], shift); | |
1738 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], mask + 1 - shift); | |
1739 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
1740 | break; | |
8cd6345d | 1741 | } |
8cd6345d | 1742 | } |
1743 | ||
1744 | /* store */ | |
d4faa3e0 | 1745 | gen_op_st_rm_T0_A0(s, ot, op1); |
8cd6345d | 1746 | |
1747 | if (op2 != 0) { | |
34d80a55 | 1748 | /* Compute the flags into CC_SRC. */ |
d229edce | 1749 | gen_compute_eflags(s); |
0ff6addd | 1750 | |
34d80a55 RH |
1751 | /* The value that was "rotated out" is now present at the other end |
1752 | of the word. Compute C into CC_DST and O into CC_SRC2. Note that | |
1753 | since we've computed the flags into CC_SRC, these variables are | |
1754 | currently dead. */ | |
8cd6345d | 1755 | if (is_right) { |
34d80a55 RH |
1756 | tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1); |
1757 | tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask); | |
38ebb396 | 1758 | tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1); |
34d80a55 RH |
1759 | } else { |
1760 | tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask); | |
1761 | tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1); | |
8cd6345d | 1762 | } |
34d80a55 RH |
1763 | tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1); |
1764 | tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst); | |
1765 | set_cc_op(s, CC_OP_ADCOX); | |
8cd6345d | 1766 | } |
8cd6345d | 1767 | } |
1768 | ||
b6abf97d FB |
1769 | /* XXX: add faster immediate = 1 case */ |
1770 | static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, | |
1771 | int is_right) | |
1772 | { | |
d229edce | 1773 | gen_compute_eflags(s); |
c7b3c873 | 1774 | assert(s->cc_op == CC_OP_EFLAGS); |
b6abf97d FB |
1775 | |
1776 | /* load */ | |
1777 | if (op1 == OR_TMP0) | |
909be183 | 1778 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
b6abf97d FB |
1779 | else |
1780 | gen_op_mov_TN_reg(ot, 0, op1); | |
1781 | ||
a7812ae4 PB |
1782 | if (is_right) { |
1783 | switch (ot) { | |
4ba9938c | 1784 | case MO_8: |
7923057b BS |
1785 | gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1786 | break; | |
4ba9938c | 1787 | case MO_16: |
7923057b BS |
1788 | gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1789 | break; | |
4ba9938c | 1790 | case MO_32: |
7923057b BS |
1791 | gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1792 | break; | |
a7812ae4 | 1793 | #ifdef TARGET_X86_64 |
4ba9938c | 1794 | case MO_64: |
7923057b BS |
1795 | gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1796 | break; | |
a7812ae4 PB |
1797 | #endif |
1798 | } | |
1799 | } else { | |
1800 | switch (ot) { | |
4ba9938c | 1801 | case MO_8: |
7923057b BS |
1802 | gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1803 | break; | |
4ba9938c | 1804 | case MO_16: |
7923057b BS |
1805 | gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1806 | break; | |
4ba9938c | 1807 | case MO_32: |
7923057b BS |
1808 | gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1809 | break; | |
a7812ae4 | 1810 | #ifdef TARGET_X86_64 |
4ba9938c | 1811 | case MO_64: |
7923057b BS |
1812 | gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1813 | break; | |
a7812ae4 PB |
1814 | #endif |
1815 | } | |
1816 | } | |
b6abf97d | 1817 | /* store */ |
d4faa3e0 | 1818 | gen_op_st_rm_T0_A0(s, ot, op1); |
b6abf97d FB |
1819 | } |
1820 | ||
1821 | /* XXX: add faster immediate case */ | |
3b9d3cf1 | 1822 | static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1, |
f437d0a3 | 1823 | bool is_right, TCGv count_in) |
b6abf97d | 1824 | { |
4ba9938c | 1825 | target_ulong mask = (ot == MO_64 ? 63 : 31); |
f437d0a3 | 1826 | TCGv count; |
b6abf97d FB |
1827 | |
1828 | /* load */ | |
1e4840bf | 1829 | if (op1 == OR_TMP0) { |
909be183 | 1830 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
1e4840bf | 1831 | } else { |
f437d0a3 | 1832 | gen_op_mov_TN_reg(ot, 0, op1); |
1e4840bf | 1833 | } |
b6abf97d | 1834 | |
f437d0a3 RH |
1835 | count = tcg_temp_new(); |
1836 | tcg_gen_andi_tl(count, count_in, mask); | |
1e4840bf | 1837 | |
f437d0a3 | 1838 | switch (ot) { |
4ba9938c | 1839 | case MO_16: |
f437d0a3 RH |
1840 | /* Note: we implement the Intel behaviour for shift count > 16. |
1841 | This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A | |
1842 | portion by constructing it as a 32-bit value. */ | |
b6abf97d | 1843 | if (is_right) { |
f437d0a3 RH |
1844 | tcg_gen_deposit_tl(cpu_tmp0, cpu_T[0], cpu_T[1], 16, 16); |
1845 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); | |
1846 | tcg_gen_mov_tl(cpu_T[0], cpu_tmp0); | |
b6abf97d | 1847 | } else { |
f437d0a3 | 1848 | tcg_gen_deposit_tl(cpu_T[1], cpu_T[0], cpu_T[1], 16, 16); |
b6abf97d | 1849 | } |
f437d0a3 RH |
1850 | /* FALLTHRU */ |
1851 | #ifdef TARGET_X86_64 | |
4ba9938c | 1852 | case MO_32: |
f437d0a3 RH |
1853 | /* Concatenate the two 32-bit values and use a 64-bit shift. */ |
1854 | tcg_gen_subi_tl(cpu_tmp0, count, 1); | |
b6abf97d | 1855 | if (is_right) { |
f437d0a3 RH |
1856 | tcg_gen_concat_tl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
1857 | tcg_gen_shr_i64(cpu_tmp0, cpu_T[0], cpu_tmp0); | |
1858 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], count); | |
1859 | } else { | |
1860 | tcg_gen_concat_tl_i64(cpu_T[0], cpu_T[1], cpu_T[0]); | |
1861 | tcg_gen_shl_i64(cpu_tmp0, cpu_T[0], cpu_tmp0); | |
1862 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], count); | |
1863 | tcg_gen_shri_i64(cpu_tmp0, cpu_tmp0, 32); | |
1864 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], 32); | |
1865 | } | |
1866 | break; | |
1867 | #endif | |
1868 | default: | |
1869 | tcg_gen_subi_tl(cpu_tmp0, count, 1); | |
1870 | if (is_right) { | |
1871 | tcg_gen_shr_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); | |
b6abf97d | 1872 | |
f437d0a3 RH |
1873 | tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count); |
1874 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], count); | |
1875 | tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp4); | |
b6abf97d | 1876 | } else { |
f437d0a3 | 1877 | tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); |
4ba9938c | 1878 | if (ot == MO_16) { |
f437d0a3 RH |
1879 | /* Only needed if count > 16, for Intel behaviour. */ |
1880 | tcg_gen_subfi_tl(cpu_tmp4, 33, count); | |
1881 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[1], cpu_tmp4); | |
1882 | tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, cpu_tmp4); | |
1883 | } | |
1884 | ||
1885 | tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count); | |
1886 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], count); | |
1887 | tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp4); | |
b6abf97d | 1888 | } |
f437d0a3 RH |
1889 | tcg_gen_movi_tl(cpu_tmp4, 0); |
1890 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[1], count, cpu_tmp4, | |
1891 | cpu_tmp4, cpu_T[1]); | |
1892 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1893 | break; | |
b6abf97d | 1894 | } |
b6abf97d | 1895 | |
b6abf97d | 1896 | /* store */ |
d4faa3e0 | 1897 | gen_op_st_rm_T0_A0(s, ot, op1); |
1e4840bf | 1898 | |
f437d0a3 RH |
1899 | gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, count, is_right); |
1900 | tcg_temp_free(count); | |
b6abf97d FB |
1901 | } |
1902 | ||
1903 | static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) | |
1904 | { | |
1905 | if (s != OR_TMP1) | |
1906 | gen_op_mov_TN_reg(ot, 1, s); | |
1907 | switch(op) { | |
1908 | case OP_ROL: | |
1909 | gen_rot_rm_T1(s1, ot, d, 0); | |
1910 | break; | |
1911 | case OP_ROR: | |
1912 | gen_rot_rm_T1(s1, ot, d, 1); | |
1913 | break; | |
1914 | case OP_SHL: | |
1915 | case OP_SHL1: | |
1916 | gen_shift_rm_T1(s1, ot, d, 0, 0); | |
1917 | break; | |
1918 | case OP_SHR: | |
1919 | gen_shift_rm_T1(s1, ot, d, 1, 0); | |
1920 | break; | |
1921 | case OP_SAR: | |
1922 | gen_shift_rm_T1(s1, ot, d, 1, 1); | |
1923 | break; | |
1924 | case OP_RCL: | |
1925 | gen_rotc_rm_T1(s1, ot, d, 0); | |
1926 | break; | |
1927 | case OP_RCR: | |
1928 | gen_rotc_rm_T1(s1, ot, d, 1); | |
1929 | break; | |
1930 | } | |
2c0262af FB |
1931 | } |
1932 | ||
1933 | static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) | |
1934 | { | |
c1c37968 | 1935 | switch(op) { |
8cd6345d | 1936 | case OP_ROL: |
1937 | gen_rot_rm_im(s1, ot, d, c, 0); | |
1938 | break; | |
1939 | case OP_ROR: | |
1940 | gen_rot_rm_im(s1, ot, d, c, 1); | |
1941 | break; | |
c1c37968 FB |
1942 | case OP_SHL: |
1943 | case OP_SHL1: | |
1944 | gen_shift_rm_im(s1, ot, d, c, 0, 0); | |
1945 | break; | |
1946 | case OP_SHR: | |
1947 | gen_shift_rm_im(s1, ot, d, c, 1, 0); | |
1948 | break; | |
1949 | case OP_SAR: | |
1950 | gen_shift_rm_im(s1, ot, d, c, 1, 1); | |
1951 | break; | |
1952 | default: | |
1953 | /* currently not optimized */ | |
1954 | gen_op_movl_T1_im(c); | |
1955 | gen_shift(s1, op, ot, d, OR_TMP1); | |
1956 | break; | |
1957 | } | |
2c0262af FB |
1958 | } |
1959 | ||
4eeb3939 | 1960 | static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm) |
2c0262af | 1961 | { |
14ce26e7 | 1962 | target_long disp; |
2c0262af | 1963 | int havesib; |
14ce26e7 | 1964 | int base; |
2c0262af FB |
1965 | int index; |
1966 | int scale; | |
2c0262af | 1967 | int mod, rm, code, override, must_add_seg; |
7865eec4 | 1968 | TCGv sum; |
2c0262af FB |
1969 | |
1970 | override = s->override; | |
1971 | must_add_seg = s->addseg; | |
1972 | if (override >= 0) | |
1973 | must_add_seg = 1; | |
1974 | mod = (modrm >> 6) & 3; | |
1975 | rm = modrm & 7; | |
1976 | ||
1977 | if (s->aflag) { | |
2c0262af FB |
1978 | havesib = 0; |
1979 | base = rm; | |
7865eec4 | 1980 | index = -1; |
2c0262af | 1981 | scale = 0; |
3b46e624 | 1982 | |
2c0262af FB |
1983 | if (base == 4) { |
1984 | havesib = 1; | |
0af10c86 | 1985 | code = cpu_ldub_code(env, s->pc++); |
2c0262af | 1986 | scale = (code >> 6) & 3; |
14ce26e7 | 1987 | index = ((code >> 3) & 7) | REX_X(s); |
7865eec4 RH |
1988 | if (index == 4) { |
1989 | index = -1; /* no index */ | |
1990 | } | |
14ce26e7 | 1991 | base = (code & 7); |
2c0262af | 1992 | } |
14ce26e7 | 1993 | base |= REX_B(s); |
2c0262af FB |
1994 | |
1995 | switch (mod) { | |
1996 | case 0: | |
14ce26e7 | 1997 | if ((base & 7) == 5) { |
2c0262af | 1998 | base = -1; |
0af10c86 | 1999 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af | 2000 | s->pc += 4; |
14ce26e7 FB |
2001 | if (CODE64(s) && !havesib) { |
2002 | disp += s->pc + s->rip_offset; | |
2003 | } | |
2c0262af FB |
2004 | } else { |
2005 | disp = 0; | |
2006 | } | |
2007 | break; | |
2008 | case 1: | |
0af10c86 | 2009 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
2010 | break; |
2011 | default: | |
2012 | case 2: | |
0af10c86 | 2013 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af FB |
2014 | s->pc += 4; |
2015 | break; | |
2016 | } | |
3b46e624 | 2017 | |
7865eec4 RH |
2018 | /* For correct popl handling with esp. */ |
2019 | if (base == R_ESP && s->popl_esp_hack) { | |
2020 | disp += s->popl_esp_hack; | |
2021 | } | |
2022 | ||
2023 | /* Compute the address, with a minimum number of TCG ops. */ | |
2024 | TCGV_UNUSED(sum); | |
2025 | if (index >= 0) { | |
2026 | if (scale == 0) { | |
2027 | sum = cpu_regs[index]; | |
2028 | } else { | |
2029 | tcg_gen_shli_tl(cpu_A0, cpu_regs[index], scale); | |
2030 | sum = cpu_A0; | |
14ce26e7 | 2031 | } |
7865eec4 RH |
2032 | if (base >= 0) { |
2033 | tcg_gen_add_tl(cpu_A0, sum, cpu_regs[base]); | |
2034 | sum = cpu_A0; | |
14ce26e7 | 2035 | } |
7865eec4 RH |
2036 | } else if (base >= 0) { |
2037 | sum = cpu_regs[base]; | |
2c0262af | 2038 | } |
7865eec4 RH |
2039 | if (TCGV_IS_UNUSED(sum)) { |
2040 | tcg_gen_movi_tl(cpu_A0, disp); | |
2041 | } else { | |
2042 | tcg_gen_addi_tl(cpu_A0, sum, disp); | |
2c0262af | 2043 | } |
7865eec4 | 2044 | |
2c0262af FB |
2045 | if (must_add_seg) { |
2046 | if (override < 0) { | |
7865eec4 | 2047 | if (base == R_EBP || base == R_ESP) { |
2c0262af | 2048 | override = R_SS; |
7865eec4 | 2049 | } else { |
2c0262af | 2050 | override = R_DS; |
7865eec4 | 2051 | } |
2c0262af | 2052 | } |
7865eec4 RH |
2053 | |
2054 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, | |
2055 | offsetof(CPUX86State, segs[override].base)); | |
2056 | if (CODE64(s)) { | |
2057 | if (s->aflag != 2) { | |
2058 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
2059 | } | |
2060 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
4eeb3939 | 2061 | return; |
14ce26e7 | 2062 | } |
7865eec4 RH |
2063 | |
2064 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
2065 | } | |
2066 | ||
2067 | if (s->aflag != 2) { | |
2068 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
2c0262af FB |
2069 | } |
2070 | } else { | |
2071 | switch (mod) { | |
2072 | case 0: | |
2073 | if (rm == 6) { | |
0af10c86 | 2074 | disp = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2075 | s->pc += 2; |
2076 | gen_op_movl_A0_im(disp); | |
2077 | rm = 0; /* avoid SS override */ | |
2078 | goto no_rm; | |
2079 | } else { | |
2080 | disp = 0; | |
2081 | } | |
2082 | break; | |
2083 | case 1: | |
0af10c86 | 2084 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
2085 | break; |
2086 | default: | |
2087 | case 2: | |
0af10c86 | 2088 | disp = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2089 | s->pc += 2; |
2090 | break; | |
2091 | } | |
2092 | switch(rm) { | |
2093 | case 0: | |
57fec1fe FB |
2094 | gen_op_movl_A0_reg(R_EBX); |
2095 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2096 | break; |
2097 | case 1: | |
57fec1fe FB |
2098 | gen_op_movl_A0_reg(R_EBX); |
2099 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2100 | break; |
2101 | case 2: | |
57fec1fe FB |
2102 | gen_op_movl_A0_reg(R_EBP); |
2103 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2104 | break; |
2105 | case 3: | |
57fec1fe FB |
2106 | gen_op_movl_A0_reg(R_EBP); |
2107 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2108 | break; |
2109 | case 4: | |
57fec1fe | 2110 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
2111 | break; |
2112 | case 5: | |
57fec1fe | 2113 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
2114 | break; |
2115 | case 6: | |
57fec1fe | 2116 | gen_op_movl_A0_reg(R_EBP); |
2c0262af FB |
2117 | break; |
2118 | default: | |
2119 | case 7: | |
57fec1fe | 2120 | gen_op_movl_A0_reg(R_EBX); |
2c0262af FB |
2121 | break; |
2122 | } | |
2123 | if (disp != 0) | |
2124 | gen_op_addl_A0_im(disp); | |
2125 | gen_op_andl_A0_ffff(); | |
2126 | no_rm: | |
2127 | if (must_add_seg) { | |
2128 | if (override < 0) { | |
2129 | if (rm == 2 || rm == 3 || rm == 6) | |
2130 | override = R_SS; | |
2131 | else | |
2132 | override = R_DS; | |
2133 | } | |
7162ab21 | 2134 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
2135 | } |
2136 | } | |
2c0262af FB |
2137 | } |
2138 | ||
0af10c86 | 2139 | static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) |
e17a36ce FB |
2140 | { |
2141 | int mod, rm, base, code; | |
2142 | ||
2143 | mod = (modrm >> 6) & 3; | |
2144 | if (mod == 3) | |
2145 | return; | |
2146 | rm = modrm & 7; | |
2147 | ||
2148 | if (s->aflag) { | |
2149 | ||
2150 | base = rm; | |
3b46e624 | 2151 | |
e17a36ce | 2152 | if (base == 4) { |
0af10c86 | 2153 | code = cpu_ldub_code(env, s->pc++); |
e17a36ce FB |
2154 | base = (code & 7); |
2155 | } | |
3b46e624 | 2156 | |
e17a36ce FB |
2157 | switch (mod) { |
2158 | case 0: | |
2159 | if (base == 5) { | |
2160 | s->pc += 4; | |
2161 | } | |
2162 | break; | |
2163 | case 1: | |
2164 | s->pc++; | |
2165 | break; | |
2166 | default: | |
2167 | case 2: | |
2168 | s->pc += 4; | |
2169 | break; | |
2170 | } | |
2171 | } else { | |
2172 | switch (mod) { | |
2173 | case 0: | |
2174 | if (rm == 6) { | |
2175 | s->pc += 2; | |
2176 | } | |
2177 | break; | |
2178 | case 1: | |
2179 | s->pc++; | |
2180 | break; | |
2181 | default: | |
2182 | case 2: | |
2183 | s->pc += 2; | |
2184 | break; | |
2185 | } | |
2186 | } | |
2187 | } | |
2188 | ||
664e0f19 FB |
2189 | /* used for LEA and MOV AX, mem */ |
2190 | static void gen_add_A0_ds_seg(DisasContext *s) | |
2191 | { | |
2192 | int override, must_add_seg; | |
2193 | must_add_seg = s->addseg; | |
2194 | override = R_DS; | |
2195 | if (s->override >= 0) { | |
2196 | override = s->override; | |
2197 | must_add_seg = 1; | |
664e0f19 FB |
2198 | } |
2199 | if (must_add_seg) { | |
8f091a59 FB |
2200 | #ifdef TARGET_X86_64 |
2201 | if (CODE64(s)) { | |
57fec1fe | 2202 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2203 | } else |
8f091a59 FB |
2204 | #endif |
2205 | { | |
7162ab21 | 2206 | gen_op_addl_A0_seg(s, override); |
8f091a59 | 2207 | } |
664e0f19 FB |
2208 | } |
2209 | } | |
2210 | ||
222a3336 | 2211 | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == |
2c0262af | 2212 | OR_TMP0 */ |
0af10c86 BS |
2213 | static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, |
2214 | int ot, int reg, int is_store) | |
2c0262af | 2215 | { |
4eeb3939 | 2216 | int mod, rm; |
2c0262af FB |
2217 | |
2218 | mod = (modrm >> 6) & 3; | |
14ce26e7 | 2219 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
2220 | if (mod == 3) { |
2221 | if (is_store) { | |
2222 | if (reg != OR_TMP0) | |
57fec1fe FB |
2223 | gen_op_mov_TN_reg(ot, 0, reg); |
2224 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 2225 | } else { |
57fec1fe | 2226 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 2227 | if (reg != OR_TMP0) |
57fec1fe | 2228 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2229 | } |
2230 | } else { | |
4eeb3939 | 2231 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
2232 | if (is_store) { |
2233 | if (reg != OR_TMP0) | |
57fec1fe | 2234 | gen_op_mov_TN_reg(ot, 0, reg); |
fd8ca9f6 | 2235 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 2236 | } else { |
909be183 | 2237 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 2238 | if (reg != OR_TMP0) |
57fec1fe | 2239 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2240 | } |
2241 | } | |
2242 | } | |
2243 | ||
0af10c86 | 2244 | static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot) |
2c0262af FB |
2245 | { |
2246 | uint32_t ret; | |
2247 | ||
2248 | switch(ot) { | |
4ba9938c | 2249 | case MO_8: |
0af10c86 | 2250 | ret = cpu_ldub_code(env, s->pc); |
2c0262af FB |
2251 | s->pc++; |
2252 | break; | |
4ba9938c | 2253 | case MO_16: |
0af10c86 | 2254 | ret = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2255 | s->pc += 2; |
2256 | break; | |
2257 | default: | |
4ba9938c | 2258 | case MO_32: |
0af10c86 | 2259 | ret = cpu_ldl_code(env, s->pc); |
2c0262af FB |
2260 | s->pc += 4; |
2261 | break; | |
2262 | } | |
2263 | return ret; | |
2264 | } | |
2265 | ||
14ce26e7 FB |
2266 | static inline int insn_const_size(unsigned int ot) |
2267 | { | |
4ba9938c | 2268 | if (ot <= MO_32) { |
14ce26e7 | 2269 | return 1 << ot; |
4ba9938c | 2270 | } else { |
14ce26e7 | 2271 | return 4; |
4ba9938c | 2272 | } |
14ce26e7 FB |
2273 | } |
2274 | ||
6e256c93 FB |
2275 | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2276 | { | |
2277 | TranslationBlock *tb; | |
2278 | target_ulong pc; | |
2279 | ||
2280 | pc = s->cs_base + eip; | |
2281 | tb = s->tb; | |
2282 | /* NOTE: we handle the case where the TB spans two pages here */ | |
2283 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) || | |
2284 | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { | |
2285 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 2286 | tcg_gen_goto_tb(tb_num); |
6e256c93 | 2287 | gen_jmp_im(eip); |
8cfd0495 | 2288 | tcg_gen_exit_tb((uintptr_t)tb + tb_num); |
6e256c93 FB |
2289 | } else { |
2290 | /* jump to another page: currently not optimized */ | |
2291 | gen_jmp_im(eip); | |
2292 | gen_eob(s); | |
2293 | } | |
2294 | } | |
2295 | ||
5fafdf24 | 2296 | static inline void gen_jcc(DisasContext *s, int b, |
14ce26e7 | 2297 | target_ulong val, target_ulong next_eip) |
2c0262af | 2298 | { |
b27fc131 | 2299 | int l1, l2; |
3b46e624 | 2300 | |
2c0262af | 2301 | if (s->jmp_opt) { |
14ce26e7 | 2302 | l1 = gen_new_label(); |
b27fc131 | 2303 | gen_jcc1(s, b, l1); |
dc259201 | 2304 | |
6e256c93 | 2305 | gen_goto_tb(s, 0, next_eip); |
14ce26e7 FB |
2306 | |
2307 | gen_set_label(l1); | |
6e256c93 | 2308 | gen_goto_tb(s, 1, val); |
5779406a | 2309 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2310 | } else { |
14ce26e7 FB |
2311 | l1 = gen_new_label(); |
2312 | l2 = gen_new_label(); | |
b27fc131 | 2313 | gen_jcc1(s, b, l1); |
8e1c85e3 | 2314 | |
14ce26e7 | 2315 | gen_jmp_im(next_eip); |
8e1c85e3 FB |
2316 | tcg_gen_br(l2); |
2317 | ||
14ce26e7 FB |
2318 | gen_set_label(l1); |
2319 | gen_jmp_im(val); | |
2320 | gen_set_label(l2); | |
2c0262af FB |
2321 | gen_eob(s); |
2322 | } | |
2323 | } | |
2324 | ||
f32d3781 PB |
2325 | static void gen_cmovcc1(CPUX86State *env, DisasContext *s, int ot, int b, |
2326 | int modrm, int reg) | |
2327 | { | |
57eb0cc8 | 2328 | CCPrepare cc; |
f32d3781 | 2329 | |
57eb0cc8 | 2330 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
f32d3781 | 2331 | |
57eb0cc8 RH |
2332 | cc = gen_prepare_cc(s, b, cpu_T[1]); |
2333 | if (cc.mask != -1) { | |
2334 | TCGv t0 = tcg_temp_new(); | |
2335 | tcg_gen_andi_tl(t0, cc.reg, cc.mask); | |
2336 | cc.reg = t0; | |
2337 | } | |
2338 | if (!cc.use_reg2) { | |
2339 | cc.reg2 = tcg_const_tl(cc.imm); | |
f32d3781 PB |
2340 | } |
2341 | ||
57eb0cc8 RH |
2342 | tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2, |
2343 | cpu_T[0], cpu_regs[reg]); | |
2344 | gen_op_mov_reg_T0(ot, reg); | |
2345 | ||
2346 | if (cc.mask != -1) { | |
2347 | tcg_temp_free(cc.reg); | |
2348 | } | |
2349 | if (!cc.use_reg2) { | |
2350 | tcg_temp_free(cc.reg2); | |
2351 | } | |
f32d3781 PB |
2352 | } |
2353 | ||
3bd7da9e FB |
2354 | static inline void gen_op_movl_T0_seg(int seg_reg) |
2355 | { | |
2356 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, | |
2357 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2358 | } | |
2359 | ||
2360 | static inline void gen_op_movl_seg_T0_vm(int seg_reg) | |
2361 | { | |
2362 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
2363 | tcg_gen_st32_tl(cpu_T[0], cpu_env, | |
2364 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2365 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); | |
2366 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
2367 | offsetof(CPUX86State,segs[seg_reg].base)); | |
2368 | } | |
2369 | ||
2c0262af FB |
2370 | /* move T0 to seg_reg and compute if the CPU state may change. Never |
2371 | call this function with seg_reg == R_CS */ | |
14ce26e7 | 2372 | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2c0262af | 2373 | { |
3415a4dd FB |
2374 | if (s->pe && !s->vm86) { |
2375 | /* XXX: optimize by finding processor state dynamically */ | |
773cdfcc | 2376 | gen_update_cc_op(s); |
14ce26e7 | 2377 | gen_jmp_im(cur_eip); |
b6abf97d | 2378 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 2379 | gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32); |
dc196a57 FB |
2380 | /* abort translation because the addseg value may change or |
2381 | because ss32 may change. For R_SS, translation must always | |
2382 | stop as a special handling must be done to disable hardware | |
2383 | interrupts for the next instruction */ | |
2384 | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) | |
5779406a | 2385 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2386 | } else { |
3bd7da9e | 2387 | gen_op_movl_seg_T0_vm(seg_reg); |
dc196a57 | 2388 | if (seg_reg == R_SS) |
5779406a | 2389 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2390 | } |
2c0262af FB |
2391 | } |
2392 | ||
0573fbfc TS |
2393 | static inline int svm_is_rep(int prefixes) |
2394 | { | |
2395 | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); | |
2396 | } | |
2397 | ||
872929aa | 2398 | static inline void |
0573fbfc | 2399 | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
b8b6a50b | 2400 | uint32_t type, uint64_t param) |
0573fbfc | 2401 | { |
872929aa FB |
2402 | /* no SVM activated; fast case */ |
2403 | if (likely(!(s->flags & HF_SVMI_MASK))) | |
2404 | return; | |
773cdfcc | 2405 | gen_update_cc_op(s); |
872929aa | 2406 | gen_jmp_im(pc_start - s->cs_base); |
052e80d5 | 2407 | gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), |
a7812ae4 | 2408 | tcg_const_i64(param)); |
0573fbfc TS |
2409 | } |
2410 | ||
872929aa | 2411 | static inline void |
0573fbfc TS |
2412 | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2413 | { | |
872929aa | 2414 | gen_svm_check_intercept_param(s, pc_start, type, 0); |
0573fbfc TS |
2415 | } |
2416 | ||
4f31916f FB |
2417 | static inline void gen_stack_update(DisasContext *s, int addend) |
2418 | { | |
14ce26e7 FB |
2419 | #ifdef TARGET_X86_64 |
2420 | if (CODE64(s)) { | |
6e0d8677 | 2421 | gen_op_add_reg_im(2, R_ESP, addend); |
14ce26e7 FB |
2422 | } else |
2423 | #endif | |
4f31916f | 2424 | if (s->ss32) { |
6e0d8677 | 2425 | gen_op_add_reg_im(1, R_ESP, addend); |
4f31916f | 2426 | } else { |
6e0d8677 | 2427 | gen_op_add_reg_im(0, R_ESP, addend); |
4f31916f FB |
2428 | } |
2429 | } | |
2430 | ||
2c0262af FB |
2431 | /* generate a push. It depends on ss32, addseg and dflag */ |
2432 | static void gen_push_T0(DisasContext *s) | |
2433 | { | |
14ce26e7 FB |
2434 | #ifdef TARGET_X86_64 |
2435 | if (CODE64(s)) { | |
57fec1fe | 2436 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2437 | if (s->dflag) { |
57fec1fe | 2438 | gen_op_addq_A0_im(-8); |
fd8ca9f6 | 2439 | gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0); |
8f091a59 | 2440 | } else { |
57fec1fe | 2441 | gen_op_addq_A0_im(-2); |
fd8ca9f6 | 2442 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
8f091a59 | 2443 | } |
57fec1fe | 2444 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2445 | } else |
14ce26e7 FB |
2446 | #endif |
2447 | { | |
57fec1fe | 2448 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2449 | if (!s->dflag) |
57fec1fe | 2450 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2451 | else |
57fec1fe | 2452 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2453 | if (s->ss32) { |
2454 | if (s->addseg) { | |
bbf662ee | 2455 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2456 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2457 | } |
2458 | } else { | |
2459 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2460 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2461 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2462 | } |
fd8ca9f6 | 2463 | gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0); |
14ce26e7 | 2464 | if (s->ss32 && !s->addseg) |
57fec1fe | 2465 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 | 2466 | else |
57fec1fe | 2467 | gen_op_mov_reg_T1(s->ss32 + 1, R_ESP); |
2c0262af FB |
2468 | } |
2469 | } | |
2470 | ||
4f31916f FB |
2471 | /* generate a push. It depends on ss32, addseg and dflag */ |
2472 | /* slower version for T1, only used for call Ev */ | |
2473 | static void gen_push_T1(DisasContext *s) | |
2c0262af | 2474 | { |
14ce26e7 FB |
2475 | #ifdef TARGET_X86_64 |
2476 | if (CODE64(s)) { | |
57fec1fe | 2477 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2478 | if (s->dflag) { |
57fec1fe | 2479 | gen_op_addq_A0_im(-8); |
b5afc104 | 2480 | gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0); |
8f091a59 | 2481 | } else { |
57fec1fe | 2482 | gen_op_addq_A0_im(-2); |
ee3138da | 2483 | gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0); |
8f091a59 | 2484 | } |
57fec1fe | 2485 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2486 | } else |
14ce26e7 FB |
2487 | #endif |
2488 | { | |
57fec1fe | 2489 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2490 | if (!s->dflag) |
57fec1fe | 2491 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2492 | else |
57fec1fe | 2493 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2494 | if (s->ss32) { |
2495 | if (s->addseg) { | |
7162ab21 | 2496 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2497 | } |
2498 | } else { | |
2499 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2500 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2501 | } |
b5afc104 | 2502 | gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0); |
3b46e624 | 2503 | |
14ce26e7 | 2504 | if (s->ss32 && !s->addseg) |
57fec1fe | 2505 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 FB |
2506 | else |
2507 | gen_stack_update(s, (-2) << s->dflag); | |
2c0262af FB |
2508 | } |
2509 | } | |
2510 | ||
4f31916f FB |
2511 | /* two step pop is necessary for precise exceptions */ |
2512 | static void gen_pop_T0(DisasContext *s) | |
2c0262af | 2513 | { |
14ce26e7 FB |
2514 | #ifdef TARGET_X86_64 |
2515 | if (CODE64(s)) { | |
57fec1fe | 2516 | gen_op_movq_A0_reg(R_ESP); |
909be183 | 2517 | gen_op_ld_v(s, s->dflag ? MO_64 : MO_16, cpu_T[0], cpu_A0); |
5fafdf24 | 2518 | } else |
14ce26e7 FB |
2519 | #endif |
2520 | { | |
57fec1fe | 2521 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 FB |
2522 | if (s->ss32) { |
2523 | if (s->addseg) | |
7162ab21 | 2524 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2525 | } else { |
2526 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2527 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 | 2528 | } |
909be183 | 2529 | gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0); |
2c0262af FB |
2530 | } |
2531 | } | |
2532 | ||
2533 | static void gen_pop_update(DisasContext *s) | |
2534 | { | |
14ce26e7 | 2535 | #ifdef TARGET_X86_64 |
8f091a59 | 2536 | if (CODE64(s) && s->dflag) { |
14ce26e7 FB |
2537 | gen_stack_update(s, 8); |
2538 | } else | |
2539 | #endif | |
2540 | { | |
2541 | gen_stack_update(s, 2 << s->dflag); | |
2542 | } | |
2c0262af FB |
2543 | } |
2544 | ||
2545 | static void gen_stack_A0(DisasContext *s) | |
2546 | { | |
57fec1fe | 2547 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2548 | if (!s->ss32) |
2549 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2550 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2551 | if (s->addseg) |
7162ab21 | 2552 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2553 | } |
2554 | ||
2555 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2556 | static void gen_pusha(DisasContext *s) | |
2557 | { | |
2558 | int i; | |
57fec1fe | 2559 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2560 | gen_op_addl_A0_im(-16 << s->dflag); |
2561 | if (!s->ss32) | |
2562 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2563 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2564 | if (s->addseg) |
7162ab21 | 2565 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2566 | for(i = 0;i < 8; i++) { |
4ba9938c | 2567 | gen_op_mov_TN_reg(MO_32, 0, 7 - i); |
fd8ca9f6 | 2568 | gen_op_st_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0); |
2c0262af FB |
2569 | gen_op_addl_A0_im(2 << s->dflag); |
2570 | } | |
4ba9938c | 2571 | gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); |
2c0262af FB |
2572 | } |
2573 | ||
2574 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2575 | static void gen_popa(DisasContext *s) | |
2576 | { | |
2577 | int i; | |
57fec1fe | 2578 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2579 | if (!s->ss32) |
2580 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
2581 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2582 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); | |
2c0262af | 2583 | if (s->addseg) |
7162ab21 | 2584 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2585 | for(i = 0;i < 8; i++) { |
2586 | /* ESP is not reloaded */ | |
2587 | if (i != 3) { | |
909be183 | 2588 | gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0); |
4ba9938c | 2589 | gen_op_mov_reg_T0(MO_16 + s->dflag, 7 - i); |
2c0262af FB |
2590 | } |
2591 | gen_op_addl_A0_im(2 << s->dflag); | |
2592 | } | |
4ba9938c | 2593 | gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); |
2c0262af FB |
2594 | } |
2595 | ||
2c0262af FB |
2596 | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2597 | { | |
61a8c4ec | 2598 | int ot, opsize; |
2c0262af | 2599 | |
2c0262af | 2600 | level &= 0x1f; |
8f091a59 FB |
2601 | #ifdef TARGET_X86_64 |
2602 | if (CODE64(s)) { | |
4ba9938c | 2603 | ot = s->dflag ? MO_64 : MO_16; |
8f091a59 | 2604 | opsize = 1 << ot; |
3b46e624 | 2605 | |
57fec1fe | 2606 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 | 2607 | gen_op_addq_A0_im(-opsize); |
bbf662ee | 2608 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 FB |
2609 | |
2610 | /* push bp */ | |
4ba9938c | 2611 | gen_op_mov_TN_reg(MO_32, 0, R_EBP); |
fd8ca9f6 | 2612 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
8f091a59 | 2613 | if (level) { |
b5b38f61 | 2614 | /* XXX: must save state */ |
2999a0b2 | 2615 | gen_helper_enter64_level(cpu_env, tcg_const_i32(level), |
4ba9938c | 2616 | tcg_const_i32((ot == MO_64)), |
a7812ae4 | 2617 | cpu_T[1]); |
8f091a59 | 2618 | } |
57fec1fe | 2619 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2620 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
4ba9938c | 2621 | gen_op_mov_reg_T1(MO_64, R_ESP); |
5fafdf24 | 2622 | } else |
8f091a59 FB |
2623 | #endif |
2624 | { | |
4ba9938c | 2625 | ot = s->dflag + MO_16; |
8f091a59 | 2626 | opsize = 2 << s->dflag; |
3b46e624 | 2627 | |
57fec1fe | 2628 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 FB |
2629 | gen_op_addl_A0_im(-opsize); |
2630 | if (!s->ss32) | |
2631 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2632 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 | 2633 | if (s->addseg) |
7162ab21 | 2634 | gen_op_addl_A0_seg(s, R_SS); |
8f091a59 | 2635 | /* push bp */ |
4ba9938c | 2636 | gen_op_mov_TN_reg(MO_32, 0, R_EBP); |
fd8ca9f6 | 2637 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
8f091a59 | 2638 | if (level) { |
b5b38f61 | 2639 | /* XXX: must save state */ |
2999a0b2 | 2640 | gen_helper_enter_level(cpu_env, tcg_const_i32(level), |
a7812ae4 PB |
2641 | tcg_const_i32(s->dflag), |
2642 | cpu_T[1]); | |
8f091a59 | 2643 | } |
57fec1fe | 2644 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2645 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
4ba9938c | 2646 | gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); |
2c0262af | 2647 | } |
2c0262af FB |
2648 | } |
2649 | ||
14ce26e7 | 2650 | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2c0262af | 2651 | { |
773cdfcc | 2652 | gen_update_cc_op(s); |
14ce26e7 | 2653 | gen_jmp_im(cur_eip); |
77b2bc2c | 2654 | gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); |
5779406a | 2655 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2656 | } |
2657 | ||
2658 | /* an interrupt is different from an exception because of the | |
7f75ffd3 | 2659 | privilege checks */ |
5fafdf24 | 2660 | static void gen_interrupt(DisasContext *s, int intno, |
14ce26e7 | 2661 | target_ulong cur_eip, target_ulong next_eip) |
2c0262af | 2662 | { |
773cdfcc | 2663 | gen_update_cc_op(s); |
14ce26e7 | 2664 | gen_jmp_im(cur_eip); |
77b2bc2c | 2665 | gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), |
a7812ae4 | 2666 | tcg_const_i32(next_eip - cur_eip)); |
5779406a | 2667 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2668 | } |
2669 | ||
14ce26e7 | 2670 | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2c0262af | 2671 | { |
773cdfcc | 2672 | gen_update_cc_op(s); |
14ce26e7 | 2673 | gen_jmp_im(cur_eip); |
4a7443be | 2674 | gen_helper_debug(cpu_env); |
5779406a | 2675 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2676 | } |
2677 | ||
2678 | /* generate a generic end of block. Trace exception is also generated | |
2679 | if needed */ | |
2680 | static void gen_eob(DisasContext *s) | |
2681 | { | |
773cdfcc | 2682 | gen_update_cc_op(s); |
a2cc3b24 | 2683 | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { |
f0967a1a | 2684 | gen_helper_reset_inhibit_irq(cpu_env); |
a2cc3b24 | 2685 | } |
a2397807 | 2686 | if (s->tb->flags & HF_RF_MASK) { |
f0967a1a | 2687 | gen_helper_reset_rf(cpu_env); |
a2397807 | 2688 | } |
34865134 | 2689 | if (s->singlestep_enabled) { |
4a7443be | 2690 | gen_helper_debug(cpu_env); |
34865134 | 2691 | } else if (s->tf) { |
4a7443be | 2692 | gen_helper_single_step(cpu_env); |
2c0262af | 2693 | } else { |
57fec1fe | 2694 | tcg_gen_exit_tb(0); |
2c0262af | 2695 | } |
5779406a | 2696 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2697 | } |
2698 | ||
2699 | /* generate a jump to eip. No segment change must happen before as a | |
2700 | direct call to the next block may occur */ | |
14ce26e7 | 2701 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2c0262af | 2702 | { |
a3251186 RH |
2703 | gen_update_cc_op(s); |
2704 | set_cc_op(s, CC_OP_DYNAMIC); | |
2c0262af | 2705 | if (s->jmp_opt) { |
6e256c93 | 2706 | gen_goto_tb(s, tb_num, eip); |
5779406a | 2707 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2708 | } else { |
14ce26e7 | 2709 | gen_jmp_im(eip); |
2c0262af FB |
2710 | gen_eob(s); |
2711 | } | |
2712 | } | |
2713 | ||
14ce26e7 FB |
2714 | static void gen_jmp(DisasContext *s, target_ulong eip) |
2715 | { | |
2716 | gen_jmp_tb(s, eip, 0); | |
2717 | } | |
2718 | ||
323d1876 | 2719 | static inline void gen_ldq_env_A0(DisasContext *s, int offset) |
8686c490 | 2720 | { |
3c5f4116 | 2721 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); |
b6abf97d | 2722 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); |
8686c490 | 2723 | } |
664e0f19 | 2724 | |
323d1876 | 2725 | static inline void gen_stq_env_A0(DisasContext *s, int offset) |
8686c490 | 2726 | { |
b6abf97d | 2727 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
3523e4bd | 2728 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); |
8686c490 | 2729 | } |
664e0f19 | 2730 | |
323d1876 | 2731 | static inline void gen_ldo_env_A0(DisasContext *s, int offset) |
8686c490 | 2732 | { |
5c42a7cd | 2733 | int mem_index = s->mem_index; |
3c5f4116 | 2734 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ); |
b6abf97d | 2735 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
8686c490 | 2736 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
3c5f4116 | 2737 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ); |
b6abf97d | 2738 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
8686c490 | 2739 | } |
14ce26e7 | 2740 | |
323d1876 | 2741 | static inline void gen_sto_env_A0(DisasContext *s, int offset) |
8686c490 | 2742 | { |
5c42a7cd | 2743 | int mem_index = s->mem_index; |
b6abf97d | 2744 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
3523e4bd | 2745 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ); |
8686c490 | 2746 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d | 2747 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
3523e4bd | 2748 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ); |
8686c490 | 2749 | } |
14ce26e7 | 2750 | |
5af45186 FB |
2751 | static inline void gen_op_movo(int d_offset, int s_offset) |
2752 | { | |
b6abf97d FB |
2753 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2754 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
2755 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8); | |
2756 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8); | |
5af45186 FB |
2757 | } |
2758 | ||
2759 | static inline void gen_op_movq(int d_offset, int s_offset) | |
2760 | { | |
b6abf97d FB |
2761 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2762 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 FB |
2763 | } |
2764 | ||
2765 | static inline void gen_op_movl(int d_offset, int s_offset) | |
2766 | { | |
b6abf97d FB |
2767 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2768 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); | |
5af45186 FB |
2769 | } |
2770 | ||
2771 | static inline void gen_op_movq_env_0(int d_offset) | |
2772 | { | |
b6abf97d FB |
2773 | tcg_gen_movi_i64(cpu_tmp1_i64, 0); |
2774 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 | 2775 | } |
664e0f19 | 2776 | |
d3eb5eae BS |
2777 | typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg); |
2778 | typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg); | |
2779 | typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val); | |
2780 | typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val); | |
2781 | typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b); | |
2782 | typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, | |
2783 | TCGv_i32 val); | |
c4baa050 | 2784 | typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val); |
d3eb5eae BS |
2785 | typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, |
2786 | TCGv val); | |
c4baa050 | 2787 | |
5af45186 FB |
2788 | #define SSE_SPECIAL ((void *)1) |
2789 | #define SSE_DUMMY ((void *)2) | |
664e0f19 | 2790 | |
a7812ae4 PB |
2791 | #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } |
2792 | #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ | |
2793 | gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } | |
5af45186 | 2794 | |
d3eb5eae | 2795 | static const SSEFunc_0_epp sse_op_table1[256][4] = { |
a35f3ec7 AJ |
2796 | /* 3DNow! extensions */ |
2797 | [0x0e] = { SSE_DUMMY }, /* femms */ | |
2798 | [0x0f] = { SSE_DUMMY }, /* pf... */ | |
664e0f19 FB |
2799 | /* pure SSE operations */ |
2800 | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
2801 | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
465e9838 | 2802 | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
664e0f19 | 2803 | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
a7812ae4 PB |
2804 | [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, |
2805 | [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2806 | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2807 | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ | |
2808 | ||
2809 | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2810 | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2811 | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ | |
d9f4bb27 | 2812 | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ |
664e0f19 FB |
2813 | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ |
2814 | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ | |
a7812ae4 PB |
2815 | [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, |
2816 | [0x2f] = { gen_helper_comiss, gen_helper_comisd }, | |
664e0f19 FB |
2817 | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2818 | [0x51] = SSE_FOP(sqrt), | |
a7812ae4 PB |
2819 | [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, |
2820 | [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, | |
2821 | [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ | |
2822 | [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ | |
2823 | [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ | |
2824 | [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ | |
664e0f19 FB |
2825 | [0x58] = SSE_FOP(add), |
2826 | [0x59] = SSE_FOP(mul), | |
a7812ae4 PB |
2827 | [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, |
2828 | gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, | |
2829 | [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, | |
664e0f19 FB |
2830 | [0x5c] = SSE_FOP(sub), |
2831 | [0x5d] = SSE_FOP(min), | |
2832 | [0x5e] = SSE_FOP(div), | |
2833 | [0x5f] = SSE_FOP(max), | |
2834 | ||
2835 | [0xc2] = SSE_FOP(cmpeq), | |
d3eb5eae BS |
2836 | [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps, |
2837 | (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ | |
664e0f19 | 2838 | |
7073fbad RH |
2839 | /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */ |
2840 | [0x38] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2841 | [0x3a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
4242b1bd | 2842 | |
664e0f19 FB |
2843 | /* MMX ops and their SSE extensions */ |
2844 | [0x60] = MMX_OP2(punpcklbw), | |
2845 | [0x61] = MMX_OP2(punpcklwd), | |
2846 | [0x62] = MMX_OP2(punpckldq), | |
2847 | [0x63] = MMX_OP2(packsswb), | |
2848 | [0x64] = MMX_OP2(pcmpgtb), | |
2849 | [0x65] = MMX_OP2(pcmpgtw), | |
2850 | [0x66] = MMX_OP2(pcmpgtl), | |
2851 | [0x67] = MMX_OP2(packuswb), | |
2852 | [0x68] = MMX_OP2(punpckhbw), | |
2853 | [0x69] = MMX_OP2(punpckhwd), | |
2854 | [0x6a] = MMX_OP2(punpckhdq), | |
2855 | [0x6b] = MMX_OP2(packssdw), | |
a7812ae4 PB |
2856 | [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, |
2857 | [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2858 | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2859 | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ | |
d3eb5eae BS |
2860 | [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx, |
2861 | (SSEFunc_0_epp)gen_helper_pshufd_xmm, | |
2862 | (SSEFunc_0_epp)gen_helper_pshufhw_xmm, | |
2863 | (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2864 | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2865 | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ | |
2866 | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ | |
2867 | [0x74] = MMX_OP2(pcmpeqb), | |
2868 | [0x75] = MMX_OP2(pcmpeqw), | |
2869 | [0x76] = MMX_OP2(pcmpeql), | |
a35f3ec7 | 2870 | [0x77] = { SSE_DUMMY }, /* emms */ |
d9f4bb27 AP |
2871 | [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ |
2872 | [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, | |
a7812ae4 PB |
2873 | [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, |
2874 | [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, | |
664e0f19 FB |
2875 | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2876 | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ | |
2877 | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ | |
2878 | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ | |
a7812ae4 | 2879 | [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, |
664e0f19 FB |
2880 | [0xd1] = MMX_OP2(psrlw), |
2881 | [0xd2] = MMX_OP2(psrld), | |
2882 | [0xd3] = MMX_OP2(psrlq), | |
2883 | [0xd4] = MMX_OP2(paddq), | |
2884 | [0xd5] = MMX_OP2(pmullw), | |
2885 | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2886 | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ | |
2887 | [0xd8] = MMX_OP2(psubusb), | |
2888 | [0xd9] = MMX_OP2(psubusw), | |
2889 | [0xda] = MMX_OP2(pminub), | |
2890 | [0xdb] = MMX_OP2(pand), | |
2891 | [0xdc] = MMX_OP2(paddusb), | |
2892 | [0xdd] = MMX_OP2(paddusw), | |
2893 | [0xde] = MMX_OP2(pmaxub), | |
2894 | [0xdf] = MMX_OP2(pandn), | |
2895 | [0xe0] = MMX_OP2(pavgb), | |
2896 | [0xe1] = MMX_OP2(psraw), | |
2897 | [0xe2] = MMX_OP2(psrad), | |
2898 | [0xe3] = MMX_OP2(pavgw), | |
2899 | [0xe4] = MMX_OP2(pmulhuw), | |
2900 | [0xe5] = MMX_OP2(pmulhw), | |
a7812ae4 | 2901 | [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, |
664e0f19 FB |
2902 | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
2903 | [0xe8] = MMX_OP2(psubsb), | |
2904 | [0xe9] = MMX_OP2(psubsw), | |
2905 | [0xea] = MMX_OP2(pminsw), | |
2906 | [0xeb] = MMX_OP2(por), | |
2907 | [0xec] = MMX_OP2(paddsb), | |
2908 | [0xed] = MMX_OP2(paddsw), | |
2909 | [0xee] = MMX_OP2(pmaxsw), | |
2910 | [0xef] = MMX_OP2(pxor), | |
465e9838 | 2911 | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
664e0f19 FB |
2912 | [0xf1] = MMX_OP2(psllw), |
2913 | [0xf2] = MMX_OP2(pslld), | |
2914 | [0xf3] = MMX_OP2(psllq), | |
2915 | [0xf4] = MMX_OP2(pmuludq), | |
2916 | [0xf5] = MMX_OP2(pmaddwd), | |
2917 | [0xf6] = MMX_OP2(psadbw), | |
d3eb5eae BS |
2918 | [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx, |
2919 | (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2920 | [0xf8] = MMX_OP2(psubb), |
2921 | [0xf9] = MMX_OP2(psubw), | |
2922 | [0xfa] = MMX_OP2(psubl), | |
2923 | [0xfb] = MMX_OP2(psubq), | |
2924 | [0xfc] = MMX_OP2(paddb), | |
2925 | [0xfd] = MMX_OP2(paddw), | |
2926 | [0xfe] = MMX_OP2(paddl), | |
2927 | }; | |
2928 | ||
d3eb5eae | 2929 | static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = { |
664e0f19 FB |
2930 | [0 + 2] = MMX_OP2(psrlw), |
2931 | [0 + 4] = MMX_OP2(psraw), | |
2932 | [0 + 6] = MMX_OP2(psllw), | |
2933 | [8 + 2] = MMX_OP2(psrld), | |
2934 | [8 + 4] = MMX_OP2(psrad), | |
2935 | [8 + 6] = MMX_OP2(pslld), | |
2936 | [16 + 2] = MMX_OP2(psrlq), | |
a7812ae4 | 2937 | [16 + 3] = { NULL, gen_helper_psrldq_xmm }, |
664e0f19 | 2938 | [16 + 6] = MMX_OP2(psllq), |
a7812ae4 | 2939 | [16 + 7] = { NULL, gen_helper_pslldq_xmm }, |
664e0f19 FB |
2940 | }; |
2941 | ||
d3eb5eae | 2942 | static const SSEFunc_0_epi sse_op_table3ai[] = { |
a7812ae4 | 2943 | gen_helper_cvtsi2ss, |
11f8cdbc | 2944 | gen_helper_cvtsi2sd |
c4baa050 | 2945 | }; |
a7812ae4 | 2946 | |
11f8cdbc | 2947 | #ifdef TARGET_X86_64 |
d3eb5eae | 2948 | static const SSEFunc_0_epl sse_op_table3aq[] = { |
11f8cdbc SW |
2949 | gen_helper_cvtsq2ss, |
2950 | gen_helper_cvtsq2sd | |
2951 | }; | |
2952 | #endif | |
2953 | ||
d3eb5eae | 2954 | static const SSEFunc_i_ep sse_op_table3bi[] = { |
a7812ae4 | 2955 | gen_helper_cvttss2si, |
a7812ae4 | 2956 | gen_helper_cvtss2si, |
bedc2ac1 | 2957 | gen_helper_cvttsd2si, |
11f8cdbc | 2958 | gen_helper_cvtsd2si |
664e0f19 | 2959 | }; |
3b46e624 | 2960 | |
11f8cdbc | 2961 | #ifdef TARGET_X86_64 |
d3eb5eae | 2962 | static const SSEFunc_l_ep sse_op_table3bq[] = { |
11f8cdbc | 2963 | gen_helper_cvttss2sq, |
11f8cdbc | 2964 | gen_helper_cvtss2sq, |
bedc2ac1 | 2965 | gen_helper_cvttsd2sq, |
11f8cdbc SW |
2966 | gen_helper_cvtsd2sq |
2967 | }; | |
2968 | #endif | |
2969 | ||
d3eb5eae | 2970 | static const SSEFunc_0_epp sse_op_table4[8][4] = { |
664e0f19 FB |
2971 | SSE_FOP(cmpeq), |
2972 | SSE_FOP(cmplt), | |
2973 | SSE_FOP(cmple), | |
2974 | SSE_FOP(cmpunord), | |
2975 | SSE_FOP(cmpneq), | |
2976 | SSE_FOP(cmpnlt), | |
2977 | SSE_FOP(cmpnle), | |
2978 | SSE_FOP(cmpord), | |
2979 | }; | |
3b46e624 | 2980 | |
d3eb5eae | 2981 | static const SSEFunc_0_epp sse_op_table5[256] = { |
a7812ae4 PB |
2982 | [0x0c] = gen_helper_pi2fw, |
2983 | [0x0d] = gen_helper_pi2fd, | |
2984 | [0x1c] = gen_helper_pf2iw, | |
2985 | [0x1d] = gen_helper_pf2id, | |
2986 | [0x8a] = gen_helper_pfnacc, | |
2987 | [0x8e] = gen_helper_pfpnacc, | |
2988 | [0x90] = gen_helper_pfcmpge, | |
2989 | [0x94] = gen_helper_pfmin, | |
2990 | [0x96] = gen_helper_pfrcp, | |
2991 | [0x97] = gen_helper_pfrsqrt, | |
2992 | [0x9a] = gen_helper_pfsub, | |
2993 | [0x9e] = gen_helper_pfadd, | |
2994 | [0xa0] = gen_helper_pfcmpgt, | |
2995 | [0xa4] = gen_helper_pfmax, | |
2996 | [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ | |
2997 | [0xa7] = gen_helper_movq, /* pfrsqit1 */ | |
2998 | [0xaa] = gen_helper_pfsubr, | |
2999 | [0xae] = gen_helper_pfacc, | |
3000 | [0xb0] = gen_helper_pfcmpeq, | |
3001 | [0xb4] = gen_helper_pfmul, | |
3002 | [0xb6] = gen_helper_movq, /* pfrcpit2 */ | |
3003 | [0xb7] = gen_helper_pmulhrw_mmx, | |
3004 | [0xbb] = gen_helper_pswapd, | |
3005 | [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ | |
a35f3ec7 AJ |
3006 | }; |
3007 | ||
d3eb5eae BS |
3008 | struct SSEOpHelper_epp { |
3009 | SSEFunc_0_epp op[2]; | |
c4baa050 BS |
3010 | uint32_t ext_mask; |
3011 | }; | |
3012 | ||
d3eb5eae BS |
3013 | struct SSEOpHelper_eppi { |
3014 | SSEFunc_0_eppi op[2]; | |
c4baa050 | 3015 | uint32_t ext_mask; |
222a3336 | 3016 | }; |
c4baa050 | 3017 | |
222a3336 | 3018 | #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 } |
a7812ae4 PB |
3019 | #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } |
3020 | #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } | |
222a3336 | 3021 | #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } |
e71827bc AJ |
3022 | #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \ |
3023 | CPUID_EXT_PCLMULQDQ } | |
d640045a | 3024 | #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES } |
c4baa050 | 3025 | |
d3eb5eae | 3026 | static const struct SSEOpHelper_epp sse_op_table6[256] = { |
222a3336 AZ |
3027 | [0x00] = SSSE3_OP(pshufb), |
3028 | [0x01] = SSSE3_OP(phaddw), | |
3029 | [0x02] = SSSE3_OP(phaddd), | |
3030 | [0x03] = SSSE3_OP(phaddsw), | |
3031 | [0x04] = SSSE3_OP(pmaddubsw), | |
3032 | [0x05] = SSSE3_OP(phsubw), | |
3033 | [0x06] = SSSE3_OP(phsubd), | |
3034 | [0x07] = SSSE3_OP(phsubsw), | |
3035 | [0x08] = SSSE3_OP(psignb), | |
3036 | [0x09] = SSSE3_OP(psignw), | |
3037 | [0x0a] = SSSE3_OP(psignd), | |
3038 | [0x0b] = SSSE3_OP(pmulhrsw), | |
3039 | [0x10] = SSE41_OP(pblendvb), | |
3040 | [0x14] = SSE41_OP(blendvps), | |
3041 | [0x15] = SSE41_OP(blendvpd), | |
3042 | [0x17] = SSE41_OP(ptest), | |
3043 | [0x1c] = SSSE3_OP(pabsb), | |
3044 | [0x1d] = SSSE3_OP(pabsw), | |
3045 | [0x1e] = SSSE3_OP(pabsd), | |
3046 | [0x20] = SSE41_OP(pmovsxbw), | |
3047 | [0x21] = SSE41_OP(pmovsxbd), | |
3048 | [0x22] = SSE41_OP(pmovsxbq), | |
3049 | [0x23] = SSE41_OP(pmovsxwd), | |
3050 | [0x24] = SSE41_OP(pmovsxwq), | |
3051 | [0x25] = SSE41_OP(pmovsxdq), | |
3052 | [0x28] = SSE41_OP(pmuldq), | |
3053 | [0x29] = SSE41_OP(pcmpeqq), | |
3054 | [0x2a] = SSE41_SPECIAL, /* movntqda */ | |
3055 | [0x2b] = SSE41_OP(packusdw), | |
3056 | [0x30] = SSE41_OP(pmovzxbw), | |
3057 | [0x31] = SSE41_OP(pmovzxbd), | |
3058 | [0x32] = SSE41_OP(pmovzxbq), | |
3059 | [0x33] = SSE41_OP(pmovzxwd), | |
3060 | [0x34] = SSE41_OP(pmovzxwq), | |
3061 | [0x35] = SSE41_OP(pmovzxdq), | |
3062 | [0x37] = SSE42_OP(pcmpgtq), | |
3063 | [0x38] = SSE41_OP(pminsb), | |
3064 | [0x39] = SSE41_OP(pminsd), | |
3065 | [0x3a] = SSE41_OP(pminuw), | |
3066 | [0x3b] = SSE41_OP(pminud), | |
3067 | [0x3c] = SSE41_OP(pmaxsb), | |
3068 | [0x3d] = SSE41_OP(pmaxsd), | |
3069 | [0x3e] = SSE41_OP(pmaxuw), | |
3070 | [0x3f] = SSE41_OP(pmaxud), | |
3071 | [0x40] = SSE41_OP(pmulld), | |
3072 | [0x41] = SSE41_OP(phminposuw), | |
d640045a AJ |
3073 | [0xdb] = AESNI_OP(aesimc), |
3074 | [0xdc] = AESNI_OP(aesenc), | |
3075 | [0xdd] = AESNI_OP(aesenclast), | |
3076 | [0xde] = AESNI_OP(aesdec), | |
3077 | [0xdf] = AESNI_OP(aesdeclast), | |
4242b1bd AZ |
3078 | }; |
3079 | ||
d3eb5eae | 3080 | static const struct SSEOpHelper_eppi sse_op_table7[256] = { |
222a3336 AZ |
3081 | [0x08] = SSE41_OP(roundps), |
3082 | [0x09] = SSE41_OP(roundpd), | |
3083 | [0x0a] = SSE41_OP(roundss), | |
3084 | [0x0b] = SSE41_OP(roundsd), | |
3085 | [0x0c] = SSE41_OP(blendps), | |
3086 | [0x0d] = SSE41_OP(blendpd), | |
3087 | [0x0e] = SSE41_OP(pblendw), | |
3088 | [0x0f] = SSSE3_OP(palignr), | |
3089 | [0x14] = SSE41_SPECIAL, /* pextrb */ | |
3090 | [0x15] = SSE41_SPECIAL, /* pextrw */ | |
3091 | [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ | |
3092 | [0x17] = SSE41_SPECIAL, /* extractps */ | |
3093 | [0x20] = SSE41_SPECIAL, /* pinsrb */ | |
3094 | [0x21] = SSE41_SPECIAL, /* insertps */ | |
3095 | [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ | |
3096 | [0x40] = SSE41_OP(dpps), | |
3097 | [0x41] = SSE41_OP(dppd), | |
3098 | [0x42] = SSE41_OP(mpsadbw), | |
e71827bc | 3099 | [0x44] = PCLMULQDQ_OP(pclmulqdq), |
222a3336 AZ |
3100 | [0x60] = SSE42_OP(pcmpestrm), |
3101 | [0x61] = SSE42_OP(pcmpestri), | |
3102 | [0x62] = SSE42_OP(pcmpistrm), | |
3103 | [0x63] = SSE42_OP(pcmpistri), | |
d640045a | 3104 | [0xdf] = AESNI_OP(aeskeygenassist), |
4242b1bd AZ |
3105 | }; |
3106 | ||
0af10c86 BS |
3107 | static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
3108 | target_ulong pc_start, int rex_r) | |
664e0f19 FB |
3109 | { |
3110 | int b1, op1_offset, op2_offset, is_xmm, val, ot; | |
4eeb3939 | 3111 | int modrm, mod, rm, reg; |
d3eb5eae BS |
3112 | SSEFunc_0_epp sse_fn_epp; |
3113 | SSEFunc_0_eppi sse_fn_eppi; | |
c4baa050 | 3114 | SSEFunc_0_ppi sse_fn_ppi; |
d3eb5eae | 3115 | SSEFunc_0_eppt sse_fn_eppt; |
664e0f19 FB |
3116 | |
3117 | b &= 0xff; | |
5fafdf24 | 3118 | if (s->prefix & PREFIX_DATA) |
664e0f19 | 3119 | b1 = 1; |
5fafdf24 | 3120 | else if (s->prefix & PREFIX_REPZ) |
664e0f19 | 3121 | b1 = 2; |
5fafdf24 | 3122 | else if (s->prefix & PREFIX_REPNZ) |
664e0f19 FB |
3123 | b1 = 3; |
3124 | else | |
3125 | b1 = 0; | |
d3eb5eae BS |
3126 | sse_fn_epp = sse_op_table1[b][b1]; |
3127 | if (!sse_fn_epp) { | |
664e0f19 | 3128 | goto illegal_op; |
c4baa050 | 3129 | } |
a35f3ec7 | 3130 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
664e0f19 FB |
3131 | is_xmm = 1; |
3132 | } else { | |
3133 | if (b1 == 0) { | |
3134 | /* MMX case */ | |
3135 | is_xmm = 0; | |
3136 | } else { | |
3137 | is_xmm = 1; | |
3138 | } | |
3139 | } | |
3140 | /* simple MMX/SSE operation */ | |
3141 | if (s->flags & HF_TS_MASK) { | |
3142 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
3143 | return; | |
3144 | } | |
3145 | if (s->flags & HF_EM_MASK) { | |
3146 | illegal_op: | |
3147 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
3148 | return; | |
3149 | } | |
3150 | if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) | |
4242b1bd AZ |
3151 | if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) |
3152 | goto illegal_op; | |
e771edab AJ |
3153 | if (b == 0x0e) { |
3154 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) | |
3155 | goto illegal_op; | |
3156 | /* femms */ | |
d3eb5eae | 3157 | gen_helper_emms(cpu_env); |
e771edab AJ |
3158 | return; |
3159 | } | |
3160 | if (b == 0x77) { | |
3161 | /* emms */ | |
d3eb5eae | 3162 | gen_helper_emms(cpu_env); |
664e0f19 FB |
3163 | return; |
3164 | } | |
3165 | /* prepare MMX state (XXX: optimize by storing fptt and fptags in | |
3166 | the static cpu state) */ | |
3167 | if (!is_xmm) { | |
d3eb5eae | 3168 | gen_helper_enter_mmx(cpu_env); |
664e0f19 FB |
3169 | } |
3170 | ||
0af10c86 | 3171 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3172 | reg = ((modrm >> 3) & 7); |
3173 | if (is_xmm) | |
3174 | reg |= rex_r; | |
3175 | mod = (modrm >> 6) & 3; | |
d3eb5eae | 3176 | if (sse_fn_epp == SSE_SPECIAL) { |
664e0f19 FB |
3177 | b |= (b1 << 8); |
3178 | switch(b) { | |
3179 | case 0x0e7: /* movntq */ | |
5fafdf24 | 3180 | if (mod == 3) |
664e0f19 | 3181 | goto illegal_op; |
4eeb3939 | 3182 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3183 | gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx)); |
664e0f19 FB |
3184 | break; |
3185 | case 0x1e7: /* movntdq */ | |
3186 | case 0x02b: /* movntps */ | |
3187 | case 0x12b: /* movntps */ | |
2e21e749 T |
3188 | if (mod == 3) |
3189 | goto illegal_op; | |
4eeb3939 | 3190 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3191 | gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
2e21e749 | 3192 | break; |
465e9838 FB |
3193 | case 0x3f0: /* lddqu */ |
3194 | if (mod == 3) | |
664e0f19 | 3195 | goto illegal_op; |
4eeb3939 | 3196 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3197 | gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
664e0f19 | 3198 | break; |
d9f4bb27 AP |
3199 | case 0x22b: /* movntss */ |
3200 | case 0x32b: /* movntsd */ | |
3201 | if (mod == 3) | |
3202 | goto illegal_op; | |
4eeb3939 | 3203 | gen_lea_modrm(env, s, modrm); |
d9f4bb27 | 3204 | if (b1 & 1) { |
323d1876 | 3205 | gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
d9f4bb27 AP |
3206 | } else { |
3207 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3208 | xmm_regs[reg].XMM_L(0))); | |
fd8ca9f6 | 3209 | gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); |
d9f4bb27 AP |
3210 | } |
3211 | break; | |
664e0f19 | 3212 | case 0x6e: /* movd mm, ea */ |
dabd98dd FB |
3213 | #ifdef TARGET_X86_64 |
3214 | if (s->dflag == 2) { | |
4ba9938c | 3215 | gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0); |
5af45186 | 3216 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); |
5fafdf24 | 3217 | } else |
dabd98dd FB |
3218 | #endif |
3219 | { | |
4ba9938c | 3220 | gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0); |
5af45186 FB |
3221 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3222 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
a7812ae4 PB |
3223 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3224 | gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); | |
dabd98dd | 3225 | } |
664e0f19 FB |
3226 | break; |
3227 | case 0x16e: /* movd xmm, ea */ | |
dabd98dd FB |
3228 | #ifdef TARGET_X86_64 |
3229 | if (s->dflag == 2) { | |
4ba9938c | 3230 | gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0); |
5af45186 FB |
3231 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3232 | offsetof(CPUX86State,xmm_regs[reg])); | |
a7812ae4 | 3233 | gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); |
5fafdf24 | 3234 | } else |
dabd98dd FB |
3235 | #endif |
3236 | { | |
4ba9938c | 3237 | gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0); |
5af45186 FB |
3238 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3239 | offsetof(CPUX86State,xmm_regs[reg])); | |
b6abf97d | 3240 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 3241 | gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); |
dabd98dd | 3242 | } |
664e0f19 FB |
3243 | break; |
3244 | case 0x6f: /* movq mm, ea */ | |
3245 | if (mod != 3) { | |
4eeb3939 | 3246 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3247 | gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx)); |
664e0f19 FB |
3248 | } else { |
3249 | rm = (modrm & 7); | |
b6abf97d | 3250 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3251 | offsetof(CPUX86State,fpregs[rm].mmx)); |
b6abf97d | 3252 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3253 | offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3254 | } |
3255 | break; | |
3256 | case 0x010: /* movups */ | |
3257 | case 0x110: /* movupd */ | |
3258 | case 0x028: /* movaps */ | |
3259 | case 0x128: /* movapd */ | |
3260 | case 0x16f: /* movdqa xmm, ea */ | |
3261 | case 0x26f: /* movdqu xmm, ea */ | |
3262 | if (mod != 3) { | |
4eeb3939 | 3263 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3264 | gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
664e0f19 FB |
3265 | } else { |
3266 | rm = (modrm & 7) | REX_B(s); | |
3267 | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), | |
3268 | offsetof(CPUX86State,xmm_regs[rm])); | |
3269 | } | |
3270 | break; | |
3271 | case 0x210: /* movss xmm, ea */ | |
3272 | if (mod != 3) { | |
4eeb3939 | 3273 | gen_lea_modrm(env, s, modrm); |
909be183 | 3274 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
651ba608 | 3275 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
664e0f19 | 3276 | gen_op_movl_T0_0(); |
651ba608 FB |
3277 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); |
3278 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3279 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3280 | } else { |
3281 | rm = (modrm & 7) | REX_B(s); | |
3282 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3283 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3284 | } | |
3285 | break; | |
3286 | case 0x310: /* movsd xmm, ea */ | |
3287 | if (mod != 3) { | |
4eeb3939 | 3288 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3289 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3290 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 | 3291 | gen_op_movl_T0_0(); |
651ba608 FB |
3292 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3293 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3294 | } else { |
3295 | rm = (modrm & 7) | REX_B(s); | |
3296 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3297 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3298 | } | |
3299 | break; | |
3300 | case 0x012: /* movlps */ | |
3301 | case 0x112: /* movlpd */ | |
3302 | if (mod != 3) { | |
4eeb3939 | 3303 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3304 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3305 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3306 | } else { |
3307 | /* movhlps */ | |
3308 | rm = (modrm & 7) | REX_B(s); | |
3309 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3310 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3311 | } | |
3312 | break; | |
465e9838 FB |
3313 | case 0x212: /* movsldup */ |
3314 | if (mod != 3) { | |
4eeb3939 | 3315 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3316 | gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
465e9838 FB |
3317 | } else { |
3318 | rm = (modrm & 7) | REX_B(s); | |
3319 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3320 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3321 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3322 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); | |
3323 | } | |
3324 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3325 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3326 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3327 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3328 | break; | |
3329 | case 0x312: /* movddup */ | |
3330 | if (mod != 3) { | |
4eeb3939 | 3331 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3332 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3333 | xmm_regs[reg].XMM_Q(0))); | |
465e9838 FB |
3334 | } else { |
3335 | rm = (modrm & 7) | REX_B(s); | |
3336 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3337 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3338 | } | |
3339 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
ba6526df | 3340 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 | 3341 | break; |
664e0f19 FB |
3342 | case 0x016: /* movhps */ |
3343 | case 0x116: /* movhpd */ | |
3344 | if (mod != 3) { | |
4eeb3939 | 3345 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3346 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3347 | xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3348 | } else { |
3349 | /* movlhps */ | |
3350 | rm = (modrm & 7) | REX_B(s); | |
3351 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
3352 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3353 | } | |
3354 | break; | |
3355 | case 0x216: /* movshdup */ | |
3356 | if (mod != 3) { | |
4eeb3939 | 3357 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3358 | gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
664e0f19 FB |
3359 | } else { |
3360 | rm = (modrm & 7) | REX_B(s); | |
3361 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3362 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); | |
3363 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3364 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); | |
3365 | } | |
3366 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3367 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); | |
3368 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3369 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
3370 | break; | |
d9f4bb27 AP |
3371 | case 0x178: |
3372 | case 0x378: | |
3373 | { | |
3374 | int bit_index, field_length; | |
3375 | ||
3376 | if (b1 == 1 && reg != 0) | |
3377 | goto illegal_op; | |
0af10c86 BS |
3378 | field_length = cpu_ldub_code(env, s->pc++) & 0x3F; |
3379 | bit_index = cpu_ldub_code(env, s->pc++) & 0x3F; | |
d9f4bb27 AP |
3380 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3381 | offsetof(CPUX86State,xmm_regs[reg])); | |
3382 | if (b1 == 1) | |
d3eb5eae BS |
3383 | gen_helper_extrq_i(cpu_env, cpu_ptr0, |
3384 | tcg_const_i32(bit_index), | |
3385 | tcg_const_i32(field_length)); | |
d9f4bb27 | 3386 | else |
d3eb5eae BS |
3387 | gen_helper_insertq_i(cpu_env, cpu_ptr0, |
3388 | tcg_const_i32(bit_index), | |
3389 | tcg_const_i32(field_length)); | |
d9f4bb27 AP |
3390 | } |
3391 | break; | |
664e0f19 | 3392 | case 0x7e: /* movd ea, mm */ |
dabd98dd FB |
3393 | #ifdef TARGET_X86_64 |
3394 | if (s->dflag == 2) { | |
5af45186 FB |
3395 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3396 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
4ba9938c | 3397 | gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1); |
5fafdf24 | 3398 | } else |
dabd98dd FB |
3399 | #endif |
3400 | { | |
5af45186 FB |
3401 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3402 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); | |
4ba9938c | 3403 | gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1); |
dabd98dd | 3404 | } |
664e0f19 FB |
3405 | break; |
3406 | case 0x17e: /* movd ea, xmm */ | |
dabd98dd FB |
3407 | #ifdef TARGET_X86_64 |
3408 | if (s->dflag == 2) { | |
5af45186 FB |
3409 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3410 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
4ba9938c | 3411 | gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1); |
5fafdf24 | 3412 | } else |
dabd98dd FB |
3413 | #endif |
3414 | { | |
5af45186 FB |
3415 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3416 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
4ba9938c | 3417 | gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1); |
dabd98dd | 3418 | } |
664e0f19 FB |
3419 | break; |
3420 | case 0x27e: /* movq xmm, ea */ | |
3421 | if (mod != 3) { | |
4eeb3939 | 3422 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3423 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3424 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3425 | } else { |
3426 | rm = (modrm & 7) | REX_B(s); | |
3427 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3428 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3429 | } | |
3430 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
3431 | break; | |
3432 | case 0x7f: /* movq ea, mm */ | |
3433 | if (mod != 3) { | |
4eeb3939 | 3434 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3435 | gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx)); |
664e0f19 FB |
3436 | } else { |
3437 | rm = (modrm & 7); | |
3438 | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), | |
3439 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
3440 | } | |
3441 | break; | |
3442 | case 0x011: /* movups */ | |
3443 | case 0x111: /* movupd */ | |
3444 | case 0x029: /* movaps */ | |
3445 | case 0x129: /* movapd */ | |
3446 | case 0x17f: /* movdqa ea, xmm */ | |
3447 | case 0x27f: /* movdqu ea, xmm */ | |
3448 | if (mod != 3) { | |
4eeb3939 | 3449 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3450 | gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
664e0f19 FB |
3451 | } else { |
3452 | rm = (modrm & 7) | REX_B(s); | |
3453 | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), | |
3454 | offsetof(CPUX86State,xmm_regs[reg])); | |
3455 | } | |
3456 | break; | |
3457 | case 0x211: /* movss ea, xmm */ | |
3458 | if (mod != 3) { | |
4eeb3939 | 3459 | gen_lea_modrm(env, s, modrm); |
651ba608 | 3460 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
fd8ca9f6 | 3461 | gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); |
664e0f19 FB |
3462 | } else { |
3463 | rm = (modrm & 7) | REX_B(s); | |
3464 | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), | |
3465 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3466 | } | |
3467 | break; | |
3468 | case 0x311: /* movsd ea, xmm */ | |
3469 | if (mod != 3) { | |
4eeb3939 | 3470 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3471 | gen_stq_env_A0(s, offsetof(CPUX86State, |
3472 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3473 | } else { |
3474 | rm = (modrm & 7) | REX_B(s); | |
3475 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3476 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3477 | } | |
3478 | break; | |
3479 | case 0x013: /* movlps */ | |
3480 | case 0x113: /* movlpd */ | |
3481 | if (mod != 3) { | |
4eeb3939 | 3482 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3483 | gen_stq_env_A0(s, offsetof(CPUX86State, |
3484 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3485 | } else { |
3486 | goto illegal_op; | |
3487 | } | |
3488 | break; | |
3489 | case 0x017: /* movhps */ | |
3490 | case 0x117: /* movhpd */ | |
3491 | if (mod != 3) { | |
4eeb3939 | 3492 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3493 | gen_stq_env_A0(s, offsetof(CPUX86State, |
3494 | xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3495 | } else { |
3496 | goto illegal_op; | |
3497 | } | |
3498 | break; | |
3499 | case 0x71: /* shift mm, im */ | |
3500 | case 0x72: | |
3501 | case 0x73: | |
3502 | case 0x171: /* shift xmm, im */ | |
3503 | case 0x172: | |
3504 | case 0x173: | |
c045af25 AK |
3505 | if (b1 >= 2) { |
3506 | goto illegal_op; | |
3507 | } | |
0af10c86 | 3508 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3509 | if (is_xmm) { |
3510 | gen_op_movl_T0_im(val); | |
651ba608 | 3511 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 | 3512 | gen_op_movl_T0_0(); |
651ba608 | 3513 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); |
664e0f19 FB |
3514 | op1_offset = offsetof(CPUX86State,xmm_t0); |
3515 | } else { | |
3516 | gen_op_movl_T0_im(val); | |
651ba608 | 3517 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); |
664e0f19 | 3518 | gen_op_movl_T0_0(); |
651ba608 | 3519 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); |
664e0f19 FB |
3520 | op1_offset = offsetof(CPUX86State,mmx_t0); |
3521 | } | |
d3eb5eae BS |
3522 | sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + |
3523 | (((modrm >> 3)) & 7)][b1]; | |
3524 | if (!sse_fn_epp) { | |
664e0f19 | 3525 | goto illegal_op; |
c4baa050 | 3526 | } |
664e0f19 FB |
3527 | if (is_xmm) { |
3528 | rm = (modrm & 7) | REX_B(s); | |
3529 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3530 | } else { | |
3531 | rm = (modrm & 7); | |
3532 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3533 | } | |
5af45186 FB |
3534 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3535 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); | |
d3eb5eae | 3536 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3537 | break; |
3538 | case 0x050: /* movmskps */ | |
664e0f19 | 3539 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3540 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3541 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3542 | gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3543 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
4ba9938c | 3544 | gen_op_mov_reg_T0(MO_32, reg); |
664e0f19 FB |
3545 | break; |
3546 | case 0x150: /* movmskpd */ | |
664e0f19 | 3547 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3548 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3549 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3550 | gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3551 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
4ba9938c | 3552 | gen_op_mov_reg_T0(MO_32, reg); |
664e0f19 FB |
3553 | break; |
3554 | case 0x02a: /* cvtpi2ps */ | |
3555 | case 0x12a: /* cvtpi2pd */ | |
d3eb5eae | 3556 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3557 | if (mod != 3) { |
4eeb3939 | 3558 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 3559 | op2_offset = offsetof(CPUX86State,mmx_t0); |
323d1876 | 3560 | gen_ldq_env_A0(s, op2_offset); |
664e0f19 FB |
3561 | } else { |
3562 | rm = (modrm & 7); | |
3563 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3564 | } | |
3565 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3566 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3567 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3568 | switch(b >> 8) { |
3569 | case 0x0: | |
d3eb5eae | 3570 | gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3571 | break; |
3572 | default: | |
3573 | case 0x1: | |
d3eb5eae | 3574 | gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3575 | break; |
3576 | } | |
3577 | break; | |
3578 | case 0x22a: /* cvtsi2ss */ | |
3579 | case 0x32a: /* cvtsi2sd */ | |
4ba9938c | 3580 | ot = (s->dflag == 2) ? MO_64 : MO_32; |
0af10c86 | 3581 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
664e0f19 | 3582 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
5af45186 | 3583 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4ba9938c | 3584 | if (ot == MO_32) { |
d3eb5eae | 3585 | SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1]; |
28e10711 | 3586 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 3587 | sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32); |
28e10711 | 3588 | } else { |
11f8cdbc | 3589 | #ifdef TARGET_X86_64 |
d3eb5eae BS |
3590 | SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1]; |
3591 | sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]); | |
11f8cdbc SW |
3592 | #else |
3593 | goto illegal_op; | |
3594 | #endif | |
28e10711 | 3595 | } |
664e0f19 FB |
3596 | break; |
3597 | case 0x02c: /* cvttps2pi */ | |
3598 | case 0x12c: /* cvttpd2pi */ | |
3599 | case 0x02d: /* cvtps2pi */ | |
3600 | case 0x12d: /* cvtpd2pi */ | |
d3eb5eae | 3601 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3602 | if (mod != 3) { |
4eeb3939 | 3603 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 3604 | op2_offset = offsetof(CPUX86State,xmm_t0); |
323d1876 | 3605 | gen_ldo_env_A0(s, op2_offset); |
664e0f19 FB |
3606 | } else { |
3607 | rm = (modrm & 7) | REX_B(s); | |
3608 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3609 | } | |
3610 | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx); | |
5af45186 FB |
3611 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3612 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3613 | switch(b) { |
3614 | case 0x02c: | |
d3eb5eae | 3615 | gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3616 | break; |
3617 | case 0x12c: | |
d3eb5eae | 3618 | gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3619 | break; |
3620 | case 0x02d: | |
d3eb5eae | 3621 | gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3622 | break; |
3623 | case 0x12d: | |
d3eb5eae | 3624 | gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3625 | break; |
3626 | } | |
3627 | break; | |
3628 | case 0x22c: /* cvttss2si */ | |
3629 | case 0x32c: /* cvttsd2si */ | |
3630 | case 0x22d: /* cvtss2si */ | |
3631 | case 0x32d: /* cvtsd2si */ | |
4ba9938c | 3632 | ot = (s->dflag == 2) ? MO_64 : MO_32; |
31313213 | 3633 | if (mod != 3) { |
4eeb3939 | 3634 | gen_lea_modrm(env, s, modrm); |
31313213 | 3635 | if ((b >> 8) & 1) { |
323d1876 | 3636 | gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0))); |
31313213 | 3637 | } else { |
909be183 | 3638 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
651ba608 | 3639 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
31313213 FB |
3640 | } |
3641 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3642 | } else { | |
3643 | rm = (modrm & 7) | REX_B(s); | |
3644 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3645 | } | |
5af45186 | 3646 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
4ba9938c | 3647 | if (ot == MO_32) { |
d3eb5eae | 3648 | SSEFunc_i_ep sse_fn_i_ep = |
bedc2ac1 | 3649 | sse_op_table3bi[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3650 | sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3651 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
5af45186 | 3652 | } else { |
11f8cdbc | 3653 | #ifdef TARGET_X86_64 |
d3eb5eae | 3654 | SSEFunc_l_ep sse_fn_l_ep = |
bedc2ac1 | 3655 | sse_op_table3bq[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3656 | sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0); |
11f8cdbc SW |
3657 | #else |
3658 | goto illegal_op; | |
3659 | #endif | |
5af45186 | 3660 | } |
57fec1fe | 3661 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3662 | break; |
3663 | case 0xc4: /* pinsrw */ | |
5fafdf24 | 3664 | case 0x1c4: |
d1e42c5c | 3665 | s->rip_offset = 1; |
4ba9938c | 3666 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
0af10c86 | 3667 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3668 | if (b1) { |
3669 | val &= 7; | |
5af45186 FB |
3670 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3671 | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); | |
664e0f19 FB |
3672 | } else { |
3673 | val &= 3; | |
5af45186 FB |
3674 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3675 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); | |
664e0f19 FB |
3676 | } |
3677 | break; | |
3678 | case 0xc5: /* pextrw */ | |
5fafdf24 | 3679 | case 0x1c5: |
664e0f19 FB |
3680 | if (mod != 3) |
3681 | goto illegal_op; | |
4ba9938c | 3682 | ot = (s->dflag == 2) ? MO_64 : MO_32; |
0af10c86 | 3683 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3684 | if (b1) { |
3685 | val &= 7; | |
3686 | rm = (modrm & 7) | REX_B(s); | |
5af45186 FB |
3687 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3688 | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); | |
664e0f19 FB |
3689 | } else { |
3690 | val &= 3; | |
3691 | rm = (modrm & 7); | |
5af45186 FB |
3692 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3693 | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); | |
664e0f19 FB |
3694 | } |
3695 | reg = ((modrm >> 3) & 7) | rex_r; | |
6dc2d0da | 3696 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3697 | break; |
3698 | case 0x1d6: /* movq ea, xmm */ | |
3699 | if (mod != 3) { | |
4eeb3939 | 3700 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3701 | gen_stq_env_A0(s, offsetof(CPUX86State, |
3702 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3703 | } else { |
3704 | rm = (modrm & 7) | REX_B(s); | |
3705 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3706 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3707 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3708 | } | |
3709 | break; | |
3710 | case 0x2d6: /* movq2dq */ | |
d3eb5eae | 3711 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3712 | rm = (modrm & 7); |
3713 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3714 | offsetof(CPUX86State,fpregs[rm].mmx)); | |
3715 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3716 | break; |
3717 | case 0x3d6: /* movdq2q */ | |
d3eb5eae | 3718 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3719 | rm = (modrm & 7) | REX_B(s); |
3720 | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), | |
3721 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
664e0f19 FB |
3722 | break; |
3723 | case 0xd7: /* pmovmskb */ | |
3724 | case 0x1d7: | |
3725 | if (mod != 3) | |
3726 | goto illegal_op; | |
3727 | if (b1) { | |
3728 | rm = (modrm & 7) | REX_B(s); | |
5af45186 | 3729 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
d3eb5eae | 3730 | gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 FB |
3731 | } else { |
3732 | rm = (modrm & 7); | |
5af45186 | 3733 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
d3eb5eae | 3734 | gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 | 3735 | } |
b6abf97d | 3736 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
664e0f19 | 3737 | reg = ((modrm >> 3) & 7) | rex_r; |
4ba9938c | 3738 | gen_op_mov_reg_T0(MO_32, reg); |
664e0f19 | 3739 | break; |
111994ee | 3740 | |
4242b1bd | 3741 | case 0x138: |
000cacf6 | 3742 | case 0x038: |
4242b1bd | 3743 | b = modrm; |
111994ee RH |
3744 | if ((b & 0xf0) == 0xf0) { |
3745 | goto do_0f_38_fx; | |
3746 | } | |
0af10c86 | 3747 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
3748 | rm = modrm & 7; |
3749 | reg = ((modrm >> 3) & 7) | rex_r; | |
3750 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3751 | if (b1 >= 2) { |
3752 | goto illegal_op; | |
3753 | } | |
4242b1bd | 3754 | |
d3eb5eae BS |
3755 | sse_fn_epp = sse_op_table6[b].op[b1]; |
3756 | if (!sse_fn_epp) { | |
4242b1bd | 3757 | goto illegal_op; |
c4baa050 | 3758 | } |
222a3336 AZ |
3759 | if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask)) |
3760 | goto illegal_op; | |
4242b1bd AZ |
3761 | |
3762 | if (b1) { | |
3763 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3764 | if (mod == 3) { | |
3765 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3766 | } else { | |
3767 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
4eeb3939 | 3768 | gen_lea_modrm(env, s, modrm); |
222a3336 AZ |
3769 | switch (b) { |
3770 | case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ | |
3771 | case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ | |
3772 | case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ | |
323d1876 | 3773 | gen_ldq_env_A0(s, op2_offset + |
222a3336 AZ |
3774 | offsetof(XMMReg, XMM_Q(0))); |
3775 | break; | |
3776 | case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ | |
3777 | case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ | |
3c5f4116 RH |
3778 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
3779 | s->mem_index, MO_LEUL); | |
222a3336 AZ |
3780 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + |
3781 | offsetof(XMMReg, XMM_L(0))); | |
3782 | break; | |
3783 | case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ | |
3c5f4116 RH |
3784 | tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0, |
3785 | s->mem_index, MO_LEUW); | |
222a3336 AZ |
3786 | tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + |
3787 | offsetof(XMMReg, XMM_W(0))); | |
3788 | break; | |
3789 | case 0x2a: /* movntqda */ | |
323d1876 | 3790 | gen_ldo_env_A0(s, op1_offset); |
222a3336 AZ |
3791 | return; |
3792 | default: | |
323d1876 | 3793 | gen_ldo_env_A0(s, op2_offset); |
222a3336 | 3794 | } |
4242b1bd AZ |
3795 | } |
3796 | } else { | |
3797 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3798 | if (mod == 3) { | |
3799 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3800 | } else { | |
3801 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
4eeb3939 | 3802 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3803 | gen_ldq_env_A0(s, op2_offset); |
4242b1bd AZ |
3804 | } |
3805 | } | |
d3eb5eae | 3806 | if (sse_fn_epp == SSE_SPECIAL) { |
222a3336 | 3807 | goto illegal_op; |
c4baa050 | 3808 | } |
222a3336 | 3809 | |
4242b1bd AZ |
3810 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3811 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 3812 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
222a3336 | 3813 | |
3ca51d07 RH |
3814 | if (b == 0x17) { |
3815 | set_cc_op(s, CC_OP_EFLAGS); | |
3816 | } | |
4242b1bd | 3817 | break; |
111994ee RH |
3818 | |
3819 | case 0x238: | |
3820 | case 0x338: | |
3821 | do_0f_38_fx: | |
3822 | /* Various integer extensions at 0f 38 f[0-f]. */ | |
3823 | b = modrm | (b1 << 8); | |
0af10c86 | 3824 | modrm = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
3825 | reg = ((modrm >> 3) & 7) | rex_r; |
3826 | ||
111994ee RH |
3827 | switch (b) { |
3828 | case 0x3f0: /* crc32 Gd,Eb */ | |
3829 | case 0x3f1: /* crc32 Gd,Ey */ | |
3830 | do_crc32: | |
3831 | if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) { | |
3832 | goto illegal_op; | |
3833 | } | |
3834 | if ((b & 0xff) == 0xf0) { | |
4ba9938c | 3835 | ot = MO_8; |
111994ee | 3836 | } else if (s->dflag != 2) { |
4ba9938c | 3837 | ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32); |
111994ee | 3838 | } else { |
4ba9938c | 3839 | ot = MO_64; |
111994ee | 3840 | } |
4242b1bd | 3841 | |
4ba9938c | 3842 | gen_op_mov_TN_reg(MO_32, 0, reg); |
111994ee RH |
3843 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3844 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); | |
3845 | gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, | |
3846 | cpu_T[0], tcg_const_i32(8 << ot)); | |
222a3336 | 3847 | |
4ba9938c | 3848 | ot = (s->dflag == 2) ? MO_64 : MO_32; |
111994ee RH |
3849 | gen_op_mov_reg_T0(ot, reg); |
3850 | break; | |
222a3336 | 3851 | |
111994ee RH |
3852 | case 0x1f0: /* crc32 or movbe */ |
3853 | case 0x1f1: | |
3854 | /* For these insns, the f3 prefix is supposed to have priority | |
3855 | over the 66 prefix, but that's not what we implement above | |
3856 | setting b1. */ | |
3857 | if (s->prefix & PREFIX_REPNZ) { | |
3858 | goto do_crc32; | |
3859 | } | |
3860 | /* FALLTHRU */ | |
3861 | case 0x0f0: /* movbe Gy,My */ | |
3862 | case 0x0f1: /* movbe My,Gy */ | |
3863 | if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) { | |
3864 | goto illegal_op; | |
3865 | } | |
3866 | if (s->dflag != 2) { | |
4ba9938c | 3867 | ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32); |
111994ee | 3868 | } else { |
4ba9938c | 3869 | ot = MO_64; |
111994ee RH |
3870 | } |
3871 | ||
3655a19f | 3872 | gen_lea_modrm(env, s, modrm); |
111994ee | 3873 | if ((b & 1) == 0) { |
3655a19f RH |
3874 | tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, |
3875 | s->mem_index, ot | MO_BE); | |
111994ee RH |
3876 | gen_op_mov_reg_T0(ot, reg); |
3877 | } else { | |
3655a19f RH |
3878 | tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0, |
3879 | s->mem_index, ot | MO_BE); | |
111994ee RH |
3880 | } |
3881 | break; | |
3882 | ||
7073fbad RH |
3883 | case 0x0f2: /* andn Gy, By, Ey */ |
3884 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1) | |
3885 | || !(s->prefix & PREFIX_VEX) | |
3886 | || s->vex_l != 0) { | |
3887 | goto illegal_op; | |
3888 | } | |
4ba9938c | 3889 | ot = s->dflag == 2 ? MO_64 : MO_32; |
7073fbad RH |
3890 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3891 | tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]); | |
3892 | gen_op_mov_reg_T0(ot, reg); | |
3893 | gen_op_update1_cc(); | |
3894 | set_cc_op(s, CC_OP_LOGICB + ot); | |
3895 | break; | |
3896 | ||
c7ab7565 RH |
3897 | case 0x0f7: /* bextr Gy, Ey, By */ |
3898 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1) | |
3899 | || !(s->prefix & PREFIX_VEX) | |
3900 | || s->vex_l != 0) { | |
3901 | goto illegal_op; | |
3902 | } | |
4ba9938c | 3903 | ot = s->dflag == 2 ? MO_64 : MO_32; |
c7ab7565 RH |
3904 | { |
3905 | TCGv bound, zero; | |
3906 | ||
3907 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); | |
3908 | /* Extract START, and shift the operand. | |
3909 | Shifts larger than operand size get zeros. */ | |
3910 | tcg_gen_ext8u_tl(cpu_A0, cpu_regs[s->vex_v]); | |
3911 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_A0); | |
3912 | ||
4ba9938c | 3913 | bound = tcg_const_tl(ot == MO_64 ? 63 : 31); |
c7ab7565 RH |
3914 | zero = tcg_const_tl(0); |
3915 | tcg_gen_movcond_tl(TCG_COND_LEU, cpu_T[0], cpu_A0, bound, | |
3916 | cpu_T[0], zero); | |
3917 | tcg_temp_free(zero); | |
3918 | ||
3919 | /* Extract the LEN into a mask. Lengths larger than | |
3920 | operand size get all ones. */ | |
3921 | tcg_gen_shri_tl(cpu_A0, cpu_regs[s->vex_v], 8); | |
3922 | tcg_gen_ext8u_tl(cpu_A0, cpu_A0); | |
3923 | tcg_gen_movcond_tl(TCG_COND_LEU, cpu_A0, cpu_A0, bound, | |
3924 | cpu_A0, bound); | |
3925 | tcg_temp_free(bound); | |
3926 | tcg_gen_movi_tl(cpu_T[1], 1); | |
3927 | tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_A0); | |
3928 | tcg_gen_subi_tl(cpu_T[1], cpu_T[1], 1); | |
3929 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
3930 | ||
3931 | gen_op_mov_reg_T0(ot, reg); | |
3932 | gen_op_update1_cc(); | |
3933 | set_cc_op(s, CC_OP_LOGICB + ot); | |
3934 | } | |
3935 | break; | |
3936 | ||
02ea1e6b RH |
3937 | case 0x0f5: /* bzhi Gy, Ey, By */ |
3938 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
3939 | || !(s->prefix & PREFIX_VEX) | |
3940 | || s->vex_l != 0) { | |
3941 | goto illegal_op; | |
3942 | } | |
4ba9938c | 3943 | ot = s->dflag == 2 ? MO_64 : MO_32; |
02ea1e6b RH |
3944 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3945 | tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]); | |
3946 | { | |
4ba9938c | 3947 | TCGv bound = tcg_const_tl(ot == MO_64 ? 63 : 31); |
02ea1e6b RH |
3948 | /* Note that since we're using BMILG (in order to get O |
3949 | cleared) we need to store the inverse into C. */ | |
3950 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src, | |
3951 | cpu_T[1], bound); | |
3952 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_T[1], cpu_T[1], | |
3953 | bound, bound, cpu_T[1]); | |
3954 | tcg_temp_free(bound); | |
3955 | } | |
3956 | tcg_gen_movi_tl(cpu_A0, -1); | |
3957 | tcg_gen_shl_tl(cpu_A0, cpu_A0, cpu_T[1]); | |
3958 | tcg_gen_andc_tl(cpu_T[0], cpu_T[0], cpu_A0); | |
3959 | gen_op_mov_reg_T0(ot, reg); | |
3960 | gen_op_update1_cc(); | |
3961 | set_cc_op(s, CC_OP_BMILGB + ot); | |
3962 | break; | |
3963 | ||
5f1f4b17 RH |
3964 | case 0x3f6: /* mulx By, Gy, rdx, Ey */ |
3965 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
3966 | || !(s->prefix & PREFIX_VEX) | |
3967 | || s->vex_l != 0) { | |
3968 | goto illegal_op; | |
3969 | } | |
4ba9938c | 3970 | ot = s->dflag == 2 ? MO_64 : MO_32; |
5f1f4b17 RH |
3971 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3972 | switch (ot) { | |
5f1f4b17 | 3973 | default: |
a4bcea3d RH |
3974 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3975 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EDX]); | |
3976 | tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32, | |
3977 | cpu_tmp2_i32, cpu_tmp3_i32); | |
3978 | tcg_gen_extu_i32_tl(cpu_regs[s->vex_v], cpu_tmp2_i32); | |
3979 | tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp3_i32); | |
5f1f4b17 RH |
3980 | break; |
3981 | #ifdef TARGET_X86_64 | |
4ba9938c | 3982 | case MO_64: |
a4bcea3d RH |
3983 | tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg], |
3984 | cpu_T[0], cpu_regs[R_EDX]); | |
5f1f4b17 RH |
3985 | break; |
3986 | #endif | |
3987 | } | |
3988 | break; | |
3989 | ||
0592f74a RH |
3990 | case 0x3f5: /* pdep Gy, By, Ey */ |
3991 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
3992 | || !(s->prefix & PREFIX_VEX) | |
3993 | || s->vex_l != 0) { | |
3994 | goto illegal_op; | |
3995 | } | |
4ba9938c | 3996 | ot = s->dflag == 2 ? MO_64 : MO_32; |
0592f74a RH |
3997 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3998 | /* Note that by zero-extending the mask operand, we | |
3999 | automatically handle zero-extending the result. */ | |
4000 | if (s->dflag == 2) { | |
4001 | tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]); | |
4002 | } else { | |
4003 | tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]); | |
4004 | } | |
4005 | gen_helper_pdep(cpu_regs[reg], cpu_T[0], cpu_T[1]); | |
4006 | break; | |
4007 | ||
4008 | case 0x2f5: /* pext Gy, By, Ey */ | |
4009 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
4010 | || !(s->prefix & PREFIX_VEX) | |
4011 | || s->vex_l != 0) { | |
4012 | goto illegal_op; | |
4013 | } | |
4ba9938c | 4014 | ot = s->dflag == 2 ? MO_64 : MO_32; |
0592f74a RH |
4015 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
4016 | /* Note that by zero-extending the mask operand, we | |
4017 | automatically handle zero-extending the result. */ | |
4018 | if (s->dflag == 2) { | |
4019 | tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]); | |
4020 | } else { | |
4021 | tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]); | |
4022 | } | |
4023 | gen_helper_pext(cpu_regs[reg], cpu_T[0], cpu_T[1]); | |
4024 | break; | |
4025 | ||
cd7f97ca RH |
4026 | case 0x1f6: /* adcx Gy, Ey */ |
4027 | case 0x2f6: /* adox Gy, Ey */ | |
4028 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX)) { | |
4029 | goto illegal_op; | |
4030 | } else { | |
76f13133 | 4031 | TCGv carry_in, carry_out, zero; |
cd7f97ca RH |
4032 | int end_op; |
4033 | ||
4ba9938c | 4034 | ot = (s->dflag == 2 ? MO_64 : MO_32); |
cd7f97ca RH |
4035 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
4036 | ||
4037 | /* Re-use the carry-out from a previous round. */ | |
4038 | TCGV_UNUSED(carry_in); | |
4039 | carry_out = (b == 0x1f6 ? cpu_cc_dst : cpu_cc_src2); | |
4040 | switch (s->cc_op) { | |
4041 | case CC_OP_ADCX: | |
4042 | if (b == 0x1f6) { | |
4043 | carry_in = cpu_cc_dst; | |
4044 | end_op = CC_OP_ADCX; | |
4045 | } else { | |
4046 | end_op = CC_OP_ADCOX; | |
4047 | } | |
4048 | break; | |
4049 | case CC_OP_ADOX: | |
4050 | if (b == 0x1f6) { | |
4051 | end_op = CC_OP_ADCOX; | |
4052 | } else { | |
4053 | carry_in = cpu_cc_src2; | |
4054 | end_op = CC_OP_ADOX; | |
4055 | } | |
4056 | break; | |
4057 | case CC_OP_ADCOX: | |
4058 | end_op = CC_OP_ADCOX; | |
4059 | carry_in = carry_out; | |
4060 | break; | |
4061 | default: | |
c53de1a2 | 4062 | end_op = (b == 0x1f6 ? CC_OP_ADCX : CC_OP_ADOX); |
cd7f97ca RH |
4063 | break; |
4064 | } | |
4065 | /* If we can't reuse carry-out, get it out of EFLAGS. */ | |
4066 | if (TCGV_IS_UNUSED(carry_in)) { | |
4067 | if (s->cc_op != CC_OP_ADCX && s->cc_op != CC_OP_ADOX) { | |
4068 | gen_compute_eflags(s); | |
4069 | } | |
4070 | carry_in = cpu_tmp0; | |
4071 | tcg_gen_shri_tl(carry_in, cpu_cc_src, | |
4072 | ctz32(b == 0x1f6 ? CC_C : CC_O)); | |
4073 | tcg_gen_andi_tl(carry_in, carry_in, 1); | |
4074 | } | |
4075 | ||
4076 | switch (ot) { | |
4077 | #ifdef TARGET_X86_64 | |
4ba9938c | 4078 | case MO_32: |
cd7f97ca RH |
4079 | /* If we know TL is 64-bit, and we want a 32-bit |
4080 | result, just do everything in 64-bit arithmetic. */ | |
4081 | tcg_gen_ext32u_i64(cpu_regs[reg], cpu_regs[reg]); | |
4082 | tcg_gen_ext32u_i64(cpu_T[0], cpu_T[0]); | |
4083 | tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_regs[reg]); | |
4084 | tcg_gen_add_i64(cpu_T[0], cpu_T[0], carry_in); | |
4085 | tcg_gen_ext32u_i64(cpu_regs[reg], cpu_T[0]); | |
4086 | tcg_gen_shri_i64(carry_out, cpu_T[0], 32); | |
4087 | break; | |
4088 | #endif | |
4089 | default: | |
4090 | /* Otherwise compute the carry-out in two steps. */ | |
76f13133 RH |
4091 | zero = tcg_const_tl(0); |
4092 | tcg_gen_add2_tl(cpu_T[0], carry_out, | |
4093 | cpu_T[0], zero, | |
4094 | carry_in, zero); | |
4095 | tcg_gen_add2_tl(cpu_regs[reg], carry_out, | |
4096 | cpu_regs[reg], carry_out, | |
4097 | cpu_T[0], zero); | |
4098 | tcg_temp_free(zero); | |
cd7f97ca RH |
4099 | break; |
4100 | } | |
cd7f97ca RH |
4101 | set_cc_op(s, end_op); |
4102 | } | |
4103 | break; | |
4104 | ||
4a554890 RH |
4105 | case 0x1f7: /* shlx Gy, Ey, By */ |
4106 | case 0x2f7: /* sarx Gy, Ey, By */ | |
4107 | case 0x3f7: /* shrx Gy, Ey, By */ | |
4108 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
4109 | || !(s->prefix & PREFIX_VEX) | |
4110 | || s->vex_l != 0) { | |
4111 | goto illegal_op; | |
4112 | } | |
4ba9938c | 4113 | ot = (s->dflag == 2 ? MO_64 : MO_32); |
4a554890 | 4114 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
4ba9938c | 4115 | if (ot == MO_64) { |
4a554890 RH |
4116 | tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63); |
4117 | } else { | |
4118 | tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 31); | |
4119 | } | |
4120 | if (b == 0x1f7) { | |
4121 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4122 | } else if (b == 0x2f7) { | |
4ba9938c | 4123 | if (ot != MO_64) { |
4a554890 RH |
4124 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4125 | } | |
4126 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4127 | } else { | |
4ba9938c | 4128 | if (ot != MO_64) { |
4a554890 RH |
4129 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
4130 | } | |
4131 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4132 | } | |
4133 | gen_op_mov_reg_T0(ot, reg); | |
4134 | break; | |
4135 | ||
bc4b43dc RH |
4136 | case 0x0f3: |
4137 | case 0x1f3: | |
4138 | case 0x2f3: | |
4139 | case 0x3f3: /* Group 17 */ | |
4140 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1) | |
4141 | || !(s->prefix & PREFIX_VEX) | |
4142 | || s->vex_l != 0) { | |
4143 | goto illegal_op; | |
4144 | } | |
4ba9938c | 4145 | ot = s->dflag == 2 ? MO_64 : MO_32; |
bc4b43dc RH |
4146 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
4147 | ||
4148 | switch (reg & 7) { | |
4149 | case 1: /* blsr By,Ey */ | |
4150 | tcg_gen_neg_tl(cpu_T[1], cpu_T[0]); | |
4151 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4152 | gen_op_mov_reg_T0(ot, s->vex_v); | |
4153 | gen_op_update2_cc(); | |
4154 | set_cc_op(s, CC_OP_BMILGB + ot); | |
4155 | break; | |
4156 | ||
4157 | case 2: /* blsmsk By,Ey */ | |
4158 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4159 | tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1); | |
4160 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_cc_src); | |
4161 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4162 | set_cc_op(s, CC_OP_BMILGB + ot); | |
4163 | break; | |
4164 | ||
4165 | case 3: /* blsi By, Ey */ | |
4166 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4167 | tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1); | |
4168 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_cc_src); | |
4169 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4170 | set_cc_op(s, CC_OP_BMILGB + ot); | |
4171 | break; | |
4172 | ||
4173 | default: | |
4174 | goto illegal_op; | |
4175 | } | |
4176 | break; | |
4177 | ||
111994ee RH |
4178 | default: |
4179 | goto illegal_op; | |
4180 | } | |
222a3336 | 4181 | break; |
111994ee | 4182 | |
222a3336 AZ |
4183 | case 0x03a: |
4184 | case 0x13a: | |
4242b1bd | 4185 | b = modrm; |
0af10c86 | 4186 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
4187 | rm = modrm & 7; |
4188 | reg = ((modrm >> 3) & 7) | rex_r; | |
4189 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
4190 | if (b1 >= 2) { |
4191 | goto illegal_op; | |
4192 | } | |
4242b1bd | 4193 | |
d3eb5eae BS |
4194 | sse_fn_eppi = sse_op_table7[b].op[b1]; |
4195 | if (!sse_fn_eppi) { | |
4242b1bd | 4196 | goto illegal_op; |
c4baa050 | 4197 | } |
222a3336 AZ |
4198 | if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) |
4199 | goto illegal_op; | |
4200 | ||
d3eb5eae | 4201 | if (sse_fn_eppi == SSE_SPECIAL) { |
4ba9938c | 4202 | ot = (s->dflag == 2) ? MO_64 : MO_32; |
222a3336 AZ |
4203 | rm = (modrm & 7) | REX_B(s); |
4204 | if (mod != 3) | |
4eeb3939 | 4205 | gen_lea_modrm(env, s, modrm); |
222a3336 | 4206 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 4207 | val = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
4208 | switch (b) { |
4209 | case 0x14: /* pextrb */ | |
4210 | tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
4211 | xmm_regs[reg].XMM_B(val & 15))); | |
3523e4bd | 4212 | if (mod == 3) { |
222a3336 | 4213 | gen_op_mov_reg_T0(ot, rm); |
3523e4bd RH |
4214 | } else { |
4215 | tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0, | |
4216 | s->mem_index, MO_UB); | |
4217 | } | |
222a3336 AZ |
4218 | break; |
4219 | case 0x15: /* pextrw */ | |
4220 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
4221 | xmm_regs[reg].XMM_W(val & 7))); | |
3523e4bd | 4222 | if (mod == 3) { |
222a3336 | 4223 | gen_op_mov_reg_T0(ot, rm); |
3523e4bd RH |
4224 | } else { |
4225 | tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0, | |
4226 | s->mem_index, MO_LEUW); | |
4227 | } | |
222a3336 AZ |
4228 | break; |
4229 | case 0x16: | |
4ba9938c | 4230 | if (ot == MO_32) { /* pextrd */ |
222a3336 AZ |
4231 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
4232 | offsetof(CPUX86State, | |
4233 | xmm_regs[reg].XMM_L(val & 3))); | |
a7812ae4 | 4234 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
3523e4bd | 4235 | if (mod == 3) { |
a7812ae4 | 4236 | gen_op_mov_reg_v(ot, rm, cpu_T[0]); |
3523e4bd RH |
4237 | } else { |
4238 | tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0, | |
4239 | s->mem_index, MO_LEUL); | |
4240 | } | |
222a3336 | 4241 | } else { /* pextrq */ |
a7812ae4 | 4242 | #ifdef TARGET_X86_64 |
222a3336 AZ |
4243 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
4244 | offsetof(CPUX86State, | |
4245 | xmm_regs[reg].XMM_Q(val & 1))); | |
3523e4bd | 4246 | if (mod == 3) { |
222a3336 | 4247 | gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); |
3523e4bd RH |
4248 | } else { |
4249 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, | |
4250 | s->mem_index, MO_LEQ); | |
4251 | } | |
a7812ae4 PB |
4252 | #else |
4253 | goto illegal_op; | |
4254 | #endif | |
222a3336 AZ |
4255 | } |
4256 | break; | |
4257 | case 0x17: /* extractps */ | |
4258 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
4259 | xmm_regs[reg].XMM_L(val & 3))); | |
3523e4bd | 4260 | if (mod == 3) { |
222a3336 | 4261 | gen_op_mov_reg_T0(ot, rm); |
3523e4bd RH |
4262 | } else { |
4263 | tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0, | |
4264 | s->mem_index, MO_LEUL); | |
4265 | } | |
222a3336 AZ |
4266 | break; |
4267 | case 0x20: /* pinsrb */ | |
3c5f4116 | 4268 | if (mod == 3) { |
4ba9938c | 4269 | gen_op_mov_TN_reg(MO_32, 0, rm); |
3c5f4116 RH |
4270 | } else { |
4271 | tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, | |
4272 | s->mem_index, MO_UB); | |
4273 | } | |
34c6addd | 4274 | tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, |
222a3336 AZ |
4275 | xmm_regs[reg].XMM_B(val & 15))); |
4276 | break; | |
4277 | case 0x21: /* insertps */ | |
a7812ae4 | 4278 | if (mod == 3) { |
222a3336 AZ |
4279 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
4280 | offsetof(CPUX86State,xmm_regs[rm] | |
4281 | .XMM_L((val >> 6) & 3))); | |
a7812ae4 | 4282 | } else { |
3c5f4116 RH |
4283 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
4284 | s->mem_index, MO_LEUL); | |
a7812ae4 | 4285 | } |
222a3336 AZ |
4286 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
4287 | offsetof(CPUX86State,xmm_regs[reg] | |
4288 | .XMM_L((val >> 4) & 3))); | |
4289 | if ((val >> 0) & 1) | |
4290 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4291 | cpu_env, offsetof(CPUX86State, | |
4292 | xmm_regs[reg].XMM_L(0))); | |
4293 | if ((val >> 1) & 1) | |
4294 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4295 | cpu_env, offsetof(CPUX86State, | |
4296 | xmm_regs[reg].XMM_L(1))); | |
4297 | if ((val >> 2) & 1) | |
4298 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4299 | cpu_env, offsetof(CPUX86State, | |
4300 | xmm_regs[reg].XMM_L(2))); | |
4301 | if ((val >> 3) & 1) | |
4302 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4303 | cpu_env, offsetof(CPUX86State, | |
4304 | xmm_regs[reg].XMM_L(3))); | |
4305 | break; | |
4306 | case 0x22: | |
4ba9938c | 4307 | if (ot == MO_32) { /* pinsrd */ |
3c5f4116 | 4308 | if (mod == 3) { |
a7812ae4 | 4309 | gen_op_mov_v_reg(ot, cpu_tmp0, rm); |
3c5f4116 RH |
4310 | } else { |
4311 | tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0, | |
4312 | s->mem_index, MO_LEUL); | |
4313 | } | |
a7812ae4 | 4314 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
4315 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
4316 | offsetof(CPUX86State, | |
4317 | xmm_regs[reg].XMM_L(val & 3))); | |
4318 | } else { /* pinsrq */ | |
a7812ae4 | 4319 | #ifdef TARGET_X86_64 |
3c5f4116 | 4320 | if (mod == 3) { |
222a3336 | 4321 | gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); |
3c5f4116 RH |
4322 | } else { |
4323 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, | |
4324 | s->mem_index, MO_LEQ); | |
4325 | } | |
222a3336 AZ |
4326 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
4327 | offsetof(CPUX86State, | |
4328 | xmm_regs[reg].XMM_Q(val & 1))); | |
a7812ae4 PB |
4329 | #else |
4330 | goto illegal_op; | |
4331 | #endif | |
222a3336 AZ |
4332 | } |
4333 | break; | |
4334 | } | |
4335 | return; | |
4336 | } | |
4242b1bd AZ |
4337 | |
4338 | if (b1) { | |
4339 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4340 | if (mod == 3) { | |
4341 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
4342 | } else { | |
4343 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
4eeb3939 | 4344 | gen_lea_modrm(env, s, modrm); |
323d1876 | 4345 | gen_ldo_env_A0(s, op2_offset); |
4242b1bd AZ |
4346 | } |
4347 | } else { | |
4348 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4349 | if (mod == 3) { | |
4350 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4351 | } else { | |
4352 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
4eeb3939 | 4353 | gen_lea_modrm(env, s, modrm); |
323d1876 | 4354 | gen_ldq_env_A0(s, op2_offset); |
4242b1bd AZ |
4355 | } |
4356 | } | |
0af10c86 | 4357 | val = cpu_ldub_code(env, s->pc++); |
4242b1bd | 4358 | |
222a3336 | 4359 | if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ |
3ca51d07 | 4360 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 AZ |
4361 | |
4362 | if (s->dflag == 2) | |
4363 | /* The helper must use entire 64-bit gp registers */ | |
4364 | val |= 1 << 8; | |
4365 | } | |
4366 | ||
4242b1bd AZ |
4367 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4368 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4369 | sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
4242b1bd | 4370 | break; |
e2c3c2c5 RH |
4371 | |
4372 | case 0x33a: | |
4373 | /* Various integer extensions at 0f 3a f[0-f]. */ | |
4374 | b = modrm | (b1 << 8); | |
4375 | modrm = cpu_ldub_code(env, s->pc++); | |
4376 | reg = ((modrm >> 3) & 7) | rex_r; | |
4377 | ||
4378 | switch (b) { | |
4379 | case 0x3f0: /* rorx Gy,Ey, Ib */ | |
4380 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
4381 | || !(s->prefix & PREFIX_VEX) | |
4382 | || s->vex_l != 0) { | |
4383 | goto illegal_op; | |
4384 | } | |
4ba9938c | 4385 | ot = s->dflag == 2 ? MO_64 : MO_32; |
e2c3c2c5 RH |
4386 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
4387 | b = cpu_ldub_code(env, s->pc++); | |
4ba9938c | 4388 | if (ot == MO_64) { |
e2c3c2c5 RH |
4389 | tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], b & 63); |
4390 | } else { | |
4391 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
4392 | tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, b & 31); | |
4393 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); | |
4394 | } | |
4395 | gen_op_mov_reg_T0(ot, reg); | |
4396 | break; | |
4397 | ||
4398 | default: | |
4399 | goto illegal_op; | |
4400 | } | |
4401 | break; | |
4402 | ||
664e0f19 FB |
4403 | default: |
4404 | goto illegal_op; | |
4405 | } | |
4406 | } else { | |
4407 | /* generic MMX or SSE operation */ | |
d1e42c5c | 4408 | switch(b) { |
d1e42c5c FB |
4409 | case 0x70: /* pshufx insn */ |
4410 | case 0xc6: /* pshufx insn */ | |
4411 | case 0xc2: /* compare insns */ | |
4412 | s->rip_offset = 1; | |
4413 | break; | |
4414 | default: | |
4415 | break; | |
664e0f19 FB |
4416 | } |
4417 | if (is_xmm) { | |
4418 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4419 | if (mod != 3) { | |
4eeb3939 | 4420 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 4421 | op2_offset = offsetof(CPUX86State,xmm_t0); |
480c1cdb | 4422 | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
664e0f19 FB |
4423 | b == 0xc2)) { |
4424 | /* specific case for SSE single instructions */ | |
4425 | if (b1 == 2) { | |
4426 | /* 32 bit access */ | |
909be183 | 4427 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
651ba608 | 4428 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 FB |
4429 | } else { |
4430 | /* 64 bit access */ | |
323d1876 RH |
4431 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
4432 | xmm_t0.XMM_D(0))); | |
664e0f19 FB |
4433 | } |
4434 | } else { | |
323d1876 | 4435 | gen_ldo_env_A0(s, op2_offset); |
664e0f19 FB |
4436 | } |
4437 | } else { | |
4438 | rm = (modrm & 7) | REX_B(s); | |
4439 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
4440 | } | |
4441 | } else { | |
4442 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4443 | if (mod != 3) { | |
4eeb3939 | 4444 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 4445 | op2_offset = offsetof(CPUX86State,mmx_t0); |
323d1876 | 4446 | gen_ldq_env_A0(s, op2_offset); |
664e0f19 FB |
4447 | } else { |
4448 | rm = (modrm & 7); | |
4449 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4450 | } | |
4451 | } | |
4452 | switch(b) { | |
a35f3ec7 | 4453 | case 0x0f: /* 3DNow! data insns */ |
e771edab AJ |
4454 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) |
4455 | goto illegal_op; | |
0af10c86 | 4456 | val = cpu_ldub_code(env, s->pc++); |
d3eb5eae BS |
4457 | sse_fn_epp = sse_op_table5[val]; |
4458 | if (!sse_fn_epp) { | |
a35f3ec7 | 4459 | goto illegal_op; |
c4baa050 | 4460 | } |
5af45186 FB |
4461 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4462 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4463 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
a35f3ec7 | 4464 | break; |
664e0f19 FB |
4465 | case 0x70: /* pshufx insn */ |
4466 | case 0xc6: /* pshufx insn */ | |
0af10c86 | 4467 | val = cpu_ldub_code(env, s->pc++); |
5af45186 FB |
4468 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4469 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4470 | /* XXX: introduce a new table? */ |
d3eb5eae | 4471 | sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp; |
c4baa050 | 4472 | sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
664e0f19 FB |
4473 | break; |
4474 | case 0xc2: | |
4475 | /* compare insns */ | |
0af10c86 | 4476 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
4477 | if (val >= 8) |
4478 | goto illegal_op; | |
d3eb5eae | 4479 | sse_fn_epp = sse_op_table4[val][b1]; |
c4baa050 | 4480 | |
5af45186 FB |
4481 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4482 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4483 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 | 4484 | break; |
b8b6a50b FB |
4485 | case 0xf7: |
4486 | /* maskmov : we must prepare A0 */ | |
4487 | if (mod != 3) | |
4488 | goto illegal_op; | |
4489 | #ifdef TARGET_X86_64 | |
4490 | if (s->aflag == 2) { | |
4491 | gen_op_movq_A0_reg(R_EDI); | |
4492 | } else | |
4493 | #endif | |
4494 | { | |
4495 | gen_op_movl_A0_reg(R_EDI); | |
4496 | if (s->aflag == 0) | |
4497 | gen_op_andl_A0_ffff(); | |
4498 | } | |
4499 | gen_add_A0_ds_seg(s); | |
4500 | ||
4501 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); | |
4502 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4503 | /* XXX: introduce a new table? */ |
d3eb5eae BS |
4504 | sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp; |
4505 | sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0); | |
b8b6a50b | 4506 | break; |
664e0f19 | 4507 | default: |
5af45186 FB |
4508 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4509 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4510 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
4511 | break; |
4512 | } | |
4513 | if (b == 0x2e || b == 0x2f) { | |
3ca51d07 | 4514 | set_cc_op(s, CC_OP_EFLAGS); |
664e0f19 FB |
4515 | } |
4516 | } | |
4517 | } | |
4518 | ||
2c0262af FB |
4519 | /* convert one instruction. s->is_jmp is set if the translation must |
4520 | be stopped. Return the next pc value */ | |
0af10c86 BS |
4521 | static target_ulong disas_insn(CPUX86State *env, DisasContext *s, |
4522 | target_ulong pc_start) | |
2c0262af FB |
4523 | { |
4524 | int b, prefixes, aflag, dflag; | |
4525 | int shift, ot; | |
4eeb3939 | 4526 | int modrm, reg, rm, mod, op, opreg, val; |
14ce26e7 FB |
4527 | target_ulong next_eip, tval; |
4528 | int rex_w, rex_r; | |
2c0262af | 4529 | |
fdefe51c | 4530 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
70cff25e | 4531 | tcg_gen_debug_insn_start(pc_start); |
fdefe51c | 4532 | } |
2c0262af FB |
4533 | s->pc = pc_start; |
4534 | prefixes = 0; | |
2c0262af | 4535 | s->override = -1; |
14ce26e7 FB |
4536 | rex_w = -1; |
4537 | rex_r = 0; | |
4538 | #ifdef TARGET_X86_64 | |
4539 | s->rex_x = 0; | |
4540 | s->rex_b = 0; | |
5fafdf24 | 4541 | x86_64_hregs = 0; |
14ce26e7 FB |
4542 | #endif |
4543 | s->rip_offset = 0; /* for relative ip address */ | |
701ed211 RH |
4544 | s->vex_l = 0; |
4545 | s->vex_v = 0; | |
2c0262af | 4546 | next_byte: |
0af10c86 | 4547 | b = cpu_ldub_code(env, s->pc); |
2c0262af | 4548 | s->pc++; |
4a6fd938 RH |
4549 | /* Collect prefixes. */ |
4550 | switch (b) { | |
4551 | case 0xf3: | |
4552 | prefixes |= PREFIX_REPZ; | |
4553 | goto next_byte; | |
4554 | case 0xf2: | |
4555 | prefixes |= PREFIX_REPNZ; | |
4556 | goto next_byte; | |
4557 | case 0xf0: | |
4558 | prefixes |= PREFIX_LOCK; | |
4559 | goto next_byte; | |
4560 | case 0x2e: | |
4561 | s->override = R_CS; | |
4562 | goto next_byte; | |
4563 | case 0x36: | |
4564 | s->override = R_SS; | |
4565 | goto next_byte; | |
4566 | case 0x3e: | |
4567 | s->override = R_DS; | |
4568 | goto next_byte; | |
4569 | case 0x26: | |
4570 | s->override = R_ES; | |
4571 | goto next_byte; | |
4572 | case 0x64: | |
4573 | s->override = R_FS; | |
4574 | goto next_byte; | |
4575 | case 0x65: | |
4576 | s->override = R_GS; | |
4577 | goto next_byte; | |
4578 | case 0x66: | |
4579 | prefixes |= PREFIX_DATA; | |
4580 | goto next_byte; | |
4581 | case 0x67: | |
4582 | prefixes |= PREFIX_ADR; | |
4583 | goto next_byte; | |
14ce26e7 | 4584 | #ifdef TARGET_X86_64 |
4a6fd938 RH |
4585 | case 0x40 ... 0x4f: |
4586 | if (CODE64(s)) { | |
14ce26e7 FB |
4587 | /* REX prefix */ |
4588 | rex_w = (b >> 3) & 1; | |
4589 | rex_r = (b & 0x4) << 1; | |
4590 | s->rex_x = (b & 0x2) << 2; | |
4591 | REX_B(s) = (b & 0x1) << 3; | |
4592 | x86_64_hregs = 1; /* select uniform byte register addressing */ | |
4593 | goto next_byte; | |
4594 | } | |
4a6fd938 RH |
4595 | break; |
4596 | #endif | |
701ed211 RH |
4597 | case 0xc5: /* 2-byte VEX */ |
4598 | case 0xc4: /* 3-byte VEX */ | |
4599 | /* VEX prefixes cannot be used except in 32-bit mode. | |
4600 | Otherwise the instruction is LES or LDS. */ | |
4601 | if (s->code32 && !s->vm86) { | |
4602 | static const int pp_prefix[4] = { | |
4603 | 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ | |
4604 | }; | |
4605 | int vex3, vex2 = cpu_ldub_code(env, s->pc); | |
4606 | ||
4607 | if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) { | |
4608 | /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b, | |
4609 | otherwise the instruction is LES or LDS. */ | |
4610 | break; | |
4611 | } | |
4612 | s->pc++; | |
4613 | ||
085d8134 | 4614 | /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */ |
701ed211 RH |
4615 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ |
4616 | | PREFIX_LOCK | PREFIX_DATA)) { | |
4617 | goto illegal_op; | |
4618 | } | |
4619 | #ifdef TARGET_X86_64 | |
4620 | if (x86_64_hregs) { | |
4621 | goto illegal_op; | |
4622 | } | |
4623 | #endif | |
4624 | rex_r = (~vex2 >> 4) & 8; | |
4625 | if (b == 0xc5) { | |
4626 | vex3 = vex2; | |
4627 | b = cpu_ldub_code(env, s->pc++); | |
4628 | } else { | |
4629 | #ifdef TARGET_X86_64 | |
4630 | s->rex_x = (~vex2 >> 3) & 8; | |
4631 | s->rex_b = (~vex2 >> 2) & 8; | |
4632 | #endif | |
4633 | vex3 = cpu_ldub_code(env, s->pc++); | |
4634 | rex_w = (vex3 >> 7) & 1; | |
4635 | switch (vex2 & 0x1f) { | |
4636 | case 0x01: /* Implied 0f leading opcode bytes. */ | |
4637 | b = cpu_ldub_code(env, s->pc++) | 0x100; | |
4638 | break; | |
4639 | case 0x02: /* Implied 0f 38 leading opcode bytes. */ | |
4640 | b = 0x138; | |
4641 | break; | |
4642 | case 0x03: /* Implied 0f 3a leading opcode bytes. */ | |
4643 | b = 0x13a; | |
4644 | break; | |
4645 | default: /* Reserved for future use. */ | |
4646 | goto illegal_op; | |
4647 | } | |
4648 | } | |
4649 | s->vex_v = (~vex3 >> 3) & 0xf; | |
4650 | s->vex_l = (vex3 >> 2) & 1; | |
4651 | prefixes |= pp_prefix[vex3 & 3] | PREFIX_VEX; | |
4652 | } | |
4653 | break; | |
4a6fd938 RH |
4654 | } |
4655 | ||
4656 | /* Post-process prefixes. */ | |
4a6fd938 | 4657 | if (CODE64(s)) { |
dec3fc96 RH |
4658 | /* In 64-bit mode, the default data size is 32-bit. Select 64-bit |
4659 | data with rex_w, and 16-bit data with 0x66; rex_w takes precedence | |
4660 | over 0x66 if both are present. */ | |
4661 | dflag = (rex_w > 0 ? 2 : prefixes & PREFIX_DATA ? 0 : 1); | |
4662 | /* In 64-bit mode, 0x67 selects 32-bit addressing. */ | |
4663 | aflag = (prefixes & PREFIX_ADR ? 1 : 2); | |
4664 | } else { | |
4665 | /* In 16/32-bit mode, 0x66 selects the opposite data size. */ | |
4666 | dflag = s->code32; | |
4667 | if (prefixes & PREFIX_DATA) { | |
4668 | dflag ^= 1; | |
14ce26e7 | 4669 | } |
dec3fc96 RH |
4670 | /* In 16/32-bit mode, 0x67 selects the opposite addressing. */ |
4671 | aflag = s->code32; | |
4672 | if (prefixes & PREFIX_ADR) { | |
4673 | aflag ^= 1; | |
14ce26e7 | 4674 | } |
2c0262af FB |
4675 | } |
4676 | ||
2c0262af FB |
4677 | s->prefix = prefixes; |
4678 | s->aflag = aflag; | |
4679 | s->dflag = dflag; | |
4680 | ||
4681 | /* lock generation */ | |
4682 | if (prefixes & PREFIX_LOCK) | |
a7812ae4 | 4683 | gen_helper_lock(); |
2c0262af FB |
4684 | |
4685 | /* now check op code */ | |
4686 | reswitch: | |
4687 | switch(b) { | |
4688 | case 0x0f: | |
4689 | /**************************/ | |
4690 | /* extended op code */ | |
0af10c86 | 4691 | b = cpu_ldub_code(env, s->pc++) | 0x100; |
2c0262af | 4692 | goto reswitch; |
3b46e624 | 4693 | |
2c0262af FB |
4694 | /**************************/ |
4695 | /* arith & logic */ | |
4696 | case 0x00 ... 0x05: | |
4697 | case 0x08 ... 0x0d: | |
4698 | case 0x10 ... 0x15: | |
4699 | case 0x18 ... 0x1d: | |
4700 | case 0x20 ... 0x25: | |
4701 | case 0x28 ... 0x2d: | |
4702 | case 0x30 ... 0x35: | |
4703 | case 0x38 ... 0x3d: | |
4704 | { | |
4705 | int op, f, val; | |
4706 | op = (b >> 3) & 7; | |
4707 | f = (b >> 1) & 3; | |
4708 | ||
4709 | if ((b & 1) == 0) | |
4ba9938c | 4710 | ot = MO_8; |
2c0262af | 4711 | else |
4ba9938c | 4712 | ot = dflag + MO_16; |
3b46e624 | 4713 | |
2c0262af FB |
4714 | switch(f) { |
4715 | case 0: /* OP Ev, Gv */ | |
0af10c86 | 4716 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4717 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 4718 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4719 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4720 | if (mod != 3) { |
4eeb3939 | 4721 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
4722 | opreg = OR_TMP0; |
4723 | } else if (op == OP_XORL && rm == reg) { | |
4724 | xor_zero: | |
4725 | /* xor reg, reg optimisation */ | |
436ff2d2 | 4726 | set_cc_op(s, CC_OP_CLR); |
2c0262af | 4727 | gen_op_movl_T0_0(); |
57fec1fe | 4728 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
4729 | break; |
4730 | } else { | |
4731 | opreg = rm; | |
4732 | } | |
57fec1fe | 4733 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4734 | gen_op(s, op, ot, opreg); |
4735 | break; | |
4736 | case 1: /* OP Gv, Ev */ | |
0af10c86 | 4737 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4738 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
4739 | reg = ((modrm >> 3) & 7) | rex_r; |
4740 | rm = (modrm & 7) | REX_B(s); | |
2c0262af | 4741 | if (mod != 3) { |
4eeb3939 | 4742 | gen_lea_modrm(env, s, modrm); |
0f712e10 | 4743 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
2c0262af FB |
4744 | } else if (op == OP_XORL && rm == reg) { |
4745 | goto xor_zero; | |
4746 | } else { | |
57fec1fe | 4747 | gen_op_mov_TN_reg(ot, 1, rm); |
2c0262af FB |
4748 | } |
4749 | gen_op(s, op, ot, reg); | |
4750 | break; | |
4751 | case 2: /* OP A, Iv */ | |
0af10c86 | 4752 | val = insn_get(env, s, ot); |
2c0262af FB |
4753 | gen_op_movl_T1_im(val); |
4754 | gen_op(s, op, ot, OR_EAX); | |
4755 | break; | |
4756 | } | |
4757 | } | |
4758 | break; | |
4759 | ||
ec9d6075 FB |
4760 | case 0x82: |
4761 | if (CODE64(s)) | |
4762 | goto illegal_op; | |
2c0262af FB |
4763 | case 0x80: /* GRP1 */ |
4764 | case 0x81: | |
4765 | case 0x83: | |
4766 | { | |
4767 | int val; | |
4768 | ||
4769 | if ((b & 1) == 0) | |
4ba9938c | 4770 | ot = MO_8; |
2c0262af | 4771 | else |
4ba9938c | 4772 | ot = dflag + MO_16; |
3b46e624 | 4773 | |
0af10c86 | 4774 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4775 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4776 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4777 | op = (modrm >> 3) & 7; |
3b46e624 | 4778 | |
2c0262af | 4779 | if (mod != 3) { |
14ce26e7 FB |
4780 | if (b == 0x83) |
4781 | s->rip_offset = 1; | |
4782 | else | |
4783 | s->rip_offset = insn_const_size(ot); | |
4eeb3939 | 4784 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
4785 | opreg = OR_TMP0; |
4786 | } else { | |
14ce26e7 | 4787 | opreg = rm; |
2c0262af FB |
4788 | } |
4789 | ||
4790 | switch(b) { | |
4791 | default: | |
4792 | case 0x80: | |
4793 | case 0x81: | |
d64477af | 4794 | case 0x82: |
0af10c86 | 4795 | val = insn_get(env, s, ot); |
2c0262af FB |
4796 | break; |
4797 | case 0x83: | |
4ba9938c | 4798 | val = (int8_t)insn_get(env, s, MO_8); |
2c0262af FB |
4799 | break; |
4800 | } | |
4801 | gen_op_movl_T1_im(val); | |
4802 | gen_op(s, op, ot, opreg); | |
4803 | } | |
4804 | break; | |
4805 | ||
4806 | /**************************/ | |
4807 | /* inc, dec, and other misc arith */ | |
4808 | case 0x40 ... 0x47: /* inc Gv */ | |
4ba9938c | 4809 | ot = dflag ? MO_32 : MO_16; |
2c0262af FB |
4810 | gen_inc(s, ot, OR_EAX + (b & 7), 1); |
4811 | break; | |
4812 | case 0x48 ... 0x4f: /* dec Gv */ | |
4ba9938c | 4813 | ot = dflag ? MO_32 : MO_16; |
2c0262af FB |
4814 | gen_inc(s, ot, OR_EAX + (b & 7), -1); |
4815 | break; | |
4816 | case 0xf6: /* GRP3 */ | |
4817 | case 0xf7: | |
4818 | if ((b & 1) == 0) | |
4ba9938c | 4819 | ot = MO_8; |
2c0262af | 4820 | else |
4ba9938c | 4821 | ot = dflag + MO_16; |
2c0262af | 4822 | |
0af10c86 | 4823 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4824 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4825 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4826 | op = (modrm >> 3) & 7; |
4827 | if (mod != 3) { | |
14ce26e7 FB |
4828 | if (op == 0) |
4829 | s->rip_offset = insn_const_size(ot); | |
4eeb3939 | 4830 | gen_lea_modrm(env, s, modrm); |
909be183 | 4831 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 4832 | } else { |
57fec1fe | 4833 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4834 | } |
4835 | ||
4836 | switch(op) { | |
4837 | case 0: /* test */ | |
0af10c86 | 4838 | val = insn_get(env, s, ot); |
2c0262af FB |
4839 | gen_op_movl_T1_im(val); |
4840 | gen_op_testl_T0_T1_cc(); | |
3ca51d07 | 4841 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af FB |
4842 | break; |
4843 | case 2: /* not */ | |
b6abf97d | 4844 | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4845 | if (mod != 3) { |
fd8ca9f6 | 4846 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 4847 | } else { |
57fec1fe | 4848 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4849 | } |
4850 | break; | |
4851 | case 3: /* neg */ | |
b6abf97d | 4852 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4853 | if (mod != 3) { |
fd8ca9f6 | 4854 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 4855 | } else { |
57fec1fe | 4856 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4857 | } |
4858 | gen_op_update_neg_cc(); | |
3ca51d07 | 4859 | set_cc_op(s, CC_OP_SUBB + ot); |
2c0262af FB |
4860 | break; |
4861 | case 4: /* mul */ | |
4862 | switch(ot) { | |
4ba9938c RH |
4863 | case MO_8: |
4864 | gen_op_mov_TN_reg(MO_8, 1, R_EAX); | |
0211e5af FB |
4865 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
4866 | tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); | |
4867 | /* XXX: use 32 bit mul which could be faster */ | |
4868 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4ba9938c | 4869 | gen_op_mov_reg_T0(MO_16, R_EAX); |
0211e5af FB |
4870 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
4871 | tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); | |
3ca51d07 | 4872 | set_cc_op(s, CC_OP_MULB); |
2c0262af | 4873 | break; |
4ba9938c RH |
4874 | case MO_16: |
4875 | gen_op_mov_TN_reg(MO_16, 1, R_EAX); | |
0211e5af FB |
4876 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
4877 | tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); | |
4878 | /* XXX: use 32 bit mul which could be faster */ | |
4879 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4ba9938c | 4880 | gen_op_mov_reg_T0(MO_16, R_EAX); |
0211e5af FB |
4881 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
4882 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4ba9938c | 4883 | gen_op_mov_reg_T0(MO_16, R_EDX); |
0211e5af | 4884 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
3ca51d07 | 4885 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4886 | break; |
4887 | default: | |
4ba9938c | 4888 | case MO_32: |
a4bcea3d RH |
4889 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
4890 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]); | |
4891 | tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32, | |
4892 | cpu_tmp2_i32, cpu_tmp3_i32); | |
4893 | tcg_gen_extu_i32_tl(cpu_regs[R_EAX], cpu_tmp2_i32); | |
4894 | tcg_gen_extu_i32_tl(cpu_regs[R_EDX], cpu_tmp3_i32); | |
4895 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]); | |
4896 | tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]); | |
3ca51d07 | 4897 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4898 | break; |
14ce26e7 | 4899 | #ifdef TARGET_X86_64 |
4ba9938c | 4900 | case MO_64: |
a4bcea3d RH |
4901 | tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX], |
4902 | cpu_T[0], cpu_regs[R_EAX]); | |
4903 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]); | |
4904 | tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]); | |
3ca51d07 | 4905 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4906 | break; |
4907 | #endif | |
2c0262af | 4908 | } |
2c0262af FB |
4909 | break; |
4910 | case 5: /* imul */ | |
4911 | switch(ot) { | |
4ba9938c RH |
4912 | case MO_8: |
4913 | gen_op_mov_TN_reg(MO_8, 1, R_EAX); | |
0211e5af FB |
4914 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
4915 | tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); | |
4916 | /* XXX: use 32 bit mul which could be faster */ | |
4917 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4ba9938c | 4918 | gen_op_mov_reg_T0(MO_16, R_EAX); |
0211e5af FB |
4919 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
4920 | tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]); | |
4921 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
3ca51d07 | 4922 | set_cc_op(s, CC_OP_MULB); |
2c0262af | 4923 | break; |
4ba9938c RH |
4924 | case MO_16: |
4925 | gen_op_mov_TN_reg(MO_16, 1, R_EAX); | |
0211e5af FB |
4926 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4927 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4928 | /* XXX: use 32 bit mul which could be faster */ | |
4929 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4ba9938c | 4930 | gen_op_mov_reg_T0(MO_16, R_EAX); |
0211e5af FB |
4931 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
4932 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4933 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4934 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4ba9938c | 4935 | gen_op_mov_reg_T0(MO_16, R_EDX); |
3ca51d07 | 4936 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4937 | break; |
4938 | default: | |
4ba9938c | 4939 | case MO_32: |
a4bcea3d RH |
4940 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
4941 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]); | |
4942 | tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32, | |
4943 | cpu_tmp2_i32, cpu_tmp3_i32); | |
4944 | tcg_gen_extu_i32_tl(cpu_regs[R_EAX], cpu_tmp2_i32); | |
4945 | tcg_gen_extu_i32_tl(cpu_regs[R_EDX], cpu_tmp3_i32); | |
4946 | tcg_gen_sari_i32(cpu_tmp2_i32, cpu_tmp2_i32, 31); | |
4947 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]); | |
4948 | tcg_gen_sub_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); | |
4949 | tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32); | |
3ca51d07 | 4950 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4951 | break; |
14ce26e7 | 4952 | #ifdef TARGET_X86_64 |
4ba9938c | 4953 | case MO_64: |
a4bcea3d RH |
4954 | tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX], |
4955 | cpu_T[0], cpu_regs[R_EAX]); | |
4956 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]); | |
4957 | tcg_gen_sari_tl(cpu_cc_src, cpu_regs[R_EAX], 63); | |
4958 | tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_regs[R_EDX]); | |
3ca51d07 | 4959 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4960 | break; |
4961 | #endif | |
2c0262af | 4962 | } |
2c0262af FB |
4963 | break; |
4964 | case 6: /* div */ | |
4965 | switch(ot) { | |
4ba9938c | 4966 | case MO_8: |
14ce26e7 | 4967 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4968 | gen_helper_divb_AL(cpu_env, cpu_T[0]); |
2c0262af | 4969 | break; |
4ba9938c | 4970 | case MO_16: |
14ce26e7 | 4971 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4972 | gen_helper_divw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4973 | break; |
4974 | default: | |
4ba9938c | 4975 | case MO_32: |
14ce26e7 | 4976 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4977 | gen_helper_divl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4978 | break; |
4979 | #ifdef TARGET_X86_64 | |
4ba9938c | 4980 | case MO_64: |
14ce26e7 | 4981 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4982 | gen_helper_divq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4983 | break; |
14ce26e7 | 4984 | #endif |
2c0262af FB |
4985 | } |
4986 | break; | |
4987 | case 7: /* idiv */ | |
4988 | switch(ot) { | |
4ba9938c | 4989 | case MO_8: |
14ce26e7 | 4990 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4991 | gen_helper_idivb_AL(cpu_env, cpu_T[0]); |
2c0262af | 4992 | break; |
4ba9938c | 4993 | case MO_16: |
14ce26e7 | 4994 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4995 | gen_helper_idivw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4996 | break; |
4997 | default: | |
4ba9938c | 4998 | case MO_32: |
14ce26e7 | 4999 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 5000 | gen_helper_idivl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
5001 | break; |
5002 | #ifdef TARGET_X86_64 | |
4ba9938c | 5003 | case MO_64: |
14ce26e7 | 5004 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 5005 | gen_helper_idivq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 5006 | break; |
14ce26e7 | 5007 | #endif |
2c0262af FB |
5008 | } |
5009 | break; | |
5010 | default: | |
5011 | goto illegal_op; | |
5012 | } | |
5013 | break; | |
5014 | ||
5015 | case 0xfe: /* GRP4 */ | |
5016 | case 0xff: /* GRP5 */ | |
5017 | if ((b & 1) == 0) | |
4ba9938c | 5018 | ot = MO_8; |
2c0262af | 5019 | else |
4ba9938c | 5020 | ot = dflag + MO_16; |
2c0262af | 5021 | |
0af10c86 | 5022 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5023 | mod = (modrm >> 6) & 3; |
14ce26e7 | 5024 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
5025 | op = (modrm >> 3) & 7; |
5026 | if (op >= 2 && b == 0xfe) { | |
5027 | goto illegal_op; | |
5028 | } | |
14ce26e7 | 5029 | if (CODE64(s)) { |
aba9d61e | 5030 | if (op == 2 || op == 4) { |
14ce26e7 | 5031 | /* operand size for jumps is 64 bit */ |
4ba9938c | 5032 | ot = MO_64; |
aba9d61e | 5033 | } else if (op == 3 || op == 5) { |
4ba9938c | 5034 | ot = dflag ? MO_32 + (rex_w == 1) : MO_16; |
14ce26e7 FB |
5035 | } else if (op == 6) { |
5036 | /* default push size is 64 bit */ | |
4ba9938c | 5037 | ot = dflag ? MO_64 : MO_16; |
14ce26e7 FB |
5038 | } |
5039 | } | |
2c0262af | 5040 | if (mod != 3) { |
4eeb3939 | 5041 | gen_lea_modrm(env, s, modrm); |
2c0262af | 5042 | if (op >= 2 && op != 3 && op != 5) |
909be183 | 5043 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 5044 | } else { |
57fec1fe | 5045 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
5046 | } |
5047 | ||
5048 | switch(op) { | |
5049 | case 0: /* inc Ev */ | |
5050 | if (mod != 3) | |
5051 | opreg = OR_TMP0; | |
5052 | else | |
5053 | opreg = rm; | |
5054 | gen_inc(s, ot, opreg, 1); | |
5055 | break; | |
5056 | case 1: /* dec Ev */ | |
5057 | if (mod != 3) | |
5058 | opreg = OR_TMP0; | |
5059 | else | |
5060 | opreg = rm; | |
5061 | gen_inc(s, ot, opreg, -1); | |
5062 | break; | |
5063 | case 2: /* call Ev */ | |
4f31916f | 5064 | /* XXX: optimize if memory (no 'and' is necessary) */ |
2c0262af FB |
5065 | if (s->dflag == 0) |
5066 | gen_op_andl_T0_ffff(); | |
2c0262af | 5067 | next_eip = s->pc - s->cs_base; |
1ef38687 | 5068 | gen_movtl_T1_im(next_eip); |
4f31916f FB |
5069 | gen_push_T1(s); |
5070 | gen_op_jmp_T0(); | |
2c0262af FB |
5071 | gen_eob(s); |
5072 | break; | |
61382a50 | 5073 | case 3: /* lcall Ev */ |
0f712e10 | 5074 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
4ba9938c | 5075 | gen_add_A0_im(s, 1 << (ot - MO_16 + 1)); |
cc1a80df | 5076 | gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); |
2c0262af FB |
5077 | do_lcall: |
5078 | if (s->pe && !s->vm86) { | |
773cdfcc | 5079 | gen_update_cc_op(s); |
14ce26e7 | 5080 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 5081 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
5082 | gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
5083 | tcg_const_i32(dflag), | |
a7812ae4 | 5084 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 5085 | } else { |
b6abf97d | 5086 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
5087 | gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1], |
5088 | tcg_const_i32(dflag), | |
a7812ae4 | 5089 | tcg_const_i32(s->pc - s->cs_base)); |
2c0262af FB |
5090 | } |
5091 | gen_eob(s); | |
5092 | break; | |
5093 | case 4: /* jmp Ev */ | |
5094 | if (s->dflag == 0) | |
5095 | gen_op_andl_T0_ffff(); | |
5096 | gen_op_jmp_T0(); | |
5097 | gen_eob(s); | |
5098 | break; | |
5099 | case 5: /* ljmp Ev */ | |
0f712e10 | 5100 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
4ba9938c | 5101 | gen_add_A0_im(s, 1 << (ot - MO_16 + 1)); |
cc1a80df | 5102 | gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); |
2c0262af FB |
5103 | do_ljmp: |
5104 | if (s->pe && !s->vm86) { | |
773cdfcc | 5105 | gen_update_cc_op(s); |
14ce26e7 | 5106 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 5107 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 5108 | gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
a7812ae4 | 5109 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 5110 | } else { |
3bd7da9e | 5111 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
5112 | gen_op_movl_T0_T1(); |
5113 | gen_op_jmp_T0(); | |
5114 | } | |
5115 | gen_eob(s); | |
5116 | break; | |
5117 | case 6: /* push Ev */ | |
5118 | gen_push_T0(s); | |
5119 | break; | |
5120 | default: | |
5121 | goto illegal_op; | |
5122 | } | |
5123 | break; | |
5124 | ||
5125 | case 0x84: /* test Ev, Gv */ | |
5fafdf24 | 5126 | case 0x85: |
2c0262af | 5127 | if ((b & 1) == 0) |
4ba9938c | 5128 | ot = MO_8; |
2c0262af | 5129 | else |
4ba9938c | 5130 | ot = dflag + MO_16; |
2c0262af | 5131 | |
0af10c86 | 5132 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5133 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5134 | |
0af10c86 | 5135 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5136 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af | 5137 | gen_op_testl_T0_T1_cc(); |
3ca51d07 | 5138 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 5139 | break; |
3b46e624 | 5140 | |
2c0262af FB |
5141 | case 0xa8: /* test eAX, Iv */ |
5142 | case 0xa9: | |
5143 | if ((b & 1) == 0) | |
4ba9938c | 5144 | ot = MO_8; |
2c0262af | 5145 | else |
4ba9938c | 5146 | ot = dflag + MO_16; |
0af10c86 | 5147 | val = insn_get(env, s, ot); |
2c0262af | 5148 | |
57fec1fe | 5149 | gen_op_mov_TN_reg(ot, 0, OR_EAX); |
2c0262af FB |
5150 | gen_op_movl_T1_im(val); |
5151 | gen_op_testl_T0_T1_cc(); | |
3ca51d07 | 5152 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 5153 | break; |
3b46e624 | 5154 | |
2c0262af | 5155 | case 0x98: /* CWDE/CBW */ |
14ce26e7 FB |
5156 | #ifdef TARGET_X86_64 |
5157 | if (dflag == 2) { | |
4ba9938c | 5158 | gen_op_mov_TN_reg(MO_32, 0, R_EAX); |
e108dd01 | 5159 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 5160 | gen_op_mov_reg_T0(MO_64, R_EAX); |
14ce26e7 FB |
5161 | } else |
5162 | #endif | |
e108dd01 | 5163 | if (dflag == 1) { |
4ba9938c | 5164 | gen_op_mov_TN_reg(MO_16, 0, R_EAX); |
e108dd01 | 5165 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 5166 | gen_op_mov_reg_T0(MO_32, R_EAX); |
e108dd01 | 5167 | } else { |
4ba9938c | 5168 | gen_op_mov_TN_reg(MO_8, 0, R_EAX); |
e108dd01 | 5169 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 5170 | gen_op_mov_reg_T0(MO_16, R_EAX); |
e108dd01 | 5171 | } |
2c0262af FB |
5172 | break; |
5173 | case 0x99: /* CDQ/CWD */ | |
14ce26e7 FB |
5174 | #ifdef TARGET_X86_64 |
5175 | if (dflag == 2) { | |
4ba9938c | 5176 | gen_op_mov_TN_reg(MO_64, 0, R_EAX); |
e108dd01 | 5177 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); |
4ba9938c | 5178 | gen_op_mov_reg_T0(MO_64, R_EDX); |
14ce26e7 FB |
5179 | } else |
5180 | #endif | |
e108dd01 | 5181 | if (dflag == 1) { |
4ba9938c | 5182 | gen_op_mov_TN_reg(MO_32, 0, R_EAX); |
e108dd01 FB |
5183 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
5184 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); | |
4ba9938c | 5185 | gen_op_mov_reg_T0(MO_32, R_EDX); |
e108dd01 | 5186 | } else { |
4ba9938c | 5187 | gen_op_mov_TN_reg(MO_16, 0, R_EAX); |
e108dd01 FB |
5188 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
5189 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); | |
4ba9938c | 5190 | gen_op_mov_reg_T0(MO_16, R_EDX); |
e108dd01 | 5191 | } |
2c0262af FB |
5192 | break; |
5193 | case 0x1af: /* imul Gv, Ev */ | |
5194 | case 0x69: /* imul Gv, Ev, I */ | |
5195 | case 0x6b: | |
4ba9938c | 5196 | ot = dflag + MO_16; |
0af10c86 | 5197 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
5198 | reg = ((modrm >> 3) & 7) | rex_r; |
5199 | if (b == 0x69) | |
5200 | s->rip_offset = insn_const_size(ot); | |
5201 | else if (b == 0x6b) | |
5202 | s->rip_offset = 1; | |
0af10c86 | 5203 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
2c0262af | 5204 | if (b == 0x69) { |
0af10c86 | 5205 | val = insn_get(env, s, ot); |
2c0262af FB |
5206 | gen_op_movl_T1_im(val); |
5207 | } else if (b == 0x6b) { | |
4ba9938c | 5208 | val = (int8_t)insn_get(env, s, MO_8); |
2c0262af FB |
5209 | gen_op_movl_T1_im(val); |
5210 | } else { | |
57fec1fe | 5211 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af | 5212 | } |
a4bcea3d | 5213 | switch (ot) { |
0211e5af | 5214 | #ifdef TARGET_X86_64 |
4ba9938c | 5215 | case MO_64: |
a4bcea3d RH |
5216 | tcg_gen_muls2_i64(cpu_regs[reg], cpu_T[1], cpu_T[0], cpu_T[1]); |
5217 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]); | |
5218 | tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63); | |
5219 | tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_T[1]); | |
5220 | break; | |
0211e5af | 5221 | #endif |
4ba9938c | 5222 | case MO_32: |
a4bcea3d RH |
5223 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
5224 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); | |
5225 | tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32, | |
5226 | cpu_tmp2_i32, cpu_tmp3_i32); | |
5227 | tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32); | |
5228 | tcg_gen_sari_i32(cpu_tmp2_i32, cpu_tmp2_i32, 31); | |
5229 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]); | |
5230 | tcg_gen_sub_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); | |
5231 | tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32); | |
5232 | break; | |
5233 | default: | |
0211e5af FB |
5234 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
5235 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
5236 | /* XXX: use 32 bit mul which could be faster */ | |
5237 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
5238 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
5239 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
5240 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
a4bcea3d RH |
5241 | gen_op_mov_reg_T0(ot, reg); |
5242 | break; | |
2c0262af | 5243 | } |
3ca51d07 | 5244 | set_cc_op(s, CC_OP_MULB + ot); |
2c0262af FB |
5245 | break; |
5246 | case 0x1c0: | |
5247 | case 0x1c1: /* xadd Ev, Gv */ | |
5248 | if ((b & 1) == 0) | |
4ba9938c | 5249 | ot = MO_8; |
2c0262af | 5250 | else |
4ba9938c | 5251 | ot = dflag + MO_16; |
0af10c86 | 5252 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5253 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5254 | mod = (modrm >> 6) & 3; |
5255 | if (mod == 3) { | |
14ce26e7 | 5256 | rm = (modrm & 7) | REX_B(s); |
57fec1fe FB |
5257 | gen_op_mov_TN_reg(ot, 0, reg); |
5258 | gen_op_mov_TN_reg(ot, 1, rm); | |
2c0262af | 5259 | gen_op_addl_T0_T1(); |
57fec1fe FB |
5260 | gen_op_mov_reg_T1(ot, reg); |
5261 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 5262 | } else { |
4eeb3939 | 5263 | gen_lea_modrm(env, s, modrm); |
57fec1fe | 5264 | gen_op_mov_TN_reg(ot, 0, reg); |
0f712e10 | 5265 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
2c0262af | 5266 | gen_op_addl_T0_T1(); |
fd8ca9f6 | 5267 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
57fec1fe | 5268 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5269 | } |
5270 | gen_op_update2_cc(); | |
3ca51d07 | 5271 | set_cc_op(s, CC_OP_ADDB + ot); |
2c0262af FB |
5272 | break; |
5273 | case 0x1b0: | |
5274 | case 0x1b1: /* cmpxchg Ev, Gv */ | |
cad3a37d | 5275 | { |
1130328e | 5276 | int label1, label2; |
1e4840bf | 5277 | TCGv t0, t1, t2, a0; |
cad3a37d FB |
5278 | |
5279 | if ((b & 1) == 0) | |
4ba9938c | 5280 | ot = MO_8; |
cad3a37d | 5281 | else |
4ba9938c | 5282 | ot = dflag + MO_16; |
0af10c86 | 5283 | modrm = cpu_ldub_code(env, s->pc++); |
cad3a37d FB |
5284 | reg = ((modrm >> 3) & 7) | rex_r; |
5285 | mod = (modrm >> 6) & 3; | |
a7812ae4 PB |
5286 | t0 = tcg_temp_local_new(); |
5287 | t1 = tcg_temp_local_new(); | |
5288 | t2 = tcg_temp_local_new(); | |
5289 | a0 = tcg_temp_local_new(); | |
1e4840bf | 5290 | gen_op_mov_v_reg(ot, t1, reg); |
cad3a37d FB |
5291 | if (mod == 3) { |
5292 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 5293 | gen_op_mov_v_reg(ot, t0, rm); |
cad3a37d | 5294 | } else { |
4eeb3939 | 5295 | gen_lea_modrm(env, s, modrm); |
1e4840bf | 5296 | tcg_gen_mov_tl(a0, cpu_A0); |
323d1876 | 5297 | gen_op_ld_v(s, ot, t0, a0); |
cad3a37d FB |
5298 | rm = 0; /* avoid warning */ |
5299 | } | |
5300 | label1 = gen_new_label(); | |
a3251186 RH |
5301 | tcg_gen_mov_tl(t2, cpu_regs[R_EAX]); |
5302 | gen_extu(ot, t0); | |
1e4840bf | 5303 | gen_extu(ot, t2); |
a3251186 | 5304 | tcg_gen_brcond_tl(TCG_COND_EQ, t2, t0, label1); |
f7e80adf | 5305 | label2 = gen_new_label(); |
cad3a37d | 5306 | if (mod == 3) { |
1e4840bf | 5307 | gen_op_mov_reg_v(ot, R_EAX, t0); |
1130328e FB |
5308 | tcg_gen_br(label2); |
5309 | gen_set_label(label1); | |
1e4840bf | 5310 | gen_op_mov_reg_v(ot, rm, t1); |
cad3a37d | 5311 | } else { |
f7e80adf AG |
5312 | /* perform no-op store cycle like physical cpu; must be |
5313 | before changing accumulator to ensure idempotency if | |
5314 | the store faults and the instruction is restarted */ | |
323d1876 | 5315 | gen_op_st_v(s, ot, t0, a0); |
1e4840bf | 5316 | gen_op_mov_reg_v(ot, R_EAX, t0); |
f7e80adf | 5317 | tcg_gen_br(label2); |
1130328e | 5318 | gen_set_label(label1); |
323d1876 | 5319 | gen_op_st_v(s, ot, t1, a0); |
cad3a37d | 5320 | } |
f7e80adf | 5321 | gen_set_label(label2); |
1e4840bf | 5322 | tcg_gen_mov_tl(cpu_cc_src, t0); |
a3251186 RH |
5323 | tcg_gen_mov_tl(cpu_cc_srcT, t2); |
5324 | tcg_gen_sub_tl(cpu_cc_dst, t2, t0); | |
3ca51d07 | 5325 | set_cc_op(s, CC_OP_SUBB + ot); |
1e4840bf FB |
5326 | tcg_temp_free(t0); |
5327 | tcg_temp_free(t1); | |
5328 | tcg_temp_free(t2); | |
5329 | tcg_temp_free(a0); | |
2c0262af | 5330 | } |
2c0262af FB |
5331 | break; |
5332 | case 0x1c7: /* cmpxchg8b */ | |
0af10c86 | 5333 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5334 | mod = (modrm >> 6) & 3; |
71c3558e | 5335 | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
2c0262af | 5336 | goto illegal_op; |
1b9d9ebb FB |
5337 | #ifdef TARGET_X86_64 |
5338 | if (dflag == 2) { | |
5339 | if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) | |
5340 | goto illegal_op; | |
5341 | gen_jmp_im(pc_start - s->cs_base); | |
773cdfcc | 5342 | gen_update_cc_op(s); |
4eeb3939 | 5343 | gen_lea_modrm(env, s, modrm); |
92fc4b58 | 5344 | gen_helper_cmpxchg16b(cpu_env, cpu_A0); |
1b9d9ebb FB |
5345 | } else |
5346 | #endif | |
5347 | { | |
5348 | if (!(s->cpuid_features & CPUID_CX8)) | |
5349 | goto illegal_op; | |
5350 | gen_jmp_im(pc_start - s->cs_base); | |
773cdfcc | 5351 | gen_update_cc_op(s); |
4eeb3939 | 5352 | gen_lea_modrm(env, s, modrm); |
92fc4b58 | 5353 | gen_helper_cmpxchg8b(cpu_env, cpu_A0); |
1b9d9ebb | 5354 | } |
3ca51d07 | 5355 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 5356 | break; |
3b46e624 | 5357 | |
2c0262af FB |
5358 | /**************************/ |
5359 | /* push/pop */ | |
5360 | case 0x50 ... 0x57: /* push */ | |
4ba9938c | 5361 | gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s)); |
2c0262af FB |
5362 | gen_push_T0(s); |
5363 | break; | |
5364 | case 0x58 ... 0x5f: /* pop */ | |
14ce26e7 | 5365 | if (CODE64(s)) { |
4ba9938c | 5366 | ot = dflag ? MO_64 : MO_16; |
14ce26e7 | 5367 | } else { |
4ba9938c | 5368 | ot = dflag + MO_16; |
14ce26e7 | 5369 | } |
2c0262af | 5370 | gen_pop_T0(s); |
77729c24 | 5371 | /* NOTE: order is important for pop %sp */ |
2c0262af | 5372 | gen_pop_update(s); |
57fec1fe | 5373 | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s)); |
2c0262af FB |
5374 | break; |
5375 | case 0x60: /* pusha */ | |
14ce26e7 FB |
5376 | if (CODE64(s)) |
5377 | goto illegal_op; | |
2c0262af FB |
5378 | gen_pusha(s); |
5379 | break; | |
5380 | case 0x61: /* popa */ | |
14ce26e7 FB |
5381 | if (CODE64(s)) |
5382 | goto illegal_op; | |
2c0262af FB |
5383 | gen_popa(s); |
5384 | break; | |
5385 | case 0x68: /* push Iv */ | |
5386 | case 0x6a: | |
14ce26e7 | 5387 | if (CODE64(s)) { |
4ba9938c | 5388 | ot = dflag ? MO_64 : MO_16; |
14ce26e7 | 5389 | } else { |
4ba9938c | 5390 | ot = dflag + MO_16; |
14ce26e7 | 5391 | } |
2c0262af | 5392 | if (b == 0x68) |
0af10c86 | 5393 | val = insn_get(env, s, ot); |
2c0262af | 5394 | else |
4ba9938c | 5395 | val = (int8_t)insn_get(env, s, MO_8); |
2c0262af FB |
5396 | gen_op_movl_T0_im(val); |
5397 | gen_push_T0(s); | |
5398 | break; | |
5399 | case 0x8f: /* pop Ev */ | |
14ce26e7 | 5400 | if (CODE64(s)) { |
4ba9938c | 5401 | ot = dflag ? MO_64 : MO_16; |
14ce26e7 | 5402 | } else { |
4ba9938c | 5403 | ot = dflag + MO_16; |
14ce26e7 | 5404 | } |
0af10c86 | 5405 | modrm = cpu_ldub_code(env, s->pc++); |
77729c24 | 5406 | mod = (modrm >> 6) & 3; |
2c0262af | 5407 | gen_pop_T0(s); |
77729c24 FB |
5408 | if (mod == 3) { |
5409 | /* NOTE: order is important for pop %sp */ | |
5410 | gen_pop_update(s); | |
14ce26e7 | 5411 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 5412 | gen_op_mov_reg_T0(ot, rm); |
77729c24 FB |
5413 | } else { |
5414 | /* NOTE: order is important too for MMU exceptions */ | |
14ce26e7 | 5415 | s->popl_esp_hack = 1 << ot; |
0af10c86 | 5416 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
77729c24 FB |
5417 | s->popl_esp_hack = 0; |
5418 | gen_pop_update(s); | |
5419 | } | |
2c0262af FB |
5420 | break; |
5421 | case 0xc8: /* enter */ | |
5422 | { | |
5423 | int level; | |
0af10c86 | 5424 | val = cpu_lduw_code(env, s->pc); |
2c0262af | 5425 | s->pc += 2; |
0af10c86 | 5426 | level = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5427 | gen_enter(s, val, level); |
5428 | } | |
5429 | break; | |
5430 | case 0xc9: /* leave */ | |
5431 | /* XXX: exception not precise (ESP is updated before potential exception) */ | |
14ce26e7 | 5432 | if (CODE64(s)) { |
4ba9938c RH |
5433 | gen_op_mov_TN_reg(MO_64, 0, R_EBP); |
5434 | gen_op_mov_reg_T0(MO_64, R_ESP); | |
14ce26e7 | 5435 | } else if (s->ss32) { |
4ba9938c RH |
5436 | gen_op_mov_TN_reg(MO_32, 0, R_EBP); |
5437 | gen_op_mov_reg_T0(MO_32, R_ESP); | |
2c0262af | 5438 | } else { |
4ba9938c RH |
5439 | gen_op_mov_TN_reg(MO_16, 0, R_EBP); |
5440 | gen_op_mov_reg_T0(MO_16, R_ESP); | |
2c0262af FB |
5441 | } |
5442 | gen_pop_T0(s); | |
14ce26e7 | 5443 | if (CODE64(s)) { |
4ba9938c | 5444 | ot = dflag ? MO_64 : MO_16; |
14ce26e7 | 5445 | } else { |
4ba9938c | 5446 | ot = dflag + MO_16; |
14ce26e7 | 5447 | } |
57fec1fe | 5448 | gen_op_mov_reg_T0(ot, R_EBP); |
2c0262af FB |
5449 | gen_pop_update(s); |
5450 | break; | |
5451 | case 0x06: /* push es */ | |
5452 | case 0x0e: /* push cs */ | |
5453 | case 0x16: /* push ss */ | |
5454 | case 0x1e: /* push ds */ | |
14ce26e7 FB |
5455 | if (CODE64(s)) |
5456 | goto illegal_op; | |
2c0262af FB |
5457 | gen_op_movl_T0_seg(b >> 3); |
5458 | gen_push_T0(s); | |
5459 | break; | |
5460 | case 0x1a0: /* push fs */ | |
5461 | case 0x1a8: /* push gs */ | |
5462 | gen_op_movl_T0_seg((b >> 3) & 7); | |
5463 | gen_push_T0(s); | |
5464 | break; | |
5465 | case 0x07: /* pop es */ | |
5466 | case 0x17: /* pop ss */ | |
5467 | case 0x1f: /* pop ds */ | |
14ce26e7 FB |
5468 | if (CODE64(s)) |
5469 | goto illegal_op; | |
2c0262af FB |
5470 | reg = b >> 3; |
5471 | gen_pop_T0(s); | |
5472 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5473 | gen_pop_update(s); | |
5474 | if (reg == R_SS) { | |
a2cc3b24 FB |
5475 | /* if reg == SS, inhibit interrupts/trace. */ |
5476 | /* If several instructions disable interrupts, only the | |
5477 | _first_ does it */ | |
5478 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5479 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5480 | s->tf = 0; |
5481 | } | |
5482 | if (s->is_jmp) { | |
14ce26e7 | 5483 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5484 | gen_eob(s); |
5485 | } | |
5486 | break; | |
5487 | case 0x1a1: /* pop fs */ | |
5488 | case 0x1a9: /* pop gs */ | |
5489 | gen_pop_T0(s); | |
5490 | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); | |
5491 | gen_pop_update(s); | |
5492 | if (s->is_jmp) { | |
14ce26e7 | 5493 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5494 | gen_eob(s); |
5495 | } | |
5496 | break; | |
5497 | ||
5498 | /**************************/ | |
5499 | /* mov */ | |
5500 | case 0x88: | |
5501 | case 0x89: /* mov Gv, Ev */ | |
5502 | if ((b & 1) == 0) | |
4ba9938c | 5503 | ot = MO_8; |
2c0262af | 5504 | else |
4ba9938c | 5505 | ot = dflag + MO_16; |
0af10c86 | 5506 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5507 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5508 | |
2c0262af | 5509 | /* generate a generic store */ |
0af10c86 | 5510 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
2c0262af FB |
5511 | break; |
5512 | case 0xc6: | |
5513 | case 0xc7: /* mov Ev, Iv */ | |
5514 | if ((b & 1) == 0) | |
4ba9938c | 5515 | ot = MO_8; |
2c0262af | 5516 | else |
4ba9938c | 5517 | ot = dflag + MO_16; |
0af10c86 | 5518 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5519 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5520 | if (mod != 3) { |
5521 | s->rip_offset = insn_const_size(ot); | |
4eeb3939 | 5522 | gen_lea_modrm(env, s, modrm); |
14ce26e7 | 5523 | } |
0af10c86 | 5524 | val = insn_get(env, s, ot); |
2c0262af | 5525 | gen_op_movl_T0_im(val); |
fd8ca9f6 RH |
5526 | if (mod != 3) { |
5527 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); | |
5528 | } else { | |
57fec1fe | 5529 | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); |
fd8ca9f6 | 5530 | } |
2c0262af FB |
5531 | break; |
5532 | case 0x8a: | |
5533 | case 0x8b: /* mov Ev, Gv */ | |
5534 | if ((b & 1) == 0) | |
4ba9938c | 5535 | ot = MO_8; |
2c0262af | 5536 | else |
4ba9938c | 5537 | ot = MO_16 + dflag; |
0af10c86 | 5538 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5539 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5540 | |
0af10c86 | 5541 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5542 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
5543 | break; |
5544 | case 0x8e: /* mov seg, Gv */ | |
0af10c86 | 5545 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5546 | reg = (modrm >> 3) & 7; |
5547 | if (reg >= 6 || reg == R_CS) | |
5548 | goto illegal_op; | |
4ba9938c | 5549 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
2c0262af FB |
5550 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
5551 | if (reg == R_SS) { | |
5552 | /* if reg == SS, inhibit interrupts/trace */ | |
a2cc3b24 FB |
5553 | /* If several instructions disable interrupts, only the |
5554 | _first_ does it */ | |
5555 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5556 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5557 | s->tf = 0; |
5558 | } | |
5559 | if (s->is_jmp) { | |
14ce26e7 | 5560 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5561 | gen_eob(s); |
5562 | } | |
5563 | break; | |
5564 | case 0x8c: /* mov Gv, seg */ | |
0af10c86 | 5565 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5566 | reg = (modrm >> 3) & 7; |
5567 | mod = (modrm >> 6) & 3; | |
5568 | if (reg >= 6) | |
5569 | goto illegal_op; | |
5570 | gen_op_movl_T0_seg(reg); | |
14ce26e7 | 5571 | if (mod == 3) |
4ba9938c | 5572 | ot = MO_16 + dflag; |
14ce26e7 | 5573 | else |
4ba9938c | 5574 | ot = MO_16; |
0af10c86 | 5575 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
5576 | break; |
5577 | ||
5578 | case 0x1b6: /* movzbS Gv, Eb */ | |
5579 | case 0x1b7: /* movzwS Gv, Eb */ | |
5580 | case 0x1be: /* movsbS Gv, Eb */ | |
5581 | case 0x1bf: /* movswS Gv, Eb */ | |
5582 | { | |
c8fbc479 RH |
5583 | TCGMemOp d_ot; |
5584 | TCGMemOp s_ot; | |
5585 | ||
2c0262af | 5586 | /* d_ot is the size of destination */ |
4ba9938c | 5587 | d_ot = dflag + MO_16; |
2c0262af | 5588 | /* ot is the size of source */ |
4ba9938c | 5589 | ot = (b & 1) + MO_8; |
c8fbc479 RH |
5590 | /* s_ot is the sign+size of source */ |
5591 | s_ot = b & 8 ? MO_SIGN | ot : ot; | |
5592 | ||
0af10c86 | 5593 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5594 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 5595 | mod = (modrm >> 6) & 3; |
14ce26e7 | 5596 | rm = (modrm & 7) | REX_B(s); |
3b46e624 | 5597 | |
2c0262af | 5598 | if (mod == 3) { |
57fec1fe | 5599 | gen_op_mov_TN_reg(ot, 0, rm); |
c8fbc479 RH |
5600 | switch (s_ot) { |
5601 | case MO_UB: | |
e108dd01 | 5602 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 5603 | break; |
c8fbc479 | 5604 | case MO_SB: |
e108dd01 | 5605 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 5606 | break; |
c8fbc479 | 5607 | case MO_UW: |
e108dd01 | 5608 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5609 | break; |
5610 | default: | |
c8fbc479 | 5611 | case MO_SW: |
e108dd01 | 5612 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5613 | break; |
5614 | } | |
57fec1fe | 5615 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af | 5616 | } else { |
4eeb3939 | 5617 | gen_lea_modrm(env, s, modrm); |
c8fbc479 | 5618 | gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0); |
57fec1fe | 5619 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5620 | } |
5621 | } | |
5622 | break; | |
5623 | ||
5624 | case 0x8d: /* lea */ | |
4ba9938c | 5625 | ot = dflag + MO_16; |
0af10c86 | 5626 | modrm = cpu_ldub_code(env, s->pc++); |
3a1d9b8b FB |
5627 | mod = (modrm >> 6) & 3; |
5628 | if (mod == 3) | |
5629 | goto illegal_op; | |
14ce26e7 | 5630 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5631 | /* we must ensure that no segment is added */ |
5632 | s->override = -1; | |
5633 | val = s->addseg; | |
5634 | s->addseg = 0; | |
4eeb3939 | 5635 | gen_lea_modrm(env, s, modrm); |
2c0262af | 5636 | s->addseg = val; |
4ba9938c | 5637 | gen_op_mov_reg_A0(ot - MO_16, reg); |
2c0262af | 5638 | break; |
3b46e624 | 5639 | |
2c0262af FB |
5640 | case 0xa0: /* mov EAX, Ov */ |
5641 | case 0xa1: | |
5642 | case 0xa2: /* mov Ov, EAX */ | |
5643 | case 0xa3: | |
2c0262af | 5644 | { |
14ce26e7 FB |
5645 | target_ulong offset_addr; |
5646 | ||
5647 | if ((b & 1) == 0) | |
4ba9938c | 5648 | ot = MO_8; |
14ce26e7 | 5649 | else |
4ba9938c | 5650 | ot = dflag + MO_16; |
14ce26e7 | 5651 | #ifdef TARGET_X86_64 |
8f091a59 | 5652 | if (s->aflag == 2) { |
0af10c86 | 5653 | offset_addr = cpu_ldq_code(env, s->pc); |
14ce26e7 | 5654 | s->pc += 8; |
57fec1fe | 5655 | gen_op_movq_A0_im(offset_addr); |
5fafdf24 | 5656 | } else |
14ce26e7 FB |
5657 | #endif |
5658 | { | |
5659 | if (s->aflag) { | |
4ba9938c | 5660 | offset_addr = insn_get(env, s, MO_32); |
14ce26e7 | 5661 | } else { |
4ba9938c | 5662 | offset_addr = insn_get(env, s, MO_16); |
14ce26e7 FB |
5663 | } |
5664 | gen_op_movl_A0_im(offset_addr); | |
5665 | } | |
664e0f19 | 5666 | gen_add_A0_ds_seg(s); |
14ce26e7 | 5667 | if ((b & 2) == 0) { |
909be183 | 5668 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
57fec1fe | 5669 | gen_op_mov_reg_T0(ot, R_EAX); |
14ce26e7 | 5670 | } else { |
57fec1fe | 5671 | gen_op_mov_TN_reg(ot, 0, R_EAX); |
fd8ca9f6 | 5672 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af FB |
5673 | } |
5674 | } | |
2c0262af FB |
5675 | break; |
5676 | case 0xd7: /* xlat */ | |
14ce26e7 | 5677 | #ifdef TARGET_X86_64 |
8f091a59 | 5678 | if (s->aflag == 2) { |
57fec1fe | 5679 | gen_op_movq_A0_reg(R_EBX); |
4ba9938c | 5680 | gen_op_mov_TN_reg(MO_64, 0, R_EAX); |
bbf662ee FB |
5681 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); |
5682 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
5fafdf24 | 5683 | } else |
14ce26e7 FB |
5684 | #endif |
5685 | { | |
57fec1fe | 5686 | gen_op_movl_A0_reg(R_EBX); |
4ba9938c | 5687 | gen_op_mov_TN_reg(MO_32, 0, R_EAX); |
bbf662ee FB |
5688 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); |
5689 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
14ce26e7 FB |
5690 | if (s->aflag == 0) |
5691 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
5692 | else |
5693 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
14ce26e7 | 5694 | } |
664e0f19 | 5695 | gen_add_A0_ds_seg(s); |
cc1a80df | 5696 | gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0); |
4ba9938c | 5697 | gen_op_mov_reg_T0(MO_8, R_EAX); |
2c0262af FB |
5698 | break; |
5699 | case 0xb0 ... 0xb7: /* mov R, Ib */ | |
4ba9938c | 5700 | val = insn_get(env, s, MO_8); |
2c0262af | 5701 | gen_op_movl_T0_im(val); |
4ba9938c | 5702 | gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s)); |
2c0262af FB |
5703 | break; |
5704 | case 0xb8 ... 0xbf: /* mov R, Iv */ | |
14ce26e7 FB |
5705 | #ifdef TARGET_X86_64 |
5706 | if (dflag == 2) { | |
5707 | uint64_t tmp; | |
5708 | /* 64 bit case */ | |
0af10c86 | 5709 | tmp = cpu_ldq_code(env, s->pc); |
14ce26e7 FB |
5710 | s->pc += 8; |
5711 | reg = (b & 7) | REX_B(s); | |
5712 | gen_movtl_T0_im(tmp); | |
4ba9938c | 5713 | gen_op_mov_reg_T0(MO_64, reg); |
5fafdf24 | 5714 | } else |
14ce26e7 FB |
5715 | #endif |
5716 | { | |
4ba9938c | 5717 | ot = dflag ? MO_32 : MO_16; |
0af10c86 | 5718 | val = insn_get(env, s, ot); |
14ce26e7 FB |
5719 | reg = (b & 7) | REX_B(s); |
5720 | gen_op_movl_T0_im(val); | |
57fec1fe | 5721 | gen_op_mov_reg_T0(ot, reg); |
14ce26e7 | 5722 | } |
2c0262af FB |
5723 | break; |
5724 | ||
5725 | case 0x91 ... 0x97: /* xchg R, EAX */ | |
7418027e | 5726 | do_xchg_reg_eax: |
4ba9938c | 5727 | ot = dflag + MO_16; |
14ce26e7 | 5728 | reg = (b & 7) | REX_B(s); |
2c0262af FB |
5729 | rm = R_EAX; |
5730 | goto do_xchg_reg; | |
5731 | case 0x86: | |
5732 | case 0x87: /* xchg Ev, Gv */ | |
5733 | if ((b & 1) == 0) | |
4ba9938c | 5734 | ot = MO_8; |
2c0262af | 5735 | else |
4ba9938c | 5736 | ot = dflag + MO_16; |
0af10c86 | 5737 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5738 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5739 | mod = (modrm >> 6) & 3; |
5740 | if (mod == 3) { | |
14ce26e7 | 5741 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 5742 | do_xchg_reg: |
57fec1fe FB |
5743 | gen_op_mov_TN_reg(ot, 0, reg); |
5744 | gen_op_mov_TN_reg(ot, 1, rm); | |
5745 | gen_op_mov_reg_T0(ot, rm); | |
5746 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af | 5747 | } else { |
4eeb3939 | 5748 | gen_lea_modrm(env, s, modrm); |
57fec1fe | 5749 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af FB |
5750 | /* for xchg, lock is implicit */ |
5751 | if (!(prefixes & PREFIX_LOCK)) | |
a7812ae4 | 5752 | gen_helper_lock(); |
0f712e10 | 5753 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
fd8ca9f6 | 5754 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 5755 | if (!(prefixes & PREFIX_LOCK)) |
a7812ae4 | 5756 | gen_helper_unlock(); |
57fec1fe | 5757 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5758 | } |
5759 | break; | |
5760 | case 0xc4: /* les Gv */ | |
701ed211 | 5761 | /* In CODE64 this is VEX3; see above. */ |
2c0262af FB |
5762 | op = R_ES; |
5763 | goto do_lxx; | |
5764 | case 0xc5: /* lds Gv */ | |
701ed211 | 5765 | /* In CODE64 this is VEX2; see above. */ |
2c0262af FB |
5766 | op = R_DS; |
5767 | goto do_lxx; | |
5768 | case 0x1b2: /* lss Gv */ | |
5769 | op = R_SS; | |
5770 | goto do_lxx; | |
5771 | case 0x1b4: /* lfs Gv */ | |
5772 | op = R_FS; | |
5773 | goto do_lxx; | |
5774 | case 0x1b5: /* lgs Gv */ | |
5775 | op = R_GS; | |
5776 | do_lxx: | |
4ba9938c | 5777 | ot = dflag ? MO_32 : MO_16; |
0af10c86 | 5778 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5779 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5780 | mod = (modrm >> 6) & 3; |
5781 | if (mod == 3) | |
5782 | goto illegal_op; | |
4eeb3939 | 5783 | gen_lea_modrm(env, s, modrm); |
0f712e10 | 5784 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
4ba9938c | 5785 | gen_add_A0_im(s, 1 << (ot - MO_16 + 1)); |
2c0262af | 5786 | /* load the segment first to handle exceptions properly */ |
cc1a80df | 5787 | gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); |
2c0262af FB |
5788 | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
5789 | /* then put the data */ | |
57fec1fe | 5790 | gen_op_mov_reg_T1(ot, reg); |
2c0262af | 5791 | if (s->is_jmp) { |
14ce26e7 | 5792 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5793 | gen_eob(s); |
5794 | } | |
5795 | break; | |
3b46e624 | 5796 | |
2c0262af FB |
5797 | /************************/ |
5798 | /* shifts */ | |
5799 | case 0xc0: | |
5800 | case 0xc1: | |
5801 | /* shift Ev,Ib */ | |
5802 | shift = 2; | |
5803 | grp2: | |
5804 | { | |
5805 | if ((b & 1) == 0) | |
4ba9938c | 5806 | ot = MO_8; |
2c0262af | 5807 | else |
4ba9938c | 5808 | ot = dflag + MO_16; |
3b46e624 | 5809 | |
0af10c86 | 5810 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5811 | mod = (modrm >> 6) & 3; |
2c0262af | 5812 | op = (modrm >> 3) & 7; |
3b46e624 | 5813 | |
2c0262af | 5814 | if (mod != 3) { |
14ce26e7 FB |
5815 | if (shift == 2) { |
5816 | s->rip_offset = 1; | |
5817 | } | |
4eeb3939 | 5818 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
5819 | opreg = OR_TMP0; |
5820 | } else { | |
14ce26e7 | 5821 | opreg = (modrm & 7) | REX_B(s); |
2c0262af FB |
5822 | } |
5823 | ||
5824 | /* simpler op */ | |
5825 | if (shift == 0) { | |
5826 | gen_shift(s, op, ot, opreg, OR_ECX); | |
5827 | } else { | |
5828 | if (shift == 2) { | |
0af10c86 | 5829 | shift = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5830 | } |
5831 | gen_shifti(s, op, ot, opreg, shift); | |
5832 | } | |
5833 | } | |
5834 | break; | |
5835 | case 0xd0: | |
5836 | case 0xd1: | |
5837 | /* shift Ev,1 */ | |
5838 | shift = 1; | |
5839 | goto grp2; | |
5840 | case 0xd2: | |
5841 | case 0xd3: | |
5842 | /* shift Ev,cl */ | |
5843 | shift = 0; | |
5844 | goto grp2; | |
5845 | ||
5846 | case 0x1a4: /* shld imm */ | |
5847 | op = 0; | |
5848 | shift = 1; | |
5849 | goto do_shiftd; | |
5850 | case 0x1a5: /* shld cl */ | |
5851 | op = 0; | |
5852 | shift = 0; | |
5853 | goto do_shiftd; | |
5854 | case 0x1ac: /* shrd imm */ | |
5855 | op = 1; | |
5856 | shift = 1; | |
5857 | goto do_shiftd; | |
5858 | case 0x1ad: /* shrd cl */ | |
5859 | op = 1; | |
5860 | shift = 0; | |
5861 | do_shiftd: | |
4ba9938c | 5862 | ot = dflag + MO_16; |
0af10c86 | 5863 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5864 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5865 | rm = (modrm & 7) | REX_B(s); |
5866 | reg = ((modrm >> 3) & 7) | rex_r; | |
2c0262af | 5867 | if (mod != 3) { |
4eeb3939 | 5868 | gen_lea_modrm(env, s, modrm); |
b6abf97d | 5869 | opreg = OR_TMP0; |
2c0262af | 5870 | } else { |
b6abf97d | 5871 | opreg = rm; |
2c0262af | 5872 | } |
57fec1fe | 5873 | gen_op_mov_TN_reg(ot, 1, reg); |
3b46e624 | 5874 | |
2c0262af | 5875 | if (shift) { |
3b9d3cf1 PB |
5876 | TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++)); |
5877 | gen_shiftd_rm_T1(s, ot, opreg, op, imm); | |
5878 | tcg_temp_free(imm); | |
2c0262af | 5879 | } else { |
3b9d3cf1 | 5880 | gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); |
2c0262af FB |
5881 | } |
5882 | break; | |
5883 | ||
5884 | /************************/ | |
5885 | /* floats */ | |
5fafdf24 | 5886 | case 0xd8 ... 0xdf: |
7eee2a50 FB |
5887 | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { |
5888 | /* if CR0.EM or CR0.TS are set, generate an FPU exception */ | |
5889 | /* XXX: what to do if illegal op ? */ | |
5890 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
5891 | break; | |
5892 | } | |
0af10c86 | 5893 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5894 | mod = (modrm >> 6) & 3; |
5895 | rm = modrm & 7; | |
5896 | op = ((b & 7) << 3) | ((modrm >> 3) & 7); | |
2c0262af FB |
5897 | if (mod != 3) { |
5898 | /* memory op */ | |
4eeb3939 | 5899 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
5900 | switch(op) { |
5901 | case 0x00 ... 0x07: /* fxxxs */ | |
5902 | case 0x10 ... 0x17: /* fixxxl */ | |
5903 | case 0x20 ... 0x27: /* fxxxl */ | |
5904 | case 0x30 ... 0x37: /* fixxx */ | |
5905 | { | |
5906 | int op1; | |
5907 | op1 = op & 7; | |
5908 | ||
5909 | switch(op >> 4) { | |
5910 | case 0: | |
909be183 | 5911 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
b6abf97d | 5912 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5913 | gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5914 | break; |
5915 | case 1: | |
909be183 | 5916 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
b6abf97d | 5917 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5918 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5919 | break; |
5920 | case 2: | |
3c5f4116 RH |
5921 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, |
5922 | s->mem_index, MO_LEQ); | |
d3eb5eae | 5923 | gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5924 | break; |
5925 | case 3: | |
5926 | default: | |
dc732b76 | 5927 | gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0); |
b6abf97d | 5928 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5929 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5930 | break; |
5931 | } | |
3b46e624 | 5932 | |
a7812ae4 | 5933 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5934 | if (op1 == 3) { |
5935 | /* fcomp needs pop */ | |
d3eb5eae | 5936 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5937 | } |
5938 | } | |
5939 | break; | |
5940 | case 0x08: /* flds */ | |
5941 | case 0x0a: /* fsts */ | |
5942 | case 0x0b: /* fstps */ | |
465e9838 FB |
5943 | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
5944 | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ | |
5945 | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ | |
2c0262af FB |
5946 | switch(op & 7) { |
5947 | case 0: | |
5948 | switch(op >> 4) { | |
5949 | case 0: | |
909be183 | 5950 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
b6abf97d | 5951 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5952 | gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5953 | break; |
5954 | case 1: | |
909be183 | 5955 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
b6abf97d | 5956 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5957 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5958 | break; |
5959 | case 2: | |
3c5f4116 RH |
5960 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, |
5961 | s->mem_index, MO_LEQ); | |
d3eb5eae | 5962 | gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5963 | break; |
5964 | case 3: | |
5965 | default: | |
dc732b76 | 5966 | gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0); |
b6abf97d | 5967 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5968 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5969 | break; |
5970 | } | |
5971 | break; | |
465e9838 | 5972 | case 1: |
19e6c4b8 | 5973 | /* XXX: the corresponding CPUID bit must be tested ! */ |
465e9838 FB |
5974 | switch(op >> 4) { |
5975 | case 1: | |
d3eb5eae | 5976 | gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5977 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
fd8ca9f6 | 5978 | gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); |
465e9838 FB |
5979 | break; |
5980 | case 2: | |
d3eb5eae | 5981 | gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); |
3523e4bd RH |
5982 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, |
5983 | s->mem_index, MO_LEQ); | |
465e9838 FB |
5984 | break; |
5985 | case 3: | |
5986 | default: | |
d3eb5eae | 5987 | gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5988 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
fd8ca9f6 | 5989 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
19e6c4b8 | 5990 | break; |
465e9838 | 5991 | } |
d3eb5eae | 5992 | gen_helper_fpop(cpu_env); |
465e9838 | 5993 | break; |
2c0262af FB |
5994 | default: |
5995 | switch(op >> 4) { | |
5996 | case 0: | |
d3eb5eae | 5997 | gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5998 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
fd8ca9f6 | 5999 | gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); |
2c0262af FB |
6000 | break; |
6001 | case 1: | |
d3eb5eae | 6002 | gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 6003 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
fd8ca9f6 | 6004 | gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); |
2c0262af FB |
6005 | break; |
6006 | case 2: | |
d3eb5eae | 6007 | gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); |
3523e4bd RH |
6008 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, |
6009 | s->mem_index, MO_LEQ); | |
2c0262af FB |
6010 | break; |
6011 | case 3: | |
6012 | default: | |
d3eb5eae | 6013 | gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 6014 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
fd8ca9f6 | 6015 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
2c0262af FB |
6016 | break; |
6017 | } | |
6018 | if ((op & 7) == 3) | |
d3eb5eae | 6019 | gen_helper_fpop(cpu_env); |
2c0262af FB |
6020 | break; |
6021 | } | |
6022 | break; | |
6023 | case 0x0c: /* fldenv mem */ | |
773cdfcc | 6024 | gen_update_cc_op(s); |
19e6c4b8 | 6025 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6026 | gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
6027 | break; |
6028 | case 0x0d: /* fldcw mem */ | |
909be183 | 6029 | gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); |
b6abf97d | 6030 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 6031 | gen_helper_fldcw(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
6032 | break; |
6033 | case 0x0e: /* fnstenv mem */ | |
773cdfcc | 6034 | gen_update_cc_op(s); |
19e6c4b8 | 6035 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6036 | gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
6037 | break; |
6038 | case 0x0f: /* fnstcw mem */ | |
d3eb5eae | 6039 | gen_helper_fnstcw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 6040 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
fd8ca9f6 | 6041 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
2c0262af FB |
6042 | break; |
6043 | case 0x1d: /* fldt mem */ | |
773cdfcc | 6044 | gen_update_cc_op(s); |
19e6c4b8 | 6045 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6046 | gen_helper_fldt_ST0(cpu_env, cpu_A0); |
2c0262af FB |
6047 | break; |
6048 | case 0x1f: /* fstpt mem */ | |
773cdfcc | 6049 | gen_update_cc_op(s); |
19e6c4b8 | 6050 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
6051 | gen_helper_fstt_ST0(cpu_env, cpu_A0); |
6052 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6053 | break; |
6054 | case 0x2c: /* frstor mem */ | |
773cdfcc | 6055 | gen_update_cc_op(s); |
19e6c4b8 | 6056 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6057 | gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
6058 | break; |
6059 | case 0x2e: /* fnsave mem */ | |
773cdfcc | 6060 | gen_update_cc_op(s); |
19e6c4b8 | 6061 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6062 | gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
6063 | break; |
6064 | case 0x2f: /* fnstsw mem */ | |
d3eb5eae | 6065 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 6066 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
fd8ca9f6 | 6067 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
2c0262af FB |
6068 | break; |
6069 | case 0x3c: /* fbld */ | |
773cdfcc | 6070 | gen_update_cc_op(s); |
19e6c4b8 | 6071 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6072 | gen_helper_fbld_ST0(cpu_env, cpu_A0); |
2c0262af FB |
6073 | break; |
6074 | case 0x3e: /* fbstp */ | |
773cdfcc | 6075 | gen_update_cc_op(s); |
19e6c4b8 | 6076 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
6077 | gen_helper_fbst_ST0(cpu_env, cpu_A0); |
6078 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6079 | break; |
6080 | case 0x3d: /* fildll */ | |
3c5f4116 | 6081 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); |
d3eb5eae | 6082 | gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
6083 | break; |
6084 | case 0x3f: /* fistpll */ | |
d3eb5eae | 6085 | gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env); |
3523e4bd | 6086 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); |
d3eb5eae | 6087 | gen_helper_fpop(cpu_env); |
2c0262af FB |
6088 | break; |
6089 | default: | |
6090 | goto illegal_op; | |
6091 | } | |
6092 | } else { | |
6093 | /* register float ops */ | |
6094 | opreg = rm; | |
6095 | ||
6096 | switch(op) { | |
6097 | case 0x08: /* fld sti */ | |
d3eb5eae BS |
6098 | gen_helper_fpush(cpu_env); |
6099 | gen_helper_fmov_ST0_STN(cpu_env, | |
6100 | tcg_const_i32((opreg + 1) & 7)); | |
2c0262af FB |
6101 | break; |
6102 | case 0x09: /* fxchg sti */ | |
c169c906 FB |
6103 | case 0x29: /* fxchg4 sti, undocumented op */ |
6104 | case 0x39: /* fxchg7 sti, undocumented op */ | |
d3eb5eae | 6105 | gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
6106 | break; |
6107 | case 0x0a: /* grp d9/2 */ | |
6108 | switch(rm) { | |
6109 | case 0: /* fnop */ | |
023fe10d | 6110 | /* check exceptions (FreeBSD FPU probe) */ |
773cdfcc | 6111 | gen_update_cc_op(s); |
14ce26e7 | 6112 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6113 | gen_helper_fwait(cpu_env); |
2c0262af FB |
6114 | break; |
6115 | default: | |
6116 | goto illegal_op; | |
6117 | } | |
6118 | break; | |
6119 | case 0x0c: /* grp d9/4 */ | |
6120 | switch(rm) { | |
6121 | case 0: /* fchs */ | |
d3eb5eae | 6122 | gen_helper_fchs_ST0(cpu_env); |
2c0262af FB |
6123 | break; |
6124 | case 1: /* fabs */ | |
d3eb5eae | 6125 | gen_helper_fabs_ST0(cpu_env); |
2c0262af FB |
6126 | break; |
6127 | case 4: /* ftst */ | |
d3eb5eae BS |
6128 | gen_helper_fldz_FT0(cpu_env); |
6129 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
6130 | break; |
6131 | case 5: /* fxam */ | |
d3eb5eae | 6132 | gen_helper_fxam_ST0(cpu_env); |
2c0262af FB |
6133 | break; |
6134 | default: | |
6135 | goto illegal_op; | |
6136 | } | |
6137 | break; | |
6138 | case 0x0d: /* grp d9/5 */ | |
6139 | { | |
6140 | switch(rm) { | |
6141 | case 0: | |
d3eb5eae BS |
6142 | gen_helper_fpush(cpu_env); |
6143 | gen_helper_fld1_ST0(cpu_env); | |
2c0262af FB |
6144 | break; |
6145 | case 1: | |
d3eb5eae BS |
6146 | gen_helper_fpush(cpu_env); |
6147 | gen_helper_fldl2t_ST0(cpu_env); | |
2c0262af FB |
6148 | break; |
6149 | case 2: | |
d3eb5eae BS |
6150 | gen_helper_fpush(cpu_env); |
6151 | gen_helper_fldl2e_ST0(cpu_env); | |
2c0262af FB |
6152 | break; |
6153 | case 3: | |
d3eb5eae BS |
6154 | gen_helper_fpush(cpu_env); |
6155 | gen_helper_fldpi_ST0(cpu_env); | |
2c0262af FB |
6156 | break; |
6157 | case 4: | |
d3eb5eae BS |
6158 | gen_helper_fpush(cpu_env); |
6159 | gen_helper_fldlg2_ST0(cpu_env); | |
2c0262af FB |
6160 | break; |
6161 | case 5: | |
d3eb5eae BS |
6162 | gen_helper_fpush(cpu_env); |
6163 | gen_helper_fldln2_ST0(cpu_env); | |
2c0262af FB |
6164 | break; |
6165 | case 6: | |
d3eb5eae BS |
6166 | gen_helper_fpush(cpu_env); |
6167 | gen_helper_fldz_ST0(cpu_env); | |
2c0262af FB |
6168 | break; |
6169 | default: | |
6170 | goto illegal_op; | |
6171 | } | |
6172 | } | |
6173 | break; | |
6174 | case 0x0e: /* grp d9/6 */ | |
6175 | switch(rm) { | |
6176 | case 0: /* f2xm1 */ | |
d3eb5eae | 6177 | gen_helper_f2xm1(cpu_env); |
2c0262af FB |
6178 | break; |
6179 | case 1: /* fyl2x */ | |
d3eb5eae | 6180 | gen_helper_fyl2x(cpu_env); |
2c0262af FB |
6181 | break; |
6182 | case 2: /* fptan */ | |
d3eb5eae | 6183 | gen_helper_fptan(cpu_env); |
2c0262af FB |
6184 | break; |
6185 | case 3: /* fpatan */ | |
d3eb5eae | 6186 | gen_helper_fpatan(cpu_env); |
2c0262af FB |
6187 | break; |
6188 | case 4: /* fxtract */ | |
d3eb5eae | 6189 | gen_helper_fxtract(cpu_env); |
2c0262af FB |
6190 | break; |
6191 | case 5: /* fprem1 */ | |
d3eb5eae | 6192 | gen_helper_fprem1(cpu_env); |
2c0262af FB |
6193 | break; |
6194 | case 6: /* fdecstp */ | |
d3eb5eae | 6195 | gen_helper_fdecstp(cpu_env); |
2c0262af FB |
6196 | break; |
6197 | default: | |
6198 | case 7: /* fincstp */ | |
d3eb5eae | 6199 | gen_helper_fincstp(cpu_env); |
2c0262af FB |
6200 | break; |
6201 | } | |
6202 | break; | |
6203 | case 0x0f: /* grp d9/7 */ | |
6204 | switch(rm) { | |
6205 | case 0: /* fprem */ | |
d3eb5eae | 6206 | gen_helper_fprem(cpu_env); |
2c0262af FB |
6207 | break; |
6208 | case 1: /* fyl2xp1 */ | |
d3eb5eae | 6209 | gen_helper_fyl2xp1(cpu_env); |
2c0262af FB |
6210 | break; |
6211 | case 2: /* fsqrt */ | |
d3eb5eae | 6212 | gen_helper_fsqrt(cpu_env); |
2c0262af FB |
6213 | break; |
6214 | case 3: /* fsincos */ | |
d3eb5eae | 6215 | gen_helper_fsincos(cpu_env); |
2c0262af FB |
6216 | break; |
6217 | case 5: /* fscale */ | |
d3eb5eae | 6218 | gen_helper_fscale(cpu_env); |
2c0262af FB |
6219 | break; |
6220 | case 4: /* frndint */ | |
d3eb5eae | 6221 | gen_helper_frndint(cpu_env); |
2c0262af FB |
6222 | break; |
6223 | case 6: /* fsin */ | |
d3eb5eae | 6224 | gen_helper_fsin(cpu_env); |
2c0262af FB |
6225 | break; |
6226 | default: | |
6227 | case 7: /* fcos */ | |
d3eb5eae | 6228 | gen_helper_fcos(cpu_env); |
2c0262af FB |
6229 | break; |
6230 | } | |
6231 | break; | |
6232 | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ | |
6233 | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ | |
6234 | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ | |
6235 | { | |
6236 | int op1; | |
3b46e624 | 6237 | |
2c0262af FB |
6238 | op1 = op & 7; |
6239 | if (op >= 0x20) { | |
a7812ae4 | 6240 | gen_helper_fp_arith_STN_ST0(op1, opreg); |
2c0262af | 6241 | if (op >= 0x30) |
d3eb5eae | 6242 | gen_helper_fpop(cpu_env); |
2c0262af | 6243 | } else { |
d3eb5eae | 6244 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
a7812ae4 | 6245 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
6246 | } |
6247 | } | |
6248 | break; | |
6249 | case 0x02: /* fcom */ | |
c169c906 | 6250 | case 0x22: /* fcom2, undocumented op */ |
d3eb5eae BS |
6251 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6252 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
6253 | break; |
6254 | case 0x03: /* fcomp */ | |
c169c906 FB |
6255 | case 0x23: /* fcomp3, undocumented op */ |
6256 | case 0x32: /* fcomp5, undocumented op */ | |
d3eb5eae BS |
6257 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6258 | gen_helper_fcom_ST0_FT0(cpu_env); | |
6259 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6260 | break; |
6261 | case 0x15: /* da/5 */ | |
6262 | switch(rm) { | |
6263 | case 1: /* fucompp */ | |
d3eb5eae BS |
6264 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
6265 | gen_helper_fucom_ST0_FT0(cpu_env); | |
6266 | gen_helper_fpop(cpu_env); | |
6267 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6268 | break; |
6269 | default: | |
6270 | goto illegal_op; | |
6271 | } | |
6272 | break; | |
6273 | case 0x1c: | |
6274 | switch(rm) { | |
6275 | case 0: /* feni (287 only, just do nop here) */ | |
6276 | break; | |
6277 | case 1: /* fdisi (287 only, just do nop here) */ | |
6278 | break; | |
6279 | case 2: /* fclex */ | |
d3eb5eae | 6280 | gen_helper_fclex(cpu_env); |
2c0262af FB |
6281 | break; |
6282 | case 3: /* fninit */ | |
d3eb5eae | 6283 | gen_helper_fninit(cpu_env); |
2c0262af FB |
6284 | break; |
6285 | case 4: /* fsetpm (287 only, just do nop here) */ | |
6286 | break; | |
6287 | default: | |
6288 | goto illegal_op; | |
6289 | } | |
6290 | break; | |
6291 | case 0x1d: /* fucomi */ | |
bff93281 PM |
6292 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6293 | goto illegal_op; | |
6294 | } | |
773cdfcc | 6295 | gen_update_cc_op(s); |
d3eb5eae BS |
6296 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6297 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
3ca51d07 | 6298 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6299 | break; |
6300 | case 0x1e: /* fcomi */ | |
bff93281 PM |
6301 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6302 | goto illegal_op; | |
6303 | } | |
773cdfcc | 6304 | gen_update_cc_op(s); |
d3eb5eae BS |
6305 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6306 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
3ca51d07 | 6307 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 6308 | break; |
658c8bda | 6309 | case 0x28: /* ffree sti */ |
d3eb5eae | 6310 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
5fafdf24 | 6311 | break; |
2c0262af | 6312 | case 0x2a: /* fst sti */ |
d3eb5eae | 6313 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
6314 | break; |
6315 | case 0x2b: /* fstp sti */ | |
c169c906 FB |
6316 | case 0x0b: /* fstp1 sti, undocumented op */ |
6317 | case 0x3a: /* fstp8 sti, undocumented op */ | |
6318 | case 0x3b: /* fstp9 sti, undocumented op */ | |
d3eb5eae BS |
6319 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
6320 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6321 | break; |
6322 | case 0x2c: /* fucom st(i) */ | |
d3eb5eae BS |
6323 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6324 | gen_helper_fucom_ST0_FT0(cpu_env); | |
2c0262af FB |
6325 | break; |
6326 | case 0x2d: /* fucomp st(i) */ | |
d3eb5eae BS |
6327 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6328 | gen_helper_fucom_ST0_FT0(cpu_env); | |
6329 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6330 | break; |
6331 | case 0x33: /* de/3 */ | |
6332 | switch(rm) { | |
6333 | case 1: /* fcompp */ | |
d3eb5eae BS |
6334 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
6335 | gen_helper_fcom_ST0_FT0(cpu_env); | |
6336 | gen_helper_fpop(cpu_env); | |
6337 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6338 | break; |
6339 | default: | |
6340 | goto illegal_op; | |
6341 | } | |
6342 | break; | |
c169c906 | 6343 | case 0x38: /* ffreep sti, undocumented op */ |
d3eb5eae BS |
6344 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
6345 | gen_helper_fpop(cpu_env); | |
c169c906 | 6346 | break; |
2c0262af FB |
6347 | case 0x3c: /* df/4 */ |
6348 | switch(rm) { | |
6349 | case 0: | |
d3eb5eae | 6350 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 6351 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
4ba9938c | 6352 | gen_op_mov_reg_T0(MO_16, R_EAX); |
2c0262af FB |
6353 | break; |
6354 | default: | |
6355 | goto illegal_op; | |
6356 | } | |
6357 | break; | |
6358 | case 0x3d: /* fucomip */ | |
bff93281 PM |
6359 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6360 | goto illegal_op; | |
6361 | } | |
773cdfcc | 6362 | gen_update_cc_op(s); |
d3eb5eae BS |
6363 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6364 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
6365 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 6366 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6367 | break; |
6368 | case 0x3e: /* fcomip */ | |
bff93281 PM |
6369 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6370 | goto illegal_op; | |
6371 | } | |
773cdfcc | 6372 | gen_update_cc_op(s); |
d3eb5eae BS |
6373 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6374 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
6375 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 6376 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 6377 | break; |
a2cc3b24 FB |
6378 | case 0x10 ... 0x13: /* fcmovxx */ |
6379 | case 0x18 ... 0x1b: | |
6380 | { | |
19e6c4b8 | 6381 | int op1, l1; |
d70040bc | 6382 | static const uint8_t fcmov_cc[8] = { |
a2cc3b24 FB |
6383 | (JCC_B << 1), |
6384 | (JCC_Z << 1), | |
6385 | (JCC_BE << 1), | |
6386 | (JCC_P << 1), | |
6387 | }; | |
bff93281 PM |
6388 | |
6389 | if (!(s->cpuid_features & CPUID_CMOV)) { | |
6390 | goto illegal_op; | |
6391 | } | |
1e4840bf | 6392 | op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); |
19e6c4b8 | 6393 | l1 = gen_new_label(); |
dc259201 | 6394 | gen_jcc1_noeob(s, op1, l1); |
d3eb5eae | 6395 | gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
19e6c4b8 | 6396 | gen_set_label(l1); |
a2cc3b24 FB |
6397 | } |
6398 | break; | |
2c0262af FB |
6399 | default: |
6400 | goto illegal_op; | |
6401 | } | |
6402 | } | |
6403 | break; | |
6404 | /************************/ | |
6405 | /* string ops */ | |
6406 | ||
6407 | case 0xa4: /* movsS */ | |
6408 | case 0xa5: | |
6409 | if ((b & 1) == 0) | |
4ba9938c | 6410 | ot = MO_8; |
2c0262af | 6411 | else |
4ba9938c | 6412 | ot = dflag + MO_16; |
2c0262af FB |
6413 | |
6414 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6415 | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6416 | } else { | |
6417 | gen_movs(s, ot); | |
6418 | } | |
6419 | break; | |
3b46e624 | 6420 | |
2c0262af FB |
6421 | case 0xaa: /* stosS */ |
6422 | case 0xab: | |
6423 | if ((b & 1) == 0) | |
4ba9938c | 6424 | ot = MO_8; |
2c0262af | 6425 | else |
4ba9938c | 6426 | ot = dflag + MO_16; |
2c0262af FB |
6427 | |
6428 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6429 | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6430 | } else { | |
6431 | gen_stos(s, ot); | |
6432 | } | |
6433 | break; | |
6434 | case 0xac: /* lodsS */ | |
6435 | case 0xad: | |
6436 | if ((b & 1) == 0) | |
4ba9938c | 6437 | ot = MO_8; |
2c0262af | 6438 | else |
4ba9938c | 6439 | ot = dflag + MO_16; |
2c0262af FB |
6440 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6441 | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6442 | } else { | |
6443 | gen_lods(s, ot); | |
6444 | } | |
6445 | break; | |
6446 | case 0xae: /* scasS */ | |
6447 | case 0xaf: | |
6448 | if ((b & 1) == 0) | |
4ba9938c | 6449 | ot = MO_8; |
2c0262af | 6450 | else |
4ba9938c | 6451 | ot = dflag + MO_16; |
2c0262af FB |
6452 | if (prefixes & PREFIX_REPNZ) { |
6453 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6454 | } else if (prefixes & PREFIX_REPZ) { | |
6455 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6456 | } else { | |
6457 | gen_scas(s, ot); | |
2c0262af FB |
6458 | } |
6459 | break; | |
6460 | ||
6461 | case 0xa6: /* cmpsS */ | |
6462 | case 0xa7: | |
6463 | if ((b & 1) == 0) | |
4ba9938c | 6464 | ot = MO_8; |
2c0262af | 6465 | else |
4ba9938c | 6466 | ot = dflag + MO_16; |
2c0262af FB |
6467 | if (prefixes & PREFIX_REPNZ) { |
6468 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6469 | } else if (prefixes & PREFIX_REPZ) { | |
6470 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6471 | } else { | |
6472 | gen_cmps(s, ot); | |
2c0262af FB |
6473 | } |
6474 | break; | |
6475 | case 0x6c: /* insS */ | |
6476 | case 0x6d: | |
f115e911 | 6477 | if ((b & 1) == 0) |
4ba9938c | 6478 | ot = MO_8; |
f115e911 | 6479 | else |
4ba9938c RH |
6480 | ot = dflag ? MO_32 : MO_16; |
6481 | gen_op_mov_TN_reg(MO_16, 0, R_EDX); | |
0573fbfc | 6482 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6483 | gen_check_io(s, ot, pc_start - s->cs_base, |
6484 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6485 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6486 | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6487 | } else { |
f115e911 | 6488 | gen_ins(s, ot); |
2e70f6ef PB |
6489 | if (use_icount) { |
6490 | gen_jmp(s, s->pc - s->cs_base); | |
6491 | } | |
2c0262af FB |
6492 | } |
6493 | break; | |
6494 | case 0x6e: /* outsS */ | |
6495 | case 0x6f: | |
f115e911 | 6496 | if ((b & 1) == 0) |
4ba9938c | 6497 | ot = MO_8; |
f115e911 | 6498 | else |
4ba9938c RH |
6499 | ot = dflag ? MO_32 : MO_16; |
6500 | gen_op_mov_TN_reg(MO_16, 0, R_EDX); | |
0573fbfc | 6501 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6502 | gen_check_io(s, ot, pc_start - s->cs_base, |
6503 | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6504 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6505 | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6506 | } else { |
f115e911 | 6507 | gen_outs(s, ot); |
2e70f6ef PB |
6508 | if (use_icount) { |
6509 | gen_jmp(s, s->pc - s->cs_base); | |
6510 | } | |
2c0262af FB |
6511 | } |
6512 | break; | |
6513 | ||
6514 | /************************/ | |
6515 | /* port I/O */ | |
0573fbfc | 6516 | |
2c0262af FB |
6517 | case 0xe4: |
6518 | case 0xe5: | |
f115e911 | 6519 | if ((b & 1) == 0) |
4ba9938c | 6520 | ot = MO_8; |
f115e911 | 6521 | else |
4ba9938c | 6522 | ot = dflag ? MO_32 : MO_16; |
0af10c86 | 6523 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6524 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6525 | gen_check_io(s, ot, pc_start - s->cs_base, |
6526 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6527 | if (use_icount) |
6528 | gen_io_start(); | |
b6abf97d | 6529 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6530 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6531 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6532 | if (use_icount) { |
6533 | gen_io_end(); | |
6534 | gen_jmp(s, s->pc - s->cs_base); | |
6535 | } | |
2c0262af FB |
6536 | break; |
6537 | case 0xe6: | |
6538 | case 0xe7: | |
f115e911 | 6539 | if ((b & 1) == 0) |
4ba9938c | 6540 | ot = MO_8; |
f115e911 | 6541 | else |
4ba9938c | 6542 | ot = dflag ? MO_32 : MO_16; |
0af10c86 | 6543 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6544 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6545 | gen_check_io(s, ot, pc_start - s->cs_base, |
6546 | svm_is_rep(prefixes)); | |
57fec1fe | 6547 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6548 | |
2e70f6ef PB |
6549 | if (use_icount) |
6550 | gen_io_start(); | |
b6abf97d | 6551 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6552 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6553 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6554 | if (use_icount) { |
6555 | gen_io_end(); | |
6556 | gen_jmp(s, s->pc - s->cs_base); | |
6557 | } | |
2c0262af FB |
6558 | break; |
6559 | case 0xec: | |
6560 | case 0xed: | |
f115e911 | 6561 | if ((b & 1) == 0) |
4ba9938c | 6562 | ot = MO_8; |
f115e911 | 6563 | else |
4ba9938c RH |
6564 | ot = dflag ? MO_32 : MO_16; |
6565 | gen_op_mov_TN_reg(MO_16, 0, R_EDX); | |
4f31916f | 6566 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6567 | gen_check_io(s, ot, pc_start - s->cs_base, |
6568 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6569 | if (use_icount) |
6570 | gen_io_start(); | |
b6abf97d | 6571 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6572 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6573 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6574 | if (use_icount) { |
6575 | gen_io_end(); | |
6576 | gen_jmp(s, s->pc - s->cs_base); | |
6577 | } | |
2c0262af FB |
6578 | break; |
6579 | case 0xee: | |
6580 | case 0xef: | |
f115e911 | 6581 | if ((b & 1) == 0) |
4ba9938c | 6582 | ot = MO_8; |
f115e911 | 6583 | else |
4ba9938c RH |
6584 | ot = dflag ? MO_32 : MO_16; |
6585 | gen_op_mov_TN_reg(MO_16, 0, R_EDX); | |
4f31916f | 6586 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6587 | gen_check_io(s, ot, pc_start - s->cs_base, |
6588 | svm_is_rep(prefixes)); | |
57fec1fe | 6589 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6590 | |
2e70f6ef PB |
6591 | if (use_icount) |
6592 | gen_io_start(); | |
b6abf97d | 6593 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6594 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6595 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6596 | if (use_icount) { |
6597 | gen_io_end(); | |
6598 | gen_jmp(s, s->pc - s->cs_base); | |
6599 | } | |
2c0262af FB |
6600 | break; |
6601 | ||
6602 | /************************/ | |
6603 | /* control */ | |
6604 | case 0xc2: /* ret im */ | |
0af10c86 | 6605 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6606 | s->pc += 2; |
6607 | gen_pop_T0(s); | |
8f091a59 FB |
6608 | if (CODE64(s) && s->dflag) |
6609 | s->dflag = 2; | |
2c0262af FB |
6610 | gen_stack_update(s, val + (2 << s->dflag)); |
6611 | if (s->dflag == 0) | |
6612 | gen_op_andl_T0_ffff(); | |
6613 | gen_op_jmp_T0(); | |
6614 | gen_eob(s); | |
6615 | break; | |
6616 | case 0xc3: /* ret */ | |
6617 | gen_pop_T0(s); | |
6618 | gen_pop_update(s); | |
6619 | if (s->dflag == 0) | |
6620 | gen_op_andl_T0_ffff(); | |
6621 | gen_op_jmp_T0(); | |
6622 | gen_eob(s); | |
6623 | break; | |
6624 | case 0xca: /* lret im */ | |
0af10c86 | 6625 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6626 | s->pc += 2; |
6627 | do_lret: | |
6628 | if (s->pe && !s->vm86) { | |
773cdfcc | 6629 | gen_update_cc_op(s); |
14ce26e7 | 6630 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6631 | gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6632 | tcg_const_i32(val)); |
2c0262af FB |
6633 | } else { |
6634 | gen_stack_A0(s); | |
6635 | /* pop offset */ | |
909be183 | 6636 | gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0); |
2c0262af FB |
6637 | if (s->dflag == 0) |
6638 | gen_op_andl_T0_ffff(); | |
6639 | /* NOTE: keeping EIP updated is not a problem in case of | |
6640 | exception */ | |
6641 | gen_op_jmp_T0(); | |
6642 | /* pop selector */ | |
6643 | gen_op_addl_A0_im(2 << s->dflag); | |
909be183 | 6644 | gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0); |
3bd7da9e | 6645 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
6646 | /* add stack offset */ |
6647 | gen_stack_update(s, val + (4 << s->dflag)); | |
6648 | } | |
6649 | gen_eob(s); | |
6650 | break; | |
6651 | case 0xcb: /* lret */ | |
6652 | val = 0; | |
6653 | goto do_lret; | |
6654 | case 0xcf: /* iret */ | |
872929aa | 6655 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); |
2c0262af FB |
6656 | if (!s->pe) { |
6657 | /* real mode */ | |
2999a0b2 | 6658 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
3ca51d07 | 6659 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 FB |
6660 | } else if (s->vm86) { |
6661 | if (s->iopl != 3) { | |
6662 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6663 | } else { | |
2999a0b2 | 6664 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
3ca51d07 | 6665 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 6666 | } |
2c0262af | 6667 | } else { |
773cdfcc | 6668 | gen_update_cc_op(s); |
14ce26e7 | 6669 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6670 | gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6671 | tcg_const_i32(s->pc - s->cs_base)); |
3ca51d07 | 6672 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6673 | } |
6674 | gen_eob(s); | |
6675 | break; | |
6676 | case 0xe8: /* call im */ | |
6677 | { | |
14ce26e7 | 6678 | if (dflag) |
4ba9938c | 6679 | tval = (int32_t)insn_get(env, s, MO_32); |
14ce26e7 | 6680 | else |
4ba9938c | 6681 | tval = (int16_t)insn_get(env, s, MO_16); |
2c0262af | 6682 | next_eip = s->pc - s->cs_base; |
14ce26e7 | 6683 | tval += next_eip; |
2c0262af | 6684 | if (s->dflag == 0) |
14ce26e7 | 6685 | tval &= 0xffff; |
99596385 AJ |
6686 | else if(!CODE64(s)) |
6687 | tval &= 0xffffffff; | |
14ce26e7 | 6688 | gen_movtl_T0_im(next_eip); |
2c0262af | 6689 | gen_push_T0(s); |
14ce26e7 | 6690 | gen_jmp(s, tval); |
2c0262af FB |
6691 | } |
6692 | break; | |
6693 | case 0x9a: /* lcall im */ | |
6694 | { | |
6695 | unsigned int selector, offset; | |
3b46e624 | 6696 | |
14ce26e7 FB |
6697 | if (CODE64(s)) |
6698 | goto illegal_op; | |
4ba9938c | 6699 | ot = dflag ? MO_32 : MO_16; |
0af10c86 | 6700 | offset = insn_get(env, s, ot); |
4ba9938c | 6701 | selector = insn_get(env, s, MO_16); |
3b46e624 | 6702 | |
2c0262af | 6703 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6704 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6705 | } |
6706 | goto do_lcall; | |
ecada8a2 | 6707 | case 0xe9: /* jmp im */ |
14ce26e7 | 6708 | if (dflag) |
4ba9938c | 6709 | tval = (int32_t)insn_get(env, s, MO_32); |
14ce26e7 | 6710 | else |
4ba9938c | 6711 | tval = (int16_t)insn_get(env, s, MO_16); |
14ce26e7 | 6712 | tval += s->pc - s->cs_base; |
2c0262af | 6713 | if (s->dflag == 0) |
14ce26e7 | 6714 | tval &= 0xffff; |
32938e12 AJ |
6715 | else if(!CODE64(s)) |
6716 | tval &= 0xffffffff; | |
14ce26e7 | 6717 | gen_jmp(s, tval); |
2c0262af FB |
6718 | break; |
6719 | case 0xea: /* ljmp im */ | |
6720 | { | |
6721 | unsigned int selector, offset; | |
6722 | ||
14ce26e7 FB |
6723 | if (CODE64(s)) |
6724 | goto illegal_op; | |
4ba9938c | 6725 | ot = dflag ? MO_32 : MO_16; |
0af10c86 | 6726 | offset = insn_get(env, s, ot); |
4ba9938c | 6727 | selector = insn_get(env, s, MO_16); |
3b46e624 | 6728 | |
2c0262af | 6729 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6730 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6731 | } |
6732 | goto do_ljmp; | |
6733 | case 0xeb: /* jmp Jb */ | |
4ba9938c | 6734 | tval = (int8_t)insn_get(env, s, MO_8); |
14ce26e7 | 6735 | tval += s->pc - s->cs_base; |
2c0262af | 6736 | if (s->dflag == 0) |
14ce26e7 FB |
6737 | tval &= 0xffff; |
6738 | gen_jmp(s, tval); | |
2c0262af FB |
6739 | break; |
6740 | case 0x70 ... 0x7f: /* jcc Jb */ | |
4ba9938c | 6741 | tval = (int8_t)insn_get(env, s, MO_8); |
2c0262af FB |
6742 | goto do_jcc; |
6743 | case 0x180 ... 0x18f: /* jcc Jv */ | |
6744 | if (dflag) { | |
4ba9938c | 6745 | tval = (int32_t)insn_get(env, s, MO_32); |
2c0262af | 6746 | } else { |
4ba9938c | 6747 | tval = (int16_t)insn_get(env, s, MO_16); |
2c0262af FB |
6748 | } |
6749 | do_jcc: | |
6750 | next_eip = s->pc - s->cs_base; | |
14ce26e7 | 6751 | tval += next_eip; |
2c0262af | 6752 | if (s->dflag == 0) |
14ce26e7 FB |
6753 | tval &= 0xffff; |
6754 | gen_jcc(s, b, tval, next_eip); | |
2c0262af FB |
6755 | break; |
6756 | ||
6757 | case 0x190 ... 0x19f: /* setcc Gv */ | |
0af10c86 | 6758 | modrm = cpu_ldub_code(env, s->pc++); |
cc8b6f5b | 6759 | gen_setcc1(s, b, cpu_T[0]); |
4ba9938c | 6760 | gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1); |
2c0262af FB |
6761 | break; |
6762 | case 0x140 ... 0x14f: /* cmov Gv, Ev */ | |
bff93281 PM |
6763 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6764 | goto illegal_op; | |
6765 | } | |
4ba9938c | 6766 | ot = dflag + MO_16; |
f32d3781 PB |
6767 | modrm = cpu_ldub_code(env, s->pc++); |
6768 | reg = ((modrm >> 3) & 7) | rex_r; | |
6769 | gen_cmovcc1(env, s, ot, b, modrm, reg); | |
2c0262af | 6770 | break; |
3b46e624 | 6771 | |
2c0262af FB |
6772 | /************************/ |
6773 | /* flags */ | |
6774 | case 0x9c: /* pushf */ | |
872929aa | 6775 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); |
2c0262af FB |
6776 | if (s->vm86 && s->iopl != 3) { |
6777 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6778 | } else { | |
773cdfcc | 6779 | gen_update_cc_op(s); |
f0967a1a | 6780 | gen_helper_read_eflags(cpu_T[0], cpu_env); |
2c0262af FB |
6781 | gen_push_T0(s); |
6782 | } | |
6783 | break; | |
6784 | case 0x9d: /* popf */ | |
872929aa | 6785 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); |
2c0262af FB |
6786 | if (s->vm86 && s->iopl != 3) { |
6787 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6788 | } else { | |
6789 | gen_pop_T0(s); | |
6790 | if (s->cpl == 0) { | |
6791 | if (s->dflag) { | |
f0967a1a BS |
6792 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6793 | tcg_const_i32((TF_MASK | AC_MASK | | |
6794 | ID_MASK | NT_MASK | | |
6795 | IF_MASK | | |
6796 | IOPL_MASK))); | |
2c0262af | 6797 | } else { |
f0967a1a BS |
6798 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6799 | tcg_const_i32((TF_MASK | AC_MASK | | |
6800 | ID_MASK | NT_MASK | | |
6801 | IF_MASK | IOPL_MASK) | |
6802 | & 0xffff)); | |
2c0262af FB |
6803 | } |
6804 | } else { | |
4136f33c FB |
6805 | if (s->cpl <= s->iopl) { |
6806 | if (s->dflag) { | |
f0967a1a BS |
6807 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6808 | tcg_const_i32((TF_MASK | | |
6809 | AC_MASK | | |
6810 | ID_MASK | | |
6811 | NT_MASK | | |
6812 | IF_MASK))); | |
4136f33c | 6813 | } else { |
f0967a1a BS |
6814 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6815 | tcg_const_i32((TF_MASK | | |
6816 | AC_MASK | | |
6817 | ID_MASK | | |
6818 | NT_MASK | | |
6819 | IF_MASK) | |
6820 | & 0xffff)); | |
4136f33c | 6821 | } |
2c0262af | 6822 | } else { |
4136f33c | 6823 | if (s->dflag) { |
f0967a1a BS |
6824 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6825 | tcg_const_i32((TF_MASK | AC_MASK | | |
6826 | ID_MASK | NT_MASK))); | |
4136f33c | 6827 | } else { |
f0967a1a BS |
6828 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6829 | tcg_const_i32((TF_MASK | AC_MASK | | |
6830 | ID_MASK | NT_MASK) | |
6831 | & 0xffff)); | |
4136f33c | 6832 | } |
2c0262af FB |
6833 | } |
6834 | } | |
6835 | gen_pop_update(s); | |
3ca51d07 | 6836 | set_cc_op(s, CC_OP_EFLAGS); |
a9321a4d | 6837 | /* abort translation because TF/AC flag may change */ |
14ce26e7 | 6838 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6839 | gen_eob(s); |
6840 | } | |
6841 | break; | |
6842 | case 0x9e: /* sahf */ | |
12e26b75 | 6843 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6844 | goto illegal_op; |
4ba9938c | 6845 | gen_op_mov_TN_reg(MO_8, 0, R_AH); |
d229edce | 6846 | gen_compute_eflags(s); |
bd7a7b33 FB |
6847 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); |
6848 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); | |
6849 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); | |
2c0262af FB |
6850 | break; |
6851 | case 0x9f: /* lahf */ | |
12e26b75 | 6852 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6853 | goto illegal_op; |
d229edce | 6854 | gen_compute_eflags(s); |
bd7a7b33 | 6855 | /* Note: gen_compute_eflags() only gives the condition codes */ |
d229edce | 6856 | tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02); |
4ba9938c | 6857 | gen_op_mov_reg_T0(MO_8, R_AH); |
2c0262af FB |
6858 | break; |
6859 | case 0xf5: /* cmc */ | |
d229edce | 6860 | gen_compute_eflags(s); |
bd7a7b33 | 6861 | tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6862 | break; |
6863 | case 0xf8: /* clc */ | |
d229edce | 6864 | gen_compute_eflags(s); |
bd7a7b33 | 6865 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); |
2c0262af FB |
6866 | break; |
6867 | case 0xf9: /* stc */ | |
d229edce | 6868 | gen_compute_eflags(s); |
bd7a7b33 | 6869 | tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6870 | break; |
6871 | case 0xfc: /* cld */ | |
b6abf97d | 6872 | tcg_gen_movi_i32(cpu_tmp2_i32, 1); |
317ac620 | 6873 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6874 | break; |
6875 | case 0xfd: /* std */ | |
b6abf97d | 6876 | tcg_gen_movi_i32(cpu_tmp2_i32, -1); |
317ac620 | 6877 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6878 | break; |
6879 | ||
6880 | /************************/ | |
6881 | /* bit operations */ | |
6882 | case 0x1ba: /* bt/bts/btr/btc Gv, im */ | |
4ba9938c | 6883 | ot = dflag + MO_16; |
0af10c86 | 6884 | modrm = cpu_ldub_code(env, s->pc++); |
33698e5f | 6885 | op = (modrm >> 3) & 7; |
2c0262af | 6886 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6887 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 6888 | if (mod != 3) { |
14ce26e7 | 6889 | s->rip_offset = 1; |
4eeb3939 | 6890 | gen_lea_modrm(env, s, modrm); |
909be183 | 6891 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 6892 | } else { |
57fec1fe | 6893 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
6894 | } |
6895 | /* load shift */ | |
0af10c86 | 6896 | val = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
6897 | gen_op_movl_T1_im(val); |
6898 | if (op < 4) | |
6899 | goto illegal_op; | |
6900 | op -= 4; | |
f484d386 | 6901 | goto bt_op; |
2c0262af FB |
6902 | case 0x1a3: /* bt Gv, Ev */ |
6903 | op = 0; | |
6904 | goto do_btx; | |
6905 | case 0x1ab: /* bts */ | |
6906 | op = 1; | |
6907 | goto do_btx; | |
6908 | case 0x1b3: /* btr */ | |
6909 | op = 2; | |
6910 | goto do_btx; | |
6911 | case 0x1bb: /* btc */ | |
6912 | op = 3; | |
6913 | do_btx: | |
4ba9938c | 6914 | ot = dflag + MO_16; |
0af10c86 | 6915 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 6916 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 6917 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6918 | rm = (modrm & 7) | REX_B(s); |
4ba9938c | 6919 | gen_op_mov_TN_reg(MO_32, 1, reg); |
2c0262af | 6920 | if (mod != 3) { |
4eeb3939 | 6921 | gen_lea_modrm(env, s, modrm); |
2c0262af | 6922 | /* specific case: we need to add a displacement */ |
f484d386 FB |
6923 | gen_exts(ot, cpu_T[1]); |
6924 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); | |
6925 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); | |
6926 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
909be183 | 6927 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 6928 | } else { |
57fec1fe | 6929 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 6930 | } |
f484d386 FB |
6931 | bt_op: |
6932 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); | |
6933 | switch(op) { | |
6934 | case 0: | |
6935 | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); | |
6936 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6937 | break; | |
6938 | case 1: | |
6939 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6940 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6941 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6942 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6943 | break; | |
6944 | case 2: | |
6945 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6946 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6947 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6948 | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); | |
6949 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6950 | break; | |
6951 | default: | |
6952 | case 3: | |
6953 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6954 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6955 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6956 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6957 | break; | |
6958 | } | |
3ca51d07 | 6959 | set_cc_op(s, CC_OP_SARB + ot); |
2c0262af | 6960 | if (op != 0) { |
fd8ca9f6 RH |
6961 | if (mod != 3) { |
6962 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); | |
6963 | } else { | |
57fec1fe | 6964 | gen_op_mov_reg_T0(ot, rm); |
fd8ca9f6 | 6965 | } |
f484d386 FB |
6966 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
6967 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
2c0262af FB |
6968 | } |
6969 | break; | |
321c5351 RH |
6970 | case 0x1bc: /* bsf / tzcnt */ |
6971 | case 0x1bd: /* bsr / lzcnt */ | |
4ba9938c | 6972 | ot = dflag + MO_16; |
321c5351 RH |
6973 | modrm = cpu_ldub_code(env, s->pc++); |
6974 | reg = ((modrm >> 3) & 7) | rex_r; | |
6975 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); | |
6976 | gen_extu(ot, cpu_T[0]); | |
6977 | ||
6978 | /* Note that lzcnt and tzcnt are in different extensions. */ | |
6979 | if ((prefixes & PREFIX_REPZ) | |
6980 | && (b & 1 | |
6981 | ? s->cpuid_ext3_features & CPUID_EXT3_ABM | |
6982 | : s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) { | |
6983 | int size = 8 << ot; | |
6984 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
6985 | if (b & 1) { | |
6986 | /* For lzcnt, reduce the target_ulong result by the | |
6987 | number of zeros that we expect to find at the top. */ | |
6988 | gen_helper_clz(cpu_T[0], cpu_T[0]); | |
6989 | tcg_gen_subi_tl(cpu_T[0], cpu_T[0], TARGET_LONG_BITS - size); | |
6191b059 | 6990 | } else { |
321c5351 RH |
6991 | /* For tzcnt, a zero input must return the operand size: |
6992 | force all bits outside the operand size to 1. */ | |
6993 | target_ulong mask = (target_ulong)-2 << (size - 1); | |
6994 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], mask); | |
6995 | gen_helper_ctz(cpu_T[0], cpu_T[0]); | |
6191b059 | 6996 | } |
321c5351 RH |
6997 | /* For lzcnt/tzcnt, C and Z bits are defined and are |
6998 | related to the result. */ | |
6999 | gen_op_update1_cc(); | |
7000 | set_cc_op(s, CC_OP_BMILGB + ot); | |
7001 | } else { | |
7002 | /* For bsr/bsf, only the Z bit is defined and it is related | |
7003 | to the input and not the result. */ | |
7004 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
7005 | set_cc_op(s, CC_OP_LOGICB + ot); | |
7006 | if (b & 1) { | |
7007 | /* For bsr, return the bit index of the first 1 bit, | |
7008 | not the count of leading zeros. */ | |
7009 | gen_helper_clz(cpu_T[0], cpu_T[0]); | |
7010 | tcg_gen_xori_tl(cpu_T[0], cpu_T[0], TARGET_LONG_BITS - 1); | |
7011 | } else { | |
7012 | gen_helper_ctz(cpu_T[0], cpu_T[0]); | |
7013 | } | |
7014 | /* ??? The manual says that the output is undefined when the | |
7015 | input is zero, but real hardware leaves it unchanged, and | |
7016 | real programs appear to depend on that. */ | |
7017 | tcg_gen_movi_tl(cpu_tmp0, 0); | |
7018 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[0], cpu_cc_dst, cpu_tmp0, | |
7019 | cpu_regs[reg], cpu_T[0]); | |
6191b059 | 7020 | } |
321c5351 | 7021 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
7022 | break; |
7023 | /************************/ | |
7024 | /* bcd */ | |
7025 | case 0x27: /* daa */ | |
14ce26e7 FB |
7026 | if (CODE64(s)) |
7027 | goto illegal_op; | |
773cdfcc | 7028 | gen_update_cc_op(s); |
7923057b | 7029 | gen_helper_daa(cpu_env); |
3ca51d07 | 7030 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
7031 | break; |
7032 | case 0x2f: /* das */ | |
14ce26e7 FB |
7033 | if (CODE64(s)) |
7034 | goto illegal_op; | |
773cdfcc | 7035 | gen_update_cc_op(s); |
7923057b | 7036 | gen_helper_das(cpu_env); |
3ca51d07 | 7037 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
7038 | break; |
7039 | case 0x37: /* aaa */ | |
14ce26e7 FB |
7040 | if (CODE64(s)) |
7041 | goto illegal_op; | |
773cdfcc | 7042 | gen_update_cc_op(s); |
7923057b | 7043 | gen_helper_aaa(cpu_env); |
3ca51d07 | 7044 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
7045 | break; |
7046 | case 0x3f: /* aas */ | |
14ce26e7 FB |
7047 | if (CODE64(s)) |
7048 | goto illegal_op; | |
773cdfcc | 7049 | gen_update_cc_op(s); |
7923057b | 7050 | gen_helper_aas(cpu_env); |
3ca51d07 | 7051 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
7052 | break; |
7053 | case 0xd4: /* aam */ | |
14ce26e7 FB |
7054 | if (CODE64(s)) |
7055 | goto illegal_op; | |
0af10c86 | 7056 | val = cpu_ldub_code(env, s->pc++); |
b6d7c3db TS |
7057 | if (val == 0) { |
7058 | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); | |
7059 | } else { | |
7923057b | 7060 | gen_helper_aam(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 7061 | set_cc_op(s, CC_OP_LOGICB); |
b6d7c3db | 7062 | } |
2c0262af FB |
7063 | break; |
7064 | case 0xd5: /* aad */ | |
14ce26e7 FB |
7065 | if (CODE64(s)) |
7066 | goto illegal_op; | |
0af10c86 | 7067 | val = cpu_ldub_code(env, s->pc++); |
7923057b | 7068 | gen_helper_aad(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 7069 | set_cc_op(s, CC_OP_LOGICB); |
2c0262af FB |
7070 | break; |
7071 | /************************/ | |
7072 | /* misc */ | |
7073 | case 0x90: /* nop */ | |
ab1f142b | 7074 | /* XXX: correct lock test for all insn */ |
7418027e | 7075 | if (prefixes & PREFIX_LOCK) { |
ab1f142b | 7076 | goto illegal_op; |
7418027e RH |
7077 | } |
7078 | /* If REX_B is set, then this is xchg eax, r8d, not a nop. */ | |
7079 | if (REX_B(s)) { | |
7080 | goto do_xchg_reg_eax; | |
7081 | } | |
0573fbfc | 7082 | if (prefixes & PREFIX_REPZ) { |
81f3053b PB |
7083 | gen_update_cc_op(s); |
7084 | gen_jmp_im(pc_start - s->cs_base); | |
7085 | gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); | |
7086 | s->is_jmp = DISAS_TB_JUMP; | |
0573fbfc | 7087 | } |
2c0262af FB |
7088 | break; |
7089 | case 0x9b: /* fwait */ | |
5fafdf24 | 7090 | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == |
7eee2a50 FB |
7091 | (HF_MP_MASK | HF_TS_MASK)) { |
7092 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
2ee73ac3 | 7093 | } else { |
773cdfcc | 7094 | gen_update_cc_op(s); |
14ce26e7 | 7095 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 7096 | gen_helper_fwait(cpu_env); |
7eee2a50 | 7097 | } |
2c0262af FB |
7098 | break; |
7099 | case 0xcc: /* int3 */ | |
7100 | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); | |
7101 | break; | |
7102 | case 0xcd: /* int N */ | |
0af10c86 | 7103 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 7104 | if (s->vm86 && s->iopl != 3) { |
5fafdf24 | 7105 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
f115e911 FB |
7106 | } else { |
7107 | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); | |
7108 | } | |
2c0262af FB |
7109 | break; |
7110 | case 0xce: /* into */ | |
14ce26e7 FB |
7111 | if (CODE64(s)) |
7112 | goto illegal_op; | |
773cdfcc | 7113 | gen_update_cc_op(s); |
a8ede8ba | 7114 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7115 | gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start)); |
2c0262af | 7116 | break; |
0b97134b | 7117 | #ifdef WANT_ICEBP |
2c0262af | 7118 | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
872929aa | 7119 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); |
aba9d61e | 7120 | #if 1 |
2c0262af | 7121 | gen_debug(s, pc_start - s->cs_base); |
aba9d61e FB |
7122 | #else |
7123 | /* start debug */ | |
0af10c86 | 7124 | tb_flush(env); |
24537a01 | 7125 | qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); |
aba9d61e | 7126 | #endif |
2c0262af | 7127 | break; |
0b97134b | 7128 | #endif |
2c0262af FB |
7129 | case 0xfa: /* cli */ |
7130 | if (!s->vm86) { | |
7131 | if (s->cpl <= s->iopl) { | |
f0967a1a | 7132 | gen_helper_cli(cpu_env); |
2c0262af FB |
7133 | } else { |
7134 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7135 | } | |
7136 | } else { | |
7137 | if (s->iopl == 3) { | |
f0967a1a | 7138 | gen_helper_cli(cpu_env); |
2c0262af FB |
7139 | } else { |
7140 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7141 | } | |
7142 | } | |
7143 | break; | |
7144 | case 0xfb: /* sti */ | |
7145 | if (!s->vm86) { | |
7146 | if (s->cpl <= s->iopl) { | |
7147 | gen_sti: | |
f0967a1a | 7148 | gen_helper_sti(cpu_env); |
2c0262af | 7149 | /* interruptions are enabled only the first insn after sti */ |
a2cc3b24 FB |
7150 | /* If several instructions disable interrupts, only the |
7151 | _first_ does it */ | |
7152 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 7153 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af | 7154 | /* give a chance to handle pending irqs */ |
14ce26e7 | 7155 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7156 | gen_eob(s); |
7157 | } else { | |
7158 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7159 | } | |
7160 | } else { | |
7161 | if (s->iopl == 3) { | |
7162 | goto gen_sti; | |
7163 | } else { | |
7164 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7165 | } | |
7166 | } | |
7167 | break; | |
7168 | case 0x62: /* bound */ | |
14ce26e7 FB |
7169 | if (CODE64(s)) |
7170 | goto illegal_op; | |
4ba9938c | 7171 | ot = dflag ? MO_32 : MO_16; |
0af10c86 | 7172 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7173 | reg = (modrm >> 3) & 7; |
7174 | mod = (modrm >> 6) & 3; | |
7175 | if (mod == 3) | |
7176 | goto illegal_op; | |
57fec1fe | 7177 | gen_op_mov_TN_reg(ot, 0, reg); |
4eeb3939 | 7178 | gen_lea_modrm(env, s, modrm); |
14ce26e7 | 7179 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7180 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
4ba9938c | 7181 | if (ot == MO_16) { |
92fc4b58 BS |
7182 | gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32); |
7183 | } else { | |
7184 | gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32); | |
7185 | } | |
2c0262af FB |
7186 | break; |
7187 | case 0x1c8 ... 0x1cf: /* bswap reg */ | |
14ce26e7 FB |
7188 | reg = (b & 7) | REX_B(s); |
7189 | #ifdef TARGET_X86_64 | |
7190 | if (dflag == 2) { | |
4ba9938c | 7191 | gen_op_mov_TN_reg(MO_64, 0, reg); |
66896cb8 | 7192 | tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); |
4ba9938c | 7193 | gen_op_mov_reg_T0(MO_64, reg); |
5fafdf24 | 7194 | } else |
8777643e | 7195 | #endif |
57fec1fe | 7196 | { |
4ba9938c | 7197 | gen_op_mov_TN_reg(MO_32, 0, reg); |
8777643e AJ |
7198 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
7199 | tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); | |
4ba9938c | 7200 | gen_op_mov_reg_T0(MO_32, reg); |
14ce26e7 | 7201 | } |
2c0262af FB |
7202 | break; |
7203 | case 0xd6: /* salc */ | |
14ce26e7 FB |
7204 | if (CODE64(s)) |
7205 | goto illegal_op; | |
cc8b6f5b | 7206 | gen_compute_eflags_c(s, cpu_T[0]); |
bd7a7b33 | 7207 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 7208 | gen_op_mov_reg_T0(MO_8, R_EAX); |
2c0262af FB |
7209 | break; |
7210 | case 0xe0: /* loopnz */ | |
7211 | case 0xe1: /* loopz */ | |
2c0262af FB |
7212 | case 0xe2: /* loop */ |
7213 | case 0xe3: /* jecxz */ | |
14ce26e7 | 7214 | { |
6e0d8677 | 7215 | int l1, l2, l3; |
14ce26e7 | 7216 | |
4ba9938c | 7217 | tval = (int8_t)insn_get(env, s, MO_8); |
14ce26e7 FB |
7218 | next_eip = s->pc - s->cs_base; |
7219 | tval += next_eip; | |
7220 | if (s->dflag == 0) | |
7221 | tval &= 0xffff; | |
3b46e624 | 7222 | |
14ce26e7 FB |
7223 | l1 = gen_new_label(); |
7224 | l2 = gen_new_label(); | |
6e0d8677 | 7225 | l3 = gen_new_label(); |
14ce26e7 | 7226 | b &= 3; |
6e0d8677 FB |
7227 | switch(b) { |
7228 | case 0: /* loopnz */ | |
7229 | case 1: /* loopz */ | |
6e0d8677 FB |
7230 | gen_op_add_reg_im(s->aflag, R_ECX, -1); |
7231 | gen_op_jz_ecx(s->aflag, l3); | |
5bdb91b0 | 7232 | gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1); |
6e0d8677 FB |
7233 | break; |
7234 | case 2: /* loop */ | |
7235 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
7236 | gen_op_jnz_ecx(s->aflag, l1); | |
7237 | break; | |
7238 | default: | |
7239 | case 3: /* jcxz */ | |
7240 | gen_op_jz_ecx(s->aflag, l1); | |
7241 | break; | |
14ce26e7 FB |
7242 | } |
7243 | ||
6e0d8677 | 7244 | gen_set_label(l3); |
14ce26e7 | 7245 | gen_jmp_im(next_eip); |
8e1c85e3 | 7246 | tcg_gen_br(l2); |
6e0d8677 | 7247 | |
14ce26e7 FB |
7248 | gen_set_label(l1); |
7249 | gen_jmp_im(tval); | |
7250 | gen_set_label(l2); | |
7251 | gen_eob(s); | |
7252 | } | |
2c0262af FB |
7253 | break; |
7254 | case 0x130: /* wrmsr */ | |
7255 | case 0x132: /* rdmsr */ | |
7256 | if (s->cpl != 0) { | |
7257 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7258 | } else { | |
773cdfcc | 7259 | gen_update_cc_op(s); |
872929aa | 7260 | gen_jmp_im(pc_start - s->cs_base); |
0573fbfc | 7261 | if (b & 2) { |
4a7443be | 7262 | gen_helper_rdmsr(cpu_env); |
0573fbfc | 7263 | } else { |
4a7443be | 7264 | gen_helper_wrmsr(cpu_env); |
0573fbfc | 7265 | } |
2c0262af FB |
7266 | } |
7267 | break; | |
7268 | case 0x131: /* rdtsc */ | |
773cdfcc | 7269 | gen_update_cc_op(s); |
ecada8a2 | 7270 | gen_jmp_im(pc_start - s->cs_base); |
efade670 PB |
7271 | if (use_icount) |
7272 | gen_io_start(); | |
4a7443be | 7273 | gen_helper_rdtsc(cpu_env); |
efade670 PB |
7274 | if (use_icount) { |
7275 | gen_io_end(); | |
7276 | gen_jmp(s, s->pc - s->cs_base); | |
7277 | } | |
2c0262af | 7278 | break; |
df01e0fc | 7279 | case 0x133: /* rdpmc */ |
773cdfcc | 7280 | gen_update_cc_op(s); |
df01e0fc | 7281 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7282 | gen_helper_rdpmc(cpu_env); |
df01e0fc | 7283 | break; |
023fe10d | 7284 | case 0x134: /* sysenter */ |
2436b61a | 7285 | /* For Intel SYSENTER is valid on 64-bit */ |
0af10c86 | 7286 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 7287 | goto illegal_op; |
023fe10d FB |
7288 | if (!s->pe) { |
7289 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7290 | } else { | |
728d803b | 7291 | gen_update_cc_op(s); |
14ce26e7 | 7292 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7293 | gen_helper_sysenter(cpu_env); |
023fe10d FB |
7294 | gen_eob(s); |
7295 | } | |
7296 | break; | |
7297 | case 0x135: /* sysexit */ | |
2436b61a | 7298 | /* For Intel SYSEXIT is valid on 64-bit */ |
0af10c86 | 7299 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 7300 | goto illegal_op; |
023fe10d FB |
7301 | if (!s->pe) { |
7302 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7303 | } else { | |
728d803b | 7304 | gen_update_cc_op(s); |
14ce26e7 | 7305 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7306 | gen_helper_sysexit(cpu_env, tcg_const_i32(dflag)); |
023fe10d FB |
7307 | gen_eob(s); |
7308 | } | |
7309 | break; | |
14ce26e7 FB |
7310 | #ifdef TARGET_X86_64 |
7311 | case 0x105: /* syscall */ | |
7312 | /* XXX: is it usable in real mode ? */ | |
728d803b | 7313 | gen_update_cc_op(s); |
14ce26e7 | 7314 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7315 | gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start)); |
14ce26e7 FB |
7316 | gen_eob(s); |
7317 | break; | |
7318 | case 0x107: /* sysret */ | |
7319 | if (!s->pe) { | |
7320 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7321 | } else { | |
728d803b | 7322 | gen_update_cc_op(s); |
14ce26e7 | 7323 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7324 | gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag)); |
aba9d61e | 7325 | /* condition codes are modified only in long mode */ |
3ca51d07 RH |
7326 | if (s->lma) { |
7327 | set_cc_op(s, CC_OP_EFLAGS); | |
7328 | } | |
14ce26e7 FB |
7329 | gen_eob(s); |
7330 | } | |
7331 | break; | |
7332 | #endif | |
2c0262af | 7333 | case 0x1a2: /* cpuid */ |
773cdfcc | 7334 | gen_update_cc_op(s); |
9575cb94 | 7335 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7336 | gen_helper_cpuid(cpu_env); |
2c0262af FB |
7337 | break; |
7338 | case 0xf4: /* hlt */ | |
7339 | if (s->cpl != 0) { | |
7340 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7341 | } else { | |
773cdfcc | 7342 | gen_update_cc_op(s); |
94451178 | 7343 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7344 | gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); |
5779406a | 7345 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
7346 | } |
7347 | break; | |
7348 | case 0x100: | |
0af10c86 | 7349 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7350 | mod = (modrm >> 6) & 3; |
7351 | op = (modrm >> 3) & 7; | |
7352 | switch(op) { | |
7353 | case 0: /* sldt */ | |
f115e911 FB |
7354 | if (!s->pe || s->vm86) |
7355 | goto illegal_op; | |
872929aa | 7356 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); |
651ba608 | 7357 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); |
4ba9938c | 7358 | ot = MO_16; |
2c0262af FB |
7359 | if (mod == 3) |
7360 | ot += s->dflag; | |
0af10c86 | 7361 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
7362 | break; |
7363 | case 2: /* lldt */ | |
f115e911 FB |
7364 | if (!s->pe || s->vm86) |
7365 | goto illegal_op; | |
2c0262af FB |
7366 | if (s->cpl != 0) { |
7367 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7368 | } else { | |
872929aa | 7369 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); |
4ba9938c | 7370 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
14ce26e7 | 7371 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7372 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7373 | gen_helper_lldt(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7374 | } |
7375 | break; | |
7376 | case 1: /* str */ | |
f115e911 FB |
7377 | if (!s->pe || s->vm86) |
7378 | goto illegal_op; | |
872929aa | 7379 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); |
651ba608 | 7380 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); |
4ba9938c | 7381 | ot = MO_16; |
2c0262af FB |
7382 | if (mod == 3) |
7383 | ot += s->dflag; | |
0af10c86 | 7384 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
7385 | break; |
7386 | case 3: /* ltr */ | |
f115e911 FB |
7387 | if (!s->pe || s->vm86) |
7388 | goto illegal_op; | |
2c0262af FB |
7389 | if (s->cpl != 0) { |
7390 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7391 | } else { | |
872929aa | 7392 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); |
4ba9938c | 7393 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
14ce26e7 | 7394 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7395 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7396 | gen_helper_ltr(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7397 | } |
7398 | break; | |
7399 | case 4: /* verr */ | |
7400 | case 5: /* verw */ | |
f115e911 FB |
7401 | if (!s->pe || s->vm86) |
7402 | goto illegal_op; | |
4ba9938c | 7403 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
773cdfcc | 7404 | gen_update_cc_op(s); |
2999a0b2 BS |
7405 | if (op == 4) { |
7406 | gen_helper_verr(cpu_env, cpu_T[0]); | |
7407 | } else { | |
7408 | gen_helper_verw(cpu_env, cpu_T[0]); | |
7409 | } | |
3ca51d07 | 7410 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 7411 | break; |
2c0262af FB |
7412 | default: |
7413 | goto illegal_op; | |
7414 | } | |
7415 | break; | |
7416 | case 0x101: | |
0af10c86 | 7417 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7418 | mod = (modrm >> 6) & 3; |
7419 | op = (modrm >> 3) & 7; | |
3d7374c5 | 7420 | rm = modrm & 7; |
2c0262af FB |
7421 | switch(op) { |
7422 | case 0: /* sgdt */ | |
2c0262af FB |
7423 | if (mod == 3) |
7424 | goto illegal_op; | |
872929aa | 7425 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); |
4eeb3939 | 7426 | gen_lea_modrm(env, s, modrm); |
651ba608 | 7427 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); |
fd8ca9f6 | 7428 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
aba9d61e | 7429 | gen_add_A0_im(s, 2); |
651ba608 | 7430 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); |
2c0262af FB |
7431 | if (!s->dflag) |
7432 | gen_op_andl_T0_im(0xffffff); | |
fd8ca9f6 | 7433 | gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); |
2c0262af | 7434 | break; |
3d7374c5 FB |
7435 | case 1: |
7436 | if (mod == 3) { | |
7437 | switch (rm) { | |
7438 | case 0: /* monitor */ | |
7439 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7440 | s->cpl != 0) | |
7441 | goto illegal_op; | |
773cdfcc | 7442 | gen_update_cc_op(s); |
3d7374c5 FB |
7443 | gen_jmp_im(pc_start - s->cs_base); |
7444 | #ifdef TARGET_X86_64 | |
7445 | if (s->aflag == 2) { | |
bbf662ee | 7446 | gen_op_movq_A0_reg(R_EAX); |
5fafdf24 | 7447 | } else |
3d7374c5 FB |
7448 | #endif |
7449 | { | |
bbf662ee | 7450 | gen_op_movl_A0_reg(R_EAX); |
3d7374c5 FB |
7451 | if (s->aflag == 0) |
7452 | gen_op_andl_A0_ffff(); | |
7453 | } | |
7454 | gen_add_A0_ds_seg(s); | |
4a7443be | 7455 | gen_helper_monitor(cpu_env, cpu_A0); |
3d7374c5 FB |
7456 | break; |
7457 | case 1: /* mwait */ | |
7458 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7459 | s->cpl != 0) | |
7460 | goto illegal_op; | |
728d803b | 7461 | gen_update_cc_op(s); |
94451178 | 7462 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7463 | gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); |
3d7374c5 FB |
7464 | gen_eob(s); |
7465 | break; | |
a9321a4d PA |
7466 | case 2: /* clac */ |
7467 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7468 | s->cpl != 0) { | |
7469 | goto illegal_op; | |
7470 | } | |
7471 | gen_helper_clac(cpu_env); | |
7472 | gen_jmp_im(s->pc - s->cs_base); | |
7473 | gen_eob(s); | |
7474 | break; | |
7475 | case 3: /* stac */ | |
7476 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7477 | s->cpl != 0) { | |
7478 | goto illegal_op; | |
7479 | } | |
7480 | gen_helper_stac(cpu_env); | |
7481 | gen_jmp_im(s->pc - s->cs_base); | |
7482 | gen_eob(s); | |
7483 | break; | |
3d7374c5 FB |
7484 | default: |
7485 | goto illegal_op; | |
7486 | } | |
7487 | } else { /* sidt */ | |
872929aa | 7488 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); |
4eeb3939 | 7489 | gen_lea_modrm(env, s, modrm); |
651ba608 | 7490 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); |
fd8ca9f6 | 7491 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
3d7374c5 | 7492 | gen_add_A0_im(s, 2); |
651ba608 | 7493 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); |
3d7374c5 FB |
7494 | if (!s->dflag) |
7495 | gen_op_andl_T0_im(0xffffff); | |
fd8ca9f6 | 7496 | gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); |
3d7374c5 FB |
7497 | } |
7498 | break; | |
2c0262af FB |
7499 | case 2: /* lgdt */ |
7500 | case 3: /* lidt */ | |
0573fbfc | 7501 | if (mod == 3) { |
773cdfcc | 7502 | gen_update_cc_op(s); |
872929aa | 7503 | gen_jmp_im(pc_start - s->cs_base); |
0573fbfc TS |
7504 | switch(rm) { |
7505 | case 0: /* VMRUN */ | |
872929aa FB |
7506 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7507 | goto illegal_op; | |
7508 | if (s->cpl != 0) { | |
7509 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
0573fbfc | 7510 | break; |
872929aa | 7511 | } else { |
052e80d5 | 7512 | gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag), |
a7812ae4 | 7513 | tcg_const_i32(s->pc - pc_start)); |
db620f46 | 7514 | tcg_gen_exit_tb(0); |
5779406a | 7515 | s->is_jmp = DISAS_TB_JUMP; |
872929aa | 7516 | } |
0573fbfc TS |
7517 | break; |
7518 | case 1: /* VMMCALL */ | |
872929aa FB |
7519 | if (!(s->flags & HF_SVME_MASK)) |
7520 | goto illegal_op; | |
052e80d5 | 7521 | gen_helper_vmmcall(cpu_env); |
0573fbfc TS |
7522 | break; |
7523 | case 2: /* VMLOAD */ | |
872929aa FB |
7524 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7525 | goto illegal_op; | |
7526 | if (s->cpl != 0) { | |
7527 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7528 | break; | |
7529 | } else { | |
052e80d5 | 7530 | gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7531 | } |
0573fbfc TS |
7532 | break; |
7533 | case 3: /* VMSAVE */ | |
872929aa FB |
7534 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7535 | goto illegal_op; | |
7536 | if (s->cpl != 0) { | |
7537 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7538 | break; | |
7539 | } else { | |
052e80d5 | 7540 | gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7541 | } |
0573fbfc TS |
7542 | break; |
7543 | case 4: /* STGI */ | |
872929aa FB |
7544 | if ((!(s->flags & HF_SVME_MASK) && |
7545 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7546 | !s->pe) | |
7547 | goto illegal_op; | |
7548 | if (s->cpl != 0) { | |
7549 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7550 | break; | |
7551 | } else { | |
052e80d5 | 7552 | gen_helper_stgi(cpu_env); |
872929aa | 7553 | } |
0573fbfc TS |
7554 | break; |
7555 | case 5: /* CLGI */ | |
872929aa FB |
7556 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7557 | goto illegal_op; | |
7558 | if (s->cpl != 0) { | |
7559 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7560 | break; | |
7561 | } else { | |
052e80d5 | 7562 | gen_helper_clgi(cpu_env); |
872929aa | 7563 | } |
0573fbfc TS |
7564 | break; |
7565 | case 6: /* SKINIT */ | |
872929aa FB |
7566 | if ((!(s->flags & HF_SVME_MASK) && |
7567 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7568 | !s->pe) | |
7569 | goto illegal_op; | |
052e80d5 | 7570 | gen_helper_skinit(cpu_env); |
0573fbfc TS |
7571 | break; |
7572 | case 7: /* INVLPGA */ | |
872929aa FB |
7573 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7574 | goto illegal_op; | |
7575 | if (s->cpl != 0) { | |
7576 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7577 | break; | |
7578 | } else { | |
052e80d5 | 7579 | gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7580 | } |
0573fbfc TS |
7581 | break; |
7582 | default: | |
7583 | goto illegal_op; | |
7584 | } | |
7585 | } else if (s->cpl != 0) { | |
2c0262af FB |
7586 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7587 | } else { | |
872929aa FB |
7588 | gen_svm_check_intercept(s, pc_start, |
7589 | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); | |
4eeb3939 | 7590 | gen_lea_modrm(env, s, modrm); |
0f712e10 | 7591 | gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0); |
aba9d61e | 7592 | gen_add_A0_im(s, 2); |
909be183 | 7593 | gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); |
2c0262af FB |
7594 | if (!s->dflag) |
7595 | gen_op_andl_T0_im(0xffffff); | |
7596 | if (op == 2) { | |
651ba608 FB |
7597 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); |
7598 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); | |
2c0262af | 7599 | } else { |
651ba608 FB |
7600 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); |
7601 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); | |
2c0262af FB |
7602 | } |
7603 | } | |
7604 | break; | |
7605 | case 4: /* smsw */ | |
872929aa | 7606 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); |
e2542fe2 | 7607 | #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN |
f60d2728 | 7608 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); |
7609 | #else | |
651ba608 | 7610 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); |
f60d2728 | 7611 | #endif |
4ba9938c | 7612 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1); |
2c0262af FB |
7613 | break; |
7614 | case 6: /* lmsw */ | |
7615 | if (s->cpl != 0) { | |
7616 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7617 | } else { | |
872929aa | 7618 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
4ba9938c | 7619 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
4a7443be | 7620 | gen_helper_lmsw(cpu_env, cpu_T[0]); |
14ce26e7 | 7621 | gen_jmp_im(s->pc - s->cs_base); |
d71b9a8b | 7622 | gen_eob(s); |
2c0262af FB |
7623 | } |
7624 | break; | |
1b050077 AP |
7625 | case 7: |
7626 | if (mod != 3) { /* invlpg */ | |
7627 | if (s->cpl != 0) { | |
7628 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7629 | } else { | |
773cdfcc | 7630 | gen_update_cc_op(s); |
1b050077 | 7631 | gen_jmp_im(pc_start - s->cs_base); |
4eeb3939 | 7632 | gen_lea_modrm(env, s, modrm); |
4a7443be | 7633 | gen_helper_invlpg(cpu_env, cpu_A0); |
1b050077 AP |
7634 | gen_jmp_im(s->pc - s->cs_base); |
7635 | gen_eob(s); | |
7636 | } | |
2c0262af | 7637 | } else { |
1b050077 AP |
7638 | switch (rm) { |
7639 | case 0: /* swapgs */ | |
14ce26e7 | 7640 | #ifdef TARGET_X86_64 |
1b050077 AP |
7641 | if (CODE64(s)) { |
7642 | if (s->cpl != 0) { | |
7643 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7644 | } else { | |
7645 | tcg_gen_ld_tl(cpu_T[0], cpu_env, | |
7646 | offsetof(CPUX86State,segs[R_GS].base)); | |
7647 | tcg_gen_ld_tl(cpu_T[1], cpu_env, | |
7648 | offsetof(CPUX86State,kernelgsbase)); | |
7649 | tcg_gen_st_tl(cpu_T[1], cpu_env, | |
7650 | offsetof(CPUX86State,segs[R_GS].base)); | |
7651 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
7652 | offsetof(CPUX86State,kernelgsbase)); | |
7653 | } | |
5fafdf24 | 7654 | } else |
14ce26e7 FB |
7655 | #endif |
7656 | { | |
7657 | goto illegal_op; | |
7658 | } | |
1b050077 AP |
7659 | break; |
7660 | case 1: /* rdtscp */ | |
7661 | if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) | |
7662 | goto illegal_op; | |
773cdfcc | 7663 | gen_update_cc_op(s); |
9575cb94 | 7664 | gen_jmp_im(pc_start - s->cs_base); |
1b050077 AP |
7665 | if (use_icount) |
7666 | gen_io_start(); | |
4a7443be | 7667 | gen_helper_rdtscp(cpu_env); |
1b050077 AP |
7668 | if (use_icount) { |
7669 | gen_io_end(); | |
7670 | gen_jmp(s, s->pc - s->cs_base); | |
7671 | } | |
7672 | break; | |
7673 | default: | |
7674 | goto illegal_op; | |
14ce26e7 | 7675 | } |
2c0262af FB |
7676 | } |
7677 | break; | |
7678 | default: | |
7679 | goto illegal_op; | |
7680 | } | |
7681 | break; | |
3415a4dd FB |
7682 | case 0x108: /* invd */ |
7683 | case 0x109: /* wbinvd */ | |
7684 | if (s->cpl != 0) { | |
7685 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7686 | } else { | |
872929aa | 7687 | gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); |
3415a4dd FB |
7688 | /* nothing to do */ |
7689 | } | |
7690 | break; | |
14ce26e7 FB |
7691 | case 0x63: /* arpl or movslS (x86_64) */ |
7692 | #ifdef TARGET_X86_64 | |
7693 | if (CODE64(s)) { | |
7694 | int d_ot; | |
7695 | /* d_ot is the size of destination */ | |
4ba9938c | 7696 | d_ot = dflag + MO_16; |
14ce26e7 | 7697 | |
0af10c86 | 7698 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7699 | reg = ((modrm >> 3) & 7) | rex_r; |
7700 | mod = (modrm >> 6) & 3; | |
7701 | rm = (modrm & 7) | REX_B(s); | |
3b46e624 | 7702 | |
14ce26e7 | 7703 | if (mod == 3) { |
4ba9938c | 7704 | gen_op_mov_TN_reg(MO_32, 0, rm); |
14ce26e7 | 7705 | /* sign extend */ |
4ba9938c | 7706 | if (d_ot == MO_64) { |
e108dd01 | 7707 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 7708 | } |
57fec1fe | 7709 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7710 | } else { |
4eeb3939 | 7711 | gen_lea_modrm(env, s, modrm); |
4b1fe067 | 7712 | gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0); |
57fec1fe | 7713 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7714 | } |
5fafdf24 | 7715 | } else |
14ce26e7 FB |
7716 | #endif |
7717 | { | |
3bd7da9e | 7718 | int label1; |
49d9fdcc | 7719 | TCGv t0, t1, t2, a0; |
1e4840bf | 7720 | |
14ce26e7 FB |
7721 | if (!s->pe || s->vm86) |
7722 | goto illegal_op; | |
a7812ae4 PB |
7723 | t0 = tcg_temp_local_new(); |
7724 | t1 = tcg_temp_local_new(); | |
7725 | t2 = tcg_temp_local_new(); | |
4ba9938c | 7726 | ot = MO_16; |
0af10c86 | 7727 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7728 | reg = (modrm >> 3) & 7; |
7729 | mod = (modrm >> 6) & 3; | |
7730 | rm = modrm & 7; | |
7731 | if (mod != 3) { | |
4eeb3939 | 7732 | gen_lea_modrm(env, s, modrm); |
323d1876 | 7733 | gen_op_ld_v(s, ot, t0, cpu_A0); |
49d9fdcc LD |
7734 | a0 = tcg_temp_local_new(); |
7735 | tcg_gen_mov_tl(a0, cpu_A0); | |
14ce26e7 | 7736 | } else { |
1e4840bf | 7737 | gen_op_mov_v_reg(ot, t0, rm); |
49d9fdcc | 7738 | TCGV_UNUSED(a0); |
14ce26e7 | 7739 | } |
1e4840bf FB |
7740 | gen_op_mov_v_reg(ot, t1, reg); |
7741 | tcg_gen_andi_tl(cpu_tmp0, t0, 3); | |
7742 | tcg_gen_andi_tl(t1, t1, 3); | |
7743 | tcg_gen_movi_tl(t2, 0); | |
3bd7da9e | 7744 | label1 = gen_new_label(); |
1e4840bf FB |
7745 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); |
7746 | tcg_gen_andi_tl(t0, t0, ~3); | |
7747 | tcg_gen_or_tl(t0, t0, t1); | |
7748 | tcg_gen_movi_tl(t2, CC_Z); | |
3bd7da9e | 7749 | gen_set_label(label1); |
14ce26e7 | 7750 | if (mod != 3) { |
323d1876 | 7751 | gen_op_st_v(s, ot, t0, a0); |
49d9fdcc LD |
7752 | tcg_temp_free(a0); |
7753 | } else { | |
1e4840bf | 7754 | gen_op_mov_reg_v(ot, rm, t0); |
14ce26e7 | 7755 | } |
d229edce | 7756 | gen_compute_eflags(s); |
3bd7da9e | 7757 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); |
1e4840bf | 7758 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); |
1e4840bf FB |
7759 | tcg_temp_free(t0); |
7760 | tcg_temp_free(t1); | |
7761 | tcg_temp_free(t2); | |
f115e911 | 7762 | } |
f115e911 | 7763 | break; |
2c0262af FB |
7764 | case 0x102: /* lar */ |
7765 | case 0x103: /* lsl */ | |
cec6843e FB |
7766 | { |
7767 | int label1; | |
1e4840bf | 7768 | TCGv t0; |
cec6843e FB |
7769 | if (!s->pe || s->vm86) |
7770 | goto illegal_op; | |
4ba9938c | 7771 | ot = dflag ? MO_32 : MO_16; |
0af10c86 | 7772 | modrm = cpu_ldub_code(env, s->pc++); |
cec6843e | 7773 | reg = ((modrm >> 3) & 7) | rex_r; |
4ba9938c | 7774 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
a7812ae4 | 7775 | t0 = tcg_temp_local_new(); |
773cdfcc | 7776 | gen_update_cc_op(s); |
2999a0b2 BS |
7777 | if (b == 0x102) { |
7778 | gen_helper_lar(t0, cpu_env, cpu_T[0]); | |
7779 | } else { | |
7780 | gen_helper_lsl(t0, cpu_env, cpu_T[0]); | |
7781 | } | |
cec6843e FB |
7782 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); |
7783 | label1 = gen_new_label(); | |
cb63669a | 7784 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
1e4840bf | 7785 | gen_op_mov_reg_v(ot, reg, t0); |
cec6843e | 7786 | gen_set_label(label1); |
3ca51d07 | 7787 | set_cc_op(s, CC_OP_EFLAGS); |
1e4840bf | 7788 | tcg_temp_free(t0); |
cec6843e | 7789 | } |
2c0262af FB |
7790 | break; |
7791 | case 0x118: | |
0af10c86 | 7792 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7793 | mod = (modrm >> 6) & 3; |
7794 | op = (modrm >> 3) & 7; | |
7795 | switch(op) { | |
7796 | case 0: /* prefetchnta */ | |
7797 | case 1: /* prefetchnt0 */ | |
7798 | case 2: /* prefetchnt0 */ | |
7799 | case 3: /* prefetchnt0 */ | |
7800 | if (mod == 3) | |
7801 | goto illegal_op; | |
4eeb3939 | 7802 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
7803 | /* nothing more to do */ |
7804 | break; | |
e17a36ce | 7805 | default: /* nop (multi byte) */ |
0af10c86 | 7806 | gen_nop_modrm(env, s, modrm); |
e17a36ce | 7807 | break; |
2c0262af FB |
7808 | } |
7809 | break; | |
e17a36ce | 7810 | case 0x119 ... 0x11f: /* nop (multi byte) */ |
0af10c86 BS |
7811 | modrm = cpu_ldub_code(env, s->pc++); |
7812 | gen_nop_modrm(env, s, modrm); | |
e17a36ce | 7813 | break; |
2c0262af FB |
7814 | case 0x120: /* mov reg, crN */ |
7815 | case 0x122: /* mov crN, reg */ | |
7816 | if (s->cpl != 0) { | |
7817 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7818 | } else { | |
0af10c86 | 7819 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7820 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7821 | * AMD documentation (24594.pdf) and testing of | |
7822 | * intel 386 and 486 processors all show that the mod bits | |
7823 | * are assumed to be 1's, regardless of actual values. | |
7824 | */ | |
14ce26e7 FB |
7825 | rm = (modrm & 7) | REX_B(s); |
7826 | reg = ((modrm >> 3) & 7) | rex_r; | |
7827 | if (CODE64(s)) | |
4ba9938c | 7828 | ot = MO_64; |
14ce26e7 | 7829 | else |
4ba9938c | 7830 | ot = MO_32; |
ccd59d09 AP |
7831 | if ((prefixes & PREFIX_LOCK) && (reg == 0) && |
7832 | (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { | |
7833 | reg = 8; | |
7834 | } | |
2c0262af FB |
7835 | switch(reg) { |
7836 | case 0: | |
7837 | case 2: | |
7838 | case 3: | |
7839 | case 4: | |
9230e66e | 7840 | case 8: |
773cdfcc | 7841 | gen_update_cc_op(s); |
872929aa | 7842 | gen_jmp_im(pc_start - s->cs_base); |
2c0262af | 7843 | if (b & 2) { |
57fec1fe | 7844 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be BS |
7845 | gen_helper_write_crN(cpu_env, tcg_const_i32(reg), |
7846 | cpu_T[0]); | |
14ce26e7 | 7847 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7848 | gen_eob(s); |
7849 | } else { | |
4a7443be | 7850 | gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg)); |
57fec1fe | 7851 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7852 | } |
7853 | break; | |
7854 | default: | |
7855 | goto illegal_op; | |
7856 | } | |
7857 | } | |
7858 | break; | |
7859 | case 0x121: /* mov reg, drN */ | |
7860 | case 0x123: /* mov drN, reg */ | |
7861 | if (s->cpl != 0) { | |
7862 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7863 | } else { | |
0af10c86 | 7864 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7865 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7866 | * AMD documentation (24594.pdf) and testing of | |
7867 | * intel 386 and 486 processors all show that the mod bits | |
7868 | * are assumed to be 1's, regardless of actual values. | |
7869 | */ | |
14ce26e7 FB |
7870 | rm = (modrm & 7) | REX_B(s); |
7871 | reg = ((modrm >> 3) & 7) | rex_r; | |
7872 | if (CODE64(s)) | |
4ba9938c | 7873 | ot = MO_64; |
14ce26e7 | 7874 | else |
4ba9938c | 7875 | ot = MO_32; |
2c0262af | 7876 | /* XXX: do it dynamically with CR4.DE bit */ |
14ce26e7 | 7877 | if (reg == 4 || reg == 5 || reg >= 8) |
2c0262af FB |
7878 | goto illegal_op; |
7879 | if (b & 2) { | |
0573fbfc | 7880 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
57fec1fe | 7881 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be | 7882 | gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7883 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7884 | gen_eob(s); |
7885 | } else { | |
0573fbfc | 7886 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
651ba608 | 7887 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); |
57fec1fe | 7888 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7889 | } |
7890 | } | |
7891 | break; | |
7892 | case 0x106: /* clts */ | |
7893 | if (s->cpl != 0) { | |
7894 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7895 | } else { | |
0573fbfc | 7896 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
f0967a1a | 7897 | gen_helper_clts(cpu_env); |
7eee2a50 | 7898 | /* abort block because static cpu state changed */ |
14ce26e7 | 7899 | gen_jmp_im(s->pc - s->cs_base); |
7eee2a50 | 7900 | gen_eob(s); |
2c0262af FB |
7901 | } |
7902 | break; | |
222a3336 | 7903 | /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ |
664e0f19 FB |
7904 | case 0x1c3: /* MOVNTI reg, mem */ |
7905 | if (!(s->cpuid_features & CPUID_SSE2)) | |
14ce26e7 | 7906 | goto illegal_op; |
4ba9938c | 7907 | ot = s->dflag == 2 ? MO_64 : MO_32; |
0af10c86 | 7908 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7909 | mod = (modrm >> 6) & 3; |
7910 | if (mod == 3) | |
7911 | goto illegal_op; | |
7912 | reg = ((modrm >> 3) & 7) | rex_r; | |
7913 | /* generate a generic store */ | |
0af10c86 | 7914 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
14ce26e7 | 7915 | break; |
664e0f19 | 7916 | case 0x1ae: |
0af10c86 | 7917 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7918 | mod = (modrm >> 6) & 3; |
7919 | op = (modrm >> 3) & 7; | |
7920 | switch(op) { | |
7921 | case 0: /* fxsave */ | |
5fafdf24 | 7922 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7923 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7924 | goto illegal_op; |
09d85fb8 | 7925 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7926 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7927 | break; | |
7928 | } | |
4eeb3939 | 7929 | gen_lea_modrm(env, s, modrm); |
773cdfcc | 7930 | gen_update_cc_op(s); |
19e6c4b8 | 7931 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 7932 | gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2))); |
664e0f19 FB |
7933 | break; |
7934 | case 1: /* fxrstor */ | |
5fafdf24 | 7935 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7936 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7937 | goto illegal_op; |
09d85fb8 | 7938 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7939 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7940 | break; | |
7941 | } | |
4eeb3939 | 7942 | gen_lea_modrm(env, s, modrm); |
773cdfcc | 7943 | gen_update_cc_op(s); |
19e6c4b8 | 7944 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
7945 | gen_helper_fxrstor(cpu_env, cpu_A0, |
7946 | tcg_const_i32((s->dflag == 2))); | |
664e0f19 FB |
7947 | break; |
7948 | case 2: /* ldmxcsr */ | |
7949 | case 3: /* stmxcsr */ | |
7950 | if (s->flags & HF_TS_MASK) { | |
7951 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7952 | break; | |
14ce26e7 | 7953 | } |
664e0f19 FB |
7954 | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) || |
7955 | mod == 3) | |
14ce26e7 | 7956 | goto illegal_op; |
4eeb3939 | 7957 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 7958 | if (op == 2) { |
909be183 | 7959 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
20f8bd48 | 7960 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 7961 | gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); |
14ce26e7 | 7962 | } else { |
651ba608 | 7963 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
fd8ca9f6 | 7964 | gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); |
14ce26e7 | 7965 | } |
664e0f19 FB |
7966 | break; |
7967 | case 5: /* lfence */ | |
7968 | case 6: /* mfence */ | |
8001c294 | 7969 | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) |
664e0f19 FB |
7970 | goto illegal_op; |
7971 | break; | |
8f091a59 FB |
7972 | case 7: /* sfence / clflush */ |
7973 | if ((modrm & 0xc7) == 0xc0) { | |
7974 | /* sfence */ | |
a35f3ec7 | 7975 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */ |
8f091a59 FB |
7976 | if (!(s->cpuid_features & CPUID_SSE)) |
7977 | goto illegal_op; | |
7978 | } else { | |
7979 | /* clflush */ | |
7980 | if (!(s->cpuid_features & CPUID_CLFLUSH)) | |
7981 | goto illegal_op; | |
4eeb3939 | 7982 | gen_lea_modrm(env, s, modrm); |
8f091a59 FB |
7983 | } |
7984 | break; | |
664e0f19 | 7985 | default: |
14ce26e7 FB |
7986 | goto illegal_op; |
7987 | } | |
7988 | break; | |
a35f3ec7 | 7989 | case 0x10d: /* 3DNow! prefetch(w) */ |
0af10c86 | 7990 | modrm = cpu_ldub_code(env, s->pc++); |
a35f3ec7 AJ |
7991 | mod = (modrm >> 6) & 3; |
7992 | if (mod == 3) | |
7993 | goto illegal_op; | |
4eeb3939 | 7994 | gen_lea_modrm(env, s, modrm); |
8f091a59 FB |
7995 | /* ignore for now */ |
7996 | break; | |
3b21e03e | 7997 | case 0x1aa: /* rsm */ |
872929aa | 7998 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); |
3b21e03e FB |
7999 | if (!(s->flags & HF_SMM_MASK)) |
8000 | goto illegal_op; | |
728d803b | 8001 | gen_update_cc_op(s); |
3b21e03e | 8002 | gen_jmp_im(s->pc - s->cs_base); |
608badfc | 8003 | gen_helper_rsm(cpu_env); |
3b21e03e FB |
8004 | gen_eob(s); |
8005 | break; | |
222a3336 AZ |
8006 | case 0x1b8: /* SSE4.2 popcnt */ |
8007 | if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != | |
8008 | PREFIX_REPZ) | |
8009 | goto illegal_op; | |
8010 | if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) | |
8011 | goto illegal_op; | |
8012 | ||
0af10c86 | 8013 | modrm = cpu_ldub_code(env, s->pc++); |
8b4a3df8 | 8014 | reg = ((modrm >> 3) & 7) | rex_r; |
222a3336 AZ |
8015 | |
8016 | if (s->prefix & PREFIX_DATA) | |
4ba9938c | 8017 | ot = MO_16; |
222a3336 | 8018 | else if (s->dflag != 2) |
4ba9938c | 8019 | ot = MO_32; |
222a3336 | 8020 | else |
4ba9938c | 8021 | ot = MO_64; |
222a3336 | 8022 | |
0af10c86 | 8023 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
d3eb5eae | 8024 | gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot)); |
222a3336 | 8025 | gen_op_mov_reg_T0(ot, reg); |
fdb0d09d | 8026 | |
3ca51d07 | 8027 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 | 8028 | break; |
a35f3ec7 AJ |
8029 | case 0x10e ... 0x10f: |
8030 | /* 3DNow! instructions, ignore prefixes */ | |
8031 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); | |
664e0f19 FB |
8032 | case 0x110 ... 0x117: |
8033 | case 0x128 ... 0x12f: | |
4242b1bd | 8034 | case 0x138 ... 0x13a: |
d9f4bb27 | 8035 | case 0x150 ... 0x179: |
664e0f19 FB |
8036 | case 0x17c ... 0x17f: |
8037 | case 0x1c2: | |
8038 | case 0x1c4 ... 0x1c6: | |
8039 | case 0x1d0 ... 0x1fe: | |
0af10c86 | 8040 | gen_sse(env, s, b, pc_start, rex_r); |
664e0f19 | 8041 | break; |
2c0262af FB |
8042 | default: |
8043 | goto illegal_op; | |
8044 | } | |
8045 | /* lock generation */ | |
8046 | if (s->prefix & PREFIX_LOCK) | |
a7812ae4 | 8047 | gen_helper_unlock(); |
2c0262af FB |
8048 | return s->pc; |
8049 | illegal_op: | |
ab1f142b | 8050 | if (s->prefix & PREFIX_LOCK) |
a7812ae4 | 8051 | gen_helper_unlock(); |
2c0262af FB |
8052 | /* XXX: ensure that no lock was generated */ |
8053 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
8054 | return s->pc; | |
8055 | } | |
8056 | ||
2c0262af FB |
8057 | void optimize_flags_init(void) |
8058 | { | |
a7812ae4 PB |
8059 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
8060 | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 | 8061 | offsetof(CPUX86State, cc_op), "cc_op"); |
317ac620 | 8062 | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst), |
a7812ae4 | 8063 | "cc_dst"); |
a3251186 RH |
8064 | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src), |
8065 | "cc_src"); | |
988c3eb0 RH |
8066 | cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src2), |
8067 | "cc_src2"); | |
437a88a5 | 8068 | |
cc739bb0 LD |
8069 | #ifdef TARGET_X86_64 |
8070 | cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0, | |
317ac620 | 8071 | offsetof(CPUX86State, regs[R_EAX]), "rax"); |
cc739bb0 | 8072 | cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8073 | offsetof(CPUX86State, regs[R_ECX]), "rcx"); |
cc739bb0 | 8074 | cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8075 | offsetof(CPUX86State, regs[R_EDX]), "rdx"); |
cc739bb0 | 8076 | cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8077 | offsetof(CPUX86State, regs[R_EBX]), "rbx"); |
cc739bb0 | 8078 | cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8079 | offsetof(CPUX86State, regs[R_ESP]), "rsp"); |
cc739bb0 | 8080 | cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8081 | offsetof(CPUX86State, regs[R_EBP]), "rbp"); |
cc739bb0 | 8082 | cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8083 | offsetof(CPUX86State, regs[R_ESI]), "rsi"); |
cc739bb0 | 8084 | cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8085 | offsetof(CPUX86State, regs[R_EDI]), "rdi"); |
cc739bb0 | 8086 | cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8087 | offsetof(CPUX86State, regs[8]), "r8"); |
cc739bb0 | 8088 | cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8089 | offsetof(CPUX86State, regs[9]), "r9"); |
cc739bb0 | 8090 | cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8091 | offsetof(CPUX86State, regs[10]), "r10"); |
cc739bb0 | 8092 | cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8093 | offsetof(CPUX86State, regs[11]), "r11"); |
cc739bb0 | 8094 | cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8095 | offsetof(CPUX86State, regs[12]), "r12"); |
cc739bb0 | 8096 | cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8097 | offsetof(CPUX86State, regs[13]), "r13"); |
cc739bb0 | 8098 | cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8099 | offsetof(CPUX86State, regs[14]), "r14"); |
cc739bb0 | 8100 | cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 8101 | offsetof(CPUX86State, regs[15]), "r15"); |
cc739bb0 LD |
8102 | #else |
8103 | cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 | 8104 | offsetof(CPUX86State, regs[R_EAX]), "eax"); |
cc739bb0 | 8105 | cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 8106 | offsetof(CPUX86State, regs[R_ECX]), "ecx"); |
cc739bb0 | 8107 | cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 8108 | offsetof(CPUX86State, regs[R_EDX]), "edx"); |
cc739bb0 | 8109 | cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 8110 | offsetof(CPUX86State, regs[R_EBX]), "ebx"); |
cc739bb0 | 8111 | cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 8112 | offsetof(CPUX86State, regs[R_ESP]), "esp"); |
cc739bb0 | 8113 | cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 8114 | offsetof(CPUX86State, regs[R_EBP]), "ebp"); |
cc739bb0 | 8115 | cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 8116 | offsetof(CPUX86State, regs[R_ESI]), "esi"); |
cc739bb0 | 8117 | cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 8118 | offsetof(CPUX86State, regs[R_EDI]), "edi"); |
cc739bb0 | 8119 | #endif |
2c0262af FB |
8120 | } |
8121 | ||
8122 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for | |
8123 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
8124 | information for each intermediate instruction. */ | |
467215c2 | 8125 | static inline void gen_intermediate_code_internal(X86CPU *cpu, |
2cfc5f17 | 8126 | TranslationBlock *tb, |
467215c2 | 8127 | bool search_pc) |
2c0262af | 8128 | { |
ed2803da | 8129 | CPUState *cs = CPU(cpu); |
467215c2 | 8130 | CPUX86State *env = &cpu->env; |
2c0262af | 8131 | DisasContext dc1, *dc = &dc1; |
14ce26e7 | 8132 | target_ulong pc_ptr; |
2c0262af | 8133 | uint16_t *gen_opc_end; |
a1d1bb31 | 8134 | CPUBreakpoint *bp; |
7f5b7d3e | 8135 | int j, lj; |
c068688b | 8136 | uint64_t flags; |
14ce26e7 FB |
8137 | target_ulong pc_start; |
8138 | target_ulong cs_base; | |
2e70f6ef PB |
8139 | int num_insns; |
8140 | int max_insns; | |
3b46e624 | 8141 | |
2c0262af | 8142 | /* generate intermediate code */ |
14ce26e7 FB |
8143 | pc_start = tb->pc; |
8144 | cs_base = tb->cs_base; | |
2c0262af | 8145 | flags = tb->flags; |
3a1d9b8b | 8146 | |
4f31916f | 8147 | dc->pe = (flags >> HF_PE_SHIFT) & 1; |
2c0262af FB |
8148 | dc->code32 = (flags >> HF_CS32_SHIFT) & 1; |
8149 | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; | |
8150 | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; | |
8151 | dc->f_st = 0; | |
8152 | dc->vm86 = (flags >> VM_SHIFT) & 1; | |
8153 | dc->cpl = (flags >> HF_CPL_SHIFT) & 3; | |
8154 | dc->iopl = (flags >> IOPL_SHIFT) & 3; | |
8155 | dc->tf = (flags >> TF_SHIFT) & 1; | |
ed2803da | 8156 | dc->singlestep_enabled = cs->singlestep_enabled; |
2c0262af | 8157 | dc->cc_op = CC_OP_DYNAMIC; |
e207582f | 8158 | dc->cc_op_dirty = false; |
2c0262af FB |
8159 | dc->cs_base = cs_base; |
8160 | dc->tb = tb; | |
8161 | dc->popl_esp_hack = 0; | |
8162 | /* select memory access functions */ | |
8163 | dc->mem_index = 0; | |
8164 | if (flags & HF_SOFTMMU_MASK) { | |
5c42a7cd | 8165 | dc->mem_index = cpu_mmu_index(env); |
2c0262af | 8166 | } |
0514ef2f EH |
8167 | dc->cpuid_features = env->features[FEAT_1_EDX]; |
8168 | dc->cpuid_ext_features = env->features[FEAT_1_ECX]; | |
8169 | dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX]; | |
8170 | dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX]; | |
8171 | dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX]; | |
14ce26e7 FB |
8172 | #ifdef TARGET_X86_64 |
8173 | dc->lma = (flags >> HF_LMA_SHIFT) & 1; | |
8174 | dc->code64 = (flags >> HF_CS64_SHIFT) & 1; | |
8175 | #endif | |
7eee2a50 | 8176 | dc->flags = flags; |
ed2803da | 8177 | dc->jmp_opt = !(dc->tf || cs->singlestep_enabled || |
a2cc3b24 | 8178 | (flags & HF_INHIBIT_IRQ_MASK) |
415fa2ea | 8179 | #ifndef CONFIG_SOFTMMU |
2c0262af FB |
8180 | || (flags & HF_SOFTMMU_MASK) |
8181 | #endif | |
8182 | ); | |
4f31916f FB |
8183 | #if 0 |
8184 | /* check addseg logic */ | |
dc196a57 | 8185 | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) |
4f31916f FB |
8186 | printf("ERROR addseg\n"); |
8187 | #endif | |
8188 | ||
a7812ae4 PB |
8189 | cpu_T[0] = tcg_temp_new(); |
8190 | cpu_T[1] = tcg_temp_new(); | |
8191 | cpu_A0 = tcg_temp_new(); | |
a7812ae4 PB |
8192 | |
8193 | cpu_tmp0 = tcg_temp_new(); | |
8194 | cpu_tmp1_i64 = tcg_temp_new_i64(); | |
8195 | cpu_tmp2_i32 = tcg_temp_new_i32(); | |
8196 | cpu_tmp3_i32 = tcg_temp_new_i32(); | |
8197 | cpu_tmp4 = tcg_temp_new(); | |
a7812ae4 PB |
8198 | cpu_ptr0 = tcg_temp_new_ptr(); |
8199 | cpu_ptr1 = tcg_temp_new_ptr(); | |
a3251186 | 8200 | cpu_cc_srcT = tcg_temp_local_new(); |
57fec1fe | 8201 | |
92414b31 | 8202 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
8203 | |
8204 | dc->is_jmp = DISAS_NEXT; | |
8205 | pc_ptr = pc_start; | |
8206 | lj = -1; | |
2e70f6ef PB |
8207 | num_insns = 0; |
8208 | max_insns = tb->cflags & CF_COUNT_MASK; | |
8209 | if (max_insns == 0) | |
8210 | max_insns = CF_COUNT_MASK; | |
2c0262af | 8211 | |
806f352d | 8212 | gen_tb_start(); |
2c0262af | 8213 | for(;;) { |
72cf2d4f BS |
8214 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
8215 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a2397807 JK |
8216 | if (bp->pc == pc_ptr && |
8217 | !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { | |
2c0262af FB |
8218 | gen_debug(dc, pc_ptr - dc->cs_base); |
8219 | break; | |
8220 | } | |
8221 | } | |
8222 | } | |
8223 | if (search_pc) { | |
92414b31 | 8224 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
8225 | if (lj < j) { |
8226 | lj++; | |
8227 | while (lj < j) | |
ab1103de | 8228 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 8229 | } |
25983cad | 8230 | tcg_ctx.gen_opc_pc[lj] = pc_ptr; |
2c0262af | 8231 | gen_opc_cc_op[lj] = dc->cc_op; |
ab1103de | 8232 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 8233 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
2c0262af | 8234 | } |
2e70f6ef PB |
8235 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
8236 | gen_io_start(); | |
8237 | ||
0af10c86 | 8238 | pc_ptr = disas_insn(env, dc, pc_ptr); |
2e70f6ef | 8239 | num_insns++; |
2c0262af FB |
8240 | /* stop translation if indicated */ |
8241 | if (dc->is_jmp) | |
8242 | break; | |
8243 | /* if single step mode, we generate only one instruction and | |
8244 | generate an exception */ | |
a2cc3b24 FB |
8245 | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear |
8246 | the flag and abort the translation to give the irqs a | |
8247 | change to be happen */ | |
5fafdf24 | 8248 | if (dc->tf || dc->singlestep_enabled || |
2e70f6ef | 8249 | (flags & HF_INHIBIT_IRQ_MASK)) { |
14ce26e7 | 8250 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
8251 | gen_eob(dc); |
8252 | break; | |
8253 | } | |
8254 | /* if too long translation, stop generation too */ | |
efd7f486 | 8255 | if (tcg_ctx.gen_opc_ptr >= gen_opc_end || |
2e70f6ef PB |
8256 | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || |
8257 | num_insns >= max_insns) { | |
14ce26e7 | 8258 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
8259 | gen_eob(dc); |
8260 | break; | |
8261 | } | |
1b530a6d AJ |
8262 | if (singlestep) { |
8263 | gen_jmp_im(pc_ptr - dc->cs_base); | |
8264 | gen_eob(dc); | |
8265 | break; | |
8266 | } | |
2c0262af | 8267 | } |
2e70f6ef PB |
8268 | if (tb->cflags & CF_LAST_IO) |
8269 | gen_io_end(); | |
806f352d | 8270 | gen_tb_end(tb, num_insns); |
efd7f486 | 8271 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
2c0262af FB |
8272 | /* we don't forget to fill the last values */ |
8273 | if (search_pc) { | |
92414b31 | 8274 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
8275 | lj++; |
8276 | while (lj <= j) | |
ab1103de | 8277 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 8278 | } |
3b46e624 | 8279 | |
2c0262af | 8280 | #ifdef DEBUG_DISAS |
8fec2b8c | 8281 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
14ce26e7 | 8282 | int disas_flags; |
93fcfe39 AL |
8283 | qemu_log("----------------\n"); |
8284 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
14ce26e7 FB |
8285 | #ifdef TARGET_X86_64 |
8286 | if (dc->code64) | |
8287 | disas_flags = 2; | |
8288 | else | |
8289 | #endif | |
8290 | disas_flags = !dc->code32; | |
f4359b9f | 8291 | log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags); |
93fcfe39 | 8292 | qemu_log("\n"); |
2c0262af FB |
8293 | } |
8294 | #endif | |
8295 | ||
2e70f6ef | 8296 | if (!search_pc) { |
2c0262af | 8297 | tb->size = pc_ptr - pc_start; |
2e70f6ef PB |
8298 | tb->icount = num_insns; |
8299 | } | |
2c0262af FB |
8300 | } |
8301 | ||
317ac620 | 8302 | void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 8303 | { |
467215c2 | 8304 | gen_intermediate_code_internal(x86_env_get_cpu(env), tb, false); |
2c0262af FB |
8305 | } |
8306 | ||
317ac620 | 8307 | void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 8308 | { |
467215c2 | 8309 | gen_intermediate_code_internal(x86_env_get_cpu(env), tb, true); |
2c0262af FB |
8310 | } |
8311 | ||
317ac620 | 8312 | void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos) |
d2856f1a AJ |
8313 | { |
8314 | int cc_op; | |
8315 | #ifdef DEBUG_DISAS | |
8fec2b8c | 8316 | if (qemu_loglevel_mask(CPU_LOG_TB_OP)) { |
d2856f1a | 8317 | int i; |
93fcfe39 | 8318 | qemu_log("RESTORE:\n"); |
d2856f1a | 8319 | for(i = 0;i <= pc_pos; i++) { |
ab1103de | 8320 | if (tcg_ctx.gen_opc_instr_start[i]) { |
25983cad EV |
8321 | qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, |
8322 | tcg_ctx.gen_opc_pc[i]); | |
d2856f1a AJ |
8323 | } |
8324 | } | |
e87b7cb0 | 8325 | qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
25983cad | 8326 | pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base, |
d2856f1a AJ |
8327 | (uint32_t)tb->cs_base); |
8328 | } | |
8329 | #endif | |
25983cad | 8330 | env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base; |
d2856f1a AJ |
8331 | cc_op = gen_opc_cc_op[pc_pos]; |
8332 | if (cc_op != CC_OP_DYNAMIC) | |
8333 | env->cc_op = cc_op; | |
8334 | } |