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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 translation | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
2c0262af FB |
25 | |
26 | #include "cpu.h" | |
76cad711 | 27 | #include "disas/disas.h" |
57fec1fe | 28 | #include "tcg-op.h" |
2c0262af | 29 | |
a7812ae4 PB |
30 | #include "helper.h" |
31 | #define GEN_HELPER 1 | |
32 | #include "helper.h" | |
33 | ||
2c0262af FB |
34 | #define PREFIX_REPZ 0x01 |
35 | #define PREFIX_REPNZ 0x02 | |
36 | #define PREFIX_LOCK 0x04 | |
37 | #define PREFIX_DATA 0x08 | |
38 | #define PREFIX_ADR 0x10 | |
39 | ||
14ce26e7 | 40 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
41 | #define CODE64(s) ((s)->code64) |
42 | #define REX_X(s) ((s)->rex_x) | |
43 | #define REX_B(s) ((s)->rex_b) | |
14ce26e7 | 44 | #else |
14ce26e7 FB |
45 | #define CODE64(s) 0 |
46 | #define REX_X(s) 0 | |
47 | #define REX_B(s) 0 | |
48 | #endif | |
49 | ||
57fec1fe FB |
50 | //#define MACRO_TEST 1 |
51 | ||
57fec1fe | 52 | /* global register indexes */ |
a7812ae4 | 53 | static TCGv_ptr cpu_env; |
f5847c91 | 54 | static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst; |
a7812ae4 | 55 | static TCGv_i32 cpu_cc_op; |
cc739bb0 | 56 | static TCGv cpu_regs[CPU_NB_REGS]; |
1e4840bf FB |
57 | /* local temps */ |
58 | static TCGv cpu_T[2], cpu_T3; | |
57fec1fe | 59 | /* local register indexes (only used inside old micro ops) */ |
a7812ae4 PB |
60 | static TCGv cpu_tmp0, cpu_tmp4; |
61 | static TCGv_ptr cpu_ptr0, cpu_ptr1; | |
62 | static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; | |
63 | static TCGv_i64 cpu_tmp1_i64; | |
bedda79c | 64 | static TCGv cpu_tmp5; |
57fec1fe | 65 | |
1a7ff922 PB |
66 | static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
67 | ||
022c62cb | 68 | #include "exec/gen-icount.h" |
2e70f6ef | 69 | |
57fec1fe FB |
70 | #ifdef TARGET_X86_64 |
71 | static int x86_64_hregs; | |
ae063a68 FB |
72 | #endif |
73 | ||
2c0262af FB |
74 | typedef struct DisasContext { |
75 | /* current insn context */ | |
76 | int override; /* -1 if no override */ | |
77 | int prefix; | |
78 | int aflag, dflag; | |
14ce26e7 | 79 | target_ulong pc; /* pc = eip + cs_base */ |
2c0262af FB |
80 | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
81 | static state change (stop translation) */ | |
82 | /* current block context */ | |
14ce26e7 | 83 | target_ulong cs_base; /* base of CS segment */ |
2c0262af FB |
84 | int pe; /* protected mode */ |
85 | int code32; /* 32 bit code segment */ | |
14ce26e7 FB |
86 | #ifdef TARGET_X86_64 |
87 | int lma; /* long mode active */ | |
88 | int code64; /* 64 bit code segment */ | |
89 | int rex_x, rex_b; | |
90 | #endif | |
2c0262af | 91 | int ss32; /* 32 bit stack segment */ |
fee71888 | 92 | CCOp cc_op; /* current CC operation */ |
e207582f | 93 | bool cc_op_dirty; |
2c0262af FB |
94 | int addseg; /* non zero if either DS/ES/SS have a non zero base */ |
95 | int f_st; /* currently unused */ | |
96 | int vm86; /* vm86 mode */ | |
97 | int cpl; | |
98 | int iopl; | |
99 | int tf; /* TF cpu flag */ | |
34865134 | 100 | int singlestep_enabled; /* "hardware" single step enabled */ |
2c0262af FB |
101 | int jmp_opt; /* use direct block chaining for direct jumps */ |
102 | int mem_index; /* select memory access functions */ | |
c068688b | 103 | uint64_t flags; /* all execution flags */ |
2c0262af FB |
104 | struct TranslationBlock *tb; |
105 | int popl_esp_hack; /* for correct popl with esp base handling */ | |
14ce26e7 FB |
106 | int rip_offset; /* only used in x86_64, but left for simplicity */ |
107 | int cpuid_features; | |
3d7374c5 | 108 | int cpuid_ext_features; |
e771edab | 109 | int cpuid_ext2_features; |
12e26b75 | 110 | int cpuid_ext3_features; |
a9321a4d | 111 | int cpuid_7_0_ebx_features; |
2c0262af FB |
112 | } DisasContext; |
113 | ||
114 | static void gen_eob(DisasContext *s); | |
14ce26e7 FB |
115 | static void gen_jmp(DisasContext *s, target_ulong eip); |
116 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); | |
2c0262af FB |
117 | |
118 | /* i386 arith/logic operations */ | |
119 | enum { | |
5fafdf24 TS |
120 | OP_ADDL, |
121 | OP_ORL, | |
122 | OP_ADCL, | |
2c0262af | 123 | OP_SBBL, |
5fafdf24 TS |
124 | OP_ANDL, |
125 | OP_SUBL, | |
126 | OP_XORL, | |
2c0262af FB |
127 | OP_CMPL, |
128 | }; | |
129 | ||
130 | /* i386 shift ops */ | |
131 | enum { | |
5fafdf24 TS |
132 | OP_ROL, |
133 | OP_ROR, | |
134 | OP_RCL, | |
135 | OP_RCR, | |
136 | OP_SHL, | |
137 | OP_SHR, | |
2c0262af FB |
138 | OP_SHL1, /* undocumented */ |
139 | OP_SAR = 7, | |
140 | }; | |
141 | ||
8e1c85e3 FB |
142 | enum { |
143 | JCC_O, | |
144 | JCC_B, | |
145 | JCC_Z, | |
146 | JCC_BE, | |
147 | JCC_S, | |
148 | JCC_P, | |
149 | JCC_L, | |
150 | JCC_LE, | |
151 | }; | |
152 | ||
2c0262af FB |
153 | /* operand size */ |
154 | enum { | |
155 | OT_BYTE = 0, | |
156 | OT_WORD, | |
5fafdf24 | 157 | OT_LONG, |
2c0262af FB |
158 | OT_QUAD, |
159 | }; | |
160 | ||
161 | enum { | |
162 | /* I386 int registers */ | |
163 | OR_EAX, /* MUST be even numbered */ | |
164 | OR_ECX, | |
165 | OR_EDX, | |
166 | OR_EBX, | |
167 | OR_ESP, | |
168 | OR_EBP, | |
169 | OR_ESI, | |
170 | OR_EDI, | |
14ce26e7 FB |
171 | |
172 | OR_TMP0 = 16, /* temporary operand register */ | |
2c0262af FB |
173 | OR_TMP1, |
174 | OR_A0, /* temporary register used when doing address evaluation */ | |
2c0262af FB |
175 | }; |
176 | ||
e207582f | 177 | static void set_cc_op(DisasContext *s, CCOp op) |
3ca51d07 | 178 | { |
e207582f RH |
179 | if (s->cc_op != op) { |
180 | s->cc_op = op; | |
181 | /* The DYNAMIC setting is translator only, and should never be | |
182 | stored. Thus we always consider it clean. */ | |
183 | s->cc_op_dirty = (op != CC_OP_DYNAMIC); | |
184 | } | |
185 | } | |
186 | ||
e207582f RH |
187 | static void gen_update_cc_op(DisasContext *s) |
188 | { | |
189 | if (s->cc_op_dirty) { | |
773cdfcc | 190 | tcg_gen_movi_i32(cpu_cc_op, s->cc_op); |
e207582f RH |
191 | s->cc_op_dirty = false; |
192 | } | |
3ca51d07 RH |
193 | } |
194 | ||
57fec1fe FB |
195 | static inline void gen_op_movl_T0_0(void) |
196 | { | |
197 | tcg_gen_movi_tl(cpu_T[0], 0); | |
198 | } | |
199 | ||
200 | static inline void gen_op_movl_T0_im(int32_t val) | |
201 | { | |
202 | tcg_gen_movi_tl(cpu_T[0], val); | |
203 | } | |
204 | ||
205 | static inline void gen_op_movl_T0_imu(uint32_t val) | |
206 | { | |
207 | tcg_gen_movi_tl(cpu_T[0], val); | |
208 | } | |
209 | ||
210 | static inline void gen_op_movl_T1_im(int32_t val) | |
211 | { | |
212 | tcg_gen_movi_tl(cpu_T[1], val); | |
213 | } | |
214 | ||
215 | static inline void gen_op_movl_T1_imu(uint32_t val) | |
216 | { | |
217 | tcg_gen_movi_tl(cpu_T[1], val); | |
218 | } | |
219 | ||
220 | static inline void gen_op_movl_A0_im(uint32_t val) | |
221 | { | |
222 | tcg_gen_movi_tl(cpu_A0, val); | |
223 | } | |
224 | ||
225 | #ifdef TARGET_X86_64 | |
226 | static inline void gen_op_movq_A0_im(int64_t val) | |
227 | { | |
228 | tcg_gen_movi_tl(cpu_A0, val); | |
229 | } | |
230 | #endif | |
231 | ||
232 | static inline void gen_movtl_T0_im(target_ulong val) | |
233 | { | |
234 | tcg_gen_movi_tl(cpu_T[0], val); | |
235 | } | |
236 | ||
237 | static inline void gen_movtl_T1_im(target_ulong val) | |
238 | { | |
239 | tcg_gen_movi_tl(cpu_T[1], val); | |
240 | } | |
241 | ||
242 | static inline void gen_op_andl_T0_ffff(void) | |
243 | { | |
244 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
245 | } | |
246 | ||
247 | static inline void gen_op_andl_T0_im(uint32_t val) | |
248 | { | |
249 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); | |
250 | } | |
251 | ||
252 | static inline void gen_op_movl_T0_T1(void) | |
253 | { | |
254 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); | |
255 | } | |
256 | ||
257 | static inline void gen_op_andl_A0_ffff(void) | |
258 | { | |
259 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff); | |
260 | } | |
261 | ||
14ce26e7 FB |
262 | #ifdef TARGET_X86_64 |
263 | ||
264 | #define NB_OP_SIZES 4 | |
265 | ||
14ce26e7 FB |
266 | #else /* !TARGET_X86_64 */ |
267 | ||
268 | #define NB_OP_SIZES 3 | |
269 | ||
14ce26e7 FB |
270 | #endif /* !TARGET_X86_64 */ |
271 | ||
e2542fe2 | 272 | #if defined(HOST_WORDS_BIGENDIAN) |
57fec1fe FB |
273 | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
274 | #define REG_H_OFFSET (sizeof(target_ulong) - 2) | |
275 | #define REG_W_OFFSET (sizeof(target_ulong) - 2) | |
276 | #define REG_L_OFFSET (sizeof(target_ulong) - 4) | |
277 | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) | |
14ce26e7 | 278 | #else |
57fec1fe FB |
279 | #define REG_B_OFFSET 0 |
280 | #define REG_H_OFFSET 1 | |
281 | #define REG_W_OFFSET 0 | |
282 | #define REG_L_OFFSET 0 | |
283 | #define REG_LH_OFFSET 4 | |
14ce26e7 | 284 | #endif |
57fec1fe | 285 | |
96d7073f PM |
286 | /* In instruction encodings for byte register accesses the |
287 | * register number usually indicates "low 8 bits of register N"; | |
288 | * however there are some special cases where N 4..7 indicates | |
289 | * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return | |
290 | * true for this special case, false otherwise. | |
291 | */ | |
292 | static inline bool byte_reg_is_xH(int reg) | |
293 | { | |
294 | if (reg < 4) { | |
295 | return false; | |
296 | } | |
297 | #ifdef TARGET_X86_64 | |
298 | if (reg >= 8 || x86_64_hregs) { | |
299 | return false; | |
300 | } | |
301 | #endif | |
302 | return true; | |
303 | } | |
304 | ||
1e4840bf | 305 | static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) |
57fec1fe FB |
306 | { |
307 | switch(ot) { | |
308 | case OT_BYTE: | |
96d7073f | 309 | if (!byte_reg_is_xH(reg)) { |
c832e3de | 310 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); |
57fec1fe | 311 | } else { |
c832e3de | 312 | tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); |
57fec1fe FB |
313 | } |
314 | break; | |
315 | case OT_WORD: | |
c832e3de | 316 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16); |
57fec1fe | 317 | break; |
cc739bb0 | 318 | default: /* XXX this shouldn't be reached; abort? */ |
57fec1fe | 319 | case OT_LONG: |
cc739bb0 LD |
320 | /* For x86_64, this sets the higher half of register to zero. |
321 | For i386, this is equivalent to a mov. */ | |
322 | tcg_gen_ext32u_tl(cpu_regs[reg], t0); | |
57fec1fe | 323 | break; |
cc739bb0 | 324 | #ifdef TARGET_X86_64 |
57fec1fe | 325 | case OT_QUAD: |
cc739bb0 | 326 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
57fec1fe | 327 | break; |
14ce26e7 | 328 | #endif |
57fec1fe FB |
329 | } |
330 | } | |
2c0262af | 331 | |
57fec1fe FB |
332 | static inline void gen_op_mov_reg_T0(int ot, int reg) |
333 | { | |
1e4840bf | 334 | gen_op_mov_reg_v(ot, reg, cpu_T[0]); |
57fec1fe FB |
335 | } |
336 | ||
337 | static inline void gen_op_mov_reg_T1(int ot, int reg) | |
338 | { | |
1e4840bf | 339 | gen_op_mov_reg_v(ot, reg, cpu_T[1]); |
57fec1fe FB |
340 | } |
341 | ||
342 | static inline void gen_op_mov_reg_A0(int size, int reg) | |
343 | { | |
344 | switch(size) { | |
93ab25d7 | 345 | case OT_BYTE: |
c832e3de | 346 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16); |
57fec1fe | 347 | break; |
cc739bb0 | 348 | default: /* XXX this shouldn't be reached; abort? */ |
93ab25d7 | 349 | case OT_WORD: |
cc739bb0 LD |
350 | /* For x86_64, this sets the higher half of register to zero. |
351 | For i386, this is equivalent to a mov. */ | |
352 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0); | |
57fec1fe | 353 | break; |
cc739bb0 | 354 | #ifdef TARGET_X86_64 |
93ab25d7 | 355 | case OT_LONG: |
cc739bb0 | 356 | tcg_gen_mov_tl(cpu_regs[reg], cpu_A0); |
57fec1fe | 357 | break; |
14ce26e7 | 358 | #endif |
57fec1fe FB |
359 | } |
360 | } | |
361 | ||
1e4840bf | 362 | static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) |
57fec1fe | 363 | { |
96d7073f PM |
364 | if (ot == OT_BYTE && byte_reg_is_xH(reg)) { |
365 | tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); | |
366 | tcg_gen_ext8u_tl(t0, t0); | |
367 | } else { | |
cc739bb0 | 368 | tcg_gen_mov_tl(t0, cpu_regs[reg]); |
57fec1fe FB |
369 | } |
370 | } | |
371 | ||
1e4840bf FB |
372 | static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) |
373 | { | |
374 | gen_op_mov_v_reg(ot, cpu_T[t_index], reg); | |
375 | } | |
376 | ||
57fec1fe FB |
377 | static inline void gen_op_movl_A0_reg(int reg) |
378 | { | |
cc739bb0 | 379 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
380 | } |
381 | ||
382 | static inline void gen_op_addl_A0_im(int32_t val) | |
383 | { | |
384 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
14ce26e7 | 385 | #ifdef TARGET_X86_64 |
57fec1fe | 386 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); |
14ce26e7 | 387 | #endif |
57fec1fe | 388 | } |
2c0262af | 389 | |
14ce26e7 | 390 | #ifdef TARGET_X86_64 |
57fec1fe FB |
391 | static inline void gen_op_addq_A0_im(int64_t val) |
392 | { | |
393 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
394 | } | |
14ce26e7 | 395 | #endif |
57fec1fe FB |
396 | |
397 | static void gen_add_A0_im(DisasContext *s, int val) | |
398 | { | |
399 | #ifdef TARGET_X86_64 | |
400 | if (CODE64(s)) | |
401 | gen_op_addq_A0_im(val); | |
402 | else | |
403 | #endif | |
404 | gen_op_addl_A0_im(val); | |
405 | } | |
2c0262af | 406 | |
57fec1fe | 407 | static inline void gen_op_addl_T0_T1(void) |
2c0262af | 408 | { |
57fec1fe FB |
409 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
410 | } | |
411 | ||
412 | static inline void gen_op_jmp_T0(void) | |
413 | { | |
317ac620 | 414 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip)); |
57fec1fe FB |
415 | } |
416 | ||
6e0d8677 | 417 | static inline void gen_op_add_reg_im(int size, int reg, int32_t val) |
57fec1fe | 418 | { |
6e0d8677 | 419 | switch(size) { |
93ab25d7 | 420 | case OT_BYTE: |
cc739bb0 | 421 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
c832e3de | 422 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 | 423 | break; |
93ab25d7 | 424 | case OT_WORD: |
cc739bb0 LD |
425 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
426 | /* For x86_64, this sets the higher half of register to zero. | |
427 | For i386, this is equivalent to a nop. */ | |
428 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
429 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 FB |
430 | break; |
431 | #ifdef TARGET_X86_64 | |
93ab25d7 | 432 | case OT_LONG: |
cc739bb0 | 433 | tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val); |
6e0d8677 FB |
434 | break; |
435 | #endif | |
436 | } | |
57fec1fe FB |
437 | } |
438 | ||
6e0d8677 | 439 | static inline void gen_op_add_reg_T0(int size, int reg) |
57fec1fe | 440 | { |
6e0d8677 | 441 | switch(size) { |
93ab25d7 | 442 | case OT_BYTE: |
cc739bb0 | 443 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
c832e3de | 444 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 | 445 | break; |
93ab25d7 | 446 | case OT_WORD: |
cc739bb0 LD |
447 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
448 | /* For x86_64, this sets the higher half of register to zero. | |
449 | For i386, this is equivalent to a nop. */ | |
450 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
451 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 | 452 | break; |
14ce26e7 | 453 | #ifdef TARGET_X86_64 |
93ab25d7 | 454 | case OT_LONG: |
cc739bb0 | 455 | tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]); |
6e0d8677 | 456 | break; |
14ce26e7 | 457 | #endif |
6e0d8677 FB |
458 | } |
459 | } | |
57fec1fe | 460 | |
57fec1fe FB |
461 | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) |
462 | { | |
cc739bb0 LD |
463 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
464 | if (shift != 0) | |
57fec1fe FB |
465 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
466 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
cc739bb0 LD |
467 | /* For x86_64, this sets the higher half of register to zero. |
468 | For i386, this is equivalent to a nop. */ | |
469 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
57fec1fe | 470 | } |
2c0262af | 471 | |
57fec1fe FB |
472 | static inline void gen_op_movl_A0_seg(int reg) |
473 | { | |
317ac620 | 474 | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET); |
57fec1fe | 475 | } |
2c0262af | 476 | |
7162ab21 | 477 | static inline void gen_op_addl_A0_seg(DisasContext *s, int reg) |
57fec1fe | 478 | { |
317ac620 | 479 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 480 | #ifdef TARGET_X86_64 |
7162ab21 VC |
481 | if (CODE64(s)) { |
482 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
483 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
484 | } else { | |
485 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
486 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
487 | } | |
488 | #else | |
489 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe FB |
490 | #endif |
491 | } | |
2c0262af | 492 | |
14ce26e7 | 493 | #ifdef TARGET_X86_64 |
57fec1fe FB |
494 | static inline void gen_op_movq_A0_seg(int reg) |
495 | { | |
317ac620 | 496 | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 497 | } |
14ce26e7 | 498 | |
57fec1fe FB |
499 | static inline void gen_op_addq_A0_seg(int reg) |
500 | { | |
317ac620 | 501 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe FB |
502 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
503 | } | |
504 | ||
505 | static inline void gen_op_movq_A0_reg(int reg) | |
506 | { | |
cc739bb0 | 507 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
508 | } |
509 | ||
510 | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) | |
511 | { | |
cc739bb0 LD |
512 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
513 | if (shift != 0) | |
57fec1fe FB |
514 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
515 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
516 | } | |
14ce26e7 FB |
517 | #endif |
518 | ||
57fec1fe FB |
519 | static inline void gen_op_lds_T0_A0(int idx) |
520 | { | |
521 | int mem_index = (idx >> 2) - 1; | |
522 | switch(idx & 3) { | |
93ab25d7 | 523 | case OT_BYTE: |
57fec1fe FB |
524 | tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index); |
525 | break; | |
93ab25d7 | 526 | case OT_WORD: |
57fec1fe FB |
527 | tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index); |
528 | break; | |
529 | default: | |
93ab25d7 | 530 | case OT_LONG: |
57fec1fe FB |
531 | tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index); |
532 | break; | |
533 | } | |
534 | } | |
2c0262af | 535 | |
1e4840bf | 536 | static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) |
57fec1fe FB |
537 | { |
538 | int mem_index = (idx >> 2) - 1; | |
539 | switch(idx & 3) { | |
93ab25d7 | 540 | case OT_BYTE: |
1e4840bf | 541 | tcg_gen_qemu_ld8u(t0, a0, mem_index); |
57fec1fe | 542 | break; |
93ab25d7 | 543 | case OT_WORD: |
1e4840bf | 544 | tcg_gen_qemu_ld16u(t0, a0, mem_index); |
57fec1fe | 545 | break; |
93ab25d7 | 546 | case OT_LONG: |
1e4840bf | 547 | tcg_gen_qemu_ld32u(t0, a0, mem_index); |
57fec1fe FB |
548 | break; |
549 | default: | |
93ab25d7 | 550 | case OT_QUAD: |
a7812ae4 PB |
551 | /* Should never happen on 32-bit targets. */ |
552 | #ifdef TARGET_X86_64 | |
1e4840bf | 553 | tcg_gen_qemu_ld64(t0, a0, mem_index); |
a7812ae4 | 554 | #endif |
57fec1fe FB |
555 | break; |
556 | } | |
557 | } | |
2c0262af | 558 | |
1e4840bf FB |
559 | /* XXX: always use ldu or lds */ |
560 | static inline void gen_op_ld_T0_A0(int idx) | |
561 | { | |
562 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); | |
563 | } | |
564 | ||
57fec1fe FB |
565 | static inline void gen_op_ldu_T0_A0(int idx) |
566 | { | |
1e4840bf | 567 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 568 | } |
2c0262af | 569 | |
57fec1fe | 570 | static inline void gen_op_ld_T1_A0(int idx) |
1e4840bf FB |
571 | { |
572 | gen_op_ld_v(idx, cpu_T[1], cpu_A0); | |
573 | } | |
574 | ||
575 | static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) | |
57fec1fe FB |
576 | { |
577 | int mem_index = (idx >> 2) - 1; | |
578 | switch(idx & 3) { | |
93ab25d7 | 579 | case OT_BYTE: |
1e4840bf | 580 | tcg_gen_qemu_st8(t0, a0, mem_index); |
57fec1fe | 581 | break; |
93ab25d7 | 582 | case OT_WORD: |
1e4840bf | 583 | tcg_gen_qemu_st16(t0, a0, mem_index); |
57fec1fe | 584 | break; |
93ab25d7 | 585 | case OT_LONG: |
1e4840bf | 586 | tcg_gen_qemu_st32(t0, a0, mem_index); |
57fec1fe FB |
587 | break; |
588 | default: | |
93ab25d7 | 589 | case OT_QUAD: |
a7812ae4 PB |
590 | /* Should never happen on 32-bit targets. */ |
591 | #ifdef TARGET_X86_64 | |
1e4840bf | 592 | tcg_gen_qemu_st64(t0, a0, mem_index); |
a7812ae4 | 593 | #endif |
57fec1fe FB |
594 | break; |
595 | } | |
596 | } | |
4f31916f | 597 | |
57fec1fe FB |
598 | static inline void gen_op_st_T0_A0(int idx) |
599 | { | |
1e4840bf | 600 | gen_op_st_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 601 | } |
4f31916f | 602 | |
57fec1fe FB |
603 | static inline void gen_op_st_T1_A0(int idx) |
604 | { | |
1e4840bf | 605 | gen_op_st_v(idx, cpu_T[1], cpu_A0); |
57fec1fe | 606 | } |
4f31916f | 607 | |
14ce26e7 FB |
608 | static inline void gen_jmp_im(target_ulong pc) |
609 | { | |
57fec1fe | 610 | tcg_gen_movi_tl(cpu_tmp0, pc); |
317ac620 | 611 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip)); |
14ce26e7 FB |
612 | } |
613 | ||
2c0262af FB |
614 | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
615 | { | |
616 | int override; | |
617 | ||
618 | override = s->override; | |
14ce26e7 FB |
619 | #ifdef TARGET_X86_64 |
620 | if (s->aflag == 2) { | |
621 | if (override >= 0) { | |
57fec1fe FB |
622 | gen_op_movq_A0_seg(override); |
623 | gen_op_addq_A0_reg_sN(0, R_ESI); | |
14ce26e7 | 624 | } else { |
57fec1fe | 625 | gen_op_movq_A0_reg(R_ESI); |
14ce26e7 FB |
626 | } |
627 | } else | |
628 | #endif | |
2c0262af FB |
629 | if (s->aflag) { |
630 | /* 32 bit address */ | |
631 | if (s->addseg && override < 0) | |
632 | override = R_DS; | |
633 | if (override >= 0) { | |
57fec1fe FB |
634 | gen_op_movl_A0_seg(override); |
635 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af | 636 | } else { |
57fec1fe | 637 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
638 | } |
639 | } else { | |
640 | /* 16 address, always override */ | |
641 | if (override < 0) | |
642 | override = R_DS; | |
57fec1fe | 643 | gen_op_movl_A0_reg(R_ESI); |
2c0262af | 644 | gen_op_andl_A0_ffff(); |
7162ab21 | 645 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
646 | } |
647 | } | |
648 | ||
649 | static inline void gen_string_movl_A0_EDI(DisasContext *s) | |
650 | { | |
14ce26e7 FB |
651 | #ifdef TARGET_X86_64 |
652 | if (s->aflag == 2) { | |
57fec1fe | 653 | gen_op_movq_A0_reg(R_EDI); |
14ce26e7 FB |
654 | } else |
655 | #endif | |
2c0262af FB |
656 | if (s->aflag) { |
657 | if (s->addseg) { | |
57fec1fe FB |
658 | gen_op_movl_A0_seg(R_ES); |
659 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af | 660 | } else { |
57fec1fe | 661 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
662 | } |
663 | } else { | |
57fec1fe | 664 | gen_op_movl_A0_reg(R_EDI); |
2c0262af | 665 | gen_op_andl_A0_ffff(); |
7162ab21 | 666 | gen_op_addl_A0_seg(s, R_ES); |
2c0262af FB |
667 | } |
668 | } | |
669 | ||
6e0d8677 FB |
670 | static inline void gen_op_movl_T0_Dshift(int ot) |
671 | { | |
317ac620 | 672 | tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df)); |
6e0d8677 | 673 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); |
2c0262af FB |
674 | }; |
675 | ||
d824df34 | 676 | static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign) |
6e0d8677 | 677 | { |
d824df34 | 678 | switch (size) { |
6e0d8677 | 679 | case OT_BYTE: |
d824df34 PB |
680 | if (sign) { |
681 | tcg_gen_ext8s_tl(dst, src); | |
682 | } else { | |
683 | tcg_gen_ext8u_tl(dst, src); | |
684 | } | |
685 | return dst; | |
6e0d8677 | 686 | case OT_WORD: |
d824df34 PB |
687 | if (sign) { |
688 | tcg_gen_ext16s_tl(dst, src); | |
689 | } else { | |
690 | tcg_gen_ext16u_tl(dst, src); | |
691 | } | |
692 | return dst; | |
693 | #ifdef TARGET_X86_64 | |
6e0d8677 | 694 | case OT_LONG: |
d824df34 PB |
695 | if (sign) { |
696 | tcg_gen_ext32s_tl(dst, src); | |
697 | } else { | |
698 | tcg_gen_ext32u_tl(dst, src); | |
699 | } | |
700 | return dst; | |
701 | #endif | |
6e0d8677 | 702 | default: |
d824df34 | 703 | return src; |
6e0d8677 FB |
704 | } |
705 | } | |
3b46e624 | 706 | |
d824df34 PB |
707 | static void gen_extu(int ot, TCGv reg) |
708 | { | |
709 | gen_ext_tl(reg, reg, ot, false); | |
710 | } | |
711 | ||
6e0d8677 FB |
712 | static void gen_exts(int ot, TCGv reg) |
713 | { | |
d824df34 | 714 | gen_ext_tl(reg, reg, ot, true); |
6e0d8677 | 715 | } |
2c0262af | 716 | |
6e0d8677 FB |
717 | static inline void gen_op_jnz_ecx(int size, int label1) |
718 | { | |
cc739bb0 | 719 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 720 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 721 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); |
6e0d8677 FB |
722 | } |
723 | ||
724 | static inline void gen_op_jz_ecx(int size, int label1) | |
725 | { | |
cc739bb0 | 726 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 727 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 728 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
6e0d8677 | 729 | } |
2c0262af | 730 | |
a7812ae4 PB |
731 | static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n) |
732 | { | |
733 | switch (ot) { | |
93ab25d7 PB |
734 | case OT_BYTE: |
735 | gen_helper_inb(v, n); | |
736 | break; | |
737 | case OT_WORD: | |
738 | gen_helper_inw(v, n); | |
739 | break; | |
740 | case OT_LONG: | |
741 | gen_helper_inl(v, n); | |
742 | break; | |
a7812ae4 | 743 | } |
a7812ae4 | 744 | } |
2c0262af | 745 | |
a7812ae4 PB |
746 | static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n) |
747 | { | |
748 | switch (ot) { | |
93ab25d7 PB |
749 | case OT_BYTE: |
750 | gen_helper_outb(v, n); | |
751 | break; | |
752 | case OT_WORD: | |
753 | gen_helper_outw(v, n); | |
754 | break; | |
755 | case OT_LONG: | |
756 | gen_helper_outl(v, n); | |
757 | break; | |
a7812ae4 | 758 | } |
a7812ae4 | 759 | } |
f115e911 | 760 | |
b8b6a50b FB |
761 | static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, |
762 | uint32_t svm_flags) | |
f115e911 | 763 | { |
b8b6a50b FB |
764 | int state_saved; |
765 | target_ulong next_eip; | |
766 | ||
767 | state_saved = 0; | |
f115e911 | 768 | if (s->pe && (s->cpl > s->iopl || s->vm86)) { |
773cdfcc | 769 | gen_update_cc_op(s); |
14ce26e7 | 770 | gen_jmp_im(cur_eip); |
b8b6a50b | 771 | state_saved = 1; |
b6abf97d | 772 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 773 | switch (ot) { |
93ab25d7 | 774 | case OT_BYTE: |
4a7443be BS |
775 | gen_helper_check_iob(cpu_env, cpu_tmp2_i32); |
776 | break; | |
93ab25d7 | 777 | case OT_WORD: |
4a7443be BS |
778 | gen_helper_check_iow(cpu_env, cpu_tmp2_i32); |
779 | break; | |
93ab25d7 | 780 | case OT_LONG: |
4a7443be BS |
781 | gen_helper_check_iol(cpu_env, cpu_tmp2_i32); |
782 | break; | |
a7812ae4 | 783 | } |
b8b6a50b | 784 | } |
872929aa | 785 | if(s->flags & HF_SVMI_MASK) { |
b8b6a50b | 786 | if (!state_saved) { |
773cdfcc | 787 | gen_update_cc_op(s); |
b8b6a50b | 788 | gen_jmp_im(cur_eip); |
b8b6a50b FB |
789 | } |
790 | svm_flags |= (1 << (4 + ot)); | |
791 | next_eip = s->pc - s->cs_base; | |
b6abf97d | 792 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
052e80d5 BS |
793 | gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32, |
794 | tcg_const_i32(svm_flags), | |
a7812ae4 | 795 | tcg_const_i32(next_eip - cur_eip)); |
f115e911 FB |
796 | } |
797 | } | |
798 | ||
2c0262af FB |
799 | static inline void gen_movs(DisasContext *s, int ot) |
800 | { | |
801 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 802 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 803 | gen_string_movl_A0_EDI(s); |
57fec1fe | 804 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
805 | gen_op_movl_T0_Dshift(ot); |
806 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
807 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
808 | } |
809 | ||
b6abf97d FB |
810 | static void gen_op_update1_cc(void) |
811 | { | |
812 | tcg_gen_discard_tl(cpu_cc_src); | |
813 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
814 | } | |
815 | ||
816 | static void gen_op_update2_cc(void) | |
817 | { | |
818 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
819 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
820 | } | |
821 | ||
822 | static inline void gen_op_cmpl_T0_T1_cc(void) | |
823 | { | |
824 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
825 | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
826 | } | |
827 | ||
828 | static inline void gen_op_testl_T0_T1_cc(void) | |
829 | { | |
830 | tcg_gen_discard_tl(cpu_cc_src); | |
831 | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
832 | } | |
833 | ||
834 | static void gen_op_update_neg_cc(void) | |
835 | { | |
836 | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]); | |
837 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
838 | } | |
839 | ||
8e1c85e3 | 840 | /* compute eflags.C to reg */ |
c7b3c873 | 841 | static void gen_compute_eflags_c(DisasContext *s, TCGv reg) |
8e1c85e3 | 842 | { |
773cdfcc | 843 | gen_update_cc_op(s); |
f0967a1a | 844 | gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op); |
8e1c85e3 FB |
845 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
846 | } | |
847 | ||
c7b3c873 PB |
848 | /* compute all eflags to reg */ |
849 | static void gen_compute_eflags(DisasContext *s, TCGv reg) | |
8e1c85e3 | 850 | { |
773cdfcc | 851 | gen_update_cc_op(s); |
f0967a1a | 852 | gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_env, cpu_cc_op); |
c7b3c873 PB |
853 | if (TCGV_EQUAL(reg, cpu_cc_src)) { |
854 | tcg_gen_discard_tl(cpu_cc_dst); | |
3ca51d07 | 855 | set_cc_op(s, CC_OP_EFLAGS); |
c7b3c873 | 856 | } |
8e1c85e3 FB |
857 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
858 | } | |
859 | ||
1e4840bf | 860 | static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) |
8e1c85e3 | 861 | { |
1e4840bf | 862 | switch(jcc_op) { |
8e1c85e3 | 863 | case JCC_O: |
c7b3c873 | 864 | gen_compute_eflags(s, cpu_T[0]); |
8e1c85e3 FB |
865 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11); |
866 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
867 | break; | |
868 | case JCC_B: | |
c7b3c873 | 869 | gen_compute_eflags_c(s, cpu_T[0]); |
8e1c85e3 FB |
870 | break; |
871 | case JCC_Z: | |
c7b3c873 | 872 | gen_compute_eflags(s, cpu_T[0]); |
8e1c85e3 FB |
873 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6); |
874 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
875 | break; | |
876 | case JCC_BE: | |
c7b3c873 | 877 | gen_compute_eflags(s, cpu_tmp0); |
8e1c85e3 FB |
878 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6); |
879 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
880 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
881 | break; | |
882 | case JCC_S: | |
c7b3c873 | 883 | gen_compute_eflags(s, cpu_T[0]); |
8e1c85e3 FB |
884 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7); |
885 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
886 | break; | |
887 | case JCC_P: | |
c7b3c873 | 888 | gen_compute_eflags(s, cpu_T[0]); |
8e1c85e3 FB |
889 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2); |
890 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
891 | break; | |
892 | case JCC_L: | |
c7b3c873 | 893 | gen_compute_eflags(s, cpu_tmp0); |
8e1c85e3 FB |
894 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ |
895 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */ | |
896 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
897 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
898 | break; | |
899 | default: | |
900 | case JCC_LE: | |
c7b3c873 | 901 | gen_compute_eflags(s, cpu_tmp0); |
8e1c85e3 FB |
902 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ |
903 | tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */ | |
904 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */ | |
905 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
906 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
907 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
908 | break; | |
909 | } | |
910 | } | |
911 | ||
912 | /* return true if setcc_slow is not needed (WARNING: must be kept in | |
913 | sync with gen_jcc1) */ | |
914 | static int is_fast_jcc_case(DisasContext *s, int b) | |
915 | { | |
916 | int jcc_op; | |
917 | jcc_op = (b >> 1) & 7; | |
918 | switch(s->cc_op) { | |
919 | /* we optimize the cmp/jcc case */ | |
920 | case CC_OP_SUBB: | |
921 | case CC_OP_SUBW: | |
922 | case CC_OP_SUBL: | |
923 | case CC_OP_SUBQ: | |
924 | if (jcc_op == JCC_O || jcc_op == JCC_P) | |
925 | goto slow_jcc; | |
926 | break; | |
927 | ||
928 | /* some jumps are easy to compute */ | |
929 | case CC_OP_ADDB: | |
930 | case CC_OP_ADDW: | |
931 | case CC_OP_ADDL: | |
932 | case CC_OP_ADDQ: | |
933 | ||
934 | case CC_OP_LOGICB: | |
935 | case CC_OP_LOGICW: | |
936 | case CC_OP_LOGICL: | |
937 | case CC_OP_LOGICQ: | |
938 | ||
939 | case CC_OP_INCB: | |
940 | case CC_OP_INCW: | |
941 | case CC_OP_INCL: | |
942 | case CC_OP_INCQ: | |
943 | ||
944 | case CC_OP_DECB: | |
945 | case CC_OP_DECW: | |
946 | case CC_OP_DECL: | |
947 | case CC_OP_DECQ: | |
948 | ||
949 | case CC_OP_SHLB: | |
950 | case CC_OP_SHLW: | |
951 | case CC_OP_SHLL: | |
952 | case CC_OP_SHLQ: | |
953 | if (jcc_op != JCC_Z && jcc_op != JCC_S) | |
954 | goto slow_jcc; | |
955 | break; | |
956 | default: | |
957 | slow_jcc: | |
958 | return 0; | |
959 | } | |
960 | return 1; | |
961 | } | |
962 | ||
963 | /* generate a conditional jump to label 'l1' according to jump opcode | |
964 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
b27fc131 | 965 | static inline void gen_jcc1(DisasContext *s, int b, int l1) |
8e1c85e3 FB |
966 | { |
967 | int inv, jcc_op, size, cond; | |
968 | TCGv t0; | |
969 | ||
970 | inv = b & 1; | |
971 | jcc_op = (b >> 1) & 7; | |
972 | ||
b27fc131 | 973 | switch (s->cc_op) { |
8e1c85e3 FB |
974 | /* we optimize the cmp/jcc case */ |
975 | case CC_OP_SUBB: | |
976 | case CC_OP_SUBW: | |
977 | case CC_OP_SUBL: | |
978 | case CC_OP_SUBQ: | |
979 | ||
b27fc131 | 980 | size = s->cc_op - CC_OP_SUBB; |
8e1c85e3 FB |
981 | switch(jcc_op) { |
982 | case JCC_Z: | |
983 | fast_jcc_z: | |
d824df34 | 984 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_dst, size, false); |
cb63669a | 985 | tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1); |
8e1c85e3 FB |
986 | break; |
987 | case JCC_S: | |
988 | fast_jcc_s: | |
d824df34 PB |
989 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_dst, size, true); |
990 | tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, t0, 0, l1); | |
8e1c85e3 | 991 | break; |
d824df34 | 992 | |
8e1c85e3 FB |
993 | case JCC_B: |
994 | cond = inv ? TCG_COND_GEU : TCG_COND_LTU; | |
995 | goto fast_jcc_b; | |
996 | case JCC_BE: | |
997 | cond = inv ? TCG_COND_GTU : TCG_COND_LEU; | |
998 | fast_jcc_b: | |
999 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
d824df34 PB |
1000 | gen_extu(size, cpu_tmp4); |
1001 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
8e1c85e3 FB |
1002 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); |
1003 | break; | |
1004 | ||
1005 | case JCC_L: | |
1006 | cond = inv ? TCG_COND_GE : TCG_COND_LT; | |
1007 | goto fast_jcc_l; | |
1008 | case JCC_LE: | |
1009 | cond = inv ? TCG_COND_GT : TCG_COND_LE; | |
1010 | fast_jcc_l: | |
1011 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
d824df34 PB |
1012 | gen_exts(size, cpu_tmp4); |
1013 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true); | |
8e1c85e3 FB |
1014 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); |
1015 | break; | |
1016 | ||
1017 | default: | |
1018 | goto slow_jcc; | |
1019 | } | |
1020 | break; | |
1021 | ||
1022 | /* some jumps are easy to compute */ | |
1023 | case CC_OP_ADDB: | |
1024 | case CC_OP_ADDW: | |
1025 | case CC_OP_ADDL: | |
1026 | case CC_OP_ADDQ: | |
1027 | ||
1028 | case CC_OP_ADCB: | |
1029 | case CC_OP_ADCW: | |
1030 | case CC_OP_ADCL: | |
1031 | case CC_OP_ADCQ: | |
1032 | ||
1033 | case CC_OP_SBBB: | |
1034 | case CC_OP_SBBW: | |
1035 | case CC_OP_SBBL: | |
1036 | case CC_OP_SBBQ: | |
1037 | ||
1038 | case CC_OP_LOGICB: | |
1039 | case CC_OP_LOGICW: | |
1040 | case CC_OP_LOGICL: | |
1041 | case CC_OP_LOGICQ: | |
1042 | ||
1043 | case CC_OP_INCB: | |
1044 | case CC_OP_INCW: | |
1045 | case CC_OP_INCL: | |
1046 | case CC_OP_INCQ: | |
1047 | ||
1048 | case CC_OP_DECB: | |
1049 | case CC_OP_DECW: | |
1050 | case CC_OP_DECL: | |
1051 | case CC_OP_DECQ: | |
1052 | ||
1053 | case CC_OP_SHLB: | |
1054 | case CC_OP_SHLW: | |
1055 | case CC_OP_SHLL: | |
1056 | case CC_OP_SHLQ: | |
1057 | ||
1058 | case CC_OP_SARB: | |
1059 | case CC_OP_SARW: | |
1060 | case CC_OP_SARL: | |
1061 | case CC_OP_SARQ: | |
1062 | switch(jcc_op) { | |
1063 | case JCC_Z: | |
b27fc131 | 1064 | size = (s->cc_op - CC_OP_ADDB) & 3; |
8e1c85e3 FB |
1065 | goto fast_jcc_z; |
1066 | case JCC_S: | |
b27fc131 | 1067 | size = (s->cc_op - CC_OP_ADDB) & 3; |
8e1c85e3 FB |
1068 | goto fast_jcc_s; |
1069 | default: | |
1070 | goto slow_jcc; | |
1071 | } | |
1072 | break; | |
1073 | default: | |
1074 | slow_jcc: | |
1e4840bf | 1075 | gen_setcc_slow_T0(s, jcc_op); |
cb63669a PB |
1076 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, |
1077 | cpu_T[0], 0, l1); | |
8e1c85e3 FB |
1078 | break; |
1079 | } | |
1080 | } | |
1081 | ||
14ce26e7 FB |
1082 | /* XXX: does not work with gdbstub "ice" single step - not a |
1083 | serious problem */ | |
1084 | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) | |
2c0262af | 1085 | { |
14ce26e7 FB |
1086 | int l1, l2; |
1087 | ||
1088 | l1 = gen_new_label(); | |
1089 | l2 = gen_new_label(); | |
6e0d8677 | 1090 | gen_op_jnz_ecx(s->aflag, l1); |
14ce26e7 FB |
1091 | gen_set_label(l2); |
1092 | gen_jmp_tb(s, next_eip, 1); | |
1093 | gen_set_label(l1); | |
1094 | return l2; | |
2c0262af FB |
1095 | } |
1096 | ||
1097 | static inline void gen_stos(DisasContext *s, int ot) | |
1098 | { | |
57fec1fe | 1099 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1100 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1101 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1102 | gen_op_movl_T0_Dshift(ot); |
1103 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1104 | } |
1105 | ||
1106 | static inline void gen_lods(DisasContext *s, int ot) | |
1107 | { | |
1108 | gen_string_movl_A0_ESI(s); | |
57fec1fe FB |
1109 | gen_op_ld_T0_A0(ot + s->mem_index); |
1110 | gen_op_mov_reg_T0(ot, R_EAX); | |
6e0d8677 FB |
1111 | gen_op_movl_T0_Dshift(ot); |
1112 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2c0262af FB |
1113 | } |
1114 | ||
1115 | static inline void gen_scas(DisasContext *s, int ot) | |
1116 | { | |
57fec1fe | 1117 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1118 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1119 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1120 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1121 | gen_op_movl_T0_Dshift(ot); |
1122 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
3ca51d07 | 1123 | set_cc_op(s, CC_OP_SUBB + ot); |
2c0262af FB |
1124 | } |
1125 | ||
1126 | static inline void gen_cmps(DisasContext *s, int ot) | |
1127 | { | |
1128 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 1129 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 1130 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1131 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1132 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1133 | gen_op_movl_T0_Dshift(ot); |
1134 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
1135 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
3ca51d07 | 1136 | set_cc_op(s, CC_OP_SUBB + ot); |
2c0262af FB |
1137 | } |
1138 | ||
1139 | static inline void gen_ins(DisasContext *s, int ot) | |
1140 | { | |
2e70f6ef PB |
1141 | if (use_icount) |
1142 | gen_io_start(); | |
2c0262af | 1143 | gen_string_movl_A0_EDI(s); |
6e0d8677 FB |
1144 | /* Note: we must do this dummy write first to be restartable in |
1145 | case of page fault. */ | |
9772c73b | 1146 | gen_op_movl_T0_0(); |
57fec1fe | 1147 | gen_op_st_T0_A0(ot + s->mem_index); |
b8b6a50b | 1148 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); |
b6abf97d FB |
1149 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1150 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
a7812ae4 | 1151 | gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 1152 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1153 | gen_op_movl_T0_Dshift(ot); |
1154 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2e70f6ef PB |
1155 | if (use_icount) |
1156 | gen_io_end(); | |
2c0262af FB |
1157 | } |
1158 | ||
1159 | static inline void gen_outs(DisasContext *s, int ot) | |
1160 | { | |
2e70f6ef PB |
1161 | if (use_icount) |
1162 | gen_io_start(); | |
2c0262af | 1163 | gen_string_movl_A0_ESI(s); |
57fec1fe | 1164 | gen_op_ld_T0_A0(ot + s->mem_index); |
b8b6a50b FB |
1165 | |
1166 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); | |
b6abf97d FB |
1167 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1168 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
1169 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); | |
a7812ae4 | 1170 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
b8b6a50b | 1171 | |
6e0d8677 FB |
1172 | gen_op_movl_T0_Dshift(ot); |
1173 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2e70f6ef PB |
1174 | if (use_icount) |
1175 | gen_io_end(); | |
2c0262af FB |
1176 | } |
1177 | ||
1178 | /* same method as Valgrind : we generate jumps to current or next | |
1179 | instruction */ | |
1180 | #define GEN_REPZ(op) \ | |
1181 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 | 1182 | target_ulong cur_eip, target_ulong next_eip) \ |
2c0262af | 1183 | { \ |
14ce26e7 | 1184 | int l2;\ |
2c0262af | 1185 | gen_update_cc_op(s); \ |
14ce26e7 | 1186 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1187 | gen_ ## op(s, ot); \ |
6e0d8677 | 1188 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af FB |
1189 | /* a loop would cause two single step exceptions if ECX = 1 \ |
1190 | before rep string_insn */ \ | |
1191 | if (!s->jmp_opt) \ | |
6e0d8677 | 1192 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1193 | gen_jmp(s, cur_eip); \ |
1194 | } | |
1195 | ||
1196 | #define GEN_REPZ2(op) \ | |
1197 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 FB |
1198 | target_ulong cur_eip, \ |
1199 | target_ulong next_eip, \ | |
2c0262af FB |
1200 | int nz) \ |
1201 | { \ | |
14ce26e7 | 1202 | int l2;\ |
2c0262af | 1203 | gen_update_cc_op(s); \ |
14ce26e7 | 1204 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1205 | gen_ ## op(s, ot); \ |
6e0d8677 | 1206 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
773cdfcc | 1207 | gen_update_cc_op(s); \ |
b27fc131 | 1208 | gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \ |
2c0262af | 1209 | if (!s->jmp_opt) \ |
6e0d8677 | 1210 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af | 1211 | gen_jmp(s, cur_eip); \ |
3ca51d07 | 1212 | set_cc_op(s, CC_OP_DYNAMIC); \ |
2c0262af FB |
1213 | } |
1214 | ||
1215 | GEN_REPZ(movs) | |
1216 | GEN_REPZ(stos) | |
1217 | GEN_REPZ(lods) | |
1218 | GEN_REPZ(ins) | |
1219 | GEN_REPZ(outs) | |
1220 | GEN_REPZ2(scas) | |
1221 | GEN_REPZ2(cmps) | |
1222 | ||
a7812ae4 PB |
1223 | static void gen_helper_fp_arith_ST0_FT0(int op) |
1224 | { | |
1225 | switch (op) { | |
d3eb5eae BS |
1226 | case 0: |
1227 | gen_helper_fadd_ST0_FT0(cpu_env); | |
1228 | break; | |
1229 | case 1: | |
1230 | gen_helper_fmul_ST0_FT0(cpu_env); | |
1231 | break; | |
1232 | case 2: | |
1233 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1234 | break; | |
1235 | case 3: | |
1236 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1237 | break; | |
1238 | case 4: | |
1239 | gen_helper_fsub_ST0_FT0(cpu_env); | |
1240 | break; | |
1241 | case 5: | |
1242 | gen_helper_fsubr_ST0_FT0(cpu_env); | |
1243 | break; | |
1244 | case 6: | |
1245 | gen_helper_fdiv_ST0_FT0(cpu_env); | |
1246 | break; | |
1247 | case 7: | |
1248 | gen_helper_fdivr_ST0_FT0(cpu_env); | |
1249 | break; | |
a7812ae4 PB |
1250 | } |
1251 | } | |
2c0262af FB |
1252 | |
1253 | /* NOTE the exception in "r" op ordering */ | |
a7812ae4 PB |
1254 | static void gen_helper_fp_arith_STN_ST0(int op, int opreg) |
1255 | { | |
1256 | TCGv_i32 tmp = tcg_const_i32(opreg); | |
1257 | switch (op) { | |
d3eb5eae BS |
1258 | case 0: |
1259 | gen_helper_fadd_STN_ST0(cpu_env, tmp); | |
1260 | break; | |
1261 | case 1: | |
1262 | gen_helper_fmul_STN_ST0(cpu_env, tmp); | |
1263 | break; | |
1264 | case 4: | |
1265 | gen_helper_fsubr_STN_ST0(cpu_env, tmp); | |
1266 | break; | |
1267 | case 5: | |
1268 | gen_helper_fsub_STN_ST0(cpu_env, tmp); | |
1269 | break; | |
1270 | case 6: | |
1271 | gen_helper_fdivr_STN_ST0(cpu_env, tmp); | |
1272 | break; | |
1273 | case 7: | |
1274 | gen_helper_fdiv_STN_ST0(cpu_env, tmp); | |
1275 | break; | |
a7812ae4 PB |
1276 | } |
1277 | } | |
2c0262af FB |
1278 | |
1279 | /* if d == OR_TMP0, it means memory operand (address in A0) */ | |
1280 | static void gen_op(DisasContext *s1, int op, int ot, int d) | |
1281 | { | |
2c0262af | 1282 | if (d != OR_TMP0) { |
57fec1fe | 1283 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1284 | } else { |
57fec1fe | 1285 | gen_op_ld_T0_A0(ot + s1->mem_index); |
2c0262af FB |
1286 | } |
1287 | switch(op) { | |
1288 | case OP_ADCL: | |
c7b3c873 | 1289 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1290 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1291 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1292 | if (d != OR_TMP0) | |
1293 | gen_op_mov_reg_T0(ot, d); | |
1294 | else | |
1295 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1296 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1297 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1298 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1299 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1300 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot); | |
3ca51d07 | 1301 | set_cc_op(s1, CC_OP_DYNAMIC); |
cad3a37d | 1302 | break; |
2c0262af | 1303 | case OP_SBBL: |
c7b3c873 | 1304 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1305 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1306 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1307 | if (d != OR_TMP0) | |
57fec1fe | 1308 | gen_op_mov_reg_T0(ot, d); |
cad3a37d FB |
1309 | else |
1310 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1311 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1312 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1313 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1314 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1315 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot); | |
3ca51d07 | 1316 | set_cc_op(s1, CC_OP_DYNAMIC); |
cad3a37d | 1317 | break; |
2c0262af FB |
1318 | case OP_ADDL: |
1319 | gen_op_addl_T0_T1(); | |
cad3a37d FB |
1320 | if (d != OR_TMP0) |
1321 | gen_op_mov_reg_T0(ot, d); | |
1322 | else | |
1323 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1324 | gen_op_update2_cc(); | |
3ca51d07 | 1325 | set_cc_op(s1, CC_OP_ADDB + ot); |
2c0262af FB |
1326 | break; |
1327 | case OP_SUBL: | |
57fec1fe | 1328 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1329 | if (d != OR_TMP0) |
1330 | gen_op_mov_reg_T0(ot, d); | |
1331 | else | |
1332 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1333 | gen_op_update2_cc(); | |
3ca51d07 | 1334 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1335 | break; |
1336 | default: | |
1337 | case OP_ANDL: | |
57fec1fe | 1338 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1339 | if (d != OR_TMP0) |
1340 | gen_op_mov_reg_T0(ot, d); | |
1341 | else | |
1342 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1343 | gen_op_update1_cc(); | |
3ca51d07 | 1344 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1345 | break; |
2c0262af | 1346 | case OP_ORL: |
57fec1fe | 1347 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1348 | if (d != OR_TMP0) |
1349 | gen_op_mov_reg_T0(ot, d); | |
1350 | else | |
1351 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1352 | gen_op_update1_cc(); | |
3ca51d07 | 1353 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1354 | break; |
2c0262af | 1355 | case OP_XORL: |
57fec1fe | 1356 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1357 | if (d != OR_TMP0) |
1358 | gen_op_mov_reg_T0(ot, d); | |
1359 | else | |
1360 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1361 | gen_op_update1_cc(); | |
3ca51d07 | 1362 | set_cc_op(s1, CC_OP_LOGICB + ot); |
2c0262af FB |
1363 | break; |
1364 | case OP_CMPL: | |
1365 | gen_op_cmpl_T0_T1_cc(); | |
3ca51d07 | 1366 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1367 | break; |
1368 | } | |
b6abf97d FB |
1369 | } |
1370 | ||
2c0262af FB |
1371 | /* if d == OR_TMP0, it means memory operand (address in A0) */ |
1372 | static void gen_inc(DisasContext *s1, int ot, int d, int c) | |
1373 | { | |
1374 | if (d != OR_TMP0) | |
57fec1fe | 1375 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1376 | else |
57fec1fe | 1377 | gen_op_ld_T0_A0(ot + s1->mem_index); |
c7b3c873 | 1378 | gen_compute_eflags_c(s1, cpu_cc_src); |
2c0262af | 1379 | if (c > 0) { |
b6abf97d | 1380 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
3ca51d07 | 1381 | set_cc_op(s1, CC_OP_INCB + ot); |
2c0262af | 1382 | } else { |
b6abf97d | 1383 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
3ca51d07 | 1384 | set_cc_op(s1, CC_OP_DECB + ot); |
2c0262af FB |
1385 | } |
1386 | if (d != OR_TMP0) | |
57fec1fe | 1387 | gen_op_mov_reg_T0(ot, d); |
2c0262af | 1388 | else |
57fec1fe | 1389 | gen_op_st_T0_A0(ot + s1->mem_index); |
cd31fefa | 1390 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
2c0262af FB |
1391 | } |
1392 | ||
b6abf97d FB |
1393 | static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
1394 | int is_right, int is_arith) | |
2c0262af | 1395 | { |
b6abf97d FB |
1396 | target_ulong mask; |
1397 | int shift_label; | |
82786041 | 1398 | TCGv t0, t1, t2; |
1e4840bf | 1399 | |
82786041 | 1400 | if (ot == OT_QUAD) { |
b6abf97d | 1401 | mask = 0x3f; |
82786041 | 1402 | } else { |
b6abf97d | 1403 | mask = 0x1f; |
82786041 | 1404 | } |
3b46e624 | 1405 | |
b6abf97d | 1406 | /* load */ |
82786041 | 1407 | if (op1 == OR_TMP0) { |
b6abf97d | 1408 | gen_op_ld_T0_A0(ot + s->mem_index); |
82786041 | 1409 | } else { |
b6abf97d | 1410 | gen_op_mov_TN_reg(ot, 0, op1); |
82786041 | 1411 | } |
b6abf97d | 1412 | |
82786041 RH |
1413 | t0 = tcg_temp_local_new(); |
1414 | t1 = tcg_temp_local_new(); | |
1415 | t2 = tcg_temp_local_new(); | |
b6abf97d | 1416 | |
82786041 | 1417 | tcg_gen_andi_tl(t2, cpu_T[1], mask); |
b6abf97d FB |
1418 | |
1419 | if (is_right) { | |
1420 | if (is_arith) { | |
f484d386 | 1421 | gen_exts(ot, cpu_T[0]); |
82786041 RH |
1422 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1423 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d | 1424 | } else { |
cad3a37d | 1425 | gen_extu(ot, cpu_T[0]); |
82786041 RH |
1426 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1427 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1428 | } |
1429 | } else { | |
82786041 RH |
1430 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1431 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1432 | } |
1433 | ||
1434 | /* store */ | |
82786041 | 1435 | if (op1 == OR_TMP0) { |
b6abf97d | 1436 | gen_op_st_T0_A0(ot + s->mem_index); |
82786041 | 1437 | } else { |
b6abf97d | 1438 | gen_op_mov_reg_T0(ot, op1); |
82786041 RH |
1439 | } |
1440 | ||
773cdfcc RH |
1441 | /* update eflags */ |
1442 | gen_update_cc_op(s); | |
b6abf97d | 1443 | |
82786041 | 1444 | tcg_gen_mov_tl(t1, cpu_T[0]); |
1e4840bf | 1445 | |
b6abf97d | 1446 | shift_label = gen_new_label(); |
82786041 RH |
1447 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label); |
1448 | ||
1449 | tcg_gen_addi_tl(t2, t2, -1); | |
1450 | tcg_gen_mov_tl(cpu_cc_dst, t1); | |
1451 | ||
1452 | if (is_right) { | |
1453 | if (is_arith) { | |
1454 | tcg_gen_sar_tl(cpu_cc_src, t0, t2); | |
1455 | } else { | |
1456 | tcg_gen_shr_tl(cpu_cc_src, t0, t2); | |
1457 | } | |
1458 | } else { | |
1459 | tcg_gen_shl_tl(cpu_cc_src, t0, t2); | |
1460 | } | |
b6abf97d | 1461 | |
82786041 | 1462 | if (is_right) { |
b6abf97d | 1463 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
82786041 | 1464 | } else { |
b6abf97d | 1465 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
82786041 RH |
1466 | } |
1467 | ||
b6abf97d | 1468 | gen_set_label(shift_label); |
3ca51d07 | 1469 | set_cc_op(s, CC_OP_DYNAMIC); /* cannot predict flags after */ |
1e4840bf FB |
1470 | |
1471 | tcg_temp_free(t0); | |
1472 | tcg_temp_free(t1); | |
82786041 | 1473 | tcg_temp_free(t2); |
b6abf97d FB |
1474 | } |
1475 | ||
c1c37968 FB |
1476 | static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, |
1477 | int is_right, int is_arith) | |
1478 | { | |
1479 | int mask; | |
1480 | ||
1481 | if (ot == OT_QUAD) | |
1482 | mask = 0x3f; | |
1483 | else | |
1484 | mask = 0x1f; | |
1485 | ||
1486 | /* load */ | |
1487 | if (op1 == OR_TMP0) | |
1488 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1489 | else | |
1490 | gen_op_mov_TN_reg(ot, 0, op1); | |
1491 | ||
1492 | op2 &= mask; | |
1493 | if (op2 != 0) { | |
1494 | if (is_right) { | |
1495 | if (is_arith) { | |
1496 | gen_exts(ot, cpu_T[0]); | |
2a449d14 | 1497 | tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1498 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
1499 | } else { | |
1500 | gen_extu(ot, cpu_T[0]); | |
2a449d14 | 1501 | tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1502 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
1503 | } | |
1504 | } else { | |
2a449d14 | 1505 | tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1506 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
1507 | } | |
1508 | } | |
1509 | ||
1510 | /* store */ | |
1511 | if (op1 == OR_TMP0) | |
1512 | gen_op_st_T0_A0(ot + s->mem_index); | |
1513 | else | |
1514 | gen_op_mov_reg_T0(ot, op1); | |
1515 | ||
1516 | /* update eflags if non zero shift */ | |
1517 | if (op2 != 0) { | |
2a449d14 | 1518 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
c1c37968 | 1519 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
3ca51d07 | 1520 | set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot); |
c1c37968 FB |
1521 | } |
1522 | } | |
1523 | ||
b6abf97d FB |
1524 | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1525 | { | |
1526 | if (arg2 >= 0) | |
1527 | tcg_gen_shli_tl(ret, arg1, arg2); | |
1528 | else | |
1529 | tcg_gen_shri_tl(ret, arg1, -arg2); | |
1530 | } | |
1531 | ||
b6abf97d FB |
1532 | static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, |
1533 | int is_right) | |
1534 | { | |
1535 | target_ulong mask; | |
1536 | int label1, label2, data_bits; | |
1e4840bf FB |
1537 | TCGv t0, t1, t2, a0; |
1538 | ||
1539 | /* XXX: inefficient, but we must use local temps */ | |
a7812ae4 PB |
1540 | t0 = tcg_temp_local_new(); |
1541 | t1 = tcg_temp_local_new(); | |
1542 | t2 = tcg_temp_local_new(); | |
1543 | a0 = tcg_temp_local_new(); | |
1e4840bf | 1544 | |
b6abf97d FB |
1545 | if (ot == OT_QUAD) |
1546 | mask = 0x3f; | |
1547 | else | |
1548 | mask = 0x1f; | |
1549 | ||
1550 | /* load */ | |
1e4840bf FB |
1551 | if (op1 == OR_TMP0) { |
1552 | tcg_gen_mov_tl(a0, cpu_A0); | |
1553 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1554 | } else { | |
1555 | gen_op_mov_v_reg(ot, t0, op1); | |
1556 | } | |
b6abf97d | 1557 | |
1e4840bf FB |
1558 | tcg_gen_mov_tl(t1, cpu_T[1]); |
1559 | ||
1560 | tcg_gen_andi_tl(t1, t1, mask); | |
b6abf97d FB |
1561 | |
1562 | /* Must test zero case to avoid using undefined behaviour in TCG | |
1563 | shifts. */ | |
1564 | label1 = gen_new_label(); | |
1e4840bf | 1565 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1); |
b6abf97d FB |
1566 | |
1567 | if (ot <= OT_WORD) | |
1e4840bf | 1568 | tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); |
b6abf97d | 1569 | else |
1e4840bf | 1570 | tcg_gen_mov_tl(cpu_tmp0, t1); |
b6abf97d | 1571 | |
1e4840bf FB |
1572 | gen_extu(ot, t0); |
1573 | tcg_gen_mov_tl(t2, t0); | |
b6abf97d FB |
1574 | |
1575 | data_bits = 8 << ot; | |
1576 | /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX: | |
1577 | fix TCG definition) */ | |
1578 | if (is_right) { | |
1e4840bf | 1579 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1580 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1581 | tcg_gen_shl_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1582 | } else { |
1e4840bf | 1583 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1584 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1585 | tcg_gen_shr_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1586 | } |
1e4840bf | 1587 | tcg_gen_or_tl(t0, t0, cpu_tmp4); |
b6abf97d FB |
1588 | |
1589 | gen_set_label(label1); | |
1590 | /* store */ | |
1e4840bf FB |
1591 | if (op1 == OR_TMP0) { |
1592 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1593 | } else { | |
1594 | gen_op_mov_reg_v(ot, op1, t0); | |
1595 | } | |
b6abf97d | 1596 | |
0ff6addd | 1597 | /* update eflags. It is needed anyway most of the time, do it always. */ |
c7b3c873 PB |
1598 | gen_compute_eflags(s, cpu_cc_src); |
1599 | assert(s->cc_op == CC_OP_EFLAGS); | |
b6abf97d FB |
1600 | |
1601 | label2 = gen_new_label(); | |
1e4840bf | 1602 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2); |
b6abf97d | 1603 | |
b6abf97d | 1604 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
1e4840bf | 1605 | tcg_gen_xor_tl(cpu_tmp0, t2, t0); |
b6abf97d FB |
1606 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
1607 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1608 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1609 | if (is_right) { | |
1e4840bf | 1610 | tcg_gen_shri_tl(t0, t0, data_bits - 1); |
b6abf97d | 1611 | } |
1e4840bf FB |
1612 | tcg_gen_andi_tl(t0, t0, CC_C); |
1613 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
0ff6addd | 1614 | |
b6abf97d | 1615 | gen_set_label(label2); |
1e4840bf FB |
1616 | |
1617 | tcg_temp_free(t0); | |
1618 | tcg_temp_free(t1); | |
1619 | tcg_temp_free(t2); | |
1620 | tcg_temp_free(a0); | |
b6abf97d FB |
1621 | } |
1622 | ||
8cd6345d | 1623 | static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, |
1624 | int is_right) | |
1625 | { | |
1626 | int mask; | |
1627 | int data_bits; | |
1628 | TCGv t0, t1, a0; | |
1629 | ||
1630 | /* XXX: inefficient, but we must use local temps */ | |
1631 | t0 = tcg_temp_local_new(); | |
1632 | t1 = tcg_temp_local_new(); | |
1633 | a0 = tcg_temp_local_new(); | |
1634 | ||
1635 | if (ot == OT_QUAD) | |
1636 | mask = 0x3f; | |
1637 | else | |
1638 | mask = 0x1f; | |
1639 | ||
1640 | /* load */ | |
1641 | if (op1 == OR_TMP0) { | |
1642 | tcg_gen_mov_tl(a0, cpu_A0); | |
1643 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1644 | } else { | |
1645 | gen_op_mov_v_reg(ot, t0, op1); | |
1646 | } | |
1647 | ||
1648 | gen_extu(ot, t0); | |
1649 | tcg_gen_mov_tl(t1, t0); | |
1650 | ||
1651 | op2 &= mask; | |
1652 | data_bits = 8 << ot; | |
1653 | if (op2 != 0) { | |
1654 | int shift = op2 & ((1 << (3 + ot)) - 1); | |
1655 | if (is_right) { | |
1656 | tcg_gen_shri_tl(cpu_tmp4, t0, shift); | |
1657 | tcg_gen_shli_tl(t0, t0, data_bits - shift); | |
1658 | } | |
1659 | else { | |
1660 | tcg_gen_shli_tl(cpu_tmp4, t0, shift); | |
1661 | tcg_gen_shri_tl(t0, t0, data_bits - shift); | |
1662 | } | |
1663 | tcg_gen_or_tl(t0, t0, cpu_tmp4); | |
1664 | } | |
1665 | ||
1666 | /* store */ | |
1667 | if (op1 == OR_TMP0) { | |
1668 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1669 | } else { | |
1670 | gen_op_mov_reg_v(ot, op1, t0); | |
1671 | } | |
1672 | ||
1673 | if (op2 != 0) { | |
1674 | /* update eflags */ | |
c7b3c873 PB |
1675 | gen_compute_eflags(s, cpu_cc_src); |
1676 | assert(s->cc_op == CC_OP_EFLAGS); | |
0ff6addd | 1677 | |
8cd6345d | 1678 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
1679 | tcg_gen_xor_tl(cpu_tmp0, t1, t0); | |
1680 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); | |
1681 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1682 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1683 | if (is_right) { | |
1684 | tcg_gen_shri_tl(t0, t0, data_bits - 1); | |
1685 | } | |
1686 | tcg_gen_andi_tl(t0, t0, CC_C); | |
1687 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
8cd6345d | 1688 | } |
1689 | ||
1690 | tcg_temp_free(t0); | |
1691 | tcg_temp_free(t1); | |
1692 | tcg_temp_free(a0); | |
1693 | } | |
1694 | ||
b6abf97d FB |
1695 | /* XXX: add faster immediate = 1 case */ |
1696 | static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, | |
1697 | int is_right) | |
1698 | { | |
773cdfcc | 1699 | gen_update_cc_op(s); |
c7b3c873 PB |
1700 | gen_compute_eflags(s, cpu_cc_src); |
1701 | assert(s->cc_op == CC_OP_EFLAGS); | |
b6abf97d FB |
1702 | |
1703 | /* load */ | |
1704 | if (op1 == OR_TMP0) | |
1705 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1706 | else | |
1707 | gen_op_mov_TN_reg(ot, 0, op1); | |
1708 | ||
a7812ae4 PB |
1709 | if (is_right) { |
1710 | switch (ot) { | |
93ab25d7 | 1711 | case OT_BYTE: |
7923057b BS |
1712 | gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1713 | break; | |
93ab25d7 | 1714 | case OT_WORD: |
7923057b BS |
1715 | gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1716 | break; | |
93ab25d7 | 1717 | case OT_LONG: |
7923057b BS |
1718 | gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1719 | break; | |
a7812ae4 | 1720 | #ifdef TARGET_X86_64 |
93ab25d7 | 1721 | case OT_QUAD: |
7923057b BS |
1722 | gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1723 | break; | |
a7812ae4 PB |
1724 | #endif |
1725 | } | |
1726 | } else { | |
1727 | switch (ot) { | |
93ab25d7 | 1728 | case OT_BYTE: |
7923057b BS |
1729 | gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1730 | break; | |
93ab25d7 | 1731 | case OT_WORD: |
7923057b BS |
1732 | gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1733 | break; | |
93ab25d7 | 1734 | case OT_LONG: |
7923057b BS |
1735 | gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1736 | break; | |
a7812ae4 | 1737 | #ifdef TARGET_X86_64 |
93ab25d7 | 1738 | case OT_QUAD: |
7923057b BS |
1739 | gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1740 | break; | |
a7812ae4 PB |
1741 | #endif |
1742 | } | |
1743 | } | |
b6abf97d FB |
1744 | /* store */ |
1745 | if (op1 == OR_TMP0) | |
1746 | gen_op_st_T0_A0(ot + s->mem_index); | |
1747 | else | |
1748 | gen_op_mov_reg_T0(ot, op1); | |
b6abf97d FB |
1749 | } |
1750 | ||
1751 | /* XXX: add faster immediate case */ | |
1752 | static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, | |
1753 | int is_right) | |
1754 | { | |
1755 | int label1, label2, data_bits; | |
1756 | target_ulong mask; | |
1e4840bf FB |
1757 | TCGv t0, t1, t2, a0; |
1758 | ||
a7812ae4 PB |
1759 | t0 = tcg_temp_local_new(); |
1760 | t1 = tcg_temp_local_new(); | |
1761 | t2 = tcg_temp_local_new(); | |
1762 | a0 = tcg_temp_local_new(); | |
b6abf97d FB |
1763 | |
1764 | if (ot == OT_QUAD) | |
1765 | mask = 0x3f; | |
1766 | else | |
1767 | mask = 0x1f; | |
1768 | ||
1769 | /* load */ | |
1e4840bf FB |
1770 | if (op1 == OR_TMP0) { |
1771 | tcg_gen_mov_tl(a0, cpu_A0); | |
1772 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1773 | } else { | |
1774 | gen_op_mov_v_reg(ot, t0, op1); | |
1775 | } | |
b6abf97d FB |
1776 | |
1777 | tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); | |
1e4840bf FB |
1778 | |
1779 | tcg_gen_mov_tl(t1, cpu_T[1]); | |
1780 | tcg_gen_mov_tl(t2, cpu_T3); | |
1781 | ||
b6abf97d FB |
1782 | /* Must test zero case to avoid using undefined behaviour in TCG |
1783 | shifts. */ | |
1784 | label1 = gen_new_label(); | |
1e4840bf | 1785 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); |
b6abf97d | 1786 | |
1e4840bf | 1787 | tcg_gen_addi_tl(cpu_tmp5, t2, -1); |
b6abf97d FB |
1788 | if (ot == OT_WORD) { |
1789 | /* Note: we implement the Intel behaviour for shift count > 16 */ | |
1790 | if (is_right) { | |
1e4840bf FB |
1791 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1792 | tcg_gen_shli_tl(cpu_tmp0, t1, 16); | |
1793 | tcg_gen_or_tl(t0, t0, cpu_tmp0); | |
1794 | tcg_gen_ext32u_tl(t0, t0); | |
b6abf97d | 1795 | |
1e4840bf | 1796 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d FB |
1797 | |
1798 | /* only needed if count > 16, but a test would complicate */ | |
5b207c00 | 1799 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf | 1800 | tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5); |
b6abf97d | 1801 | |
1e4840bf | 1802 | tcg_gen_shr_tl(t0, t0, t2); |
b6abf97d | 1803 | |
1e4840bf | 1804 | tcg_gen_or_tl(t0, t0, cpu_tmp0); |
b6abf97d FB |
1805 | } else { |
1806 | /* XXX: not optimal */ | |
1e4840bf FB |
1807 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1808 | tcg_gen_shli_tl(t1, t1, 16); | |
1809 | tcg_gen_or_tl(t1, t1, t0); | |
1810 | tcg_gen_ext32u_tl(t1, t1); | |
b6abf97d | 1811 | |
1e4840bf | 1812 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
5b207c00 | 1813 | tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5); |
bedda79c AJ |
1814 | tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0); |
1815 | tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5); | |
b6abf97d | 1816 | |
1e4840bf | 1817 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1818 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf FB |
1819 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1820 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1821 | } |
1822 | } else { | |
1823 | data_bits = 8 << ot; | |
1824 | if (is_right) { | |
1825 | if (ot == OT_LONG) | |
1e4840bf | 1826 | tcg_gen_ext32u_tl(t0, t0); |
b6abf97d | 1827 | |
1e4840bf | 1828 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1829 | |
1e4840bf | 1830 | tcg_gen_shr_tl(t0, t0, t2); |
5b207c00 | 1831 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1832 | tcg_gen_shl_tl(t1, t1, cpu_tmp5); |
1833 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1834 | |
1835 | } else { | |
1836 | if (ot == OT_LONG) | |
1e4840bf | 1837 | tcg_gen_ext32u_tl(t1, t1); |
b6abf97d | 1838 | |
1e4840bf | 1839 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1840 | |
1e4840bf | 1841 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1842 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1843 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1844 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1845 | } |
1846 | } | |
1e4840bf | 1847 | tcg_gen_mov_tl(t1, cpu_tmp4); |
b6abf97d FB |
1848 | |
1849 | gen_set_label(label1); | |
1850 | /* store */ | |
1e4840bf FB |
1851 | if (op1 == OR_TMP0) { |
1852 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1853 | } else { | |
1854 | gen_op_mov_reg_v(ot, op1, t0); | |
1855 | } | |
b6abf97d FB |
1856 | |
1857 | /* update eflags */ | |
773cdfcc | 1858 | gen_update_cc_op(s); |
b6abf97d FB |
1859 | |
1860 | label2 = gen_new_label(); | |
1e4840bf | 1861 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2); |
b6abf97d | 1862 | |
1e4840bf FB |
1863 | tcg_gen_mov_tl(cpu_cc_src, t1); |
1864 | tcg_gen_mov_tl(cpu_cc_dst, t0); | |
b6abf97d FB |
1865 | if (is_right) { |
1866 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); | |
1867 | } else { | |
1868 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); | |
1869 | } | |
1870 | gen_set_label(label2); | |
3ca51d07 | 1871 | set_cc_op(s, CC_OP_DYNAMIC); /* cannot predict flags after */ |
1e4840bf FB |
1872 | |
1873 | tcg_temp_free(t0); | |
1874 | tcg_temp_free(t1); | |
1875 | tcg_temp_free(t2); | |
1876 | tcg_temp_free(a0); | |
b6abf97d FB |
1877 | } |
1878 | ||
1879 | static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) | |
1880 | { | |
1881 | if (s != OR_TMP1) | |
1882 | gen_op_mov_TN_reg(ot, 1, s); | |
1883 | switch(op) { | |
1884 | case OP_ROL: | |
1885 | gen_rot_rm_T1(s1, ot, d, 0); | |
1886 | break; | |
1887 | case OP_ROR: | |
1888 | gen_rot_rm_T1(s1, ot, d, 1); | |
1889 | break; | |
1890 | case OP_SHL: | |
1891 | case OP_SHL1: | |
1892 | gen_shift_rm_T1(s1, ot, d, 0, 0); | |
1893 | break; | |
1894 | case OP_SHR: | |
1895 | gen_shift_rm_T1(s1, ot, d, 1, 0); | |
1896 | break; | |
1897 | case OP_SAR: | |
1898 | gen_shift_rm_T1(s1, ot, d, 1, 1); | |
1899 | break; | |
1900 | case OP_RCL: | |
1901 | gen_rotc_rm_T1(s1, ot, d, 0); | |
1902 | break; | |
1903 | case OP_RCR: | |
1904 | gen_rotc_rm_T1(s1, ot, d, 1); | |
1905 | break; | |
1906 | } | |
2c0262af FB |
1907 | } |
1908 | ||
1909 | static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) | |
1910 | { | |
c1c37968 | 1911 | switch(op) { |
8cd6345d | 1912 | case OP_ROL: |
1913 | gen_rot_rm_im(s1, ot, d, c, 0); | |
1914 | break; | |
1915 | case OP_ROR: | |
1916 | gen_rot_rm_im(s1, ot, d, c, 1); | |
1917 | break; | |
c1c37968 FB |
1918 | case OP_SHL: |
1919 | case OP_SHL1: | |
1920 | gen_shift_rm_im(s1, ot, d, c, 0, 0); | |
1921 | break; | |
1922 | case OP_SHR: | |
1923 | gen_shift_rm_im(s1, ot, d, c, 1, 0); | |
1924 | break; | |
1925 | case OP_SAR: | |
1926 | gen_shift_rm_im(s1, ot, d, c, 1, 1); | |
1927 | break; | |
1928 | default: | |
1929 | /* currently not optimized */ | |
1930 | gen_op_movl_T1_im(c); | |
1931 | gen_shift(s1, op, ot, d, OR_TMP1); | |
1932 | break; | |
1933 | } | |
2c0262af FB |
1934 | } |
1935 | ||
0af10c86 BS |
1936 | static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm, |
1937 | int *reg_ptr, int *offset_ptr) | |
2c0262af | 1938 | { |
14ce26e7 | 1939 | target_long disp; |
2c0262af | 1940 | int havesib; |
14ce26e7 | 1941 | int base; |
2c0262af FB |
1942 | int index; |
1943 | int scale; | |
1944 | int opreg; | |
1945 | int mod, rm, code, override, must_add_seg; | |
1946 | ||
1947 | override = s->override; | |
1948 | must_add_seg = s->addseg; | |
1949 | if (override >= 0) | |
1950 | must_add_seg = 1; | |
1951 | mod = (modrm >> 6) & 3; | |
1952 | rm = modrm & 7; | |
1953 | ||
1954 | if (s->aflag) { | |
1955 | ||
1956 | havesib = 0; | |
1957 | base = rm; | |
1958 | index = 0; | |
1959 | scale = 0; | |
3b46e624 | 1960 | |
2c0262af FB |
1961 | if (base == 4) { |
1962 | havesib = 1; | |
0af10c86 | 1963 | code = cpu_ldub_code(env, s->pc++); |
2c0262af | 1964 | scale = (code >> 6) & 3; |
14ce26e7 FB |
1965 | index = ((code >> 3) & 7) | REX_X(s); |
1966 | base = (code & 7); | |
2c0262af | 1967 | } |
14ce26e7 | 1968 | base |= REX_B(s); |
2c0262af FB |
1969 | |
1970 | switch (mod) { | |
1971 | case 0: | |
14ce26e7 | 1972 | if ((base & 7) == 5) { |
2c0262af | 1973 | base = -1; |
0af10c86 | 1974 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af | 1975 | s->pc += 4; |
14ce26e7 FB |
1976 | if (CODE64(s) && !havesib) { |
1977 | disp += s->pc + s->rip_offset; | |
1978 | } | |
2c0262af FB |
1979 | } else { |
1980 | disp = 0; | |
1981 | } | |
1982 | break; | |
1983 | case 1: | |
0af10c86 | 1984 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
1985 | break; |
1986 | default: | |
1987 | case 2: | |
0af10c86 | 1988 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af FB |
1989 | s->pc += 4; |
1990 | break; | |
1991 | } | |
3b46e624 | 1992 | |
2c0262af FB |
1993 | if (base >= 0) { |
1994 | /* for correct popl handling with esp */ | |
1995 | if (base == 4 && s->popl_esp_hack) | |
1996 | disp += s->popl_esp_hack; | |
14ce26e7 FB |
1997 | #ifdef TARGET_X86_64 |
1998 | if (s->aflag == 2) { | |
57fec1fe | 1999 | gen_op_movq_A0_reg(base); |
14ce26e7 | 2000 | if (disp != 0) { |
57fec1fe | 2001 | gen_op_addq_A0_im(disp); |
14ce26e7 | 2002 | } |
5fafdf24 | 2003 | } else |
14ce26e7 FB |
2004 | #endif |
2005 | { | |
57fec1fe | 2006 | gen_op_movl_A0_reg(base); |
14ce26e7 FB |
2007 | if (disp != 0) |
2008 | gen_op_addl_A0_im(disp); | |
2009 | } | |
2c0262af | 2010 | } else { |
14ce26e7 FB |
2011 | #ifdef TARGET_X86_64 |
2012 | if (s->aflag == 2) { | |
57fec1fe | 2013 | gen_op_movq_A0_im(disp); |
5fafdf24 | 2014 | } else |
14ce26e7 FB |
2015 | #endif |
2016 | { | |
2017 | gen_op_movl_A0_im(disp); | |
2018 | } | |
2c0262af | 2019 | } |
b16f827b AJ |
2020 | /* index == 4 means no index */ |
2021 | if (havesib && (index != 4)) { | |
14ce26e7 FB |
2022 | #ifdef TARGET_X86_64 |
2023 | if (s->aflag == 2) { | |
57fec1fe | 2024 | gen_op_addq_A0_reg_sN(scale, index); |
5fafdf24 | 2025 | } else |
14ce26e7 FB |
2026 | #endif |
2027 | { | |
57fec1fe | 2028 | gen_op_addl_A0_reg_sN(scale, index); |
14ce26e7 | 2029 | } |
2c0262af FB |
2030 | } |
2031 | if (must_add_seg) { | |
2032 | if (override < 0) { | |
2033 | if (base == R_EBP || base == R_ESP) | |
2034 | override = R_SS; | |
2035 | else | |
2036 | override = R_DS; | |
2037 | } | |
14ce26e7 FB |
2038 | #ifdef TARGET_X86_64 |
2039 | if (s->aflag == 2) { | |
57fec1fe | 2040 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2041 | } else |
14ce26e7 FB |
2042 | #endif |
2043 | { | |
7162ab21 | 2044 | gen_op_addl_A0_seg(s, override); |
14ce26e7 | 2045 | } |
2c0262af FB |
2046 | } |
2047 | } else { | |
2048 | switch (mod) { | |
2049 | case 0: | |
2050 | if (rm == 6) { | |
0af10c86 | 2051 | disp = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2052 | s->pc += 2; |
2053 | gen_op_movl_A0_im(disp); | |
2054 | rm = 0; /* avoid SS override */ | |
2055 | goto no_rm; | |
2056 | } else { | |
2057 | disp = 0; | |
2058 | } | |
2059 | break; | |
2060 | case 1: | |
0af10c86 | 2061 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
2062 | break; |
2063 | default: | |
2064 | case 2: | |
0af10c86 | 2065 | disp = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2066 | s->pc += 2; |
2067 | break; | |
2068 | } | |
2069 | switch(rm) { | |
2070 | case 0: | |
57fec1fe FB |
2071 | gen_op_movl_A0_reg(R_EBX); |
2072 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2073 | break; |
2074 | case 1: | |
57fec1fe FB |
2075 | gen_op_movl_A0_reg(R_EBX); |
2076 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2077 | break; |
2078 | case 2: | |
57fec1fe FB |
2079 | gen_op_movl_A0_reg(R_EBP); |
2080 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2081 | break; |
2082 | case 3: | |
57fec1fe FB |
2083 | gen_op_movl_A0_reg(R_EBP); |
2084 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2085 | break; |
2086 | case 4: | |
57fec1fe | 2087 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
2088 | break; |
2089 | case 5: | |
57fec1fe | 2090 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
2091 | break; |
2092 | case 6: | |
57fec1fe | 2093 | gen_op_movl_A0_reg(R_EBP); |
2c0262af FB |
2094 | break; |
2095 | default: | |
2096 | case 7: | |
57fec1fe | 2097 | gen_op_movl_A0_reg(R_EBX); |
2c0262af FB |
2098 | break; |
2099 | } | |
2100 | if (disp != 0) | |
2101 | gen_op_addl_A0_im(disp); | |
2102 | gen_op_andl_A0_ffff(); | |
2103 | no_rm: | |
2104 | if (must_add_seg) { | |
2105 | if (override < 0) { | |
2106 | if (rm == 2 || rm == 3 || rm == 6) | |
2107 | override = R_SS; | |
2108 | else | |
2109 | override = R_DS; | |
2110 | } | |
7162ab21 | 2111 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
2112 | } |
2113 | } | |
2114 | ||
2115 | opreg = OR_A0; | |
2116 | disp = 0; | |
2117 | *reg_ptr = opreg; | |
2118 | *offset_ptr = disp; | |
2119 | } | |
2120 | ||
0af10c86 | 2121 | static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) |
e17a36ce FB |
2122 | { |
2123 | int mod, rm, base, code; | |
2124 | ||
2125 | mod = (modrm >> 6) & 3; | |
2126 | if (mod == 3) | |
2127 | return; | |
2128 | rm = modrm & 7; | |
2129 | ||
2130 | if (s->aflag) { | |
2131 | ||
2132 | base = rm; | |
3b46e624 | 2133 | |
e17a36ce | 2134 | if (base == 4) { |
0af10c86 | 2135 | code = cpu_ldub_code(env, s->pc++); |
e17a36ce FB |
2136 | base = (code & 7); |
2137 | } | |
3b46e624 | 2138 | |
e17a36ce FB |
2139 | switch (mod) { |
2140 | case 0: | |
2141 | if (base == 5) { | |
2142 | s->pc += 4; | |
2143 | } | |
2144 | break; | |
2145 | case 1: | |
2146 | s->pc++; | |
2147 | break; | |
2148 | default: | |
2149 | case 2: | |
2150 | s->pc += 4; | |
2151 | break; | |
2152 | } | |
2153 | } else { | |
2154 | switch (mod) { | |
2155 | case 0: | |
2156 | if (rm == 6) { | |
2157 | s->pc += 2; | |
2158 | } | |
2159 | break; | |
2160 | case 1: | |
2161 | s->pc++; | |
2162 | break; | |
2163 | default: | |
2164 | case 2: | |
2165 | s->pc += 2; | |
2166 | break; | |
2167 | } | |
2168 | } | |
2169 | } | |
2170 | ||
664e0f19 FB |
2171 | /* used for LEA and MOV AX, mem */ |
2172 | static void gen_add_A0_ds_seg(DisasContext *s) | |
2173 | { | |
2174 | int override, must_add_seg; | |
2175 | must_add_seg = s->addseg; | |
2176 | override = R_DS; | |
2177 | if (s->override >= 0) { | |
2178 | override = s->override; | |
2179 | must_add_seg = 1; | |
664e0f19 FB |
2180 | } |
2181 | if (must_add_seg) { | |
8f091a59 FB |
2182 | #ifdef TARGET_X86_64 |
2183 | if (CODE64(s)) { | |
57fec1fe | 2184 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2185 | } else |
8f091a59 FB |
2186 | #endif |
2187 | { | |
7162ab21 | 2188 | gen_op_addl_A0_seg(s, override); |
8f091a59 | 2189 | } |
664e0f19 FB |
2190 | } |
2191 | } | |
2192 | ||
222a3336 | 2193 | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == |
2c0262af | 2194 | OR_TMP0 */ |
0af10c86 BS |
2195 | static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, |
2196 | int ot, int reg, int is_store) | |
2c0262af FB |
2197 | { |
2198 | int mod, rm, opreg, disp; | |
2199 | ||
2200 | mod = (modrm >> 6) & 3; | |
14ce26e7 | 2201 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
2202 | if (mod == 3) { |
2203 | if (is_store) { | |
2204 | if (reg != OR_TMP0) | |
57fec1fe FB |
2205 | gen_op_mov_TN_reg(ot, 0, reg); |
2206 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 2207 | } else { |
57fec1fe | 2208 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 2209 | if (reg != OR_TMP0) |
57fec1fe | 2210 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2211 | } |
2212 | } else { | |
0af10c86 | 2213 | gen_lea_modrm(env, s, modrm, &opreg, &disp); |
2c0262af FB |
2214 | if (is_store) { |
2215 | if (reg != OR_TMP0) | |
57fec1fe FB |
2216 | gen_op_mov_TN_reg(ot, 0, reg); |
2217 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 2218 | } else { |
57fec1fe | 2219 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 2220 | if (reg != OR_TMP0) |
57fec1fe | 2221 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2222 | } |
2223 | } | |
2224 | } | |
2225 | ||
0af10c86 | 2226 | static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot) |
2c0262af FB |
2227 | { |
2228 | uint32_t ret; | |
2229 | ||
2230 | switch(ot) { | |
2231 | case OT_BYTE: | |
0af10c86 | 2232 | ret = cpu_ldub_code(env, s->pc); |
2c0262af FB |
2233 | s->pc++; |
2234 | break; | |
2235 | case OT_WORD: | |
0af10c86 | 2236 | ret = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2237 | s->pc += 2; |
2238 | break; | |
2239 | default: | |
2240 | case OT_LONG: | |
0af10c86 | 2241 | ret = cpu_ldl_code(env, s->pc); |
2c0262af FB |
2242 | s->pc += 4; |
2243 | break; | |
2244 | } | |
2245 | return ret; | |
2246 | } | |
2247 | ||
14ce26e7 FB |
2248 | static inline int insn_const_size(unsigned int ot) |
2249 | { | |
2250 | if (ot <= OT_LONG) | |
2251 | return 1 << ot; | |
2252 | else | |
2253 | return 4; | |
2254 | } | |
2255 | ||
6e256c93 FB |
2256 | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2257 | { | |
2258 | TranslationBlock *tb; | |
2259 | target_ulong pc; | |
2260 | ||
2261 | pc = s->cs_base + eip; | |
2262 | tb = s->tb; | |
2263 | /* NOTE: we handle the case where the TB spans two pages here */ | |
2264 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) || | |
2265 | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { | |
2266 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 2267 | tcg_gen_goto_tb(tb_num); |
6e256c93 | 2268 | gen_jmp_im(eip); |
4b4a72e5 | 2269 | tcg_gen_exit_tb((tcg_target_long)tb + tb_num); |
6e256c93 FB |
2270 | } else { |
2271 | /* jump to another page: currently not optimized */ | |
2272 | gen_jmp_im(eip); | |
2273 | gen_eob(s); | |
2274 | } | |
2275 | } | |
2276 | ||
5fafdf24 | 2277 | static inline void gen_jcc(DisasContext *s, int b, |
14ce26e7 | 2278 | target_ulong val, target_ulong next_eip) |
2c0262af | 2279 | { |
b27fc131 | 2280 | int l1, l2; |
3b46e624 | 2281 | |
773cdfcc | 2282 | gen_update_cc_op(s); |
2c0262af | 2283 | if (s->jmp_opt) { |
14ce26e7 | 2284 | l1 = gen_new_label(); |
b27fc131 | 2285 | gen_jcc1(s, b, l1); |
3ca51d07 | 2286 | set_cc_op(s, CC_OP_DYNAMIC); |
8e1c85e3 | 2287 | |
6e256c93 | 2288 | gen_goto_tb(s, 0, next_eip); |
14ce26e7 FB |
2289 | |
2290 | gen_set_label(l1); | |
6e256c93 | 2291 | gen_goto_tb(s, 1, val); |
5779406a | 2292 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2293 | } else { |
14ce26e7 | 2294 | |
14ce26e7 FB |
2295 | l1 = gen_new_label(); |
2296 | l2 = gen_new_label(); | |
b27fc131 | 2297 | gen_jcc1(s, b, l1); |
3ca51d07 | 2298 | set_cc_op(s, CC_OP_DYNAMIC); |
8e1c85e3 | 2299 | |
14ce26e7 | 2300 | gen_jmp_im(next_eip); |
8e1c85e3 FB |
2301 | tcg_gen_br(l2); |
2302 | ||
14ce26e7 FB |
2303 | gen_set_label(l1); |
2304 | gen_jmp_im(val); | |
2305 | gen_set_label(l2); | |
2c0262af FB |
2306 | gen_eob(s); |
2307 | } | |
2308 | } | |
2309 | ||
2310 | static void gen_setcc(DisasContext *s, int b) | |
2311 | { | |
8e1c85e3 | 2312 | int inv, jcc_op, l1; |
1e4840bf | 2313 | TCGv t0; |
14ce26e7 | 2314 | |
8e1c85e3 FB |
2315 | if (is_fast_jcc_case(s, b)) { |
2316 | /* nominal case: we use a jump */ | |
1e4840bf | 2317 | /* XXX: make it faster by adding new instructions in TCG */ |
a7812ae4 | 2318 | t0 = tcg_temp_local_new(); |
1e4840bf | 2319 | tcg_gen_movi_tl(t0, 0); |
8e1c85e3 | 2320 | l1 = gen_new_label(); |
b27fc131 | 2321 | gen_jcc1(s, b ^ 1, l1); |
1e4840bf | 2322 | tcg_gen_movi_tl(t0, 1); |
8e1c85e3 | 2323 | gen_set_label(l1); |
1e4840bf FB |
2324 | tcg_gen_mov_tl(cpu_T[0], t0); |
2325 | tcg_temp_free(t0); | |
8e1c85e3 FB |
2326 | } else { |
2327 | /* slow case: it is more efficient not to generate a jump, | |
2328 | although it is questionnable whether this optimization is | |
2329 | worth to */ | |
2330 | inv = b & 1; | |
2331 | jcc_op = (b >> 1) & 7; | |
1e4840bf | 2332 | gen_setcc_slow_T0(s, jcc_op); |
8e1c85e3 FB |
2333 | if (inv) { |
2334 | tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1); | |
2335 | } | |
2c0262af FB |
2336 | } |
2337 | } | |
2338 | ||
3bd7da9e FB |
2339 | static inline void gen_op_movl_T0_seg(int seg_reg) |
2340 | { | |
2341 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, | |
2342 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2343 | } | |
2344 | ||
2345 | static inline void gen_op_movl_seg_T0_vm(int seg_reg) | |
2346 | { | |
2347 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
2348 | tcg_gen_st32_tl(cpu_T[0], cpu_env, | |
2349 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2350 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); | |
2351 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
2352 | offsetof(CPUX86State,segs[seg_reg].base)); | |
2353 | } | |
2354 | ||
2c0262af FB |
2355 | /* move T0 to seg_reg and compute if the CPU state may change. Never |
2356 | call this function with seg_reg == R_CS */ | |
14ce26e7 | 2357 | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2c0262af | 2358 | { |
3415a4dd FB |
2359 | if (s->pe && !s->vm86) { |
2360 | /* XXX: optimize by finding processor state dynamically */ | |
773cdfcc | 2361 | gen_update_cc_op(s); |
14ce26e7 | 2362 | gen_jmp_im(cur_eip); |
b6abf97d | 2363 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 2364 | gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32); |
dc196a57 FB |
2365 | /* abort translation because the addseg value may change or |
2366 | because ss32 may change. For R_SS, translation must always | |
2367 | stop as a special handling must be done to disable hardware | |
2368 | interrupts for the next instruction */ | |
2369 | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) | |
5779406a | 2370 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2371 | } else { |
3bd7da9e | 2372 | gen_op_movl_seg_T0_vm(seg_reg); |
dc196a57 | 2373 | if (seg_reg == R_SS) |
5779406a | 2374 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2375 | } |
2c0262af FB |
2376 | } |
2377 | ||
0573fbfc TS |
2378 | static inline int svm_is_rep(int prefixes) |
2379 | { | |
2380 | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); | |
2381 | } | |
2382 | ||
872929aa | 2383 | static inline void |
0573fbfc | 2384 | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
b8b6a50b | 2385 | uint32_t type, uint64_t param) |
0573fbfc | 2386 | { |
872929aa FB |
2387 | /* no SVM activated; fast case */ |
2388 | if (likely(!(s->flags & HF_SVMI_MASK))) | |
2389 | return; | |
773cdfcc | 2390 | gen_update_cc_op(s); |
872929aa | 2391 | gen_jmp_im(pc_start - s->cs_base); |
052e80d5 | 2392 | gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), |
a7812ae4 | 2393 | tcg_const_i64(param)); |
0573fbfc TS |
2394 | } |
2395 | ||
872929aa | 2396 | static inline void |
0573fbfc TS |
2397 | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2398 | { | |
872929aa | 2399 | gen_svm_check_intercept_param(s, pc_start, type, 0); |
0573fbfc TS |
2400 | } |
2401 | ||
4f31916f FB |
2402 | static inline void gen_stack_update(DisasContext *s, int addend) |
2403 | { | |
14ce26e7 FB |
2404 | #ifdef TARGET_X86_64 |
2405 | if (CODE64(s)) { | |
6e0d8677 | 2406 | gen_op_add_reg_im(2, R_ESP, addend); |
14ce26e7 FB |
2407 | } else |
2408 | #endif | |
4f31916f | 2409 | if (s->ss32) { |
6e0d8677 | 2410 | gen_op_add_reg_im(1, R_ESP, addend); |
4f31916f | 2411 | } else { |
6e0d8677 | 2412 | gen_op_add_reg_im(0, R_ESP, addend); |
4f31916f FB |
2413 | } |
2414 | } | |
2415 | ||
2c0262af FB |
2416 | /* generate a push. It depends on ss32, addseg and dflag */ |
2417 | static void gen_push_T0(DisasContext *s) | |
2418 | { | |
14ce26e7 FB |
2419 | #ifdef TARGET_X86_64 |
2420 | if (CODE64(s)) { | |
57fec1fe | 2421 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2422 | if (s->dflag) { |
57fec1fe FB |
2423 | gen_op_addq_A0_im(-8); |
2424 | gen_op_st_T0_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2425 | } else { |
57fec1fe FB |
2426 | gen_op_addq_A0_im(-2); |
2427 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2428 | } |
57fec1fe | 2429 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2430 | } else |
14ce26e7 FB |
2431 | #endif |
2432 | { | |
57fec1fe | 2433 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2434 | if (!s->dflag) |
57fec1fe | 2435 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2436 | else |
57fec1fe | 2437 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2438 | if (s->ss32) { |
2439 | if (s->addseg) { | |
bbf662ee | 2440 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2441 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2442 | } |
2443 | } else { | |
2444 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2445 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2446 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2447 | } |
57fec1fe | 2448 | gen_op_st_T0_A0(s->dflag + 1 + s->mem_index); |
14ce26e7 | 2449 | if (s->ss32 && !s->addseg) |
57fec1fe | 2450 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 | 2451 | else |
57fec1fe | 2452 | gen_op_mov_reg_T1(s->ss32 + 1, R_ESP); |
2c0262af FB |
2453 | } |
2454 | } | |
2455 | ||
4f31916f FB |
2456 | /* generate a push. It depends on ss32, addseg and dflag */ |
2457 | /* slower version for T1, only used for call Ev */ | |
2458 | static void gen_push_T1(DisasContext *s) | |
2c0262af | 2459 | { |
14ce26e7 FB |
2460 | #ifdef TARGET_X86_64 |
2461 | if (CODE64(s)) { | |
57fec1fe | 2462 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2463 | if (s->dflag) { |
57fec1fe FB |
2464 | gen_op_addq_A0_im(-8); |
2465 | gen_op_st_T1_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2466 | } else { |
57fec1fe FB |
2467 | gen_op_addq_A0_im(-2); |
2468 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2469 | } |
57fec1fe | 2470 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2471 | } else |
14ce26e7 FB |
2472 | #endif |
2473 | { | |
57fec1fe | 2474 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2475 | if (!s->dflag) |
57fec1fe | 2476 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2477 | else |
57fec1fe | 2478 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2479 | if (s->ss32) { |
2480 | if (s->addseg) { | |
7162ab21 | 2481 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2482 | } |
2483 | } else { | |
2484 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2485 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2486 | } |
57fec1fe | 2487 | gen_op_st_T1_A0(s->dflag + 1 + s->mem_index); |
3b46e624 | 2488 | |
14ce26e7 | 2489 | if (s->ss32 && !s->addseg) |
57fec1fe | 2490 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 FB |
2491 | else |
2492 | gen_stack_update(s, (-2) << s->dflag); | |
2c0262af FB |
2493 | } |
2494 | } | |
2495 | ||
4f31916f FB |
2496 | /* two step pop is necessary for precise exceptions */ |
2497 | static void gen_pop_T0(DisasContext *s) | |
2c0262af | 2498 | { |
14ce26e7 FB |
2499 | #ifdef TARGET_X86_64 |
2500 | if (CODE64(s)) { | |
57fec1fe FB |
2501 | gen_op_movq_A0_reg(R_ESP); |
2502 | gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index); | |
5fafdf24 | 2503 | } else |
14ce26e7 FB |
2504 | #endif |
2505 | { | |
57fec1fe | 2506 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 FB |
2507 | if (s->ss32) { |
2508 | if (s->addseg) | |
7162ab21 | 2509 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2510 | } else { |
2511 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2512 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 | 2513 | } |
57fec1fe | 2514 | gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index); |
2c0262af FB |
2515 | } |
2516 | } | |
2517 | ||
2518 | static void gen_pop_update(DisasContext *s) | |
2519 | { | |
14ce26e7 | 2520 | #ifdef TARGET_X86_64 |
8f091a59 | 2521 | if (CODE64(s) && s->dflag) { |
14ce26e7 FB |
2522 | gen_stack_update(s, 8); |
2523 | } else | |
2524 | #endif | |
2525 | { | |
2526 | gen_stack_update(s, 2 << s->dflag); | |
2527 | } | |
2c0262af FB |
2528 | } |
2529 | ||
2530 | static void gen_stack_A0(DisasContext *s) | |
2531 | { | |
57fec1fe | 2532 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2533 | if (!s->ss32) |
2534 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2535 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2536 | if (s->addseg) |
7162ab21 | 2537 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2538 | } |
2539 | ||
2540 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2541 | static void gen_pusha(DisasContext *s) | |
2542 | { | |
2543 | int i; | |
57fec1fe | 2544 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2545 | gen_op_addl_A0_im(-16 << s->dflag); |
2546 | if (!s->ss32) | |
2547 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2548 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2549 | if (s->addseg) |
7162ab21 | 2550 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2551 | for(i = 0;i < 8; i++) { |
57fec1fe FB |
2552 | gen_op_mov_TN_reg(OT_LONG, 0, 7 - i); |
2553 | gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index); | |
2c0262af FB |
2554 | gen_op_addl_A0_im(2 << s->dflag); |
2555 | } | |
57fec1fe | 2556 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2557 | } |
2558 | ||
2559 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2560 | static void gen_popa(DisasContext *s) | |
2561 | { | |
2562 | int i; | |
57fec1fe | 2563 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2564 | if (!s->ss32) |
2565 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
2566 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2567 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); | |
2c0262af | 2568 | if (s->addseg) |
7162ab21 | 2569 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2570 | for(i = 0;i < 8; i++) { |
2571 | /* ESP is not reloaded */ | |
2572 | if (i != 3) { | |
57fec1fe FB |
2573 | gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2574 | gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i); | |
2c0262af FB |
2575 | } |
2576 | gen_op_addl_A0_im(2 << s->dflag); | |
2577 | } | |
57fec1fe | 2578 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2579 | } |
2580 | ||
2c0262af FB |
2581 | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2582 | { | |
61a8c4ec | 2583 | int ot, opsize; |
2c0262af | 2584 | |
2c0262af | 2585 | level &= 0x1f; |
8f091a59 FB |
2586 | #ifdef TARGET_X86_64 |
2587 | if (CODE64(s)) { | |
2588 | ot = s->dflag ? OT_QUAD : OT_WORD; | |
2589 | opsize = 1 << ot; | |
3b46e624 | 2590 | |
57fec1fe | 2591 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 | 2592 | gen_op_addq_A0_im(-opsize); |
bbf662ee | 2593 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 FB |
2594 | |
2595 | /* push bp */ | |
57fec1fe FB |
2596 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2597 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2598 | if (level) { |
b5b38f61 | 2599 | /* XXX: must save state */ |
2999a0b2 | 2600 | gen_helper_enter64_level(cpu_env, tcg_const_i32(level), |
a7812ae4 PB |
2601 | tcg_const_i32((ot == OT_QUAD)), |
2602 | cpu_T[1]); | |
8f091a59 | 2603 | } |
57fec1fe | 2604 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2605 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2606 | gen_op_mov_reg_T1(OT_QUAD, R_ESP); |
5fafdf24 | 2607 | } else |
8f091a59 FB |
2608 | #endif |
2609 | { | |
2610 | ot = s->dflag + OT_WORD; | |
2611 | opsize = 2 << s->dflag; | |
3b46e624 | 2612 | |
57fec1fe | 2613 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 FB |
2614 | gen_op_addl_A0_im(-opsize); |
2615 | if (!s->ss32) | |
2616 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2617 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 | 2618 | if (s->addseg) |
7162ab21 | 2619 | gen_op_addl_A0_seg(s, R_SS); |
8f091a59 | 2620 | /* push bp */ |
57fec1fe FB |
2621 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2622 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2623 | if (level) { |
b5b38f61 | 2624 | /* XXX: must save state */ |
2999a0b2 | 2625 | gen_helper_enter_level(cpu_env, tcg_const_i32(level), |
a7812ae4 PB |
2626 | tcg_const_i32(s->dflag), |
2627 | cpu_T[1]); | |
8f091a59 | 2628 | } |
57fec1fe | 2629 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2630 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2631 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af | 2632 | } |
2c0262af FB |
2633 | } |
2634 | ||
14ce26e7 | 2635 | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2c0262af | 2636 | { |
773cdfcc | 2637 | gen_update_cc_op(s); |
14ce26e7 | 2638 | gen_jmp_im(cur_eip); |
77b2bc2c | 2639 | gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); |
5779406a | 2640 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2641 | } |
2642 | ||
2643 | /* an interrupt is different from an exception because of the | |
7f75ffd3 | 2644 | privilege checks */ |
5fafdf24 | 2645 | static void gen_interrupt(DisasContext *s, int intno, |
14ce26e7 | 2646 | target_ulong cur_eip, target_ulong next_eip) |
2c0262af | 2647 | { |
773cdfcc | 2648 | gen_update_cc_op(s); |
14ce26e7 | 2649 | gen_jmp_im(cur_eip); |
77b2bc2c | 2650 | gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), |
a7812ae4 | 2651 | tcg_const_i32(next_eip - cur_eip)); |
5779406a | 2652 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2653 | } |
2654 | ||
14ce26e7 | 2655 | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2c0262af | 2656 | { |
773cdfcc | 2657 | gen_update_cc_op(s); |
14ce26e7 | 2658 | gen_jmp_im(cur_eip); |
4a7443be | 2659 | gen_helper_debug(cpu_env); |
5779406a | 2660 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2661 | } |
2662 | ||
2663 | /* generate a generic end of block. Trace exception is also generated | |
2664 | if needed */ | |
2665 | static void gen_eob(DisasContext *s) | |
2666 | { | |
773cdfcc | 2667 | gen_update_cc_op(s); |
a2cc3b24 | 2668 | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { |
f0967a1a | 2669 | gen_helper_reset_inhibit_irq(cpu_env); |
a2cc3b24 | 2670 | } |
a2397807 | 2671 | if (s->tb->flags & HF_RF_MASK) { |
f0967a1a | 2672 | gen_helper_reset_rf(cpu_env); |
a2397807 | 2673 | } |
34865134 | 2674 | if (s->singlestep_enabled) { |
4a7443be | 2675 | gen_helper_debug(cpu_env); |
34865134 | 2676 | } else if (s->tf) { |
4a7443be | 2677 | gen_helper_single_step(cpu_env); |
2c0262af | 2678 | } else { |
57fec1fe | 2679 | tcg_gen_exit_tb(0); |
2c0262af | 2680 | } |
5779406a | 2681 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2682 | } |
2683 | ||
2684 | /* generate a jump to eip. No segment change must happen before as a | |
2685 | direct call to the next block may occur */ | |
14ce26e7 | 2686 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2c0262af | 2687 | { |
2c0262af | 2688 | if (s->jmp_opt) { |
728d803b | 2689 | gen_update_cc_op(s); |
6e256c93 | 2690 | gen_goto_tb(s, tb_num, eip); |
5779406a | 2691 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2692 | } else { |
14ce26e7 | 2693 | gen_jmp_im(eip); |
2c0262af FB |
2694 | gen_eob(s); |
2695 | } | |
2696 | } | |
2697 | ||
14ce26e7 FB |
2698 | static void gen_jmp(DisasContext *s, target_ulong eip) |
2699 | { | |
2700 | gen_jmp_tb(s, eip, 0); | |
2701 | } | |
2702 | ||
8686c490 FB |
2703 | static inline void gen_ldq_env_A0(int idx, int offset) |
2704 | { | |
2705 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2706 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2707 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); | |
8686c490 | 2708 | } |
664e0f19 | 2709 | |
8686c490 FB |
2710 | static inline void gen_stq_env_A0(int idx, int offset) |
2711 | { | |
2712 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2713 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
2714 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2715 | } |
664e0f19 | 2716 | |
8686c490 FB |
2717 | static inline void gen_ldo_env_A0(int idx, int offset) |
2718 | { | |
2719 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2720 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2721 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); | |
8686c490 | 2722 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2723 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2724 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); | |
8686c490 | 2725 | } |
14ce26e7 | 2726 | |
8686c490 FB |
2727 | static inline void gen_sto_env_A0(int idx, int offset) |
2728 | { | |
2729 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2730 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
2731 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2732 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2733 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
2734 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index); | |
8686c490 | 2735 | } |
14ce26e7 | 2736 | |
5af45186 FB |
2737 | static inline void gen_op_movo(int d_offset, int s_offset) |
2738 | { | |
b6abf97d FB |
2739 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2740 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
2741 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8); | |
2742 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8); | |
5af45186 FB |
2743 | } |
2744 | ||
2745 | static inline void gen_op_movq(int d_offset, int s_offset) | |
2746 | { | |
b6abf97d FB |
2747 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2748 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 FB |
2749 | } |
2750 | ||
2751 | static inline void gen_op_movl(int d_offset, int s_offset) | |
2752 | { | |
b6abf97d FB |
2753 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2754 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); | |
5af45186 FB |
2755 | } |
2756 | ||
2757 | static inline void gen_op_movq_env_0(int d_offset) | |
2758 | { | |
b6abf97d FB |
2759 | tcg_gen_movi_i64(cpu_tmp1_i64, 0); |
2760 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 | 2761 | } |
664e0f19 | 2762 | |
d3eb5eae BS |
2763 | typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg); |
2764 | typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg); | |
2765 | typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val); | |
2766 | typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val); | |
2767 | typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b); | |
2768 | typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, | |
2769 | TCGv_i32 val); | |
c4baa050 | 2770 | typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val); |
d3eb5eae BS |
2771 | typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, |
2772 | TCGv val); | |
c4baa050 | 2773 | |
5af45186 FB |
2774 | #define SSE_SPECIAL ((void *)1) |
2775 | #define SSE_DUMMY ((void *)2) | |
664e0f19 | 2776 | |
a7812ae4 PB |
2777 | #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } |
2778 | #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ | |
2779 | gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } | |
5af45186 | 2780 | |
d3eb5eae | 2781 | static const SSEFunc_0_epp sse_op_table1[256][4] = { |
a35f3ec7 AJ |
2782 | /* 3DNow! extensions */ |
2783 | [0x0e] = { SSE_DUMMY }, /* femms */ | |
2784 | [0x0f] = { SSE_DUMMY }, /* pf... */ | |
664e0f19 FB |
2785 | /* pure SSE operations */ |
2786 | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
2787 | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
465e9838 | 2788 | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
664e0f19 | 2789 | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
a7812ae4 PB |
2790 | [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, |
2791 | [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2792 | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2793 | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ | |
2794 | ||
2795 | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2796 | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2797 | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ | |
d9f4bb27 | 2798 | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ |
664e0f19 FB |
2799 | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ |
2800 | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ | |
a7812ae4 PB |
2801 | [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, |
2802 | [0x2f] = { gen_helper_comiss, gen_helper_comisd }, | |
664e0f19 FB |
2803 | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2804 | [0x51] = SSE_FOP(sqrt), | |
a7812ae4 PB |
2805 | [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, |
2806 | [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, | |
2807 | [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ | |
2808 | [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ | |
2809 | [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ | |
2810 | [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ | |
664e0f19 FB |
2811 | [0x58] = SSE_FOP(add), |
2812 | [0x59] = SSE_FOP(mul), | |
a7812ae4 PB |
2813 | [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, |
2814 | gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, | |
2815 | [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, | |
664e0f19 FB |
2816 | [0x5c] = SSE_FOP(sub), |
2817 | [0x5d] = SSE_FOP(min), | |
2818 | [0x5e] = SSE_FOP(div), | |
2819 | [0x5f] = SSE_FOP(max), | |
2820 | ||
2821 | [0xc2] = SSE_FOP(cmpeq), | |
d3eb5eae BS |
2822 | [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps, |
2823 | (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ | |
664e0f19 | 2824 | |
222a3336 AZ |
2825 | [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */ |
2826 | [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */ | |
4242b1bd | 2827 | |
664e0f19 FB |
2828 | /* MMX ops and their SSE extensions */ |
2829 | [0x60] = MMX_OP2(punpcklbw), | |
2830 | [0x61] = MMX_OP2(punpcklwd), | |
2831 | [0x62] = MMX_OP2(punpckldq), | |
2832 | [0x63] = MMX_OP2(packsswb), | |
2833 | [0x64] = MMX_OP2(pcmpgtb), | |
2834 | [0x65] = MMX_OP2(pcmpgtw), | |
2835 | [0x66] = MMX_OP2(pcmpgtl), | |
2836 | [0x67] = MMX_OP2(packuswb), | |
2837 | [0x68] = MMX_OP2(punpckhbw), | |
2838 | [0x69] = MMX_OP2(punpckhwd), | |
2839 | [0x6a] = MMX_OP2(punpckhdq), | |
2840 | [0x6b] = MMX_OP2(packssdw), | |
a7812ae4 PB |
2841 | [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, |
2842 | [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2843 | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2844 | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ | |
d3eb5eae BS |
2845 | [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx, |
2846 | (SSEFunc_0_epp)gen_helper_pshufd_xmm, | |
2847 | (SSEFunc_0_epp)gen_helper_pshufhw_xmm, | |
2848 | (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2849 | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2850 | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ | |
2851 | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ | |
2852 | [0x74] = MMX_OP2(pcmpeqb), | |
2853 | [0x75] = MMX_OP2(pcmpeqw), | |
2854 | [0x76] = MMX_OP2(pcmpeql), | |
a35f3ec7 | 2855 | [0x77] = { SSE_DUMMY }, /* emms */ |
d9f4bb27 AP |
2856 | [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ |
2857 | [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, | |
a7812ae4 PB |
2858 | [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, |
2859 | [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, | |
664e0f19 FB |
2860 | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2861 | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ | |
2862 | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ | |
2863 | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ | |
a7812ae4 | 2864 | [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, |
664e0f19 FB |
2865 | [0xd1] = MMX_OP2(psrlw), |
2866 | [0xd2] = MMX_OP2(psrld), | |
2867 | [0xd3] = MMX_OP2(psrlq), | |
2868 | [0xd4] = MMX_OP2(paddq), | |
2869 | [0xd5] = MMX_OP2(pmullw), | |
2870 | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2871 | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ | |
2872 | [0xd8] = MMX_OP2(psubusb), | |
2873 | [0xd9] = MMX_OP2(psubusw), | |
2874 | [0xda] = MMX_OP2(pminub), | |
2875 | [0xdb] = MMX_OP2(pand), | |
2876 | [0xdc] = MMX_OP2(paddusb), | |
2877 | [0xdd] = MMX_OP2(paddusw), | |
2878 | [0xde] = MMX_OP2(pmaxub), | |
2879 | [0xdf] = MMX_OP2(pandn), | |
2880 | [0xe0] = MMX_OP2(pavgb), | |
2881 | [0xe1] = MMX_OP2(psraw), | |
2882 | [0xe2] = MMX_OP2(psrad), | |
2883 | [0xe3] = MMX_OP2(pavgw), | |
2884 | [0xe4] = MMX_OP2(pmulhuw), | |
2885 | [0xe5] = MMX_OP2(pmulhw), | |
a7812ae4 | 2886 | [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, |
664e0f19 FB |
2887 | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
2888 | [0xe8] = MMX_OP2(psubsb), | |
2889 | [0xe9] = MMX_OP2(psubsw), | |
2890 | [0xea] = MMX_OP2(pminsw), | |
2891 | [0xeb] = MMX_OP2(por), | |
2892 | [0xec] = MMX_OP2(paddsb), | |
2893 | [0xed] = MMX_OP2(paddsw), | |
2894 | [0xee] = MMX_OP2(pmaxsw), | |
2895 | [0xef] = MMX_OP2(pxor), | |
465e9838 | 2896 | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
664e0f19 FB |
2897 | [0xf1] = MMX_OP2(psllw), |
2898 | [0xf2] = MMX_OP2(pslld), | |
2899 | [0xf3] = MMX_OP2(psllq), | |
2900 | [0xf4] = MMX_OP2(pmuludq), | |
2901 | [0xf5] = MMX_OP2(pmaddwd), | |
2902 | [0xf6] = MMX_OP2(psadbw), | |
d3eb5eae BS |
2903 | [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx, |
2904 | (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2905 | [0xf8] = MMX_OP2(psubb), |
2906 | [0xf9] = MMX_OP2(psubw), | |
2907 | [0xfa] = MMX_OP2(psubl), | |
2908 | [0xfb] = MMX_OP2(psubq), | |
2909 | [0xfc] = MMX_OP2(paddb), | |
2910 | [0xfd] = MMX_OP2(paddw), | |
2911 | [0xfe] = MMX_OP2(paddl), | |
2912 | }; | |
2913 | ||
d3eb5eae | 2914 | static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = { |
664e0f19 FB |
2915 | [0 + 2] = MMX_OP2(psrlw), |
2916 | [0 + 4] = MMX_OP2(psraw), | |
2917 | [0 + 6] = MMX_OP2(psllw), | |
2918 | [8 + 2] = MMX_OP2(psrld), | |
2919 | [8 + 4] = MMX_OP2(psrad), | |
2920 | [8 + 6] = MMX_OP2(pslld), | |
2921 | [16 + 2] = MMX_OP2(psrlq), | |
a7812ae4 | 2922 | [16 + 3] = { NULL, gen_helper_psrldq_xmm }, |
664e0f19 | 2923 | [16 + 6] = MMX_OP2(psllq), |
a7812ae4 | 2924 | [16 + 7] = { NULL, gen_helper_pslldq_xmm }, |
664e0f19 FB |
2925 | }; |
2926 | ||
d3eb5eae | 2927 | static const SSEFunc_0_epi sse_op_table3ai[] = { |
a7812ae4 | 2928 | gen_helper_cvtsi2ss, |
11f8cdbc | 2929 | gen_helper_cvtsi2sd |
c4baa050 | 2930 | }; |
a7812ae4 | 2931 | |
11f8cdbc | 2932 | #ifdef TARGET_X86_64 |
d3eb5eae | 2933 | static const SSEFunc_0_epl sse_op_table3aq[] = { |
11f8cdbc SW |
2934 | gen_helper_cvtsq2ss, |
2935 | gen_helper_cvtsq2sd | |
2936 | }; | |
2937 | #endif | |
2938 | ||
d3eb5eae | 2939 | static const SSEFunc_i_ep sse_op_table3bi[] = { |
a7812ae4 | 2940 | gen_helper_cvttss2si, |
a7812ae4 | 2941 | gen_helper_cvtss2si, |
bedc2ac1 | 2942 | gen_helper_cvttsd2si, |
11f8cdbc | 2943 | gen_helper_cvtsd2si |
664e0f19 | 2944 | }; |
3b46e624 | 2945 | |
11f8cdbc | 2946 | #ifdef TARGET_X86_64 |
d3eb5eae | 2947 | static const SSEFunc_l_ep sse_op_table3bq[] = { |
11f8cdbc | 2948 | gen_helper_cvttss2sq, |
11f8cdbc | 2949 | gen_helper_cvtss2sq, |
bedc2ac1 | 2950 | gen_helper_cvttsd2sq, |
11f8cdbc SW |
2951 | gen_helper_cvtsd2sq |
2952 | }; | |
2953 | #endif | |
2954 | ||
d3eb5eae | 2955 | static const SSEFunc_0_epp sse_op_table4[8][4] = { |
664e0f19 FB |
2956 | SSE_FOP(cmpeq), |
2957 | SSE_FOP(cmplt), | |
2958 | SSE_FOP(cmple), | |
2959 | SSE_FOP(cmpunord), | |
2960 | SSE_FOP(cmpneq), | |
2961 | SSE_FOP(cmpnlt), | |
2962 | SSE_FOP(cmpnle), | |
2963 | SSE_FOP(cmpord), | |
2964 | }; | |
3b46e624 | 2965 | |
d3eb5eae | 2966 | static const SSEFunc_0_epp sse_op_table5[256] = { |
a7812ae4 PB |
2967 | [0x0c] = gen_helper_pi2fw, |
2968 | [0x0d] = gen_helper_pi2fd, | |
2969 | [0x1c] = gen_helper_pf2iw, | |
2970 | [0x1d] = gen_helper_pf2id, | |
2971 | [0x8a] = gen_helper_pfnacc, | |
2972 | [0x8e] = gen_helper_pfpnacc, | |
2973 | [0x90] = gen_helper_pfcmpge, | |
2974 | [0x94] = gen_helper_pfmin, | |
2975 | [0x96] = gen_helper_pfrcp, | |
2976 | [0x97] = gen_helper_pfrsqrt, | |
2977 | [0x9a] = gen_helper_pfsub, | |
2978 | [0x9e] = gen_helper_pfadd, | |
2979 | [0xa0] = gen_helper_pfcmpgt, | |
2980 | [0xa4] = gen_helper_pfmax, | |
2981 | [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ | |
2982 | [0xa7] = gen_helper_movq, /* pfrsqit1 */ | |
2983 | [0xaa] = gen_helper_pfsubr, | |
2984 | [0xae] = gen_helper_pfacc, | |
2985 | [0xb0] = gen_helper_pfcmpeq, | |
2986 | [0xb4] = gen_helper_pfmul, | |
2987 | [0xb6] = gen_helper_movq, /* pfrcpit2 */ | |
2988 | [0xb7] = gen_helper_pmulhrw_mmx, | |
2989 | [0xbb] = gen_helper_pswapd, | |
2990 | [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ | |
a35f3ec7 AJ |
2991 | }; |
2992 | ||
d3eb5eae BS |
2993 | struct SSEOpHelper_epp { |
2994 | SSEFunc_0_epp op[2]; | |
c4baa050 BS |
2995 | uint32_t ext_mask; |
2996 | }; | |
2997 | ||
d3eb5eae BS |
2998 | struct SSEOpHelper_eppi { |
2999 | SSEFunc_0_eppi op[2]; | |
c4baa050 | 3000 | uint32_t ext_mask; |
222a3336 | 3001 | }; |
c4baa050 | 3002 | |
222a3336 | 3003 | #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 } |
a7812ae4 PB |
3004 | #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } |
3005 | #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } | |
222a3336 | 3006 | #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } |
c4baa050 | 3007 | |
d3eb5eae | 3008 | static const struct SSEOpHelper_epp sse_op_table6[256] = { |
222a3336 AZ |
3009 | [0x00] = SSSE3_OP(pshufb), |
3010 | [0x01] = SSSE3_OP(phaddw), | |
3011 | [0x02] = SSSE3_OP(phaddd), | |
3012 | [0x03] = SSSE3_OP(phaddsw), | |
3013 | [0x04] = SSSE3_OP(pmaddubsw), | |
3014 | [0x05] = SSSE3_OP(phsubw), | |
3015 | [0x06] = SSSE3_OP(phsubd), | |
3016 | [0x07] = SSSE3_OP(phsubsw), | |
3017 | [0x08] = SSSE3_OP(psignb), | |
3018 | [0x09] = SSSE3_OP(psignw), | |
3019 | [0x0a] = SSSE3_OP(psignd), | |
3020 | [0x0b] = SSSE3_OP(pmulhrsw), | |
3021 | [0x10] = SSE41_OP(pblendvb), | |
3022 | [0x14] = SSE41_OP(blendvps), | |
3023 | [0x15] = SSE41_OP(blendvpd), | |
3024 | [0x17] = SSE41_OP(ptest), | |
3025 | [0x1c] = SSSE3_OP(pabsb), | |
3026 | [0x1d] = SSSE3_OP(pabsw), | |
3027 | [0x1e] = SSSE3_OP(pabsd), | |
3028 | [0x20] = SSE41_OP(pmovsxbw), | |
3029 | [0x21] = SSE41_OP(pmovsxbd), | |
3030 | [0x22] = SSE41_OP(pmovsxbq), | |
3031 | [0x23] = SSE41_OP(pmovsxwd), | |
3032 | [0x24] = SSE41_OP(pmovsxwq), | |
3033 | [0x25] = SSE41_OP(pmovsxdq), | |
3034 | [0x28] = SSE41_OP(pmuldq), | |
3035 | [0x29] = SSE41_OP(pcmpeqq), | |
3036 | [0x2a] = SSE41_SPECIAL, /* movntqda */ | |
3037 | [0x2b] = SSE41_OP(packusdw), | |
3038 | [0x30] = SSE41_OP(pmovzxbw), | |
3039 | [0x31] = SSE41_OP(pmovzxbd), | |
3040 | [0x32] = SSE41_OP(pmovzxbq), | |
3041 | [0x33] = SSE41_OP(pmovzxwd), | |
3042 | [0x34] = SSE41_OP(pmovzxwq), | |
3043 | [0x35] = SSE41_OP(pmovzxdq), | |
3044 | [0x37] = SSE42_OP(pcmpgtq), | |
3045 | [0x38] = SSE41_OP(pminsb), | |
3046 | [0x39] = SSE41_OP(pminsd), | |
3047 | [0x3a] = SSE41_OP(pminuw), | |
3048 | [0x3b] = SSE41_OP(pminud), | |
3049 | [0x3c] = SSE41_OP(pmaxsb), | |
3050 | [0x3d] = SSE41_OP(pmaxsd), | |
3051 | [0x3e] = SSE41_OP(pmaxuw), | |
3052 | [0x3f] = SSE41_OP(pmaxud), | |
3053 | [0x40] = SSE41_OP(pmulld), | |
3054 | [0x41] = SSE41_OP(phminposuw), | |
4242b1bd AZ |
3055 | }; |
3056 | ||
d3eb5eae | 3057 | static const struct SSEOpHelper_eppi sse_op_table7[256] = { |
222a3336 AZ |
3058 | [0x08] = SSE41_OP(roundps), |
3059 | [0x09] = SSE41_OP(roundpd), | |
3060 | [0x0a] = SSE41_OP(roundss), | |
3061 | [0x0b] = SSE41_OP(roundsd), | |
3062 | [0x0c] = SSE41_OP(blendps), | |
3063 | [0x0d] = SSE41_OP(blendpd), | |
3064 | [0x0e] = SSE41_OP(pblendw), | |
3065 | [0x0f] = SSSE3_OP(palignr), | |
3066 | [0x14] = SSE41_SPECIAL, /* pextrb */ | |
3067 | [0x15] = SSE41_SPECIAL, /* pextrw */ | |
3068 | [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ | |
3069 | [0x17] = SSE41_SPECIAL, /* extractps */ | |
3070 | [0x20] = SSE41_SPECIAL, /* pinsrb */ | |
3071 | [0x21] = SSE41_SPECIAL, /* insertps */ | |
3072 | [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ | |
3073 | [0x40] = SSE41_OP(dpps), | |
3074 | [0x41] = SSE41_OP(dppd), | |
3075 | [0x42] = SSE41_OP(mpsadbw), | |
3076 | [0x60] = SSE42_OP(pcmpestrm), | |
3077 | [0x61] = SSE42_OP(pcmpestri), | |
3078 | [0x62] = SSE42_OP(pcmpistrm), | |
3079 | [0x63] = SSE42_OP(pcmpistri), | |
4242b1bd AZ |
3080 | }; |
3081 | ||
0af10c86 BS |
3082 | static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
3083 | target_ulong pc_start, int rex_r) | |
664e0f19 FB |
3084 | { |
3085 | int b1, op1_offset, op2_offset, is_xmm, val, ot; | |
3086 | int modrm, mod, rm, reg, reg_addr, offset_addr; | |
d3eb5eae BS |
3087 | SSEFunc_0_epp sse_fn_epp; |
3088 | SSEFunc_0_eppi sse_fn_eppi; | |
c4baa050 | 3089 | SSEFunc_0_ppi sse_fn_ppi; |
d3eb5eae | 3090 | SSEFunc_0_eppt sse_fn_eppt; |
664e0f19 FB |
3091 | |
3092 | b &= 0xff; | |
5fafdf24 | 3093 | if (s->prefix & PREFIX_DATA) |
664e0f19 | 3094 | b1 = 1; |
5fafdf24 | 3095 | else if (s->prefix & PREFIX_REPZ) |
664e0f19 | 3096 | b1 = 2; |
5fafdf24 | 3097 | else if (s->prefix & PREFIX_REPNZ) |
664e0f19 FB |
3098 | b1 = 3; |
3099 | else | |
3100 | b1 = 0; | |
d3eb5eae BS |
3101 | sse_fn_epp = sse_op_table1[b][b1]; |
3102 | if (!sse_fn_epp) { | |
664e0f19 | 3103 | goto illegal_op; |
c4baa050 | 3104 | } |
a35f3ec7 | 3105 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
664e0f19 FB |
3106 | is_xmm = 1; |
3107 | } else { | |
3108 | if (b1 == 0) { | |
3109 | /* MMX case */ | |
3110 | is_xmm = 0; | |
3111 | } else { | |
3112 | is_xmm = 1; | |
3113 | } | |
3114 | } | |
3115 | /* simple MMX/SSE operation */ | |
3116 | if (s->flags & HF_TS_MASK) { | |
3117 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
3118 | return; | |
3119 | } | |
3120 | if (s->flags & HF_EM_MASK) { | |
3121 | illegal_op: | |
3122 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
3123 | return; | |
3124 | } | |
3125 | if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) | |
4242b1bd AZ |
3126 | if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) |
3127 | goto illegal_op; | |
e771edab AJ |
3128 | if (b == 0x0e) { |
3129 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) | |
3130 | goto illegal_op; | |
3131 | /* femms */ | |
d3eb5eae | 3132 | gen_helper_emms(cpu_env); |
e771edab AJ |
3133 | return; |
3134 | } | |
3135 | if (b == 0x77) { | |
3136 | /* emms */ | |
d3eb5eae | 3137 | gen_helper_emms(cpu_env); |
664e0f19 FB |
3138 | return; |
3139 | } | |
3140 | /* prepare MMX state (XXX: optimize by storing fptt and fptags in | |
3141 | the static cpu state) */ | |
3142 | if (!is_xmm) { | |
d3eb5eae | 3143 | gen_helper_enter_mmx(cpu_env); |
664e0f19 FB |
3144 | } |
3145 | ||
0af10c86 | 3146 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3147 | reg = ((modrm >> 3) & 7); |
3148 | if (is_xmm) | |
3149 | reg |= rex_r; | |
3150 | mod = (modrm >> 6) & 3; | |
d3eb5eae | 3151 | if (sse_fn_epp == SSE_SPECIAL) { |
664e0f19 FB |
3152 | b |= (b1 << 8); |
3153 | switch(b) { | |
3154 | case 0x0e7: /* movntq */ | |
5fafdf24 | 3155 | if (mod == 3) |
664e0f19 | 3156 | goto illegal_op; |
0af10c86 | 3157 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3158 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3159 | break; |
3160 | case 0x1e7: /* movntdq */ | |
3161 | case 0x02b: /* movntps */ | |
3162 | case 0x12b: /* movntps */ | |
2e21e749 T |
3163 | if (mod == 3) |
3164 | goto illegal_op; | |
0af10c86 | 3165 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2e21e749 T |
3166 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3167 | break; | |
465e9838 FB |
3168 | case 0x3f0: /* lddqu */ |
3169 | if (mod == 3) | |
664e0f19 | 3170 | goto illegal_op; |
0af10c86 | 3171 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
c2254920 | 3172 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 | 3173 | break; |
d9f4bb27 AP |
3174 | case 0x22b: /* movntss */ |
3175 | case 0x32b: /* movntsd */ | |
3176 | if (mod == 3) | |
3177 | goto illegal_op; | |
0af10c86 | 3178 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
d9f4bb27 AP |
3179 | if (b1 & 1) { |
3180 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State, | |
3181 | xmm_regs[reg])); | |
3182 | } else { | |
3183 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3184 | xmm_regs[reg].XMM_L(0))); | |
3185 | gen_op_st_T0_A0(OT_LONG + s->mem_index); | |
3186 | } | |
3187 | break; | |
664e0f19 | 3188 | case 0x6e: /* movd mm, ea */ |
dabd98dd FB |
3189 | #ifdef TARGET_X86_64 |
3190 | if (s->dflag == 2) { | |
0af10c86 | 3191 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0); |
5af45186 | 3192 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); |
5fafdf24 | 3193 | } else |
dabd98dd FB |
3194 | #endif |
3195 | { | |
0af10c86 | 3196 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0); |
5af45186 FB |
3197 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3198 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
a7812ae4 PB |
3199 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3200 | gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); | |
dabd98dd | 3201 | } |
664e0f19 FB |
3202 | break; |
3203 | case 0x16e: /* movd xmm, ea */ | |
dabd98dd FB |
3204 | #ifdef TARGET_X86_64 |
3205 | if (s->dflag == 2) { | |
0af10c86 | 3206 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0); |
5af45186 FB |
3207 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3208 | offsetof(CPUX86State,xmm_regs[reg])); | |
a7812ae4 | 3209 | gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); |
5fafdf24 | 3210 | } else |
dabd98dd FB |
3211 | #endif |
3212 | { | |
0af10c86 | 3213 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0); |
5af45186 FB |
3214 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3215 | offsetof(CPUX86State,xmm_regs[reg])); | |
b6abf97d | 3216 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 3217 | gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); |
dabd98dd | 3218 | } |
664e0f19 FB |
3219 | break; |
3220 | case 0x6f: /* movq mm, ea */ | |
3221 | if (mod != 3) { | |
0af10c86 | 3222 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3223 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3224 | } else { |
3225 | rm = (modrm & 7); | |
b6abf97d | 3226 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3227 | offsetof(CPUX86State,fpregs[rm].mmx)); |
b6abf97d | 3228 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3229 | offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3230 | } |
3231 | break; | |
3232 | case 0x010: /* movups */ | |
3233 | case 0x110: /* movupd */ | |
3234 | case 0x028: /* movaps */ | |
3235 | case 0x128: /* movapd */ | |
3236 | case 0x16f: /* movdqa xmm, ea */ | |
3237 | case 0x26f: /* movdqu xmm, ea */ | |
3238 | if (mod != 3) { | |
0af10c86 | 3239 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3240 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3241 | } else { |
3242 | rm = (modrm & 7) | REX_B(s); | |
3243 | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), | |
3244 | offsetof(CPUX86State,xmm_regs[rm])); | |
3245 | } | |
3246 | break; | |
3247 | case 0x210: /* movss xmm, ea */ | |
3248 | if (mod != 3) { | |
0af10c86 | 3249 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 3250 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3251 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
664e0f19 | 3252 | gen_op_movl_T0_0(); |
651ba608 FB |
3253 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); |
3254 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3255 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3256 | } else { |
3257 | rm = (modrm & 7) | REX_B(s); | |
3258 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3259 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3260 | } | |
3261 | break; | |
3262 | case 0x310: /* movsd xmm, ea */ | |
3263 | if (mod != 3) { | |
0af10c86 | 3264 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3265 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 | 3266 | gen_op_movl_T0_0(); |
651ba608 FB |
3267 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3268 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3269 | } else { |
3270 | rm = (modrm & 7) | REX_B(s); | |
3271 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3272 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3273 | } | |
3274 | break; | |
3275 | case 0x012: /* movlps */ | |
3276 | case 0x112: /* movlpd */ | |
3277 | if (mod != 3) { | |
0af10c86 | 3278 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3279 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3280 | } else { |
3281 | /* movhlps */ | |
3282 | rm = (modrm & 7) | REX_B(s); | |
3283 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3284 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3285 | } | |
3286 | break; | |
465e9838 FB |
3287 | case 0x212: /* movsldup */ |
3288 | if (mod != 3) { | |
0af10c86 | 3289 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3290 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
465e9838 FB |
3291 | } else { |
3292 | rm = (modrm & 7) | REX_B(s); | |
3293 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3294 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3295 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3296 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); | |
3297 | } | |
3298 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3299 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3300 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3301 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3302 | break; | |
3303 | case 0x312: /* movddup */ | |
3304 | if (mod != 3) { | |
0af10c86 | 3305 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3306 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 FB |
3307 | } else { |
3308 | rm = (modrm & 7) | REX_B(s); | |
3309 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3310 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3311 | } | |
3312 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
ba6526df | 3313 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 | 3314 | break; |
664e0f19 FB |
3315 | case 0x016: /* movhps */ |
3316 | case 0x116: /* movhpd */ | |
3317 | if (mod != 3) { | |
0af10c86 | 3318 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3319 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3320 | } else { |
3321 | /* movlhps */ | |
3322 | rm = (modrm & 7) | REX_B(s); | |
3323 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
3324 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3325 | } | |
3326 | break; | |
3327 | case 0x216: /* movshdup */ | |
3328 | if (mod != 3) { | |
0af10c86 | 3329 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3330 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3331 | } else { |
3332 | rm = (modrm & 7) | REX_B(s); | |
3333 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3334 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); | |
3335 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3336 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); | |
3337 | } | |
3338 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3339 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); | |
3340 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3341 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
3342 | break; | |
d9f4bb27 AP |
3343 | case 0x178: |
3344 | case 0x378: | |
3345 | { | |
3346 | int bit_index, field_length; | |
3347 | ||
3348 | if (b1 == 1 && reg != 0) | |
3349 | goto illegal_op; | |
0af10c86 BS |
3350 | field_length = cpu_ldub_code(env, s->pc++) & 0x3F; |
3351 | bit_index = cpu_ldub_code(env, s->pc++) & 0x3F; | |
d9f4bb27 AP |
3352 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3353 | offsetof(CPUX86State,xmm_regs[reg])); | |
3354 | if (b1 == 1) | |
d3eb5eae BS |
3355 | gen_helper_extrq_i(cpu_env, cpu_ptr0, |
3356 | tcg_const_i32(bit_index), | |
3357 | tcg_const_i32(field_length)); | |
d9f4bb27 | 3358 | else |
d3eb5eae BS |
3359 | gen_helper_insertq_i(cpu_env, cpu_ptr0, |
3360 | tcg_const_i32(bit_index), | |
3361 | tcg_const_i32(field_length)); | |
d9f4bb27 AP |
3362 | } |
3363 | break; | |
664e0f19 | 3364 | case 0x7e: /* movd ea, mm */ |
dabd98dd FB |
3365 | #ifdef TARGET_X86_64 |
3366 | if (s->dflag == 2) { | |
5af45186 FB |
3367 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3368 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
0af10c86 | 3369 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3370 | } else |
dabd98dd FB |
3371 | #endif |
3372 | { | |
5af45186 FB |
3373 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3374 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); | |
0af10c86 | 3375 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1); |
dabd98dd | 3376 | } |
664e0f19 FB |
3377 | break; |
3378 | case 0x17e: /* movd ea, xmm */ | |
dabd98dd FB |
3379 | #ifdef TARGET_X86_64 |
3380 | if (s->dflag == 2) { | |
5af45186 FB |
3381 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3382 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
0af10c86 | 3383 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3384 | } else |
dabd98dd FB |
3385 | #endif |
3386 | { | |
5af45186 FB |
3387 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3388 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
0af10c86 | 3389 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1); |
dabd98dd | 3390 | } |
664e0f19 FB |
3391 | break; |
3392 | case 0x27e: /* movq xmm, ea */ | |
3393 | if (mod != 3) { | |
0af10c86 | 3394 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3395 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3396 | } else { |
3397 | rm = (modrm & 7) | REX_B(s); | |
3398 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3399 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3400 | } | |
3401 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
3402 | break; | |
3403 | case 0x7f: /* movq ea, mm */ | |
3404 | if (mod != 3) { | |
0af10c86 | 3405 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3406 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3407 | } else { |
3408 | rm = (modrm & 7); | |
3409 | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), | |
3410 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
3411 | } | |
3412 | break; | |
3413 | case 0x011: /* movups */ | |
3414 | case 0x111: /* movupd */ | |
3415 | case 0x029: /* movaps */ | |
3416 | case 0x129: /* movapd */ | |
3417 | case 0x17f: /* movdqa ea, xmm */ | |
3418 | case 0x27f: /* movdqu ea, xmm */ | |
3419 | if (mod != 3) { | |
0af10c86 | 3420 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3421 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3422 | } else { |
3423 | rm = (modrm & 7) | REX_B(s); | |
3424 | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), | |
3425 | offsetof(CPUX86State,xmm_regs[reg])); | |
3426 | } | |
3427 | break; | |
3428 | case 0x211: /* movss ea, xmm */ | |
3429 | if (mod != 3) { | |
0af10c86 | 3430 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
651ba608 | 3431 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
57fec1fe | 3432 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
664e0f19 FB |
3433 | } else { |
3434 | rm = (modrm & 7) | REX_B(s); | |
3435 | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), | |
3436 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3437 | } | |
3438 | break; | |
3439 | case 0x311: /* movsd ea, xmm */ | |
3440 | if (mod != 3) { | |
0af10c86 | 3441 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3442 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3443 | } else { |
3444 | rm = (modrm & 7) | REX_B(s); | |
3445 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3446 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3447 | } | |
3448 | break; | |
3449 | case 0x013: /* movlps */ | |
3450 | case 0x113: /* movlpd */ | |
3451 | if (mod != 3) { | |
0af10c86 | 3452 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3453 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3454 | } else { |
3455 | goto illegal_op; | |
3456 | } | |
3457 | break; | |
3458 | case 0x017: /* movhps */ | |
3459 | case 0x117: /* movhpd */ | |
3460 | if (mod != 3) { | |
0af10c86 | 3461 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3462 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3463 | } else { |
3464 | goto illegal_op; | |
3465 | } | |
3466 | break; | |
3467 | case 0x71: /* shift mm, im */ | |
3468 | case 0x72: | |
3469 | case 0x73: | |
3470 | case 0x171: /* shift xmm, im */ | |
3471 | case 0x172: | |
3472 | case 0x173: | |
c045af25 AK |
3473 | if (b1 >= 2) { |
3474 | goto illegal_op; | |
3475 | } | |
0af10c86 | 3476 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3477 | if (is_xmm) { |
3478 | gen_op_movl_T0_im(val); | |
651ba608 | 3479 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 | 3480 | gen_op_movl_T0_0(); |
651ba608 | 3481 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); |
664e0f19 FB |
3482 | op1_offset = offsetof(CPUX86State,xmm_t0); |
3483 | } else { | |
3484 | gen_op_movl_T0_im(val); | |
651ba608 | 3485 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); |
664e0f19 | 3486 | gen_op_movl_T0_0(); |
651ba608 | 3487 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); |
664e0f19 FB |
3488 | op1_offset = offsetof(CPUX86State,mmx_t0); |
3489 | } | |
d3eb5eae BS |
3490 | sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + |
3491 | (((modrm >> 3)) & 7)][b1]; | |
3492 | if (!sse_fn_epp) { | |
664e0f19 | 3493 | goto illegal_op; |
c4baa050 | 3494 | } |
664e0f19 FB |
3495 | if (is_xmm) { |
3496 | rm = (modrm & 7) | REX_B(s); | |
3497 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3498 | } else { | |
3499 | rm = (modrm & 7); | |
3500 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3501 | } | |
5af45186 FB |
3502 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3503 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); | |
d3eb5eae | 3504 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3505 | break; |
3506 | case 0x050: /* movmskps */ | |
664e0f19 | 3507 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3508 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3509 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3510 | gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3511 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3512 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3513 | break; |
3514 | case 0x150: /* movmskpd */ | |
664e0f19 | 3515 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3516 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3517 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3518 | gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3519 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3520 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3521 | break; |
3522 | case 0x02a: /* cvtpi2ps */ | |
3523 | case 0x12a: /* cvtpi2pd */ | |
d3eb5eae | 3524 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3525 | if (mod != 3) { |
0af10c86 | 3526 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 3527 | op2_offset = offsetof(CPUX86State,mmx_t0); |
8686c490 | 3528 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3529 | } else { |
3530 | rm = (modrm & 7); | |
3531 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3532 | } | |
3533 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3534 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3535 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3536 | switch(b >> 8) { |
3537 | case 0x0: | |
d3eb5eae | 3538 | gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3539 | break; |
3540 | default: | |
3541 | case 0x1: | |
d3eb5eae | 3542 | gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3543 | break; |
3544 | } | |
3545 | break; | |
3546 | case 0x22a: /* cvtsi2ss */ | |
3547 | case 0x32a: /* cvtsi2sd */ | |
3548 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
0af10c86 | 3549 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
664e0f19 | 3550 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
5af45186 | 3551 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
28e10711 | 3552 | if (ot == OT_LONG) { |
d3eb5eae | 3553 | SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1]; |
28e10711 | 3554 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 3555 | sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32); |
28e10711 | 3556 | } else { |
11f8cdbc | 3557 | #ifdef TARGET_X86_64 |
d3eb5eae BS |
3558 | SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1]; |
3559 | sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]); | |
11f8cdbc SW |
3560 | #else |
3561 | goto illegal_op; | |
3562 | #endif | |
28e10711 | 3563 | } |
664e0f19 FB |
3564 | break; |
3565 | case 0x02c: /* cvttps2pi */ | |
3566 | case 0x12c: /* cvttpd2pi */ | |
3567 | case 0x02d: /* cvtps2pi */ | |
3568 | case 0x12d: /* cvtpd2pi */ | |
d3eb5eae | 3569 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3570 | if (mod != 3) { |
0af10c86 | 3571 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 3572 | op2_offset = offsetof(CPUX86State,xmm_t0); |
8686c490 | 3573 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3574 | } else { |
3575 | rm = (modrm & 7) | REX_B(s); | |
3576 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3577 | } | |
3578 | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx); | |
5af45186 FB |
3579 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3580 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3581 | switch(b) { |
3582 | case 0x02c: | |
d3eb5eae | 3583 | gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3584 | break; |
3585 | case 0x12c: | |
d3eb5eae | 3586 | gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3587 | break; |
3588 | case 0x02d: | |
d3eb5eae | 3589 | gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3590 | break; |
3591 | case 0x12d: | |
d3eb5eae | 3592 | gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3593 | break; |
3594 | } | |
3595 | break; | |
3596 | case 0x22c: /* cvttss2si */ | |
3597 | case 0x32c: /* cvttsd2si */ | |
3598 | case 0x22d: /* cvtss2si */ | |
3599 | case 0x32d: /* cvtsd2si */ | |
3600 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
31313213 | 3601 | if (mod != 3) { |
0af10c86 | 3602 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
31313213 | 3603 | if ((b >> 8) & 1) { |
8686c490 | 3604 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))); |
31313213 | 3605 | } else { |
57fec1fe | 3606 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3607 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
31313213 FB |
3608 | } |
3609 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3610 | } else { | |
3611 | rm = (modrm & 7) | REX_B(s); | |
3612 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3613 | } | |
5af45186 FB |
3614 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3615 | if (ot == OT_LONG) { | |
d3eb5eae | 3616 | SSEFunc_i_ep sse_fn_i_ep = |
bedc2ac1 | 3617 | sse_op_table3bi[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3618 | sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3619 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
5af45186 | 3620 | } else { |
11f8cdbc | 3621 | #ifdef TARGET_X86_64 |
d3eb5eae | 3622 | SSEFunc_l_ep sse_fn_l_ep = |
bedc2ac1 | 3623 | sse_op_table3bq[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3624 | sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0); |
11f8cdbc SW |
3625 | #else |
3626 | goto illegal_op; | |
3627 | #endif | |
5af45186 | 3628 | } |
57fec1fe | 3629 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3630 | break; |
3631 | case 0xc4: /* pinsrw */ | |
5fafdf24 | 3632 | case 0x1c4: |
d1e42c5c | 3633 | s->rip_offset = 1; |
0af10c86 BS |
3634 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
3635 | val = cpu_ldub_code(env, s->pc++); | |
664e0f19 FB |
3636 | if (b1) { |
3637 | val &= 7; | |
5af45186 FB |
3638 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3639 | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); | |
664e0f19 FB |
3640 | } else { |
3641 | val &= 3; | |
5af45186 FB |
3642 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3643 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); | |
664e0f19 FB |
3644 | } |
3645 | break; | |
3646 | case 0xc5: /* pextrw */ | |
5fafdf24 | 3647 | case 0x1c5: |
664e0f19 FB |
3648 | if (mod != 3) |
3649 | goto illegal_op; | |
6dc2d0da | 3650 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
0af10c86 | 3651 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3652 | if (b1) { |
3653 | val &= 7; | |
3654 | rm = (modrm & 7) | REX_B(s); | |
5af45186 FB |
3655 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3656 | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); | |
664e0f19 FB |
3657 | } else { |
3658 | val &= 3; | |
3659 | rm = (modrm & 7); | |
5af45186 FB |
3660 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3661 | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); | |
664e0f19 FB |
3662 | } |
3663 | reg = ((modrm >> 3) & 7) | rex_r; | |
6dc2d0da | 3664 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3665 | break; |
3666 | case 0x1d6: /* movq ea, xmm */ | |
3667 | if (mod != 3) { | |
0af10c86 | 3668 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3669 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3670 | } else { |
3671 | rm = (modrm & 7) | REX_B(s); | |
3672 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3673 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3674 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3675 | } | |
3676 | break; | |
3677 | case 0x2d6: /* movq2dq */ | |
d3eb5eae | 3678 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3679 | rm = (modrm & 7); |
3680 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3681 | offsetof(CPUX86State,fpregs[rm].mmx)); | |
3682 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3683 | break; |
3684 | case 0x3d6: /* movdq2q */ | |
d3eb5eae | 3685 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3686 | rm = (modrm & 7) | REX_B(s); |
3687 | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), | |
3688 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
664e0f19 FB |
3689 | break; |
3690 | case 0xd7: /* pmovmskb */ | |
3691 | case 0x1d7: | |
3692 | if (mod != 3) | |
3693 | goto illegal_op; | |
3694 | if (b1) { | |
3695 | rm = (modrm & 7) | REX_B(s); | |
5af45186 | 3696 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
d3eb5eae | 3697 | gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 FB |
3698 | } else { |
3699 | rm = (modrm & 7); | |
5af45186 | 3700 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
d3eb5eae | 3701 | gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 | 3702 | } |
b6abf97d | 3703 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
664e0f19 | 3704 | reg = ((modrm >> 3) & 7) | rex_r; |
57fec1fe | 3705 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 | 3706 | break; |
4242b1bd | 3707 | case 0x138: |
000cacf6 AZ |
3708 | if (s->prefix & PREFIX_REPNZ) |
3709 | goto crc32; | |
3710 | case 0x038: | |
4242b1bd | 3711 | b = modrm; |
0af10c86 | 3712 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
3713 | rm = modrm & 7; |
3714 | reg = ((modrm >> 3) & 7) | rex_r; | |
3715 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3716 | if (b1 >= 2) { |
3717 | goto illegal_op; | |
3718 | } | |
4242b1bd | 3719 | |
d3eb5eae BS |
3720 | sse_fn_epp = sse_op_table6[b].op[b1]; |
3721 | if (!sse_fn_epp) { | |
4242b1bd | 3722 | goto illegal_op; |
c4baa050 | 3723 | } |
222a3336 AZ |
3724 | if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask)) |
3725 | goto illegal_op; | |
4242b1bd AZ |
3726 | |
3727 | if (b1) { | |
3728 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3729 | if (mod == 3) { | |
3730 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3731 | } else { | |
3732 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
0af10c86 | 3733 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
222a3336 AZ |
3734 | switch (b) { |
3735 | case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ | |
3736 | case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ | |
3737 | case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ | |
3738 | gen_ldq_env_A0(s->mem_index, op2_offset + | |
3739 | offsetof(XMMReg, XMM_Q(0))); | |
3740 | break; | |
3741 | case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ | |
3742 | case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ | |
a7812ae4 | 3743 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3744 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3745 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3746 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + |
3747 | offsetof(XMMReg, XMM_L(0))); | |
3748 | break; | |
3749 | case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ | |
3750 | tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, | |
3751 | (s->mem_index >> 2) - 1); | |
3752 | tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + | |
3753 | offsetof(XMMReg, XMM_W(0))); | |
3754 | break; | |
3755 | case 0x2a: /* movntqda */ | |
3756 | gen_ldo_env_A0(s->mem_index, op1_offset); | |
3757 | return; | |
3758 | default: | |
3759 | gen_ldo_env_A0(s->mem_index, op2_offset); | |
3760 | } | |
4242b1bd AZ |
3761 | } |
3762 | } else { | |
3763 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3764 | if (mod == 3) { | |
3765 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3766 | } else { | |
3767 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
0af10c86 | 3768 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4242b1bd AZ |
3769 | gen_ldq_env_A0(s->mem_index, op2_offset); |
3770 | } | |
3771 | } | |
d3eb5eae | 3772 | if (sse_fn_epp == SSE_SPECIAL) { |
222a3336 | 3773 | goto illegal_op; |
c4baa050 | 3774 | } |
222a3336 | 3775 | |
4242b1bd AZ |
3776 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3777 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 3778 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
222a3336 | 3779 | |
3ca51d07 RH |
3780 | if (b == 0x17) { |
3781 | set_cc_op(s, CC_OP_EFLAGS); | |
3782 | } | |
4242b1bd | 3783 | break; |
222a3336 AZ |
3784 | case 0x338: /* crc32 */ |
3785 | crc32: | |
3786 | b = modrm; | |
0af10c86 | 3787 | modrm = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
3788 | reg = ((modrm >> 3) & 7) | rex_r; |
3789 | ||
3790 | if (b != 0xf0 && b != 0xf1) | |
3791 | goto illegal_op; | |
3792 | if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) | |
4242b1bd AZ |
3793 | goto illegal_op; |
3794 | ||
222a3336 AZ |
3795 | if (b == 0xf0) |
3796 | ot = OT_BYTE; | |
3797 | else if (b == 0xf1 && s->dflag != 2) | |
3798 | if (s->prefix & PREFIX_DATA) | |
3799 | ot = OT_WORD; | |
3800 | else | |
3801 | ot = OT_LONG; | |
3802 | else | |
3803 | ot = OT_QUAD; | |
3804 | ||
3805 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
3806 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
0af10c86 | 3807 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
a7812ae4 PB |
3808 | gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, |
3809 | cpu_T[0], tcg_const_i32(8 << ot)); | |
222a3336 AZ |
3810 | |
3811 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3812 | gen_op_mov_reg_T0(ot, reg); | |
3813 | break; | |
3814 | case 0x03a: | |
3815 | case 0x13a: | |
4242b1bd | 3816 | b = modrm; |
0af10c86 | 3817 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
3818 | rm = modrm & 7; |
3819 | reg = ((modrm >> 3) & 7) | rex_r; | |
3820 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3821 | if (b1 >= 2) { |
3822 | goto illegal_op; | |
3823 | } | |
4242b1bd | 3824 | |
d3eb5eae BS |
3825 | sse_fn_eppi = sse_op_table7[b].op[b1]; |
3826 | if (!sse_fn_eppi) { | |
4242b1bd | 3827 | goto illegal_op; |
c4baa050 | 3828 | } |
222a3336 AZ |
3829 | if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) |
3830 | goto illegal_op; | |
3831 | ||
d3eb5eae | 3832 | if (sse_fn_eppi == SSE_SPECIAL) { |
222a3336 AZ |
3833 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
3834 | rm = (modrm & 7) | REX_B(s); | |
3835 | if (mod != 3) | |
0af10c86 | 3836 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
222a3336 | 3837 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 3838 | val = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
3839 | switch (b) { |
3840 | case 0x14: /* pextrb */ | |
3841 | tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3842 | xmm_regs[reg].XMM_B(val & 15))); | |
3843 | if (mod == 3) | |
3844 | gen_op_mov_reg_T0(ot, rm); | |
3845 | else | |
3846 | tcg_gen_qemu_st8(cpu_T[0], cpu_A0, | |
3847 | (s->mem_index >> 2) - 1); | |
3848 | break; | |
3849 | case 0x15: /* pextrw */ | |
3850 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3851 | xmm_regs[reg].XMM_W(val & 7))); | |
3852 | if (mod == 3) | |
3853 | gen_op_mov_reg_T0(ot, rm); | |
3854 | else | |
3855 | tcg_gen_qemu_st16(cpu_T[0], cpu_A0, | |
3856 | (s->mem_index >> 2) - 1); | |
3857 | break; | |
3858 | case 0x16: | |
3859 | if (ot == OT_LONG) { /* pextrd */ | |
3860 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, | |
3861 | offsetof(CPUX86State, | |
3862 | xmm_regs[reg].XMM_L(val & 3))); | |
a7812ae4 | 3863 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
222a3336 | 3864 | if (mod == 3) |
a7812ae4 | 3865 | gen_op_mov_reg_v(ot, rm, cpu_T[0]); |
222a3336 | 3866 | else |
a7812ae4 | 3867 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, |
222a3336 AZ |
3868 | (s->mem_index >> 2) - 1); |
3869 | } else { /* pextrq */ | |
a7812ae4 | 3870 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3871 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
3872 | offsetof(CPUX86State, | |
3873 | xmm_regs[reg].XMM_Q(val & 1))); | |
3874 | if (mod == 3) | |
3875 | gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); | |
3876 | else | |
3877 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, | |
3878 | (s->mem_index >> 2) - 1); | |
a7812ae4 PB |
3879 | #else |
3880 | goto illegal_op; | |
3881 | #endif | |
222a3336 AZ |
3882 | } |
3883 | break; | |
3884 | case 0x17: /* extractps */ | |
3885 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3886 | xmm_regs[reg].XMM_L(val & 3))); | |
3887 | if (mod == 3) | |
3888 | gen_op_mov_reg_T0(ot, rm); | |
3889 | else | |
3890 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, | |
3891 | (s->mem_index >> 2) - 1); | |
3892 | break; | |
3893 | case 0x20: /* pinsrb */ | |
3894 | if (mod == 3) | |
3895 | gen_op_mov_TN_reg(OT_LONG, 0, rm); | |
3896 | else | |
a7812ae4 | 3897 | tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0, |
222a3336 | 3898 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3899 | tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, |
222a3336 AZ |
3900 | xmm_regs[reg].XMM_B(val & 15))); |
3901 | break; | |
3902 | case 0x21: /* insertps */ | |
a7812ae4 | 3903 | if (mod == 3) { |
222a3336 AZ |
3904 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
3905 | offsetof(CPUX86State,xmm_regs[rm] | |
3906 | .XMM_L((val >> 6) & 3))); | |
a7812ae4 PB |
3907 | } else { |
3908 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, | |
222a3336 | 3909 | (s->mem_index >> 2) - 1); |
a7812ae4 PB |
3910 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
3911 | } | |
222a3336 AZ |
3912 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3913 | offsetof(CPUX86State,xmm_regs[reg] | |
3914 | .XMM_L((val >> 4) & 3))); | |
3915 | if ((val >> 0) & 1) | |
3916 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3917 | cpu_env, offsetof(CPUX86State, | |
3918 | xmm_regs[reg].XMM_L(0))); | |
3919 | if ((val >> 1) & 1) | |
3920 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3921 | cpu_env, offsetof(CPUX86State, | |
3922 | xmm_regs[reg].XMM_L(1))); | |
3923 | if ((val >> 2) & 1) | |
3924 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3925 | cpu_env, offsetof(CPUX86State, | |
3926 | xmm_regs[reg].XMM_L(2))); | |
3927 | if ((val >> 3) & 1) | |
3928 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3929 | cpu_env, offsetof(CPUX86State, | |
3930 | xmm_regs[reg].XMM_L(3))); | |
3931 | break; | |
3932 | case 0x22: | |
3933 | if (ot == OT_LONG) { /* pinsrd */ | |
3934 | if (mod == 3) | |
a7812ae4 | 3935 | gen_op_mov_v_reg(ot, cpu_tmp0, rm); |
222a3336 | 3936 | else |
a7812ae4 | 3937 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3938 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3939 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3940 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3941 | offsetof(CPUX86State, | |
3942 | xmm_regs[reg].XMM_L(val & 3))); | |
3943 | } else { /* pinsrq */ | |
a7812ae4 | 3944 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3945 | if (mod == 3) |
3946 | gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); | |
3947 | else | |
3948 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, | |
3949 | (s->mem_index >> 2) - 1); | |
3950 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, | |
3951 | offsetof(CPUX86State, | |
3952 | xmm_regs[reg].XMM_Q(val & 1))); | |
a7812ae4 PB |
3953 | #else |
3954 | goto illegal_op; | |
3955 | #endif | |
222a3336 AZ |
3956 | } |
3957 | break; | |
3958 | } | |
3959 | return; | |
3960 | } | |
4242b1bd AZ |
3961 | |
3962 | if (b1) { | |
3963 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3964 | if (mod == 3) { | |
3965 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3966 | } else { | |
3967 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
0af10c86 | 3968 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4242b1bd AZ |
3969 | gen_ldo_env_A0(s->mem_index, op2_offset); |
3970 | } | |
3971 | } else { | |
3972 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3973 | if (mod == 3) { | |
3974 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3975 | } else { | |
3976 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
0af10c86 | 3977 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4242b1bd AZ |
3978 | gen_ldq_env_A0(s->mem_index, op2_offset); |
3979 | } | |
3980 | } | |
0af10c86 | 3981 | val = cpu_ldub_code(env, s->pc++); |
4242b1bd | 3982 | |
222a3336 | 3983 | if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ |
3ca51d07 | 3984 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 AZ |
3985 | |
3986 | if (s->dflag == 2) | |
3987 | /* The helper must use entire 64-bit gp registers */ | |
3988 | val |= 1 << 8; | |
3989 | } | |
3990 | ||
4242b1bd AZ |
3991 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3992 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 3993 | sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
4242b1bd | 3994 | break; |
664e0f19 FB |
3995 | default: |
3996 | goto illegal_op; | |
3997 | } | |
3998 | } else { | |
3999 | /* generic MMX or SSE operation */ | |
d1e42c5c | 4000 | switch(b) { |
d1e42c5c FB |
4001 | case 0x70: /* pshufx insn */ |
4002 | case 0xc6: /* pshufx insn */ | |
4003 | case 0xc2: /* compare insns */ | |
4004 | s->rip_offset = 1; | |
4005 | break; | |
4006 | default: | |
4007 | break; | |
664e0f19 FB |
4008 | } |
4009 | if (is_xmm) { | |
4010 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4011 | if (mod != 3) { | |
0af10c86 | 4012 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 4013 | op2_offset = offsetof(CPUX86State,xmm_t0); |
480c1cdb | 4014 | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
664e0f19 FB |
4015 | b == 0xc2)) { |
4016 | /* specific case for SSE single instructions */ | |
4017 | if (b1 == 2) { | |
4018 | /* 32 bit access */ | |
57fec1fe | 4019 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 4020 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 FB |
4021 | } else { |
4022 | /* 64 bit access */ | |
8686c490 | 4023 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0))); |
664e0f19 FB |
4024 | } |
4025 | } else { | |
8686c490 | 4026 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
4027 | } |
4028 | } else { | |
4029 | rm = (modrm & 7) | REX_B(s); | |
4030 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
4031 | } | |
4032 | } else { | |
4033 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4034 | if (mod != 3) { | |
0af10c86 | 4035 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 4036 | op2_offset = offsetof(CPUX86State,mmx_t0); |
8686c490 | 4037 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
4038 | } else { |
4039 | rm = (modrm & 7); | |
4040 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4041 | } | |
4042 | } | |
4043 | switch(b) { | |
a35f3ec7 | 4044 | case 0x0f: /* 3DNow! data insns */ |
e771edab AJ |
4045 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) |
4046 | goto illegal_op; | |
0af10c86 | 4047 | val = cpu_ldub_code(env, s->pc++); |
d3eb5eae BS |
4048 | sse_fn_epp = sse_op_table5[val]; |
4049 | if (!sse_fn_epp) { | |
a35f3ec7 | 4050 | goto illegal_op; |
c4baa050 | 4051 | } |
5af45186 FB |
4052 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4053 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4054 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
a35f3ec7 | 4055 | break; |
664e0f19 FB |
4056 | case 0x70: /* pshufx insn */ |
4057 | case 0xc6: /* pshufx insn */ | |
0af10c86 | 4058 | val = cpu_ldub_code(env, s->pc++); |
5af45186 FB |
4059 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4060 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4061 | /* XXX: introduce a new table? */ |
d3eb5eae | 4062 | sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp; |
c4baa050 | 4063 | sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
664e0f19 FB |
4064 | break; |
4065 | case 0xc2: | |
4066 | /* compare insns */ | |
0af10c86 | 4067 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
4068 | if (val >= 8) |
4069 | goto illegal_op; | |
d3eb5eae | 4070 | sse_fn_epp = sse_op_table4[val][b1]; |
c4baa050 | 4071 | |
5af45186 FB |
4072 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4073 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4074 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 | 4075 | break; |
b8b6a50b FB |
4076 | case 0xf7: |
4077 | /* maskmov : we must prepare A0 */ | |
4078 | if (mod != 3) | |
4079 | goto illegal_op; | |
4080 | #ifdef TARGET_X86_64 | |
4081 | if (s->aflag == 2) { | |
4082 | gen_op_movq_A0_reg(R_EDI); | |
4083 | } else | |
4084 | #endif | |
4085 | { | |
4086 | gen_op_movl_A0_reg(R_EDI); | |
4087 | if (s->aflag == 0) | |
4088 | gen_op_andl_A0_ffff(); | |
4089 | } | |
4090 | gen_add_A0_ds_seg(s); | |
4091 | ||
4092 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); | |
4093 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4094 | /* XXX: introduce a new table? */ |
d3eb5eae BS |
4095 | sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp; |
4096 | sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0); | |
b8b6a50b | 4097 | break; |
664e0f19 | 4098 | default: |
5af45186 FB |
4099 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4100 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4101 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
4102 | break; |
4103 | } | |
4104 | if (b == 0x2e || b == 0x2f) { | |
3ca51d07 | 4105 | set_cc_op(s, CC_OP_EFLAGS); |
664e0f19 FB |
4106 | } |
4107 | } | |
4108 | } | |
4109 | ||
2c0262af FB |
4110 | /* convert one instruction. s->is_jmp is set if the translation must |
4111 | be stopped. Return the next pc value */ | |
0af10c86 BS |
4112 | static target_ulong disas_insn(CPUX86State *env, DisasContext *s, |
4113 | target_ulong pc_start) | |
2c0262af FB |
4114 | { |
4115 | int b, prefixes, aflag, dflag; | |
4116 | int shift, ot; | |
4117 | int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val; | |
14ce26e7 FB |
4118 | target_ulong next_eip, tval; |
4119 | int rex_w, rex_r; | |
2c0262af | 4120 | |
fdefe51c | 4121 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
70cff25e | 4122 | tcg_gen_debug_insn_start(pc_start); |
fdefe51c | 4123 | } |
2c0262af FB |
4124 | s->pc = pc_start; |
4125 | prefixes = 0; | |
4126 | aflag = s->code32; | |
4127 | dflag = s->code32; | |
4128 | s->override = -1; | |
14ce26e7 FB |
4129 | rex_w = -1; |
4130 | rex_r = 0; | |
4131 | #ifdef TARGET_X86_64 | |
4132 | s->rex_x = 0; | |
4133 | s->rex_b = 0; | |
5fafdf24 | 4134 | x86_64_hregs = 0; |
14ce26e7 FB |
4135 | #endif |
4136 | s->rip_offset = 0; /* for relative ip address */ | |
2c0262af | 4137 | next_byte: |
0af10c86 | 4138 | b = cpu_ldub_code(env, s->pc); |
2c0262af FB |
4139 | s->pc++; |
4140 | /* check prefixes */ | |
14ce26e7 FB |
4141 | #ifdef TARGET_X86_64 |
4142 | if (CODE64(s)) { | |
4143 | switch (b) { | |
4144 | case 0xf3: | |
4145 | prefixes |= PREFIX_REPZ; | |
4146 | goto next_byte; | |
4147 | case 0xf2: | |
4148 | prefixes |= PREFIX_REPNZ; | |
4149 | goto next_byte; | |
4150 | case 0xf0: | |
4151 | prefixes |= PREFIX_LOCK; | |
4152 | goto next_byte; | |
4153 | case 0x2e: | |
4154 | s->override = R_CS; | |
4155 | goto next_byte; | |
4156 | case 0x36: | |
4157 | s->override = R_SS; | |
4158 | goto next_byte; | |
4159 | case 0x3e: | |
4160 | s->override = R_DS; | |
4161 | goto next_byte; | |
4162 | case 0x26: | |
4163 | s->override = R_ES; | |
4164 | goto next_byte; | |
4165 | case 0x64: | |
4166 | s->override = R_FS; | |
4167 | goto next_byte; | |
4168 | case 0x65: | |
4169 | s->override = R_GS; | |
4170 | goto next_byte; | |
4171 | case 0x66: | |
4172 | prefixes |= PREFIX_DATA; | |
4173 | goto next_byte; | |
4174 | case 0x67: | |
4175 | prefixes |= PREFIX_ADR; | |
4176 | goto next_byte; | |
4177 | case 0x40 ... 0x4f: | |
4178 | /* REX prefix */ | |
4179 | rex_w = (b >> 3) & 1; | |
4180 | rex_r = (b & 0x4) << 1; | |
4181 | s->rex_x = (b & 0x2) << 2; | |
4182 | REX_B(s) = (b & 0x1) << 3; | |
4183 | x86_64_hregs = 1; /* select uniform byte register addressing */ | |
4184 | goto next_byte; | |
4185 | } | |
4186 | if (rex_w == 1) { | |
4187 | /* 0x66 is ignored if rex.w is set */ | |
4188 | dflag = 2; | |
4189 | } else { | |
4190 | if (prefixes & PREFIX_DATA) | |
4191 | dflag ^= 1; | |
4192 | } | |
4193 | if (!(prefixes & PREFIX_ADR)) | |
4194 | aflag = 2; | |
5fafdf24 | 4195 | } else |
14ce26e7 FB |
4196 | #endif |
4197 | { | |
4198 | switch (b) { | |
4199 | case 0xf3: | |
4200 | prefixes |= PREFIX_REPZ; | |
4201 | goto next_byte; | |
4202 | case 0xf2: | |
4203 | prefixes |= PREFIX_REPNZ; | |
4204 | goto next_byte; | |
4205 | case 0xf0: | |
4206 | prefixes |= PREFIX_LOCK; | |
4207 | goto next_byte; | |
4208 | case 0x2e: | |
4209 | s->override = R_CS; | |
4210 | goto next_byte; | |
4211 | case 0x36: | |
4212 | s->override = R_SS; | |
4213 | goto next_byte; | |
4214 | case 0x3e: | |
4215 | s->override = R_DS; | |
4216 | goto next_byte; | |
4217 | case 0x26: | |
4218 | s->override = R_ES; | |
4219 | goto next_byte; | |
4220 | case 0x64: | |
4221 | s->override = R_FS; | |
4222 | goto next_byte; | |
4223 | case 0x65: | |
4224 | s->override = R_GS; | |
4225 | goto next_byte; | |
4226 | case 0x66: | |
4227 | prefixes |= PREFIX_DATA; | |
4228 | goto next_byte; | |
4229 | case 0x67: | |
4230 | prefixes |= PREFIX_ADR; | |
4231 | goto next_byte; | |
4232 | } | |
4233 | if (prefixes & PREFIX_DATA) | |
4234 | dflag ^= 1; | |
4235 | if (prefixes & PREFIX_ADR) | |
4236 | aflag ^= 1; | |
2c0262af FB |
4237 | } |
4238 | ||
2c0262af FB |
4239 | s->prefix = prefixes; |
4240 | s->aflag = aflag; | |
4241 | s->dflag = dflag; | |
4242 | ||
4243 | /* lock generation */ | |
4244 | if (prefixes & PREFIX_LOCK) | |
a7812ae4 | 4245 | gen_helper_lock(); |
2c0262af FB |
4246 | |
4247 | /* now check op code */ | |
4248 | reswitch: | |
4249 | switch(b) { | |
4250 | case 0x0f: | |
4251 | /**************************/ | |
4252 | /* extended op code */ | |
0af10c86 | 4253 | b = cpu_ldub_code(env, s->pc++) | 0x100; |
2c0262af | 4254 | goto reswitch; |
3b46e624 | 4255 | |
2c0262af FB |
4256 | /**************************/ |
4257 | /* arith & logic */ | |
4258 | case 0x00 ... 0x05: | |
4259 | case 0x08 ... 0x0d: | |
4260 | case 0x10 ... 0x15: | |
4261 | case 0x18 ... 0x1d: | |
4262 | case 0x20 ... 0x25: | |
4263 | case 0x28 ... 0x2d: | |
4264 | case 0x30 ... 0x35: | |
4265 | case 0x38 ... 0x3d: | |
4266 | { | |
4267 | int op, f, val; | |
4268 | op = (b >> 3) & 7; | |
4269 | f = (b >> 1) & 3; | |
4270 | ||
4271 | if ((b & 1) == 0) | |
4272 | ot = OT_BYTE; | |
4273 | else | |
14ce26e7 | 4274 | ot = dflag + OT_WORD; |
3b46e624 | 4275 | |
2c0262af FB |
4276 | switch(f) { |
4277 | case 0: /* OP Ev, Gv */ | |
0af10c86 | 4278 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4279 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 4280 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4281 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4282 | if (mod != 3) { |
0af10c86 | 4283 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
4284 | opreg = OR_TMP0; |
4285 | } else if (op == OP_XORL && rm == reg) { | |
4286 | xor_zero: | |
4287 | /* xor reg, reg optimisation */ | |
4288 | gen_op_movl_T0_0(); | |
3ca51d07 | 4289 | set_cc_op(s, CC_OP_LOGICB + ot); |
57fec1fe | 4290 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
4291 | gen_op_update1_cc(); |
4292 | break; | |
4293 | } else { | |
4294 | opreg = rm; | |
4295 | } | |
57fec1fe | 4296 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4297 | gen_op(s, op, ot, opreg); |
4298 | break; | |
4299 | case 1: /* OP Gv, Ev */ | |
0af10c86 | 4300 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4301 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
4302 | reg = ((modrm >> 3) & 7) | rex_r; |
4303 | rm = (modrm & 7) | REX_B(s); | |
2c0262af | 4304 | if (mod != 3) { |
0af10c86 | 4305 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 4306 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af FB |
4307 | } else if (op == OP_XORL && rm == reg) { |
4308 | goto xor_zero; | |
4309 | } else { | |
57fec1fe | 4310 | gen_op_mov_TN_reg(ot, 1, rm); |
2c0262af FB |
4311 | } |
4312 | gen_op(s, op, ot, reg); | |
4313 | break; | |
4314 | case 2: /* OP A, Iv */ | |
0af10c86 | 4315 | val = insn_get(env, s, ot); |
2c0262af FB |
4316 | gen_op_movl_T1_im(val); |
4317 | gen_op(s, op, ot, OR_EAX); | |
4318 | break; | |
4319 | } | |
4320 | } | |
4321 | break; | |
4322 | ||
ec9d6075 FB |
4323 | case 0x82: |
4324 | if (CODE64(s)) | |
4325 | goto illegal_op; | |
2c0262af FB |
4326 | case 0x80: /* GRP1 */ |
4327 | case 0x81: | |
4328 | case 0x83: | |
4329 | { | |
4330 | int val; | |
4331 | ||
4332 | if ((b & 1) == 0) | |
4333 | ot = OT_BYTE; | |
4334 | else | |
14ce26e7 | 4335 | ot = dflag + OT_WORD; |
3b46e624 | 4336 | |
0af10c86 | 4337 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4338 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4339 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4340 | op = (modrm >> 3) & 7; |
3b46e624 | 4341 | |
2c0262af | 4342 | if (mod != 3) { |
14ce26e7 FB |
4343 | if (b == 0x83) |
4344 | s->rip_offset = 1; | |
4345 | else | |
4346 | s->rip_offset = insn_const_size(ot); | |
0af10c86 | 4347 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
4348 | opreg = OR_TMP0; |
4349 | } else { | |
14ce26e7 | 4350 | opreg = rm; |
2c0262af FB |
4351 | } |
4352 | ||
4353 | switch(b) { | |
4354 | default: | |
4355 | case 0x80: | |
4356 | case 0x81: | |
d64477af | 4357 | case 0x82: |
0af10c86 | 4358 | val = insn_get(env, s, ot); |
2c0262af FB |
4359 | break; |
4360 | case 0x83: | |
0af10c86 | 4361 | val = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
4362 | break; |
4363 | } | |
4364 | gen_op_movl_T1_im(val); | |
4365 | gen_op(s, op, ot, opreg); | |
4366 | } | |
4367 | break; | |
4368 | ||
4369 | /**************************/ | |
4370 | /* inc, dec, and other misc arith */ | |
4371 | case 0x40 ... 0x47: /* inc Gv */ | |
4372 | ot = dflag ? OT_LONG : OT_WORD; | |
4373 | gen_inc(s, ot, OR_EAX + (b & 7), 1); | |
4374 | break; | |
4375 | case 0x48 ... 0x4f: /* dec Gv */ | |
4376 | ot = dflag ? OT_LONG : OT_WORD; | |
4377 | gen_inc(s, ot, OR_EAX + (b & 7), -1); | |
4378 | break; | |
4379 | case 0xf6: /* GRP3 */ | |
4380 | case 0xf7: | |
4381 | if ((b & 1) == 0) | |
4382 | ot = OT_BYTE; | |
4383 | else | |
14ce26e7 | 4384 | ot = dflag + OT_WORD; |
2c0262af | 4385 | |
0af10c86 | 4386 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4387 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4388 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4389 | op = (modrm >> 3) & 7; |
4390 | if (mod != 3) { | |
14ce26e7 FB |
4391 | if (op == 0) |
4392 | s->rip_offset = insn_const_size(ot); | |
0af10c86 | 4393 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 4394 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4395 | } else { |
57fec1fe | 4396 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4397 | } |
4398 | ||
4399 | switch(op) { | |
4400 | case 0: /* test */ | |
0af10c86 | 4401 | val = insn_get(env, s, ot); |
2c0262af FB |
4402 | gen_op_movl_T1_im(val); |
4403 | gen_op_testl_T0_T1_cc(); | |
3ca51d07 | 4404 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af FB |
4405 | break; |
4406 | case 2: /* not */ | |
b6abf97d | 4407 | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4408 | if (mod != 3) { |
57fec1fe | 4409 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4410 | } else { |
57fec1fe | 4411 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4412 | } |
4413 | break; | |
4414 | case 3: /* neg */ | |
b6abf97d | 4415 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4416 | if (mod != 3) { |
57fec1fe | 4417 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4418 | } else { |
57fec1fe | 4419 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4420 | } |
4421 | gen_op_update_neg_cc(); | |
3ca51d07 | 4422 | set_cc_op(s, CC_OP_SUBB + ot); |
2c0262af FB |
4423 | break; |
4424 | case 4: /* mul */ | |
4425 | switch(ot) { | |
4426 | case OT_BYTE: | |
0211e5af FB |
4427 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4428 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); | |
4429 | tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); | |
4430 | /* XXX: use 32 bit mul which could be faster */ | |
4431 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4432 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4433 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4434 | tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); | |
3ca51d07 | 4435 | set_cc_op(s, CC_OP_MULB); |
2c0262af FB |
4436 | break; |
4437 | case OT_WORD: | |
0211e5af FB |
4438 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4439 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); | |
4440 | tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); | |
4441 | /* XXX: use 32 bit mul which could be faster */ | |
4442 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4443 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4444 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4445 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4446 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4447 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
3ca51d07 | 4448 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4449 | break; |
4450 | default: | |
4451 | case OT_LONG: | |
0211e5af FB |
4452 | #ifdef TARGET_X86_64 |
4453 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4454 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); | |
4455 | tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); | |
4456 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4457 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4458 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4459 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4460 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4461 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4462 | #else | |
4463 | { | |
a7812ae4 PB |
4464 | TCGv_i64 t0, t1; |
4465 | t0 = tcg_temp_new_i64(); | |
4466 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4467 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4468 | tcg_gen_extu_i32_i64(t0, cpu_T[0]); | |
4469 | tcg_gen_extu_i32_i64(t1, cpu_T[1]); | |
4470 | tcg_gen_mul_i64(t0, t0, t1); | |
4471 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4472 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4473 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4474 | tcg_gen_shri_i64(t0, t0, 32); | |
4475 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4476 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4477 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4478 | } | |
4479 | #endif | |
3ca51d07 | 4480 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4481 | break; |
14ce26e7 FB |
4482 | #ifdef TARGET_X86_64 |
4483 | case OT_QUAD: | |
7923057b | 4484 | gen_helper_mulq_EAX_T0(cpu_env, cpu_T[0]); |
3ca51d07 | 4485 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4486 | break; |
4487 | #endif | |
2c0262af | 4488 | } |
2c0262af FB |
4489 | break; |
4490 | case 5: /* imul */ | |
4491 | switch(ot) { | |
4492 | case OT_BYTE: | |
0211e5af FB |
4493 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4494 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4495 | tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); | |
4496 | /* XXX: use 32 bit mul which could be faster */ | |
4497 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4498 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4499 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4500 | tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]); | |
4501 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
3ca51d07 | 4502 | set_cc_op(s, CC_OP_MULB); |
2c0262af FB |
4503 | break; |
4504 | case OT_WORD: | |
0211e5af FB |
4505 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4506 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4507 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4508 | /* XXX: use 32 bit mul which could be faster */ | |
4509 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4510 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4511 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4512 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4513 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4514 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4515 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
3ca51d07 | 4516 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4517 | break; |
4518 | default: | |
4519 | case OT_LONG: | |
0211e5af FB |
4520 | #ifdef TARGET_X86_64 |
4521 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4522 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4523 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4524 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4525 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4526 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4527 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4528 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4529 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4530 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4531 | #else | |
4532 | { | |
a7812ae4 PB |
4533 | TCGv_i64 t0, t1; |
4534 | t0 = tcg_temp_new_i64(); | |
4535 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4536 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4537 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); | |
4538 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4539 | tcg_gen_mul_i64(t0, t0, t1); | |
4540 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4541 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4542 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4543 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4544 | tcg_gen_shri_i64(t0, t0, 32); | |
4545 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4546 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4547 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4548 | } | |
4549 | #endif | |
3ca51d07 | 4550 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4551 | break; |
14ce26e7 FB |
4552 | #ifdef TARGET_X86_64 |
4553 | case OT_QUAD: | |
7923057b | 4554 | gen_helper_imulq_EAX_T0(cpu_env, cpu_T[0]); |
3ca51d07 | 4555 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4556 | break; |
4557 | #endif | |
2c0262af | 4558 | } |
2c0262af FB |
4559 | break; |
4560 | case 6: /* div */ | |
4561 | switch(ot) { | |
4562 | case OT_BYTE: | |
14ce26e7 | 4563 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4564 | gen_helper_divb_AL(cpu_env, cpu_T[0]); |
2c0262af FB |
4565 | break; |
4566 | case OT_WORD: | |
14ce26e7 | 4567 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4568 | gen_helper_divw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4569 | break; |
4570 | default: | |
4571 | case OT_LONG: | |
14ce26e7 | 4572 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4573 | gen_helper_divl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4574 | break; |
4575 | #ifdef TARGET_X86_64 | |
4576 | case OT_QUAD: | |
4577 | gen_jmp_im(pc_start - s->cs_base); | |
7923057b | 4578 | gen_helper_divq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4579 | break; |
14ce26e7 | 4580 | #endif |
2c0262af FB |
4581 | } |
4582 | break; | |
4583 | case 7: /* idiv */ | |
4584 | switch(ot) { | |
4585 | case OT_BYTE: | |
14ce26e7 | 4586 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4587 | gen_helper_idivb_AL(cpu_env, cpu_T[0]); |
2c0262af FB |
4588 | break; |
4589 | case OT_WORD: | |
14ce26e7 | 4590 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4591 | gen_helper_idivw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4592 | break; |
4593 | default: | |
4594 | case OT_LONG: | |
14ce26e7 | 4595 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4596 | gen_helper_idivl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4597 | break; |
4598 | #ifdef TARGET_X86_64 | |
4599 | case OT_QUAD: | |
4600 | gen_jmp_im(pc_start - s->cs_base); | |
7923057b | 4601 | gen_helper_idivq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4602 | break; |
14ce26e7 | 4603 | #endif |
2c0262af FB |
4604 | } |
4605 | break; | |
4606 | default: | |
4607 | goto illegal_op; | |
4608 | } | |
4609 | break; | |
4610 | ||
4611 | case 0xfe: /* GRP4 */ | |
4612 | case 0xff: /* GRP5 */ | |
4613 | if ((b & 1) == 0) | |
4614 | ot = OT_BYTE; | |
4615 | else | |
14ce26e7 | 4616 | ot = dflag + OT_WORD; |
2c0262af | 4617 | |
0af10c86 | 4618 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4619 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4620 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4621 | op = (modrm >> 3) & 7; |
4622 | if (op >= 2 && b == 0xfe) { | |
4623 | goto illegal_op; | |
4624 | } | |
14ce26e7 | 4625 | if (CODE64(s)) { |
aba9d61e | 4626 | if (op == 2 || op == 4) { |
14ce26e7 FB |
4627 | /* operand size for jumps is 64 bit */ |
4628 | ot = OT_QUAD; | |
aba9d61e | 4629 | } else if (op == 3 || op == 5) { |
41b1e61f | 4630 | ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD; |
14ce26e7 FB |
4631 | } else if (op == 6) { |
4632 | /* default push size is 64 bit */ | |
4633 | ot = dflag ? OT_QUAD : OT_WORD; | |
4634 | } | |
4635 | } | |
2c0262af | 4636 | if (mod != 3) { |
0af10c86 | 4637 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 4638 | if (op >= 2 && op != 3 && op != 5) |
57fec1fe | 4639 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4640 | } else { |
57fec1fe | 4641 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4642 | } |
4643 | ||
4644 | switch(op) { | |
4645 | case 0: /* inc Ev */ | |
4646 | if (mod != 3) | |
4647 | opreg = OR_TMP0; | |
4648 | else | |
4649 | opreg = rm; | |
4650 | gen_inc(s, ot, opreg, 1); | |
4651 | break; | |
4652 | case 1: /* dec Ev */ | |
4653 | if (mod != 3) | |
4654 | opreg = OR_TMP0; | |
4655 | else | |
4656 | opreg = rm; | |
4657 | gen_inc(s, ot, opreg, -1); | |
4658 | break; | |
4659 | case 2: /* call Ev */ | |
4f31916f | 4660 | /* XXX: optimize if memory (no 'and' is necessary) */ |
2c0262af FB |
4661 | if (s->dflag == 0) |
4662 | gen_op_andl_T0_ffff(); | |
2c0262af | 4663 | next_eip = s->pc - s->cs_base; |
1ef38687 | 4664 | gen_movtl_T1_im(next_eip); |
4f31916f FB |
4665 | gen_push_T1(s); |
4666 | gen_op_jmp_T0(); | |
2c0262af FB |
4667 | gen_eob(s); |
4668 | break; | |
61382a50 | 4669 | case 3: /* lcall Ev */ |
57fec1fe | 4670 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4671 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4672 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4673 | do_lcall: |
4674 | if (s->pe && !s->vm86) { | |
773cdfcc | 4675 | gen_update_cc_op(s); |
14ce26e7 | 4676 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4677 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
4678 | gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
4679 | tcg_const_i32(dflag), | |
a7812ae4 | 4680 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 4681 | } else { |
b6abf97d | 4682 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
4683 | gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1], |
4684 | tcg_const_i32(dflag), | |
a7812ae4 | 4685 | tcg_const_i32(s->pc - s->cs_base)); |
2c0262af FB |
4686 | } |
4687 | gen_eob(s); | |
4688 | break; | |
4689 | case 4: /* jmp Ev */ | |
4690 | if (s->dflag == 0) | |
4691 | gen_op_andl_T0_ffff(); | |
4692 | gen_op_jmp_T0(); | |
4693 | gen_eob(s); | |
4694 | break; | |
4695 | case 5: /* ljmp Ev */ | |
57fec1fe | 4696 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4697 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4698 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4699 | do_ljmp: |
4700 | if (s->pe && !s->vm86) { | |
773cdfcc | 4701 | gen_update_cc_op(s); |
14ce26e7 | 4702 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4703 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 4704 | gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
a7812ae4 | 4705 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 4706 | } else { |
3bd7da9e | 4707 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
4708 | gen_op_movl_T0_T1(); |
4709 | gen_op_jmp_T0(); | |
4710 | } | |
4711 | gen_eob(s); | |
4712 | break; | |
4713 | case 6: /* push Ev */ | |
4714 | gen_push_T0(s); | |
4715 | break; | |
4716 | default: | |
4717 | goto illegal_op; | |
4718 | } | |
4719 | break; | |
4720 | ||
4721 | case 0x84: /* test Ev, Gv */ | |
5fafdf24 | 4722 | case 0x85: |
2c0262af FB |
4723 | if ((b & 1) == 0) |
4724 | ot = OT_BYTE; | |
4725 | else | |
14ce26e7 | 4726 | ot = dflag + OT_WORD; |
2c0262af | 4727 | |
0af10c86 | 4728 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4729 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 4730 | |
0af10c86 | 4731 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 4732 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af | 4733 | gen_op_testl_T0_T1_cc(); |
3ca51d07 | 4734 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 4735 | break; |
3b46e624 | 4736 | |
2c0262af FB |
4737 | case 0xa8: /* test eAX, Iv */ |
4738 | case 0xa9: | |
4739 | if ((b & 1) == 0) | |
4740 | ot = OT_BYTE; | |
4741 | else | |
14ce26e7 | 4742 | ot = dflag + OT_WORD; |
0af10c86 | 4743 | val = insn_get(env, s, ot); |
2c0262af | 4744 | |
57fec1fe | 4745 | gen_op_mov_TN_reg(ot, 0, OR_EAX); |
2c0262af FB |
4746 | gen_op_movl_T1_im(val); |
4747 | gen_op_testl_T0_T1_cc(); | |
3ca51d07 | 4748 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 4749 | break; |
3b46e624 | 4750 | |
2c0262af | 4751 | case 0x98: /* CWDE/CBW */ |
14ce26e7 FB |
4752 | #ifdef TARGET_X86_64 |
4753 | if (dflag == 2) { | |
e108dd01 FB |
4754 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
4755 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4756 | gen_op_mov_reg_T0(OT_QUAD, R_EAX); | |
14ce26e7 FB |
4757 | } else |
4758 | #endif | |
e108dd01 FB |
4759 | if (dflag == 1) { |
4760 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4761 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4762 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4763 | } else { | |
4764 | gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX); | |
4765 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4766 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4767 | } | |
2c0262af FB |
4768 | break; |
4769 | case 0x99: /* CDQ/CWD */ | |
14ce26e7 FB |
4770 | #ifdef TARGET_X86_64 |
4771 | if (dflag == 2) { | |
e108dd01 FB |
4772 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
4773 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); | |
4774 | gen_op_mov_reg_T0(OT_QUAD, R_EDX); | |
14ce26e7 FB |
4775 | } else |
4776 | #endif | |
e108dd01 FB |
4777 | if (dflag == 1) { |
4778 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); | |
4779 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4780 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); | |
4781 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4782 | } else { | |
4783 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4784 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4785 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); | |
4786 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4787 | } | |
2c0262af FB |
4788 | break; |
4789 | case 0x1af: /* imul Gv, Ev */ | |
4790 | case 0x69: /* imul Gv, Ev, I */ | |
4791 | case 0x6b: | |
14ce26e7 | 4792 | ot = dflag + OT_WORD; |
0af10c86 | 4793 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
4794 | reg = ((modrm >> 3) & 7) | rex_r; |
4795 | if (b == 0x69) | |
4796 | s->rip_offset = insn_const_size(ot); | |
4797 | else if (b == 0x6b) | |
4798 | s->rip_offset = 1; | |
0af10c86 | 4799 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
2c0262af | 4800 | if (b == 0x69) { |
0af10c86 | 4801 | val = insn_get(env, s, ot); |
2c0262af FB |
4802 | gen_op_movl_T1_im(val); |
4803 | } else if (b == 0x6b) { | |
0af10c86 | 4804 | val = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
4805 | gen_op_movl_T1_im(val); |
4806 | } else { | |
57fec1fe | 4807 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4808 | } |
4809 | ||
14ce26e7 FB |
4810 | #ifdef TARGET_X86_64 |
4811 | if (ot == OT_QUAD) { | |
7923057b | 4812 | gen_helper_imulq_T0_T1(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
14ce26e7 FB |
4813 | } else |
4814 | #endif | |
2c0262af | 4815 | if (ot == OT_LONG) { |
0211e5af FB |
4816 | #ifdef TARGET_X86_64 |
4817 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4818 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4819 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4820 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4821 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4822 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4823 | #else | |
4824 | { | |
a7812ae4 PB |
4825 | TCGv_i64 t0, t1; |
4826 | t0 = tcg_temp_new_i64(); | |
4827 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4828 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); |
4829 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4830 | tcg_gen_mul_i64(t0, t0, t1); | |
4831 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4832 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4833 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4834 | tcg_gen_shri_i64(t0, t0, 32); | |
4835 | tcg_gen_trunc_i64_i32(cpu_T[1], t0); | |
4836 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0); | |
4837 | } | |
4838 | #endif | |
2c0262af | 4839 | } else { |
0211e5af FB |
4840 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4841 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4842 | /* XXX: use 32 bit mul which could be faster */ | |
4843 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4844 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4845 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4846 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
2c0262af | 4847 | } |
57fec1fe | 4848 | gen_op_mov_reg_T0(ot, reg); |
3ca51d07 | 4849 | set_cc_op(s, CC_OP_MULB + ot); |
2c0262af FB |
4850 | break; |
4851 | case 0x1c0: | |
4852 | case 0x1c1: /* xadd Ev, Gv */ | |
4853 | if ((b & 1) == 0) | |
4854 | ot = OT_BYTE; | |
4855 | else | |
14ce26e7 | 4856 | ot = dflag + OT_WORD; |
0af10c86 | 4857 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4858 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
4859 | mod = (modrm >> 6) & 3; |
4860 | if (mod == 3) { | |
14ce26e7 | 4861 | rm = (modrm & 7) | REX_B(s); |
57fec1fe FB |
4862 | gen_op_mov_TN_reg(ot, 0, reg); |
4863 | gen_op_mov_TN_reg(ot, 1, rm); | |
2c0262af | 4864 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4865 | gen_op_mov_reg_T1(ot, reg); |
4866 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 4867 | } else { |
0af10c86 | 4868 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe FB |
4869 | gen_op_mov_TN_reg(ot, 0, reg); |
4870 | gen_op_ld_T1_A0(ot + s->mem_index); | |
2c0262af | 4871 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4872 | gen_op_st_T0_A0(ot + s->mem_index); |
4873 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af FB |
4874 | } |
4875 | gen_op_update2_cc(); | |
3ca51d07 | 4876 | set_cc_op(s, CC_OP_ADDB + ot); |
2c0262af FB |
4877 | break; |
4878 | case 0x1b0: | |
4879 | case 0x1b1: /* cmpxchg Ev, Gv */ | |
cad3a37d | 4880 | { |
1130328e | 4881 | int label1, label2; |
1e4840bf | 4882 | TCGv t0, t1, t2, a0; |
cad3a37d FB |
4883 | |
4884 | if ((b & 1) == 0) | |
4885 | ot = OT_BYTE; | |
4886 | else | |
4887 | ot = dflag + OT_WORD; | |
0af10c86 | 4888 | modrm = cpu_ldub_code(env, s->pc++); |
cad3a37d FB |
4889 | reg = ((modrm >> 3) & 7) | rex_r; |
4890 | mod = (modrm >> 6) & 3; | |
a7812ae4 PB |
4891 | t0 = tcg_temp_local_new(); |
4892 | t1 = tcg_temp_local_new(); | |
4893 | t2 = tcg_temp_local_new(); | |
4894 | a0 = tcg_temp_local_new(); | |
1e4840bf | 4895 | gen_op_mov_v_reg(ot, t1, reg); |
cad3a37d FB |
4896 | if (mod == 3) { |
4897 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 4898 | gen_op_mov_v_reg(ot, t0, rm); |
cad3a37d | 4899 | } else { |
0af10c86 | 4900 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
1e4840bf FB |
4901 | tcg_gen_mov_tl(a0, cpu_A0); |
4902 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
cad3a37d FB |
4903 | rm = 0; /* avoid warning */ |
4904 | } | |
4905 | label1 = gen_new_label(); | |
cc739bb0 | 4906 | tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0); |
1e4840bf FB |
4907 | gen_extu(ot, t2); |
4908 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); | |
f7e80adf | 4909 | label2 = gen_new_label(); |
cad3a37d | 4910 | if (mod == 3) { |
1e4840bf | 4911 | gen_op_mov_reg_v(ot, R_EAX, t0); |
1130328e FB |
4912 | tcg_gen_br(label2); |
4913 | gen_set_label(label1); | |
1e4840bf | 4914 | gen_op_mov_reg_v(ot, rm, t1); |
cad3a37d | 4915 | } else { |
f7e80adf AG |
4916 | /* perform no-op store cycle like physical cpu; must be |
4917 | before changing accumulator to ensure idempotency if | |
4918 | the store faults and the instruction is restarted */ | |
4919 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1e4840bf | 4920 | gen_op_mov_reg_v(ot, R_EAX, t0); |
f7e80adf | 4921 | tcg_gen_br(label2); |
1130328e | 4922 | gen_set_label(label1); |
1e4840bf | 4923 | gen_op_st_v(ot + s->mem_index, t1, a0); |
cad3a37d | 4924 | } |
f7e80adf | 4925 | gen_set_label(label2); |
1e4840bf FB |
4926 | tcg_gen_mov_tl(cpu_cc_src, t0); |
4927 | tcg_gen_mov_tl(cpu_cc_dst, t2); | |
3ca51d07 | 4928 | set_cc_op(s, CC_OP_SUBB + ot); |
1e4840bf FB |
4929 | tcg_temp_free(t0); |
4930 | tcg_temp_free(t1); | |
4931 | tcg_temp_free(t2); | |
4932 | tcg_temp_free(a0); | |
2c0262af | 4933 | } |
2c0262af FB |
4934 | break; |
4935 | case 0x1c7: /* cmpxchg8b */ | |
0af10c86 | 4936 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4937 | mod = (modrm >> 6) & 3; |
71c3558e | 4938 | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
2c0262af | 4939 | goto illegal_op; |
1b9d9ebb FB |
4940 | #ifdef TARGET_X86_64 |
4941 | if (dflag == 2) { | |
4942 | if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) | |
4943 | goto illegal_op; | |
4944 | gen_jmp_im(pc_start - s->cs_base); | |
773cdfcc | 4945 | gen_update_cc_op(s); |
0af10c86 | 4946 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
92fc4b58 | 4947 | gen_helper_cmpxchg16b(cpu_env, cpu_A0); |
1b9d9ebb FB |
4948 | } else |
4949 | #endif | |
4950 | { | |
4951 | if (!(s->cpuid_features & CPUID_CX8)) | |
4952 | goto illegal_op; | |
4953 | gen_jmp_im(pc_start - s->cs_base); | |
773cdfcc | 4954 | gen_update_cc_op(s); |
0af10c86 | 4955 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
92fc4b58 | 4956 | gen_helper_cmpxchg8b(cpu_env, cpu_A0); |
1b9d9ebb | 4957 | } |
3ca51d07 | 4958 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 4959 | break; |
3b46e624 | 4960 | |
2c0262af FB |
4961 | /**************************/ |
4962 | /* push/pop */ | |
4963 | case 0x50 ... 0x57: /* push */ | |
57fec1fe | 4964 | gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s)); |
2c0262af FB |
4965 | gen_push_T0(s); |
4966 | break; | |
4967 | case 0x58 ... 0x5f: /* pop */ | |
14ce26e7 FB |
4968 | if (CODE64(s)) { |
4969 | ot = dflag ? OT_QUAD : OT_WORD; | |
4970 | } else { | |
4971 | ot = dflag + OT_WORD; | |
4972 | } | |
2c0262af | 4973 | gen_pop_T0(s); |
77729c24 | 4974 | /* NOTE: order is important for pop %sp */ |
2c0262af | 4975 | gen_pop_update(s); |
57fec1fe | 4976 | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s)); |
2c0262af FB |
4977 | break; |
4978 | case 0x60: /* pusha */ | |
14ce26e7 FB |
4979 | if (CODE64(s)) |
4980 | goto illegal_op; | |
2c0262af FB |
4981 | gen_pusha(s); |
4982 | break; | |
4983 | case 0x61: /* popa */ | |
14ce26e7 FB |
4984 | if (CODE64(s)) |
4985 | goto illegal_op; | |
2c0262af FB |
4986 | gen_popa(s); |
4987 | break; | |
4988 | case 0x68: /* push Iv */ | |
4989 | case 0x6a: | |
14ce26e7 FB |
4990 | if (CODE64(s)) { |
4991 | ot = dflag ? OT_QUAD : OT_WORD; | |
4992 | } else { | |
4993 | ot = dflag + OT_WORD; | |
4994 | } | |
2c0262af | 4995 | if (b == 0x68) |
0af10c86 | 4996 | val = insn_get(env, s, ot); |
2c0262af | 4997 | else |
0af10c86 | 4998 | val = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
4999 | gen_op_movl_T0_im(val); |
5000 | gen_push_T0(s); | |
5001 | break; | |
5002 | case 0x8f: /* pop Ev */ | |
14ce26e7 FB |
5003 | if (CODE64(s)) { |
5004 | ot = dflag ? OT_QUAD : OT_WORD; | |
5005 | } else { | |
5006 | ot = dflag + OT_WORD; | |
5007 | } | |
0af10c86 | 5008 | modrm = cpu_ldub_code(env, s->pc++); |
77729c24 | 5009 | mod = (modrm >> 6) & 3; |
2c0262af | 5010 | gen_pop_T0(s); |
77729c24 FB |
5011 | if (mod == 3) { |
5012 | /* NOTE: order is important for pop %sp */ | |
5013 | gen_pop_update(s); | |
14ce26e7 | 5014 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 5015 | gen_op_mov_reg_T0(ot, rm); |
77729c24 FB |
5016 | } else { |
5017 | /* NOTE: order is important too for MMU exceptions */ | |
14ce26e7 | 5018 | s->popl_esp_hack = 1 << ot; |
0af10c86 | 5019 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
77729c24 FB |
5020 | s->popl_esp_hack = 0; |
5021 | gen_pop_update(s); | |
5022 | } | |
2c0262af FB |
5023 | break; |
5024 | case 0xc8: /* enter */ | |
5025 | { | |
5026 | int level; | |
0af10c86 | 5027 | val = cpu_lduw_code(env, s->pc); |
2c0262af | 5028 | s->pc += 2; |
0af10c86 | 5029 | level = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5030 | gen_enter(s, val, level); |
5031 | } | |
5032 | break; | |
5033 | case 0xc9: /* leave */ | |
5034 | /* XXX: exception not precise (ESP is updated before potential exception) */ | |
14ce26e7 | 5035 | if (CODE64(s)) { |
57fec1fe FB |
5036 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP); |
5037 | gen_op_mov_reg_T0(OT_QUAD, R_ESP); | |
14ce26e7 | 5038 | } else if (s->ss32) { |
57fec1fe FB |
5039 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
5040 | gen_op_mov_reg_T0(OT_LONG, R_ESP); | |
2c0262af | 5041 | } else { |
57fec1fe FB |
5042 | gen_op_mov_TN_reg(OT_WORD, 0, R_EBP); |
5043 | gen_op_mov_reg_T0(OT_WORD, R_ESP); | |
2c0262af FB |
5044 | } |
5045 | gen_pop_T0(s); | |
14ce26e7 FB |
5046 | if (CODE64(s)) { |
5047 | ot = dflag ? OT_QUAD : OT_WORD; | |
5048 | } else { | |
5049 | ot = dflag + OT_WORD; | |
5050 | } | |
57fec1fe | 5051 | gen_op_mov_reg_T0(ot, R_EBP); |
2c0262af FB |
5052 | gen_pop_update(s); |
5053 | break; | |
5054 | case 0x06: /* push es */ | |
5055 | case 0x0e: /* push cs */ | |
5056 | case 0x16: /* push ss */ | |
5057 | case 0x1e: /* push ds */ | |
14ce26e7 FB |
5058 | if (CODE64(s)) |
5059 | goto illegal_op; | |
2c0262af FB |
5060 | gen_op_movl_T0_seg(b >> 3); |
5061 | gen_push_T0(s); | |
5062 | break; | |
5063 | case 0x1a0: /* push fs */ | |
5064 | case 0x1a8: /* push gs */ | |
5065 | gen_op_movl_T0_seg((b >> 3) & 7); | |
5066 | gen_push_T0(s); | |
5067 | break; | |
5068 | case 0x07: /* pop es */ | |
5069 | case 0x17: /* pop ss */ | |
5070 | case 0x1f: /* pop ds */ | |
14ce26e7 FB |
5071 | if (CODE64(s)) |
5072 | goto illegal_op; | |
2c0262af FB |
5073 | reg = b >> 3; |
5074 | gen_pop_T0(s); | |
5075 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5076 | gen_pop_update(s); | |
5077 | if (reg == R_SS) { | |
a2cc3b24 FB |
5078 | /* if reg == SS, inhibit interrupts/trace. */ |
5079 | /* If several instructions disable interrupts, only the | |
5080 | _first_ does it */ | |
5081 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5082 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5083 | s->tf = 0; |
5084 | } | |
5085 | if (s->is_jmp) { | |
14ce26e7 | 5086 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5087 | gen_eob(s); |
5088 | } | |
5089 | break; | |
5090 | case 0x1a1: /* pop fs */ | |
5091 | case 0x1a9: /* pop gs */ | |
5092 | gen_pop_T0(s); | |
5093 | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); | |
5094 | gen_pop_update(s); | |
5095 | if (s->is_jmp) { | |
14ce26e7 | 5096 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5097 | gen_eob(s); |
5098 | } | |
5099 | break; | |
5100 | ||
5101 | /**************************/ | |
5102 | /* mov */ | |
5103 | case 0x88: | |
5104 | case 0x89: /* mov Gv, Ev */ | |
5105 | if ((b & 1) == 0) | |
5106 | ot = OT_BYTE; | |
5107 | else | |
14ce26e7 | 5108 | ot = dflag + OT_WORD; |
0af10c86 | 5109 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5110 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5111 | |
2c0262af | 5112 | /* generate a generic store */ |
0af10c86 | 5113 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
2c0262af FB |
5114 | break; |
5115 | case 0xc6: | |
5116 | case 0xc7: /* mov Ev, Iv */ | |
5117 | if ((b & 1) == 0) | |
5118 | ot = OT_BYTE; | |
5119 | else | |
14ce26e7 | 5120 | ot = dflag + OT_WORD; |
0af10c86 | 5121 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5122 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5123 | if (mod != 3) { |
5124 | s->rip_offset = insn_const_size(ot); | |
0af10c86 | 5125 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 5126 | } |
0af10c86 | 5127 | val = insn_get(env, s, ot); |
2c0262af FB |
5128 | gen_op_movl_T0_im(val); |
5129 | if (mod != 3) | |
57fec1fe | 5130 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 5131 | else |
57fec1fe | 5132 | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); |
2c0262af FB |
5133 | break; |
5134 | case 0x8a: | |
5135 | case 0x8b: /* mov Ev, Gv */ | |
5136 | if ((b & 1) == 0) | |
5137 | ot = OT_BYTE; | |
5138 | else | |
14ce26e7 | 5139 | ot = OT_WORD + dflag; |
0af10c86 | 5140 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5141 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5142 | |
0af10c86 | 5143 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5144 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
5145 | break; |
5146 | case 0x8e: /* mov seg, Gv */ | |
0af10c86 | 5147 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5148 | reg = (modrm >> 3) & 7; |
5149 | if (reg >= 6 || reg == R_CS) | |
5150 | goto illegal_op; | |
0af10c86 | 5151 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
2c0262af FB |
5152 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
5153 | if (reg == R_SS) { | |
5154 | /* if reg == SS, inhibit interrupts/trace */ | |
a2cc3b24 FB |
5155 | /* If several instructions disable interrupts, only the |
5156 | _first_ does it */ | |
5157 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5158 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5159 | s->tf = 0; |
5160 | } | |
5161 | if (s->is_jmp) { | |
14ce26e7 | 5162 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5163 | gen_eob(s); |
5164 | } | |
5165 | break; | |
5166 | case 0x8c: /* mov Gv, seg */ | |
0af10c86 | 5167 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5168 | reg = (modrm >> 3) & 7; |
5169 | mod = (modrm >> 6) & 3; | |
5170 | if (reg >= 6) | |
5171 | goto illegal_op; | |
5172 | gen_op_movl_T0_seg(reg); | |
14ce26e7 FB |
5173 | if (mod == 3) |
5174 | ot = OT_WORD + dflag; | |
5175 | else | |
5176 | ot = OT_WORD; | |
0af10c86 | 5177 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
5178 | break; |
5179 | ||
5180 | case 0x1b6: /* movzbS Gv, Eb */ | |
5181 | case 0x1b7: /* movzwS Gv, Eb */ | |
5182 | case 0x1be: /* movsbS Gv, Eb */ | |
5183 | case 0x1bf: /* movswS Gv, Eb */ | |
5184 | { | |
5185 | int d_ot; | |
5186 | /* d_ot is the size of destination */ | |
5187 | d_ot = dflag + OT_WORD; | |
5188 | /* ot is the size of source */ | |
5189 | ot = (b & 1) + OT_BYTE; | |
0af10c86 | 5190 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5191 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 5192 | mod = (modrm >> 6) & 3; |
14ce26e7 | 5193 | rm = (modrm & 7) | REX_B(s); |
3b46e624 | 5194 | |
2c0262af | 5195 | if (mod == 3) { |
57fec1fe | 5196 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
5197 | switch(ot | (b & 8)) { |
5198 | case OT_BYTE: | |
e108dd01 | 5199 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5200 | break; |
5201 | case OT_BYTE | 8: | |
e108dd01 | 5202 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5203 | break; |
5204 | case OT_WORD: | |
e108dd01 | 5205 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5206 | break; |
5207 | default: | |
5208 | case OT_WORD | 8: | |
e108dd01 | 5209 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5210 | break; |
5211 | } | |
57fec1fe | 5212 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af | 5213 | } else { |
0af10c86 | 5214 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 5215 | if (b & 8) { |
57fec1fe | 5216 | gen_op_lds_T0_A0(ot + s->mem_index); |
2c0262af | 5217 | } else { |
57fec1fe | 5218 | gen_op_ldu_T0_A0(ot + s->mem_index); |
2c0262af | 5219 | } |
57fec1fe | 5220 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5221 | } |
5222 | } | |
5223 | break; | |
5224 | ||
5225 | case 0x8d: /* lea */ | |
14ce26e7 | 5226 | ot = dflag + OT_WORD; |
0af10c86 | 5227 | modrm = cpu_ldub_code(env, s->pc++); |
3a1d9b8b FB |
5228 | mod = (modrm >> 6) & 3; |
5229 | if (mod == 3) | |
5230 | goto illegal_op; | |
14ce26e7 | 5231 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5232 | /* we must ensure that no segment is added */ |
5233 | s->override = -1; | |
5234 | val = s->addseg; | |
5235 | s->addseg = 0; | |
0af10c86 | 5236 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 5237 | s->addseg = val; |
57fec1fe | 5238 | gen_op_mov_reg_A0(ot - OT_WORD, reg); |
2c0262af | 5239 | break; |
3b46e624 | 5240 | |
2c0262af FB |
5241 | case 0xa0: /* mov EAX, Ov */ |
5242 | case 0xa1: | |
5243 | case 0xa2: /* mov Ov, EAX */ | |
5244 | case 0xa3: | |
2c0262af | 5245 | { |
14ce26e7 FB |
5246 | target_ulong offset_addr; |
5247 | ||
5248 | if ((b & 1) == 0) | |
5249 | ot = OT_BYTE; | |
5250 | else | |
5251 | ot = dflag + OT_WORD; | |
5252 | #ifdef TARGET_X86_64 | |
8f091a59 | 5253 | if (s->aflag == 2) { |
0af10c86 | 5254 | offset_addr = cpu_ldq_code(env, s->pc); |
14ce26e7 | 5255 | s->pc += 8; |
57fec1fe | 5256 | gen_op_movq_A0_im(offset_addr); |
5fafdf24 | 5257 | } else |
14ce26e7 FB |
5258 | #endif |
5259 | { | |
5260 | if (s->aflag) { | |
0af10c86 | 5261 | offset_addr = insn_get(env, s, OT_LONG); |
14ce26e7 | 5262 | } else { |
0af10c86 | 5263 | offset_addr = insn_get(env, s, OT_WORD); |
14ce26e7 FB |
5264 | } |
5265 | gen_op_movl_A0_im(offset_addr); | |
5266 | } | |
664e0f19 | 5267 | gen_add_A0_ds_seg(s); |
14ce26e7 | 5268 | if ((b & 2) == 0) { |
57fec1fe FB |
5269 | gen_op_ld_T0_A0(ot + s->mem_index); |
5270 | gen_op_mov_reg_T0(ot, R_EAX); | |
14ce26e7 | 5271 | } else { |
57fec1fe FB |
5272 | gen_op_mov_TN_reg(ot, 0, R_EAX); |
5273 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af FB |
5274 | } |
5275 | } | |
2c0262af FB |
5276 | break; |
5277 | case 0xd7: /* xlat */ | |
14ce26e7 | 5278 | #ifdef TARGET_X86_64 |
8f091a59 | 5279 | if (s->aflag == 2) { |
57fec1fe | 5280 | gen_op_movq_A0_reg(R_EBX); |
bbf662ee FB |
5281 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
5282 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5283 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
5fafdf24 | 5284 | } else |
14ce26e7 FB |
5285 | #endif |
5286 | { | |
57fec1fe | 5287 | gen_op_movl_A0_reg(R_EBX); |
bbf662ee FB |
5288 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
5289 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5290 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
14ce26e7 FB |
5291 | if (s->aflag == 0) |
5292 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
5293 | else |
5294 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
14ce26e7 | 5295 | } |
664e0f19 | 5296 | gen_add_A0_ds_seg(s); |
57fec1fe FB |
5297 | gen_op_ldu_T0_A0(OT_BYTE + s->mem_index); |
5298 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
5299 | break; |
5300 | case 0xb0 ... 0xb7: /* mov R, Ib */ | |
0af10c86 | 5301 | val = insn_get(env, s, OT_BYTE); |
2c0262af | 5302 | gen_op_movl_T0_im(val); |
57fec1fe | 5303 | gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s)); |
2c0262af FB |
5304 | break; |
5305 | case 0xb8 ... 0xbf: /* mov R, Iv */ | |
14ce26e7 FB |
5306 | #ifdef TARGET_X86_64 |
5307 | if (dflag == 2) { | |
5308 | uint64_t tmp; | |
5309 | /* 64 bit case */ | |
0af10c86 | 5310 | tmp = cpu_ldq_code(env, s->pc); |
14ce26e7 FB |
5311 | s->pc += 8; |
5312 | reg = (b & 7) | REX_B(s); | |
5313 | gen_movtl_T0_im(tmp); | |
57fec1fe | 5314 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 5315 | } else |
14ce26e7 FB |
5316 | #endif |
5317 | { | |
5318 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 5319 | val = insn_get(env, s, ot); |
14ce26e7 FB |
5320 | reg = (b & 7) | REX_B(s); |
5321 | gen_op_movl_T0_im(val); | |
57fec1fe | 5322 | gen_op_mov_reg_T0(ot, reg); |
14ce26e7 | 5323 | } |
2c0262af FB |
5324 | break; |
5325 | ||
5326 | case 0x91 ... 0x97: /* xchg R, EAX */ | |
7418027e | 5327 | do_xchg_reg_eax: |
14ce26e7 FB |
5328 | ot = dflag + OT_WORD; |
5329 | reg = (b & 7) | REX_B(s); | |
2c0262af FB |
5330 | rm = R_EAX; |
5331 | goto do_xchg_reg; | |
5332 | case 0x86: | |
5333 | case 0x87: /* xchg Ev, Gv */ | |
5334 | if ((b & 1) == 0) | |
5335 | ot = OT_BYTE; | |
5336 | else | |
14ce26e7 | 5337 | ot = dflag + OT_WORD; |
0af10c86 | 5338 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5339 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5340 | mod = (modrm >> 6) & 3; |
5341 | if (mod == 3) { | |
14ce26e7 | 5342 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 5343 | do_xchg_reg: |
57fec1fe FB |
5344 | gen_op_mov_TN_reg(ot, 0, reg); |
5345 | gen_op_mov_TN_reg(ot, 1, rm); | |
5346 | gen_op_mov_reg_T0(ot, rm); | |
5347 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af | 5348 | } else { |
0af10c86 | 5349 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 5350 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af FB |
5351 | /* for xchg, lock is implicit */ |
5352 | if (!(prefixes & PREFIX_LOCK)) | |
a7812ae4 | 5353 | gen_helper_lock(); |
57fec1fe FB |
5354 | gen_op_ld_T1_A0(ot + s->mem_index); |
5355 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 5356 | if (!(prefixes & PREFIX_LOCK)) |
a7812ae4 | 5357 | gen_helper_unlock(); |
57fec1fe | 5358 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5359 | } |
5360 | break; | |
5361 | case 0xc4: /* les Gv */ | |
14ce26e7 FB |
5362 | if (CODE64(s)) |
5363 | goto illegal_op; | |
2c0262af FB |
5364 | op = R_ES; |
5365 | goto do_lxx; | |
5366 | case 0xc5: /* lds Gv */ | |
14ce26e7 FB |
5367 | if (CODE64(s)) |
5368 | goto illegal_op; | |
2c0262af FB |
5369 | op = R_DS; |
5370 | goto do_lxx; | |
5371 | case 0x1b2: /* lss Gv */ | |
5372 | op = R_SS; | |
5373 | goto do_lxx; | |
5374 | case 0x1b4: /* lfs Gv */ | |
5375 | op = R_FS; | |
5376 | goto do_lxx; | |
5377 | case 0x1b5: /* lgs Gv */ | |
5378 | op = R_GS; | |
5379 | do_lxx: | |
5380 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 5381 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5382 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5383 | mod = (modrm >> 6) & 3; |
5384 | if (mod == 3) | |
5385 | goto illegal_op; | |
0af10c86 | 5386 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 5387 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 5388 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
2c0262af | 5389 | /* load the segment first to handle exceptions properly */ |
57fec1fe | 5390 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5391 | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
5392 | /* then put the data */ | |
57fec1fe | 5393 | gen_op_mov_reg_T1(ot, reg); |
2c0262af | 5394 | if (s->is_jmp) { |
14ce26e7 | 5395 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5396 | gen_eob(s); |
5397 | } | |
5398 | break; | |
3b46e624 | 5399 | |
2c0262af FB |
5400 | /************************/ |
5401 | /* shifts */ | |
5402 | case 0xc0: | |
5403 | case 0xc1: | |
5404 | /* shift Ev,Ib */ | |
5405 | shift = 2; | |
5406 | grp2: | |
5407 | { | |
5408 | if ((b & 1) == 0) | |
5409 | ot = OT_BYTE; | |
5410 | else | |
14ce26e7 | 5411 | ot = dflag + OT_WORD; |
3b46e624 | 5412 | |
0af10c86 | 5413 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5414 | mod = (modrm >> 6) & 3; |
2c0262af | 5415 | op = (modrm >> 3) & 7; |
3b46e624 | 5416 | |
2c0262af | 5417 | if (mod != 3) { |
14ce26e7 FB |
5418 | if (shift == 2) { |
5419 | s->rip_offset = 1; | |
5420 | } | |
0af10c86 | 5421 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
5422 | opreg = OR_TMP0; |
5423 | } else { | |
14ce26e7 | 5424 | opreg = (modrm & 7) | REX_B(s); |
2c0262af FB |
5425 | } |
5426 | ||
5427 | /* simpler op */ | |
5428 | if (shift == 0) { | |
5429 | gen_shift(s, op, ot, opreg, OR_ECX); | |
5430 | } else { | |
5431 | if (shift == 2) { | |
0af10c86 | 5432 | shift = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5433 | } |
5434 | gen_shifti(s, op, ot, opreg, shift); | |
5435 | } | |
5436 | } | |
5437 | break; | |
5438 | case 0xd0: | |
5439 | case 0xd1: | |
5440 | /* shift Ev,1 */ | |
5441 | shift = 1; | |
5442 | goto grp2; | |
5443 | case 0xd2: | |
5444 | case 0xd3: | |
5445 | /* shift Ev,cl */ | |
5446 | shift = 0; | |
5447 | goto grp2; | |
5448 | ||
5449 | case 0x1a4: /* shld imm */ | |
5450 | op = 0; | |
5451 | shift = 1; | |
5452 | goto do_shiftd; | |
5453 | case 0x1a5: /* shld cl */ | |
5454 | op = 0; | |
5455 | shift = 0; | |
5456 | goto do_shiftd; | |
5457 | case 0x1ac: /* shrd imm */ | |
5458 | op = 1; | |
5459 | shift = 1; | |
5460 | goto do_shiftd; | |
5461 | case 0x1ad: /* shrd cl */ | |
5462 | op = 1; | |
5463 | shift = 0; | |
5464 | do_shiftd: | |
14ce26e7 | 5465 | ot = dflag + OT_WORD; |
0af10c86 | 5466 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5467 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5468 | rm = (modrm & 7) | REX_B(s); |
5469 | reg = ((modrm >> 3) & 7) | rex_r; | |
2c0262af | 5470 | if (mod != 3) { |
0af10c86 | 5471 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
b6abf97d | 5472 | opreg = OR_TMP0; |
2c0262af | 5473 | } else { |
b6abf97d | 5474 | opreg = rm; |
2c0262af | 5475 | } |
57fec1fe | 5476 | gen_op_mov_TN_reg(ot, 1, reg); |
3b46e624 | 5477 | |
2c0262af | 5478 | if (shift) { |
0af10c86 | 5479 | val = cpu_ldub_code(env, s->pc++); |
b6abf97d | 5480 | tcg_gen_movi_tl(cpu_T3, val); |
2c0262af | 5481 | } else { |
cc739bb0 | 5482 | tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]); |
2c0262af | 5483 | } |
b6abf97d | 5484 | gen_shiftd_rm_T1_T3(s, ot, opreg, op); |
2c0262af FB |
5485 | break; |
5486 | ||
5487 | /************************/ | |
5488 | /* floats */ | |
5fafdf24 | 5489 | case 0xd8 ... 0xdf: |
7eee2a50 FB |
5490 | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { |
5491 | /* if CR0.EM or CR0.TS are set, generate an FPU exception */ | |
5492 | /* XXX: what to do if illegal op ? */ | |
5493 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
5494 | break; | |
5495 | } | |
0af10c86 | 5496 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5497 | mod = (modrm >> 6) & 3; |
5498 | rm = modrm & 7; | |
5499 | op = ((b & 7) << 3) | ((modrm >> 3) & 7); | |
2c0262af FB |
5500 | if (mod != 3) { |
5501 | /* memory op */ | |
0af10c86 | 5502 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
5503 | switch(op) { |
5504 | case 0x00 ... 0x07: /* fxxxs */ | |
5505 | case 0x10 ... 0x17: /* fixxxl */ | |
5506 | case 0x20 ... 0x27: /* fxxxl */ | |
5507 | case 0x30 ... 0x37: /* fixxx */ | |
5508 | { | |
5509 | int op1; | |
5510 | op1 = op & 7; | |
5511 | ||
5512 | switch(op >> 4) { | |
5513 | case 0: | |
ba7cd150 | 5514 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5515 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5516 | gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5517 | break; |
5518 | case 1: | |
ba7cd150 | 5519 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5520 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5521 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5522 | break; |
5523 | case 2: | |
b6abf97d | 5524 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5525 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5526 | gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5527 | break; |
5528 | case 3: | |
5529 | default: | |
ba7cd150 | 5530 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5531 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5532 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5533 | break; |
5534 | } | |
3b46e624 | 5535 | |
a7812ae4 | 5536 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5537 | if (op1 == 3) { |
5538 | /* fcomp needs pop */ | |
d3eb5eae | 5539 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5540 | } |
5541 | } | |
5542 | break; | |
5543 | case 0x08: /* flds */ | |
5544 | case 0x0a: /* fsts */ | |
5545 | case 0x0b: /* fstps */ | |
465e9838 FB |
5546 | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
5547 | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ | |
5548 | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ | |
2c0262af FB |
5549 | switch(op & 7) { |
5550 | case 0: | |
5551 | switch(op >> 4) { | |
5552 | case 0: | |
ba7cd150 | 5553 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5554 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5555 | gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5556 | break; |
5557 | case 1: | |
ba7cd150 | 5558 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5559 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5560 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5561 | break; |
5562 | case 2: | |
b6abf97d | 5563 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5564 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5565 | gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5566 | break; |
5567 | case 3: | |
5568 | default: | |
ba7cd150 | 5569 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5570 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5571 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5572 | break; |
5573 | } | |
5574 | break; | |
465e9838 | 5575 | case 1: |
19e6c4b8 | 5576 | /* XXX: the corresponding CPUID bit must be tested ! */ |
465e9838 FB |
5577 | switch(op >> 4) { |
5578 | case 1: | |
d3eb5eae | 5579 | gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5580 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5581 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
465e9838 FB |
5582 | break; |
5583 | case 2: | |
d3eb5eae | 5584 | gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5585 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5586 | (s->mem_index >> 2) - 1); |
465e9838 FB |
5587 | break; |
5588 | case 3: | |
5589 | default: | |
d3eb5eae | 5590 | gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5591 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5592 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
19e6c4b8 | 5593 | break; |
465e9838 | 5594 | } |
d3eb5eae | 5595 | gen_helper_fpop(cpu_env); |
465e9838 | 5596 | break; |
2c0262af FB |
5597 | default: |
5598 | switch(op >> 4) { | |
5599 | case 0: | |
d3eb5eae | 5600 | gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5601 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5602 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5603 | break; |
5604 | case 1: | |
d3eb5eae | 5605 | gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5606 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5607 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5608 | break; |
5609 | case 2: | |
d3eb5eae | 5610 | gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5611 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5612 | (s->mem_index >> 2) - 1); |
2c0262af FB |
5613 | break; |
5614 | case 3: | |
5615 | default: | |
d3eb5eae | 5616 | gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5617 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5618 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5619 | break; |
5620 | } | |
5621 | if ((op & 7) == 3) | |
d3eb5eae | 5622 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5623 | break; |
5624 | } | |
5625 | break; | |
5626 | case 0x0c: /* fldenv mem */ | |
773cdfcc | 5627 | gen_update_cc_op(s); |
19e6c4b8 | 5628 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5629 | gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5630 | break; |
5631 | case 0x0d: /* fldcw mem */ | |
19e6c4b8 | 5632 | gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5633 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5634 | gen_helper_fldcw(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5635 | break; |
5636 | case 0x0e: /* fnstenv mem */ | |
773cdfcc | 5637 | gen_update_cc_op(s); |
19e6c4b8 | 5638 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5639 | gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5640 | break; |
5641 | case 0x0f: /* fnstcw mem */ | |
d3eb5eae | 5642 | gen_helper_fnstcw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5643 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5644 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5645 | break; |
5646 | case 0x1d: /* fldt mem */ | |
773cdfcc | 5647 | gen_update_cc_op(s); |
19e6c4b8 | 5648 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5649 | gen_helper_fldt_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5650 | break; |
5651 | case 0x1f: /* fstpt mem */ | |
773cdfcc | 5652 | gen_update_cc_op(s); |
19e6c4b8 | 5653 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
5654 | gen_helper_fstt_ST0(cpu_env, cpu_A0); |
5655 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5656 | break; |
5657 | case 0x2c: /* frstor mem */ | |
773cdfcc | 5658 | gen_update_cc_op(s); |
19e6c4b8 | 5659 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5660 | gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5661 | break; |
5662 | case 0x2e: /* fnsave mem */ | |
773cdfcc | 5663 | gen_update_cc_op(s); |
19e6c4b8 | 5664 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5665 | gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5666 | break; |
5667 | case 0x2f: /* fnstsw mem */ | |
d3eb5eae | 5668 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5669 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5670 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5671 | break; |
5672 | case 0x3c: /* fbld */ | |
773cdfcc | 5673 | gen_update_cc_op(s); |
19e6c4b8 | 5674 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5675 | gen_helper_fbld_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5676 | break; |
5677 | case 0x3e: /* fbstp */ | |
773cdfcc | 5678 | gen_update_cc_op(s); |
19e6c4b8 | 5679 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
5680 | gen_helper_fbst_ST0(cpu_env, cpu_A0); |
5681 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5682 | break; |
5683 | case 0x3d: /* fildll */ | |
b6abf97d | 5684 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5685 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5686 | gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5687 | break; |
5688 | case 0x3f: /* fistpll */ | |
d3eb5eae | 5689 | gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5690 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5691 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5692 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5693 | break; |
5694 | default: | |
5695 | goto illegal_op; | |
5696 | } | |
5697 | } else { | |
5698 | /* register float ops */ | |
5699 | opreg = rm; | |
5700 | ||
5701 | switch(op) { | |
5702 | case 0x08: /* fld sti */ | |
d3eb5eae BS |
5703 | gen_helper_fpush(cpu_env); |
5704 | gen_helper_fmov_ST0_STN(cpu_env, | |
5705 | tcg_const_i32((opreg + 1) & 7)); | |
2c0262af FB |
5706 | break; |
5707 | case 0x09: /* fxchg sti */ | |
c169c906 FB |
5708 | case 0x29: /* fxchg4 sti, undocumented op */ |
5709 | case 0x39: /* fxchg7 sti, undocumented op */ | |
d3eb5eae | 5710 | gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
5711 | break; |
5712 | case 0x0a: /* grp d9/2 */ | |
5713 | switch(rm) { | |
5714 | case 0: /* fnop */ | |
023fe10d | 5715 | /* check exceptions (FreeBSD FPU probe) */ |
773cdfcc | 5716 | gen_update_cc_op(s); |
14ce26e7 | 5717 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5718 | gen_helper_fwait(cpu_env); |
2c0262af FB |
5719 | break; |
5720 | default: | |
5721 | goto illegal_op; | |
5722 | } | |
5723 | break; | |
5724 | case 0x0c: /* grp d9/4 */ | |
5725 | switch(rm) { | |
5726 | case 0: /* fchs */ | |
d3eb5eae | 5727 | gen_helper_fchs_ST0(cpu_env); |
2c0262af FB |
5728 | break; |
5729 | case 1: /* fabs */ | |
d3eb5eae | 5730 | gen_helper_fabs_ST0(cpu_env); |
2c0262af FB |
5731 | break; |
5732 | case 4: /* ftst */ | |
d3eb5eae BS |
5733 | gen_helper_fldz_FT0(cpu_env); |
5734 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
5735 | break; |
5736 | case 5: /* fxam */ | |
d3eb5eae | 5737 | gen_helper_fxam_ST0(cpu_env); |
2c0262af FB |
5738 | break; |
5739 | default: | |
5740 | goto illegal_op; | |
5741 | } | |
5742 | break; | |
5743 | case 0x0d: /* grp d9/5 */ | |
5744 | { | |
5745 | switch(rm) { | |
5746 | case 0: | |
d3eb5eae BS |
5747 | gen_helper_fpush(cpu_env); |
5748 | gen_helper_fld1_ST0(cpu_env); | |
2c0262af FB |
5749 | break; |
5750 | case 1: | |
d3eb5eae BS |
5751 | gen_helper_fpush(cpu_env); |
5752 | gen_helper_fldl2t_ST0(cpu_env); | |
2c0262af FB |
5753 | break; |
5754 | case 2: | |
d3eb5eae BS |
5755 | gen_helper_fpush(cpu_env); |
5756 | gen_helper_fldl2e_ST0(cpu_env); | |
2c0262af FB |
5757 | break; |
5758 | case 3: | |
d3eb5eae BS |
5759 | gen_helper_fpush(cpu_env); |
5760 | gen_helper_fldpi_ST0(cpu_env); | |
2c0262af FB |
5761 | break; |
5762 | case 4: | |
d3eb5eae BS |
5763 | gen_helper_fpush(cpu_env); |
5764 | gen_helper_fldlg2_ST0(cpu_env); | |
2c0262af FB |
5765 | break; |
5766 | case 5: | |
d3eb5eae BS |
5767 | gen_helper_fpush(cpu_env); |
5768 | gen_helper_fldln2_ST0(cpu_env); | |
2c0262af FB |
5769 | break; |
5770 | case 6: | |
d3eb5eae BS |
5771 | gen_helper_fpush(cpu_env); |
5772 | gen_helper_fldz_ST0(cpu_env); | |
2c0262af FB |
5773 | break; |
5774 | default: | |
5775 | goto illegal_op; | |
5776 | } | |
5777 | } | |
5778 | break; | |
5779 | case 0x0e: /* grp d9/6 */ | |
5780 | switch(rm) { | |
5781 | case 0: /* f2xm1 */ | |
d3eb5eae | 5782 | gen_helper_f2xm1(cpu_env); |
2c0262af FB |
5783 | break; |
5784 | case 1: /* fyl2x */ | |
d3eb5eae | 5785 | gen_helper_fyl2x(cpu_env); |
2c0262af FB |
5786 | break; |
5787 | case 2: /* fptan */ | |
d3eb5eae | 5788 | gen_helper_fptan(cpu_env); |
2c0262af FB |
5789 | break; |
5790 | case 3: /* fpatan */ | |
d3eb5eae | 5791 | gen_helper_fpatan(cpu_env); |
2c0262af FB |
5792 | break; |
5793 | case 4: /* fxtract */ | |
d3eb5eae | 5794 | gen_helper_fxtract(cpu_env); |
2c0262af FB |
5795 | break; |
5796 | case 5: /* fprem1 */ | |
d3eb5eae | 5797 | gen_helper_fprem1(cpu_env); |
2c0262af FB |
5798 | break; |
5799 | case 6: /* fdecstp */ | |
d3eb5eae | 5800 | gen_helper_fdecstp(cpu_env); |
2c0262af FB |
5801 | break; |
5802 | default: | |
5803 | case 7: /* fincstp */ | |
d3eb5eae | 5804 | gen_helper_fincstp(cpu_env); |
2c0262af FB |
5805 | break; |
5806 | } | |
5807 | break; | |
5808 | case 0x0f: /* grp d9/7 */ | |
5809 | switch(rm) { | |
5810 | case 0: /* fprem */ | |
d3eb5eae | 5811 | gen_helper_fprem(cpu_env); |
2c0262af FB |
5812 | break; |
5813 | case 1: /* fyl2xp1 */ | |
d3eb5eae | 5814 | gen_helper_fyl2xp1(cpu_env); |
2c0262af FB |
5815 | break; |
5816 | case 2: /* fsqrt */ | |
d3eb5eae | 5817 | gen_helper_fsqrt(cpu_env); |
2c0262af FB |
5818 | break; |
5819 | case 3: /* fsincos */ | |
d3eb5eae | 5820 | gen_helper_fsincos(cpu_env); |
2c0262af FB |
5821 | break; |
5822 | case 5: /* fscale */ | |
d3eb5eae | 5823 | gen_helper_fscale(cpu_env); |
2c0262af FB |
5824 | break; |
5825 | case 4: /* frndint */ | |
d3eb5eae | 5826 | gen_helper_frndint(cpu_env); |
2c0262af FB |
5827 | break; |
5828 | case 6: /* fsin */ | |
d3eb5eae | 5829 | gen_helper_fsin(cpu_env); |
2c0262af FB |
5830 | break; |
5831 | default: | |
5832 | case 7: /* fcos */ | |
d3eb5eae | 5833 | gen_helper_fcos(cpu_env); |
2c0262af FB |
5834 | break; |
5835 | } | |
5836 | break; | |
5837 | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ | |
5838 | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ | |
5839 | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ | |
5840 | { | |
5841 | int op1; | |
3b46e624 | 5842 | |
2c0262af FB |
5843 | op1 = op & 7; |
5844 | if (op >= 0x20) { | |
a7812ae4 | 5845 | gen_helper_fp_arith_STN_ST0(op1, opreg); |
2c0262af | 5846 | if (op >= 0x30) |
d3eb5eae | 5847 | gen_helper_fpop(cpu_env); |
2c0262af | 5848 | } else { |
d3eb5eae | 5849 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
a7812ae4 | 5850 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5851 | } |
5852 | } | |
5853 | break; | |
5854 | case 0x02: /* fcom */ | |
c169c906 | 5855 | case 0x22: /* fcom2, undocumented op */ |
d3eb5eae BS |
5856 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5857 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
5858 | break; |
5859 | case 0x03: /* fcomp */ | |
c169c906 FB |
5860 | case 0x23: /* fcomp3, undocumented op */ |
5861 | case 0x32: /* fcomp5, undocumented op */ | |
d3eb5eae BS |
5862 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5863 | gen_helper_fcom_ST0_FT0(cpu_env); | |
5864 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5865 | break; |
5866 | case 0x15: /* da/5 */ | |
5867 | switch(rm) { | |
5868 | case 1: /* fucompp */ | |
d3eb5eae BS |
5869 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
5870 | gen_helper_fucom_ST0_FT0(cpu_env); | |
5871 | gen_helper_fpop(cpu_env); | |
5872 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5873 | break; |
5874 | default: | |
5875 | goto illegal_op; | |
5876 | } | |
5877 | break; | |
5878 | case 0x1c: | |
5879 | switch(rm) { | |
5880 | case 0: /* feni (287 only, just do nop here) */ | |
5881 | break; | |
5882 | case 1: /* fdisi (287 only, just do nop here) */ | |
5883 | break; | |
5884 | case 2: /* fclex */ | |
d3eb5eae | 5885 | gen_helper_fclex(cpu_env); |
2c0262af FB |
5886 | break; |
5887 | case 3: /* fninit */ | |
d3eb5eae | 5888 | gen_helper_fninit(cpu_env); |
2c0262af FB |
5889 | break; |
5890 | case 4: /* fsetpm (287 only, just do nop here) */ | |
5891 | break; | |
5892 | default: | |
5893 | goto illegal_op; | |
5894 | } | |
5895 | break; | |
5896 | case 0x1d: /* fucomi */ | |
773cdfcc | 5897 | gen_update_cc_op(s); |
d3eb5eae BS |
5898 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5899 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
3ca51d07 | 5900 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
5901 | break; |
5902 | case 0x1e: /* fcomi */ | |
773cdfcc | 5903 | gen_update_cc_op(s); |
d3eb5eae BS |
5904 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5905 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
3ca51d07 | 5906 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 5907 | break; |
658c8bda | 5908 | case 0x28: /* ffree sti */ |
d3eb5eae | 5909 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
5fafdf24 | 5910 | break; |
2c0262af | 5911 | case 0x2a: /* fst sti */ |
d3eb5eae | 5912 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
5913 | break; |
5914 | case 0x2b: /* fstp sti */ | |
c169c906 FB |
5915 | case 0x0b: /* fstp1 sti, undocumented op */ |
5916 | case 0x3a: /* fstp8 sti, undocumented op */ | |
5917 | case 0x3b: /* fstp9 sti, undocumented op */ | |
d3eb5eae BS |
5918 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
5919 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5920 | break; |
5921 | case 0x2c: /* fucom st(i) */ | |
d3eb5eae BS |
5922 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5923 | gen_helper_fucom_ST0_FT0(cpu_env); | |
2c0262af FB |
5924 | break; |
5925 | case 0x2d: /* fucomp st(i) */ | |
d3eb5eae BS |
5926 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5927 | gen_helper_fucom_ST0_FT0(cpu_env); | |
5928 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5929 | break; |
5930 | case 0x33: /* de/3 */ | |
5931 | switch(rm) { | |
5932 | case 1: /* fcompp */ | |
d3eb5eae BS |
5933 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
5934 | gen_helper_fcom_ST0_FT0(cpu_env); | |
5935 | gen_helper_fpop(cpu_env); | |
5936 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5937 | break; |
5938 | default: | |
5939 | goto illegal_op; | |
5940 | } | |
5941 | break; | |
c169c906 | 5942 | case 0x38: /* ffreep sti, undocumented op */ |
d3eb5eae BS |
5943 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
5944 | gen_helper_fpop(cpu_env); | |
c169c906 | 5945 | break; |
2c0262af FB |
5946 | case 0x3c: /* df/4 */ |
5947 | switch(rm) { | |
5948 | case 0: | |
d3eb5eae | 5949 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5950 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5951 | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
2c0262af FB |
5952 | break; |
5953 | default: | |
5954 | goto illegal_op; | |
5955 | } | |
5956 | break; | |
5957 | case 0x3d: /* fucomip */ | |
773cdfcc | 5958 | gen_update_cc_op(s); |
d3eb5eae BS |
5959 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5960 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
5961 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 5962 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
5963 | break; |
5964 | case 0x3e: /* fcomip */ | |
773cdfcc | 5965 | gen_update_cc_op(s); |
d3eb5eae BS |
5966 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5967 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
5968 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 5969 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 5970 | break; |
a2cc3b24 FB |
5971 | case 0x10 ... 0x13: /* fcmovxx */ |
5972 | case 0x18 ... 0x1b: | |
5973 | { | |
19e6c4b8 | 5974 | int op1, l1; |
d70040bc | 5975 | static const uint8_t fcmov_cc[8] = { |
a2cc3b24 FB |
5976 | (JCC_B << 1), |
5977 | (JCC_Z << 1), | |
5978 | (JCC_BE << 1), | |
5979 | (JCC_P << 1), | |
5980 | }; | |
1e4840bf | 5981 | op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); |
19e6c4b8 | 5982 | l1 = gen_new_label(); |
b27fc131 | 5983 | gen_jcc1(s, op1, l1); |
d3eb5eae | 5984 | gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
19e6c4b8 | 5985 | gen_set_label(l1); |
a2cc3b24 FB |
5986 | } |
5987 | break; | |
2c0262af FB |
5988 | default: |
5989 | goto illegal_op; | |
5990 | } | |
5991 | } | |
5992 | break; | |
5993 | /************************/ | |
5994 | /* string ops */ | |
5995 | ||
5996 | case 0xa4: /* movsS */ | |
5997 | case 0xa5: | |
5998 | if ((b & 1) == 0) | |
5999 | ot = OT_BYTE; | |
6000 | else | |
14ce26e7 | 6001 | ot = dflag + OT_WORD; |
2c0262af FB |
6002 | |
6003 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6004 | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6005 | } else { | |
6006 | gen_movs(s, ot); | |
6007 | } | |
6008 | break; | |
3b46e624 | 6009 | |
2c0262af FB |
6010 | case 0xaa: /* stosS */ |
6011 | case 0xab: | |
6012 | if ((b & 1) == 0) | |
6013 | ot = OT_BYTE; | |
6014 | else | |
14ce26e7 | 6015 | ot = dflag + OT_WORD; |
2c0262af FB |
6016 | |
6017 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6018 | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6019 | } else { | |
6020 | gen_stos(s, ot); | |
6021 | } | |
6022 | break; | |
6023 | case 0xac: /* lodsS */ | |
6024 | case 0xad: | |
6025 | if ((b & 1) == 0) | |
6026 | ot = OT_BYTE; | |
6027 | else | |
14ce26e7 | 6028 | ot = dflag + OT_WORD; |
2c0262af FB |
6029 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6030 | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6031 | } else { | |
6032 | gen_lods(s, ot); | |
6033 | } | |
6034 | break; | |
6035 | case 0xae: /* scasS */ | |
6036 | case 0xaf: | |
6037 | if ((b & 1) == 0) | |
6038 | ot = OT_BYTE; | |
6039 | else | |
14ce26e7 | 6040 | ot = dflag + OT_WORD; |
2c0262af FB |
6041 | if (prefixes & PREFIX_REPNZ) { |
6042 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6043 | } else if (prefixes & PREFIX_REPZ) { | |
6044 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6045 | } else { | |
6046 | gen_scas(s, ot); | |
2c0262af FB |
6047 | } |
6048 | break; | |
6049 | ||
6050 | case 0xa6: /* cmpsS */ | |
6051 | case 0xa7: | |
6052 | if ((b & 1) == 0) | |
6053 | ot = OT_BYTE; | |
6054 | else | |
14ce26e7 | 6055 | ot = dflag + OT_WORD; |
2c0262af FB |
6056 | if (prefixes & PREFIX_REPNZ) { |
6057 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6058 | } else if (prefixes & PREFIX_REPZ) { | |
6059 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6060 | } else { | |
6061 | gen_cmps(s, ot); | |
2c0262af FB |
6062 | } |
6063 | break; | |
6064 | case 0x6c: /* insS */ | |
6065 | case 0x6d: | |
f115e911 FB |
6066 | if ((b & 1) == 0) |
6067 | ot = OT_BYTE; | |
6068 | else | |
6069 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6070 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6071 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6072 | gen_check_io(s, ot, pc_start - s->cs_base, |
6073 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6074 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6075 | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6076 | } else { |
f115e911 | 6077 | gen_ins(s, ot); |
2e70f6ef PB |
6078 | if (use_icount) { |
6079 | gen_jmp(s, s->pc - s->cs_base); | |
6080 | } | |
2c0262af FB |
6081 | } |
6082 | break; | |
6083 | case 0x6e: /* outsS */ | |
6084 | case 0x6f: | |
f115e911 FB |
6085 | if ((b & 1) == 0) |
6086 | ot = OT_BYTE; | |
6087 | else | |
6088 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6089 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6090 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6091 | gen_check_io(s, ot, pc_start - s->cs_base, |
6092 | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6093 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6094 | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6095 | } else { |
f115e911 | 6096 | gen_outs(s, ot); |
2e70f6ef PB |
6097 | if (use_icount) { |
6098 | gen_jmp(s, s->pc - s->cs_base); | |
6099 | } | |
2c0262af FB |
6100 | } |
6101 | break; | |
6102 | ||
6103 | /************************/ | |
6104 | /* port I/O */ | |
0573fbfc | 6105 | |
2c0262af FB |
6106 | case 0xe4: |
6107 | case 0xe5: | |
f115e911 FB |
6108 | if ((b & 1) == 0) |
6109 | ot = OT_BYTE; | |
6110 | else | |
6111 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 6112 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6113 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6114 | gen_check_io(s, ot, pc_start - s->cs_base, |
6115 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6116 | if (use_icount) |
6117 | gen_io_start(); | |
b6abf97d | 6118 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6119 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6120 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6121 | if (use_icount) { |
6122 | gen_io_end(); | |
6123 | gen_jmp(s, s->pc - s->cs_base); | |
6124 | } | |
2c0262af FB |
6125 | break; |
6126 | case 0xe6: | |
6127 | case 0xe7: | |
f115e911 FB |
6128 | if ((b & 1) == 0) |
6129 | ot = OT_BYTE; | |
6130 | else | |
6131 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 6132 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6133 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6134 | gen_check_io(s, ot, pc_start - s->cs_base, |
6135 | svm_is_rep(prefixes)); | |
57fec1fe | 6136 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6137 | |
2e70f6ef PB |
6138 | if (use_icount) |
6139 | gen_io_start(); | |
b6abf97d | 6140 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6141 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6142 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6143 | if (use_icount) { |
6144 | gen_io_end(); | |
6145 | gen_jmp(s, s->pc - s->cs_base); | |
6146 | } | |
2c0262af FB |
6147 | break; |
6148 | case 0xec: | |
6149 | case 0xed: | |
f115e911 FB |
6150 | if ((b & 1) == 0) |
6151 | ot = OT_BYTE; | |
6152 | else | |
6153 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6154 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6155 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6156 | gen_check_io(s, ot, pc_start - s->cs_base, |
6157 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6158 | if (use_icount) |
6159 | gen_io_start(); | |
b6abf97d | 6160 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6161 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6162 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6163 | if (use_icount) { |
6164 | gen_io_end(); | |
6165 | gen_jmp(s, s->pc - s->cs_base); | |
6166 | } | |
2c0262af FB |
6167 | break; |
6168 | case 0xee: | |
6169 | case 0xef: | |
f115e911 FB |
6170 | if ((b & 1) == 0) |
6171 | ot = OT_BYTE; | |
6172 | else | |
6173 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6174 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6175 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6176 | gen_check_io(s, ot, pc_start - s->cs_base, |
6177 | svm_is_rep(prefixes)); | |
57fec1fe | 6178 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6179 | |
2e70f6ef PB |
6180 | if (use_icount) |
6181 | gen_io_start(); | |
b6abf97d | 6182 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6183 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6184 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6185 | if (use_icount) { |
6186 | gen_io_end(); | |
6187 | gen_jmp(s, s->pc - s->cs_base); | |
6188 | } | |
2c0262af FB |
6189 | break; |
6190 | ||
6191 | /************************/ | |
6192 | /* control */ | |
6193 | case 0xc2: /* ret im */ | |
0af10c86 | 6194 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6195 | s->pc += 2; |
6196 | gen_pop_T0(s); | |
8f091a59 FB |
6197 | if (CODE64(s) && s->dflag) |
6198 | s->dflag = 2; | |
2c0262af FB |
6199 | gen_stack_update(s, val + (2 << s->dflag)); |
6200 | if (s->dflag == 0) | |
6201 | gen_op_andl_T0_ffff(); | |
6202 | gen_op_jmp_T0(); | |
6203 | gen_eob(s); | |
6204 | break; | |
6205 | case 0xc3: /* ret */ | |
6206 | gen_pop_T0(s); | |
6207 | gen_pop_update(s); | |
6208 | if (s->dflag == 0) | |
6209 | gen_op_andl_T0_ffff(); | |
6210 | gen_op_jmp_T0(); | |
6211 | gen_eob(s); | |
6212 | break; | |
6213 | case 0xca: /* lret im */ | |
0af10c86 | 6214 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6215 | s->pc += 2; |
6216 | do_lret: | |
6217 | if (s->pe && !s->vm86) { | |
773cdfcc | 6218 | gen_update_cc_op(s); |
14ce26e7 | 6219 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6220 | gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6221 | tcg_const_i32(val)); |
2c0262af FB |
6222 | } else { |
6223 | gen_stack_A0(s); | |
6224 | /* pop offset */ | |
57fec1fe | 6225 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
2c0262af FB |
6226 | if (s->dflag == 0) |
6227 | gen_op_andl_T0_ffff(); | |
6228 | /* NOTE: keeping EIP updated is not a problem in case of | |
6229 | exception */ | |
6230 | gen_op_jmp_T0(); | |
6231 | /* pop selector */ | |
6232 | gen_op_addl_A0_im(2 << s->dflag); | |
57fec1fe | 6233 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
3bd7da9e | 6234 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
6235 | /* add stack offset */ |
6236 | gen_stack_update(s, val + (4 << s->dflag)); | |
6237 | } | |
6238 | gen_eob(s); | |
6239 | break; | |
6240 | case 0xcb: /* lret */ | |
6241 | val = 0; | |
6242 | goto do_lret; | |
6243 | case 0xcf: /* iret */ | |
872929aa | 6244 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); |
2c0262af FB |
6245 | if (!s->pe) { |
6246 | /* real mode */ | |
2999a0b2 | 6247 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
3ca51d07 | 6248 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 FB |
6249 | } else if (s->vm86) { |
6250 | if (s->iopl != 3) { | |
6251 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6252 | } else { | |
2999a0b2 | 6253 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
3ca51d07 | 6254 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 6255 | } |
2c0262af | 6256 | } else { |
773cdfcc | 6257 | gen_update_cc_op(s); |
14ce26e7 | 6258 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6259 | gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6260 | tcg_const_i32(s->pc - s->cs_base)); |
3ca51d07 | 6261 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6262 | } |
6263 | gen_eob(s); | |
6264 | break; | |
6265 | case 0xe8: /* call im */ | |
6266 | { | |
14ce26e7 | 6267 | if (dflag) |
0af10c86 | 6268 | tval = (int32_t)insn_get(env, s, OT_LONG); |
14ce26e7 | 6269 | else |
0af10c86 | 6270 | tval = (int16_t)insn_get(env, s, OT_WORD); |
2c0262af | 6271 | next_eip = s->pc - s->cs_base; |
14ce26e7 | 6272 | tval += next_eip; |
2c0262af | 6273 | if (s->dflag == 0) |
14ce26e7 | 6274 | tval &= 0xffff; |
99596385 AJ |
6275 | else if(!CODE64(s)) |
6276 | tval &= 0xffffffff; | |
14ce26e7 | 6277 | gen_movtl_T0_im(next_eip); |
2c0262af | 6278 | gen_push_T0(s); |
14ce26e7 | 6279 | gen_jmp(s, tval); |
2c0262af FB |
6280 | } |
6281 | break; | |
6282 | case 0x9a: /* lcall im */ | |
6283 | { | |
6284 | unsigned int selector, offset; | |
3b46e624 | 6285 | |
14ce26e7 FB |
6286 | if (CODE64(s)) |
6287 | goto illegal_op; | |
2c0262af | 6288 | ot = dflag ? OT_LONG : OT_WORD; |
0af10c86 BS |
6289 | offset = insn_get(env, s, ot); |
6290 | selector = insn_get(env, s, OT_WORD); | |
3b46e624 | 6291 | |
2c0262af | 6292 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6293 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6294 | } |
6295 | goto do_lcall; | |
ecada8a2 | 6296 | case 0xe9: /* jmp im */ |
14ce26e7 | 6297 | if (dflag) |
0af10c86 | 6298 | tval = (int32_t)insn_get(env, s, OT_LONG); |
14ce26e7 | 6299 | else |
0af10c86 | 6300 | tval = (int16_t)insn_get(env, s, OT_WORD); |
14ce26e7 | 6301 | tval += s->pc - s->cs_base; |
2c0262af | 6302 | if (s->dflag == 0) |
14ce26e7 | 6303 | tval &= 0xffff; |
32938e12 AJ |
6304 | else if(!CODE64(s)) |
6305 | tval &= 0xffffffff; | |
14ce26e7 | 6306 | gen_jmp(s, tval); |
2c0262af FB |
6307 | break; |
6308 | case 0xea: /* ljmp im */ | |
6309 | { | |
6310 | unsigned int selector, offset; | |
6311 | ||
14ce26e7 FB |
6312 | if (CODE64(s)) |
6313 | goto illegal_op; | |
2c0262af | 6314 | ot = dflag ? OT_LONG : OT_WORD; |
0af10c86 BS |
6315 | offset = insn_get(env, s, ot); |
6316 | selector = insn_get(env, s, OT_WORD); | |
3b46e624 | 6317 | |
2c0262af | 6318 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6319 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6320 | } |
6321 | goto do_ljmp; | |
6322 | case 0xeb: /* jmp Jb */ | |
0af10c86 | 6323 | tval = (int8_t)insn_get(env, s, OT_BYTE); |
14ce26e7 | 6324 | tval += s->pc - s->cs_base; |
2c0262af | 6325 | if (s->dflag == 0) |
14ce26e7 FB |
6326 | tval &= 0xffff; |
6327 | gen_jmp(s, tval); | |
2c0262af FB |
6328 | break; |
6329 | case 0x70 ... 0x7f: /* jcc Jb */ | |
0af10c86 | 6330 | tval = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
6331 | goto do_jcc; |
6332 | case 0x180 ... 0x18f: /* jcc Jv */ | |
6333 | if (dflag) { | |
0af10c86 | 6334 | tval = (int32_t)insn_get(env, s, OT_LONG); |
2c0262af | 6335 | } else { |
0af10c86 | 6336 | tval = (int16_t)insn_get(env, s, OT_WORD); |
2c0262af FB |
6337 | } |
6338 | do_jcc: | |
6339 | next_eip = s->pc - s->cs_base; | |
14ce26e7 | 6340 | tval += next_eip; |
2c0262af | 6341 | if (s->dflag == 0) |
14ce26e7 FB |
6342 | tval &= 0xffff; |
6343 | gen_jcc(s, b, tval, next_eip); | |
2c0262af FB |
6344 | break; |
6345 | ||
6346 | case 0x190 ... 0x19f: /* setcc Gv */ | |
0af10c86 | 6347 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 6348 | gen_setcc(s, b); |
0af10c86 | 6349 | gen_ldst_modrm(env, s, modrm, OT_BYTE, OR_TMP0, 1); |
2c0262af FB |
6350 | break; |
6351 | case 0x140 ... 0x14f: /* cmov Gv, Ev */ | |
8e1c85e3 FB |
6352 | { |
6353 | int l1; | |
1e4840bf FB |
6354 | TCGv t0; |
6355 | ||
8e1c85e3 | 6356 | ot = dflag + OT_WORD; |
0af10c86 | 6357 | modrm = cpu_ldub_code(env, s->pc++); |
8e1c85e3 FB |
6358 | reg = ((modrm >> 3) & 7) | rex_r; |
6359 | mod = (modrm >> 6) & 3; | |
a7812ae4 | 6360 | t0 = tcg_temp_local_new(); |
8e1c85e3 | 6361 | if (mod != 3) { |
0af10c86 | 6362 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
1e4840bf | 6363 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
8e1c85e3 FB |
6364 | } else { |
6365 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 6366 | gen_op_mov_v_reg(ot, t0, rm); |
8e1c85e3 | 6367 | } |
8e1c85e3 FB |
6368 | #ifdef TARGET_X86_64 |
6369 | if (ot == OT_LONG) { | |
6370 | /* XXX: specific Intel behaviour ? */ | |
6371 | l1 = gen_new_label(); | |
b27fc131 | 6372 | gen_jcc1(s, b ^ 1, l1); |
cc739bb0 | 6373 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
8e1c85e3 | 6374 | gen_set_label(l1); |
cc739bb0 | 6375 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]); |
8e1c85e3 FB |
6376 | } else |
6377 | #endif | |
6378 | { | |
6379 | l1 = gen_new_label(); | |
b27fc131 | 6380 | gen_jcc1(s, b ^ 1, l1); |
1e4840bf | 6381 | gen_op_mov_reg_v(ot, reg, t0); |
8e1c85e3 FB |
6382 | gen_set_label(l1); |
6383 | } | |
1e4840bf | 6384 | tcg_temp_free(t0); |
2c0262af | 6385 | } |
2c0262af | 6386 | break; |
3b46e624 | 6387 | |
2c0262af FB |
6388 | /************************/ |
6389 | /* flags */ | |
6390 | case 0x9c: /* pushf */ | |
872929aa | 6391 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); |
2c0262af FB |
6392 | if (s->vm86 && s->iopl != 3) { |
6393 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6394 | } else { | |
773cdfcc | 6395 | gen_update_cc_op(s); |
f0967a1a | 6396 | gen_helper_read_eflags(cpu_T[0], cpu_env); |
2c0262af FB |
6397 | gen_push_T0(s); |
6398 | } | |
6399 | break; | |
6400 | case 0x9d: /* popf */ | |
872929aa | 6401 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); |
2c0262af FB |
6402 | if (s->vm86 && s->iopl != 3) { |
6403 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6404 | } else { | |
6405 | gen_pop_T0(s); | |
6406 | if (s->cpl == 0) { | |
6407 | if (s->dflag) { | |
f0967a1a BS |
6408 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6409 | tcg_const_i32((TF_MASK | AC_MASK | | |
6410 | ID_MASK | NT_MASK | | |
6411 | IF_MASK | | |
6412 | IOPL_MASK))); | |
2c0262af | 6413 | } else { |
f0967a1a BS |
6414 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6415 | tcg_const_i32((TF_MASK | AC_MASK | | |
6416 | ID_MASK | NT_MASK | | |
6417 | IF_MASK | IOPL_MASK) | |
6418 | & 0xffff)); | |
2c0262af FB |
6419 | } |
6420 | } else { | |
4136f33c FB |
6421 | if (s->cpl <= s->iopl) { |
6422 | if (s->dflag) { | |
f0967a1a BS |
6423 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6424 | tcg_const_i32((TF_MASK | | |
6425 | AC_MASK | | |
6426 | ID_MASK | | |
6427 | NT_MASK | | |
6428 | IF_MASK))); | |
4136f33c | 6429 | } else { |
f0967a1a BS |
6430 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6431 | tcg_const_i32((TF_MASK | | |
6432 | AC_MASK | | |
6433 | ID_MASK | | |
6434 | NT_MASK | | |
6435 | IF_MASK) | |
6436 | & 0xffff)); | |
4136f33c | 6437 | } |
2c0262af | 6438 | } else { |
4136f33c | 6439 | if (s->dflag) { |
f0967a1a BS |
6440 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6441 | tcg_const_i32((TF_MASK | AC_MASK | | |
6442 | ID_MASK | NT_MASK))); | |
4136f33c | 6443 | } else { |
f0967a1a BS |
6444 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6445 | tcg_const_i32((TF_MASK | AC_MASK | | |
6446 | ID_MASK | NT_MASK) | |
6447 | & 0xffff)); | |
4136f33c | 6448 | } |
2c0262af FB |
6449 | } |
6450 | } | |
6451 | gen_pop_update(s); | |
3ca51d07 | 6452 | set_cc_op(s, CC_OP_EFLAGS); |
a9321a4d | 6453 | /* abort translation because TF/AC flag may change */ |
14ce26e7 | 6454 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6455 | gen_eob(s); |
6456 | } | |
6457 | break; | |
6458 | case 0x9e: /* sahf */ | |
12e26b75 | 6459 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6460 | goto illegal_op; |
57fec1fe | 6461 | gen_op_mov_TN_reg(OT_BYTE, 0, R_AH); |
c7b3c873 | 6462 | gen_compute_eflags(s, cpu_cc_src); |
bd7a7b33 FB |
6463 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); |
6464 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); | |
6465 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); | |
2c0262af FB |
6466 | break; |
6467 | case 0x9f: /* lahf */ | |
12e26b75 | 6468 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6469 | goto illegal_op; |
c7b3c873 | 6470 | gen_compute_eflags(s, cpu_T[0]); |
bd7a7b33 FB |
6471 | /* Note: gen_compute_eflags() only gives the condition codes */ |
6472 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02); | |
57fec1fe | 6473 | gen_op_mov_reg_T0(OT_BYTE, R_AH); |
2c0262af FB |
6474 | break; |
6475 | case 0xf5: /* cmc */ | |
c7b3c873 | 6476 | gen_compute_eflags(s, cpu_cc_src); |
bd7a7b33 | 6477 | tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6478 | break; |
6479 | case 0xf8: /* clc */ | |
c7b3c873 | 6480 | gen_compute_eflags(s, cpu_cc_src); |
bd7a7b33 | 6481 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); |
2c0262af FB |
6482 | break; |
6483 | case 0xf9: /* stc */ | |
c7b3c873 | 6484 | gen_compute_eflags(s, cpu_cc_src); |
bd7a7b33 | 6485 | tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6486 | break; |
6487 | case 0xfc: /* cld */ | |
b6abf97d | 6488 | tcg_gen_movi_i32(cpu_tmp2_i32, 1); |
317ac620 | 6489 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6490 | break; |
6491 | case 0xfd: /* std */ | |
b6abf97d | 6492 | tcg_gen_movi_i32(cpu_tmp2_i32, -1); |
317ac620 | 6493 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6494 | break; |
6495 | ||
6496 | /************************/ | |
6497 | /* bit operations */ | |
6498 | case 0x1ba: /* bt/bts/btr/btc Gv, im */ | |
14ce26e7 | 6499 | ot = dflag + OT_WORD; |
0af10c86 | 6500 | modrm = cpu_ldub_code(env, s->pc++); |
33698e5f | 6501 | op = (modrm >> 3) & 7; |
2c0262af | 6502 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6503 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 6504 | if (mod != 3) { |
14ce26e7 | 6505 | s->rip_offset = 1; |
0af10c86 | 6506 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 6507 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6508 | } else { |
57fec1fe | 6509 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
6510 | } |
6511 | /* load shift */ | |
0af10c86 | 6512 | val = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
6513 | gen_op_movl_T1_im(val); |
6514 | if (op < 4) | |
6515 | goto illegal_op; | |
6516 | op -= 4; | |
f484d386 | 6517 | goto bt_op; |
2c0262af FB |
6518 | case 0x1a3: /* bt Gv, Ev */ |
6519 | op = 0; | |
6520 | goto do_btx; | |
6521 | case 0x1ab: /* bts */ | |
6522 | op = 1; | |
6523 | goto do_btx; | |
6524 | case 0x1b3: /* btr */ | |
6525 | op = 2; | |
6526 | goto do_btx; | |
6527 | case 0x1bb: /* btc */ | |
6528 | op = 3; | |
6529 | do_btx: | |
14ce26e7 | 6530 | ot = dflag + OT_WORD; |
0af10c86 | 6531 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 6532 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 6533 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6534 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 6535 | gen_op_mov_TN_reg(OT_LONG, 1, reg); |
2c0262af | 6536 | if (mod != 3) { |
0af10c86 | 6537 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 6538 | /* specific case: we need to add a displacement */ |
f484d386 FB |
6539 | gen_exts(ot, cpu_T[1]); |
6540 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); | |
6541 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); | |
6542 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe | 6543 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6544 | } else { |
57fec1fe | 6545 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 6546 | } |
f484d386 FB |
6547 | bt_op: |
6548 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); | |
6549 | switch(op) { | |
6550 | case 0: | |
6551 | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); | |
6552 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6553 | break; | |
6554 | case 1: | |
6555 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6556 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6557 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6558 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6559 | break; | |
6560 | case 2: | |
6561 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6562 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6563 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6564 | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); | |
6565 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6566 | break; | |
6567 | default: | |
6568 | case 3: | |
6569 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6570 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6571 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6572 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6573 | break; | |
6574 | } | |
3ca51d07 | 6575 | set_cc_op(s, CC_OP_SARB + ot); |
2c0262af FB |
6576 | if (op != 0) { |
6577 | if (mod != 3) | |
57fec1fe | 6578 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 6579 | else |
57fec1fe | 6580 | gen_op_mov_reg_T0(ot, rm); |
f484d386 FB |
6581 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
6582 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
2c0262af FB |
6583 | } |
6584 | break; | |
6585 | case 0x1bc: /* bsf */ | |
6586 | case 0x1bd: /* bsr */ | |
6191b059 FB |
6587 | { |
6588 | int label1; | |
1e4840bf FB |
6589 | TCGv t0; |
6590 | ||
6191b059 | 6591 | ot = dflag + OT_WORD; |
0af10c86 | 6592 | modrm = cpu_ldub_code(env, s->pc++); |
6191b059 | 6593 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 6594 | gen_ldst_modrm(env, s,modrm, ot, OR_TMP0, 0); |
6191b059 | 6595 | gen_extu(ot, cpu_T[0]); |
a7812ae4 | 6596 | t0 = tcg_temp_local_new(); |
1e4840bf | 6597 | tcg_gen_mov_tl(t0, cpu_T[0]); |
31501a71 AP |
6598 | if ((b & 1) && (prefixes & PREFIX_REPZ) && |
6599 | (s->cpuid_ext3_features & CPUID_EXT3_ABM)) { | |
6600 | switch(ot) { | |
6601 | case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0, | |
6602 | tcg_const_i32(16)); break; | |
6603 | case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0, | |
6604 | tcg_const_i32(32)); break; | |
6605 | case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0, | |
6606 | tcg_const_i32(64)); break; | |
6607 | } | |
6608 | gen_op_mov_reg_T0(ot, reg); | |
6191b059 | 6609 | } else { |
31501a71 AP |
6610 | label1 = gen_new_label(); |
6611 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6612 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1); | |
6613 | if (b & 1) { | |
6614 | gen_helper_bsr(cpu_T[0], t0); | |
6615 | } else { | |
6616 | gen_helper_bsf(cpu_T[0], t0); | |
6617 | } | |
6618 | gen_op_mov_reg_T0(ot, reg); | |
6619 | tcg_gen_movi_tl(cpu_cc_dst, 1); | |
6620 | gen_set_label(label1); | |
6621 | tcg_gen_discard_tl(cpu_cc_src); | |
3ca51d07 | 6622 | set_cc_op(s, CC_OP_LOGICB + ot); |
6191b059 | 6623 | } |
1e4840bf | 6624 | tcg_temp_free(t0); |
6191b059 | 6625 | } |
2c0262af FB |
6626 | break; |
6627 | /************************/ | |
6628 | /* bcd */ | |
6629 | case 0x27: /* daa */ | |
14ce26e7 FB |
6630 | if (CODE64(s)) |
6631 | goto illegal_op; | |
773cdfcc | 6632 | gen_update_cc_op(s); |
7923057b | 6633 | gen_helper_daa(cpu_env); |
3ca51d07 | 6634 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6635 | break; |
6636 | case 0x2f: /* das */ | |
14ce26e7 FB |
6637 | if (CODE64(s)) |
6638 | goto illegal_op; | |
773cdfcc | 6639 | gen_update_cc_op(s); |
7923057b | 6640 | gen_helper_das(cpu_env); |
3ca51d07 | 6641 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6642 | break; |
6643 | case 0x37: /* aaa */ | |
14ce26e7 FB |
6644 | if (CODE64(s)) |
6645 | goto illegal_op; | |
773cdfcc | 6646 | gen_update_cc_op(s); |
7923057b | 6647 | gen_helper_aaa(cpu_env); |
3ca51d07 | 6648 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6649 | break; |
6650 | case 0x3f: /* aas */ | |
14ce26e7 FB |
6651 | if (CODE64(s)) |
6652 | goto illegal_op; | |
773cdfcc | 6653 | gen_update_cc_op(s); |
7923057b | 6654 | gen_helper_aas(cpu_env); |
3ca51d07 | 6655 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6656 | break; |
6657 | case 0xd4: /* aam */ | |
14ce26e7 FB |
6658 | if (CODE64(s)) |
6659 | goto illegal_op; | |
0af10c86 | 6660 | val = cpu_ldub_code(env, s->pc++); |
b6d7c3db TS |
6661 | if (val == 0) { |
6662 | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); | |
6663 | } else { | |
7923057b | 6664 | gen_helper_aam(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 6665 | set_cc_op(s, CC_OP_LOGICB); |
b6d7c3db | 6666 | } |
2c0262af FB |
6667 | break; |
6668 | case 0xd5: /* aad */ | |
14ce26e7 FB |
6669 | if (CODE64(s)) |
6670 | goto illegal_op; | |
0af10c86 | 6671 | val = cpu_ldub_code(env, s->pc++); |
7923057b | 6672 | gen_helper_aad(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 6673 | set_cc_op(s, CC_OP_LOGICB); |
2c0262af FB |
6674 | break; |
6675 | /************************/ | |
6676 | /* misc */ | |
6677 | case 0x90: /* nop */ | |
ab1f142b | 6678 | /* XXX: correct lock test for all insn */ |
7418027e | 6679 | if (prefixes & PREFIX_LOCK) { |
ab1f142b | 6680 | goto illegal_op; |
7418027e RH |
6681 | } |
6682 | /* If REX_B is set, then this is xchg eax, r8d, not a nop. */ | |
6683 | if (REX_B(s)) { | |
6684 | goto do_xchg_reg_eax; | |
6685 | } | |
0573fbfc TS |
6686 | if (prefixes & PREFIX_REPZ) { |
6687 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE); | |
6688 | } | |
2c0262af FB |
6689 | break; |
6690 | case 0x9b: /* fwait */ | |
5fafdf24 | 6691 | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == |
7eee2a50 FB |
6692 | (HF_MP_MASK | HF_TS_MASK)) { |
6693 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
2ee73ac3 | 6694 | } else { |
773cdfcc | 6695 | gen_update_cc_op(s); |
14ce26e7 | 6696 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6697 | gen_helper_fwait(cpu_env); |
7eee2a50 | 6698 | } |
2c0262af FB |
6699 | break; |
6700 | case 0xcc: /* int3 */ | |
6701 | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); | |
6702 | break; | |
6703 | case 0xcd: /* int N */ | |
0af10c86 | 6704 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6705 | if (s->vm86 && s->iopl != 3) { |
5fafdf24 | 6706 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
f115e911 FB |
6707 | } else { |
6708 | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); | |
6709 | } | |
2c0262af FB |
6710 | break; |
6711 | case 0xce: /* into */ | |
14ce26e7 FB |
6712 | if (CODE64(s)) |
6713 | goto illegal_op; | |
773cdfcc | 6714 | gen_update_cc_op(s); |
a8ede8ba | 6715 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6716 | gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start)); |
2c0262af | 6717 | break; |
0b97134b | 6718 | #ifdef WANT_ICEBP |
2c0262af | 6719 | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
872929aa | 6720 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); |
aba9d61e | 6721 | #if 1 |
2c0262af | 6722 | gen_debug(s, pc_start - s->cs_base); |
aba9d61e FB |
6723 | #else |
6724 | /* start debug */ | |
0af10c86 | 6725 | tb_flush(env); |
24537a01 | 6726 | qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); |
aba9d61e | 6727 | #endif |
2c0262af | 6728 | break; |
0b97134b | 6729 | #endif |
2c0262af FB |
6730 | case 0xfa: /* cli */ |
6731 | if (!s->vm86) { | |
6732 | if (s->cpl <= s->iopl) { | |
f0967a1a | 6733 | gen_helper_cli(cpu_env); |
2c0262af FB |
6734 | } else { |
6735 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6736 | } | |
6737 | } else { | |
6738 | if (s->iopl == 3) { | |
f0967a1a | 6739 | gen_helper_cli(cpu_env); |
2c0262af FB |
6740 | } else { |
6741 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6742 | } | |
6743 | } | |
6744 | break; | |
6745 | case 0xfb: /* sti */ | |
6746 | if (!s->vm86) { | |
6747 | if (s->cpl <= s->iopl) { | |
6748 | gen_sti: | |
f0967a1a | 6749 | gen_helper_sti(cpu_env); |
2c0262af | 6750 | /* interruptions are enabled only the first insn after sti */ |
a2cc3b24 FB |
6751 | /* If several instructions disable interrupts, only the |
6752 | _first_ does it */ | |
6753 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 6754 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af | 6755 | /* give a chance to handle pending irqs */ |
14ce26e7 | 6756 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6757 | gen_eob(s); |
6758 | } else { | |
6759 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6760 | } | |
6761 | } else { | |
6762 | if (s->iopl == 3) { | |
6763 | goto gen_sti; | |
6764 | } else { | |
6765 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6766 | } | |
6767 | } | |
6768 | break; | |
6769 | case 0x62: /* bound */ | |
14ce26e7 FB |
6770 | if (CODE64(s)) |
6771 | goto illegal_op; | |
2c0262af | 6772 | ot = dflag ? OT_LONG : OT_WORD; |
0af10c86 | 6773 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
6774 | reg = (modrm >> 3) & 7; |
6775 | mod = (modrm >> 6) & 3; | |
6776 | if (mod == 3) | |
6777 | goto illegal_op; | |
57fec1fe | 6778 | gen_op_mov_TN_reg(ot, 0, reg); |
0af10c86 | 6779 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 6780 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6781 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
92fc4b58 BS |
6782 | if (ot == OT_WORD) { |
6783 | gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32); | |
6784 | } else { | |
6785 | gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32); | |
6786 | } | |
2c0262af FB |
6787 | break; |
6788 | case 0x1c8 ... 0x1cf: /* bswap reg */ | |
14ce26e7 FB |
6789 | reg = (b & 7) | REX_B(s); |
6790 | #ifdef TARGET_X86_64 | |
6791 | if (dflag == 2) { | |
57fec1fe | 6792 | gen_op_mov_TN_reg(OT_QUAD, 0, reg); |
66896cb8 | 6793 | tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); |
57fec1fe | 6794 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 6795 | } else |
8777643e | 6796 | #endif |
57fec1fe FB |
6797 | { |
6798 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
8777643e AJ |
6799 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
6800 | tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); | |
57fec1fe | 6801 | gen_op_mov_reg_T0(OT_LONG, reg); |
14ce26e7 | 6802 | } |
2c0262af FB |
6803 | break; |
6804 | case 0xd6: /* salc */ | |
14ce26e7 FB |
6805 | if (CODE64(s)) |
6806 | goto illegal_op; | |
c7b3c873 | 6807 | gen_compute_eflags_c(s, cpu_T[0]); |
bd7a7b33 FB |
6808 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
6809 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
6810 | break; |
6811 | case 0xe0: /* loopnz */ | |
6812 | case 0xe1: /* loopz */ | |
2c0262af FB |
6813 | case 0xe2: /* loop */ |
6814 | case 0xe3: /* jecxz */ | |
14ce26e7 | 6815 | { |
6e0d8677 | 6816 | int l1, l2, l3; |
14ce26e7 | 6817 | |
0af10c86 | 6818 | tval = (int8_t)insn_get(env, s, OT_BYTE); |
14ce26e7 FB |
6819 | next_eip = s->pc - s->cs_base; |
6820 | tval += next_eip; | |
6821 | if (s->dflag == 0) | |
6822 | tval &= 0xffff; | |
3b46e624 | 6823 | |
14ce26e7 FB |
6824 | l1 = gen_new_label(); |
6825 | l2 = gen_new_label(); | |
6e0d8677 | 6826 | l3 = gen_new_label(); |
14ce26e7 | 6827 | b &= 3; |
6e0d8677 FB |
6828 | switch(b) { |
6829 | case 0: /* loopnz */ | |
6830 | case 1: /* loopz */ | |
6e0d8677 FB |
6831 | gen_op_add_reg_im(s->aflag, R_ECX, -1); |
6832 | gen_op_jz_ecx(s->aflag, l3); | |
5bdb91b0 | 6833 | gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1); |
6e0d8677 FB |
6834 | break; |
6835 | case 2: /* loop */ | |
6836 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
6837 | gen_op_jnz_ecx(s->aflag, l1); | |
6838 | break; | |
6839 | default: | |
6840 | case 3: /* jcxz */ | |
6841 | gen_op_jz_ecx(s->aflag, l1); | |
6842 | break; | |
14ce26e7 FB |
6843 | } |
6844 | ||
6e0d8677 | 6845 | gen_set_label(l3); |
14ce26e7 | 6846 | gen_jmp_im(next_eip); |
8e1c85e3 | 6847 | tcg_gen_br(l2); |
6e0d8677 | 6848 | |
14ce26e7 FB |
6849 | gen_set_label(l1); |
6850 | gen_jmp_im(tval); | |
6851 | gen_set_label(l2); | |
6852 | gen_eob(s); | |
6853 | } | |
2c0262af FB |
6854 | break; |
6855 | case 0x130: /* wrmsr */ | |
6856 | case 0x132: /* rdmsr */ | |
6857 | if (s->cpl != 0) { | |
6858 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6859 | } else { | |
773cdfcc | 6860 | gen_update_cc_op(s); |
872929aa | 6861 | gen_jmp_im(pc_start - s->cs_base); |
0573fbfc | 6862 | if (b & 2) { |
4a7443be | 6863 | gen_helper_rdmsr(cpu_env); |
0573fbfc | 6864 | } else { |
4a7443be | 6865 | gen_helper_wrmsr(cpu_env); |
0573fbfc | 6866 | } |
2c0262af FB |
6867 | } |
6868 | break; | |
6869 | case 0x131: /* rdtsc */ | |
773cdfcc | 6870 | gen_update_cc_op(s); |
ecada8a2 | 6871 | gen_jmp_im(pc_start - s->cs_base); |
efade670 PB |
6872 | if (use_icount) |
6873 | gen_io_start(); | |
4a7443be | 6874 | gen_helper_rdtsc(cpu_env); |
efade670 PB |
6875 | if (use_icount) { |
6876 | gen_io_end(); | |
6877 | gen_jmp(s, s->pc - s->cs_base); | |
6878 | } | |
2c0262af | 6879 | break; |
df01e0fc | 6880 | case 0x133: /* rdpmc */ |
773cdfcc | 6881 | gen_update_cc_op(s); |
df01e0fc | 6882 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6883 | gen_helper_rdpmc(cpu_env); |
df01e0fc | 6884 | break; |
023fe10d | 6885 | case 0x134: /* sysenter */ |
2436b61a | 6886 | /* For Intel SYSENTER is valid on 64-bit */ |
0af10c86 | 6887 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 6888 | goto illegal_op; |
023fe10d FB |
6889 | if (!s->pe) { |
6890 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6891 | } else { | |
728d803b | 6892 | gen_update_cc_op(s); |
14ce26e7 | 6893 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6894 | gen_helper_sysenter(cpu_env); |
023fe10d FB |
6895 | gen_eob(s); |
6896 | } | |
6897 | break; | |
6898 | case 0x135: /* sysexit */ | |
2436b61a | 6899 | /* For Intel SYSEXIT is valid on 64-bit */ |
0af10c86 | 6900 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 6901 | goto illegal_op; |
023fe10d FB |
6902 | if (!s->pe) { |
6903 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6904 | } else { | |
728d803b | 6905 | gen_update_cc_op(s); |
14ce26e7 | 6906 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6907 | gen_helper_sysexit(cpu_env, tcg_const_i32(dflag)); |
023fe10d FB |
6908 | gen_eob(s); |
6909 | } | |
6910 | break; | |
14ce26e7 FB |
6911 | #ifdef TARGET_X86_64 |
6912 | case 0x105: /* syscall */ | |
6913 | /* XXX: is it usable in real mode ? */ | |
728d803b | 6914 | gen_update_cc_op(s); |
14ce26e7 | 6915 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6916 | gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start)); |
14ce26e7 FB |
6917 | gen_eob(s); |
6918 | break; | |
6919 | case 0x107: /* sysret */ | |
6920 | if (!s->pe) { | |
6921 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6922 | } else { | |
728d803b | 6923 | gen_update_cc_op(s); |
14ce26e7 | 6924 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6925 | gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag)); |
aba9d61e | 6926 | /* condition codes are modified only in long mode */ |
3ca51d07 RH |
6927 | if (s->lma) { |
6928 | set_cc_op(s, CC_OP_EFLAGS); | |
6929 | } | |
14ce26e7 FB |
6930 | gen_eob(s); |
6931 | } | |
6932 | break; | |
6933 | #endif | |
2c0262af | 6934 | case 0x1a2: /* cpuid */ |
773cdfcc | 6935 | gen_update_cc_op(s); |
9575cb94 | 6936 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6937 | gen_helper_cpuid(cpu_env); |
2c0262af FB |
6938 | break; |
6939 | case 0xf4: /* hlt */ | |
6940 | if (s->cpl != 0) { | |
6941 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6942 | } else { | |
773cdfcc | 6943 | gen_update_cc_op(s); |
94451178 | 6944 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6945 | gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); |
5779406a | 6946 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
6947 | } |
6948 | break; | |
6949 | case 0x100: | |
0af10c86 | 6950 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
6951 | mod = (modrm >> 6) & 3; |
6952 | op = (modrm >> 3) & 7; | |
6953 | switch(op) { | |
6954 | case 0: /* sldt */ | |
f115e911 FB |
6955 | if (!s->pe || s->vm86) |
6956 | goto illegal_op; | |
872929aa | 6957 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); |
651ba608 | 6958 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); |
2c0262af FB |
6959 | ot = OT_WORD; |
6960 | if (mod == 3) | |
6961 | ot += s->dflag; | |
0af10c86 | 6962 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
6963 | break; |
6964 | case 2: /* lldt */ | |
f115e911 FB |
6965 | if (!s->pe || s->vm86) |
6966 | goto illegal_op; | |
2c0262af FB |
6967 | if (s->cpl != 0) { |
6968 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6969 | } else { | |
872929aa | 6970 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); |
0af10c86 | 6971 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 6972 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6973 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 6974 | gen_helper_lldt(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
6975 | } |
6976 | break; | |
6977 | case 1: /* str */ | |
f115e911 FB |
6978 | if (!s->pe || s->vm86) |
6979 | goto illegal_op; | |
872929aa | 6980 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); |
651ba608 | 6981 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); |
2c0262af FB |
6982 | ot = OT_WORD; |
6983 | if (mod == 3) | |
6984 | ot += s->dflag; | |
0af10c86 | 6985 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
6986 | break; |
6987 | case 3: /* ltr */ | |
f115e911 FB |
6988 | if (!s->pe || s->vm86) |
6989 | goto illegal_op; | |
2c0262af FB |
6990 | if (s->cpl != 0) { |
6991 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6992 | } else { | |
872929aa | 6993 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); |
0af10c86 | 6994 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 6995 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6996 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 6997 | gen_helper_ltr(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
6998 | } |
6999 | break; | |
7000 | case 4: /* verr */ | |
7001 | case 5: /* verw */ | |
f115e911 FB |
7002 | if (!s->pe || s->vm86) |
7003 | goto illegal_op; | |
0af10c86 | 7004 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
773cdfcc | 7005 | gen_update_cc_op(s); |
2999a0b2 BS |
7006 | if (op == 4) { |
7007 | gen_helper_verr(cpu_env, cpu_T[0]); | |
7008 | } else { | |
7009 | gen_helper_verw(cpu_env, cpu_T[0]); | |
7010 | } | |
3ca51d07 | 7011 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 7012 | break; |
2c0262af FB |
7013 | default: |
7014 | goto illegal_op; | |
7015 | } | |
7016 | break; | |
7017 | case 0x101: | |
0af10c86 | 7018 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7019 | mod = (modrm >> 6) & 3; |
7020 | op = (modrm >> 3) & 7; | |
3d7374c5 | 7021 | rm = modrm & 7; |
2c0262af FB |
7022 | switch(op) { |
7023 | case 0: /* sgdt */ | |
2c0262af FB |
7024 | if (mod == 3) |
7025 | goto illegal_op; | |
872929aa | 7026 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); |
0af10c86 | 7027 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
651ba608 | 7028 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); |
57fec1fe | 7029 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
aba9d61e | 7030 | gen_add_A0_im(s, 2); |
651ba608 | 7031 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); |
2c0262af FB |
7032 | if (!s->dflag) |
7033 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7034 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af | 7035 | break; |
3d7374c5 FB |
7036 | case 1: |
7037 | if (mod == 3) { | |
7038 | switch (rm) { | |
7039 | case 0: /* monitor */ | |
7040 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7041 | s->cpl != 0) | |
7042 | goto illegal_op; | |
773cdfcc | 7043 | gen_update_cc_op(s); |
3d7374c5 FB |
7044 | gen_jmp_im(pc_start - s->cs_base); |
7045 | #ifdef TARGET_X86_64 | |
7046 | if (s->aflag == 2) { | |
bbf662ee | 7047 | gen_op_movq_A0_reg(R_EAX); |
5fafdf24 | 7048 | } else |
3d7374c5 FB |
7049 | #endif |
7050 | { | |
bbf662ee | 7051 | gen_op_movl_A0_reg(R_EAX); |
3d7374c5 FB |
7052 | if (s->aflag == 0) |
7053 | gen_op_andl_A0_ffff(); | |
7054 | } | |
7055 | gen_add_A0_ds_seg(s); | |
4a7443be | 7056 | gen_helper_monitor(cpu_env, cpu_A0); |
3d7374c5 FB |
7057 | break; |
7058 | case 1: /* mwait */ | |
7059 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7060 | s->cpl != 0) | |
7061 | goto illegal_op; | |
728d803b | 7062 | gen_update_cc_op(s); |
94451178 | 7063 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7064 | gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); |
3d7374c5 FB |
7065 | gen_eob(s); |
7066 | break; | |
a9321a4d PA |
7067 | case 2: /* clac */ |
7068 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7069 | s->cpl != 0) { | |
7070 | goto illegal_op; | |
7071 | } | |
7072 | gen_helper_clac(cpu_env); | |
7073 | gen_jmp_im(s->pc - s->cs_base); | |
7074 | gen_eob(s); | |
7075 | break; | |
7076 | case 3: /* stac */ | |
7077 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7078 | s->cpl != 0) { | |
7079 | goto illegal_op; | |
7080 | } | |
7081 | gen_helper_stac(cpu_env); | |
7082 | gen_jmp_im(s->pc - s->cs_base); | |
7083 | gen_eob(s); | |
7084 | break; | |
3d7374c5 FB |
7085 | default: |
7086 | goto illegal_op; | |
7087 | } | |
7088 | } else { /* sidt */ | |
872929aa | 7089 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); |
0af10c86 | 7090 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
651ba608 | 7091 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); |
57fec1fe | 7092 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
3d7374c5 | 7093 | gen_add_A0_im(s, 2); |
651ba608 | 7094 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); |
3d7374c5 FB |
7095 | if (!s->dflag) |
7096 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7097 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
3d7374c5 FB |
7098 | } |
7099 | break; | |
2c0262af FB |
7100 | case 2: /* lgdt */ |
7101 | case 3: /* lidt */ | |
0573fbfc | 7102 | if (mod == 3) { |
773cdfcc | 7103 | gen_update_cc_op(s); |
872929aa | 7104 | gen_jmp_im(pc_start - s->cs_base); |
0573fbfc TS |
7105 | switch(rm) { |
7106 | case 0: /* VMRUN */ | |
872929aa FB |
7107 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7108 | goto illegal_op; | |
7109 | if (s->cpl != 0) { | |
7110 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
0573fbfc | 7111 | break; |
872929aa | 7112 | } else { |
052e80d5 | 7113 | gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag), |
a7812ae4 | 7114 | tcg_const_i32(s->pc - pc_start)); |
db620f46 | 7115 | tcg_gen_exit_tb(0); |
5779406a | 7116 | s->is_jmp = DISAS_TB_JUMP; |
872929aa | 7117 | } |
0573fbfc TS |
7118 | break; |
7119 | case 1: /* VMMCALL */ | |
872929aa FB |
7120 | if (!(s->flags & HF_SVME_MASK)) |
7121 | goto illegal_op; | |
052e80d5 | 7122 | gen_helper_vmmcall(cpu_env); |
0573fbfc TS |
7123 | break; |
7124 | case 2: /* VMLOAD */ | |
872929aa FB |
7125 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7126 | goto illegal_op; | |
7127 | if (s->cpl != 0) { | |
7128 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7129 | break; | |
7130 | } else { | |
052e80d5 | 7131 | gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7132 | } |
0573fbfc TS |
7133 | break; |
7134 | case 3: /* VMSAVE */ | |
872929aa FB |
7135 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7136 | goto illegal_op; | |
7137 | if (s->cpl != 0) { | |
7138 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7139 | break; | |
7140 | } else { | |
052e80d5 | 7141 | gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7142 | } |
0573fbfc TS |
7143 | break; |
7144 | case 4: /* STGI */ | |
872929aa FB |
7145 | if ((!(s->flags & HF_SVME_MASK) && |
7146 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7147 | !s->pe) | |
7148 | goto illegal_op; | |
7149 | if (s->cpl != 0) { | |
7150 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7151 | break; | |
7152 | } else { | |
052e80d5 | 7153 | gen_helper_stgi(cpu_env); |
872929aa | 7154 | } |
0573fbfc TS |
7155 | break; |
7156 | case 5: /* CLGI */ | |
872929aa FB |
7157 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7158 | goto illegal_op; | |
7159 | if (s->cpl != 0) { | |
7160 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7161 | break; | |
7162 | } else { | |
052e80d5 | 7163 | gen_helper_clgi(cpu_env); |
872929aa | 7164 | } |
0573fbfc TS |
7165 | break; |
7166 | case 6: /* SKINIT */ | |
872929aa FB |
7167 | if ((!(s->flags & HF_SVME_MASK) && |
7168 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7169 | !s->pe) | |
7170 | goto illegal_op; | |
052e80d5 | 7171 | gen_helper_skinit(cpu_env); |
0573fbfc TS |
7172 | break; |
7173 | case 7: /* INVLPGA */ | |
872929aa FB |
7174 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7175 | goto illegal_op; | |
7176 | if (s->cpl != 0) { | |
7177 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7178 | break; | |
7179 | } else { | |
052e80d5 | 7180 | gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7181 | } |
0573fbfc TS |
7182 | break; |
7183 | default: | |
7184 | goto illegal_op; | |
7185 | } | |
7186 | } else if (s->cpl != 0) { | |
2c0262af FB |
7187 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7188 | } else { | |
872929aa FB |
7189 | gen_svm_check_intercept(s, pc_start, |
7190 | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); | |
0af10c86 | 7191 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 7192 | gen_op_ld_T1_A0(OT_WORD + s->mem_index); |
aba9d61e | 7193 | gen_add_A0_im(s, 2); |
57fec1fe | 7194 | gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af FB |
7195 | if (!s->dflag) |
7196 | gen_op_andl_T0_im(0xffffff); | |
7197 | if (op == 2) { | |
651ba608 FB |
7198 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); |
7199 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); | |
2c0262af | 7200 | } else { |
651ba608 FB |
7201 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); |
7202 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); | |
2c0262af FB |
7203 | } |
7204 | } | |
7205 | break; | |
7206 | case 4: /* smsw */ | |
872929aa | 7207 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); |
e2542fe2 | 7208 | #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN |
f60d2728 | 7209 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); |
7210 | #else | |
651ba608 | 7211 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); |
f60d2728 | 7212 | #endif |
0af10c86 | 7213 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 1); |
2c0262af FB |
7214 | break; |
7215 | case 6: /* lmsw */ | |
7216 | if (s->cpl != 0) { | |
7217 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7218 | } else { | |
872929aa | 7219 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
0af10c86 | 7220 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
4a7443be | 7221 | gen_helper_lmsw(cpu_env, cpu_T[0]); |
14ce26e7 | 7222 | gen_jmp_im(s->pc - s->cs_base); |
d71b9a8b | 7223 | gen_eob(s); |
2c0262af FB |
7224 | } |
7225 | break; | |
1b050077 AP |
7226 | case 7: |
7227 | if (mod != 3) { /* invlpg */ | |
7228 | if (s->cpl != 0) { | |
7229 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7230 | } else { | |
773cdfcc | 7231 | gen_update_cc_op(s); |
1b050077 | 7232 | gen_jmp_im(pc_start - s->cs_base); |
0af10c86 | 7233 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4a7443be | 7234 | gen_helper_invlpg(cpu_env, cpu_A0); |
1b050077 AP |
7235 | gen_jmp_im(s->pc - s->cs_base); |
7236 | gen_eob(s); | |
7237 | } | |
2c0262af | 7238 | } else { |
1b050077 AP |
7239 | switch (rm) { |
7240 | case 0: /* swapgs */ | |
14ce26e7 | 7241 | #ifdef TARGET_X86_64 |
1b050077 AP |
7242 | if (CODE64(s)) { |
7243 | if (s->cpl != 0) { | |
7244 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7245 | } else { | |
7246 | tcg_gen_ld_tl(cpu_T[0], cpu_env, | |
7247 | offsetof(CPUX86State,segs[R_GS].base)); | |
7248 | tcg_gen_ld_tl(cpu_T[1], cpu_env, | |
7249 | offsetof(CPUX86State,kernelgsbase)); | |
7250 | tcg_gen_st_tl(cpu_T[1], cpu_env, | |
7251 | offsetof(CPUX86State,segs[R_GS].base)); | |
7252 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
7253 | offsetof(CPUX86State,kernelgsbase)); | |
7254 | } | |
5fafdf24 | 7255 | } else |
14ce26e7 FB |
7256 | #endif |
7257 | { | |
7258 | goto illegal_op; | |
7259 | } | |
1b050077 AP |
7260 | break; |
7261 | case 1: /* rdtscp */ | |
7262 | if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) | |
7263 | goto illegal_op; | |
773cdfcc | 7264 | gen_update_cc_op(s); |
9575cb94 | 7265 | gen_jmp_im(pc_start - s->cs_base); |
1b050077 AP |
7266 | if (use_icount) |
7267 | gen_io_start(); | |
4a7443be | 7268 | gen_helper_rdtscp(cpu_env); |
1b050077 AP |
7269 | if (use_icount) { |
7270 | gen_io_end(); | |
7271 | gen_jmp(s, s->pc - s->cs_base); | |
7272 | } | |
7273 | break; | |
7274 | default: | |
7275 | goto illegal_op; | |
14ce26e7 | 7276 | } |
2c0262af FB |
7277 | } |
7278 | break; | |
7279 | default: | |
7280 | goto illegal_op; | |
7281 | } | |
7282 | break; | |
3415a4dd FB |
7283 | case 0x108: /* invd */ |
7284 | case 0x109: /* wbinvd */ | |
7285 | if (s->cpl != 0) { | |
7286 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7287 | } else { | |
872929aa | 7288 | gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); |
3415a4dd FB |
7289 | /* nothing to do */ |
7290 | } | |
7291 | break; | |
14ce26e7 FB |
7292 | case 0x63: /* arpl or movslS (x86_64) */ |
7293 | #ifdef TARGET_X86_64 | |
7294 | if (CODE64(s)) { | |
7295 | int d_ot; | |
7296 | /* d_ot is the size of destination */ | |
7297 | d_ot = dflag + OT_WORD; | |
7298 | ||
0af10c86 | 7299 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7300 | reg = ((modrm >> 3) & 7) | rex_r; |
7301 | mod = (modrm >> 6) & 3; | |
7302 | rm = (modrm & 7) | REX_B(s); | |
3b46e624 | 7303 | |
14ce26e7 | 7304 | if (mod == 3) { |
57fec1fe | 7305 | gen_op_mov_TN_reg(OT_LONG, 0, rm); |
14ce26e7 FB |
7306 | /* sign extend */ |
7307 | if (d_ot == OT_QUAD) | |
e108dd01 | 7308 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
57fec1fe | 7309 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7310 | } else { |
0af10c86 | 7311 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 7312 | if (d_ot == OT_QUAD) { |
57fec1fe | 7313 | gen_op_lds_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7314 | } else { |
57fec1fe | 7315 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7316 | } |
57fec1fe | 7317 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7318 | } |
5fafdf24 | 7319 | } else |
14ce26e7 FB |
7320 | #endif |
7321 | { | |
3bd7da9e | 7322 | int label1; |
49d9fdcc | 7323 | TCGv t0, t1, t2, a0; |
1e4840bf | 7324 | |
14ce26e7 FB |
7325 | if (!s->pe || s->vm86) |
7326 | goto illegal_op; | |
a7812ae4 PB |
7327 | t0 = tcg_temp_local_new(); |
7328 | t1 = tcg_temp_local_new(); | |
7329 | t2 = tcg_temp_local_new(); | |
3bd7da9e | 7330 | ot = OT_WORD; |
0af10c86 | 7331 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7332 | reg = (modrm >> 3) & 7; |
7333 | mod = (modrm >> 6) & 3; | |
7334 | rm = modrm & 7; | |
7335 | if (mod != 3) { | |
0af10c86 | 7336 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
1e4840bf | 7337 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
49d9fdcc LD |
7338 | a0 = tcg_temp_local_new(); |
7339 | tcg_gen_mov_tl(a0, cpu_A0); | |
14ce26e7 | 7340 | } else { |
1e4840bf | 7341 | gen_op_mov_v_reg(ot, t0, rm); |
49d9fdcc | 7342 | TCGV_UNUSED(a0); |
14ce26e7 | 7343 | } |
1e4840bf FB |
7344 | gen_op_mov_v_reg(ot, t1, reg); |
7345 | tcg_gen_andi_tl(cpu_tmp0, t0, 3); | |
7346 | tcg_gen_andi_tl(t1, t1, 3); | |
7347 | tcg_gen_movi_tl(t2, 0); | |
3bd7da9e | 7348 | label1 = gen_new_label(); |
1e4840bf FB |
7349 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); |
7350 | tcg_gen_andi_tl(t0, t0, ~3); | |
7351 | tcg_gen_or_tl(t0, t0, t1); | |
7352 | tcg_gen_movi_tl(t2, CC_Z); | |
3bd7da9e | 7353 | gen_set_label(label1); |
14ce26e7 | 7354 | if (mod != 3) { |
49d9fdcc LD |
7355 | gen_op_st_v(ot + s->mem_index, t0, a0); |
7356 | tcg_temp_free(a0); | |
7357 | } else { | |
1e4840bf | 7358 | gen_op_mov_reg_v(ot, rm, t0); |
14ce26e7 | 7359 | } |
c7b3c873 | 7360 | gen_compute_eflags(s, cpu_cc_src); |
3bd7da9e | 7361 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); |
1e4840bf | 7362 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); |
1e4840bf FB |
7363 | tcg_temp_free(t0); |
7364 | tcg_temp_free(t1); | |
7365 | tcg_temp_free(t2); | |
f115e911 | 7366 | } |
f115e911 | 7367 | break; |
2c0262af FB |
7368 | case 0x102: /* lar */ |
7369 | case 0x103: /* lsl */ | |
cec6843e FB |
7370 | { |
7371 | int label1; | |
1e4840bf | 7372 | TCGv t0; |
cec6843e FB |
7373 | if (!s->pe || s->vm86) |
7374 | goto illegal_op; | |
7375 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 7376 | modrm = cpu_ldub_code(env, s->pc++); |
cec6843e | 7377 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 7378 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
a7812ae4 | 7379 | t0 = tcg_temp_local_new(); |
773cdfcc | 7380 | gen_update_cc_op(s); |
2999a0b2 BS |
7381 | if (b == 0x102) { |
7382 | gen_helper_lar(t0, cpu_env, cpu_T[0]); | |
7383 | } else { | |
7384 | gen_helper_lsl(t0, cpu_env, cpu_T[0]); | |
7385 | } | |
cec6843e FB |
7386 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); |
7387 | label1 = gen_new_label(); | |
cb63669a | 7388 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
1e4840bf | 7389 | gen_op_mov_reg_v(ot, reg, t0); |
cec6843e | 7390 | gen_set_label(label1); |
3ca51d07 | 7391 | set_cc_op(s, CC_OP_EFLAGS); |
1e4840bf | 7392 | tcg_temp_free(t0); |
cec6843e | 7393 | } |
2c0262af FB |
7394 | break; |
7395 | case 0x118: | |
0af10c86 | 7396 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7397 | mod = (modrm >> 6) & 3; |
7398 | op = (modrm >> 3) & 7; | |
7399 | switch(op) { | |
7400 | case 0: /* prefetchnta */ | |
7401 | case 1: /* prefetchnt0 */ | |
7402 | case 2: /* prefetchnt0 */ | |
7403 | case 3: /* prefetchnt0 */ | |
7404 | if (mod == 3) | |
7405 | goto illegal_op; | |
0af10c86 | 7406 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
7407 | /* nothing more to do */ |
7408 | break; | |
e17a36ce | 7409 | default: /* nop (multi byte) */ |
0af10c86 | 7410 | gen_nop_modrm(env, s, modrm); |
e17a36ce | 7411 | break; |
2c0262af FB |
7412 | } |
7413 | break; | |
e17a36ce | 7414 | case 0x119 ... 0x11f: /* nop (multi byte) */ |
0af10c86 BS |
7415 | modrm = cpu_ldub_code(env, s->pc++); |
7416 | gen_nop_modrm(env, s, modrm); | |
e17a36ce | 7417 | break; |
2c0262af FB |
7418 | case 0x120: /* mov reg, crN */ |
7419 | case 0x122: /* mov crN, reg */ | |
7420 | if (s->cpl != 0) { | |
7421 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7422 | } else { | |
0af10c86 | 7423 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7424 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7425 | * AMD documentation (24594.pdf) and testing of | |
7426 | * intel 386 and 486 processors all show that the mod bits | |
7427 | * are assumed to be 1's, regardless of actual values. | |
7428 | */ | |
14ce26e7 FB |
7429 | rm = (modrm & 7) | REX_B(s); |
7430 | reg = ((modrm >> 3) & 7) | rex_r; | |
7431 | if (CODE64(s)) | |
7432 | ot = OT_QUAD; | |
7433 | else | |
7434 | ot = OT_LONG; | |
ccd59d09 AP |
7435 | if ((prefixes & PREFIX_LOCK) && (reg == 0) && |
7436 | (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { | |
7437 | reg = 8; | |
7438 | } | |
2c0262af FB |
7439 | switch(reg) { |
7440 | case 0: | |
7441 | case 2: | |
7442 | case 3: | |
7443 | case 4: | |
9230e66e | 7444 | case 8: |
773cdfcc | 7445 | gen_update_cc_op(s); |
872929aa | 7446 | gen_jmp_im(pc_start - s->cs_base); |
2c0262af | 7447 | if (b & 2) { |
57fec1fe | 7448 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be BS |
7449 | gen_helper_write_crN(cpu_env, tcg_const_i32(reg), |
7450 | cpu_T[0]); | |
14ce26e7 | 7451 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7452 | gen_eob(s); |
7453 | } else { | |
4a7443be | 7454 | gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg)); |
57fec1fe | 7455 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7456 | } |
7457 | break; | |
7458 | default: | |
7459 | goto illegal_op; | |
7460 | } | |
7461 | } | |
7462 | break; | |
7463 | case 0x121: /* mov reg, drN */ | |
7464 | case 0x123: /* mov drN, reg */ | |
7465 | if (s->cpl != 0) { | |
7466 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7467 | } else { | |
0af10c86 | 7468 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7469 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7470 | * AMD documentation (24594.pdf) and testing of | |
7471 | * intel 386 and 486 processors all show that the mod bits | |
7472 | * are assumed to be 1's, regardless of actual values. | |
7473 | */ | |
14ce26e7 FB |
7474 | rm = (modrm & 7) | REX_B(s); |
7475 | reg = ((modrm >> 3) & 7) | rex_r; | |
7476 | if (CODE64(s)) | |
7477 | ot = OT_QUAD; | |
7478 | else | |
7479 | ot = OT_LONG; | |
2c0262af | 7480 | /* XXX: do it dynamically with CR4.DE bit */ |
14ce26e7 | 7481 | if (reg == 4 || reg == 5 || reg >= 8) |
2c0262af FB |
7482 | goto illegal_op; |
7483 | if (b & 2) { | |
0573fbfc | 7484 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
57fec1fe | 7485 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be | 7486 | gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7487 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7488 | gen_eob(s); |
7489 | } else { | |
0573fbfc | 7490 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
651ba608 | 7491 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); |
57fec1fe | 7492 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7493 | } |
7494 | } | |
7495 | break; | |
7496 | case 0x106: /* clts */ | |
7497 | if (s->cpl != 0) { | |
7498 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7499 | } else { | |
0573fbfc | 7500 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
f0967a1a | 7501 | gen_helper_clts(cpu_env); |
7eee2a50 | 7502 | /* abort block because static cpu state changed */ |
14ce26e7 | 7503 | gen_jmp_im(s->pc - s->cs_base); |
7eee2a50 | 7504 | gen_eob(s); |
2c0262af FB |
7505 | } |
7506 | break; | |
222a3336 | 7507 | /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ |
664e0f19 FB |
7508 | case 0x1c3: /* MOVNTI reg, mem */ |
7509 | if (!(s->cpuid_features & CPUID_SSE2)) | |
14ce26e7 | 7510 | goto illegal_op; |
664e0f19 | 7511 | ot = s->dflag == 2 ? OT_QUAD : OT_LONG; |
0af10c86 | 7512 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7513 | mod = (modrm >> 6) & 3; |
7514 | if (mod == 3) | |
7515 | goto illegal_op; | |
7516 | reg = ((modrm >> 3) & 7) | rex_r; | |
7517 | /* generate a generic store */ | |
0af10c86 | 7518 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
14ce26e7 | 7519 | break; |
664e0f19 | 7520 | case 0x1ae: |
0af10c86 | 7521 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7522 | mod = (modrm >> 6) & 3; |
7523 | op = (modrm >> 3) & 7; | |
7524 | switch(op) { | |
7525 | case 0: /* fxsave */ | |
5fafdf24 | 7526 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7527 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7528 | goto illegal_op; |
09d85fb8 | 7529 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7530 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7531 | break; | |
7532 | } | |
0af10c86 | 7533 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
773cdfcc | 7534 | gen_update_cc_op(s); |
19e6c4b8 | 7535 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 7536 | gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2))); |
664e0f19 FB |
7537 | break; |
7538 | case 1: /* fxrstor */ | |
5fafdf24 | 7539 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7540 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7541 | goto illegal_op; |
09d85fb8 | 7542 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7543 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7544 | break; | |
7545 | } | |
0af10c86 | 7546 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
773cdfcc | 7547 | gen_update_cc_op(s); |
19e6c4b8 | 7548 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
7549 | gen_helper_fxrstor(cpu_env, cpu_A0, |
7550 | tcg_const_i32((s->dflag == 2))); | |
664e0f19 FB |
7551 | break; |
7552 | case 2: /* ldmxcsr */ | |
7553 | case 3: /* stmxcsr */ | |
7554 | if (s->flags & HF_TS_MASK) { | |
7555 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7556 | break; | |
14ce26e7 | 7557 | } |
664e0f19 FB |
7558 | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) || |
7559 | mod == 3) | |
14ce26e7 | 7560 | goto illegal_op; |
0af10c86 | 7561 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 7562 | if (op == 2) { |
57fec1fe | 7563 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
20f8bd48 | 7564 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 7565 | gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); |
14ce26e7 | 7566 | } else { |
651ba608 | 7567 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
57fec1fe | 7568 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7569 | } |
664e0f19 FB |
7570 | break; |
7571 | case 5: /* lfence */ | |
7572 | case 6: /* mfence */ | |
8001c294 | 7573 | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) |
664e0f19 FB |
7574 | goto illegal_op; |
7575 | break; | |
8f091a59 FB |
7576 | case 7: /* sfence / clflush */ |
7577 | if ((modrm & 0xc7) == 0xc0) { | |
7578 | /* sfence */ | |
a35f3ec7 | 7579 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */ |
8f091a59 FB |
7580 | if (!(s->cpuid_features & CPUID_SSE)) |
7581 | goto illegal_op; | |
7582 | } else { | |
7583 | /* clflush */ | |
7584 | if (!(s->cpuid_features & CPUID_CLFLUSH)) | |
7585 | goto illegal_op; | |
0af10c86 | 7586 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8f091a59 FB |
7587 | } |
7588 | break; | |
664e0f19 | 7589 | default: |
14ce26e7 FB |
7590 | goto illegal_op; |
7591 | } | |
7592 | break; | |
a35f3ec7 | 7593 | case 0x10d: /* 3DNow! prefetch(w) */ |
0af10c86 | 7594 | modrm = cpu_ldub_code(env, s->pc++); |
a35f3ec7 AJ |
7595 | mod = (modrm >> 6) & 3; |
7596 | if (mod == 3) | |
7597 | goto illegal_op; | |
0af10c86 | 7598 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8f091a59 FB |
7599 | /* ignore for now */ |
7600 | break; | |
3b21e03e | 7601 | case 0x1aa: /* rsm */ |
872929aa | 7602 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); |
3b21e03e FB |
7603 | if (!(s->flags & HF_SMM_MASK)) |
7604 | goto illegal_op; | |
728d803b | 7605 | gen_update_cc_op(s); |
3b21e03e | 7606 | gen_jmp_im(s->pc - s->cs_base); |
608badfc | 7607 | gen_helper_rsm(cpu_env); |
3b21e03e FB |
7608 | gen_eob(s); |
7609 | break; | |
222a3336 AZ |
7610 | case 0x1b8: /* SSE4.2 popcnt */ |
7611 | if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != | |
7612 | PREFIX_REPZ) | |
7613 | goto illegal_op; | |
7614 | if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) | |
7615 | goto illegal_op; | |
7616 | ||
0af10c86 | 7617 | modrm = cpu_ldub_code(env, s->pc++); |
8b4a3df8 | 7618 | reg = ((modrm >> 3) & 7) | rex_r; |
222a3336 AZ |
7619 | |
7620 | if (s->prefix & PREFIX_DATA) | |
7621 | ot = OT_WORD; | |
7622 | else if (s->dflag != 2) | |
7623 | ot = OT_LONG; | |
7624 | else | |
7625 | ot = OT_QUAD; | |
7626 | ||
0af10c86 | 7627 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
d3eb5eae | 7628 | gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot)); |
222a3336 | 7629 | gen_op_mov_reg_T0(ot, reg); |
fdb0d09d | 7630 | |
3ca51d07 | 7631 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 | 7632 | break; |
a35f3ec7 AJ |
7633 | case 0x10e ... 0x10f: |
7634 | /* 3DNow! instructions, ignore prefixes */ | |
7635 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); | |
664e0f19 FB |
7636 | case 0x110 ... 0x117: |
7637 | case 0x128 ... 0x12f: | |
4242b1bd | 7638 | case 0x138 ... 0x13a: |
d9f4bb27 | 7639 | case 0x150 ... 0x179: |
664e0f19 FB |
7640 | case 0x17c ... 0x17f: |
7641 | case 0x1c2: | |
7642 | case 0x1c4 ... 0x1c6: | |
7643 | case 0x1d0 ... 0x1fe: | |
0af10c86 | 7644 | gen_sse(env, s, b, pc_start, rex_r); |
664e0f19 | 7645 | break; |
2c0262af FB |
7646 | default: |
7647 | goto illegal_op; | |
7648 | } | |
7649 | /* lock generation */ | |
7650 | if (s->prefix & PREFIX_LOCK) | |
a7812ae4 | 7651 | gen_helper_unlock(); |
2c0262af FB |
7652 | return s->pc; |
7653 | illegal_op: | |
ab1f142b | 7654 | if (s->prefix & PREFIX_LOCK) |
a7812ae4 | 7655 | gen_helper_unlock(); |
2c0262af FB |
7656 | /* XXX: ensure that no lock was generated */ |
7657 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
7658 | return s->pc; | |
7659 | } | |
7660 | ||
2c0262af FB |
7661 | void optimize_flags_init(void) |
7662 | { | |
a7812ae4 PB |
7663 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7664 | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 AF |
7665 | offsetof(CPUX86State, cc_op), "cc_op"); |
7666 | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src), | |
a7812ae4 | 7667 | "cc_src"); |
317ac620 | 7668 | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst), |
a7812ae4 | 7669 | "cc_dst"); |
437a88a5 | 7670 | |
cc739bb0 LD |
7671 | #ifdef TARGET_X86_64 |
7672 | cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0, | |
317ac620 | 7673 | offsetof(CPUX86State, regs[R_EAX]), "rax"); |
cc739bb0 | 7674 | cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7675 | offsetof(CPUX86State, regs[R_ECX]), "rcx"); |
cc739bb0 | 7676 | cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7677 | offsetof(CPUX86State, regs[R_EDX]), "rdx"); |
cc739bb0 | 7678 | cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7679 | offsetof(CPUX86State, regs[R_EBX]), "rbx"); |
cc739bb0 | 7680 | cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7681 | offsetof(CPUX86State, regs[R_ESP]), "rsp"); |
cc739bb0 | 7682 | cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7683 | offsetof(CPUX86State, regs[R_EBP]), "rbp"); |
cc739bb0 | 7684 | cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7685 | offsetof(CPUX86State, regs[R_ESI]), "rsi"); |
cc739bb0 | 7686 | cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7687 | offsetof(CPUX86State, regs[R_EDI]), "rdi"); |
cc739bb0 | 7688 | cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7689 | offsetof(CPUX86State, regs[8]), "r8"); |
cc739bb0 | 7690 | cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7691 | offsetof(CPUX86State, regs[9]), "r9"); |
cc739bb0 | 7692 | cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7693 | offsetof(CPUX86State, regs[10]), "r10"); |
cc739bb0 | 7694 | cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7695 | offsetof(CPUX86State, regs[11]), "r11"); |
cc739bb0 | 7696 | cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7697 | offsetof(CPUX86State, regs[12]), "r12"); |
cc739bb0 | 7698 | cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7699 | offsetof(CPUX86State, regs[13]), "r13"); |
cc739bb0 | 7700 | cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7701 | offsetof(CPUX86State, regs[14]), "r14"); |
cc739bb0 | 7702 | cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7703 | offsetof(CPUX86State, regs[15]), "r15"); |
cc739bb0 LD |
7704 | #else |
7705 | cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 | 7706 | offsetof(CPUX86State, regs[R_EAX]), "eax"); |
cc739bb0 | 7707 | cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7708 | offsetof(CPUX86State, regs[R_ECX]), "ecx"); |
cc739bb0 | 7709 | cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7710 | offsetof(CPUX86State, regs[R_EDX]), "edx"); |
cc739bb0 | 7711 | cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7712 | offsetof(CPUX86State, regs[R_EBX]), "ebx"); |
cc739bb0 | 7713 | cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7714 | offsetof(CPUX86State, regs[R_ESP]), "esp"); |
cc739bb0 | 7715 | cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7716 | offsetof(CPUX86State, regs[R_EBP]), "ebp"); |
cc739bb0 | 7717 | cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7718 | offsetof(CPUX86State, regs[R_ESI]), "esi"); |
cc739bb0 | 7719 | cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7720 | offsetof(CPUX86State, regs[R_EDI]), "edi"); |
cc739bb0 LD |
7721 | #endif |
7722 | ||
437a88a5 | 7723 | /* register helpers */ |
a7812ae4 | 7724 | #define GEN_HELPER 2 |
437a88a5 | 7725 | #include "helper.h" |
2c0262af FB |
7726 | } |
7727 | ||
7728 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for | |
7729 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
7730 | information for each intermediate instruction. */ | |
317ac620 | 7731 | static inline void gen_intermediate_code_internal(CPUX86State *env, |
2cfc5f17 TS |
7732 | TranslationBlock *tb, |
7733 | int search_pc) | |
2c0262af FB |
7734 | { |
7735 | DisasContext dc1, *dc = &dc1; | |
14ce26e7 | 7736 | target_ulong pc_ptr; |
2c0262af | 7737 | uint16_t *gen_opc_end; |
a1d1bb31 | 7738 | CPUBreakpoint *bp; |
7f5b7d3e | 7739 | int j, lj; |
c068688b | 7740 | uint64_t flags; |
14ce26e7 FB |
7741 | target_ulong pc_start; |
7742 | target_ulong cs_base; | |
2e70f6ef PB |
7743 | int num_insns; |
7744 | int max_insns; | |
3b46e624 | 7745 | |
2c0262af | 7746 | /* generate intermediate code */ |
14ce26e7 FB |
7747 | pc_start = tb->pc; |
7748 | cs_base = tb->cs_base; | |
2c0262af | 7749 | flags = tb->flags; |
3a1d9b8b | 7750 | |
4f31916f | 7751 | dc->pe = (flags >> HF_PE_SHIFT) & 1; |
2c0262af FB |
7752 | dc->code32 = (flags >> HF_CS32_SHIFT) & 1; |
7753 | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; | |
7754 | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; | |
7755 | dc->f_st = 0; | |
7756 | dc->vm86 = (flags >> VM_SHIFT) & 1; | |
7757 | dc->cpl = (flags >> HF_CPL_SHIFT) & 3; | |
7758 | dc->iopl = (flags >> IOPL_SHIFT) & 3; | |
7759 | dc->tf = (flags >> TF_SHIFT) & 1; | |
34865134 | 7760 | dc->singlestep_enabled = env->singlestep_enabled; |
2c0262af | 7761 | dc->cc_op = CC_OP_DYNAMIC; |
e207582f | 7762 | dc->cc_op_dirty = false; |
2c0262af FB |
7763 | dc->cs_base = cs_base; |
7764 | dc->tb = tb; | |
7765 | dc->popl_esp_hack = 0; | |
7766 | /* select memory access functions */ | |
7767 | dc->mem_index = 0; | |
7768 | if (flags & HF_SOFTMMU_MASK) { | |
a9321a4d | 7769 | dc->mem_index = (cpu_mmu_index(env) + 1) << 2; |
2c0262af | 7770 | } |
14ce26e7 | 7771 | dc->cpuid_features = env->cpuid_features; |
3d7374c5 | 7772 | dc->cpuid_ext_features = env->cpuid_ext_features; |
e771edab | 7773 | dc->cpuid_ext2_features = env->cpuid_ext2_features; |
12e26b75 | 7774 | dc->cpuid_ext3_features = env->cpuid_ext3_features; |
a9321a4d | 7775 | dc->cpuid_7_0_ebx_features = env->cpuid_7_0_ebx_features; |
14ce26e7 FB |
7776 | #ifdef TARGET_X86_64 |
7777 | dc->lma = (flags >> HF_LMA_SHIFT) & 1; | |
7778 | dc->code64 = (flags >> HF_CS64_SHIFT) & 1; | |
7779 | #endif | |
7eee2a50 | 7780 | dc->flags = flags; |
a2cc3b24 FB |
7781 | dc->jmp_opt = !(dc->tf || env->singlestep_enabled || |
7782 | (flags & HF_INHIBIT_IRQ_MASK) | |
415fa2ea | 7783 | #ifndef CONFIG_SOFTMMU |
2c0262af FB |
7784 | || (flags & HF_SOFTMMU_MASK) |
7785 | #endif | |
7786 | ); | |
4f31916f FB |
7787 | #if 0 |
7788 | /* check addseg logic */ | |
dc196a57 | 7789 | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) |
4f31916f FB |
7790 | printf("ERROR addseg\n"); |
7791 | #endif | |
7792 | ||
a7812ae4 PB |
7793 | cpu_T[0] = tcg_temp_new(); |
7794 | cpu_T[1] = tcg_temp_new(); | |
7795 | cpu_A0 = tcg_temp_new(); | |
7796 | cpu_T3 = tcg_temp_new(); | |
7797 | ||
7798 | cpu_tmp0 = tcg_temp_new(); | |
7799 | cpu_tmp1_i64 = tcg_temp_new_i64(); | |
7800 | cpu_tmp2_i32 = tcg_temp_new_i32(); | |
7801 | cpu_tmp3_i32 = tcg_temp_new_i32(); | |
7802 | cpu_tmp4 = tcg_temp_new(); | |
7803 | cpu_tmp5 = tcg_temp_new(); | |
a7812ae4 PB |
7804 | cpu_ptr0 = tcg_temp_new_ptr(); |
7805 | cpu_ptr1 = tcg_temp_new_ptr(); | |
57fec1fe | 7806 | |
92414b31 | 7807 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
7808 | |
7809 | dc->is_jmp = DISAS_NEXT; | |
7810 | pc_ptr = pc_start; | |
7811 | lj = -1; | |
2e70f6ef PB |
7812 | num_insns = 0; |
7813 | max_insns = tb->cflags & CF_COUNT_MASK; | |
7814 | if (max_insns == 0) | |
7815 | max_insns = CF_COUNT_MASK; | |
2c0262af | 7816 | |
2e70f6ef | 7817 | gen_icount_start(); |
2c0262af | 7818 | for(;;) { |
72cf2d4f BS |
7819 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
7820 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a2397807 JK |
7821 | if (bp->pc == pc_ptr && |
7822 | !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { | |
2c0262af FB |
7823 | gen_debug(dc, pc_ptr - dc->cs_base); |
7824 | break; | |
7825 | } | |
7826 | } | |
7827 | } | |
7828 | if (search_pc) { | |
92414b31 | 7829 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
7830 | if (lj < j) { |
7831 | lj++; | |
7832 | while (lj < j) | |
ab1103de | 7833 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 7834 | } |
25983cad | 7835 | tcg_ctx.gen_opc_pc[lj] = pc_ptr; |
2c0262af | 7836 | gen_opc_cc_op[lj] = dc->cc_op; |
ab1103de | 7837 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 7838 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
2c0262af | 7839 | } |
2e70f6ef PB |
7840 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
7841 | gen_io_start(); | |
7842 | ||
0af10c86 | 7843 | pc_ptr = disas_insn(env, dc, pc_ptr); |
2e70f6ef | 7844 | num_insns++; |
2c0262af FB |
7845 | /* stop translation if indicated */ |
7846 | if (dc->is_jmp) | |
7847 | break; | |
7848 | /* if single step mode, we generate only one instruction and | |
7849 | generate an exception */ | |
a2cc3b24 FB |
7850 | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear |
7851 | the flag and abort the translation to give the irqs a | |
7852 | change to be happen */ | |
5fafdf24 | 7853 | if (dc->tf || dc->singlestep_enabled || |
2e70f6ef | 7854 | (flags & HF_INHIBIT_IRQ_MASK)) { |
14ce26e7 | 7855 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7856 | gen_eob(dc); |
7857 | break; | |
7858 | } | |
7859 | /* if too long translation, stop generation too */ | |
efd7f486 | 7860 | if (tcg_ctx.gen_opc_ptr >= gen_opc_end || |
2e70f6ef PB |
7861 | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || |
7862 | num_insns >= max_insns) { | |
14ce26e7 | 7863 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7864 | gen_eob(dc); |
7865 | break; | |
7866 | } | |
1b530a6d AJ |
7867 | if (singlestep) { |
7868 | gen_jmp_im(pc_ptr - dc->cs_base); | |
7869 | gen_eob(dc); | |
7870 | break; | |
7871 | } | |
2c0262af | 7872 | } |
2e70f6ef PB |
7873 | if (tb->cflags & CF_LAST_IO) |
7874 | gen_io_end(); | |
7875 | gen_icount_end(tb, num_insns); | |
efd7f486 | 7876 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
2c0262af FB |
7877 | /* we don't forget to fill the last values */ |
7878 | if (search_pc) { | |
92414b31 | 7879 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
7880 | lj++; |
7881 | while (lj <= j) | |
ab1103de | 7882 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 7883 | } |
3b46e624 | 7884 | |
2c0262af | 7885 | #ifdef DEBUG_DISAS |
8fec2b8c | 7886 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
14ce26e7 | 7887 | int disas_flags; |
93fcfe39 AL |
7888 | qemu_log("----------------\n"); |
7889 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
14ce26e7 FB |
7890 | #ifdef TARGET_X86_64 |
7891 | if (dc->code64) | |
7892 | disas_flags = 2; | |
7893 | else | |
7894 | #endif | |
7895 | disas_flags = !dc->code32; | |
f4359b9f | 7896 | log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags); |
93fcfe39 | 7897 | qemu_log("\n"); |
2c0262af FB |
7898 | } |
7899 | #endif | |
7900 | ||
2e70f6ef | 7901 | if (!search_pc) { |
2c0262af | 7902 | tb->size = pc_ptr - pc_start; |
2e70f6ef PB |
7903 | tb->icount = num_insns; |
7904 | } | |
2c0262af FB |
7905 | } |
7906 | ||
317ac620 | 7907 | void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 7908 | { |
2cfc5f17 | 7909 | gen_intermediate_code_internal(env, tb, 0); |
2c0262af FB |
7910 | } |
7911 | ||
317ac620 | 7912 | void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 7913 | { |
2cfc5f17 | 7914 | gen_intermediate_code_internal(env, tb, 1); |
2c0262af FB |
7915 | } |
7916 | ||
317ac620 | 7917 | void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos) |
d2856f1a AJ |
7918 | { |
7919 | int cc_op; | |
7920 | #ifdef DEBUG_DISAS | |
8fec2b8c | 7921 | if (qemu_loglevel_mask(CPU_LOG_TB_OP)) { |
d2856f1a | 7922 | int i; |
93fcfe39 | 7923 | qemu_log("RESTORE:\n"); |
d2856f1a | 7924 | for(i = 0;i <= pc_pos; i++) { |
ab1103de | 7925 | if (tcg_ctx.gen_opc_instr_start[i]) { |
25983cad EV |
7926 | qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, |
7927 | tcg_ctx.gen_opc_pc[i]); | |
d2856f1a AJ |
7928 | } |
7929 | } | |
e87b7cb0 | 7930 | qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
25983cad | 7931 | pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base, |
d2856f1a AJ |
7932 | (uint32_t)tb->cs_base); |
7933 | } | |
7934 | #endif | |
25983cad | 7935 | env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base; |
d2856f1a AJ |
7936 | cc_op = gen_opc_cc_op[pc_pos]; |
7937 | if (cc_op != CC_OP_DYNAMIC) | |
7938 | env->cc_op = cc_op; | |
7939 | } |