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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 translation | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
2c0262af | 25 | |
bec93d72 | 26 | #include "qemu/host-utils.h" |
2c0262af | 27 | #include "cpu.h" |
76cad711 | 28 | #include "disas/disas.h" |
57fec1fe | 29 | #include "tcg-op.h" |
2c0262af | 30 | |
a7812ae4 PB |
31 | #include "helper.h" |
32 | #define GEN_HELPER 1 | |
33 | #include "helper.h" | |
34 | ||
2c0262af FB |
35 | #define PREFIX_REPZ 0x01 |
36 | #define PREFIX_REPNZ 0x02 | |
37 | #define PREFIX_LOCK 0x04 | |
38 | #define PREFIX_DATA 0x08 | |
39 | #define PREFIX_ADR 0x10 | |
701ed211 | 40 | #define PREFIX_VEX 0x20 |
2c0262af | 41 | |
14ce26e7 | 42 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
43 | #define CODE64(s) ((s)->code64) |
44 | #define REX_X(s) ((s)->rex_x) | |
45 | #define REX_B(s) ((s)->rex_b) | |
14ce26e7 | 46 | #else |
14ce26e7 FB |
47 | #define CODE64(s) 0 |
48 | #define REX_X(s) 0 | |
49 | #define REX_B(s) 0 | |
50 | #endif | |
51 | ||
bec93d72 RH |
52 | #ifdef TARGET_X86_64 |
53 | # define ctztl ctz64 | |
54 | # define clztl clz64 | |
55 | #else | |
56 | # define ctztl ctz32 | |
57 | # define clztl clz32 | |
58 | #endif | |
59 | ||
57fec1fe FB |
60 | //#define MACRO_TEST 1 |
61 | ||
57fec1fe | 62 | /* global register indexes */ |
a7812ae4 | 63 | static TCGv_ptr cpu_env; |
a3251186 | 64 | static TCGv cpu_A0; |
988c3eb0 | 65 | static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT; |
a7812ae4 | 66 | static TCGv_i32 cpu_cc_op; |
cc739bb0 | 67 | static TCGv cpu_regs[CPU_NB_REGS]; |
1e4840bf | 68 | /* local temps */ |
3b9d3cf1 | 69 | static TCGv cpu_T[2]; |
57fec1fe | 70 | /* local register indexes (only used inside old micro ops) */ |
a7812ae4 PB |
71 | static TCGv cpu_tmp0, cpu_tmp4; |
72 | static TCGv_ptr cpu_ptr0, cpu_ptr1; | |
73 | static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; | |
74 | static TCGv_i64 cpu_tmp1_i64; | |
57fec1fe | 75 | |
1a7ff922 PB |
76 | static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
77 | ||
022c62cb | 78 | #include "exec/gen-icount.h" |
2e70f6ef | 79 | |
57fec1fe FB |
80 | #ifdef TARGET_X86_64 |
81 | static int x86_64_hregs; | |
ae063a68 FB |
82 | #endif |
83 | ||
2c0262af FB |
84 | typedef struct DisasContext { |
85 | /* current insn context */ | |
86 | int override; /* -1 if no override */ | |
87 | int prefix; | |
1d71ddb1 | 88 | TCGMemOp aflag; |
ab4e4aec | 89 | TCGMemOp dflag; |
14ce26e7 | 90 | target_ulong pc; /* pc = eip + cs_base */ |
2c0262af FB |
91 | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
92 | static state change (stop translation) */ | |
93 | /* current block context */ | |
14ce26e7 | 94 | target_ulong cs_base; /* base of CS segment */ |
2c0262af FB |
95 | int pe; /* protected mode */ |
96 | int code32; /* 32 bit code segment */ | |
14ce26e7 FB |
97 | #ifdef TARGET_X86_64 |
98 | int lma; /* long mode active */ | |
99 | int code64; /* 64 bit code segment */ | |
100 | int rex_x, rex_b; | |
101 | #endif | |
701ed211 RH |
102 | int vex_l; /* vex vector length */ |
103 | int vex_v; /* vex vvvv register, without 1's compliment. */ | |
2c0262af | 104 | int ss32; /* 32 bit stack segment */ |
fee71888 | 105 | CCOp cc_op; /* current CC operation */ |
e207582f | 106 | bool cc_op_dirty; |
2c0262af FB |
107 | int addseg; /* non zero if either DS/ES/SS have a non zero base */ |
108 | int f_st; /* currently unused */ | |
109 | int vm86; /* vm86 mode */ | |
110 | int cpl; | |
111 | int iopl; | |
112 | int tf; /* TF cpu flag */ | |
34865134 | 113 | int singlestep_enabled; /* "hardware" single step enabled */ |
2c0262af FB |
114 | int jmp_opt; /* use direct block chaining for direct jumps */ |
115 | int mem_index; /* select memory access functions */ | |
c068688b | 116 | uint64_t flags; /* all execution flags */ |
2c0262af FB |
117 | struct TranslationBlock *tb; |
118 | int popl_esp_hack; /* for correct popl with esp base handling */ | |
14ce26e7 FB |
119 | int rip_offset; /* only used in x86_64, but left for simplicity */ |
120 | int cpuid_features; | |
3d7374c5 | 121 | int cpuid_ext_features; |
e771edab | 122 | int cpuid_ext2_features; |
12e26b75 | 123 | int cpuid_ext3_features; |
a9321a4d | 124 | int cpuid_7_0_ebx_features; |
2c0262af FB |
125 | } DisasContext; |
126 | ||
127 | static void gen_eob(DisasContext *s); | |
14ce26e7 FB |
128 | static void gen_jmp(DisasContext *s, target_ulong eip); |
129 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); | |
d67dc9e6 | 130 | static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d); |
2c0262af FB |
131 | |
132 | /* i386 arith/logic operations */ | |
133 | enum { | |
5fafdf24 TS |
134 | OP_ADDL, |
135 | OP_ORL, | |
136 | OP_ADCL, | |
2c0262af | 137 | OP_SBBL, |
5fafdf24 TS |
138 | OP_ANDL, |
139 | OP_SUBL, | |
140 | OP_XORL, | |
2c0262af FB |
141 | OP_CMPL, |
142 | }; | |
143 | ||
144 | /* i386 shift ops */ | |
145 | enum { | |
5fafdf24 TS |
146 | OP_ROL, |
147 | OP_ROR, | |
148 | OP_RCL, | |
149 | OP_RCR, | |
150 | OP_SHL, | |
151 | OP_SHR, | |
2c0262af FB |
152 | OP_SHL1, /* undocumented */ |
153 | OP_SAR = 7, | |
154 | }; | |
155 | ||
8e1c85e3 FB |
156 | enum { |
157 | JCC_O, | |
158 | JCC_B, | |
159 | JCC_Z, | |
160 | JCC_BE, | |
161 | JCC_S, | |
162 | JCC_P, | |
163 | JCC_L, | |
164 | JCC_LE, | |
165 | }; | |
166 | ||
2c0262af FB |
167 | enum { |
168 | /* I386 int registers */ | |
169 | OR_EAX, /* MUST be even numbered */ | |
170 | OR_ECX, | |
171 | OR_EDX, | |
172 | OR_EBX, | |
173 | OR_ESP, | |
174 | OR_EBP, | |
175 | OR_ESI, | |
176 | OR_EDI, | |
14ce26e7 FB |
177 | |
178 | OR_TMP0 = 16, /* temporary operand register */ | |
2c0262af FB |
179 | OR_TMP1, |
180 | OR_A0, /* temporary register used when doing address evaluation */ | |
2c0262af FB |
181 | }; |
182 | ||
b666265b | 183 | enum { |
a3251186 RH |
184 | USES_CC_DST = 1, |
185 | USES_CC_SRC = 2, | |
988c3eb0 RH |
186 | USES_CC_SRC2 = 4, |
187 | USES_CC_SRCT = 8, | |
b666265b RH |
188 | }; |
189 | ||
190 | /* Bit set if the global variable is live after setting CC_OP to X. */ | |
191 | static const uint8_t cc_op_live[CC_OP_NB] = { | |
988c3eb0 | 192 | [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, |
b666265b RH |
193 | [CC_OP_EFLAGS] = USES_CC_SRC, |
194 | [CC_OP_MULB ... CC_OP_MULQ] = USES_CC_DST | USES_CC_SRC, | |
195 | [CC_OP_ADDB ... CC_OP_ADDQ] = USES_CC_DST | USES_CC_SRC, | |
988c3eb0 | 196 | [CC_OP_ADCB ... CC_OP_ADCQ] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, |
a3251186 | 197 | [CC_OP_SUBB ... CC_OP_SUBQ] = USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, |
988c3eb0 | 198 | [CC_OP_SBBB ... CC_OP_SBBQ] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, |
b666265b RH |
199 | [CC_OP_LOGICB ... CC_OP_LOGICQ] = USES_CC_DST, |
200 | [CC_OP_INCB ... CC_OP_INCQ] = USES_CC_DST | USES_CC_SRC, | |
201 | [CC_OP_DECB ... CC_OP_DECQ] = USES_CC_DST | USES_CC_SRC, | |
202 | [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC, | |
203 | [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC, | |
bc4b43dc | 204 | [CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC, |
cd7f97ca RH |
205 | [CC_OP_ADCX] = USES_CC_DST | USES_CC_SRC, |
206 | [CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2, | |
207 | [CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, | |
436ff2d2 | 208 | [CC_OP_CLR] = 0, |
b666265b RH |
209 | }; |
210 | ||
e207582f | 211 | static void set_cc_op(DisasContext *s, CCOp op) |
3ca51d07 | 212 | { |
b666265b RH |
213 | int dead; |
214 | ||
215 | if (s->cc_op == op) { | |
216 | return; | |
217 | } | |
218 | ||
219 | /* Discard CC computation that will no longer be used. */ | |
220 | dead = cc_op_live[s->cc_op] & ~cc_op_live[op]; | |
221 | if (dead & USES_CC_DST) { | |
222 | tcg_gen_discard_tl(cpu_cc_dst); | |
e207582f | 223 | } |
b666265b RH |
224 | if (dead & USES_CC_SRC) { |
225 | tcg_gen_discard_tl(cpu_cc_src); | |
226 | } | |
988c3eb0 RH |
227 | if (dead & USES_CC_SRC2) { |
228 | tcg_gen_discard_tl(cpu_cc_src2); | |
229 | } | |
a3251186 RH |
230 | if (dead & USES_CC_SRCT) { |
231 | tcg_gen_discard_tl(cpu_cc_srcT); | |
232 | } | |
b666265b | 233 | |
e2f515cf RH |
234 | if (op == CC_OP_DYNAMIC) { |
235 | /* The DYNAMIC setting is translator only, and should never be | |
236 | stored. Thus we always consider it clean. */ | |
237 | s->cc_op_dirty = false; | |
238 | } else { | |
239 | /* Discard any computed CC_OP value (see shifts). */ | |
240 | if (s->cc_op == CC_OP_DYNAMIC) { | |
241 | tcg_gen_discard_i32(cpu_cc_op); | |
242 | } | |
243 | s->cc_op_dirty = true; | |
244 | } | |
b666265b | 245 | s->cc_op = op; |
e207582f RH |
246 | } |
247 | ||
e207582f RH |
248 | static void gen_update_cc_op(DisasContext *s) |
249 | { | |
250 | if (s->cc_op_dirty) { | |
773cdfcc | 251 | tcg_gen_movi_i32(cpu_cc_op, s->cc_op); |
e207582f RH |
252 | s->cc_op_dirty = false; |
253 | } | |
3ca51d07 RH |
254 | } |
255 | ||
14ce26e7 FB |
256 | #ifdef TARGET_X86_64 |
257 | ||
258 | #define NB_OP_SIZES 4 | |
259 | ||
14ce26e7 FB |
260 | #else /* !TARGET_X86_64 */ |
261 | ||
262 | #define NB_OP_SIZES 3 | |
263 | ||
14ce26e7 FB |
264 | #endif /* !TARGET_X86_64 */ |
265 | ||
e2542fe2 | 266 | #if defined(HOST_WORDS_BIGENDIAN) |
57fec1fe FB |
267 | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
268 | #define REG_H_OFFSET (sizeof(target_ulong) - 2) | |
269 | #define REG_W_OFFSET (sizeof(target_ulong) - 2) | |
270 | #define REG_L_OFFSET (sizeof(target_ulong) - 4) | |
271 | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) | |
14ce26e7 | 272 | #else |
57fec1fe FB |
273 | #define REG_B_OFFSET 0 |
274 | #define REG_H_OFFSET 1 | |
275 | #define REG_W_OFFSET 0 | |
276 | #define REG_L_OFFSET 0 | |
277 | #define REG_LH_OFFSET 4 | |
14ce26e7 | 278 | #endif |
57fec1fe | 279 | |
96d7073f PM |
280 | /* In instruction encodings for byte register accesses the |
281 | * register number usually indicates "low 8 bits of register N"; | |
282 | * however there are some special cases where N 4..7 indicates | |
283 | * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return | |
284 | * true for this special case, false otherwise. | |
285 | */ | |
286 | static inline bool byte_reg_is_xH(int reg) | |
287 | { | |
288 | if (reg < 4) { | |
289 | return false; | |
290 | } | |
291 | #ifdef TARGET_X86_64 | |
292 | if (reg >= 8 || x86_64_hregs) { | |
293 | return false; | |
294 | } | |
295 | #endif | |
296 | return true; | |
297 | } | |
298 | ||
ab4e4aec RH |
299 | /* Select the size of a push/pop operation. */ |
300 | static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot) | |
301 | { | |
302 | if (CODE64(s)) { | |
303 | return ot == MO_16 ? MO_16 : MO_64; | |
304 | } else { | |
305 | return ot; | |
306 | } | |
307 | } | |
308 | ||
309 | /* Select only size 64 else 32. Used for SSE operand sizes. */ | |
310 | static inline TCGMemOp mo_64_32(TCGMemOp ot) | |
311 | { | |
312 | #ifdef TARGET_X86_64 | |
313 | return ot == MO_64 ? MO_64 : MO_32; | |
314 | #else | |
315 | return MO_32; | |
316 | #endif | |
317 | } | |
318 | ||
319 | /* Select size 8 if lsb of B is clear, else OT. Used for decoding | |
320 | byte vs word opcodes. */ | |
321 | static inline TCGMemOp mo_b_d(int b, TCGMemOp ot) | |
322 | { | |
323 | return b & 1 ? ot : MO_8; | |
324 | } | |
325 | ||
326 | /* Select size 8 if lsb of B is clear, else OT capped at 32. | |
327 | Used for decoding operand size of port opcodes. */ | |
328 | static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot) | |
329 | { | |
330 | return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8; | |
331 | } | |
332 | ||
d67dc9e6 | 333 | static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0) |
57fec1fe FB |
334 | { |
335 | switch(ot) { | |
4ba9938c | 336 | case MO_8: |
96d7073f | 337 | if (!byte_reg_is_xH(reg)) { |
c832e3de | 338 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); |
57fec1fe | 339 | } else { |
c832e3de | 340 | tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); |
57fec1fe FB |
341 | } |
342 | break; | |
4ba9938c | 343 | case MO_16: |
c832e3de | 344 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16); |
57fec1fe | 345 | break; |
4ba9938c | 346 | case MO_32: |
cc739bb0 LD |
347 | /* For x86_64, this sets the higher half of register to zero. |
348 | For i386, this is equivalent to a mov. */ | |
349 | tcg_gen_ext32u_tl(cpu_regs[reg], t0); | |
57fec1fe | 350 | break; |
cc739bb0 | 351 | #ifdef TARGET_X86_64 |
4ba9938c | 352 | case MO_64: |
cc739bb0 | 353 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
57fec1fe | 354 | break; |
14ce26e7 | 355 | #endif |
d67dc9e6 RH |
356 | default: |
357 | tcg_abort(); | |
57fec1fe FB |
358 | } |
359 | } | |
2c0262af | 360 | |
d67dc9e6 | 361 | static inline void gen_op_mov_reg_T0(TCGMemOp ot, int reg) |
57fec1fe | 362 | { |
1e4840bf | 363 | gen_op_mov_reg_v(ot, reg, cpu_T[0]); |
57fec1fe FB |
364 | } |
365 | ||
d67dc9e6 | 366 | static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg) |
57fec1fe | 367 | { |
1e4840bf | 368 | gen_op_mov_reg_v(ot, reg, cpu_T[1]); |
57fec1fe FB |
369 | } |
370 | ||
6f17675a | 371 | static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg) |
57fec1fe | 372 | { |
6f17675a | 373 | gen_op_mov_reg_v(size, reg, cpu_A0); |
57fec1fe FB |
374 | } |
375 | ||
d67dc9e6 | 376 | static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg) |
57fec1fe | 377 | { |
4ba9938c | 378 | if (ot == MO_8 && byte_reg_is_xH(reg)) { |
96d7073f PM |
379 | tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); |
380 | tcg_gen_ext8u_tl(t0, t0); | |
381 | } else { | |
cc739bb0 | 382 | tcg_gen_mov_tl(t0, cpu_regs[reg]); |
57fec1fe FB |
383 | } |
384 | } | |
385 | ||
d67dc9e6 | 386 | static inline void gen_op_mov_TN_reg(TCGMemOp ot, int t_index, int reg) |
1e4840bf FB |
387 | { |
388 | gen_op_mov_v_reg(ot, cpu_T[t_index], reg); | |
389 | } | |
390 | ||
57fec1fe FB |
391 | static inline void gen_op_movl_A0_reg(int reg) |
392 | { | |
cc739bb0 | 393 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
394 | } |
395 | ||
396 | static inline void gen_op_addl_A0_im(int32_t val) | |
397 | { | |
398 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
14ce26e7 | 399 | #ifdef TARGET_X86_64 |
57fec1fe | 400 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); |
14ce26e7 | 401 | #endif |
57fec1fe | 402 | } |
2c0262af | 403 | |
14ce26e7 | 404 | #ifdef TARGET_X86_64 |
57fec1fe FB |
405 | static inline void gen_op_addq_A0_im(int64_t val) |
406 | { | |
407 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
408 | } | |
14ce26e7 | 409 | #endif |
57fec1fe FB |
410 | |
411 | static void gen_add_A0_im(DisasContext *s, int val) | |
412 | { | |
413 | #ifdef TARGET_X86_64 | |
414 | if (CODE64(s)) | |
415 | gen_op_addq_A0_im(val); | |
416 | else | |
417 | #endif | |
418 | gen_op_addl_A0_im(val); | |
419 | } | |
2c0262af | 420 | |
57fec1fe | 421 | static inline void gen_op_addl_T0_T1(void) |
2c0262af | 422 | { |
57fec1fe FB |
423 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
424 | } | |
425 | ||
426 | static inline void gen_op_jmp_T0(void) | |
427 | { | |
317ac620 | 428 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip)); |
57fec1fe FB |
429 | } |
430 | ||
d3f4bbe3 | 431 | static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val) |
57fec1fe | 432 | { |
d3f4bbe3 RH |
433 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
434 | gen_op_mov_reg_v(size, reg, cpu_tmp0); | |
57fec1fe FB |
435 | } |
436 | ||
d3f4bbe3 | 437 | static inline void gen_op_add_reg_T0(TCGMemOp size, int reg) |
57fec1fe | 438 | { |
d3f4bbe3 RH |
439 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
440 | gen_op_mov_reg_v(size, reg, cpu_tmp0); | |
6e0d8677 | 441 | } |
57fec1fe | 442 | |
57fec1fe FB |
443 | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) |
444 | { | |
cc739bb0 LD |
445 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
446 | if (shift != 0) | |
57fec1fe FB |
447 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
448 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
cc739bb0 LD |
449 | /* For x86_64, this sets the higher half of register to zero. |
450 | For i386, this is equivalent to a nop. */ | |
451 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
57fec1fe | 452 | } |
2c0262af | 453 | |
57fec1fe FB |
454 | static inline void gen_op_movl_A0_seg(int reg) |
455 | { | |
317ac620 | 456 | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET); |
57fec1fe | 457 | } |
2c0262af | 458 | |
7162ab21 | 459 | static inline void gen_op_addl_A0_seg(DisasContext *s, int reg) |
57fec1fe | 460 | { |
317ac620 | 461 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 462 | #ifdef TARGET_X86_64 |
7162ab21 VC |
463 | if (CODE64(s)) { |
464 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
465 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
466 | } else { | |
467 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
468 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
469 | } | |
470 | #else | |
471 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe FB |
472 | #endif |
473 | } | |
2c0262af | 474 | |
14ce26e7 | 475 | #ifdef TARGET_X86_64 |
57fec1fe FB |
476 | static inline void gen_op_movq_A0_seg(int reg) |
477 | { | |
317ac620 | 478 | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 479 | } |
14ce26e7 | 480 | |
57fec1fe FB |
481 | static inline void gen_op_addq_A0_seg(int reg) |
482 | { | |
317ac620 | 483 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe FB |
484 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
485 | } | |
486 | ||
487 | static inline void gen_op_movq_A0_reg(int reg) | |
488 | { | |
cc739bb0 | 489 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
490 | } |
491 | ||
492 | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) | |
493 | { | |
cc739bb0 LD |
494 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
495 | if (shift != 0) | |
57fec1fe FB |
496 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
497 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
498 | } | |
14ce26e7 FB |
499 | #endif |
500 | ||
323d1876 | 501 | static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0) |
57fec1fe | 502 | { |
3c5f4116 | 503 | tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE); |
57fec1fe | 504 | } |
2c0262af | 505 | |
323d1876 | 506 | static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0) |
57fec1fe | 507 | { |
3523e4bd | 508 | tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE); |
57fec1fe | 509 | } |
4f31916f | 510 | |
d4faa3e0 RH |
511 | static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) |
512 | { | |
513 | if (d == OR_TMP0) { | |
fd8ca9f6 | 514 | gen_op_st_v(s, idx, cpu_T[0], cpu_A0); |
d4faa3e0 RH |
515 | } else { |
516 | gen_op_mov_reg_T0(idx, d); | |
517 | } | |
518 | } | |
519 | ||
14ce26e7 FB |
520 | static inline void gen_jmp_im(target_ulong pc) |
521 | { | |
57fec1fe | 522 | tcg_gen_movi_tl(cpu_tmp0, pc); |
317ac620 | 523 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip)); |
14ce26e7 FB |
524 | } |
525 | ||
2c0262af FB |
526 | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
527 | { | |
528 | int override; | |
529 | ||
530 | override = s->override; | |
1d71ddb1 | 531 | switch (s->aflag) { |
14ce26e7 | 532 | #ifdef TARGET_X86_64 |
1d71ddb1 | 533 | case MO_64: |
14ce26e7 | 534 | if (override >= 0) { |
57fec1fe FB |
535 | gen_op_movq_A0_seg(override); |
536 | gen_op_addq_A0_reg_sN(0, R_ESI); | |
14ce26e7 | 537 | } else { |
57fec1fe | 538 | gen_op_movq_A0_reg(R_ESI); |
14ce26e7 | 539 | } |
1d71ddb1 | 540 | break; |
14ce26e7 | 541 | #endif |
1d71ddb1 | 542 | case MO_32: |
2c0262af FB |
543 | /* 32 bit address */ |
544 | if (s->addseg && override < 0) | |
545 | override = R_DS; | |
546 | if (override >= 0) { | |
57fec1fe FB |
547 | gen_op_movl_A0_seg(override); |
548 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af | 549 | } else { |
57fec1fe | 550 | gen_op_movl_A0_reg(R_ESI); |
2c0262af | 551 | } |
1d71ddb1 RH |
552 | break; |
553 | case MO_16: | |
2c0262af FB |
554 | /* 16 address, always override */ |
555 | if (override < 0) | |
556 | override = R_DS; | |
a7e5c7de | 557 | tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]); |
7162ab21 | 558 | gen_op_addl_A0_seg(s, override); |
1d71ddb1 RH |
559 | break; |
560 | default: | |
561 | tcg_abort(); | |
2c0262af FB |
562 | } |
563 | } | |
564 | ||
565 | static inline void gen_string_movl_A0_EDI(DisasContext *s) | |
566 | { | |
1d71ddb1 | 567 | switch (s->aflag) { |
14ce26e7 | 568 | #ifdef TARGET_X86_64 |
1d71ddb1 | 569 | case MO_64: |
57fec1fe | 570 | gen_op_movq_A0_reg(R_EDI); |
1d71ddb1 | 571 | break; |
14ce26e7 | 572 | #endif |
1d71ddb1 | 573 | case MO_32: |
2c0262af | 574 | if (s->addseg) { |
57fec1fe FB |
575 | gen_op_movl_A0_seg(R_ES); |
576 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af | 577 | } else { |
57fec1fe | 578 | gen_op_movl_A0_reg(R_EDI); |
2c0262af | 579 | } |
1d71ddb1 RH |
580 | break; |
581 | case MO_16: | |
a7e5c7de | 582 | tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_EDI]); |
7162ab21 | 583 | gen_op_addl_A0_seg(s, R_ES); |
1d71ddb1 RH |
584 | break; |
585 | default: | |
586 | tcg_abort(); | |
2c0262af FB |
587 | } |
588 | } | |
589 | ||
d67dc9e6 | 590 | static inline void gen_op_movl_T0_Dshift(TCGMemOp ot) |
6e0d8677 | 591 | { |
317ac620 | 592 | tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df)); |
6e0d8677 | 593 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); |
2c0262af FB |
594 | }; |
595 | ||
d67dc9e6 | 596 | static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign) |
6e0d8677 | 597 | { |
d824df34 | 598 | switch (size) { |
4ba9938c | 599 | case MO_8: |
d824df34 PB |
600 | if (sign) { |
601 | tcg_gen_ext8s_tl(dst, src); | |
602 | } else { | |
603 | tcg_gen_ext8u_tl(dst, src); | |
604 | } | |
605 | return dst; | |
4ba9938c | 606 | case MO_16: |
d824df34 PB |
607 | if (sign) { |
608 | tcg_gen_ext16s_tl(dst, src); | |
609 | } else { | |
610 | tcg_gen_ext16u_tl(dst, src); | |
611 | } | |
612 | return dst; | |
613 | #ifdef TARGET_X86_64 | |
4ba9938c | 614 | case MO_32: |
d824df34 PB |
615 | if (sign) { |
616 | tcg_gen_ext32s_tl(dst, src); | |
617 | } else { | |
618 | tcg_gen_ext32u_tl(dst, src); | |
619 | } | |
620 | return dst; | |
621 | #endif | |
6e0d8677 | 622 | default: |
d824df34 | 623 | return src; |
6e0d8677 FB |
624 | } |
625 | } | |
3b46e624 | 626 | |
d67dc9e6 | 627 | static void gen_extu(TCGMemOp ot, TCGv reg) |
d824df34 PB |
628 | { |
629 | gen_ext_tl(reg, reg, ot, false); | |
630 | } | |
631 | ||
d67dc9e6 | 632 | static void gen_exts(TCGMemOp ot, TCGv reg) |
6e0d8677 | 633 | { |
d824df34 | 634 | gen_ext_tl(reg, reg, ot, true); |
6e0d8677 | 635 | } |
2c0262af | 636 | |
c92aa1ad | 637 | static inline void gen_op_jnz_ecx(TCGMemOp size, int label1) |
6e0d8677 | 638 | { |
cc739bb0 | 639 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
c92aa1ad | 640 | gen_extu(size, cpu_tmp0); |
cb63669a | 641 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); |
6e0d8677 FB |
642 | } |
643 | ||
c92aa1ad | 644 | static inline void gen_op_jz_ecx(TCGMemOp size, int label1) |
6e0d8677 | 645 | { |
cc739bb0 | 646 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
c92aa1ad | 647 | gen_extu(size, cpu_tmp0); |
cb63669a | 648 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
6e0d8677 | 649 | } |
2c0262af | 650 | |
d67dc9e6 | 651 | static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n) |
a7812ae4 PB |
652 | { |
653 | switch (ot) { | |
4ba9938c | 654 | case MO_8: |
93ab25d7 PB |
655 | gen_helper_inb(v, n); |
656 | break; | |
4ba9938c | 657 | case MO_16: |
93ab25d7 PB |
658 | gen_helper_inw(v, n); |
659 | break; | |
4ba9938c | 660 | case MO_32: |
93ab25d7 PB |
661 | gen_helper_inl(v, n); |
662 | break; | |
d67dc9e6 RH |
663 | default: |
664 | tcg_abort(); | |
a7812ae4 | 665 | } |
a7812ae4 | 666 | } |
2c0262af | 667 | |
d67dc9e6 | 668 | static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n) |
a7812ae4 PB |
669 | { |
670 | switch (ot) { | |
4ba9938c | 671 | case MO_8: |
93ab25d7 PB |
672 | gen_helper_outb(v, n); |
673 | break; | |
4ba9938c | 674 | case MO_16: |
93ab25d7 PB |
675 | gen_helper_outw(v, n); |
676 | break; | |
4ba9938c | 677 | case MO_32: |
93ab25d7 PB |
678 | gen_helper_outl(v, n); |
679 | break; | |
d67dc9e6 RH |
680 | default: |
681 | tcg_abort(); | |
a7812ae4 | 682 | } |
a7812ae4 | 683 | } |
f115e911 | 684 | |
d67dc9e6 | 685 | static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip, |
b8b6a50b | 686 | uint32_t svm_flags) |
f115e911 | 687 | { |
b8b6a50b FB |
688 | int state_saved; |
689 | target_ulong next_eip; | |
690 | ||
691 | state_saved = 0; | |
f115e911 | 692 | if (s->pe && (s->cpl > s->iopl || s->vm86)) { |
773cdfcc | 693 | gen_update_cc_op(s); |
14ce26e7 | 694 | gen_jmp_im(cur_eip); |
b8b6a50b | 695 | state_saved = 1; |
b6abf97d | 696 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 697 | switch (ot) { |
4ba9938c | 698 | case MO_8: |
4a7443be BS |
699 | gen_helper_check_iob(cpu_env, cpu_tmp2_i32); |
700 | break; | |
4ba9938c | 701 | case MO_16: |
4a7443be BS |
702 | gen_helper_check_iow(cpu_env, cpu_tmp2_i32); |
703 | break; | |
4ba9938c | 704 | case MO_32: |
4a7443be BS |
705 | gen_helper_check_iol(cpu_env, cpu_tmp2_i32); |
706 | break; | |
d67dc9e6 RH |
707 | default: |
708 | tcg_abort(); | |
a7812ae4 | 709 | } |
b8b6a50b | 710 | } |
872929aa | 711 | if(s->flags & HF_SVMI_MASK) { |
b8b6a50b | 712 | if (!state_saved) { |
773cdfcc | 713 | gen_update_cc_op(s); |
b8b6a50b | 714 | gen_jmp_im(cur_eip); |
b8b6a50b FB |
715 | } |
716 | svm_flags |= (1 << (4 + ot)); | |
717 | next_eip = s->pc - s->cs_base; | |
b6abf97d | 718 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
052e80d5 BS |
719 | gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32, |
720 | tcg_const_i32(svm_flags), | |
a7812ae4 | 721 | tcg_const_i32(next_eip - cur_eip)); |
f115e911 FB |
722 | } |
723 | } | |
724 | ||
d67dc9e6 | 725 | static inline void gen_movs(DisasContext *s, TCGMemOp ot) |
2c0262af FB |
726 | { |
727 | gen_string_movl_A0_ESI(s); | |
909be183 | 728 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 729 | gen_string_movl_A0_EDI(s); |
fd8ca9f6 | 730 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
6e0d8677 | 731 | gen_op_movl_T0_Dshift(ot); |
1d71ddb1 RH |
732 | gen_op_add_reg_T0(s->aflag, R_ESI); |
733 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
734 | } |
735 | ||
b6abf97d FB |
736 | static void gen_op_update1_cc(void) |
737 | { | |
b6abf97d FB |
738 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
739 | } | |
740 | ||
741 | static void gen_op_update2_cc(void) | |
742 | { | |
743 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
744 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
745 | } | |
746 | ||
988c3eb0 RH |
747 | static void gen_op_update3_cc(TCGv reg) |
748 | { | |
749 | tcg_gen_mov_tl(cpu_cc_src2, reg); | |
750 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
751 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
752 | } | |
753 | ||
b6abf97d FB |
754 | static inline void gen_op_testl_T0_T1_cc(void) |
755 | { | |
b6abf97d FB |
756 | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
757 | } | |
758 | ||
759 | static void gen_op_update_neg_cc(void) | |
760 | { | |
b6abf97d | 761 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
a3251186 RH |
762 | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]); |
763 | tcg_gen_movi_tl(cpu_cc_srcT, 0); | |
b6abf97d FB |
764 | } |
765 | ||
d229edce RH |
766 | /* compute all eflags to cc_src */ |
767 | static void gen_compute_eflags(DisasContext *s) | |
8e1c85e3 | 768 | { |
988c3eb0 | 769 | TCGv zero, dst, src1, src2; |
db9f2597 RH |
770 | int live, dead; |
771 | ||
d229edce RH |
772 | if (s->cc_op == CC_OP_EFLAGS) { |
773 | return; | |
774 | } | |
436ff2d2 RH |
775 | if (s->cc_op == CC_OP_CLR) { |
776 | tcg_gen_movi_tl(cpu_cc_src, CC_Z); | |
777 | set_cc_op(s, CC_OP_EFLAGS); | |
778 | return; | |
779 | } | |
db9f2597 RH |
780 | |
781 | TCGV_UNUSED(zero); | |
782 | dst = cpu_cc_dst; | |
783 | src1 = cpu_cc_src; | |
988c3eb0 | 784 | src2 = cpu_cc_src2; |
db9f2597 RH |
785 | |
786 | /* Take care to not read values that are not live. */ | |
787 | live = cc_op_live[s->cc_op] & ~USES_CC_SRCT; | |
988c3eb0 | 788 | dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2); |
db9f2597 RH |
789 | if (dead) { |
790 | zero = tcg_const_tl(0); | |
791 | if (dead & USES_CC_DST) { | |
792 | dst = zero; | |
793 | } | |
794 | if (dead & USES_CC_SRC) { | |
795 | src1 = zero; | |
796 | } | |
988c3eb0 RH |
797 | if (dead & USES_CC_SRC2) { |
798 | src2 = zero; | |
799 | } | |
db9f2597 RH |
800 | } |
801 | ||
773cdfcc | 802 | gen_update_cc_op(s); |
988c3eb0 | 803 | gen_helper_cc_compute_all(cpu_cc_src, dst, src1, src2, cpu_cc_op); |
d229edce | 804 | set_cc_op(s, CC_OP_EFLAGS); |
db9f2597 RH |
805 | |
806 | if (dead) { | |
807 | tcg_temp_free(zero); | |
808 | } | |
8e1c85e3 FB |
809 | } |
810 | ||
bec93d72 RH |
811 | typedef struct CCPrepare { |
812 | TCGCond cond; | |
813 | TCGv reg; | |
814 | TCGv reg2; | |
815 | target_ulong imm; | |
816 | target_ulong mask; | |
817 | bool use_reg2; | |
818 | bool no_setcond; | |
819 | } CCPrepare; | |
820 | ||
06847f1f | 821 | /* compute eflags.C to reg */ |
bec93d72 | 822 | static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) |
06847f1f RH |
823 | { |
824 | TCGv t0, t1; | |
bec93d72 | 825 | int size, shift; |
06847f1f RH |
826 | |
827 | switch (s->cc_op) { | |
828 | case CC_OP_SUBB ... CC_OP_SUBQ: | |
a3251186 | 829 | /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */ |
06847f1f RH |
830 | size = s->cc_op - CC_OP_SUBB; |
831 | t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
832 | /* If no temporary was used, be careful not to alias t1 and t0. */ | |
833 | t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg; | |
a3251186 | 834 | tcg_gen_mov_tl(t0, cpu_cc_srcT); |
06847f1f RH |
835 | gen_extu(size, t0); |
836 | goto add_sub; | |
837 | ||
838 | case CC_OP_ADDB ... CC_OP_ADDQ: | |
839 | /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ | |
840 | size = s->cc_op - CC_OP_ADDB; | |
841 | t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
842 | t0 = gen_ext_tl(reg, cpu_cc_dst, size, false); | |
843 | add_sub: | |
bec93d72 RH |
844 | return (CCPrepare) { .cond = TCG_COND_LTU, .reg = t0, |
845 | .reg2 = t1, .mask = -1, .use_reg2 = true }; | |
06847f1f | 846 | |
06847f1f | 847 | case CC_OP_LOGICB ... CC_OP_LOGICQ: |
436ff2d2 | 848 | case CC_OP_CLR: |
bec93d72 | 849 | return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; |
06847f1f RH |
850 | |
851 | case CC_OP_INCB ... CC_OP_INCQ: | |
852 | case CC_OP_DECB ... CC_OP_DECQ: | |
bec93d72 RH |
853 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
854 | .mask = -1, .no_setcond = true }; | |
06847f1f RH |
855 | |
856 | case CC_OP_SHLB ... CC_OP_SHLQ: | |
857 | /* (CC_SRC >> (DATA_BITS - 1)) & 1 */ | |
858 | size = s->cc_op - CC_OP_SHLB; | |
bec93d72 RH |
859 | shift = (8 << size) - 1; |
860 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, | |
861 | .mask = (target_ulong)1 << shift }; | |
06847f1f RH |
862 | |
863 | case CC_OP_MULB ... CC_OP_MULQ: | |
bec93d72 RH |
864 | return (CCPrepare) { .cond = TCG_COND_NE, |
865 | .reg = cpu_cc_src, .mask = -1 }; | |
06847f1f | 866 | |
bc4b43dc RH |
867 | case CC_OP_BMILGB ... CC_OP_BMILGQ: |
868 | size = s->cc_op - CC_OP_BMILGB; | |
869 | t0 = gen_ext_tl(reg, cpu_cc_src, size, false); | |
870 | return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 }; | |
871 | ||
cd7f97ca RH |
872 | case CC_OP_ADCX: |
873 | case CC_OP_ADCOX: | |
874 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_dst, | |
875 | .mask = -1, .no_setcond = true }; | |
876 | ||
06847f1f RH |
877 | case CC_OP_EFLAGS: |
878 | case CC_OP_SARB ... CC_OP_SARQ: | |
879 | /* CC_SRC & 1 */ | |
bec93d72 RH |
880 | return (CCPrepare) { .cond = TCG_COND_NE, |
881 | .reg = cpu_cc_src, .mask = CC_C }; | |
06847f1f RH |
882 | |
883 | default: | |
884 | /* The need to compute only C from CC_OP_DYNAMIC is important | |
885 | in efficiently implementing e.g. INC at the start of a TB. */ | |
886 | gen_update_cc_op(s); | |
988c3eb0 RH |
887 | gen_helper_cc_compute_c(reg, cpu_cc_dst, cpu_cc_src, |
888 | cpu_cc_src2, cpu_cc_op); | |
bec93d72 RH |
889 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, |
890 | .mask = -1, .no_setcond = true }; | |
06847f1f RH |
891 | } |
892 | } | |
893 | ||
1608ecca | 894 | /* compute eflags.P to reg */ |
bec93d72 | 895 | static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg) |
1608ecca | 896 | { |
d229edce | 897 | gen_compute_eflags(s); |
bec93d72 RH |
898 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
899 | .mask = CC_P }; | |
1608ecca PB |
900 | } |
901 | ||
902 | /* compute eflags.S to reg */ | |
bec93d72 | 903 | static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg) |
1608ecca | 904 | { |
086c4077 RH |
905 | switch (s->cc_op) { |
906 | case CC_OP_DYNAMIC: | |
907 | gen_compute_eflags(s); | |
908 | /* FALLTHRU */ | |
909 | case CC_OP_EFLAGS: | |
cd7f97ca RH |
910 | case CC_OP_ADCX: |
911 | case CC_OP_ADOX: | |
912 | case CC_OP_ADCOX: | |
bec93d72 RH |
913 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
914 | .mask = CC_S }; | |
436ff2d2 RH |
915 | case CC_OP_CLR: |
916 | return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; | |
086c4077 RH |
917 | default: |
918 | { | |
d67dc9e6 | 919 | TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3; |
086c4077 | 920 | TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true); |
bec93d72 | 921 | return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 }; |
086c4077 | 922 | } |
086c4077 | 923 | } |
1608ecca PB |
924 | } |
925 | ||
926 | /* compute eflags.O to reg */ | |
bec93d72 | 927 | static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg) |
1608ecca | 928 | { |
cd7f97ca RH |
929 | switch (s->cc_op) { |
930 | case CC_OP_ADOX: | |
931 | case CC_OP_ADCOX: | |
932 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src2, | |
933 | .mask = -1, .no_setcond = true }; | |
436ff2d2 RH |
934 | case CC_OP_CLR: |
935 | return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; | |
cd7f97ca RH |
936 | default: |
937 | gen_compute_eflags(s); | |
938 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, | |
939 | .mask = CC_O }; | |
940 | } | |
1608ecca PB |
941 | } |
942 | ||
943 | /* compute eflags.Z to reg */ | |
bec93d72 | 944 | static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) |
1608ecca | 945 | { |
086c4077 RH |
946 | switch (s->cc_op) { |
947 | case CC_OP_DYNAMIC: | |
948 | gen_compute_eflags(s); | |
949 | /* FALLTHRU */ | |
950 | case CC_OP_EFLAGS: | |
cd7f97ca RH |
951 | case CC_OP_ADCX: |
952 | case CC_OP_ADOX: | |
953 | case CC_OP_ADCOX: | |
bec93d72 RH |
954 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
955 | .mask = CC_Z }; | |
436ff2d2 RH |
956 | case CC_OP_CLR: |
957 | return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 }; | |
086c4077 RH |
958 | default: |
959 | { | |
d67dc9e6 | 960 | TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3; |
086c4077 | 961 | TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false); |
bec93d72 | 962 | return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 }; |
086c4077 | 963 | } |
bec93d72 RH |
964 | } |
965 | } | |
966 | ||
c365395e PB |
967 | /* perform a conditional store into register 'reg' according to jump opcode |
968 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
276e6b5f | 969 | static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) |
8e1c85e3 | 970 | { |
d67dc9e6 RH |
971 | int inv, jcc_op, cond; |
972 | TCGMemOp size; | |
276e6b5f | 973 | CCPrepare cc; |
c365395e PB |
974 | TCGv t0; |
975 | ||
976 | inv = b & 1; | |
8e1c85e3 | 977 | jcc_op = (b >> 1) & 7; |
c365395e PB |
978 | |
979 | switch (s->cc_op) { | |
69d1aa31 RH |
980 | case CC_OP_SUBB ... CC_OP_SUBQ: |
981 | /* We optimize relational operators for the cmp/jcc case. */ | |
c365395e PB |
982 | size = s->cc_op - CC_OP_SUBB; |
983 | switch (jcc_op) { | |
984 | case JCC_BE: | |
a3251186 | 985 | tcg_gen_mov_tl(cpu_tmp4, cpu_cc_srcT); |
c365395e PB |
986 | gen_extu(size, cpu_tmp4); |
987 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
276e6b5f RH |
988 | cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4, |
989 | .reg2 = t0, .mask = -1, .use_reg2 = true }; | |
c365395e | 990 | break; |
8e1c85e3 | 991 | |
c365395e | 992 | case JCC_L: |
276e6b5f | 993 | cond = TCG_COND_LT; |
c365395e PB |
994 | goto fast_jcc_l; |
995 | case JCC_LE: | |
276e6b5f | 996 | cond = TCG_COND_LE; |
c365395e | 997 | fast_jcc_l: |
a3251186 | 998 | tcg_gen_mov_tl(cpu_tmp4, cpu_cc_srcT); |
c365395e PB |
999 | gen_exts(size, cpu_tmp4); |
1000 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true); | |
276e6b5f RH |
1001 | cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4, |
1002 | .reg2 = t0, .mask = -1, .use_reg2 = true }; | |
c365395e | 1003 | break; |
8e1c85e3 | 1004 | |
c365395e | 1005 | default: |
8e1c85e3 | 1006 | goto slow_jcc; |
c365395e | 1007 | } |
8e1c85e3 | 1008 | break; |
c365395e | 1009 | |
8e1c85e3 FB |
1010 | default: |
1011 | slow_jcc: | |
69d1aa31 RH |
1012 | /* This actually generates good code for JC, JZ and JS. */ |
1013 | switch (jcc_op) { | |
1014 | case JCC_O: | |
1015 | cc = gen_prepare_eflags_o(s, reg); | |
1016 | break; | |
1017 | case JCC_B: | |
1018 | cc = gen_prepare_eflags_c(s, reg); | |
1019 | break; | |
1020 | case JCC_Z: | |
1021 | cc = gen_prepare_eflags_z(s, reg); | |
1022 | break; | |
1023 | case JCC_BE: | |
1024 | gen_compute_eflags(s); | |
1025 | cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, | |
1026 | .mask = CC_Z | CC_C }; | |
1027 | break; | |
1028 | case JCC_S: | |
1029 | cc = gen_prepare_eflags_s(s, reg); | |
1030 | break; | |
1031 | case JCC_P: | |
1032 | cc = gen_prepare_eflags_p(s, reg); | |
1033 | break; | |
1034 | case JCC_L: | |
1035 | gen_compute_eflags(s); | |
1036 | if (TCGV_EQUAL(reg, cpu_cc_src)) { | |
1037 | reg = cpu_tmp0; | |
1038 | } | |
1039 | tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ | |
1040 | tcg_gen_xor_tl(reg, reg, cpu_cc_src); | |
1041 | cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, | |
1042 | .mask = CC_S }; | |
1043 | break; | |
1044 | default: | |
1045 | case JCC_LE: | |
1046 | gen_compute_eflags(s); | |
1047 | if (TCGV_EQUAL(reg, cpu_cc_src)) { | |
1048 | reg = cpu_tmp0; | |
1049 | } | |
1050 | tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ | |
1051 | tcg_gen_xor_tl(reg, reg, cpu_cc_src); | |
1052 | cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, | |
1053 | .mask = CC_S | CC_Z }; | |
1054 | break; | |
1055 | } | |
c365395e | 1056 | break; |
8e1c85e3 | 1057 | } |
276e6b5f RH |
1058 | |
1059 | if (inv) { | |
1060 | cc.cond = tcg_invert_cond(cc.cond); | |
1061 | } | |
1062 | return cc; | |
8e1c85e3 FB |
1063 | } |
1064 | ||
cc8b6f5b PB |
1065 | static void gen_setcc1(DisasContext *s, int b, TCGv reg) |
1066 | { | |
1067 | CCPrepare cc = gen_prepare_cc(s, b, reg); | |
1068 | ||
1069 | if (cc.no_setcond) { | |
1070 | if (cc.cond == TCG_COND_EQ) { | |
1071 | tcg_gen_xori_tl(reg, cc.reg, 1); | |
1072 | } else { | |
1073 | tcg_gen_mov_tl(reg, cc.reg); | |
1074 | } | |
1075 | return; | |
1076 | } | |
1077 | ||
1078 | if (cc.cond == TCG_COND_NE && !cc.use_reg2 && cc.imm == 0 && | |
1079 | cc.mask != 0 && (cc.mask & (cc.mask - 1)) == 0) { | |
1080 | tcg_gen_shri_tl(reg, cc.reg, ctztl(cc.mask)); | |
1081 | tcg_gen_andi_tl(reg, reg, 1); | |
1082 | return; | |
1083 | } | |
1084 | if (cc.mask != -1) { | |
1085 | tcg_gen_andi_tl(reg, cc.reg, cc.mask); | |
1086 | cc.reg = reg; | |
1087 | } | |
1088 | if (cc.use_reg2) { | |
1089 | tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2); | |
1090 | } else { | |
1091 | tcg_gen_setcondi_tl(cc.cond, reg, cc.reg, cc.imm); | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg) | |
1096 | { | |
1097 | gen_setcc1(s, JCC_B << 1, reg); | |
1098 | } | |
276e6b5f | 1099 | |
8e1c85e3 FB |
1100 | /* generate a conditional jump to label 'l1' according to jump opcode |
1101 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
dc259201 RH |
1102 | static inline void gen_jcc1_noeob(DisasContext *s, int b, int l1) |
1103 | { | |
1104 | CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]); | |
1105 | ||
1106 | if (cc.mask != -1) { | |
1107 | tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask); | |
1108 | cc.reg = cpu_T[0]; | |
1109 | } | |
1110 | if (cc.use_reg2) { | |
1111 | tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); | |
1112 | } else { | |
1113 | tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1); | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | /* Generate a conditional jump to label 'l1' according to jump opcode | |
1118 | value 'b'. In the fast case, T0 is guaranted not to be used. | |
1119 | A translation block must end soon. */ | |
b27fc131 | 1120 | static inline void gen_jcc1(DisasContext *s, int b, int l1) |
8e1c85e3 | 1121 | { |
943131ca | 1122 | CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]); |
8e1c85e3 | 1123 | |
dc259201 | 1124 | gen_update_cc_op(s); |
943131ca PB |
1125 | if (cc.mask != -1) { |
1126 | tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask); | |
1127 | cc.reg = cpu_T[0]; | |
1128 | } | |
dc259201 | 1129 | set_cc_op(s, CC_OP_DYNAMIC); |
943131ca PB |
1130 | if (cc.use_reg2) { |
1131 | tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); | |
1132 | } else { | |
1133 | tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1); | |
8e1c85e3 FB |
1134 | } |
1135 | } | |
1136 | ||
14ce26e7 FB |
1137 | /* XXX: does not work with gdbstub "ice" single step - not a |
1138 | serious problem */ | |
1139 | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) | |
2c0262af | 1140 | { |
14ce26e7 FB |
1141 | int l1, l2; |
1142 | ||
1143 | l1 = gen_new_label(); | |
1144 | l2 = gen_new_label(); | |
1d71ddb1 | 1145 | gen_op_jnz_ecx(s->aflag, l1); |
14ce26e7 FB |
1146 | gen_set_label(l2); |
1147 | gen_jmp_tb(s, next_eip, 1); | |
1148 | gen_set_label(l1); | |
1149 | return l2; | |
2c0262af FB |
1150 | } |
1151 | ||
d67dc9e6 | 1152 | static inline void gen_stos(DisasContext *s, TCGMemOp ot) |
2c0262af | 1153 | { |
4ba9938c | 1154 | gen_op_mov_TN_reg(MO_32, 0, R_EAX); |
2c0262af | 1155 | gen_string_movl_A0_EDI(s); |
fd8ca9f6 | 1156 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
6e0d8677 | 1157 | gen_op_movl_T0_Dshift(ot); |
1d71ddb1 | 1158 | gen_op_add_reg_T0(s->aflag, R_EDI); |
2c0262af FB |
1159 | } |
1160 | ||
d67dc9e6 | 1161 | static inline void gen_lods(DisasContext *s, TCGMemOp ot) |
2c0262af FB |
1162 | { |
1163 | gen_string_movl_A0_ESI(s); | |
909be183 | 1164 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
57fec1fe | 1165 | gen_op_mov_reg_T0(ot, R_EAX); |
6e0d8677 | 1166 | gen_op_movl_T0_Dshift(ot); |
1d71ddb1 | 1167 | gen_op_add_reg_T0(s->aflag, R_ESI); |
2c0262af FB |
1168 | } |
1169 | ||
d67dc9e6 | 1170 | static inline void gen_scas(DisasContext *s, TCGMemOp ot) |
2c0262af | 1171 | { |
2c0262af | 1172 | gen_string_movl_A0_EDI(s); |
0f712e10 | 1173 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
63633fe6 | 1174 | gen_op(s, OP_CMPL, ot, R_EAX); |
6e0d8677 | 1175 | gen_op_movl_T0_Dshift(ot); |
1d71ddb1 | 1176 | gen_op_add_reg_T0(s->aflag, R_EDI); |
2c0262af FB |
1177 | } |
1178 | ||
d67dc9e6 | 1179 | static inline void gen_cmps(DisasContext *s, TCGMemOp ot) |
2c0262af | 1180 | { |
2c0262af | 1181 | gen_string_movl_A0_EDI(s); |
0f712e10 | 1182 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
63633fe6 RH |
1183 | gen_string_movl_A0_ESI(s); |
1184 | gen_op(s, OP_CMPL, ot, OR_TMP0); | |
6e0d8677 | 1185 | gen_op_movl_T0_Dshift(ot); |
1d71ddb1 RH |
1186 | gen_op_add_reg_T0(s->aflag, R_ESI); |
1187 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1188 | } |
1189 | ||
d67dc9e6 | 1190 | static inline void gen_ins(DisasContext *s, TCGMemOp ot) |
2c0262af | 1191 | { |
2e70f6ef PB |
1192 | if (use_icount) |
1193 | gen_io_start(); | |
2c0262af | 1194 | gen_string_movl_A0_EDI(s); |
6e0d8677 FB |
1195 | /* Note: we must do this dummy write first to be restartable in |
1196 | case of page fault. */ | |
97212c88 | 1197 | tcg_gen_movi_tl(cpu_T[0], 0); |
fd8ca9f6 | 1198 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
24b9c00f | 1199 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]); |
b6abf97d | 1200 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); |
a7812ae4 | 1201 | gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); |
fd8ca9f6 | 1202 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
6e0d8677 | 1203 | gen_op_movl_T0_Dshift(ot); |
1d71ddb1 | 1204 | gen_op_add_reg_T0(s->aflag, R_EDI); |
2e70f6ef PB |
1205 | if (use_icount) |
1206 | gen_io_end(); | |
2c0262af FB |
1207 | } |
1208 | ||
d67dc9e6 | 1209 | static inline void gen_outs(DisasContext *s, TCGMemOp ot) |
2c0262af | 1210 | { |
2e70f6ef PB |
1211 | if (use_icount) |
1212 | gen_io_start(); | |
2c0262af | 1213 | gen_string_movl_A0_ESI(s); |
909be183 | 1214 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
b8b6a50b | 1215 | |
24b9c00f | 1216 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]); |
b6abf97d FB |
1217 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); |
1218 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); | |
a7812ae4 | 1219 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
b8b6a50b | 1220 | |
6e0d8677 | 1221 | gen_op_movl_T0_Dshift(ot); |
1d71ddb1 | 1222 | gen_op_add_reg_T0(s->aflag, R_ESI); |
2e70f6ef PB |
1223 | if (use_icount) |
1224 | gen_io_end(); | |
2c0262af FB |
1225 | } |
1226 | ||
1227 | /* same method as Valgrind : we generate jumps to current or next | |
1228 | instruction */ | |
1229 | #define GEN_REPZ(op) \ | |
d67dc9e6 | 1230 | static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \ |
14ce26e7 | 1231 | target_ulong cur_eip, target_ulong next_eip) \ |
2c0262af | 1232 | { \ |
14ce26e7 | 1233 | int l2;\ |
2c0262af | 1234 | gen_update_cc_op(s); \ |
14ce26e7 | 1235 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1236 | gen_ ## op(s, ot); \ |
1d71ddb1 | 1237 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af FB |
1238 | /* a loop would cause two single step exceptions if ECX = 1 \ |
1239 | before rep string_insn */ \ | |
1240 | if (!s->jmp_opt) \ | |
1d71ddb1 | 1241 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1242 | gen_jmp(s, cur_eip); \ |
1243 | } | |
1244 | ||
1245 | #define GEN_REPZ2(op) \ | |
d67dc9e6 | 1246 | static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \ |
14ce26e7 FB |
1247 | target_ulong cur_eip, \ |
1248 | target_ulong next_eip, \ | |
2c0262af FB |
1249 | int nz) \ |
1250 | { \ | |
14ce26e7 | 1251 | int l2;\ |
2c0262af | 1252 | gen_update_cc_op(s); \ |
14ce26e7 | 1253 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1254 | gen_ ## op(s, ot); \ |
1d71ddb1 | 1255 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
773cdfcc | 1256 | gen_update_cc_op(s); \ |
b27fc131 | 1257 | gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \ |
2c0262af | 1258 | if (!s->jmp_opt) \ |
1d71ddb1 | 1259 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1260 | gen_jmp(s, cur_eip); \ |
1261 | } | |
1262 | ||
1263 | GEN_REPZ(movs) | |
1264 | GEN_REPZ(stos) | |
1265 | GEN_REPZ(lods) | |
1266 | GEN_REPZ(ins) | |
1267 | GEN_REPZ(outs) | |
1268 | GEN_REPZ2(scas) | |
1269 | GEN_REPZ2(cmps) | |
1270 | ||
a7812ae4 PB |
1271 | static void gen_helper_fp_arith_ST0_FT0(int op) |
1272 | { | |
1273 | switch (op) { | |
d3eb5eae BS |
1274 | case 0: |
1275 | gen_helper_fadd_ST0_FT0(cpu_env); | |
1276 | break; | |
1277 | case 1: | |
1278 | gen_helper_fmul_ST0_FT0(cpu_env); | |
1279 | break; | |
1280 | case 2: | |
1281 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1282 | break; | |
1283 | case 3: | |
1284 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1285 | break; | |
1286 | case 4: | |
1287 | gen_helper_fsub_ST0_FT0(cpu_env); | |
1288 | break; | |
1289 | case 5: | |
1290 | gen_helper_fsubr_ST0_FT0(cpu_env); | |
1291 | break; | |
1292 | case 6: | |
1293 | gen_helper_fdiv_ST0_FT0(cpu_env); | |
1294 | break; | |
1295 | case 7: | |
1296 | gen_helper_fdivr_ST0_FT0(cpu_env); | |
1297 | break; | |
a7812ae4 PB |
1298 | } |
1299 | } | |
2c0262af FB |
1300 | |
1301 | /* NOTE the exception in "r" op ordering */ | |
a7812ae4 PB |
1302 | static void gen_helper_fp_arith_STN_ST0(int op, int opreg) |
1303 | { | |
1304 | TCGv_i32 tmp = tcg_const_i32(opreg); | |
1305 | switch (op) { | |
d3eb5eae BS |
1306 | case 0: |
1307 | gen_helper_fadd_STN_ST0(cpu_env, tmp); | |
1308 | break; | |
1309 | case 1: | |
1310 | gen_helper_fmul_STN_ST0(cpu_env, tmp); | |
1311 | break; | |
1312 | case 4: | |
1313 | gen_helper_fsubr_STN_ST0(cpu_env, tmp); | |
1314 | break; | |
1315 | case 5: | |
1316 | gen_helper_fsub_STN_ST0(cpu_env, tmp); | |
1317 | break; | |
1318 | case 6: | |
1319 | gen_helper_fdivr_STN_ST0(cpu_env, tmp); | |
1320 | break; | |
1321 | case 7: | |
1322 | gen_helper_fdiv_STN_ST0(cpu_env, tmp); | |
1323 | break; | |
a7812ae4 PB |
1324 | } |
1325 | } | |
2c0262af FB |
1326 | |
1327 | /* if d == OR_TMP0, it means memory operand (address in A0) */ | |
d67dc9e6 | 1328 | static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) |
2c0262af | 1329 | { |
2c0262af | 1330 | if (d != OR_TMP0) { |
57fec1fe | 1331 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1332 | } else { |
909be183 | 1333 | gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0); |
2c0262af FB |
1334 | } |
1335 | switch(op) { | |
1336 | case OP_ADCL: | |
cc8b6f5b | 1337 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1338 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1339 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
d4faa3e0 | 1340 | gen_op_st_rm_T0_A0(s1, ot, d); |
988c3eb0 RH |
1341 | gen_op_update3_cc(cpu_tmp4); |
1342 | set_cc_op(s1, CC_OP_ADCB + ot); | |
cad3a37d | 1343 | break; |
2c0262af | 1344 | case OP_SBBL: |
cc8b6f5b | 1345 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1346 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1347 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
d4faa3e0 | 1348 | gen_op_st_rm_T0_A0(s1, ot, d); |
988c3eb0 RH |
1349 | gen_op_update3_cc(cpu_tmp4); |
1350 | set_cc_op(s1, CC_OP_SBBB + ot); | |
cad3a37d | 1351 | break; |
2c0262af FB |
1352 | case OP_ADDL: |
1353 | gen_op_addl_T0_T1(); | |
d4faa3e0 | 1354 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1355 | gen_op_update2_cc(); |
3ca51d07 | 1356 | set_cc_op(s1, CC_OP_ADDB + ot); |
2c0262af FB |
1357 | break; |
1358 | case OP_SUBL: | |
a3251186 | 1359 | tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]); |
57fec1fe | 1360 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
d4faa3e0 | 1361 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1362 | gen_op_update2_cc(); |
3ca51d07 | 1363 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1364 | break; |
1365 | default: | |
1366 | case OP_ANDL: | |
57fec1fe | 1367 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
d4faa3e0 | 1368 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1369 | gen_op_update1_cc(); |
3ca51d07 | 1370 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1371 | break; |
2c0262af | 1372 | case OP_ORL: |
57fec1fe | 1373 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
d4faa3e0 | 1374 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1375 | gen_op_update1_cc(); |
3ca51d07 | 1376 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1377 | break; |
2c0262af | 1378 | case OP_XORL: |
57fec1fe | 1379 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
d4faa3e0 | 1380 | gen_op_st_rm_T0_A0(s1, ot, d); |
cad3a37d | 1381 | gen_op_update1_cc(); |
3ca51d07 | 1382 | set_cc_op(s1, CC_OP_LOGICB + ot); |
2c0262af FB |
1383 | break; |
1384 | case OP_CMPL: | |
63633fe6 | 1385 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); |
a3251186 | 1386 | tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]); |
63633fe6 | 1387 | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
3ca51d07 | 1388 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1389 | break; |
1390 | } | |
b6abf97d FB |
1391 | } |
1392 | ||
2c0262af | 1393 | /* if d == OR_TMP0, it means memory operand (address in A0) */ |
d67dc9e6 | 1394 | static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) |
2c0262af | 1395 | { |
909be183 | 1396 | if (d != OR_TMP0) { |
57fec1fe | 1397 | gen_op_mov_TN_reg(ot, 0, d); |
909be183 RH |
1398 | } else { |
1399 | gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0); | |
1400 | } | |
cc8b6f5b | 1401 | gen_compute_eflags_c(s1, cpu_cc_src); |
2c0262af | 1402 | if (c > 0) { |
b6abf97d | 1403 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
3ca51d07 | 1404 | set_cc_op(s1, CC_OP_INCB + ot); |
2c0262af | 1405 | } else { |
b6abf97d | 1406 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
3ca51d07 | 1407 | set_cc_op(s1, CC_OP_DECB + ot); |
2c0262af | 1408 | } |
d4faa3e0 | 1409 | gen_op_st_rm_T0_A0(s1, ot, d); |
cd31fefa | 1410 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
2c0262af FB |
1411 | } |
1412 | ||
d67dc9e6 RH |
1413 | static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result, |
1414 | TCGv shm1, TCGv count, bool is_right) | |
f437d0a3 RH |
1415 | { |
1416 | TCGv_i32 z32, s32, oldop; | |
1417 | TCGv z_tl; | |
1418 | ||
1419 | /* Store the results into the CC variables. If we know that the | |
1420 | variable must be dead, store unconditionally. Otherwise we'll | |
1421 | need to not disrupt the current contents. */ | |
1422 | z_tl = tcg_const_tl(0); | |
1423 | if (cc_op_live[s->cc_op] & USES_CC_DST) { | |
1424 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl, | |
1425 | result, cpu_cc_dst); | |
1426 | } else { | |
1427 | tcg_gen_mov_tl(cpu_cc_dst, result); | |
1428 | } | |
1429 | if (cc_op_live[s->cc_op] & USES_CC_SRC) { | |
1430 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_src, count, z_tl, | |
1431 | shm1, cpu_cc_src); | |
1432 | } else { | |
1433 | tcg_gen_mov_tl(cpu_cc_src, shm1); | |
1434 | } | |
1435 | tcg_temp_free(z_tl); | |
1436 | ||
1437 | /* Get the two potential CC_OP values into temporaries. */ | |
1438 | tcg_gen_movi_i32(cpu_tmp2_i32, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot); | |
1439 | if (s->cc_op == CC_OP_DYNAMIC) { | |
1440 | oldop = cpu_cc_op; | |
1441 | } else { | |
1442 | tcg_gen_movi_i32(cpu_tmp3_i32, s->cc_op); | |
1443 | oldop = cpu_tmp3_i32; | |
1444 | } | |
1445 | ||
1446 | /* Conditionally store the CC_OP value. */ | |
1447 | z32 = tcg_const_i32(0); | |
1448 | s32 = tcg_temp_new_i32(); | |
1449 | tcg_gen_trunc_tl_i32(s32, count); | |
1450 | tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, cpu_tmp2_i32, oldop); | |
1451 | tcg_temp_free_i32(z32); | |
1452 | tcg_temp_free_i32(s32); | |
1453 | ||
1454 | /* The CC_OP value is no longer predictable. */ | |
1455 | set_cc_op(s, CC_OP_DYNAMIC); | |
1456 | } | |
1457 | ||
d67dc9e6 | 1458 | static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1, |
b6abf97d | 1459 | int is_right, int is_arith) |
2c0262af | 1460 | { |
4ba9938c | 1461 | target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f); |
3b46e624 | 1462 | |
b6abf97d | 1463 | /* load */ |
82786041 | 1464 | if (op1 == OR_TMP0) { |
909be183 | 1465 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
82786041 | 1466 | } else { |
b6abf97d | 1467 | gen_op_mov_TN_reg(ot, 0, op1); |
82786041 | 1468 | } |
b6abf97d | 1469 | |
a41f62f5 RH |
1470 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); |
1471 | tcg_gen_subi_tl(cpu_tmp0, cpu_T[1], 1); | |
b6abf97d FB |
1472 | |
1473 | if (is_right) { | |
1474 | if (is_arith) { | |
f484d386 | 1475 | gen_exts(ot, cpu_T[0]); |
a41f62f5 RH |
1476 | tcg_gen_sar_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); |
1477 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
b6abf97d | 1478 | } else { |
cad3a37d | 1479 | gen_extu(ot, cpu_T[0]); |
a41f62f5 RH |
1480 | tcg_gen_shr_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); |
1481 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
b6abf97d FB |
1482 | } |
1483 | } else { | |
a41f62f5 RH |
1484 | tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); |
1485 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
b6abf97d FB |
1486 | } |
1487 | ||
1488 | /* store */ | |
d4faa3e0 | 1489 | gen_op_st_rm_T0_A0(s, ot, op1); |
82786041 | 1490 | |
f437d0a3 | 1491 | gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, cpu_T[1], is_right); |
b6abf97d FB |
1492 | } |
1493 | ||
d67dc9e6 | 1494 | static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, |
c1c37968 FB |
1495 | int is_right, int is_arith) |
1496 | { | |
4ba9938c | 1497 | int mask = (ot == MO_64 ? 0x3f : 0x1f); |
c1c37968 FB |
1498 | |
1499 | /* load */ | |
1500 | if (op1 == OR_TMP0) | |
909be183 | 1501 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
c1c37968 FB |
1502 | else |
1503 | gen_op_mov_TN_reg(ot, 0, op1); | |
1504 | ||
1505 | op2 &= mask; | |
1506 | if (op2 != 0) { | |
1507 | if (is_right) { | |
1508 | if (is_arith) { | |
1509 | gen_exts(ot, cpu_T[0]); | |
2a449d14 | 1510 | tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1511 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
1512 | } else { | |
1513 | gen_extu(ot, cpu_T[0]); | |
2a449d14 | 1514 | tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1515 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
1516 | } | |
1517 | } else { | |
2a449d14 | 1518 | tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1519 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
1520 | } | |
1521 | } | |
1522 | ||
1523 | /* store */ | |
d4faa3e0 RH |
1524 | gen_op_st_rm_T0_A0(s, ot, op1); |
1525 | ||
c1c37968 FB |
1526 | /* update eflags if non zero shift */ |
1527 | if (op2 != 0) { | |
2a449d14 | 1528 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
c1c37968 | 1529 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
3ca51d07 | 1530 | set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot); |
c1c37968 FB |
1531 | } |
1532 | } | |
1533 | ||
b6abf97d FB |
1534 | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1535 | { | |
1536 | if (arg2 >= 0) | |
1537 | tcg_gen_shli_tl(ret, arg1, arg2); | |
1538 | else | |
1539 | tcg_gen_shri_tl(ret, arg1, -arg2); | |
1540 | } | |
1541 | ||
d67dc9e6 | 1542 | static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right) |
b6abf97d | 1543 | { |
4ba9938c | 1544 | target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f); |
34d80a55 | 1545 | TCGv_i32 t0, t1; |
b6abf97d FB |
1546 | |
1547 | /* load */ | |
1e4840bf | 1548 | if (op1 == OR_TMP0) { |
909be183 | 1549 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
1e4840bf | 1550 | } else { |
34d80a55 | 1551 | gen_op_mov_TN_reg(ot, 0, op1); |
1e4840bf | 1552 | } |
b6abf97d | 1553 | |
34d80a55 | 1554 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); |
b6abf97d | 1555 | |
34d80a55 | 1556 | switch (ot) { |
4ba9938c | 1557 | case MO_8: |
34d80a55 RH |
1558 | /* Replicate the 8-bit input so that a 32-bit rotate works. */ |
1559 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); | |
1560 | tcg_gen_muli_tl(cpu_T[0], cpu_T[0], 0x01010101); | |
1561 | goto do_long; | |
4ba9938c | 1562 | case MO_16: |
34d80a55 RH |
1563 | /* Replicate the 16-bit input so that a 32-bit rotate works. */ |
1564 | tcg_gen_deposit_tl(cpu_T[0], cpu_T[0], cpu_T[0], 16, 16); | |
1565 | goto do_long; | |
1566 | do_long: | |
1567 | #ifdef TARGET_X86_64 | |
4ba9938c | 1568 | case MO_32: |
34d80a55 RH |
1569 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
1570 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); | |
1571 | if (is_right) { | |
1572 | tcg_gen_rotr_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); | |
1573 | } else { | |
1574 | tcg_gen_rotl_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); | |
1575 | } | |
1576 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); | |
1577 | break; | |
1578 | #endif | |
1579 | default: | |
1580 | if (is_right) { | |
1581 | tcg_gen_rotr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1582 | } else { | |
1583 | tcg_gen_rotl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1584 | } | |
1585 | break; | |
b6abf97d | 1586 | } |
b6abf97d | 1587 | |
b6abf97d | 1588 | /* store */ |
d4faa3e0 | 1589 | gen_op_st_rm_T0_A0(s, ot, op1); |
b6abf97d | 1590 | |
34d80a55 RH |
1591 | /* We'll need the flags computed into CC_SRC. */ |
1592 | gen_compute_eflags(s); | |
b6abf97d | 1593 | |
34d80a55 RH |
1594 | /* The value that was "rotated out" is now present at the other end |
1595 | of the word. Compute C into CC_DST and O into CC_SRC2. Note that | |
1596 | since we've computed the flags into CC_SRC, these variables are | |
1597 | currently dead. */ | |
b6abf97d | 1598 | if (is_right) { |
34d80a55 RH |
1599 | tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1); |
1600 | tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask); | |
089305ac | 1601 | tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1); |
34d80a55 RH |
1602 | } else { |
1603 | tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask); | |
1604 | tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1); | |
b6abf97d | 1605 | } |
34d80a55 RH |
1606 | tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1); |
1607 | tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst); | |
1608 | ||
1609 | /* Now conditionally store the new CC_OP value. If the shift count | |
1610 | is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live. | |
1611 | Otherwise reuse CC_OP_ADCOX which have the C and O flags split out | |
1612 | exactly as we computed above. */ | |
1613 | t0 = tcg_const_i32(0); | |
1614 | t1 = tcg_temp_new_i32(); | |
1615 | tcg_gen_trunc_tl_i32(t1, cpu_T[1]); | |
1616 | tcg_gen_movi_i32(cpu_tmp2_i32, CC_OP_ADCOX); | |
1617 | tcg_gen_movi_i32(cpu_tmp3_i32, CC_OP_EFLAGS); | |
1618 | tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, t1, t0, | |
1619 | cpu_tmp2_i32, cpu_tmp3_i32); | |
1620 | tcg_temp_free_i32(t0); | |
1621 | tcg_temp_free_i32(t1); | |
1622 | ||
1623 | /* The CC_OP value is no longer predictable. */ | |
1624 | set_cc_op(s, CC_OP_DYNAMIC); | |
b6abf97d FB |
1625 | } |
1626 | ||
d67dc9e6 | 1627 | static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, |
8cd6345d | 1628 | int is_right) |
1629 | { | |
4ba9938c | 1630 | int mask = (ot == MO_64 ? 0x3f : 0x1f); |
34d80a55 | 1631 | int shift; |
8cd6345d | 1632 | |
1633 | /* load */ | |
1634 | if (op1 == OR_TMP0) { | |
909be183 | 1635 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
8cd6345d | 1636 | } else { |
34d80a55 | 1637 | gen_op_mov_TN_reg(ot, 0, op1); |
8cd6345d | 1638 | } |
1639 | ||
8cd6345d | 1640 | op2 &= mask; |
8cd6345d | 1641 | if (op2 != 0) { |
34d80a55 RH |
1642 | switch (ot) { |
1643 | #ifdef TARGET_X86_64 | |
4ba9938c | 1644 | case MO_32: |
34d80a55 RH |
1645 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
1646 | if (is_right) { | |
1647 | tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2); | |
1648 | } else { | |
1649 | tcg_gen_rotli_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2); | |
1650 | } | |
1651 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); | |
1652 | break; | |
1653 | #endif | |
1654 | default: | |
1655 | if (is_right) { | |
1656 | tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], op2); | |
1657 | } else { | |
1658 | tcg_gen_rotli_tl(cpu_T[0], cpu_T[0], op2); | |
1659 | } | |
1660 | break; | |
4ba9938c | 1661 | case MO_8: |
34d80a55 RH |
1662 | mask = 7; |
1663 | goto do_shifts; | |
4ba9938c | 1664 | case MO_16: |
34d80a55 RH |
1665 | mask = 15; |
1666 | do_shifts: | |
1667 | shift = op2 & mask; | |
1668 | if (is_right) { | |
1669 | shift = mask + 1 - shift; | |
1670 | } | |
1671 | gen_extu(ot, cpu_T[0]); | |
1672 | tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], shift); | |
1673 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], mask + 1 - shift); | |
1674 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
1675 | break; | |
8cd6345d | 1676 | } |
8cd6345d | 1677 | } |
1678 | ||
1679 | /* store */ | |
d4faa3e0 | 1680 | gen_op_st_rm_T0_A0(s, ot, op1); |
8cd6345d | 1681 | |
1682 | if (op2 != 0) { | |
34d80a55 | 1683 | /* Compute the flags into CC_SRC. */ |
d229edce | 1684 | gen_compute_eflags(s); |
0ff6addd | 1685 | |
34d80a55 RH |
1686 | /* The value that was "rotated out" is now present at the other end |
1687 | of the word. Compute C into CC_DST and O into CC_SRC2. Note that | |
1688 | since we've computed the flags into CC_SRC, these variables are | |
1689 | currently dead. */ | |
8cd6345d | 1690 | if (is_right) { |
34d80a55 RH |
1691 | tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1); |
1692 | tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask); | |
38ebb396 | 1693 | tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1); |
34d80a55 RH |
1694 | } else { |
1695 | tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask); | |
1696 | tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1); | |
8cd6345d | 1697 | } |
34d80a55 RH |
1698 | tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1); |
1699 | tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst); | |
1700 | set_cc_op(s, CC_OP_ADCOX); | |
8cd6345d | 1701 | } |
8cd6345d | 1702 | } |
1703 | ||
b6abf97d | 1704 | /* XXX: add faster immediate = 1 case */ |
d67dc9e6 | 1705 | static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1, |
b6abf97d FB |
1706 | int is_right) |
1707 | { | |
d229edce | 1708 | gen_compute_eflags(s); |
c7b3c873 | 1709 | assert(s->cc_op == CC_OP_EFLAGS); |
b6abf97d FB |
1710 | |
1711 | /* load */ | |
1712 | if (op1 == OR_TMP0) | |
909be183 | 1713 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
b6abf97d FB |
1714 | else |
1715 | gen_op_mov_TN_reg(ot, 0, op1); | |
1716 | ||
a7812ae4 PB |
1717 | if (is_right) { |
1718 | switch (ot) { | |
4ba9938c | 1719 | case MO_8: |
7923057b BS |
1720 | gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1721 | break; | |
4ba9938c | 1722 | case MO_16: |
7923057b BS |
1723 | gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1724 | break; | |
4ba9938c | 1725 | case MO_32: |
7923057b BS |
1726 | gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1727 | break; | |
a7812ae4 | 1728 | #ifdef TARGET_X86_64 |
4ba9938c | 1729 | case MO_64: |
7923057b BS |
1730 | gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1731 | break; | |
a7812ae4 | 1732 | #endif |
d67dc9e6 RH |
1733 | default: |
1734 | tcg_abort(); | |
a7812ae4 PB |
1735 | } |
1736 | } else { | |
1737 | switch (ot) { | |
4ba9938c | 1738 | case MO_8: |
7923057b BS |
1739 | gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1740 | break; | |
4ba9938c | 1741 | case MO_16: |
7923057b BS |
1742 | gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1743 | break; | |
4ba9938c | 1744 | case MO_32: |
7923057b BS |
1745 | gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1746 | break; | |
a7812ae4 | 1747 | #ifdef TARGET_X86_64 |
4ba9938c | 1748 | case MO_64: |
7923057b BS |
1749 | gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1750 | break; | |
a7812ae4 | 1751 | #endif |
d67dc9e6 RH |
1752 | default: |
1753 | tcg_abort(); | |
a7812ae4 PB |
1754 | } |
1755 | } | |
b6abf97d | 1756 | /* store */ |
d4faa3e0 | 1757 | gen_op_st_rm_T0_A0(s, ot, op1); |
b6abf97d FB |
1758 | } |
1759 | ||
1760 | /* XXX: add faster immediate case */ | |
d67dc9e6 | 1761 | static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1, |
f437d0a3 | 1762 | bool is_right, TCGv count_in) |
b6abf97d | 1763 | { |
4ba9938c | 1764 | target_ulong mask = (ot == MO_64 ? 63 : 31); |
f437d0a3 | 1765 | TCGv count; |
b6abf97d FB |
1766 | |
1767 | /* load */ | |
1e4840bf | 1768 | if (op1 == OR_TMP0) { |
909be183 | 1769 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
1e4840bf | 1770 | } else { |
f437d0a3 | 1771 | gen_op_mov_TN_reg(ot, 0, op1); |
1e4840bf | 1772 | } |
b6abf97d | 1773 | |
f437d0a3 RH |
1774 | count = tcg_temp_new(); |
1775 | tcg_gen_andi_tl(count, count_in, mask); | |
1e4840bf | 1776 | |
f437d0a3 | 1777 | switch (ot) { |
4ba9938c | 1778 | case MO_16: |
f437d0a3 RH |
1779 | /* Note: we implement the Intel behaviour for shift count > 16. |
1780 | This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A | |
1781 | portion by constructing it as a 32-bit value. */ | |
b6abf97d | 1782 | if (is_right) { |
f437d0a3 RH |
1783 | tcg_gen_deposit_tl(cpu_tmp0, cpu_T[0], cpu_T[1], 16, 16); |
1784 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); | |
1785 | tcg_gen_mov_tl(cpu_T[0], cpu_tmp0); | |
b6abf97d | 1786 | } else { |
f437d0a3 | 1787 | tcg_gen_deposit_tl(cpu_T[1], cpu_T[0], cpu_T[1], 16, 16); |
b6abf97d | 1788 | } |
f437d0a3 RH |
1789 | /* FALLTHRU */ |
1790 | #ifdef TARGET_X86_64 | |
4ba9938c | 1791 | case MO_32: |
f437d0a3 RH |
1792 | /* Concatenate the two 32-bit values and use a 64-bit shift. */ |
1793 | tcg_gen_subi_tl(cpu_tmp0, count, 1); | |
b6abf97d | 1794 | if (is_right) { |
f437d0a3 RH |
1795 | tcg_gen_concat_tl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
1796 | tcg_gen_shr_i64(cpu_tmp0, cpu_T[0], cpu_tmp0); | |
1797 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], count); | |
1798 | } else { | |
1799 | tcg_gen_concat_tl_i64(cpu_T[0], cpu_T[1], cpu_T[0]); | |
1800 | tcg_gen_shl_i64(cpu_tmp0, cpu_T[0], cpu_tmp0); | |
1801 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], count); | |
1802 | tcg_gen_shri_i64(cpu_tmp0, cpu_tmp0, 32); | |
1803 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], 32); | |
1804 | } | |
1805 | break; | |
1806 | #endif | |
1807 | default: | |
1808 | tcg_gen_subi_tl(cpu_tmp0, count, 1); | |
1809 | if (is_right) { | |
1810 | tcg_gen_shr_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); | |
b6abf97d | 1811 | |
f437d0a3 RH |
1812 | tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count); |
1813 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], count); | |
1814 | tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp4); | |
b6abf97d | 1815 | } else { |
f437d0a3 | 1816 | tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0); |
4ba9938c | 1817 | if (ot == MO_16) { |
f437d0a3 RH |
1818 | /* Only needed if count > 16, for Intel behaviour. */ |
1819 | tcg_gen_subfi_tl(cpu_tmp4, 33, count); | |
1820 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[1], cpu_tmp4); | |
1821 | tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, cpu_tmp4); | |
1822 | } | |
1823 | ||
1824 | tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count); | |
1825 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], count); | |
1826 | tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp4); | |
b6abf97d | 1827 | } |
f437d0a3 RH |
1828 | tcg_gen_movi_tl(cpu_tmp4, 0); |
1829 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[1], count, cpu_tmp4, | |
1830 | cpu_tmp4, cpu_T[1]); | |
1831 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1832 | break; | |
b6abf97d | 1833 | } |
b6abf97d | 1834 | |
b6abf97d | 1835 | /* store */ |
d4faa3e0 | 1836 | gen_op_st_rm_T0_A0(s, ot, op1); |
1e4840bf | 1837 | |
f437d0a3 RH |
1838 | gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, count, is_right); |
1839 | tcg_temp_free(count); | |
b6abf97d FB |
1840 | } |
1841 | ||
d67dc9e6 | 1842 | static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s) |
b6abf97d FB |
1843 | { |
1844 | if (s != OR_TMP1) | |
1845 | gen_op_mov_TN_reg(ot, 1, s); | |
1846 | switch(op) { | |
1847 | case OP_ROL: | |
1848 | gen_rot_rm_T1(s1, ot, d, 0); | |
1849 | break; | |
1850 | case OP_ROR: | |
1851 | gen_rot_rm_T1(s1, ot, d, 1); | |
1852 | break; | |
1853 | case OP_SHL: | |
1854 | case OP_SHL1: | |
1855 | gen_shift_rm_T1(s1, ot, d, 0, 0); | |
1856 | break; | |
1857 | case OP_SHR: | |
1858 | gen_shift_rm_T1(s1, ot, d, 1, 0); | |
1859 | break; | |
1860 | case OP_SAR: | |
1861 | gen_shift_rm_T1(s1, ot, d, 1, 1); | |
1862 | break; | |
1863 | case OP_RCL: | |
1864 | gen_rotc_rm_T1(s1, ot, d, 0); | |
1865 | break; | |
1866 | case OP_RCR: | |
1867 | gen_rotc_rm_T1(s1, ot, d, 1); | |
1868 | break; | |
1869 | } | |
2c0262af FB |
1870 | } |
1871 | ||
d67dc9e6 | 1872 | static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c) |
2c0262af | 1873 | { |
c1c37968 | 1874 | switch(op) { |
8cd6345d | 1875 | case OP_ROL: |
1876 | gen_rot_rm_im(s1, ot, d, c, 0); | |
1877 | break; | |
1878 | case OP_ROR: | |
1879 | gen_rot_rm_im(s1, ot, d, c, 1); | |
1880 | break; | |
c1c37968 FB |
1881 | case OP_SHL: |
1882 | case OP_SHL1: | |
1883 | gen_shift_rm_im(s1, ot, d, c, 0, 0); | |
1884 | break; | |
1885 | case OP_SHR: | |
1886 | gen_shift_rm_im(s1, ot, d, c, 1, 0); | |
1887 | break; | |
1888 | case OP_SAR: | |
1889 | gen_shift_rm_im(s1, ot, d, c, 1, 1); | |
1890 | break; | |
1891 | default: | |
1892 | /* currently not optimized */ | |
0ae657b1 | 1893 | tcg_gen_movi_tl(cpu_T[1], c); |
c1c37968 FB |
1894 | gen_shift(s1, op, ot, d, OR_TMP1); |
1895 | break; | |
1896 | } | |
2c0262af FB |
1897 | } |
1898 | ||
4eeb3939 | 1899 | static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm) |
2c0262af | 1900 | { |
14ce26e7 | 1901 | target_long disp; |
2c0262af | 1902 | int havesib; |
14ce26e7 | 1903 | int base; |
2c0262af FB |
1904 | int index; |
1905 | int scale; | |
2c0262af | 1906 | int mod, rm, code, override, must_add_seg; |
7865eec4 | 1907 | TCGv sum; |
2c0262af FB |
1908 | |
1909 | override = s->override; | |
1910 | must_add_seg = s->addseg; | |
1911 | if (override >= 0) | |
1912 | must_add_seg = 1; | |
1913 | mod = (modrm >> 6) & 3; | |
1914 | rm = modrm & 7; | |
1915 | ||
1d71ddb1 RH |
1916 | switch (s->aflag) { |
1917 | case MO_64: | |
1918 | case MO_32: | |
2c0262af FB |
1919 | havesib = 0; |
1920 | base = rm; | |
7865eec4 | 1921 | index = -1; |
2c0262af | 1922 | scale = 0; |
3b46e624 | 1923 | |
2c0262af FB |
1924 | if (base == 4) { |
1925 | havesib = 1; | |
0af10c86 | 1926 | code = cpu_ldub_code(env, s->pc++); |
2c0262af | 1927 | scale = (code >> 6) & 3; |
14ce26e7 | 1928 | index = ((code >> 3) & 7) | REX_X(s); |
7865eec4 RH |
1929 | if (index == 4) { |
1930 | index = -1; /* no index */ | |
1931 | } | |
14ce26e7 | 1932 | base = (code & 7); |
2c0262af | 1933 | } |
14ce26e7 | 1934 | base |= REX_B(s); |
2c0262af FB |
1935 | |
1936 | switch (mod) { | |
1937 | case 0: | |
14ce26e7 | 1938 | if ((base & 7) == 5) { |
2c0262af | 1939 | base = -1; |
0af10c86 | 1940 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af | 1941 | s->pc += 4; |
14ce26e7 FB |
1942 | if (CODE64(s) && !havesib) { |
1943 | disp += s->pc + s->rip_offset; | |
1944 | } | |
2c0262af FB |
1945 | } else { |
1946 | disp = 0; | |
1947 | } | |
1948 | break; | |
1949 | case 1: | |
0af10c86 | 1950 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
1951 | break; |
1952 | default: | |
1953 | case 2: | |
0af10c86 | 1954 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af FB |
1955 | s->pc += 4; |
1956 | break; | |
1957 | } | |
3b46e624 | 1958 | |
7865eec4 RH |
1959 | /* For correct popl handling with esp. */ |
1960 | if (base == R_ESP && s->popl_esp_hack) { | |
1961 | disp += s->popl_esp_hack; | |
1962 | } | |
1963 | ||
1964 | /* Compute the address, with a minimum number of TCG ops. */ | |
1965 | TCGV_UNUSED(sum); | |
1966 | if (index >= 0) { | |
1967 | if (scale == 0) { | |
1968 | sum = cpu_regs[index]; | |
1969 | } else { | |
1970 | tcg_gen_shli_tl(cpu_A0, cpu_regs[index], scale); | |
1971 | sum = cpu_A0; | |
14ce26e7 | 1972 | } |
7865eec4 RH |
1973 | if (base >= 0) { |
1974 | tcg_gen_add_tl(cpu_A0, sum, cpu_regs[base]); | |
1975 | sum = cpu_A0; | |
14ce26e7 | 1976 | } |
7865eec4 RH |
1977 | } else if (base >= 0) { |
1978 | sum = cpu_regs[base]; | |
2c0262af | 1979 | } |
7865eec4 RH |
1980 | if (TCGV_IS_UNUSED(sum)) { |
1981 | tcg_gen_movi_tl(cpu_A0, disp); | |
1982 | } else { | |
1983 | tcg_gen_addi_tl(cpu_A0, sum, disp); | |
2c0262af | 1984 | } |
7865eec4 | 1985 | |
2c0262af FB |
1986 | if (must_add_seg) { |
1987 | if (override < 0) { | |
7865eec4 | 1988 | if (base == R_EBP || base == R_ESP) { |
2c0262af | 1989 | override = R_SS; |
7865eec4 | 1990 | } else { |
2c0262af | 1991 | override = R_DS; |
7865eec4 | 1992 | } |
2c0262af | 1993 | } |
7865eec4 RH |
1994 | |
1995 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, | |
1996 | offsetof(CPUX86State, segs[override].base)); | |
1997 | if (CODE64(s)) { | |
1d71ddb1 | 1998 | if (s->aflag == MO_32) { |
7865eec4 RH |
1999 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); |
2000 | } | |
2001 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
4eeb3939 | 2002 | return; |
14ce26e7 | 2003 | } |
7865eec4 RH |
2004 | |
2005 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
2006 | } | |
2007 | ||
1d71ddb1 | 2008 | if (s->aflag == MO_32) { |
7865eec4 | 2009 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); |
2c0262af | 2010 | } |
1d71ddb1 RH |
2011 | break; |
2012 | ||
2013 | case MO_16: | |
2c0262af FB |
2014 | switch (mod) { |
2015 | case 0: | |
2016 | if (rm == 6) { | |
0af10c86 | 2017 | disp = cpu_lduw_code(env, s->pc); |
2c0262af | 2018 | s->pc += 2; |
3250cff8 | 2019 | tcg_gen_movi_tl(cpu_A0, disp); |
2c0262af FB |
2020 | rm = 0; /* avoid SS override */ |
2021 | goto no_rm; | |
2022 | } else { | |
2023 | disp = 0; | |
2024 | } | |
2025 | break; | |
2026 | case 1: | |
0af10c86 | 2027 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
2028 | break; |
2029 | default: | |
2030 | case 2: | |
7effd625 | 2031 | disp = (int16_t)cpu_lduw_code(env, s->pc); |
2c0262af FB |
2032 | s->pc += 2; |
2033 | break; | |
2034 | } | |
7effd625 RH |
2035 | |
2036 | sum = cpu_A0; | |
2037 | switch (rm) { | |
2c0262af | 2038 | case 0: |
7effd625 | 2039 | tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_ESI]); |
2c0262af FB |
2040 | break; |
2041 | case 1: | |
7effd625 | 2042 | tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_EDI]); |
2c0262af FB |
2043 | break; |
2044 | case 2: | |
7effd625 | 2045 | tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_ESI]); |
2c0262af FB |
2046 | break; |
2047 | case 3: | |
7effd625 | 2048 | tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_EDI]); |
2c0262af FB |
2049 | break; |
2050 | case 4: | |
7effd625 | 2051 | sum = cpu_regs[R_ESI]; |
2c0262af FB |
2052 | break; |
2053 | case 5: | |
7effd625 | 2054 | sum = cpu_regs[R_EDI]; |
2c0262af FB |
2055 | break; |
2056 | case 6: | |
7effd625 | 2057 | sum = cpu_regs[R_EBP]; |
2c0262af FB |
2058 | break; |
2059 | default: | |
2060 | case 7: | |
7effd625 | 2061 | sum = cpu_regs[R_EBX]; |
2c0262af FB |
2062 | break; |
2063 | } | |
7effd625 | 2064 | tcg_gen_addi_tl(cpu_A0, sum, disp); |
a7e5c7de | 2065 | tcg_gen_ext16u_tl(cpu_A0, cpu_A0); |
2c0262af FB |
2066 | no_rm: |
2067 | if (must_add_seg) { | |
2068 | if (override < 0) { | |
7effd625 | 2069 | if (rm == 2 || rm == 3 || rm == 6) { |
2c0262af | 2070 | override = R_SS; |
7effd625 | 2071 | } else { |
2c0262af | 2072 | override = R_DS; |
7effd625 | 2073 | } |
2c0262af | 2074 | } |
7162ab21 | 2075 | gen_op_addl_A0_seg(s, override); |
2c0262af | 2076 | } |
1d71ddb1 RH |
2077 | break; |
2078 | ||
2079 | default: | |
2080 | tcg_abort(); | |
2c0262af | 2081 | } |
2c0262af FB |
2082 | } |
2083 | ||
0af10c86 | 2084 | static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) |
e17a36ce FB |
2085 | { |
2086 | int mod, rm, base, code; | |
2087 | ||
2088 | mod = (modrm >> 6) & 3; | |
2089 | if (mod == 3) | |
2090 | return; | |
2091 | rm = modrm & 7; | |
2092 | ||
1d71ddb1 RH |
2093 | switch (s->aflag) { |
2094 | case MO_64: | |
2095 | case MO_32: | |
e17a36ce | 2096 | base = rm; |
3b46e624 | 2097 | |
e17a36ce | 2098 | if (base == 4) { |
0af10c86 | 2099 | code = cpu_ldub_code(env, s->pc++); |
e17a36ce FB |
2100 | base = (code & 7); |
2101 | } | |
3b46e624 | 2102 | |
e17a36ce FB |
2103 | switch (mod) { |
2104 | case 0: | |
2105 | if (base == 5) { | |
2106 | s->pc += 4; | |
2107 | } | |
2108 | break; | |
2109 | case 1: | |
2110 | s->pc++; | |
2111 | break; | |
2112 | default: | |
2113 | case 2: | |
2114 | s->pc += 4; | |
2115 | break; | |
2116 | } | |
1d71ddb1 RH |
2117 | break; |
2118 | ||
2119 | case MO_16: | |
e17a36ce FB |
2120 | switch (mod) { |
2121 | case 0: | |
2122 | if (rm == 6) { | |
2123 | s->pc += 2; | |
2124 | } | |
2125 | break; | |
2126 | case 1: | |
2127 | s->pc++; | |
2128 | break; | |
2129 | default: | |
2130 | case 2: | |
2131 | s->pc += 2; | |
2132 | break; | |
2133 | } | |
1d71ddb1 RH |
2134 | break; |
2135 | ||
2136 | default: | |
2137 | tcg_abort(); | |
e17a36ce FB |
2138 | } |
2139 | } | |
2140 | ||
664e0f19 FB |
2141 | /* used for LEA and MOV AX, mem */ |
2142 | static void gen_add_A0_ds_seg(DisasContext *s) | |
2143 | { | |
2144 | int override, must_add_seg; | |
2145 | must_add_seg = s->addseg; | |
2146 | override = R_DS; | |
2147 | if (s->override >= 0) { | |
2148 | override = s->override; | |
2149 | must_add_seg = 1; | |
664e0f19 FB |
2150 | } |
2151 | if (must_add_seg) { | |
8f091a59 FB |
2152 | #ifdef TARGET_X86_64 |
2153 | if (CODE64(s)) { | |
57fec1fe | 2154 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2155 | } else |
8f091a59 FB |
2156 | #endif |
2157 | { | |
7162ab21 | 2158 | gen_op_addl_A0_seg(s, override); |
8f091a59 | 2159 | } |
664e0f19 FB |
2160 | } |
2161 | } | |
2162 | ||
222a3336 | 2163 | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == |
2c0262af | 2164 | OR_TMP0 */ |
0af10c86 | 2165 | static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, |
d67dc9e6 | 2166 | TCGMemOp ot, int reg, int is_store) |
2c0262af | 2167 | { |
4eeb3939 | 2168 | int mod, rm; |
2c0262af FB |
2169 | |
2170 | mod = (modrm >> 6) & 3; | |
14ce26e7 | 2171 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
2172 | if (mod == 3) { |
2173 | if (is_store) { | |
2174 | if (reg != OR_TMP0) | |
57fec1fe FB |
2175 | gen_op_mov_TN_reg(ot, 0, reg); |
2176 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 2177 | } else { |
57fec1fe | 2178 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 2179 | if (reg != OR_TMP0) |
57fec1fe | 2180 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2181 | } |
2182 | } else { | |
4eeb3939 | 2183 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
2184 | if (is_store) { |
2185 | if (reg != OR_TMP0) | |
57fec1fe | 2186 | gen_op_mov_TN_reg(ot, 0, reg); |
fd8ca9f6 | 2187 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 2188 | } else { |
909be183 | 2189 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 2190 | if (reg != OR_TMP0) |
57fec1fe | 2191 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2192 | } |
2193 | } | |
2194 | } | |
2195 | ||
d67dc9e6 | 2196 | static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot) |
2c0262af FB |
2197 | { |
2198 | uint32_t ret; | |
2199 | ||
d67dc9e6 | 2200 | switch (ot) { |
4ba9938c | 2201 | case MO_8: |
0af10c86 | 2202 | ret = cpu_ldub_code(env, s->pc); |
2c0262af FB |
2203 | s->pc++; |
2204 | break; | |
4ba9938c | 2205 | case MO_16: |
0af10c86 | 2206 | ret = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2207 | s->pc += 2; |
2208 | break; | |
4ba9938c | 2209 | case MO_32: |
d67dc9e6 RH |
2210 | #ifdef TARGET_X86_64 |
2211 | case MO_64: | |
2212 | #endif | |
0af10c86 | 2213 | ret = cpu_ldl_code(env, s->pc); |
2c0262af FB |
2214 | s->pc += 4; |
2215 | break; | |
d67dc9e6 RH |
2216 | default: |
2217 | tcg_abort(); | |
2c0262af FB |
2218 | } |
2219 | return ret; | |
2220 | } | |
2221 | ||
d67dc9e6 | 2222 | static inline int insn_const_size(TCGMemOp ot) |
14ce26e7 | 2223 | { |
4ba9938c | 2224 | if (ot <= MO_32) { |
14ce26e7 | 2225 | return 1 << ot; |
4ba9938c | 2226 | } else { |
14ce26e7 | 2227 | return 4; |
4ba9938c | 2228 | } |
14ce26e7 FB |
2229 | } |
2230 | ||
6e256c93 FB |
2231 | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2232 | { | |
2233 | TranslationBlock *tb; | |
2234 | target_ulong pc; | |
2235 | ||
2236 | pc = s->cs_base + eip; | |
2237 | tb = s->tb; | |
2238 | /* NOTE: we handle the case where the TB spans two pages here */ | |
2239 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) || | |
2240 | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { | |
2241 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 2242 | tcg_gen_goto_tb(tb_num); |
6e256c93 | 2243 | gen_jmp_im(eip); |
8cfd0495 | 2244 | tcg_gen_exit_tb((uintptr_t)tb + tb_num); |
6e256c93 FB |
2245 | } else { |
2246 | /* jump to another page: currently not optimized */ | |
2247 | gen_jmp_im(eip); | |
2248 | gen_eob(s); | |
2249 | } | |
2250 | } | |
2251 | ||
5fafdf24 | 2252 | static inline void gen_jcc(DisasContext *s, int b, |
14ce26e7 | 2253 | target_ulong val, target_ulong next_eip) |
2c0262af | 2254 | { |
b27fc131 | 2255 | int l1, l2; |
3b46e624 | 2256 | |
2c0262af | 2257 | if (s->jmp_opt) { |
14ce26e7 | 2258 | l1 = gen_new_label(); |
b27fc131 | 2259 | gen_jcc1(s, b, l1); |
dc259201 | 2260 | |
6e256c93 | 2261 | gen_goto_tb(s, 0, next_eip); |
14ce26e7 FB |
2262 | |
2263 | gen_set_label(l1); | |
6e256c93 | 2264 | gen_goto_tb(s, 1, val); |
5779406a | 2265 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2266 | } else { |
14ce26e7 FB |
2267 | l1 = gen_new_label(); |
2268 | l2 = gen_new_label(); | |
b27fc131 | 2269 | gen_jcc1(s, b, l1); |
8e1c85e3 | 2270 | |
14ce26e7 | 2271 | gen_jmp_im(next_eip); |
8e1c85e3 FB |
2272 | tcg_gen_br(l2); |
2273 | ||
14ce26e7 FB |
2274 | gen_set_label(l1); |
2275 | gen_jmp_im(val); | |
2276 | gen_set_label(l2); | |
2c0262af FB |
2277 | gen_eob(s); |
2278 | } | |
2279 | } | |
2280 | ||
d67dc9e6 | 2281 | static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b, |
f32d3781 PB |
2282 | int modrm, int reg) |
2283 | { | |
57eb0cc8 | 2284 | CCPrepare cc; |
f32d3781 | 2285 | |
57eb0cc8 | 2286 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
f32d3781 | 2287 | |
57eb0cc8 RH |
2288 | cc = gen_prepare_cc(s, b, cpu_T[1]); |
2289 | if (cc.mask != -1) { | |
2290 | TCGv t0 = tcg_temp_new(); | |
2291 | tcg_gen_andi_tl(t0, cc.reg, cc.mask); | |
2292 | cc.reg = t0; | |
2293 | } | |
2294 | if (!cc.use_reg2) { | |
2295 | cc.reg2 = tcg_const_tl(cc.imm); | |
f32d3781 PB |
2296 | } |
2297 | ||
57eb0cc8 RH |
2298 | tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2, |
2299 | cpu_T[0], cpu_regs[reg]); | |
2300 | gen_op_mov_reg_T0(ot, reg); | |
2301 | ||
2302 | if (cc.mask != -1) { | |
2303 | tcg_temp_free(cc.reg); | |
2304 | } | |
2305 | if (!cc.use_reg2) { | |
2306 | tcg_temp_free(cc.reg2); | |
2307 | } | |
f32d3781 PB |
2308 | } |
2309 | ||
3bd7da9e FB |
2310 | static inline void gen_op_movl_T0_seg(int seg_reg) |
2311 | { | |
2312 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, | |
2313 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2314 | } | |
2315 | ||
2316 | static inline void gen_op_movl_seg_T0_vm(int seg_reg) | |
2317 | { | |
2318 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
2319 | tcg_gen_st32_tl(cpu_T[0], cpu_env, | |
2320 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2321 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); | |
2322 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
2323 | offsetof(CPUX86State,segs[seg_reg].base)); | |
2324 | } | |
2325 | ||
2c0262af FB |
2326 | /* move T0 to seg_reg and compute if the CPU state may change. Never |
2327 | call this function with seg_reg == R_CS */ | |
14ce26e7 | 2328 | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2c0262af | 2329 | { |
3415a4dd FB |
2330 | if (s->pe && !s->vm86) { |
2331 | /* XXX: optimize by finding processor state dynamically */ | |
773cdfcc | 2332 | gen_update_cc_op(s); |
14ce26e7 | 2333 | gen_jmp_im(cur_eip); |
b6abf97d | 2334 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 2335 | gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32); |
dc196a57 FB |
2336 | /* abort translation because the addseg value may change or |
2337 | because ss32 may change. For R_SS, translation must always | |
2338 | stop as a special handling must be done to disable hardware | |
2339 | interrupts for the next instruction */ | |
2340 | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) | |
5779406a | 2341 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2342 | } else { |
3bd7da9e | 2343 | gen_op_movl_seg_T0_vm(seg_reg); |
dc196a57 | 2344 | if (seg_reg == R_SS) |
5779406a | 2345 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2346 | } |
2c0262af FB |
2347 | } |
2348 | ||
0573fbfc TS |
2349 | static inline int svm_is_rep(int prefixes) |
2350 | { | |
2351 | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); | |
2352 | } | |
2353 | ||
872929aa | 2354 | static inline void |
0573fbfc | 2355 | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
b8b6a50b | 2356 | uint32_t type, uint64_t param) |
0573fbfc | 2357 | { |
872929aa FB |
2358 | /* no SVM activated; fast case */ |
2359 | if (likely(!(s->flags & HF_SVMI_MASK))) | |
2360 | return; | |
773cdfcc | 2361 | gen_update_cc_op(s); |
872929aa | 2362 | gen_jmp_im(pc_start - s->cs_base); |
052e80d5 | 2363 | gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), |
a7812ae4 | 2364 | tcg_const_i64(param)); |
0573fbfc TS |
2365 | } |
2366 | ||
872929aa | 2367 | static inline void |
0573fbfc TS |
2368 | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2369 | { | |
872929aa | 2370 | gen_svm_check_intercept_param(s, pc_start, type, 0); |
0573fbfc TS |
2371 | } |
2372 | ||
4f31916f FB |
2373 | static inline void gen_stack_update(DisasContext *s, int addend) |
2374 | { | |
14ce26e7 FB |
2375 | #ifdef TARGET_X86_64 |
2376 | if (CODE64(s)) { | |
d3f4bbe3 | 2377 | gen_op_add_reg_im(MO_64, R_ESP, addend); |
14ce26e7 FB |
2378 | } else |
2379 | #endif | |
4f31916f | 2380 | if (s->ss32) { |
d3f4bbe3 | 2381 | gen_op_add_reg_im(MO_32, R_ESP, addend); |
4f31916f | 2382 | } else { |
d3f4bbe3 | 2383 | gen_op_add_reg_im(MO_16, R_ESP, addend); |
4f31916f FB |
2384 | } |
2385 | } | |
2386 | ||
2c0262af FB |
2387 | /* generate a push. It depends on ss32, addseg and dflag */ |
2388 | static void gen_push_T0(DisasContext *s) | |
2389 | { | |
14ce26e7 FB |
2390 | #ifdef TARGET_X86_64 |
2391 | if (CODE64(s)) { | |
57fec1fe | 2392 | gen_op_movq_A0_reg(R_ESP); |
ab4e4aec | 2393 | if (s->dflag != MO_16) { |
57fec1fe | 2394 | gen_op_addq_A0_im(-8); |
fd8ca9f6 | 2395 | gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0); |
8f091a59 | 2396 | } else { |
57fec1fe | 2397 | gen_op_addq_A0_im(-2); |
fd8ca9f6 | 2398 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
8f091a59 | 2399 | } |
6f17675a | 2400 | gen_op_mov_reg_A0(MO_64, R_ESP); |
5fafdf24 | 2401 | } else |
14ce26e7 FB |
2402 | #endif |
2403 | { | |
57fec1fe | 2404 | gen_op_movl_A0_reg(R_ESP); |
ab4e4aec | 2405 | gen_op_addl_A0_im(-1 << s->dflag); |
14ce26e7 FB |
2406 | if (s->ss32) { |
2407 | if (s->addseg) { | |
bbf662ee | 2408 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2409 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2410 | } |
2411 | } else { | |
a7e5c7de | 2412 | tcg_gen_ext16u_tl(cpu_A0, cpu_A0); |
bbf662ee | 2413 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2414 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2415 | } |
ab4e4aec | 2416 | gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0); |
14ce26e7 | 2417 | if (s->ss32 && !s->addseg) |
6f17675a | 2418 | gen_op_mov_reg_A0(MO_32, R_ESP); |
14ce26e7 | 2419 | else |
6f17675a | 2420 | gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); |
2c0262af FB |
2421 | } |
2422 | } | |
2423 | ||
4f31916f FB |
2424 | /* generate a push. It depends on ss32, addseg and dflag */ |
2425 | /* slower version for T1, only used for call Ev */ | |
2426 | static void gen_push_T1(DisasContext *s) | |
2c0262af | 2427 | { |
14ce26e7 FB |
2428 | #ifdef TARGET_X86_64 |
2429 | if (CODE64(s)) { | |
57fec1fe | 2430 | gen_op_movq_A0_reg(R_ESP); |
ab4e4aec | 2431 | if (s->dflag != MO_16) { |
57fec1fe | 2432 | gen_op_addq_A0_im(-8); |
b5afc104 | 2433 | gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0); |
8f091a59 | 2434 | } else { |
57fec1fe | 2435 | gen_op_addq_A0_im(-2); |
ee3138da | 2436 | gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0); |
8f091a59 | 2437 | } |
6f17675a | 2438 | gen_op_mov_reg_A0(MO_64, R_ESP); |
5fafdf24 | 2439 | } else |
14ce26e7 FB |
2440 | #endif |
2441 | { | |
57fec1fe | 2442 | gen_op_movl_A0_reg(R_ESP); |
ab4e4aec | 2443 | gen_op_addl_A0_im(-1 << s->dflag); |
14ce26e7 FB |
2444 | if (s->ss32) { |
2445 | if (s->addseg) { | |
7162ab21 | 2446 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2447 | } |
2448 | } else { | |
a7e5c7de | 2449 | tcg_gen_ext16u_tl(cpu_A0, cpu_A0); |
7162ab21 | 2450 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2451 | } |
ab4e4aec | 2452 | gen_op_st_v(s, s->dflag, cpu_T[1], cpu_A0); |
3b46e624 | 2453 | |
14ce26e7 | 2454 | if (s->ss32 && !s->addseg) |
6f17675a | 2455 | gen_op_mov_reg_A0(MO_32, R_ESP); |
14ce26e7 | 2456 | else |
ab4e4aec | 2457 | gen_stack_update(s, -1 << s->dflag); |
2c0262af FB |
2458 | } |
2459 | } | |
2460 | ||
4f31916f FB |
2461 | /* two step pop is necessary for precise exceptions */ |
2462 | static void gen_pop_T0(DisasContext *s) | |
2c0262af | 2463 | { |
14ce26e7 FB |
2464 | #ifdef TARGET_X86_64 |
2465 | if (CODE64(s)) { | |
57fec1fe | 2466 | gen_op_movq_A0_reg(R_ESP); |
ab4e4aec | 2467 | gen_op_ld_v(s, mo_pushpop(s, s->dflag), cpu_T[0], cpu_A0); |
5fafdf24 | 2468 | } else |
14ce26e7 FB |
2469 | #endif |
2470 | { | |
57fec1fe | 2471 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 FB |
2472 | if (s->ss32) { |
2473 | if (s->addseg) | |
7162ab21 | 2474 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 | 2475 | } else { |
a7e5c7de | 2476 | tcg_gen_ext16u_tl(cpu_A0, cpu_A0); |
7162ab21 | 2477 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 | 2478 | } |
ab4e4aec | 2479 | gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0); |
2c0262af FB |
2480 | } |
2481 | } | |
2482 | ||
2483 | static void gen_pop_update(DisasContext *s) | |
2484 | { | |
ab4e4aec | 2485 | gen_stack_update(s, 1 << mo_pushpop(s, s->dflag)); |
2c0262af FB |
2486 | } |
2487 | ||
2488 | static void gen_stack_A0(DisasContext *s) | |
2489 | { | |
57fec1fe | 2490 | gen_op_movl_A0_reg(R_ESP); |
2c0262af | 2491 | if (!s->ss32) |
a7e5c7de | 2492 | tcg_gen_ext16u_tl(cpu_A0, cpu_A0); |
bbf662ee | 2493 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2494 | if (s->addseg) |
7162ab21 | 2495 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2496 | } |
2497 | ||
2498 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2499 | static void gen_pusha(DisasContext *s) | |
2500 | { | |
2501 | int i; | |
57fec1fe | 2502 | gen_op_movl_A0_reg(R_ESP); |
ab4e4aec | 2503 | gen_op_addl_A0_im(-8 << s->dflag); |
2c0262af | 2504 | if (!s->ss32) |
a7e5c7de | 2505 | tcg_gen_ext16u_tl(cpu_A0, cpu_A0); |
bbf662ee | 2506 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2507 | if (s->addseg) |
7162ab21 | 2508 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2509 | for(i = 0;i < 8; i++) { |
4ba9938c | 2510 | gen_op_mov_TN_reg(MO_32, 0, 7 - i); |
ab4e4aec RH |
2511 | gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0); |
2512 | gen_op_addl_A0_im(1 << s->dflag); | |
2c0262af | 2513 | } |
4ba9938c | 2514 | gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); |
2c0262af FB |
2515 | } |
2516 | ||
2517 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2518 | static void gen_popa(DisasContext *s) | |
2519 | { | |
2520 | int i; | |
57fec1fe | 2521 | gen_op_movl_A0_reg(R_ESP); |
2c0262af | 2522 | if (!s->ss32) |
a7e5c7de | 2523 | tcg_gen_ext16u_tl(cpu_A0, cpu_A0); |
bbf662ee | 2524 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
ab4e4aec | 2525 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 8 << s->dflag); |
2c0262af | 2526 | if (s->addseg) |
7162ab21 | 2527 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2528 | for(i = 0;i < 8; i++) { |
2529 | /* ESP is not reloaded */ | |
2530 | if (i != 3) { | |
ab4e4aec RH |
2531 | gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0); |
2532 | gen_op_mov_reg_T0(s->dflag, 7 - i); | |
2c0262af | 2533 | } |
ab4e4aec | 2534 | gen_op_addl_A0_im(1 << s->dflag); |
2c0262af | 2535 | } |
4ba9938c | 2536 | gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); |
2c0262af FB |
2537 | } |
2538 | ||
2c0262af FB |
2539 | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2540 | { | |
ab4e4aec RH |
2541 | TCGMemOp ot = mo_pushpop(s, s->dflag); |
2542 | int opsize = 1 << ot; | |
2c0262af | 2543 | |
2c0262af | 2544 | level &= 0x1f; |
8f091a59 FB |
2545 | #ifdef TARGET_X86_64 |
2546 | if (CODE64(s)) { | |
57fec1fe | 2547 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 | 2548 | gen_op_addq_A0_im(-opsize); |
bbf662ee | 2549 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 FB |
2550 | |
2551 | /* push bp */ | |
4ba9938c | 2552 | gen_op_mov_TN_reg(MO_32, 0, R_EBP); |
fd8ca9f6 | 2553 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
8f091a59 | 2554 | if (level) { |
b5b38f61 | 2555 | /* XXX: must save state */ |
2999a0b2 | 2556 | gen_helper_enter64_level(cpu_env, tcg_const_i32(level), |
4ba9938c | 2557 | tcg_const_i32((ot == MO_64)), |
a7812ae4 | 2558 | cpu_T[1]); |
8f091a59 | 2559 | } |
57fec1fe | 2560 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2561 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
4ba9938c | 2562 | gen_op_mov_reg_T1(MO_64, R_ESP); |
5fafdf24 | 2563 | } else |
8f091a59 FB |
2564 | #endif |
2565 | { | |
57fec1fe | 2566 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 FB |
2567 | gen_op_addl_A0_im(-opsize); |
2568 | if (!s->ss32) | |
a7e5c7de | 2569 | tcg_gen_ext16u_tl(cpu_A0, cpu_A0); |
bbf662ee | 2570 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 | 2571 | if (s->addseg) |
7162ab21 | 2572 | gen_op_addl_A0_seg(s, R_SS); |
8f091a59 | 2573 | /* push bp */ |
4ba9938c | 2574 | gen_op_mov_TN_reg(MO_32, 0, R_EBP); |
fd8ca9f6 | 2575 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
8f091a59 | 2576 | if (level) { |
b5b38f61 | 2577 | /* XXX: must save state */ |
2999a0b2 | 2578 | gen_helper_enter_level(cpu_env, tcg_const_i32(level), |
ab4e4aec | 2579 | tcg_const_i32(s->dflag - 1), |
a7812ae4 | 2580 | cpu_T[1]); |
8f091a59 | 2581 | } |
57fec1fe | 2582 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2583 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
4ba9938c | 2584 | gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); |
2c0262af | 2585 | } |
2c0262af FB |
2586 | } |
2587 | ||
14ce26e7 | 2588 | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2c0262af | 2589 | { |
773cdfcc | 2590 | gen_update_cc_op(s); |
14ce26e7 | 2591 | gen_jmp_im(cur_eip); |
77b2bc2c | 2592 | gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); |
5779406a | 2593 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2594 | } |
2595 | ||
2596 | /* an interrupt is different from an exception because of the | |
7f75ffd3 | 2597 | privilege checks */ |
5fafdf24 | 2598 | static void gen_interrupt(DisasContext *s, int intno, |
14ce26e7 | 2599 | target_ulong cur_eip, target_ulong next_eip) |
2c0262af | 2600 | { |
773cdfcc | 2601 | gen_update_cc_op(s); |
14ce26e7 | 2602 | gen_jmp_im(cur_eip); |
77b2bc2c | 2603 | gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), |
a7812ae4 | 2604 | tcg_const_i32(next_eip - cur_eip)); |
5779406a | 2605 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2606 | } |
2607 | ||
14ce26e7 | 2608 | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2c0262af | 2609 | { |
773cdfcc | 2610 | gen_update_cc_op(s); |
14ce26e7 | 2611 | gen_jmp_im(cur_eip); |
4a7443be | 2612 | gen_helper_debug(cpu_env); |
5779406a | 2613 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2614 | } |
2615 | ||
2616 | /* generate a generic end of block. Trace exception is also generated | |
2617 | if needed */ | |
2618 | static void gen_eob(DisasContext *s) | |
2619 | { | |
773cdfcc | 2620 | gen_update_cc_op(s); |
a2cc3b24 | 2621 | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { |
f0967a1a | 2622 | gen_helper_reset_inhibit_irq(cpu_env); |
a2cc3b24 | 2623 | } |
a2397807 | 2624 | if (s->tb->flags & HF_RF_MASK) { |
f0967a1a | 2625 | gen_helper_reset_rf(cpu_env); |
a2397807 | 2626 | } |
34865134 | 2627 | if (s->singlestep_enabled) { |
4a7443be | 2628 | gen_helper_debug(cpu_env); |
34865134 | 2629 | } else if (s->tf) { |
4a7443be | 2630 | gen_helper_single_step(cpu_env); |
2c0262af | 2631 | } else { |
57fec1fe | 2632 | tcg_gen_exit_tb(0); |
2c0262af | 2633 | } |
5779406a | 2634 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2635 | } |
2636 | ||
2637 | /* generate a jump to eip. No segment change must happen before as a | |
2638 | direct call to the next block may occur */ | |
14ce26e7 | 2639 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2c0262af | 2640 | { |
a3251186 RH |
2641 | gen_update_cc_op(s); |
2642 | set_cc_op(s, CC_OP_DYNAMIC); | |
2c0262af | 2643 | if (s->jmp_opt) { |
6e256c93 | 2644 | gen_goto_tb(s, tb_num, eip); |
5779406a | 2645 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2646 | } else { |
14ce26e7 | 2647 | gen_jmp_im(eip); |
2c0262af FB |
2648 | gen_eob(s); |
2649 | } | |
2650 | } | |
2651 | ||
14ce26e7 FB |
2652 | static void gen_jmp(DisasContext *s, target_ulong eip) |
2653 | { | |
2654 | gen_jmp_tb(s, eip, 0); | |
2655 | } | |
2656 | ||
323d1876 | 2657 | static inline void gen_ldq_env_A0(DisasContext *s, int offset) |
8686c490 | 2658 | { |
3c5f4116 | 2659 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); |
b6abf97d | 2660 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); |
8686c490 | 2661 | } |
664e0f19 | 2662 | |
323d1876 | 2663 | static inline void gen_stq_env_A0(DisasContext *s, int offset) |
8686c490 | 2664 | { |
b6abf97d | 2665 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
3523e4bd | 2666 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); |
8686c490 | 2667 | } |
664e0f19 | 2668 | |
323d1876 | 2669 | static inline void gen_ldo_env_A0(DisasContext *s, int offset) |
8686c490 | 2670 | { |
5c42a7cd | 2671 | int mem_index = s->mem_index; |
3c5f4116 | 2672 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ); |
b6abf97d | 2673 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
8686c490 | 2674 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
3c5f4116 | 2675 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ); |
b6abf97d | 2676 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
8686c490 | 2677 | } |
14ce26e7 | 2678 | |
323d1876 | 2679 | static inline void gen_sto_env_A0(DisasContext *s, int offset) |
8686c490 | 2680 | { |
5c42a7cd | 2681 | int mem_index = s->mem_index; |
b6abf97d | 2682 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
3523e4bd | 2683 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ); |
8686c490 | 2684 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d | 2685 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
3523e4bd | 2686 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ); |
8686c490 | 2687 | } |
14ce26e7 | 2688 | |
5af45186 FB |
2689 | static inline void gen_op_movo(int d_offset, int s_offset) |
2690 | { | |
b6abf97d FB |
2691 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2692 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
2693 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8); | |
2694 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8); | |
5af45186 FB |
2695 | } |
2696 | ||
2697 | static inline void gen_op_movq(int d_offset, int s_offset) | |
2698 | { | |
b6abf97d FB |
2699 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2700 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 FB |
2701 | } |
2702 | ||
2703 | static inline void gen_op_movl(int d_offset, int s_offset) | |
2704 | { | |
b6abf97d FB |
2705 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2706 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); | |
5af45186 FB |
2707 | } |
2708 | ||
2709 | static inline void gen_op_movq_env_0(int d_offset) | |
2710 | { | |
b6abf97d FB |
2711 | tcg_gen_movi_i64(cpu_tmp1_i64, 0); |
2712 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 | 2713 | } |
664e0f19 | 2714 | |
d3eb5eae BS |
2715 | typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg); |
2716 | typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg); | |
2717 | typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val); | |
2718 | typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val); | |
2719 | typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b); | |
2720 | typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, | |
2721 | TCGv_i32 val); | |
c4baa050 | 2722 | typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val); |
d3eb5eae BS |
2723 | typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, |
2724 | TCGv val); | |
c4baa050 | 2725 | |
5af45186 FB |
2726 | #define SSE_SPECIAL ((void *)1) |
2727 | #define SSE_DUMMY ((void *)2) | |
664e0f19 | 2728 | |
a7812ae4 PB |
2729 | #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } |
2730 | #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ | |
2731 | gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } | |
5af45186 | 2732 | |
d3eb5eae | 2733 | static const SSEFunc_0_epp sse_op_table1[256][4] = { |
a35f3ec7 AJ |
2734 | /* 3DNow! extensions */ |
2735 | [0x0e] = { SSE_DUMMY }, /* femms */ | |
2736 | [0x0f] = { SSE_DUMMY }, /* pf... */ | |
664e0f19 FB |
2737 | /* pure SSE operations */ |
2738 | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
2739 | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
465e9838 | 2740 | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
664e0f19 | 2741 | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
a7812ae4 PB |
2742 | [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, |
2743 | [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2744 | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2745 | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ | |
2746 | ||
2747 | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2748 | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2749 | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ | |
d9f4bb27 | 2750 | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ |
664e0f19 FB |
2751 | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ |
2752 | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ | |
a7812ae4 PB |
2753 | [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, |
2754 | [0x2f] = { gen_helper_comiss, gen_helper_comisd }, | |
664e0f19 FB |
2755 | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2756 | [0x51] = SSE_FOP(sqrt), | |
a7812ae4 PB |
2757 | [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, |
2758 | [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, | |
2759 | [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ | |
2760 | [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ | |
2761 | [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ | |
2762 | [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ | |
664e0f19 FB |
2763 | [0x58] = SSE_FOP(add), |
2764 | [0x59] = SSE_FOP(mul), | |
a7812ae4 PB |
2765 | [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, |
2766 | gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, | |
2767 | [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, | |
664e0f19 FB |
2768 | [0x5c] = SSE_FOP(sub), |
2769 | [0x5d] = SSE_FOP(min), | |
2770 | [0x5e] = SSE_FOP(div), | |
2771 | [0x5f] = SSE_FOP(max), | |
2772 | ||
2773 | [0xc2] = SSE_FOP(cmpeq), | |
d3eb5eae BS |
2774 | [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps, |
2775 | (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ | |
664e0f19 | 2776 | |
7073fbad RH |
2777 | /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */ |
2778 | [0x38] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2779 | [0x3a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
4242b1bd | 2780 | |
664e0f19 FB |
2781 | /* MMX ops and their SSE extensions */ |
2782 | [0x60] = MMX_OP2(punpcklbw), | |
2783 | [0x61] = MMX_OP2(punpcklwd), | |
2784 | [0x62] = MMX_OP2(punpckldq), | |
2785 | [0x63] = MMX_OP2(packsswb), | |
2786 | [0x64] = MMX_OP2(pcmpgtb), | |
2787 | [0x65] = MMX_OP2(pcmpgtw), | |
2788 | [0x66] = MMX_OP2(pcmpgtl), | |
2789 | [0x67] = MMX_OP2(packuswb), | |
2790 | [0x68] = MMX_OP2(punpckhbw), | |
2791 | [0x69] = MMX_OP2(punpckhwd), | |
2792 | [0x6a] = MMX_OP2(punpckhdq), | |
2793 | [0x6b] = MMX_OP2(packssdw), | |
a7812ae4 PB |
2794 | [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, |
2795 | [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2796 | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2797 | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ | |
d3eb5eae BS |
2798 | [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx, |
2799 | (SSEFunc_0_epp)gen_helper_pshufd_xmm, | |
2800 | (SSEFunc_0_epp)gen_helper_pshufhw_xmm, | |
2801 | (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2802 | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2803 | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ | |
2804 | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ | |
2805 | [0x74] = MMX_OP2(pcmpeqb), | |
2806 | [0x75] = MMX_OP2(pcmpeqw), | |
2807 | [0x76] = MMX_OP2(pcmpeql), | |
a35f3ec7 | 2808 | [0x77] = { SSE_DUMMY }, /* emms */ |
d9f4bb27 AP |
2809 | [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ |
2810 | [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, | |
a7812ae4 PB |
2811 | [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, |
2812 | [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, | |
664e0f19 FB |
2813 | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2814 | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ | |
2815 | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ | |
2816 | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ | |
a7812ae4 | 2817 | [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, |
664e0f19 FB |
2818 | [0xd1] = MMX_OP2(psrlw), |
2819 | [0xd2] = MMX_OP2(psrld), | |
2820 | [0xd3] = MMX_OP2(psrlq), | |
2821 | [0xd4] = MMX_OP2(paddq), | |
2822 | [0xd5] = MMX_OP2(pmullw), | |
2823 | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2824 | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ | |
2825 | [0xd8] = MMX_OP2(psubusb), | |
2826 | [0xd9] = MMX_OP2(psubusw), | |
2827 | [0xda] = MMX_OP2(pminub), | |
2828 | [0xdb] = MMX_OP2(pand), | |
2829 | [0xdc] = MMX_OP2(paddusb), | |
2830 | [0xdd] = MMX_OP2(paddusw), | |
2831 | [0xde] = MMX_OP2(pmaxub), | |
2832 | [0xdf] = MMX_OP2(pandn), | |
2833 | [0xe0] = MMX_OP2(pavgb), | |
2834 | [0xe1] = MMX_OP2(psraw), | |
2835 | [0xe2] = MMX_OP2(psrad), | |
2836 | [0xe3] = MMX_OP2(pavgw), | |
2837 | [0xe4] = MMX_OP2(pmulhuw), | |
2838 | [0xe5] = MMX_OP2(pmulhw), | |
a7812ae4 | 2839 | [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, |
664e0f19 FB |
2840 | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
2841 | [0xe8] = MMX_OP2(psubsb), | |
2842 | [0xe9] = MMX_OP2(psubsw), | |
2843 | [0xea] = MMX_OP2(pminsw), | |
2844 | [0xeb] = MMX_OP2(por), | |
2845 | [0xec] = MMX_OP2(paddsb), | |
2846 | [0xed] = MMX_OP2(paddsw), | |
2847 | [0xee] = MMX_OP2(pmaxsw), | |
2848 | [0xef] = MMX_OP2(pxor), | |
465e9838 | 2849 | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
664e0f19 FB |
2850 | [0xf1] = MMX_OP2(psllw), |
2851 | [0xf2] = MMX_OP2(pslld), | |
2852 | [0xf3] = MMX_OP2(psllq), | |
2853 | [0xf4] = MMX_OP2(pmuludq), | |
2854 | [0xf5] = MMX_OP2(pmaddwd), | |
2855 | [0xf6] = MMX_OP2(psadbw), | |
d3eb5eae BS |
2856 | [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx, |
2857 | (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2858 | [0xf8] = MMX_OP2(psubb), |
2859 | [0xf9] = MMX_OP2(psubw), | |
2860 | [0xfa] = MMX_OP2(psubl), | |
2861 | [0xfb] = MMX_OP2(psubq), | |
2862 | [0xfc] = MMX_OP2(paddb), | |
2863 | [0xfd] = MMX_OP2(paddw), | |
2864 | [0xfe] = MMX_OP2(paddl), | |
2865 | }; | |
2866 | ||
d3eb5eae | 2867 | static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = { |
664e0f19 FB |
2868 | [0 + 2] = MMX_OP2(psrlw), |
2869 | [0 + 4] = MMX_OP2(psraw), | |
2870 | [0 + 6] = MMX_OP2(psllw), | |
2871 | [8 + 2] = MMX_OP2(psrld), | |
2872 | [8 + 4] = MMX_OP2(psrad), | |
2873 | [8 + 6] = MMX_OP2(pslld), | |
2874 | [16 + 2] = MMX_OP2(psrlq), | |
a7812ae4 | 2875 | [16 + 3] = { NULL, gen_helper_psrldq_xmm }, |
664e0f19 | 2876 | [16 + 6] = MMX_OP2(psllq), |
a7812ae4 | 2877 | [16 + 7] = { NULL, gen_helper_pslldq_xmm }, |
664e0f19 FB |
2878 | }; |
2879 | ||
d3eb5eae | 2880 | static const SSEFunc_0_epi sse_op_table3ai[] = { |
a7812ae4 | 2881 | gen_helper_cvtsi2ss, |
11f8cdbc | 2882 | gen_helper_cvtsi2sd |
c4baa050 | 2883 | }; |
a7812ae4 | 2884 | |
11f8cdbc | 2885 | #ifdef TARGET_X86_64 |
d3eb5eae | 2886 | static const SSEFunc_0_epl sse_op_table3aq[] = { |
11f8cdbc SW |
2887 | gen_helper_cvtsq2ss, |
2888 | gen_helper_cvtsq2sd | |
2889 | }; | |
2890 | #endif | |
2891 | ||
d3eb5eae | 2892 | static const SSEFunc_i_ep sse_op_table3bi[] = { |
a7812ae4 | 2893 | gen_helper_cvttss2si, |
a7812ae4 | 2894 | gen_helper_cvtss2si, |
bedc2ac1 | 2895 | gen_helper_cvttsd2si, |
11f8cdbc | 2896 | gen_helper_cvtsd2si |
664e0f19 | 2897 | }; |
3b46e624 | 2898 | |
11f8cdbc | 2899 | #ifdef TARGET_X86_64 |
d3eb5eae | 2900 | static const SSEFunc_l_ep sse_op_table3bq[] = { |
11f8cdbc | 2901 | gen_helper_cvttss2sq, |
11f8cdbc | 2902 | gen_helper_cvtss2sq, |
bedc2ac1 | 2903 | gen_helper_cvttsd2sq, |
11f8cdbc SW |
2904 | gen_helper_cvtsd2sq |
2905 | }; | |
2906 | #endif | |
2907 | ||
d3eb5eae | 2908 | static const SSEFunc_0_epp sse_op_table4[8][4] = { |
664e0f19 FB |
2909 | SSE_FOP(cmpeq), |
2910 | SSE_FOP(cmplt), | |
2911 | SSE_FOP(cmple), | |
2912 | SSE_FOP(cmpunord), | |
2913 | SSE_FOP(cmpneq), | |
2914 | SSE_FOP(cmpnlt), | |
2915 | SSE_FOP(cmpnle), | |
2916 | SSE_FOP(cmpord), | |
2917 | }; | |
3b46e624 | 2918 | |
d3eb5eae | 2919 | static const SSEFunc_0_epp sse_op_table5[256] = { |
a7812ae4 PB |
2920 | [0x0c] = gen_helper_pi2fw, |
2921 | [0x0d] = gen_helper_pi2fd, | |
2922 | [0x1c] = gen_helper_pf2iw, | |
2923 | [0x1d] = gen_helper_pf2id, | |
2924 | [0x8a] = gen_helper_pfnacc, | |
2925 | [0x8e] = gen_helper_pfpnacc, | |
2926 | [0x90] = gen_helper_pfcmpge, | |
2927 | [0x94] = gen_helper_pfmin, | |
2928 | [0x96] = gen_helper_pfrcp, | |
2929 | [0x97] = gen_helper_pfrsqrt, | |
2930 | [0x9a] = gen_helper_pfsub, | |
2931 | [0x9e] = gen_helper_pfadd, | |
2932 | [0xa0] = gen_helper_pfcmpgt, | |
2933 | [0xa4] = gen_helper_pfmax, | |
2934 | [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ | |
2935 | [0xa7] = gen_helper_movq, /* pfrsqit1 */ | |
2936 | [0xaa] = gen_helper_pfsubr, | |
2937 | [0xae] = gen_helper_pfacc, | |
2938 | [0xb0] = gen_helper_pfcmpeq, | |
2939 | [0xb4] = gen_helper_pfmul, | |
2940 | [0xb6] = gen_helper_movq, /* pfrcpit2 */ | |
2941 | [0xb7] = gen_helper_pmulhrw_mmx, | |
2942 | [0xbb] = gen_helper_pswapd, | |
2943 | [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ | |
a35f3ec7 AJ |
2944 | }; |
2945 | ||
d3eb5eae BS |
2946 | struct SSEOpHelper_epp { |
2947 | SSEFunc_0_epp op[2]; | |
c4baa050 BS |
2948 | uint32_t ext_mask; |
2949 | }; | |
2950 | ||
d3eb5eae BS |
2951 | struct SSEOpHelper_eppi { |
2952 | SSEFunc_0_eppi op[2]; | |
c4baa050 | 2953 | uint32_t ext_mask; |
222a3336 | 2954 | }; |
c4baa050 | 2955 | |
222a3336 | 2956 | #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 } |
a7812ae4 PB |
2957 | #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } |
2958 | #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } | |
222a3336 | 2959 | #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } |
e71827bc AJ |
2960 | #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \ |
2961 | CPUID_EXT_PCLMULQDQ } | |
d640045a | 2962 | #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES } |
c4baa050 | 2963 | |
d3eb5eae | 2964 | static const struct SSEOpHelper_epp sse_op_table6[256] = { |
222a3336 AZ |
2965 | [0x00] = SSSE3_OP(pshufb), |
2966 | [0x01] = SSSE3_OP(phaddw), | |
2967 | [0x02] = SSSE3_OP(phaddd), | |
2968 | [0x03] = SSSE3_OP(phaddsw), | |
2969 | [0x04] = SSSE3_OP(pmaddubsw), | |
2970 | [0x05] = SSSE3_OP(phsubw), | |
2971 | [0x06] = SSSE3_OP(phsubd), | |
2972 | [0x07] = SSSE3_OP(phsubsw), | |
2973 | [0x08] = SSSE3_OP(psignb), | |
2974 | [0x09] = SSSE3_OP(psignw), | |
2975 | [0x0a] = SSSE3_OP(psignd), | |
2976 | [0x0b] = SSSE3_OP(pmulhrsw), | |
2977 | [0x10] = SSE41_OP(pblendvb), | |
2978 | [0x14] = SSE41_OP(blendvps), | |
2979 | [0x15] = SSE41_OP(blendvpd), | |
2980 | [0x17] = SSE41_OP(ptest), | |
2981 | [0x1c] = SSSE3_OP(pabsb), | |
2982 | [0x1d] = SSSE3_OP(pabsw), | |
2983 | [0x1e] = SSSE3_OP(pabsd), | |
2984 | [0x20] = SSE41_OP(pmovsxbw), | |
2985 | [0x21] = SSE41_OP(pmovsxbd), | |
2986 | [0x22] = SSE41_OP(pmovsxbq), | |
2987 | [0x23] = SSE41_OP(pmovsxwd), | |
2988 | [0x24] = SSE41_OP(pmovsxwq), | |
2989 | [0x25] = SSE41_OP(pmovsxdq), | |
2990 | [0x28] = SSE41_OP(pmuldq), | |
2991 | [0x29] = SSE41_OP(pcmpeqq), | |
2992 | [0x2a] = SSE41_SPECIAL, /* movntqda */ | |
2993 | [0x2b] = SSE41_OP(packusdw), | |
2994 | [0x30] = SSE41_OP(pmovzxbw), | |
2995 | [0x31] = SSE41_OP(pmovzxbd), | |
2996 | [0x32] = SSE41_OP(pmovzxbq), | |
2997 | [0x33] = SSE41_OP(pmovzxwd), | |
2998 | [0x34] = SSE41_OP(pmovzxwq), | |
2999 | [0x35] = SSE41_OP(pmovzxdq), | |
3000 | [0x37] = SSE42_OP(pcmpgtq), | |
3001 | [0x38] = SSE41_OP(pminsb), | |
3002 | [0x39] = SSE41_OP(pminsd), | |
3003 | [0x3a] = SSE41_OP(pminuw), | |
3004 | [0x3b] = SSE41_OP(pminud), | |
3005 | [0x3c] = SSE41_OP(pmaxsb), | |
3006 | [0x3d] = SSE41_OP(pmaxsd), | |
3007 | [0x3e] = SSE41_OP(pmaxuw), | |
3008 | [0x3f] = SSE41_OP(pmaxud), | |
3009 | [0x40] = SSE41_OP(pmulld), | |
3010 | [0x41] = SSE41_OP(phminposuw), | |
d640045a AJ |
3011 | [0xdb] = AESNI_OP(aesimc), |
3012 | [0xdc] = AESNI_OP(aesenc), | |
3013 | [0xdd] = AESNI_OP(aesenclast), | |
3014 | [0xde] = AESNI_OP(aesdec), | |
3015 | [0xdf] = AESNI_OP(aesdeclast), | |
4242b1bd AZ |
3016 | }; |
3017 | ||
d3eb5eae | 3018 | static const struct SSEOpHelper_eppi sse_op_table7[256] = { |
222a3336 AZ |
3019 | [0x08] = SSE41_OP(roundps), |
3020 | [0x09] = SSE41_OP(roundpd), | |
3021 | [0x0a] = SSE41_OP(roundss), | |
3022 | [0x0b] = SSE41_OP(roundsd), | |
3023 | [0x0c] = SSE41_OP(blendps), | |
3024 | [0x0d] = SSE41_OP(blendpd), | |
3025 | [0x0e] = SSE41_OP(pblendw), | |
3026 | [0x0f] = SSSE3_OP(palignr), | |
3027 | [0x14] = SSE41_SPECIAL, /* pextrb */ | |
3028 | [0x15] = SSE41_SPECIAL, /* pextrw */ | |
3029 | [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ | |
3030 | [0x17] = SSE41_SPECIAL, /* extractps */ | |
3031 | [0x20] = SSE41_SPECIAL, /* pinsrb */ | |
3032 | [0x21] = SSE41_SPECIAL, /* insertps */ | |
3033 | [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ | |
3034 | [0x40] = SSE41_OP(dpps), | |
3035 | [0x41] = SSE41_OP(dppd), | |
3036 | [0x42] = SSE41_OP(mpsadbw), | |
e71827bc | 3037 | [0x44] = PCLMULQDQ_OP(pclmulqdq), |
222a3336 AZ |
3038 | [0x60] = SSE42_OP(pcmpestrm), |
3039 | [0x61] = SSE42_OP(pcmpestri), | |
3040 | [0x62] = SSE42_OP(pcmpistrm), | |
3041 | [0x63] = SSE42_OP(pcmpistri), | |
d640045a | 3042 | [0xdf] = AESNI_OP(aeskeygenassist), |
4242b1bd AZ |
3043 | }; |
3044 | ||
0af10c86 BS |
3045 | static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
3046 | target_ulong pc_start, int rex_r) | |
664e0f19 | 3047 | { |
d67dc9e6 | 3048 | int b1, op1_offset, op2_offset, is_xmm, val; |
4eeb3939 | 3049 | int modrm, mod, rm, reg; |
d3eb5eae BS |
3050 | SSEFunc_0_epp sse_fn_epp; |
3051 | SSEFunc_0_eppi sse_fn_eppi; | |
c4baa050 | 3052 | SSEFunc_0_ppi sse_fn_ppi; |
d3eb5eae | 3053 | SSEFunc_0_eppt sse_fn_eppt; |
d67dc9e6 | 3054 | TCGMemOp ot; |
664e0f19 FB |
3055 | |
3056 | b &= 0xff; | |
5fafdf24 | 3057 | if (s->prefix & PREFIX_DATA) |
664e0f19 | 3058 | b1 = 1; |
5fafdf24 | 3059 | else if (s->prefix & PREFIX_REPZ) |
664e0f19 | 3060 | b1 = 2; |
5fafdf24 | 3061 | else if (s->prefix & PREFIX_REPNZ) |
664e0f19 FB |
3062 | b1 = 3; |
3063 | else | |
3064 | b1 = 0; | |
d3eb5eae BS |
3065 | sse_fn_epp = sse_op_table1[b][b1]; |
3066 | if (!sse_fn_epp) { | |
664e0f19 | 3067 | goto illegal_op; |
c4baa050 | 3068 | } |
a35f3ec7 | 3069 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
664e0f19 FB |
3070 | is_xmm = 1; |
3071 | } else { | |
3072 | if (b1 == 0) { | |
3073 | /* MMX case */ | |
3074 | is_xmm = 0; | |
3075 | } else { | |
3076 | is_xmm = 1; | |
3077 | } | |
3078 | } | |
3079 | /* simple MMX/SSE operation */ | |
3080 | if (s->flags & HF_TS_MASK) { | |
3081 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
3082 | return; | |
3083 | } | |
3084 | if (s->flags & HF_EM_MASK) { | |
3085 | illegal_op: | |
3086 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
3087 | return; | |
3088 | } | |
3089 | if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) | |
4242b1bd AZ |
3090 | if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) |
3091 | goto illegal_op; | |
e771edab AJ |
3092 | if (b == 0x0e) { |
3093 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) | |
3094 | goto illegal_op; | |
3095 | /* femms */ | |
d3eb5eae | 3096 | gen_helper_emms(cpu_env); |
e771edab AJ |
3097 | return; |
3098 | } | |
3099 | if (b == 0x77) { | |
3100 | /* emms */ | |
d3eb5eae | 3101 | gen_helper_emms(cpu_env); |
664e0f19 FB |
3102 | return; |
3103 | } | |
3104 | /* prepare MMX state (XXX: optimize by storing fptt and fptags in | |
3105 | the static cpu state) */ | |
3106 | if (!is_xmm) { | |
d3eb5eae | 3107 | gen_helper_enter_mmx(cpu_env); |
664e0f19 FB |
3108 | } |
3109 | ||
0af10c86 | 3110 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3111 | reg = ((modrm >> 3) & 7); |
3112 | if (is_xmm) | |
3113 | reg |= rex_r; | |
3114 | mod = (modrm >> 6) & 3; | |
d3eb5eae | 3115 | if (sse_fn_epp == SSE_SPECIAL) { |
664e0f19 FB |
3116 | b |= (b1 << 8); |
3117 | switch(b) { | |
3118 | case 0x0e7: /* movntq */ | |
5fafdf24 | 3119 | if (mod == 3) |
664e0f19 | 3120 | goto illegal_op; |
4eeb3939 | 3121 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3122 | gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx)); |
664e0f19 FB |
3123 | break; |
3124 | case 0x1e7: /* movntdq */ | |
3125 | case 0x02b: /* movntps */ | |
3126 | case 0x12b: /* movntps */ | |
2e21e749 T |
3127 | if (mod == 3) |
3128 | goto illegal_op; | |
4eeb3939 | 3129 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3130 | gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
2e21e749 | 3131 | break; |
465e9838 FB |
3132 | case 0x3f0: /* lddqu */ |
3133 | if (mod == 3) | |
664e0f19 | 3134 | goto illegal_op; |
4eeb3939 | 3135 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3136 | gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
664e0f19 | 3137 | break; |
d9f4bb27 AP |
3138 | case 0x22b: /* movntss */ |
3139 | case 0x32b: /* movntsd */ | |
3140 | if (mod == 3) | |
3141 | goto illegal_op; | |
4eeb3939 | 3142 | gen_lea_modrm(env, s, modrm); |
d9f4bb27 | 3143 | if (b1 & 1) { |
323d1876 | 3144 | gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
d9f4bb27 AP |
3145 | } else { |
3146 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3147 | xmm_regs[reg].XMM_L(0))); | |
fd8ca9f6 | 3148 | gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); |
d9f4bb27 AP |
3149 | } |
3150 | break; | |
664e0f19 | 3151 | case 0x6e: /* movd mm, ea */ |
dabd98dd | 3152 | #ifdef TARGET_X86_64 |
ab4e4aec | 3153 | if (s->dflag == MO_64) { |
4ba9938c | 3154 | gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0); |
5af45186 | 3155 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); |
5fafdf24 | 3156 | } else |
dabd98dd FB |
3157 | #endif |
3158 | { | |
4ba9938c | 3159 | gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0); |
5af45186 FB |
3160 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3161 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
a7812ae4 PB |
3162 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3163 | gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); | |
dabd98dd | 3164 | } |
664e0f19 FB |
3165 | break; |
3166 | case 0x16e: /* movd xmm, ea */ | |
dabd98dd | 3167 | #ifdef TARGET_X86_64 |
ab4e4aec | 3168 | if (s->dflag == MO_64) { |
4ba9938c | 3169 | gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0); |
5af45186 FB |
3170 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3171 | offsetof(CPUX86State,xmm_regs[reg])); | |
a7812ae4 | 3172 | gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); |
5fafdf24 | 3173 | } else |
dabd98dd FB |
3174 | #endif |
3175 | { | |
4ba9938c | 3176 | gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0); |
5af45186 FB |
3177 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3178 | offsetof(CPUX86State,xmm_regs[reg])); | |
b6abf97d | 3179 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 3180 | gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); |
dabd98dd | 3181 | } |
664e0f19 FB |
3182 | break; |
3183 | case 0x6f: /* movq mm, ea */ | |
3184 | if (mod != 3) { | |
4eeb3939 | 3185 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3186 | gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx)); |
664e0f19 FB |
3187 | } else { |
3188 | rm = (modrm & 7); | |
b6abf97d | 3189 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3190 | offsetof(CPUX86State,fpregs[rm].mmx)); |
b6abf97d | 3191 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3192 | offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3193 | } |
3194 | break; | |
3195 | case 0x010: /* movups */ | |
3196 | case 0x110: /* movupd */ | |
3197 | case 0x028: /* movaps */ | |
3198 | case 0x128: /* movapd */ | |
3199 | case 0x16f: /* movdqa xmm, ea */ | |
3200 | case 0x26f: /* movdqu xmm, ea */ | |
3201 | if (mod != 3) { | |
4eeb3939 | 3202 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3203 | gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
664e0f19 FB |
3204 | } else { |
3205 | rm = (modrm & 7) | REX_B(s); | |
3206 | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), | |
3207 | offsetof(CPUX86State,xmm_regs[rm])); | |
3208 | } | |
3209 | break; | |
3210 | case 0x210: /* movss xmm, ea */ | |
3211 | if (mod != 3) { | |
4eeb3939 | 3212 | gen_lea_modrm(env, s, modrm); |
909be183 | 3213 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
651ba608 | 3214 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
97212c88 | 3215 | tcg_gen_movi_tl(cpu_T[0], 0); |
651ba608 FB |
3216 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); |
3217 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3218 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3219 | } else { |
3220 | rm = (modrm & 7) | REX_B(s); | |
3221 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3222 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3223 | } | |
3224 | break; | |
3225 | case 0x310: /* movsd xmm, ea */ | |
3226 | if (mod != 3) { | |
4eeb3939 | 3227 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3228 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3229 | xmm_regs[reg].XMM_Q(0))); | |
97212c88 | 3230 | tcg_gen_movi_tl(cpu_T[0], 0); |
651ba608 FB |
3231 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3232 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3233 | } else { |
3234 | rm = (modrm & 7) | REX_B(s); | |
3235 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3236 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3237 | } | |
3238 | break; | |
3239 | case 0x012: /* movlps */ | |
3240 | case 0x112: /* movlpd */ | |
3241 | if (mod != 3) { | |
4eeb3939 | 3242 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3243 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3244 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3245 | } else { |
3246 | /* movhlps */ | |
3247 | rm = (modrm & 7) | REX_B(s); | |
3248 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3249 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3250 | } | |
3251 | break; | |
465e9838 FB |
3252 | case 0x212: /* movsldup */ |
3253 | if (mod != 3) { | |
4eeb3939 | 3254 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3255 | gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
465e9838 FB |
3256 | } else { |
3257 | rm = (modrm & 7) | REX_B(s); | |
3258 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3259 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3260 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3261 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); | |
3262 | } | |
3263 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3264 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3265 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3266 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3267 | break; | |
3268 | case 0x312: /* movddup */ | |
3269 | if (mod != 3) { | |
4eeb3939 | 3270 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3271 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3272 | xmm_regs[reg].XMM_Q(0))); | |
465e9838 FB |
3273 | } else { |
3274 | rm = (modrm & 7) | REX_B(s); | |
3275 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3276 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3277 | } | |
3278 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
ba6526df | 3279 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 | 3280 | break; |
664e0f19 FB |
3281 | case 0x016: /* movhps */ |
3282 | case 0x116: /* movhpd */ | |
3283 | if (mod != 3) { | |
4eeb3939 | 3284 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3285 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3286 | xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3287 | } else { |
3288 | /* movlhps */ | |
3289 | rm = (modrm & 7) | REX_B(s); | |
3290 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
3291 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3292 | } | |
3293 | break; | |
3294 | case 0x216: /* movshdup */ | |
3295 | if (mod != 3) { | |
4eeb3939 | 3296 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3297 | gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
664e0f19 FB |
3298 | } else { |
3299 | rm = (modrm & 7) | REX_B(s); | |
3300 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3301 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); | |
3302 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3303 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); | |
3304 | } | |
3305 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3306 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); | |
3307 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3308 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
3309 | break; | |
d9f4bb27 AP |
3310 | case 0x178: |
3311 | case 0x378: | |
3312 | { | |
3313 | int bit_index, field_length; | |
3314 | ||
3315 | if (b1 == 1 && reg != 0) | |
3316 | goto illegal_op; | |
0af10c86 BS |
3317 | field_length = cpu_ldub_code(env, s->pc++) & 0x3F; |
3318 | bit_index = cpu_ldub_code(env, s->pc++) & 0x3F; | |
d9f4bb27 AP |
3319 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3320 | offsetof(CPUX86State,xmm_regs[reg])); | |
3321 | if (b1 == 1) | |
d3eb5eae BS |
3322 | gen_helper_extrq_i(cpu_env, cpu_ptr0, |
3323 | tcg_const_i32(bit_index), | |
3324 | tcg_const_i32(field_length)); | |
d9f4bb27 | 3325 | else |
d3eb5eae BS |
3326 | gen_helper_insertq_i(cpu_env, cpu_ptr0, |
3327 | tcg_const_i32(bit_index), | |
3328 | tcg_const_i32(field_length)); | |
d9f4bb27 AP |
3329 | } |
3330 | break; | |
664e0f19 | 3331 | case 0x7e: /* movd ea, mm */ |
dabd98dd | 3332 | #ifdef TARGET_X86_64 |
ab4e4aec | 3333 | if (s->dflag == MO_64) { |
5af45186 FB |
3334 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3335 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
4ba9938c | 3336 | gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1); |
5fafdf24 | 3337 | } else |
dabd98dd FB |
3338 | #endif |
3339 | { | |
5af45186 FB |
3340 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3341 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); | |
4ba9938c | 3342 | gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1); |
dabd98dd | 3343 | } |
664e0f19 FB |
3344 | break; |
3345 | case 0x17e: /* movd ea, xmm */ | |
dabd98dd | 3346 | #ifdef TARGET_X86_64 |
ab4e4aec | 3347 | if (s->dflag == MO_64) { |
5af45186 FB |
3348 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3349 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
4ba9938c | 3350 | gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1); |
5fafdf24 | 3351 | } else |
dabd98dd FB |
3352 | #endif |
3353 | { | |
5af45186 FB |
3354 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3355 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
4ba9938c | 3356 | gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1); |
dabd98dd | 3357 | } |
664e0f19 FB |
3358 | break; |
3359 | case 0x27e: /* movq xmm, ea */ | |
3360 | if (mod != 3) { | |
4eeb3939 | 3361 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3362 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
3363 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3364 | } else { |
3365 | rm = (modrm & 7) | REX_B(s); | |
3366 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3367 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3368 | } | |
3369 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
3370 | break; | |
3371 | case 0x7f: /* movq ea, mm */ | |
3372 | if (mod != 3) { | |
4eeb3939 | 3373 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3374 | gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx)); |
664e0f19 FB |
3375 | } else { |
3376 | rm = (modrm & 7); | |
3377 | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), | |
3378 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
3379 | } | |
3380 | break; | |
3381 | case 0x011: /* movups */ | |
3382 | case 0x111: /* movupd */ | |
3383 | case 0x029: /* movaps */ | |
3384 | case 0x129: /* movapd */ | |
3385 | case 0x17f: /* movdqa ea, xmm */ | |
3386 | case 0x27f: /* movdqu ea, xmm */ | |
3387 | if (mod != 3) { | |
4eeb3939 | 3388 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3389 | gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); |
664e0f19 FB |
3390 | } else { |
3391 | rm = (modrm & 7) | REX_B(s); | |
3392 | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), | |
3393 | offsetof(CPUX86State,xmm_regs[reg])); | |
3394 | } | |
3395 | break; | |
3396 | case 0x211: /* movss ea, xmm */ | |
3397 | if (mod != 3) { | |
4eeb3939 | 3398 | gen_lea_modrm(env, s, modrm); |
651ba608 | 3399 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
fd8ca9f6 | 3400 | gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); |
664e0f19 FB |
3401 | } else { |
3402 | rm = (modrm & 7) | REX_B(s); | |
3403 | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), | |
3404 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3405 | } | |
3406 | break; | |
3407 | case 0x311: /* movsd ea, xmm */ | |
3408 | if (mod != 3) { | |
4eeb3939 | 3409 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3410 | gen_stq_env_A0(s, offsetof(CPUX86State, |
3411 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3412 | } else { |
3413 | rm = (modrm & 7) | REX_B(s); | |
3414 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3415 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3416 | } | |
3417 | break; | |
3418 | case 0x013: /* movlps */ | |
3419 | case 0x113: /* movlpd */ | |
3420 | if (mod != 3) { | |
4eeb3939 | 3421 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3422 | gen_stq_env_A0(s, offsetof(CPUX86State, |
3423 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3424 | } else { |
3425 | goto illegal_op; | |
3426 | } | |
3427 | break; | |
3428 | case 0x017: /* movhps */ | |
3429 | case 0x117: /* movhpd */ | |
3430 | if (mod != 3) { | |
4eeb3939 | 3431 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3432 | gen_stq_env_A0(s, offsetof(CPUX86State, |
3433 | xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3434 | } else { |
3435 | goto illegal_op; | |
3436 | } | |
3437 | break; | |
3438 | case 0x71: /* shift mm, im */ | |
3439 | case 0x72: | |
3440 | case 0x73: | |
3441 | case 0x171: /* shift xmm, im */ | |
3442 | case 0x172: | |
3443 | case 0x173: | |
c045af25 AK |
3444 | if (b1 >= 2) { |
3445 | goto illegal_op; | |
3446 | } | |
0af10c86 | 3447 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 | 3448 | if (is_xmm) { |
1b90d56e | 3449 | tcg_gen_movi_tl(cpu_T[0], val); |
651ba608 | 3450 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
97212c88 | 3451 | tcg_gen_movi_tl(cpu_T[0], 0); |
651ba608 | 3452 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); |
664e0f19 FB |
3453 | op1_offset = offsetof(CPUX86State,xmm_t0); |
3454 | } else { | |
1b90d56e | 3455 | tcg_gen_movi_tl(cpu_T[0], val); |
651ba608 | 3456 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); |
97212c88 | 3457 | tcg_gen_movi_tl(cpu_T[0], 0); |
651ba608 | 3458 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); |
664e0f19 FB |
3459 | op1_offset = offsetof(CPUX86State,mmx_t0); |
3460 | } | |
d3eb5eae BS |
3461 | sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + |
3462 | (((modrm >> 3)) & 7)][b1]; | |
3463 | if (!sse_fn_epp) { | |
664e0f19 | 3464 | goto illegal_op; |
c4baa050 | 3465 | } |
664e0f19 FB |
3466 | if (is_xmm) { |
3467 | rm = (modrm & 7) | REX_B(s); | |
3468 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3469 | } else { | |
3470 | rm = (modrm & 7); | |
3471 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3472 | } | |
5af45186 FB |
3473 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3474 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); | |
d3eb5eae | 3475 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3476 | break; |
3477 | case 0x050: /* movmskps */ | |
664e0f19 | 3478 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3479 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3480 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3481 | gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
a7fbcbe5 | 3482 | tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32); |
664e0f19 FB |
3483 | break; |
3484 | case 0x150: /* movmskpd */ | |
664e0f19 | 3485 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3486 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3487 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3488 | gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
a7fbcbe5 | 3489 | tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32); |
664e0f19 FB |
3490 | break; |
3491 | case 0x02a: /* cvtpi2ps */ | |
3492 | case 0x12a: /* cvtpi2pd */ | |
d3eb5eae | 3493 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3494 | if (mod != 3) { |
4eeb3939 | 3495 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 3496 | op2_offset = offsetof(CPUX86State,mmx_t0); |
323d1876 | 3497 | gen_ldq_env_A0(s, op2_offset); |
664e0f19 FB |
3498 | } else { |
3499 | rm = (modrm & 7); | |
3500 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3501 | } | |
3502 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3503 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3504 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3505 | switch(b >> 8) { |
3506 | case 0x0: | |
d3eb5eae | 3507 | gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3508 | break; |
3509 | default: | |
3510 | case 0x1: | |
d3eb5eae | 3511 | gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3512 | break; |
3513 | } | |
3514 | break; | |
3515 | case 0x22a: /* cvtsi2ss */ | |
3516 | case 0x32a: /* cvtsi2sd */ | |
ab4e4aec | 3517 | ot = mo_64_32(s->dflag); |
0af10c86 | 3518 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
664e0f19 | 3519 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
5af45186 | 3520 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4ba9938c | 3521 | if (ot == MO_32) { |
d3eb5eae | 3522 | SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1]; |
28e10711 | 3523 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 3524 | sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32); |
28e10711 | 3525 | } else { |
11f8cdbc | 3526 | #ifdef TARGET_X86_64 |
d3eb5eae BS |
3527 | SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1]; |
3528 | sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]); | |
11f8cdbc SW |
3529 | #else |
3530 | goto illegal_op; | |
3531 | #endif | |
28e10711 | 3532 | } |
664e0f19 FB |
3533 | break; |
3534 | case 0x02c: /* cvttps2pi */ | |
3535 | case 0x12c: /* cvttpd2pi */ | |
3536 | case 0x02d: /* cvtps2pi */ | |
3537 | case 0x12d: /* cvtpd2pi */ | |
d3eb5eae | 3538 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3539 | if (mod != 3) { |
4eeb3939 | 3540 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 3541 | op2_offset = offsetof(CPUX86State,xmm_t0); |
323d1876 | 3542 | gen_ldo_env_A0(s, op2_offset); |
664e0f19 FB |
3543 | } else { |
3544 | rm = (modrm & 7) | REX_B(s); | |
3545 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3546 | } | |
3547 | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx); | |
5af45186 FB |
3548 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3549 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3550 | switch(b) { |
3551 | case 0x02c: | |
d3eb5eae | 3552 | gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3553 | break; |
3554 | case 0x12c: | |
d3eb5eae | 3555 | gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3556 | break; |
3557 | case 0x02d: | |
d3eb5eae | 3558 | gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3559 | break; |
3560 | case 0x12d: | |
d3eb5eae | 3561 | gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3562 | break; |
3563 | } | |
3564 | break; | |
3565 | case 0x22c: /* cvttss2si */ | |
3566 | case 0x32c: /* cvttsd2si */ | |
3567 | case 0x22d: /* cvtss2si */ | |
3568 | case 0x32d: /* cvtsd2si */ | |
ab4e4aec | 3569 | ot = mo_64_32(s->dflag); |
31313213 | 3570 | if (mod != 3) { |
4eeb3939 | 3571 | gen_lea_modrm(env, s, modrm); |
31313213 | 3572 | if ((b >> 8) & 1) { |
323d1876 | 3573 | gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0))); |
31313213 | 3574 | } else { |
909be183 | 3575 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
651ba608 | 3576 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
31313213 FB |
3577 | } |
3578 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3579 | } else { | |
3580 | rm = (modrm & 7) | REX_B(s); | |
3581 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3582 | } | |
5af45186 | 3583 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
4ba9938c | 3584 | if (ot == MO_32) { |
d3eb5eae | 3585 | SSEFunc_i_ep sse_fn_i_ep = |
bedc2ac1 | 3586 | sse_op_table3bi[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3587 | sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3588 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
5af45186 | 3589 | } else { |
11f8cdbc | 3590 | #ifdef TARGET_X86_64 |
d3eb5eae | 3591 | SSEFunc_l_ep sse_fn_l_ep = |
bedc2ac1 | 3592 | sse_op_table3bq[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3593 | sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0); |
11f8cdbc SW |
3594 | #else |
3595 | goto illegal_op; | |
3596 | #endif | |
5af45186 | 3597 | } |
57fec1fe | 3598 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3599 | break; |
3600 | case 0xc4: /* pinsrw */ | |
5fafdf24 | 3601 | case 0x1c4: |
d1e42c5c | 3602 | s->rip_offset = 1; |
4ba9938c | 3603 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
0af10c86 | 3604 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3605 | if (b1) { |
3606 | val &= 7; | |
5af45186 FB |
3607 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3608 | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); | |
664e0f19 FB |
3609 | } else { |
3610 | val &= 3; | |
5af45186 FB |
3611 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3612 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); | |
664e0f19 FB |
3613 | } |
3614 | break; | |
3615 | case 0xc5: /* pextrw */ | |
5fafdf24 | 3616 | case 0x1c5: |
664e0f19 FB |
3617 | if (mod != 3) |
3618 | goto illegal_op; | |
ab4e4aec | 3619 | ot = mo_64_32(s->dflag); |
0af10c86 | 3620 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3621 | if (b1) { |
3622 | val &= 7; | |
3623 | rm = (modrm & 7) | REX_B(s); | |
5af45186 FB |
3624 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3625 | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); | |
664e0f19 FB |
3626 | } else { |
3627 | val &= 3; | |
3628 | rm = (modrm & 7); | |
5af45186 FB |
3629 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3630 | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); | |
664e0f19 FB |
3631 | } |
3632 | reg = ((modrm >> 3) & 7) | rex_r; | |
6dc2d0da | 3633 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3634 | break; |
3635 | case 0x1d6: /* movq ea, xmm */ | |
3636 | if (mod != 3) { | |
4eeb3939 | 3637 | gen_lea_modrm(env, s, modrm); |
323d1876 RH |
3638 | gen_stq_env_A0(s, offsetof(CPUX86State, |
3639 | xmm_regs[reg].XMM_Q(0))); | |
664e0f19 FB |
3640 | } else { |
3641 | rm = (modrm & 7) | REX_B(s); | |
3642 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3643 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3644 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3645 | } | |
3646 | break; | |
3647 | case 0x2d6: /* movq2dq */ | |
d3eb5eae | 3648 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3649 | rm = (modrm & 7); |
3650 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3651 | offsetof(CPUX86State,fpregs[rm].mmx)); | |
3652 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3653 | break; |
3654 | case 0x3d6: /* movdq2q */ | |
d3eb5eae | 3655 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3656 | rm = (modrm & 7) | REX_B(s); |
3657 | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), | |
3658 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
664e0f19 FB |
3659 | break; |
3660 | case 0xd7: /* pmovmskb */ | |
3661 | case 0x1d7: | |
3662 | if (mod != 3) | |
3663 | goto illegal_op; | |
3664 | if (b1) { | |
3665 | rm = (modrm & 7) | REX_B(s); | |
5af45186 | 3666 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
d3eb5eae | 3667 | gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 FB |
3668 | } else { |
3669 | rm = (modrm & 7); | |
5af45186 | 3670 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
d3eb5eae | 3671 | gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 FB |
3672 | } |
3673 | reg = ((modrm >> 3) & 7) | rex_r; | |
a7fbcbe5 | 3674 | tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32); |
664e0f19 | 3675 | break; |
111994ee | 3676 | |
4242b1bd | 3677 | case 0x138: |
000cacf6 | 3678 | case 0x038: |
4242b1bd | 3679 | b = modrm; |
111994ee RH |
3680 | if ((b & 0xf0) == 0xf0) { |
3681 | goto do_0f_38_fx; | |
3682 | } | |
0af10c86 | 3683 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
3684 | rm = modrm & 7; |
3685 | reg = ((modrm >> 3) & 7) | rex_r; | |
3686 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3687 | if (b1 >= 2) { |
3688 | goto illegal_op; | |
3689 | } | |
4242b1bd | 3690 | |
d3eb5eae BS |
3691 | sse_fn_epp = sse_op_table6[b].op[b1]; |
3692 | if (!sse_fn_epp) { | |
4242b1bd | 3693 | goto illegal_op; |
c4baa050 | 3694 | } |
222a3336 AZ |
3695 | if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask)) |
3696 | goto illegal_op; | |
4242b1bd AZ |
3697 | |
3698 | if (b1) { | |
3699 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3700 | if (mod == 3) { | |
3701 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3702 | } else { | |
3703 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
4eeb3939 | 3704 | gen_lea_modrm(env, s, modrm); |
222a3336 AZ |
3705 | switch (b) { |
3706 | case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ | |
3707 | case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ | |
3708 | case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ | |
323d1876 | 3709 | gen_ldq_env_A0(s, op2_offset + |
222a3336 AZ |
3710 | offsetof(XMMReg, XMM_Q(0))); |
3711 | break; | |
3712 | case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ | |
3713 | case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ | |
3c5f4116 RH |
3714 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
3715 | s->mem_index, MO_LEUL); | |
222a3336 AZ |
3716 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + |
3717 | offsetof(XMMReg, XMM_L(0))); | |
3718 | break; | |
3719 | case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ | |
3c5f4116 RH |
3720 | tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0, |
3721 | s->mem_index, MO_LEUW); | |
222a3336 AZ |
3722 | tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + |
3723 | offsetof(XMMReg, XMM_W(0))); | |
3724 | break; | |
3725 | case 0x2a: /* movntqda */ | |
323d1876 | 3726 | gen_ldo_env_A0(s, op1_offset); |
222a3336 AZ |
3727 | return; |
3728 | default: | |
323d1876 | 3729 | gen_ldo_env_A0(s, op2_offset); |
222a3336 | 3730 | } |
4242b1bd AZ |
3731 | } |
3732 | } else { | |
3733 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3734 | if (mod == 3) { | |
3735 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3736 | } else { | |
3737 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
4eeb3939 | 3738 | gen_lea_modrm(env, s, modrm); |
323d1876 | 3739 | gen_ldq_env_A0(s, op2_offset); |
4242b1bd AZ |
3740 | } |
3741 | } | |
d3eb5eae | 3742 | if (sse_fn_epp == SSE_SPECIAL) { |
222a3336 | 3743 | goto illegal_op; |
c4baa050 | 3744 | } |
222a3336 | 3745 | |
4242b1bd AZ |
3746 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3747 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 3748 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
222a3336 | 3749 | |
3ca51d07 RH |
3750 | if (b == 0x17) { |
3751 | set_cc_op(s, CC_OP_EFLAGS); | |
3752 | } | |
4242b1bd | 3753 | break; |
111994ee RH |
3754 | |
3755 | case 0x238: | |
3756 | case 0x338: | |
3757 | do_0f_38_fx: | |
3758 | /* Various integer extensions at 0f 38 f[0-f]. */ | |
3759 | b = modrm | (b1 << 8); | |
0af10c86 | 3760 | modrm = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
3761 | reg = ((modrm >> 3) & 7) | rex_r; |
3762 | ||
111994ee RH |
3763 | switch (b) { |
3764 | case 0x3f0: /* crc32 Gd,Eb */ | |
3765 | case 0x3f1: /* crc32 Gd,Ey */ | |
3766 | do_crc32: | |
3767 | if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) { | |
3768 | goto illegal_op; | |
3769 | } | |
3770 | if ((b & 0xff) == 0xf0) { | |
4ba9938c | 3771 | ot = MO_8; |
ab4e4aec | 3772 | } else if (s->dflag != MO_64) { |
4ba9938c | 3773 | ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32); |
111994ee | 3774 | } else { |
4ba9938c | 3775 | ot = MO_64; |
111994ee | 3776 | } |
4242b1bd | 3777 | |
24b9c00f | 3778 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[reg]); |
111994ee RH |
3779 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3780 | gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, | |
3781 | cpu_T[0], tcg_const_i32(8 << ot)); | |
222a3336 | 3782 | |
ab4e4aec | 3783 | ot = mo_64_32(s->dflag); |
111994ee RH |
3784 | gen_op_mov_reg_T0(ot, reg); |
3785 | break; | |
222a3336 | 3786 | |
111994ee RH |
3787 | case 0x1f0: /* crc32 or movbe */ |
3788 | case 0x1f1: | |
3789 | /* For these insns, the f3 prefix is supposed to have priority | |
3790 | over the 66 prefix, but that's not what we implement above | |
3791 | setting b1. */ | |
3792 | if (s->prefix & PREFIX_REPNZ) { | |
3793 | goto do_crc32; | |
3794 | } | |
3795 | /* FALLTHRU */ | |
3796 | case 0x0f0: /* movbe Gy,My */ | |
3797 | case 0x0f1: /* movbe My,Gy */ | |
3798 | if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) { | |
3799 | goto illegal_op; | |
3800 | } | |
ab4e4aec | 3801 | if (s->dflag != MO_64) { |
4ba9938c | 3802 | ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32); |
111994ee | 3803 | } else { |
4ba9938c | 3804 | ot = MO_64; |
111994ee RH |
3805 | } |
3806 | ||
3655a19f | 3807 | gen_lea_modrm(env, s, modrm); |
111994ee | 3808 | if ((b & 1) == 0) { |
3655a19f RH |
3809 | tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, |
3810 | s->mem_index, ot | MO_BE); | |
111994ee RH |
3811 | gen_op_mov_reg_T0(ot, reg); |
3812 | } else { | |
3655a19f RH |
3813 | tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0, |
3814 | s->mem_index, ot | MO_BE); | |
111994ee RH |
3815 | } |
3816 | break; | |
3817 | ||
7073fbad RH |
3818 | case 0x0f2: /* andn Gy, By, Ey */ |
3819 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1) | |
3820 | || !(s->prefix & PREFIX_VEX) | |
3821 | || s->vex_l != 0) { | |
3822 | goto illegal_op; | |
3823 | } | |
ab4e4aec | 3824 | ot = mo_64_32(s->dflag); |
7073fbad RH |
3825 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3826 | tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]); | |
3827 | gen_op_mov_reg_T0(ot, reg); | |
3828 | gen_op_update1_cc(); | |
3829 | set_cc_op(s, CC_OP_LOGICB + ot); | |
3830 | break; | |
3831 | ||
c7ab7565 RH |
3832 | case 0x0f7: /* bextr Gy, Ey, By */ |
3833 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1) | |
3834 | || !(s->prefix & PREFIX_VEX) | |
3835 | || s->vex_l != 0) { | |
3836 | goto illegal_op; | |
3837 | } | |
ab4e4aec | 3838 | ot = mo_64_32(s->dflag); |
c7ab7565 RH |
3839 | { |
3840 | TCGv bound, zero; | |
3841 | ||
3842 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); | |
3843 | /* Extract START, and shift the operand. | |
3844 | Shifts larger than operand size get zeros. */ | |
3845 | tcg_gen_ext8u_tl(cpu_A0, cpu_regs[s->vex_v]); | |
3846 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_A0); | |
3847 | ||
4ba9938c | 3848 | bound = tcg_const_tl(ot == MO_64 ? 63 : 31); |
c7ab7565 RH |
3849 | zero = tcg_const_tl(0); |
3850 | tcg_gen_movcond_tl(TCG_COND_LEU, cpu_T[0], cpu_A0, bound, | |
3851 | cpu_T[0], zero); | |
3852 | tcg_temp_free(zero); | |
3853 | ||
3854 | /* Extract the LEN into a mask. Lengths larger than | |
3855 | operand size get all ones. */ | |
3856 | tcg_gen_shri_tl(cpu_A0, cpu_regs[s->vex_v], 8); | |
3857 | tcg_gen_ext8u_tl(cpu_A0, cpu_A0); | |
3858 | tcg_gen_movcond_tl(TCG_COND_LEU, cpu_A0, cpu_A0, bound, | |
3859 | cpu_A0, bound); | |
3860 | tcg_temp_free(bound); | |
3861 | tcg_gen_movi_tl(cpu_T[1], 1); | |
3862 | tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_A0); | |
3863 | tcg_gen_subi_tl(cpu_T[1], cpu_T[1], 1); | |
3864 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
3865 | ||
3866 | gen_op_mov_reg_T0(ot, reg); | |
3867 | gen_op_update1_cc(); | |
3868 | set_cc_op(s, CC_OP_LOGICB + ot); | |
3869 | } | |
3870 | break; | |
3871 | ||
02ea1e6b RH |
3872 | case 0x0f5: /* bzhi Gy, Ey, By */ |
3873 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
3874 | || !(s->prefix & PREFIX_VEX) | |
3875 | || s->vex_l != 0) { | |
3876 | goto illegal_op; | |
3877 | } | |
ab4e4aec | 3878 | ot = mo_64_32(s->dflag); |
02ea1e6b RH |
3879 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3880 | tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]); | |
3881 | { | |
4ba9938c | 3882 | TCGv bound = tcg_const_tl(ot == MO_64 ? 63 : 31); |
02ea1e6b RH |
3883 | /* Note that since we're using BMILG (in order to get O |
3884 | cleared) we need to store the inverse into C. */ | |
3885 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src, | |
3886 | cpu_T[1], bound); | |
3887 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_T[1], cpu_T[1], | |
3888 | bound, bound, cpu_T[1]); | |
3889 | tcg_temp_free(bound); | |
3890 | } | |
3891 | tcg_gen_movi_tl(cpu_A0, -1); | |
3892 | tcg_gen_shl_tl(cpu_A0, cpu_A0, cpu_T[1]); | |
3893 | tcg_gen_andc_tl(cpu_T[0], cpu_T[0], cpu_A0); | |
3894 | gen_op_mov_reg_T0(ot, reg); | |
3895 | gen_op_update1_cc(); | |
3896 | set_cc_op(s, CC_OP_BMILGB + ot); | |
3897 | break; | |
3898 | ||
5f1f4b17 RH |
3899 | case 0x3f6: /* mulx By, Gy, rdx, Ey */ |
3900 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
3901 | || !(s->prefix & PREFIX_VEX) | |
3902 | || s->vex_l != 0) { | |
3903 | goto illegal_op; | |
3904 | } | |
ab4e4aec | 3905 | ot = mo_64_32(s->dflag); |
5f1f4b17 RH |
3906 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3907 | switch (ot) { | |
5f1f4b17 | 3908 | default: |
a4bcea3d RH |
3909 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3910 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EDX]); | |
3911 | tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32, | |
3912 | cpu_tmp2_i32, cpu_tmp3_i32); | |
3913 | tcg_gen_extu_i32_tl(cpu_regs[s->vex_v], cpu_tmp2_i32); | |
3914 | tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp3_i32); | |
5f1f4b17 RH |
3915 | break; |
3916 | #ifdef TARGET_X86_64 | |
4ba9938c | 3917 | case MO_64: |
a4bcea3d RH |
3918 | tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg], |
3919 | cpu_T[0], cpu_regs[R_EDX]); | |
5f1f4b17 RH |
3920 | break; |
3921 | #endif | |
3922 | } | |
3923 | break; | |
3924 | ||
0592f74a RH |
3925 | case 0x3f5: /* pdep Gy, By, Ey */ |
3926 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
3927 | || !(s->prefix & PREFIX_VEX) | |
3928 | || s->vex_l != 0) { | |
3929 | goto illegal_op; | |
3930 | } | |
ab4e4aec | 3931 | ot = mo_64_32(s->dflag); |
0592f74a RH |
3932 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3933 | /* Note that by zero-extending the mask operand, we | |
3934 | automatically handle zero-extending the result. */ | |
ab4e4aec | 3935 | if (ot == MO_64) { |
0592f74a RH |
3936 | tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]); |
3937 | } else { | |
3938 | tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]); | |
3939 | } | |
3940 | gen_helper_pdep(cpu_regs[reg], cpu_T[0], cpu_T[1]); | |
3941 | break; | |
3942 | ||
3943 | case 0x2f5: /* pext Gy, By, Ey */ | |
3944 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
3945 | || !(s->prefix & PREFIX_VEX) | |
3946 | || s->vex_l != 0) { | |
3947 | goto illegal_op; | |
3948 | } | |
ab4e4aec | 3949 | ot = mo_64_32(s->dflag); |
0592f74a RH |
3950 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3951 | /* Note that by zero-extending the mask operand, we | |
3952 | automatically handle zero-extending the result. */ | |
ab4e4aec | 3953 | if (ot == MO_64) { |
0592f74a RH |
3954 | tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]); |
3955 | } else { | |
3956 | tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]); | |
3957 | } | |
3958 | gen_helper_pext(cpu_regs[reg], cpu_T[0], cpu_T[1]); | |
3959 | break; | |
3960 | ||
cd7f97ca RH |
3961 | case 0x1f6: /* adcx Gy, Ey */ |
3962 | case 0x2f6: /* adox Gy, Ey */ | |
3963 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX)) { | |
3964 | goto illegal_op; | |
3965 | } else { | |
76f13133 | 3966 | TCGv carry_in, carry_out, zero; |
cd7f97ca RH |
3967 | int end_op; |
3968 | ||
ab4e4aec | 3969 | ot = mo_64_32(s->dflag); |
cd7f97ca RH |
3970 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
3971 | ||
3972 | /* Re-use the carry-out from a previous round. */ | |
3973 | TCGV_UNUSED(carry_in); | |
3974 | carry_out = (b == 0x1f6 ? cpu_cc_dst : cpu_cc_src2); | |
3975 | switch (s->cc_op) { | |
3976 | case CC_OP_ADCX: | |
3977 | if (b == 0x1f6) { | |
3978 | carry_in = cpu_cc_dst; | |
3979 | end_op = CC_OP_ADCX; | |
3980 | } else { | |
3981 | end_op = CC_OP_ADCOX; | |
3982 | } | |
3983 | break; | |
3984 | case CC_OP_ADOX: | |
3985 | if (b == 0x1f6) { | |
3986 | end_op = CC_OP_ADCOX; | |
3987 | } else { | |
3988 | carry_in = cpu_cc_src2; | |
3989 | end_op = CC_OP_ADOX; | |
3990 | } | |
3991 | break; | |
3992 | case CC_OP_ADCOX: | |
3993 | end_op = CC_OP_ADCOX; | |
3994 | carry_in = carry_out; | |
3995 | break; | |
3996 | default: | |
c53de1a2 | 3997 | end_op = (b == 0x1f6 ? CC_OP_ADCX : CC_OP_ADOX); |
cd7f97ca RH |
3998 | break; |
3999 | } | |
4000 | /* If we can't reuse carry-out, get it out of EFLAGS. */ | |
4001 | if (TCGV_IS_UNUSED(carry_in)) { | |
4002 | if (s->cc_op != CC_OP_ADCX && s->cc_op != CC_OP_ADOX) { | |
4003 | gen_compute_eflags(s); | |
4004 | } | |
4005 | carry_in = cpu_tmp0; | |
4006 | tcg_gen_shri_tl(carry_in, cpu_cc_src, | |
4007 | ctz32(b == 0x1f6 ? CC_C : CC_O)); | |
4008 | tcg_gen_andi_tl(carry_in, carry_in, 1); | |
4009 | } | |
4010 | ||
4011 | switch (ot) { | |
4012 | #ifdef TARGET_X86_64 | |
4ba9938c | 4013 | case MO_32: |
cd7f97ca RH |
4014 | /* If we know TL is 64-bit, and we want a 32-bit |
4015 | result, just do everything in 64-bit arithmetic. */ | |
4016 | tcg_gen_ext32u_i64(cpu_regs[reg], cpu_regs[reg]); | |
4017 | tcg_gen_ext32u_i64(cpu_T[0], cpu_T[0]); | |
4018 | tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_regs[reg]); | |
4019 | tcg_gen_add_i64(cpu_T[0], cpu_T[0], carry_in); | |
4020 | tcg_gen_ext32u_i64(cpu_regs[reg], cpu_T[0]); | |
4021 | tcg_gen_shri_i64(carry_out, cpu_T[0], 32); | |
4022 | break; | |
4023 | #endif | |
4024 | default: | |
4025 | /* Otherwise compute the carry-out in two steps. */ | |
76f13133 RH |
4026 | zero = tcg_const_tl(0); |
4027 | tcg_gen_add2_tl(cpu_T[0], carry_out, | |
4028 | cpu_T[0], zero, | |
4029 | carry_in, zero); | |
4030 | tcg_gen_add2_tl(cpu_regs[reg], carry_out, | |
4031 | cpu_regs[reg], carry_out, | |
4032 | cpu_T[0], zero); | |
4033 | tcg_temp_free(zero); | |
cd7f97ca RH |
4034 | break; |
4035 | } | |
cd7f97ca RH |
4036 | set_cc_op(s, end_op); |
4037 | } | |
4038 | break; | |
4039 | ||
4a554890 RH |
4040 | case 0x1f7: /* shlx Gy, Ey, By */ |
4041 | case 0x2f7: /* sarx Gy, Ey, By */ | |
4042 | case 0x3f7: /* shrx Gy, Ey, By */ | |
4043 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
4044 | || !(s->prefix & PREFIX_VEX) | |
4045 | || s->vex_l != 0) { | |
4046 | goto illegal_op; | |
4047 | } | |
ab4e4aec | 4048 | ot = mo_64_32(s->dflag); |
4a554890 | 4049 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
4ba9938c | 4050 | if (ot == MO_64) { |
4a554890 RH |
4051 | tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63); |
4052 | } else { | |
4053 | tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 31); | |
4054 | } | |
4055 | if (b == 0x1f7) { | |
4056 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4057 | } else if (b == 0x2f7) { | |
4ba9938c | 4058 | if (ot != MO_64) { |
4a554890 RH |
4059 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4060 | } | |
4061 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4062 | } else { | |
4ba9938c | 4063 | if (ot != MO_64) { |
4a554890 RH |
4064 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
4065 | } | |
4066 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4067 | } | |
4068 | gen_op_mov_reg_T0(ot, reg); | |
4069 | break; | |
4070 | ||
bc4b43dc RH |
4071 | case 0x0f3: |
4072 | case 0x1f3: | |
4073 | case 0x2f3: | |
4074 | case 0x3f3: /* Group 17 */ | |
4075 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1) | |
4076 | || !(s->prefix & PREFIX_VEX) | |
4077 | || s->vex_l != 0) { | |
4078 | goto illegal_op; | |
4079 | } | |
ab4e4aec | 4080 | ot = mo_64_32(s->dflag); |
bc4b43dc RH |
4081 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
4082 | ||
4083 | switch (reg & 7) { | |
4084 | case 1: /* blsr By,Ey */ | |
4085 | tcg_gen_neg_tl(cpu_T[1], cpu_T[0]); | |
4086 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4087 | gen_op_mov_reg_T0(ot, s->vex_v); | |
4088 | gen_op_update2_cc(); | |
4089 | set_cc_op(s, CC_OP_BMILGB + ot); | |
4090 | break; | |
4091 | ||
4092 | case 2: /* blsmsk By,Ey */ | |
4093 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4094 | tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1); | |
4095 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_cc_src); | |
4096 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4097 | set_cc_op(s, CC_OP_BMILGB + ot); | |
4098 | break; | |
4099 | ||
4100 | case 3: /* blsi By, Ey */ | |
4101 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4102 | tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1); | |
4103 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_cc_src); | |
4104 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4105 | set_cc_op(s, CC_OP_BMILGB + ot); | |
4106 | break; | |
4107 | ||
4108 | default: | |
4109 | goto illegal_op; | |
4110 | } | |
4111 | break; | |
4112 | ||
111994ee RH |
4113 | default: |
4114 | goto illegal_op; | |
4115 | } | |
222a3336 | 4116 | break; |
111994ee | 4117 | |
222a3336 AZ |
4118 | case 0x03a: |
4119 | case 0x13a: | |
4242b1bd | 4120 | b = modrm; |
0af10c86 | 4121 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
4122 | rm = modrm & 7; |
4123 | reg = ((modrm >> 3) & 7) | rex_r; | |
4124 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
4125 | if (b1 >= 2) { |
4126 | goto illegal_op; | |
4127 | } | |
4242b1bd | 4128 | |
d3eb5eae BS |
4129 | sse_fn_eppi = sse_op_table7[b].op[b1]; |
4130 | if (!sse_fn_eppi) { | |
4242b1bd | 4131 | goto illegal_op; |
c4baa050 | 4132 | } |
222a3336 AZ |
4133 | if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) |
4134 | goto illegal_op; | |
4135 | ||
d3eb5eae | 4136 | if (sse_fn_eppi == SSE_SPECIAL) { |
ab4e4aec | 4137 | ot = mo_64_32(s->dflag); |
222a3336 AZ |
4138 | rm = (modrm & 7) | REX_B(s); |
4139 | if (mod != 3) | |
4eeb3939 | 4140 | gen_lea_modrm(env, s, modrm); |
222a3336 | 4141 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 4142 | val = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
4143 | switch (b) { |
4144 | case 0x14: /* pextrb */ | |
4145 | tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
4146 | xmm_regs[reg].XMM_B(val & 15))); | |
3523e4bd | 4147 | if (mod == 3) { |
222a3336 | 4148 | gen_op_mov_reg_T0(ot, rm); |
3523e4bd RH |
4149 | } else { |
4150 | tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0, | |
4151 | s->mem_index, MO_UB); | |
4152 | } | |
222a3336 AZ |
4153 | break; |
4154 | case 0x15: /* pextrw */ | |
4155 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
4156 | xmm_regs[reg].XMM_W(val & 7))); | |
3523e4bd | 4157 | if (mod == 3) { |
222a3336 | 4158 | gen_op_mov_reg_T0(ot, rm); |
3523e4bd RH |
4159 | } else { |
4160 | tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0, | |
4161 | s->mem_index, MO_LEUW); | |
4162 | } | |
222a3336 AZ |
4163 | break; |
4164 | case 0x16: | |
4ba9938c | 4165 | if (ot == MO_32) { /* pextrd */ |
222a3336 AZ |
4166 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
4167 | offsetof(CPUX86State, | |
4168 | xmm_regs[reg].XMM_L(val & 3))); | |
3523e4bd | 4169 | if (mod == 3) { |
a7fbcbe5 | 4170 | tcg_gen_extu_i32_tl(cpu_regs[rm], cpu_tmp2_i32); |
3523e4bd | 4171 | } else { |
d5601ad0 RH |
4172 | tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, |
4173 | s->mem_index, MO_LEUL); | |
3523e4bd | 4174 | } |
222a3336 | 4175 | } else { /* pextrq */ |
a7812ae4 | 4176 | #ifdef TARGET_X86_64 |
222a3336 AZ |
4177 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
4178 | offsetof(CPUX86State, | |
4179 | xmm_regs[reg].XMM_Q(val & 1))); | |
3523e4bd | 4180 | if (mod == 3) { |
a7fbcbe5 | 4181 | tcg_gen_mov_i64(cpu_regs[rm], cpu_tmp1_i64); |
3523e4bd RH |
4182 | } else { |
4183 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, | |
4184 | s->mem_index, MO_LEQ); | |
4185 | } | |
a7812ae4 PB |
4186 | #else |
4187 | goto illegal_op; | |
4188 | #endif | |
222a3336 AZ |
4189 | } |
4190 | break; | |
4191 | case 0x17: /* extractps */ | |
4192 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
4193 | xmm_regs[reg].XMM_L(val & 3))); | |
3523e4bd | 4194 | if (mod == 3) { |
222a3336 | 4195 | gen_op_mov_reg_T0(ot, rm); |
3523e4bd RH |
4196 | } else { |
4197 | tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0, | |
4198 | s->mem_index, MO_LEUL); | |
4199 | } | |
222a3336 AZ |
4200 | break; |
4201 | case 0x20: /* pinsrb */ | |
3c5f4116 | 4202 | if (mod == 3) { |
4ba9938c | 4203 | gen_op_mov_TN_reg(MO_32, 0, rm); |
3c5f4116 RH |
4204 | } else { |
4205 | tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, | |
4206 | s->mem_index, MO_UB); | |
4207 | } | |
34c6addd | 4208 | tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, |
222a3336 AZ |
4209 | xmm_regs[reg].XMM_B(val & 15))); |
4210 | break; | |
4211 | case 0x21: /* insertps */ | |
a7812ae4 | 4212 | if (mod == 3) { |
222a3336 AZ |
4213 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
4214 | offsetof(CPUX86State,xmm_regs[rm] | |
4215 | .XMM_L((val >> 6) & 3))); | |
a7812ae4 | 4216 | } else { |
3c5f4116 RH |
4217 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
4218 | s->mem_index, MO_LEUL); | |
a7812ae4 | 4219 | } |
222a3336 AZ |
4220 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
4221 | offsetof(CPUX86State,xmm_regs[reg] | |
4222 | .XMM_L((val >> 4) & 3))); | |
4223 | if ((val >> 0) & 1) | |
4224 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4225 | cpu_env, offsetof(CPUX86State, | |
4226 | xmm_regs[reg].XMM_L(0))); | |
4227 | if ((val >> 1) & 1) | |
4228 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4229 | cpu_env, offsetof(CPUX86State, | |
4230 | xmm_regs[reg].XMM_L(1))); | |
4231 | if ((val >> 2) & 1) | |
4232 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4233 | cpu_env, offsetof(CPUX86State, | |
4234 | xmm_regs[reg].XMM_L(2))); | |
4235 | if ((val >> 3) & 1) | |
4236 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4237 | cpu_env, offsetof(CPUX86State, | |
4238 | xmm_regs[reg].XMM_L(3))); | |
4239 | break; | |
4240 | case 0x22: | |
4ba9938c | 4241 | if (ot == MO_32) { /* pinsrd */ |
3c5f4116 | 4242 | if (mod == 3) { |
80b02013 | 4243 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[rm]); |
3c5f4116 | 4244 | } else { |
80b02013 RH |
4245 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
4246 | s->mem_index, MO_LEUL); | |
3c5f4116 | 4247 | } |
222a3336 AZ |
4248 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
4249 | offsetof(CPUX86State, | |
4250 | xmm_regs[reg].XMM_L(val & 3))); | |
4251 | } else { /* pinsrq */ | |
a7812ae4 | 4252 | #ifdef TARGET_X86_64 |
3c5f4116 | 4253 | if (mod == 3) { |
222a3336 | 4254 | gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); |
3c5f4116 RH |
4255 | } else { |
4256 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, | |
4257 | s->mem_index, MO_LEQ); | |
4258 | } | |
222a3336 AZ |
4259 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
4260 | offsetof(CPUX86State, | |
4261 | xmm_regs[reg].XMM_Q(val & 1))); | |
a7812ae4 PB |
4262 | #else |
4263 | goto illegal_op; | |
4264 | #endif | |
222a3336 AZ |
4265 | } |
4266 | break; | |
4267 | } | |
4268 | return; | |
4269 | } | |
4242b1bd AZ |
4270 | |
4271 | if (b1) { | |
4272 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4273 | if (mod == 3) { | |
4274 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
4275 | } else { | |
4276 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
4eeb3939 | 4277 | gen_lea_modrm(env, s, modrm); |
323d1876 | 4278 | gen_ldo_env_A0(s, op2_offset); |
4242b1bd AZ |
4279 | } |
4280 | } else { | |
4281 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4282 | if (mod == 3) { | |
4283 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4284 | } else { | |
4285 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
4eeb3939 | 4286 | gen_lea_modrm(env, s, modrm); |
323d1876 | 4287 | gen_ldq_env_A0(s, op2_offset); |
4242b1bd AZ |
4288 | } |
4289 | } | |
0af10c86 | 4290 | val = cpu_ldub_code(env, s->pc++); |
4242b1bd | 4291 | |
222a3336 | 4292 | if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ |
3ca51d07 | 4293 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 | 4294 | |
ab4e4aec | 4295 | if (s->dflag == MO_64) { |
222a3336 AZ |
4296 | /* The helper must use entire 64-bit gp registers */ |
4297 | val |= 1 << 8; | |
ab4e4aec | 4298 | } |
222a3336 AZ |
4299 | } |
4300 | ||
4242b1bd AZ |
4301 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4302 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4303 | sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
4242b1bd | 4304 | break; |
e2c3c2c5 RH |
4305 | |
4306 | case 0x33a: | |
4307 | /* Various integer extensions at 0f 3a f[0-f]. */ | |
4308 | b = modrm | (b1 << 8); | |
4309 | modrm = cpu_ldub_code(env, s->pc++); | |
4310 | reg = ((modrm >> 3) & 7) | rex_r; | |
4311 | ||
4312 | switch (b) { | |
4313 | case 0x3f0: /* rorx Gy,Ey, Ib */ | |
4314 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2) | |
4315 | || !(s->prefix & PREFIX_VEX) | |
4316 | || s->vex_l != 0) { | |
4317 | goto illegal_op; | |
4318 | } | |
ab4e4aec | 4319 | ot = mo_64_32(s->dflag); |
e2c3c2c5 RH |
4320 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
4321 | b = cpu_ldub_code(env, s->pc++); | |
4ba9938c | 4322 | if (ot == MO_64) { |
e2c3c2c5 RH |
4323 | tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], b & 63); |
4324 | } else { | |
4325 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
4326 | tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, b & 31); | |
4327 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); | |
4328 | } | |
4329 | gen_op_mov_reg_T0(ot, reg); | |
4330 | break; | |
4331 | ||
4332 | default: | |
4333 | goto illegal_op; | |
4334 | } | |
4335 | break; | |
4336 | ||
664e0f19 FB |
4337 | default: |
4338 | goto illegal_op; | |
4339 | } | |
4340 | } else { | |
4341 | /* generic MMX or SSE operation */ | |
d1e42c5c | 4342 | switch(b) { |
d1e42c5c FB |
4343 | case 0x70: /* pshufx insn */ |
4344 | case 0xc6: /* pshufx insn */ | |
4345 | case 0xc2: /* compare insns */ | |
4346 | s->rip_offset = 1; | |
4347 | break; | |
4348 | default: | |
4349 | break; | |
664e0f19 FB |
4350 | } |
4351 | if (is_xmm) { | |
4352 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4353 | if (mod != 3) { | |
4eeb3939 | 4354 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 4355 | op2_offset = offsetof(CPUX86State,xmm_t0); |
480c1cdb | 4356 | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
664e0f19 FB |
4357 | b == 0xc2)) { |
4358 | /* specific case for SSE single instructions */ | |
4359 | if (b1 == 2) { | |
4360 | /* 32 bit access */ | |
909be183 | 4361 | gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); |
651ba608 | 4362 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 FB |
4363 | } else { |
4364 | /* 64 bit access */ | |
323d1876 RH |
4365 | gen_ldq_env_A0(s, offsetof(CPUX86State, |
4366 | xmm_t0.XMM_D(0))); | |
664e0f19 FB |
4367 | } |
4368 | } else { | |
323d1876 | 4369 | gen_ldo_env_A0(s, op2_offset); |
664e0f19 FB |
4370 | } |
4371 | } else { | |
4372 | rm = (modrm & 7) | REX_B(s); | |
4373 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
4374 | } | |
4375 | } else { | |
4376 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4377 | if (mod != 3) { | |
4eeb3939 | 4378 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 4379 | op2_offset = offsetof(CPUX86State,mmx_t0); |
323d1876 | 4380 | gen_ldq_env_A0(s, op2_offset); |
664e0f19 FB |
4381 | } else { |
4382 | rm = (modrm & 7); | |
4383 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4384 | } | |
4385 | } | |
4386 | switch(b) { | |
a35f3ec7 | 4387 | case 0x0f: /* 3DNow! data insns */ |
e771edab AJ |
4388 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) |
4389 | goto illegal_op; | |
0af10c86 | 4390 | val = cpu_ldub_code(env, s->pc++); |
d3eb5eae BS |
4391 | sse_fn_epp = sse_op_table5[val]; |
4392 | if (!sse_fn_epp) { | |
a35f3ec7 | 4393 | goto illegal_op; |
c4baa050 | 4394 | } |
5af45186 FB |
4395 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4396 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4397 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
a35f3ec7 | 4398 | break; |
664e0f19 FB |
4399 | case 0x70: /* pshufx insn */ |
4400 | case 0xc6: /* pshufx insn */ | |
0af10c86 | 4401 | val = cpu_ldub_code(env, s->pc++); |
5af45186 FB |
4402 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4403 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4404 | /* XXX: introduce a new table? */ |
d3eb5eae | 4405 | sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp; |
c4baa050 | 4406 | sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
664e0f19 FB |
4407 | break; |
4408 | case 0xc2: | |
4409 | /* compare insns */ | |
0af10c86 | 4410 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
4411 | if (val >= 8) |
4412 | goto illegal_op; | |
d3eb5eae | 4413 | sse_fn_epp = sse_op_table4[val][b1]; |
c4baa050 | 4414 | |
5af45186 FB |
4415 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4416 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4417 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 | 4418 | break; |
b8b6a50b FB |
4419 | case 0xf7: |
4420 | /* maskmov : we must prepare A0 */ | |
4421 | if (mod != 3) | |
4422 | goto illegal_op; | |
1d71ddb1 RH |
4423 | tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EDI]); |
4424 | gen_extu(s->aflag, cpu_A0); | |
b8b6a50b FB |
4425 | gen_add_A0_ds_seg(s); |
4426 | ||
4427 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); | |
4428 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4429 | /* XXX: introduce a new table? */ |
d3eb5eae BS |
4430 | sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp; |
4431 | sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0); | |
b8b6a50b | 4432 | break; |
664e0f19 | 4433 | default: |
5af45186 FB |
4434 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4435 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4436 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
4437 | break; |
4438 | } | |
4439 | if (b == 0x2e || b == 0x2f) { | |
3ca51d07 | 4440 | set_cc_op(s, CC_OP_EFLAGS); |
664e0f19 FB |
4441 | } |
4442 | } | |
4443 | } | |
4444 | ||
2c0262af FB |
4445 | /* convert one instruction. s->is_jmp is set if the translation must |
4446 | be stopped. Return the next pc value */ | |
0af10c86 BS |
4447 | static target_ulong disas_insn(CPUX86State *env, DisasContext *s, |
4448 | target_ulong pc_start) | |
2c0262af | 4449 | { |
ab4e4aec | 4450 | int b, prefixes; |
d67dc9e6 | 4451 | int shift; |
ab4e4aec | 4452 | TCGMemOp ot, aflag, dflag; |
4eeb3939 | 4453 | int modrm, reg, rm, mod, op, opreg, val; |
14ce26e7 FB |
4454 | target_ulong next_eip, tval; |
4455 | int rex_w, rex_r; | |
2c0262af | 4456 | |
fdefe51c | 4457 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
70cff25e | 4458 | tcg_gen_debug_insn_start(pc_start); |
fdefe51c | 4459 | } |
2c0262af FB |
4460 | s->pc = pc_start; |
4461 | prefixes = 0; | |
2c0262af | 4462 | s->override = -1; |
14ce26e7 FB |
4463 | rex_w = -1; |
4464 | rex_r = 0; | |
4465 | #ifdef TARGET_X86_64 | |
4466 | s->rex_x = 0; | |
4467 | s->rex_b = 0; | |
5fafdf24 | 4468 | x86_64_hregs = 0; |
14ce26e7 FB |
4469 | #endif |
4470 | s->rip_offset = 0; /* for relative ip address */ | |
701ed211 RH |
4471 | s->vex_l = 0; |
4472 | s->vex_v = 0; | |
2c0262af | 4473 | next_byte: |
0af10c86 | 4474 | b = cpu_ldub_code(env, s->pc); |
2c0262af | 4475 | s->pc++; |
4a6fd938 RH |
4476 | /* Collect prefixes. */ |
4477 | switch (b) { | |
4478 | case 0xf3: | |
4479 | prefixes |= PREFIX_REPZ; | |
4480 | goto next_byte; | |
4481 | case 0xf2: | |
4482 | prefixes |= PREFIX_REPNZ; | |
4483 | goto next_byte; | |
4484 | case 0xf0: | |
4485 | prefixes |= PREFIX_LOCK; | |
4486 | goto next_byte; | |
4487 | case 0x2e: | |
4488 | s->override = R_CS; | |
4489 | goto next_byte; | |
4490 | case 0x36: | |
4491 | s->override = R_SS; | |
4492 | goto next_byte; | |
4493 | case 0x3e: | |
4494 | s->override = R_DS; | |
4495 | goto next_byte; | |
4496 | case 0x26: | |
4497 | s->override = R_ES; | |
4498 | goto next_byte; | |
4499 | case 0x64: | |
4500 | s->override = R_FS; | |
4501 | goto next_byte; | |
4502 | case 0x65: | |
4503 | s->override = R_GS; | |
4504 | goto next_byte; | |
4505 | case 0x66: | |
4506 | prefixes |= PREFIX_DATA; | |
4507 | goto next_byte; | |
4508 | case 0x67: | |
4509 | prefixes |= PREFIX_ADR; | |
4510 | goto next_byte; | |
14ce26e7 | 4511 | #ifdef TARGET_X86_64 |
4a6fd938 RH |
4512 | case 0x40 ... 0x4f: |
4513 | if (CODE64(s)) { | |
14ce26e7 FB |
4514 | /* REX prefix */ |
4515 | rex_w = (b >> 3) & 1; | |
4516 | rex_r = (b & 0x4) << 1; | |
4517 | s->rex_x = (b & 0x2) << 2; | |
4518 | REX_B(s) = (b & 0x1) << 3; | |
4519 | x86_64_hregs = 1; /* select uniform byte register addressing */ | |
4520 | goto next_byte; | |
4521 | } | |
4a6fd938 RH |
4522 | break; |
4523 | #endif | |
701ed211 RH |
4524 | case 0xc5: /* 2-byte VEX */ |
4525 | case 0xc4: /* 3-byte VEX */ | |
4526 | /* VEX prefixes cannot be used except in 32-bit mode. | |
4527 | Otherwise the instruction is LES or LDS. */ | |
4528 | if (s->code32 && !s->vm86) { | |
4529 | static const int pp_prefix[4] = { | |
4530 | 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ | |
4531 | }; | |
4532 | int vex3, vex2 = cpu_ldub_code(env, s->pc); | |
4533 | ||
4534 | if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) { | |
4535 | /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b, | |
4536 | otherwise the instruction is LES or LDS. */ | |
4537 | break; | |
4538 | } | |
4539 | s->pc++; | |
4540 | ||
085d8134 | 4541 | /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */ |
701ed211 RH |
4542 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ |
4543 | | PREFIX_LOCK | PREFIX_DATA)) { | |
4544 | goto illegal_op; | |
4545 | } | |
4546 | #ifdef TARGET_X86_64 | |
4547 | if (x86_64_hregs) { | |
4548 | goto illegal_op; | |
4549 | } | |
4550 | #endif | |
4551 | rex_r = (~vex2 >> 4) & 8; | |
4552 | if (b == 0xc5) { | |
4553 | vex3 = vex2; | |
4554 | b = cpu_ldub_code(env, s->pc++); | |
4555 | } else { | |
4556 | #ifdef TARGET_X86_64 | |
4557 | s->rex_x = (~vex2 >> 3) & 8; | |
4558 | s->rex_b = (~vex2 >> 2) & 8; | |
4559 | #endif | |
4560 | vex3 = cpu_ldub_code(env, s->pc++); | |
4561 | rex_w = (vex3 >> 7) & 1; | |
4562 | switch (vex2 & 0x1f) { | |
4563 | case 0x01: /* Implied 0f leading opcode bytes. */ | |
4564 | b = cpu_ldub_code(env, s->pc++) | 0x100; | |
4565 | break; | |
4566 | case 0x02: /* Implied 0f 38 leading opcode bytes. */ | |
4567 | b = 0x138; | |
4568 | break; | |
4569 | case 0x03: /* Implied 0f 3a leading opcode bytes. */ | |
4570 | b = 0x13a; | |
4571 | break; | |
4572 | default: /* Reserved for future use. */ | |
4573 | goto illegal_op; | |
4574 | } | |
4575 | } | |
4576 | s->vex_v = (~vex3 >> 3) & 0xf; | |
4577 | s->vex_l = (vex3 >> 2) & 1; | |
4578 | prefixes |= pp_prefix[vex3 & 3] | PREFIX_VEX; | |
4579 | } | |
4580 | break; | |
4a6fd938 RH |
4581 | } |
4582 | ||
4583 | /* Post-process prefixes. */ | |
4a6fd938 | 4584 | if (CODE64(s)) { |
dec3fc96 RH |
4585 | /* In 64-bit mode, the default data size is 32-bit. Select 64-bit |
4586 | data with rex_w, and 16-bit data with 0x66; rex_w takes precedence | |
4587 | over 0x66 if both are present. */ | |
ab4e4aec | 4588 | dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32); |
dec3fc96 | 4589 | /* In 64-bit mode, 0x67 selects 32-bit addressing. */ |
1d71ddb1 | 4590 | aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64); |
dec3fc96 RH |
4591 | } else { |
4592 | /* In 16/32-bit mode, 0x66 selects the opposite data size. */ | |
ab4e4aec RH |
4593 | if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) { |
4594 | dflag = MO_32; | |
4595 | } else { | |
4596 | dflag = MO_16; | |
14ce26e7 | 4597 | } |
dec3fc96 | 4598 | /* In 16/32-bit mode, 0x67 selects the opposite addressing. */ |
1d71ddb1 RH |
4599 | if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) { |
4600 | aflag = MO_32; | |
4601 | } else { | |
4602 | aflag = MO_16; | |
14ce26e7 | 4603 | } |
2c0262af FB |
4604 | } |
4605 | ||
2c0262af FB |
4606 | s->prefix = prefixes; |
4607 | s->aflag = aflag; | |
4608 | s->dflag = dflag; | |
4609 | ||
4610 | /* lock generation */ | |
4611 | if (prefixes & PREFIX_LOCK) | |
a7812ae4 | 4612 | gen_helper_lock(); |
2c0262af FB |
4613 | |
4614 | /* now check op code */ | |
4615 | reswitch: | |
4616 | switch(b) { | |
4617 | case 0x0f: | |
4618 | /**************************/ | |
4619 | /* extended op code */ | |
0af10c86 | 4620 | b = cpu_ldub_code(env, s->pc++) | 0x100; |
2c0262af | 4621 | goto reswitch; |
3b46e624 | 4622 | |
2c0262af FB |
4623 | /**************************/ |
4624 | /* arith & logic */ | |
4625 | case 0x00 ... 0x05: | |
4626 | case 0x08 ... 0x0d: | |
4627 | case 0x10 ... 0x15: | |
4628 | case 0x18 ... 0x1d: | |
4629 | case 0x20 ... 0x25: | |
4630 | case 0x28 ... 0x2d: | |
4631 | case 0x30 ... 0x35: | |
4632 | case 0x38 ... 0x3d: | |
4633 | { | |
4634 | int op, f, val; | |
4635 | op = (b >> 3) & 7; | |
4636 | f = (b >> 1) & 3; | |
4637 | ||
ab4e4aec | 4638 | ot = mo_b_d(b, dflag); |
3b46e624 | 4639 | |
2c0262af FB |
4640 | switch(f) { |
4641 | case 0: /* OP Ev, Gv */ | |
0af10c86 | 4642 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4643 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 4644 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4645 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4646 | if (mod != 3) { |
4eeb3939 | 4647 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
4648 | opreg = OR_TMP0; |
4649 | } else if (op == OP_XORL && rm == reg) { | |
4650 | xor_zero: | |
4651 | /* xor reg, reg optimisation */ | |
436ff2d2 | 4652 | set_cc_op(s, CC_OP_CLR); |
97212c88 | 4653 | tcg_gen_movi_tl(cpu_T[0], 0); |
57fec1fe | 4654 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
4655 | break; |
4656 | } else { | |
4657 | opreg = rm; | |
4658 | } | |
57fec1fe | 4659 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4660 | gen_op(s, op, ot, opreg); |
4661 | break; | |
4662 | case 1: /* OP Gv, Ev */ | |
0af10c86 | 4663 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4664 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
4665 | reg = ((modrm >> 3) & 7) | rex_r; |
4666 | rm = (modrm & 7) | REX_B(s); | |
2c0262af | 4667 | if (mod != 3) { |
4eeb3939 | 4668 | gen_lea_modrm(env, s, modrm); |
0f712e10 | 4669 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
2c0262af FB |
4670 | } else if (op == OP_XORL && rm == reg) { |
4671 | goto xor_zero; | |
4672 | } else { | |
57fec1fe | 4673 | gen_op_mov_TN_reg(ot, 1, rm); |
2c0262af FB |
4674 | } |
4675 | gen_op(s, op, ot, reg); | |
4676 | break; | |
4677 | case 2: /* OP A, Iv */ | |
0af10c86 | 4678 | val = insn_get(env, s, ot); |
0ae657b1 | 4679 | tcg_gen_movi_tl(cpu_T[1], val); |
2c0262af FB |
4680 | gen_op(s, op, ot, OR_EAX); |
4681 | break; | |
4682 | } | |
4683 | } | |
4684 | break; | |
4685 | ||
ec9d6075 FB |
4686 | case 0x82: |
4687 | if (CODE64(s)) | |
4688 | goto illegal_op; | |
2c0262af FB |
4689 | case 0x80: /* GRP1 */ |
4690 | case 0x81: | |
4691 | case 0x83: | |
4692 | { | |
4693 | int val; | |
4694 | ||
ab4e4aec | 4695 | ot = mo_b_d(b, dflag); |
3b46e624 | 4696 | |
0af10c86 | 4697 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4698 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4699 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4700 | op = (modrm >> 3) & 7; |
3b46e624 | 4701 | |
2c0262af | 4702 | if (mod != 3) { |
14ce26e7 FB |
4703 | if (b == 0x83) |
4704 | s->rip_offset = 1; | |
4705 | else | |
4706 | s->rip_offset = insn_const_size(ot); | |
4eeb3939 | 4707 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
4708 | opreg = OR_TMP0; |
4709 | } else { | |
14ce26e7 | 4710 | opreg = rm; |
2c0262af FB |
4711 | } |
4712 | ||
4713 | switch(b) { | |
4714 | default: | |
4715 | case 0x80: | |
4716 | case 0x81: | |
d64477af | 4717 | case 0x82: |
0af10c86 | 4718 | val = insn_get(env, s, ot); |
2c0262af FB |
4719 | break; |
4720 | case 0x83: | |
4ba9938c | 4721 | val = (int8_t)insn_get(env, s, MO_8); |
2c0262af FB |
4722 | break; |
4723 | } | |
0ae657b1 | 4724 | tcg_gen_movi_tl(cpu_T[1], val); |
2c0262af FB |
4725 | gen_op(s, op, ot, opreg); |
4726 | } | |
4727 | break; | |
4728 | ||
4729 | /**************************/ | |
4730 | /* inc, dec, and other misc arith */ | |
4731 | case 0x40 ... 0x47: /* inc Gv */ | |
ab4e4aec | 4732 | ot = dflag; |
2c0262af FB |
4733 | gen_inc(s, ot, OR_EAX + (b & 7), 1); |
4734 | break; | |
4735 | case 0x48 ... 0x4f: /* dec Gv */ | |
ab4e4aec | 4736 | ot = dflag; |
2c0262af FB |
4737 | gen_inc(s, ot, OR_EAX + (b & 7), -1); |
4738 | break; | |
4739 | case 0xf6: /* GRP3 */ | |
4740 | case 0xf7: | |
ab4e4aec | 4741 | ot = mo_b_d(b, dflag); |
2c0262af | 4742 | |
0af10c86 | 4743 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4744 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4745 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4746 | op = (modrm >> 3) & 7; |
4747 | if (mod != 3) { | |
14ce26e7 FB |
4748 | if (op == 0) |
4749 | s->rip_offset = insn_const_size(ot); | |
4eeb3939 | 4750 | gen_lea_modrm(env, s, modrm); |
909be183 | 4751 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 4752 | } else { |
57fec1fe | 4753 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4754 | } |
4755 | ||
4756 | switch(op) { | |
4757 | case 0: /* test */ | |
0af10c86 | 4758 | val = insn_get(env, s, ot); |
0ae657b1 | 4759 | tcg_gen_movi_tl(cpu_T[1], val); |
2c0262af | 4760 | gen_op_testl_T0_T1_cc(); |
3ca51d07 | 4761 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af FB |
4762 | break; |
4763 | case 2: /* not */ | |
b6abf97d | 4764 | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4765 | if (mod != 3) { |
fd8ca9f6 | 4766 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 4767 | } else { |
57fec1fe | 4768 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4769 | } |
4770 | break; | |
4771 | case 3: /* neg */ | |
b6abf97d | 4772 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4773 | if (mod != 3) { |
fd8ca9f6 | 4774 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 4775 | } else { |
57fec1fe | 4776 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4777 | } |
4778 | gen_op_update_neg_cc(); | |
3ca51d07 | 4779 | set_cc_op(s, CC_OP_SUBB + ot); |
2c0262af FB |
4780 | break; |
4781 | case 4: /* mul */ | |
4782 | switch(ot) { | |
4ba9938c RH |
4783 | case MO_8: |
4784 | gen_op_mov_TN_reg(MO_8, 1, R_EAX); | |
0211e5af FB |
4785 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
4786 | tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); | |
4787 | /* XXX: use 32 bit mul which could be faster */ | |
4788 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4ba9938c | 4789 | gen_op_mov_reg_T0(MO_16, R_EAX); |
0211e5af FB |
4790 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
4791 | tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); | |
3ca51d07 | 4792 | set_cc_op(s, CC_OP_MULB); |
2c0262af | 4793 | break; |
4ba9938c RH |
4794 | case MO_16: |
4795 | gen_op_mov_TN_reg(MO_16, 1, R_EAX); | |
0211e5af FB |
4796 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
4797 | tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); | |
4798 | /* XXX: use 32 bit mul which could be faster */ | |
4799 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4ba9938c | 4800 | gen_op_mov_reg_T0(MO_16, R_EAX); |
0211e5af FB |
4801 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
4802 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4ba9938c | 4803 | gen_op_mov_reg_T0(MO_16, R_EDX); |
0211e5af | 4804 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
3ca51d07 | 4805 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4806 | break; |
4807 | default: | |
4ba9938c | 4808 | case MO_32: |
a4bcea3d RH |
4809 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
4810 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]); | |
4811 | tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32, | |
4812 | cpu_tmp2_i32, cpu_tmp3_i32); | |
4813 | tcg_gen_extu_i32_tl(cpu_regs[R_EAX], cpu_tmp2_i32); | |
4814 | tcg_gen_extu_i32_tl(cpu_regs[R_EDX], cpu_tmp3_i32); | |
4815 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]); | |
4816 | tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]); | |
3ca51d07 | 4817 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4818 | break; |
14ce26e7 | 4819 | #ifdef TARGET_X86_64 |
4ba9938c | 4820 | case MO_64: |
a4bcea3d RH |
4821 | tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX], |
4822 | cpu_T[0], cpu_regs[R_EAX]); | |
4823 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]); | |
4824 | tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]); | |
3ca51d07 | 4825 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4826 | break; |
4827 | #endif | |
2c0262af | 4828 | } |
2c0262af FB |
4829 | break; |
4830 | case 5: /* imul */ | |
4831 | switch(ot) { | |
4ba9938c RH |
4832 | case MO_8: |
4833 | gen_op_mov_TN_reg(MO_8, 1, R_EAX); | |
0211e5af FB |
4834 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
4835 | tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); | |
4836 | /* XXX: use 32 bit mul which could be faster */ | |
4837 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4ba9938c | 4838 | gen_op_mov_reg_T0(MO_16, R_EAX); |
0211e5af FB |
4839 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
4840 | tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]); | |
4841 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
3ca51d07 | 4842 | set_cc_op(s, CC_OP_MULB); |
2c0262af | 4843 | break; |
4ba9938c RH |
4844 | case MO_16: |
4845 | gen_op_mov_TN_reg(MO_16, 1, R_EAX); | |
0211e5af FB |
4846 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4847 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4848 | /* XXX: use 32 bit mul which could be faster */ | |
4849 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4ba9938c | 4850 | gen_op_mov_reg_T0(MO_16, R_EAX); |
0211e5af FB |
4851 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
4852 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4853 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4854 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4ba9938c | 4855 | gen_op_mov_reg_T0(MO_16, R_EDX); |
3ca51d07 | 4856 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4857 | break; |
4858 | default: | |
4ba9938c | 4859 | case MO_32: |
a4bcea3d RH |
4860 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
4861 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]); | |
4862 | tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32, | |
4863 | cpu_tmp2_i32, cpu_tmp3_i32); | |
4864 | tcg_gen_extu_i32_tl(cpu_regs[R_EAX], cpu_tmp2_i32); | |
4865 | tcg_gen_extu_i32_tl(cpu_regs[R_EDX], cpu_tmp3_i32); | |
4866 | tcg_gen_sari_i32(cpu_tmp2_i32, cpu_tmp2_i32, 31); | |
4867 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]); | |
4868 | tcg_gen_sub_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); | |
4869 | tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32); | |
3ca51d07 | 4870 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4871 | break; |
14ce26e7 | 4872 | #ifdef TARGET_X86_64 |
4ba9938c | 4873 | case MO_64: |
a4bcea3d RH |
4874 | tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX], |
4875 | cpu_T[0], cpu_regs[R_EAX]); | |
4876 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]); | |
4877 | tcg_gen_sari_tl(cpu_cc_src, cpu_regs[R_EAX], 63); | |
4878 | tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_regs[R_EDX]); | |
3ca51d07 | 4879 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4880 | break; |
4881 | #endif | |
2c0262af | 4882 | } |
2c0262af FB |
4883 | break; |
4884 | case 6: /* div */ | |
4885 | switch(ot) { | |
4ba9938c | 4886 | case MO_8: |
14ce26e7 | 4887 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4888 | gen_helper_divb_AL(cpu_env, cpu_T[0]); |
2c0262af | 4889 | break; |
4ba9938c | 4890 | case MO_16: |
14ce26e7 | 4891 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4892 | gen_helper_divw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4893 | break; |
4894 | default: | |
4ba9938c | 4895 | case MO_32: |
14ce26e7 | 4896 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4897 | gen_helper_divl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4898 | break; |
4899 | #ifdef TARGET_X86_64 | |
4ba9938c | 4900 | case MO_64: |
14ce26e7 | 4901 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4902 | gen_helper_divq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4903 | break; |
14ce26e7 | 4904 | #endif |
2c0262af FB |
4905 | } |
4906 | break; | |
4907 | case 7: /* idiv */ | |
4908 | switch(ot) { | |
4ba9938c | 4909 | case MO_8: |
14ce26e7 | 4910 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4911 | gen_helper_idivb_AL(cpu_env, cpu_T[0]); |
2c0262af | 4912 | break; |
4ba9938c | 4913 | case MO_16: |
14ce26e7 | 4914 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4915 | gen_helper_idivw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4916 | break; |
4917 | default: | |
4ba9938c | 4918 | case MO_32: |
14ce26e7 | 4919 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4920 | gen_helper_idivl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4921 | break; |
4922 | #ifdef TARGET_X86_64 | |
4ba9938c | 4923 | case MO_64: |
14ce26e7 | 4924 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4925 | gen_helper_idivq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4926 | break; |
14ce26e7 | 4927 | #endif |
2c0262af FB |
4928 | } |
4929 | break; | |
4930 | default: | |
4931 | goto illegal_op; | |
4932 | } | |
4933 | break; | |
4934 | ||
4935 | case 0xfe: /* GRP4 */ | |
4936 | case 0xff: /* GRP5 */ | |
ab4e4aec | 4937 | ot = mo_b_d(b, dflag); |
2c0262af | 4938 | |
0af10c86 | 4939 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4940 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4941 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4942 | op = (modrm >> 3) & 7; |
4943 | if (op >= 2 && b == 0xfe) { | |
4944 | goto illegal_op; | |
4945 | } | |
14ce26e7 | 4946 | if (CODE64(s)) { |
aba9d61e | 4947 | if (op == 2 || op == 4) { |
14ce26e7 | 4948 | /* operand size for jumps is 64 bit */ |
4ba9938c | 4949 | ot = MO_64; |
aba9d61e | 4950 | } else if (op == 3 || op == 5) { |
ab4e4aec | 4951 | ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16; |
14ce26e7 FB |
4952 | } else if (op == 6) { |
4953 | /* default push size is 64 bit */ | |
ab4e4aec | 4954 | ot = mo_pushpop(s, dflag); |
14ce26e7 FB |
4955 | } |
4956 | } | |
2c0262af | 4957 | if (mod != 3) { |
4eeb3939 | 4958 | gen_lea_modrm(env, s, modrm); |
2c0262af | 4959 | if (op >= 2 && op != 3 && op != 5) |
909be183 | 4960 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 4961 | } else { |
57fec1fe | 4962 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4963 | } |
4964 | ||
4965 | switch(op) { | |
4966 | case 0: /* inc Ev */ | |
4967 | if (mod != 3) | |
4968 | opreg = OR_TMP0; | |
4969 | else | |
4970 | opreg = rm; | |
4971 | gen_inc(s, ot, opreg, 1); | |
4972 | break; | |
4973 | case 1: /* dec Ev */ | |
4974 | if (mod != 3) | |
4975 | opreg = OR_TMP0; | |
4976 | else | |
4977 | opreg = rm; | |
4978 | gen_inc(s, ot, opreg, -1); | |
4979 | break; | |
4980 | case 2: /* call Ev */ | |
4f31916f | 4981 | /* XXX: optimize if memory (no 'and' is necessary) */ |
ab4e4aec | 4982 | if (dflag == MO_16) { |
40b90233 RH |
4983 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
4984 | } | |
2c0262af | 4985 | next_eip = s->pc - s->cs_base; |
cc0bce88 | 4986 | tcg_gen_movi_tl(cpu_T[1], next_eip); |
4f31916f FB |
4987 | gen_push_T1(s); |
4988 | gen_op_jmp_T0(); | |
2c0262af FB |
4989 | gen_eob(s); |
4990 | break; | |
61382a50 | 4991 | case 3: /* lcall Ev */ |
0f712e10 | 4992 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
4ba9938c | 4993 | gen_add_A0_im(s, 1 << (ot - MO_16 + 1)); |
cc1a80df | 4994 | gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); |
2c0262af FB |
4995 | do_lcall: |
4996 | if (s->pe && !s->vm86) { | |
773cdfcc | 4997 | gen_update_cc_op(s); |
14ce26e7 | 4998 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4999 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 5000 | gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
ab4e4aec | 5001 | tcg_const_i32(dflag - 1), |
a7812ae4 | 5002 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 5003 | } else { |
b6abf97d | 5004 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 5005 | gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1], |
ab4e4aec | 5006 | tcg_const_i32(dflag - 1), |
a7812ae4 | 5007 | tcg_const_i32(s->pc - s->cs_base)); |
2c0262af FB |
5008 | } |
5009 | gen_eob(s); | |
5010 | break; | |
5011 | case 4: /* jmp Ev */ | |
ab4e4aec | 5012 | if (dflag == MO_16) { |
40b90233 RH |
5013 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
5014 | } | |
2c0262af FB |
5015 | gen_op_jmp_T0(); |
5016 | gen_eob(s); | |
5017 | break; | |
5018 | case 5: /* ljmp Ev */ | |
0f712e10 | 5019 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
4ba9938c | 5020 | gen_add_A0_im(s, 1 << (ot - MO_16 + 1)); |
cc1a80df | 5021 | gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); |
2c0262af FB |
5022 | do_ljmp: |
5023 | if (s->pe && !s->vm86) { | |
773cdfcc | 5024 | gen_update_cc_op(s); |
14ce26e7 | 5025 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 5026 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 5027 | gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
a7812ae4 | 5028 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 5029 | } else { |
3bd7da9e | 5030 | gen_op_movl_seg_T0_vm(R_CS); |
2b98a7d7 | 5031 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); |
2c0262af FB |
5032 | gen_op_jmp_T0(); |
5033 | } | |
5034 | gen_eob(s); | |
5035 | break; | |
5036 | case 6: /* push Ev */ | |
5037 | gen_push_T0(s); | |
5038 | break; | |
5039 | default: | |
5040 | goto illegal_op; | |
5041 | } | |
5042 | break; | |
5043 | ||
5044 | case 0x84: /* test Ev, Gv */ | |
5fafdf24 | 5045 | case 0x85: |
ab4e4aec | 5046 | ot = mo_b_d(b, dflag); |
2c0262af | 5047 | |
0af10c86 | 5048 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5049 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5050 | |
0af10c86 | 5051 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5052 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af | 5053 | gen_op_testl_T0_T1_cc(); |
3ca51d07 | 5054 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 5055 | break; |
3b46e624 | 5056 | |
2c0262af FB |
5057 | case 0xa8: /* test eAX, Iv */ |
5058 | case 0xa9: | |
ab4e4aec | 5059 | ot = mo_b_d(b, dflag); |
0af10c86 | 5060 | val = insn_get(env, s, ot); |
2c0262af | 5061 | |
57fec1fe | 5062 | gen_op_mov_TN_reg(ot, 0, OR_EAX); |
0ae657b1 | 5063 | tcg_gen_movi_tl(cpu_T[1], val); |
2c0262af | 5064 | gen_op_testl_T0_T1_cc(); |
3ca51d07 | 5065 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 5066 | break; |
3b46e624 | 5067 | |
2c0262af | 5068 | case 0x98: /* CWDE/CBW */ |
ab4e4aec | 5069 | switch (dflag) { |
14ce26e7 | 5070 | #ifdef TARGET_X86_64 |
ab4e4aec | 5071 | case MO_64: |
4ba9938c | 5072 | gen_op_mov_TN_reg(MO_32, 0, R_EAX); |
e108dd01 | 5073 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 5074 | gen_op_mov_reg_T0(MO_64, R_EAX); |
ab4e4aec | 5075 | break; |
14ce26e7 | 5076 | #endif |
ab4e4aec | 5077 | case MO_32: |
4ba9938c | 5078 | gen_op_mov_TN_reg(MO_16, 0, R_EAX); |
e108dd01 | 5079 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 5080 | gen_op_mov_reg_T0(MO_32, R_EAX); |
ab4e4aec RH |
5081 | break; |
5082 | case MO_16: | |
4ba9938c | 5083 | gen_op_mov_TN_reg(MO_8, 0, R_EAX); |
e108dd01 | 5084 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 5085 | gen_op_mov_reg_T0(MO_16, R_EAX); |
ab4e4aec RH |
5086 | break; |
5087 | default: | |
5088 | tcg_abort(); | |
e108dd01 | 5089 | } |
2c0262af FB |
5090 | break; |
5091 | case 0x99: /* CDQ/CWD */ | |
ab4e4aec | 5092 | switch (dflag) { |
14ce26e7 | 5093 | #ifdef TARGET_X86_64 |
ab4e4aec | 5094 | case MO_64: |
4ba9938c | 5095 | gen_op_mov_TN_reg(MO_64, 0, R_EAX); |
e108dd01 | 5096 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); |
4ba9938c | 5097 | gen_op_mov_reg_T0(MO_64, R_EDX); |
ab4e4aec | 5098 | break; |
14ce26e7 | 5099 | #endif |
ab4e4aec | 5100 | case MO_32: |
4ba9938c | 5101 | gen_op_mov_TN_reg(MO_32, 0, R_EAX); |
e108dd01 FB |
5102 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
5103 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); | |
4ba9938c | 5104 | gen_op_mov_reg_T0(MO_32, R_EDX); |
ab4e4aec RH |
5105 | break; |
5106 | case MO_16: | |
4ba9938c | 5107 | gen_op_mov_TN_reg(MO_16, 0, R_EAX); |
e108dd01 FB |
5108 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
5109 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); | |
4ba9938c | 5110 | gen_op_mov_reg_T0(MO_16, R_EDX); |
ab4e4aec RH |
5111 | break; |
5112 | default: | |
5113 | tcg_abort(); | |
e108dd01 | 5114 | } |
2c0262af FB |
5115 | break; |
5116 | case 0x1af: /* imul Gv, Ev */ | |
5117 | case 0x69: /* imul Gv, Ev, I */ | |
5118 | case 0x6b: | |
ab4e4aec | 5119 | ot = dflag; |
0af10c86 | 5120 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
5121 | reg = ((modrm >> 3) & 7) | rex_r; |
5122 | if (b == 0x69) | |
5123 | s->rip_offset = insn_const_size(ot); | |
5124 | else if (b == 0x6b) | |
5125 | s->rip_offset = 1; | |
0af10c86 | 5126 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
2c0262af | 5127 | if (b == 0x69) { |
0af10c86 | 5128 | val = insn_get(env, s, ot); |
0ae657b1 | 5129 | tcg_gen_movi_tl(cpu_T[1], val); |
2c0262af | 5130 | } else if (b == 0x6b) { |
4ba9938c | 5131 | val = (int8_t)insn_get(env, s, MO_8); |
0ae657b1 | 5132 | tcg_gen_movi_tl(cpu_T[1], val); |
2c0262af | 5133 | } else { |
57fec1fe | 5134 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af | 5135 | } |
a4bcea3d | 5136 | switch (ot) { |
0211e5af | 5137 | #ifdef TARGET_X86_64 |
4ba9938c | 5138 | case MO_64: |
a4bcea3d RH |
5139 | tcg_gen_muls2_i64(cpu_regs[reg], cpu_T[1], cpu_T[0], cpu_T[1]); |
5140 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]); | |
5141 | tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63); | |
5142 | tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_T[1]); | |
5143 | break; | |
0211e5af | 5144 | #endif |
4ba9938c | 5145 | case MO_32: |
a4bcea3d RH |
5146 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
5147 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); | |
5148 | tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32, | |
5149 | cpu_tmp2_i32, cpu_tmp3_i32); | |
5150 | tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32); | |
5151 | tcg_gen_sari_i32(cpu_tmp2_i32, cpu_tmp2_i32, 31); | |
5152 | tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]); | |
5153 | tcg_gen_sub_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); | |
5154 | tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32); | |
5155 | break; | |
5156 | default: | |
0211e5af FB |
5157 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
5158 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
5159 | /* XXX: use 32 bit mul which could be faster */ | |
5160 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
5161 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
5162 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
5163 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
a4bcea3d RH |
5164 | gen_op_mov_reg_T0(ot, reg); |
5165 | break; | |
2c0262af | 5166 | } |
3ca51d07 | 5167 | set_cc_op(s, CC_OP_MULB + ot); |
2c0262af FB |
5168 | break; |
5169 | case 0x1c0: | |
5170 | case 0x1c1: /* xadd Ev, Gv */ | |
ab4e4aec | 5171 | ot = mo_b_d(b, dflag); |
0af10c86 | 5172 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5173 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5174 | mod = (modrm >> 6) & 3; |
5175 | if (mod == 3) { | |
14ce26e7 | 5176 | rm = (modrm & 7) | REX_B(s); |
57fec1fe FB |
5177 | gen_op_mov_TN_reg(ot, 0, reg); |
5178 | gen_op_mov_TN_reg(ot, 1, rm); | |
2c0262af | 5179 | gen_op_addl_T0_T1(); |
57fec1fe FB |
5180 | gen_op_mov_reg_T1(ot, reg); |
5181 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 5182 | } else { |
4eeb3939 | 5183 | gen_lea_modrm(env, s, modrm); |
57fec1fe | 5184 | gen_op_mov_TN_reg(ot, 0, reg); |
0f712e10 | 5185 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
2c0262af | 5186 | gen_op_addl_T0_T1(); |
fd8ca9f6 | 5187 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
57fec1fe | 5188 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5189 | } |
5190 | gen_op_update2_cc(); | |
3ca51d07 | 5191 | set_cc_op(s, CC_OP_ADDB + ot); |
2c0262af FB |
5192 | break; |
5193 | case 0x1b0: | |
5194 | case 0x1b1: /* cmpxchg Ev, Gv */ | |
cad3a37d | 5195 | { |
1130328e | 5196 | int label1, label2; |
1e4840bf | 5197 | TCGv t0, t1, t2, a0; |
cad3a37d | 5198 | |
ab4e4aec | 5199 | ot = mo_b_d(b, dflag); |
0af10c86 | 5200 | modrm = cpu_ldub_code(env, s->pc++); |
cad3a37d FB |
5201 | reg = ((modrm >> 3) & 7) | rex_r; |
5202 | mod = (modrm >> 6) & 3; | |
a7812ae4 PB |
5203 | t0 = tcg_temp_local_new(); |
5204 | t1 = tcg_temp_local_new(); | |
5205 | t2 = tcg_temp_local_new(); | |
5206 | a0 = tcg_temp_local_new(); | |
1e4840bf | 5207 | gen_op_mov_v_reg(ot, t1, reg); |
cad3a37d FB |
5208 | if (mod == 3) { |
5209 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 5210 | gen_op_mov_v_reg(ot, t0, rm); |
cad3a37d | 5211 | } else { |
4eeb3939 | 5212 | gen_lea_modrm(env, s, modrm); |
1e4840bf | 5213 | tcg_gen_mov_tl(a0, cpu_A0); |
323d1876 | 5214 | gen_op_ld_v(s, ot, t0, a0); |
cad3a37d FB |
5215 | rm = 0; /* avoid warning */ |
5216 | } | |
5217 | label1 = gen_new_label(); | |
a3251186 RH |
5218 | tcg_gen_mov_tl(t2, cpu_regs[R_EAX]); |
5219 | gen_extu(ot, t0); | |
1e4840bf | 5220 | gen_extu(ot, t2); |
a3251186 | 5221 | tcg_gen_brcond_tl(TCG_COND_EQ, t2, t0, label1); |
f7e80adf | 5222 | label2 = gen_new_label(); |
cad3a37d | 5223 | if (mod == 3) { |
1e4840bf | 5224 | gen_op_mov_reg_v(ot, R_EAX, t0); |
1130328e FB |
5225 | tcg_gen_br(label2); |
5226 | gen_set_label(label1); | |
1e4840bf | 5227 | gen_op_mov_reg_v(ot, rm, t1); |
cad3a37d | 5228 | } else { |
f7e80adf AG |
5229 | /* perform no-op store cycle like physical cpu; must be |
5230 | before changing accumulator to ensure idempotency if | |
5231 | the store faults and the instruction is restarted */ | |
323d1876 | 5232 | gen_op_st_v(s, ot, t0, a0); |
1e4840bf | 5233 | gen_op_mov_reg_v(ot, R_EAX, t0); |
f7e80adf | 5234 | tcg_gen_br(label2); |
1130328e | 5235 | gen_set_label(label1); |
323d1876 | 5236 | gen_op_st_v(s, ot, t1, a0); |
cad3a37d | 5237 | } |
f7e80adf | 5238 | gen_set_label(label2); |
1e4840bf | 5239 | tcg_gen_mov_tl(cpu_cc_src, t0); |
a3251186 RH |
5240 | tcg_gen_mov_tl(cpu_cc_srcT, t2); |
5241 | tcg_gen_sub_tl(cpu_cc_dst, t2, t0); | |
3ca51d07 | 5242 | set_cc_op(s, CC_OP_SUBB + ot); |
1e4840bf FB |
5243 | tcg_temp_free(t0); |
5244 | tcg_temp_free(t1); | |
5245 | tcg_temp_free(t2); | |
5246 | tcg_temp_free(a0); | |
2c0262af | 5247 | } |
2c0262af FB |
5248 | break; |
5249 | case 0x1c7: /* cmpxchg8b */ | |
0af10c86 | 5250 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5251 | mod = (modrm >> 6) & 3; |
71c3558e | 5252 | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
2c0262af | 5253 | goto illegal_op; |
1b9d9ebb | 5254 | #ifdef TARGET_X86_64 |
ab4e4aec | 5255 | if (dflag == MO_64) { |
1b9d9ebb FB |
5256 | if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) |
5257 | goto illegal_op; | |
5258 | gen_jmp_im(pc_start - s->cs_base); | |
773cdfcc | 5259 | gen_update_cc_op(s); |
4eeb3939 | 5260 | gen_lea_modrm(env, s, modrm); |
92fc4b58 | 5261 | gen_helper_cmpxchg16b(cpu_env, cpu_A0); |
1b9d9ebb FB |
5262 | } else |
5263 | #endif | |
5264 | { | |
5265 | if (!(s->cpuid_features & CPUID_CX8)) | |
5266 | goto illegal_op; | |
5267 | gen_jmp_im(pc_start - s->cs_base); | |
773cdfcc | 5268 | gen_update_cc_op(s); |
4eeb3939 | 5269 | gen_lea_modrm(env, s, modrm); |
92fc4b58 | 5270 | gen_helper_cmpxchg8b(cpu_env, cpu_A0); |
1b9d9ebb | 5271 | } |
3ca51d07 | 5272 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 5273 | break; |
3b46e624 | 5274 | |
2c0262af FB |
5275 | /**************************/ |
5276 | /* push/pop */ | |
5277 | case 0x50 ... 0x57: /* push */ | |
4ba9938c | 5278 | gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s)); |
2c0262af FB |
5279 | gen_push_T0(s); |
5280 | break; | |
5281 | case 0x58 ... 0x5f: /* pop */ | |
ab4e4aec | 5282 | ot = mo_pushpop(s, dflag); |
2c0262af | 5283 | gen_pop_T0(s); |
77729c24 | 5284 | /* NOTE: order is important for pop %sp */ |
2c0262af | 5285 | gen_pop_update(s); |
57fec1fe | 5286 | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s)); |
2c0262af FB |
5287 | break; |
5288 | case 0x60: /* pusha */ | |
14ce26e7 FB |
5289 | if (CODE64(s)) |
5290 | goto illegal_op; | |
2c0262af FB |
5291 | gen_pusha(s); |
5292 | break; | |
5293 | case 0x61: /* popa */ | |
14ce26e7 FB |
5294 | if (CODE64(s)) |
5295 | goto illegal_op; | |
2c0262af FB |
5296 | gen_popa(s); |
5297 | break; | |
5298 | case 0x68: /* push Iv */ | |
5299 | case 0x6a: | |
ab4e4aec | 5300 | ot = mo_pushpop(s, dflag); |
2c0262af | 5301 | if (b == 0x68) |
0af10c86 | 5302 | val = insn_get(env, s, ot); |
2c0262af | 5303 | else |
4ba9938c | 5304 | val = (int8_t)insn_get(env, s, MO_8); |
1b90d56e | 5305 | tcg_gen_movi_tl(cpu_T[0], val); |
2c0262af FB |
5306 | gen_push_T0(s); |
5307 | break; | |
5308 | case 0x8f: /* pop Ev */ | |
ab4e4aec | 5309 | ot = mo_pushpop(s, dflag); |
0af10c86 | 5310 | modrm = cpu_ldub_code(env, s->pc++); |
77729c24 | 5311 | mod = (modrm >> 6) & 3; |
2c0262af | 5312 | gen_pop_T0(s); |
77729c24 FB |
5313 | if (mod == 3) { |
5314 | /* NOTE: order is important for pop %sp */ | |
5315 | gen_pop_update(s); | |
14ce26e7 | 5316 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 5317 | gen_op_mov_reg_T0(ot, rm); |
77729c24 FB |
5318 | } else { |
5319 | /* NOTE: order is important too for MMU exceptions */ | |
14ce26e7 | 5320 | s->popl_esp_hack = 1 << ot; |
0af10c86 | 5321 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
77729c24 FB |
5322 | s->popl_esp_hack = 0; |
5323 | gen_pop_update(s); | |
5324 | } | |
2c0262af FB |
5325 | break; |
5326 | case 0xc8: /* enter */ | |
5327 | { | |
5328 | int level; | |
0af10c86 | 5329 | val = cpu_lduw_code(env, s->pc); |
2c0262af | 5330 | s->pc += 2; |
0af10c86 | 5331 | level = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5332 | gen_enter(s, val, level); |
5333 | } | |
5334 | break; | |
5335 | case 0xc9: /* leave */ | |
5336 | /* XXX: exception not precise (ESP is updated before potential exception) */ | |
14ce26e7 | 5337 | if (CODE64(s)) { |
4ba9938c RH |
5338 | gen_op_mov_TN_reg(MO_64, 0, R_EBP); |
5339 | gen_op_mov_reg_T0(MO_64, R_ESP); | |
14ce26e7 | 5340 | } else if (s->ss32) { |
4ba9938c RH |
5341 | gen_op_mov_TN_reg(MO_32, 0, R_EBP); |
5342 | gen_op_mov_reg_T0(MO_32, R_ESP); | |
2c0262af | 5343 | } else { |
4ba9938c RH |
5344 | gen_op_mov_TN_reg(MO_16, 0, R_EBP); |
5345 | gen_op_mov_reg_T0(MO_16, R_ESP); | |
2c0262af FB |
5346 | } |
5347 | gen_pop_T0(s); | |
ab4e4aec | 5348 | ot = mo_pushpop(s, dflag); |
57fec1fe | 5349 | gen_op_mov_reg_T0(ot, R_EBP); |
2c0262af FB |
5350 | gen_pop_update(s); |
5351 | break; | |
5352 | case 0x06: /* push es */ | |
5353 | case 0x0e: /* push cs */ | |
5354 | case 0x16: /* push ss */ | |
5355 | case 0x1e: /* push ds */ | |
14ce26e7 FB |
5356 | if (CODE64(s)) |
5357 | goto illegal_op; | |
2c0262af FB |
5358 | gen_op_movl_T0_seg(b >> 3); |
5359 | gen_push_T0(s); | |
5360 | break; | |
5361 | case 0x1a0: /* push fs */ | |
5362 | case 0x1a8: /* push gs */ | |
5363 | gen_op_movl_T0_seg((b >> 3) & 7); | |
5364 | gen_push_T0(s); | |
5365 | break; | |
5366 | case 0x07: /* pop es */ | |
5367 | case 0x17: /* pop ss */ | |
5368 | case 0x1f: /* pop ds */ | |
14ce26e7 FB |
5369 | if (CODE64(s)) |
5370 | goto illegal_op; | |
2c0262af FB |
5371 | reg = b >> 3; |
5372 | gen_pop_T0(s); | |
5373 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5374 | gen_pop_update(s); | |
5375 | if (reg == R_SS) { | |
a2cc3b24 FB |
5376 | /* if reg == SS, inhibit interrupts/trace. */ |
5377 | /* If several instructions disable interrupts, only the | |
5378 | _first_ does it */ | |
5379 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5380 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5381 | s->tf = 0; |
5382 | } | |
5383 | if (s->is_jmp) { | |
14ce26e7 | 5384 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5385 | gen_eob(s); |
5386 | } | |
5387 | break; | |
5388 | case 0x1a1: /* pop fs */ | |
5389 | case 0x1a9: /* pop gs */ | |
5390 | gen_pop_T0(s); | |
5391 | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); | |
5392 | gen_pop_update(s); | |
5393 | if (s->is_jmp) { | |
14ce26e7 | 5394 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5395 | gen_eob(s); |
5396 | } | |
5397 | break; | |
5398 | ||
5399 | /**************************/ | |
5400 | /* mov */ | |
5401 | case 0x88: | |
5402 | case 0x89: /* mov Gv, Ev */ | |
ab4e4aec | 5403 | ot = mo_b_d(b, dflag); |
0af10c86 | 5404 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5405 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5406 | |
2c0262af | 5407 | /* generate a generic store */ |
0af10c86 | 5408 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
2c0262af FB |
5409 | break; |
5410 | case 0xc6: | |
5411 | case 0xc7: /* mov Ev, Iv */ | |
ab4e4aec | 5412 | ot = mo_b_d(b, dflag); |
0af10c86 | 5413 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5414 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5415 | if (mod != 3) { |
5416 | s->rip_offset = insn_const_size(ot); | |
4eeb3939 | 5417 | gen_lea_modrm(env, s, modrm); |
14ce26e7 | 5418 | } |
0af10c86 | 5419 | val = insn_get(env, s, ot); |
1b90d56e | 5420 | tcg_gen_movi_tl(cpu_T[0], val); |
fd8ca9f6 RH |
5421 | if (mod != 3) { |
5422 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); | |
5423 | } else { | |
57fec1fe | 5424 | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); |
fd8ca9f6 | 5425 | } |
2c0262af FB |
5426 | break; |
5427 | case 0x8a: | |
5428 | case 0x8b: /* mov Ev, Gv */ | |
ab4e4aec | 5429 | ot = mo_b_d(b, dflag); |
0af10c86 | 5430 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5431 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5432 | |
0af10c86 | 5433 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5434 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
5435 | break; |
5436 | case 0x8e: /* mov seg, Gv */ | |
0af10c86 | 5437 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5438 | reg = (modrm >> 3) & 7; |
5439 | if (reg >= 6 || reg == R_CS) | |
5440 | goto illegal_op; | |
4ba9938c | 5441 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
2c0262af FB |
5442 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
5443 | if (reg == R_SS) { | |
5444 | /* if reg == SS, inhibit interrupts/trace */ | |
a2cc3b24 FB |
5445 | /* If several instructions disable interrupts, only the |
5446 | _first_ does it */ | |
5447 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5448 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5449 | s->tf = 0; |
5450 | } | |
5451 | if (s->is_jmp) { | |
14ce26e7 | 5452 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5453 | gen_eob(s); |
5454 | } | |
5455 | break; | |
5456 | case 0x8c: /* mov Gv, seg */ | |
0af10c86 | 5457 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5458 | reg = (modrm >> 3) & 7; |
5459 | mod = (modrm >> 6) & 3; | |
5460 | if (reg >= 6) | |
5461 | goto illegal_op; | |
5462 | gen_op_movl_T0_seg(reg); | |
ab4e4aec | 5463 | ot = mod == 3 ? dflag : MO_16; |
0af10c86 | 5464 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
5465 | break; |
5466 | ||
5467 | case 0x1b6: /* movzbS Gv, Eb */ | |
5468 | case 0x1b7: /* movzwS Gv, Eb */ | |
5469 | case 0x1be: /* movsbS Gv, Eb */ | |
5470 | case 0x1bf: /* movswS Gv, Eb */ | |
5471 | { | |
c8fbc479 RH |
5472 | TCGMemOp d_ot; |
5473 | TCGMemOp s_ot; | |
5474 | ||
2c0262af | 5475 | /* d_ot is the size of destination */ |
ab4e4aec | 5476 | d_ot = dflag; |
2c0262af | 5477 | /* ot is the size of source */ |
4ba9938c | 5478 | ot = (b & 1) + MO_8; |
c8fbc479 RH |
5479 | /* s_ot is the sign+size of source */ |
5480 | s_ot = b & 8 ? MO_SIGN | ot : ot; | |
5481 | ||
0af10c86 | 5482 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5483 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 5484 | mod = (modrm >> 6) & 3; |
14ce26e7 | 5485 | rm = (modrm & 7) | REX_B(s); |
3b46e624 | 5486 | |
2c0262af | 5487 | if (mod == 3) { |
57fec1fe | 5488 | gen_op_mov_TN_reg(ot, 0, rm); |
c8fbc479 RH |
5489 | switch (s_ot) { |
5490 | case MO_UB: | |
e108dd01 | 5491 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 5492 | break; |
c8fbc479 | 5493 | case MO_SB: |
e108dd01 | 5494 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 5495 | break; |
c8fbc479 | 5496 | case MO_UW: |
e108dd01 | 5497 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5498 | break; |
5499 | default: | |
c8fbc479 | 5500 | case MO_SW: |
e108dd01 | 5501 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5502 | break; |
5503 | } | |
57fec1fe | 5504 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af | 5505 | } else { |
4eeb3939 | 5506 | gen_lea_modrm(env, s, modrm); |
c8fbc479 | 5507 | gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0); |
57fec1fe | 5508 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5509 | } |
5510 | } | |
5511 | break; | |
5512 | ||
5513 | case 0x8d: /* lea */ | |
ab4e4aec | 5514 | ot = dflag; |
0af10c86 | 5515 | modrm = cpu_ldub_code(env, s->pc++); |
3a1d9b8b FB |
5516 | mod = (modrm >> 6) & 3; |
5517 | if (mod == 3) | |
5518 | goto illegal_op; | |
14ce26e7 | 5519 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5520 | /* we must ensure that no segment is added */ |
5521 | s->override = -1; | |
5522 | val = s->addseg; | |
5523 | s->addseg = 0; | |
4eeb3939 | 5524 | gen_lea_modrm(env, s, modrm); |
2c0262af | 5525 | s->addseg = val; |
6f17675a | 5526 | gen_op_mov_reg_A0(ot, reg); |
2c0262af | 5527 | break; |
3b46e624 | 5528 | |
2c0262af FB |
5529 | case 0xa0: /* mov EAX, Ov */ |
5530 | case 0xa1: | |
5531 | case 0xa2: /* mov Ov, EAX */ | |
5532 | case 0xa3: | |
2c0262af | 5533 | { |
14ce26e7 FB |
5534 | target_ulong offset_addr; |
5535 | ||
ab4e4aec | 5536 | ot = mo_b_d(b, dflag); |
1d71ddb1 | 5537 | switch (s->aflag) { |
14ce26e7 | 5538 | #ifdef TARGET_X86_64 |
1d71ddb1 | 5539 | case MO_64: |
0af10c86 | 5540 | offset_addr = cpu_ldq_code(env, s->pc); |
14ce26e7 | 5541 | s->pc += 8; |
1d71ddb1 | 5542 | break; |
14ce26e7 | 5543 | #endif |
1d71ddb1 RH |
5544 | default: |
5545 | offset_addr = insn_get(env, s, s->aflag); | |
5546 | break; | |
14ce26e7 | 5547 | } |
3250cff8 | 5548 | tcg_gen_movi_tl(cpu_A0, offset_addr); |
664e0f19 | 5549 | gen_add_A0_ds_seg(s); |
14ce26e7 | 5550 | if ((b & 2) == 0) { |
909be183 | 5551 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
57fec1fe | 5552 | gen_op_mov_reg_T0(ot, R_EAX); |
14ce26e7 | 5553 | } else { |
57fec1fe | 5554 | gen_op_mov_TN_reg(ot, 0, R_EAX); |
fd8ca9f6 | 5555 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af FB |
5556 | } |
5557 | } | |
2c0262af FB |
5558 | break; |
5559 | case 0xd7: /* xlat */ | |
1d71ddb1 RH |
5560 | tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EBX]); |
5561 | tcg_gen_ext8u_tl(cpu_T[0], cpu_regs[R_EAX]); | |
5562 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
5563 | gen_extu(s->aflag, cpu_A0); | |
664e0f19 | 5564 | gen_add_A0_ds_seg(s); |
cc1a80df | 5565 | gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0); |
4ba9938c | 5566 | gen_op_mov_reg_T0(MO_8, R_EAX); |
2c0262af FB |
5567 | break; |
5568 | case 0xb0 ... 0xb7: /* mov R, Ib */ | |
4ba9938c | 5569 | val = insn_get(env, s, MO_8); |
1b90d56e | 5570 | tcg_gen_movi_tl(cpu_T[0], val); |
4ba9938c | 5571 | gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s)); |
2c0262af FB |
5572 | break; |
5573 | case 0xb8 ... 0xbf: /* mov R, Iv */ | |
14ce26e7 | 5574 | #ifdef TARGET_X86_64 |
ab4e4aec | 5575 | if (dflag == MO_64) { |
14ce26e7 FB |
5576 | uint64_t tmp; |
5577 | /* 64 bit case */ | |
0af10c86 | 5578 | tmp = cpu_ldq_code(env, s->pc); |
14ce26e7 FB |
5579 | s->pc += 8; |
5580 | reg = (b & 7) | REX_B(s); | |
cc0bce88 | 5581 | tcg_gen_movi_tl(cpu_T[0], tmp); |
4ba9938c | 5582 | gen_op_mov_reg_T0(MO_64, reg); |
5fafdf24 | 5583 | } else |
14ce26e7 FB |
5584 | #endif |
5585 | { | |
ab4e4aec | 5586 | ot = dflag; |
0af10c86 | 5587 | val = insn_get(env, s, ot); |
14ce26e7 | 5588 | reg = (b & 7) | REX_B(s); |
1b90d56e | 5589 | tcg_gen_movi_tl(cpu_T[0], val); |
57fec1fe | 5590 | gen_op_mov_reg_T0(ot, reg); |
14ce26e7 | 5591 | } |
2c0262af FB |
5592 | break; |
5593 | ||
5594 | case 0x91 ... 0x97: /* xchg R, EAX */ | |
7418027e | 5595 | do_xchg_reg_eax: |
ab4e4aec | 5596 | ot = dflag; |
14ce26e7 | 5597 | reg = (b & 7) | REX_B(s); |
2c0262af FB |
5598 | rm = R_EAX; |
5599 | goto do_xchg_reg; | |
5600 | case 0x86: | |
5601 | case 0x87: /* xchg Ev, Gv */ | |
ab4e4aec | 5602 | ot = mo_b_d(b, dflag); |
0af10c86 | 5603 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5604 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5605 | mod = (modrm >> 6) & 3; |
5606 | if (mod == 3) { | |
14ce26e7 | 5607 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 5608 | do_xchg_reg: |
57fec1fe FB |
5609 | gen_op_mov_TN_reg(ot, 0, reg); |
5610 | gen_op_mov_TN_reg(ot, 1, rm); | |
5611 | gen_op_mov_reg_T0(ot, rm); | |
5612 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af | 5613 | } else { |
4eeb3939 | 5614 | gen_lea_modrm(env, s, modrm); |
57fec1fe | 5615 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af FB |
5616 | /* for xchg, lock is implicit */ |
5617 | if (!(prefixes & PREFIX_LOCK)) | |
a7812ae4 | 5618 | gen_helper_lock(); |
0f712e10 | 5619 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
fd8ca9f6 | 5620 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 5621 | if (!(prefixes & PREFIX_LOCK)) |
a7812ae4 | 5622 | gen_helper_unlock(); |
57fec1fe | 5623 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5624 | } |
5625 | break; | |
5626 | case 0xc4: /* les Gv */ | |
701ed211 | 5627 | /* In CODE64 this is VEX3; see above. */ |
2c0262af FB |
5628 | op = R_ES; |
5629 | goto do_lxx; | |
5630 | case 0xc5: /* lds Gv */ | |
701ed211 | 5631 | /* In CODE64 this is VEX2; see above. */ |
2c0262af FB |
5632 | op = R_DS; |
5633 | goto do_lxx; | |
5634 | case 0x1b2: /* lss Gv */ | |
5635 | op = R_SS; | |
5636 | goto do_lxx; | |
5637 | case 0x1b4: /* lfs Gv */ | |
5638 | op = R_FS; | |
5639 | goto do_lxx; | |
5640 | case 0x1b5: /* lgs Gv */ | |
5641 | op = R_GS; | |
5642 | do_lxx: | |
ab4e4aec | 5643 | ot = dflag != MO_16 ? MO_32 : MO_16; |
0af10c86 | 5644 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5645 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5646 | mod = (modrm >> 6) & 3; |
5647 | if (mod == 3) | |
5648 | goto illegal_op; | |
4eeb3939 | 5649 | gen_lea_modrm(env, s, modrm); |
0f712e10 | 5650 | gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); |
4ba9938c | 5651 | gen_add_A0_im(s, 1 << (ot - MO_16 + 1)); |
2c0262af | 5652 | /* load the segment first to handle exceptions properly */ |
cc1a80df | 5653 | gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); |
2c0262af FB |
5654 | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
5655 | /* then put the data */ | |
57fec1fe | 5656 | gen_op_mov_reg_T1(ot, reg); |
2c0262af | 5657 | if (s->is_jmp) { |
14ce26e7 | 5658 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5659 | gen_eob(s); |
5660 | } | |
5661 | break; | |
3b46e624 | 5662 | |
2c0262af FB |
5663 | /************************/ |
5664 | /* shifts */ | |
5665 | case 0xc0: | |
5666 | case 0xc1: | |
5667 | /* shift Ev,Ib */ | |
5668 | shift = 2; | |
5669 | grp2: | |
5670 | { | |
ab4e4aec | 5671 | ot = mo_b_d(b, dflag); |
0af10c86 | 5672 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5673 | mod = (modrm >> 6) & 3; |
2c0262af | 5674 | op = (modrm >> 3) & 7; |
3b46e624 | 5675 | |
2c0262af | 5676 | if (mod != 3) { |
14ce26e7 FB |
5677 | if (shift == 2) { |
5678 | s->rip_offset = 1; | |
5679 | } | |
4eeb3939 | 5680 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
5681 | opreg = OR_TMP0; |
5682 | } else { | |
14ce26e7 | 5683 | opreg = (modrm & 7) | REX_B(s); |
2c0262af FB |
5684 | } |
5685 | ||
5686 | /* simpler op */ | |
5687 | if (shift == 0) { | |
5688 | gen_shift(s, op, ot, opreg, OR_ECX); | |
5689 | } else { | |
5690 | if (shift == 2) { | |
0af10c86 | 5691 | shift = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5692 | } |
5693 | gen_shifti(s, op, ot, opreg, shift); | |
5694 | } | |
5695 | } | |
5696 | break; | |
5697 | case 0xd0: | |
5698 | case 0xd1: | |
5699 | /* shift Ev,1 */ | |
5700 | shift = 1; | |
5701 | goto grp2; | |
5702 | case 0xd2: | |
5703 | case 0xd3: | |
5704 | /* shift Ev,cl */ | |
5705 | shift = 0; | |
5706 | goto grp2; | |
5707 | ||
5708 | case 0x1a4: /* shld imm */ | |
5709 | op = 0; | |
5710 | shift = 1; | |
5711 | goto do_shiftd; | |
5712 | case 0x1a5: /* shld cl */ | |
5713 | op = 0; | |
5714 | shift = 0; | |
5715 | goto do_shiftd; | |
5716 | case 0x1ac: /* shrd imm */ | |
5717 | op = 1; | |
5718 | shift = 1; | |
5719 | goto do_shiftd; | |
5720 | case 0x1ad: /* shrd cl */ | |
5721 | op = 1; | |
5722 | shift = 0; | |
5723 | do_shiftd: | |
ab4e4aec | 5724 | ot = dflag; |
0af10c86 | 5725 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5726 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5727 | rm = (modrm & 7) | REX_B(s); |
5728 | reg = ((modrm >> 3) & 7) | rex_r; | |
2c0262af | 5729 | if (mod != 3) { |
4eeb3939 | 5730 | gen_lea_modrm(env, s, modrm); |
b6abf97d | 5731 | opreg = OR_TMP0; |
2c0262af | 5732 | } else { |
b6abf97d | 5733 | opreg = rm; |
2c0262af | 5734 | } |
57fec1fe | 5735 | gen_op_mov_TN_reg(ot, 1, reg); |
3b46e624 | 5736 | |
2c0262af | 5737 | if (shift) { |
3b9d3cf1 PB |
5738 | TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++)); |
5739 | gen_shiftd_rm_T1(s, ot, opreg, op, imm); | |
5740 | tcg_temp_free(imm); | |
2c0262af | 5741 | } else { |
3b9d3cf1 | 5742 | gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); |
2c0262af FB |
5743 | } |
5744 | break; | |
5745 | ||
5746 | /************************/ | |
5747 | /* floats */ | |
5fafdf24 | 5748 | case 0xd8 ... 0xdf: |
7eee2a50 FB |
5749 | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { |
5750 | /* if CR0.EM or CR0.TS are set, generate an FPU exception */ | |
5751 | /* XXX: what to do if illegal op ? */ | |
5752 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
5753 | break; | |
5754 | } | |
0af10c86 | 5755 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5756 | mod = (modrm >> 6) & 3; |
5757 | rm = modrm & 7; | |
5758 | op = ((b & 7) << 3) | ((modrm >> 3) & 7); | |
2c0262af FB |
5759 | if (mod != 3) { |
5760 | /* memory op */ | |
4eeb3939 | 5761 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
5762 | switch(op) { |
5763 | case 0x00 ... 0x07: /* fxxxs */ | |
5764 | case 0x10 ... 0x17: /* fixxxl */ | |
5765 | case 0x20 ... 0x27: /* fxxxl */ | |
5766 | case 0x30 ... 0x37: /* fixxx */ | |
5767 | { | |
5768 | int op1; | |
5769 | op1 = op & 7; | |
5770 | ||
5771 | switch(op >> 4) { | |
5772 | case 0: | |
80b02013 RH |
5773 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
5774 | s->mem_index, MO_LEUL); | |
d3eb5eae | 5775 | gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5776 | break; |
5777 | case 1: | |
80b02013 RH |
5778 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
5779 | s->mem_index, MO_LEUL); | |
d3eb5eae | 5780 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5781 | break; |
5782 | case 2: | |
3c5f4116 RH |
5783 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, |
5784 | s->mem_index, MO_LEQ); | |
d3eb5eae | 5785 | gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5786 | break; |
5787 | case 3: | |
5788 | default: | |
80b02013 RH |
5789 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
5790 | s->mem_index, MO_LESW); | |
d3eb5eae | 5791 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5792 | break; |
5793 | } | |
3b46e624 | 5794 | |
a7812ae4 | 5795 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5796 | if (op1 == 3) { |
5797 | /* fcomp needs pop */ | |
d3eb5eae | 5798 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5799 | } |
5800 | } | |
5801 | break; | |
5802 | case 0x08: /* flds */ | |
5803 | case 0x0a: /* fsts */ | |
5804 | case 0x0b: /* fstps */ | |
465e9838 FB |
5805 | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
5806 | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ | |
5807 | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ | |
2c0262af FB |
5808 | switch(op & 7) { |
5809 | case 0: | |
5810 | switch(op >> 4) { | |
5811 | case 0: | |
80b02013 RH |
5812 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
5813 | s->mem_index, MO_LEUL); | |
d3eb5eae | 5814 | gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5815 | break; |
5816 | case 1: | |
80b02013 RH |
5817 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
5818 | s->mem_index, MO_LEUL); | |
d3eb5eae | 5819 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5820 | break; |
5821 | case 2: | |
3c5f4116 RH |
5822 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, |
5823 | s->mem_index, MO_LEQ); | |
d3eb5eae | 5824 | gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5825 | break; |
5826 | case 3: | |
5827 | default: | |
80b02013 RH |
5828 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
5829 | s->mem_index, MO_LESW); | |
d3eb5eae | 5830 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5831 | break; |
5832 | } | |
5833 | break; | |
465e9838 | 5834 | case 1: |
19e6c4b8 | 5835 | /* XXX: the corresponding CPUID bit must be tested ! */ |
465e9838 FB |
5836 | switch(op >> 4) { |
5837 | case 1: | |
d3eb5eae | 5838 | gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env); |
d5601ad0 RH |
5839 | tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, |
5840 | s->mem_index, MO_LEUL); | |
465e9838 FB |
5841 | break; |
5842 | case 2: | |
d3eb5eae | 5843 | gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); |
3523e4bd RH |
5844 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, |
5845 | s->mem_index, MO_LEQ); | |
465e9838 FB |
5846 | break; |
5847 | case 3: | |
5848 | default: | |
d3eb5eae | 5849 | gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env); |
d5601ad0 RH |
5850 | tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, |
5851 | s->mem_index, MO_LEUW); | |
19e6c4b8 | 5852 | break; |
465e9838 | 5853 | } |
d3eb5eae | 5854 | gen_helper_fpop(cpu_env); |
465e9838 | 5855 | break; |
2c0262af FB |
5856 | default: |
5857 | switch(op >> 4) { | |
5858 | case 0: | |
d3eb5eae | 5859 | gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env); |
d5601ad0 RH |
5860 | tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, |
5861 | s->mem_index, MO_LEUL); | |
2c0262af FB |
5862 | break; |
5863 | case 1: | |
d3eb5eae | 5864 | gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env); |
d5601ad0 RH |
5865 | tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, |
5866 | s->mem_index, MO_LEUL); | |
2c0262af FB |
5867 | break; |
5868 | case 2: | |
d3eb5eae | 5869 | gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); |
3523e4bd RH |
5870 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, |
5871 | s->mem_index, MO_LEQ); | |
2c0262af FB |
5872 | break; |
5873 | case 3: | |
5874 | default: | |
d3eb5eae | 5875 | gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env); |
d5601ad0 RH |
5876 | tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, |
5877 | s->mem_index, MO_LEUW); | |
2c0262af FB |
5878 | break; |
5879 | } | |
5880 | if ((op & 7) == 3) | |
d3eb5eae | 5881 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5882 | break; |
5883 | } | |
5884 | break; | |
5885 | case 0x0c: /* fldenv mem */ | |
773cdfcc | 5886 | gen_update_cc_op(s); |
19e6c4b8 | 5887 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 5888 | gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1)); |
2c0262af FB |
5889 | break; |
5890 | case 0x0d: /* fldcw mem */ | |
80b02013 RH |
5891 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
5892 | s->mem_index, MO_LEUW); | |
d3eb5eae | 5893 | gen_helper_fldcw(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5894 | break; |
5895 | case 0x0e: /* fnstenv mem */ | |
773cdfcc | 5896 | gen_update_cc_op(s); |
19e6c4b8 | 5897 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 5898 | gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1)); |
2c0262af FB |
5899 | break; |
5900 | case 0x0f: /* fnstcw mem */ | |
d3eb5eae | 5901 | gen_helper_fnstcw(cpu_tmp2_i32, cpu_env); |
d5601ad0 RH |
5902 | tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, |
5903 | s->mem_index, MO_LEUW); | |
2c0262af FB |
5904 | break; |
5905 | case 0x1d: /* fldt mem */ | |
773cdfcc | 5906 | gen_update_cc_op(s); |
19e6c4b8 | 5907 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5908 | gen_helper_fldt_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5909 | break; |
5910 | case 0x1f: /* fstpt mem */ | |
773cdfcc | 5911 | gen_update_cc_op(s); |
19e6c4b8 | 5912 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
5913 | gen_helper_fstt_ST0(cpu_env, cpu_A0); |
5914 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5915 | break; |
5916 | case 0x2c: /* frstor mem */ | |
773cdfcc | 5917 | gen_update_cc_op(s); |
19e6c4b8 | 5918 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 5919 | gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(dflag - 1)); |
2c0262af FB |
5920 | break; |
5921 | case 0x2e: /* fnsave mem */ | |
773cdfcc | 5922 | gen_update_cc_op(s); |
19e6c4b8 | 5923 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 5924 | gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(dflag - 1)); |
2c0262af FB |
5925 | break; |
5926 | case 0x2f: /* fnstsw mem */ | |
d3eb5eae | 5927 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
d5601ad0 RH |
5928 | tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, |
5929 | s->mem_index, MO_LEUW); | |
2c0262af FB |
5930 | break; |
5931 | case 0x3c: /* fbld */ | |
773cdfcc | 5932 | gen_update_cc_op(s); |
19e6c4b8 | 5933 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5934 | gen_helper_fbld_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5935 | break; |
5936 | case 0x3e: /* fbstp */ | |
773cdfcc | 5937 | gen_update_cc_op(s); |
19e6c4b8 | 5938 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
5939 | gen_helper_fbst_ST0(cpu_env, cpu_A0); |
5940 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5941 | break; |
5942 | case 0x3d: /* fildll */ | |
3c5f4116 | 5943 | tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); |
d3eb5eae | 5944 | gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5945 | break; |
5946 | case 0x3f: /* fistpll */ | |
d3eb5eae | 5947 | gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env); |
3523e4bd | 5948 | tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); |
d3eb5eae | 5949 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5950 | break; |
5951 | default: | |
5952 | goto illegal_op; | |
5953 | } | |
5954 | } else { | |
5955 | /* register float ops */ | |
5956 | opreg = rm; | |
5957 | ||
5958 | switch(op) { | |
5959 | case 0x08: /* fld sti */ | |
d3eb5eae BS |
5960 | gen_helper_fpush(cpu_env); |
5961 | gen_helper_fmov_ST0_STN(cpu_env, | |
5962 | tcg_const_i32((opreg + 1) & 7)); | |
2c0262af FB |
5963 | break; |
5964 | case 0x09: /* fxchg sti */ | |
c169c906 FB |
5965 | case 0x29: /* fxchg4 sti, undocumented op */ |
5966 | case 0x39: /* fxchg7 sti, undocumented op */ | |
d3eb5eae | 5967 | gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
5968 | break; |
5969 | case 0x0a: /* grp d9/2 */ | |
5970 | switch(rm) { | |
5971 | case 0: /* fnop */ | |
023fe10d | 5972 | /* check exceptions (FreeBSD FPU probe) */ |
773cdfcc | 5973 | gen_update_cc_op(s); |
14ce26e7 | 5974 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5975 | gen_helper_fwait(cpu_env); |
2c0262af FB |
5976 | break; |
5977 | default: | |
5978 | goto illegal_op; | |
5979 | } | |
5980 | break; | |
5981 | case 0x0c: /* grp d9/4 */ | |
5982 | switch(rm) { | |
5983 | case 0: /* fchs */ | |
d3eb5eae | 5984 | gen_helper_fchs_ST0(cpu_env); |
2c0262af FB |
5985 | break; |
5986 | case 1: /* fabs */ | |
d3eb5eae | 5987 | gen_helper_fabs_ST0(cpu_env); |
2c0262af FB |
5988 | break; |
5989 | case 4: /* ftst */ | |
d3eb5eae BS |
5990 | gen_helper_fldz_FT0(cpu_env); |
5991 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
5992 | break; |
5993 | case 5: /* fxam */ | |
d3eb5eae | 5994 | gen_helper_fxam_ST0(cpu_env); |
2c0262af FB |
5995 | break; |
5996 | default: | |
5997 | goto illegal_op; | |
5998 | } | |
5999 | break; | |
6000 | case 0x0d: /* grp d9/5 */ | |
6001 | { | |
6002 | switch(rm) { | |
6003 | case 0: | |
d3eb5eae BS |
6004 | gen_helper_fpush(cpu_env); |
6005 | gen_helper_fld1_ST0(cpu_env); | |
2c0262af FB |
6006 | break; |
6007 | case 1: | |
d3eb5eae BS |
6008 | gen_helper_fpush(cpu_env); |
6009 | gen_helper_fldl2t_ST0(cpu_env); | |
2c0262af FB |
6010 | break; |
6011 | case 2: | |
d3eb5eae BS |
6012 | gen_helper_fpush(cpu_env); |
6013 | gen_helper_fldl2e_ST0(cpu_env); | |
2c0262af FB |
6014 | break; |
6015 | case 3: | |
d3eb5eae BS |
6016 | gen_helper_fpush(cpu_env); |
6017 | gen_helper_fldpi_ST0(cpu_env); | |
2c0262af FB |
6018 | break; |
6019 | case 4: | |
d3eb5eae BS |
6020 | gen_helper_fpush(cpu_env); |
6021 | gen_helper_fldlg2_ST0(cpu_env); | |
2c0262af FB |
6022 | break; |
6023 | case 5: | |
d3eb5eae BS |
6024 | gen_helper_fpush(cpu_env); |
6025 | gen_helper_fldln2_ST0(cpu_env); | |
2c0262af FB |
6026 | break; |
6027 | case 6: | |
d3eb5eae BS |
6028 | gen_helper_fpush(cpu_env); |
6029 | gen_helper_fldz_ST0(cpu_env); | |
2c0262af FB |
6030 | break; |
6031 | default: | |
6032 | goto illegal_op; | |
6033 | } | |
6034 | } | |
6035 | break; | |
6036 | case 0x0e: /* grp d9/6 */ | |
6037 | switch(rm) { | |
6038 | case 0: /* f2xm1 */ | |
d3eb5eae | 6039 | gen_helper_f2xm1(cpu_env); |
2c0262af FB |
6040 | break; |
6041 | case 1: /* fyl2x */ | |
d3eb5eae | 6042 | gen_helper_fyl2x(cpu_env); |
2c0262af FB |
6043 | break; |
6044 | case 2: /* fptan */ | |
d3eb5eae | 6045 | gen_helper_fptan(cpu_env); |
2c0262af FB |
6046 | break; |
6047 | case 3: /* fpatan */ | |
d3eb5eae | 6048 | gen_helper_fpatan(cpu_env); |
2c0262af FB |
6049 | break; |
6050 | case 4: /* fxtract */ | |
d3eb5eae | 6051 | gen_helper_fxtract(cpu_env); |
2c0262af FB |
6052 | break; |
6053 | case 5: /* fprem1 */ | |
d3eb5eae | 6054 | gen_helper_fprem1(cpu_env); |
2c0262af FB |
6055 | break; |
6056 | case 6: /* fdecstp */ | |
d3eb5eae | 6057 | gen_helper_fdecstp(cpu_env); |
2c0262af FB |
6058 | break; |
6059 | default: | |
6060 | case 7: /* fincstp */ | |
d3eb5eae | 6061 | gen_helper_fincstp(cpu_env); |
2c0262af FB |
6062 | break; |
6063 | } | |
6064 | break; | |
6065 | case 0x0f: /* grp d9/7 */ | |
6066 | switch(rm) { | |
6067 | case 0: /* fprem */ | |
d3eb5eae | 6068 | gen_helper_fprem(cpu_env); |
2c0262af FB |
6069 | break; |
6070 | case 1: /* fyl2xp1 */ | |
d3eb5eae | 6071 | gen_helper_fyl2xp1(cpu_env); |
2c0262af FB |
6072 | break; |
6073 | case 2: /* fsqrt */ | |
d3eb5eae | 6074 | gen_helper_fsqrt(cpu_env); |
2c0262af FB |
6075 | break; |
6076 | case 3: /* fsincos */ | |
d3eb5eae | 6077 | gen_helper_fsincos(cpu_env); |
2c0262af FB |
6078 | break; |
6079 | case 5: /* fscale */ | |
d3eb5eae | 6080 | gen_helper_fscale(cpu_env); |
2c0262af FB |
6081 | break; |
6082 | case 4: /* frndint */ | |
d3eb5eae | 6083 | gen_helper_frndint(cpu_env); |
2c0262af FB |
6084 | break; |
6085 | case 6: /* fsin */ | |
d3eb5eae | 6086 | gen_helper_fsin(cpu_env); |
2c0262af FB |
6087 | break; |
6088 | default: | |
6089 | case 7: /* fcos */ | |
d3eb5eae | 6090 | gen_helper_fcos(cpu_env); |
2c0262af FB |
6091 | break; |
6092 | } | |
6093 | break; | |
6094 | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ | |
6095 | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ | |
6096 | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ | |
6097 | { | |
6098 | int op1; | |
3b46e624 | 6099 | |
2c0262af FB |
6100 | op1 = op & 7; |
6101 | if (op >= 0x20) { | |
a7812ae4 | 6102 | gen_helper_fp_arith_STN_ST0(op1, opreg); |
2c0262af | 6103 | if (op >= 0x30) |
d3eb5eae | 6104 | gen_helper_fpop(cpu_env); |
2c0262af | 6105 | } else { |
d3eb5eae | 6106 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
a7812ae4 | 6107 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
6108 | } |
6109 | } | |
6110 | break; | |
6111 | case 0x02: /* fcom */ | |
c169c906 | 6112 | case 0x22: /* fcom2, undocumented op */ |
d3eb5eae BS |
6113 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6114 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
6115 | break; |
6116 | case 0x03: /* fcomp */ | |
c169c906 FB |
6117 | case 0x23: /* fcomp3, undocumented op */ |
6118 | case 0x32: /* fcomp5, undocumented op */ | |
d3eb5eae BS |
6119 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6120 | gen_helper_fcom_ST0_FT0(cpu_env); | |
6121 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6122 | break; |
6123 | case 0x15: /* da/5 */ | |
6124 | switch(rm) { | |
6125 | case 1: /* fucompp */ | |
d3eb5eae BS |
6126 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
6127 | gen_helper_fucom_ST0_FT0(cpu_env); | |
6128 | gen_helper_fpop(cpu_env); | |
6129 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6130 | break; |
6131 | default: | |
6132 | goto illegal_op; | |
6133 | } | |
6134 | break; | |
6135 | case 0x1c: | |
6136 | switch(rm) { | |
6137 | case 0: /* feni (287 only, just do nop here) */ | |
6138 | break; | |
6139 | case 1: /* fdisi (287 only, just do nop here) */ | |
6140 | break; | |
6141 | case 2: /* fclex */ | |
d3eb5eae | 6142 | gen_helper_fclex(cpu_env); |
2c0262af FB |
6143 | break; |
6144 | case 3: /* fninit */ | |
d3eb5eae | 6145 | gen_helper_fninit(cpu_env); |
2c0262af FB |
6146 | break; |
6147 | case 4: /* fsetpm (287 only, just do nop here) */ | |
6148 | break; | |
6149 | default: | |
6150 | goto illegal_op; | |
6151 | } | |
6152 | break; | |
6153 | case 0x1d: /* fucomi */ | |
bff93281 PM |
6154 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6155 | goto illegal_op; | |
6156 | } | |
773cdfcc | 6157 | gen_update_cc_op(s); |
d3eb5eae BS |
6158 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6159 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
3ca51d07 | 6160 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6161 | break; |
6162 | case 0x1e: /* fcomi */ | |
bff93281 PM |
6163 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6164 | goto illegal_op; | |
6165 | } | |
773cdfcc | 6166 | gen_update_cc_op(s); |
d3eb5eae BS |
6167 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6168 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
3ca51d07 | 6169 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 6170 | break; |
658c8bda | 6171 | case 0x28: /* ffree sti */ |
d3eb5eae | 6172 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
5fafdf24 | 6173 | break; |
2c0262af | 6174 | case 0x2a: /* fst sti */ |
d3eb5eae | 6175 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
6176 | break; |
6177 | case 0x2b: /* fstp sti */ | |
c169c906 FB |
6178 | case 0x0b: /* fstp1 sti, undocumented op */ |
6179 | case 0x3a: /* fstp8 sti, undocumented op */ | |
6180 | case 0x3b: /* fstp9 sti, undocumented op */ | |
d3eb5eae BS |
6181 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
6182 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6183 | break; |
6184 | case 0x2c: /* fucom st(i) */ | |
d3eb5eae BS |
6185 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6186 | gen_helper_fucom_ST0_FT0(cpu_env); | |
2c0262af FB |
6187 | break; |
6188 | case 0x2d: /* fucomp st(i) */ | |
d3eb5eae BS |
6189 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6190 | gen_helper_fucom_ST0_FT0(cpu_env); | |
6191 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6192 | break; |
6193 | case 0x33: /* de/3 */ | |
6194 | switch(rm) { | |
6195 | case 1: /* fcompp */ | |
d3eb5eae BS |
6196 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
6197 | gen_helper_fcom_ST0_FT0(cpu_env); | |
6198 | gen_helper_fpop(cpu_env); | |
6199 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6200 | break; |
6201 | default: | |
6202 | goto illegal_op; | |
6203 | } | |
6204 | break; | |
c169c906 | 6205 | case 0x38: /* ffreep sti, undocumented op */ |
d3eb5eae BS |
6206 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
6207 | gen_helper_fpop(cpu_env); | |
c169c906 | 6208 | break; |
2c0262af FB |
6209 | case 0x3c: /* df/4 */ |
6210 | switch(rm) { | |
6211 | case 0: | |
d3eb5eae | 6212 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 6213 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
4ba9938c | 6214 | gen_op_mov_reg_T0(MO_16, R_EAX); |
2c0262af FB |
6215 | break; |
6216 | default: | |
6217 | goto illegal_op; | |
6218 | } | |
6219 | break; | |
6220 | case 0x3d: /* fucomip */ | |
bff93281 PM |
6221 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6222 | goto illegal_op; | |
6223 | } | |
773cdfcc | 6224 | gen_update_cc_op(s); |
d3eb5eae BS |
6225 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6226 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
6227 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 6228 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6229 | break; |
6230 | case 0x3e: /* fcomip */ | |
bff93281 PM |
6231 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6232 | goto illegal_op; | |
6233 | } | |
773cdfcc | 6234 | gen_update_cc_op(s); |
d3eb5eae BS |
6235 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6236 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
6237 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 6238 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 6239 | break; |
a2cc3b24 FB |
6240 | case 0x10 ... 0x13: /* fcmovxx */ |
6241 | case 0x18 ... 0x1b: | |
6242 | { | |
19e6c4b8 | 6243 | int op1, l1; |
d70040bc | 6244 | static const uint8_t fcmov_cc[8] = { |
a2cc3b24 FB |
6245 | (JCC_B << 1), |
6246 | (JCC_Z << 1), | |
6247 | (JCC_BE << 1), | |
6248 | (JCC_P << 1), | |
6249 | }; | |
bff93281 PM |
6250 | |
6251 | if (!(s->cpuid_features & CPUID_CMOV)) { | |
6252 | goto illegal_op; | |
6253 | } | |
1e4840bf | 6254 | op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); |
19e6c4b8 | 6255 | l1 = gen_new_label(); |
dc259201 | 6256 | gen_jcc1_noeob(s, op1, l1); |
d3eb5eae | 6257 | gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
19e6c4b8 | 6258 | gen_set_label(l1); |
a2cc3b24 FB |
6259 | } |
6260 | break; | |
2c0262af FB |
6261 | default: |
6262 | goto illegal_op; | |
6263 | } | |
6264 | } | |
6265 | break; | |
6266 | /************************/ | |
6267 | /* string ops */ | |
6268 | ||
6269 | case 0xa4: /* movsS */ | |
6270 | case 0xa5: | |
ab4e4aec | 6271 | ot = mo_b_d(b, dflag); |
2c0262af FB |
6272 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6273 | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6274 | } else { | |
6275 | gen_movs(s, ot); | |
6276 | } | |
6277 | break; | |
3b46e624 | 6278 | |
2c0262af FB |
6279 | case 0xaa: /* stosS */ |
6280 | case 0xab: | |
ab4e4aec | 6281 | ot = mo_b_d(b, dflag); |
2c0262af FB |
6282 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6283 | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6284 | } else { | |
6285 | gen_stos(s, ot); | |
6286 | } | |
6287 | break; | |
6288 | case 0xac: /* lodsS */ | |
6289 | case 0xad: | |
ab4e4aec | 6290 | ot = mo_b_d(b, dflag); |
2c0262af FB |
6291 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6292 | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6293 | } else { | |
6294 | gen_lods(s, ot); | |
6295 | } | |
6296 | break; | |
6297 | case 0xae: /* scasS */ | |
6298 | case 0xaf: | |
ab4e4aec | 6299 | ot = mo_b_d(b, dflag); |
2c0262af FB |
6300 | if (prefixes & PREFIX_REPNZ) { |
6301 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6302 | } else if (prefixes & PREFIX_REPZ) { | |
6303 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6304 | } else { | |
6305 | gen_scas(s, ot); | |
2c0262af FB |
6306 | } |
6307 | break; | |
6308 | ||
6309 | case 0xa6: /* cmpsS */ | |
6310 | case 0xa7: | |
ab4e4aec | 6311 | ot = mo_b_d(b, dflag); |
2c0262af FB |
6312 | if (prefixes & PREFIX_REPNZ) { |
6313 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6314 | } else if (prefixes & PREFIX_REPZ) { | |
6315 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6316 | } else { | |
6317 | gen_cmps(s, ot); | |
2c0262af FB |
6318 | } |
6319 | break; | |
6320 | case 0x6c: /* insS */ | |
6321 | case 0x6d: | |
ab4e4aec | 6322 | ot = mo_b_d32(b, dflag); |
40b90233 | 6323 | tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); |
b8b6a50b FB |
6324 | gen_check_io(s, ot, pc_start - s->cs_base, |
6325 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6326 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6327 | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6328 | } else { |
f115e911 | 6329 | gen_ins(s, ot); |
2e70f6ef PB |
6330 | if (use_icount) { |
6331 | gen_jmp(s, s->pc - s->cs_base); | |
6332 | } | |
2c0262af FB |
6333 | } |
6334 | break; | |
6335 | case 0x6e: /* outsS */ | |
6336 | case 0x6f: | |
ab4e4aec | 6337 | ot = mo_b_d32(b, dflag); |
40b90233 | 6338 | tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); |
b8b6a50b FB |
6339 | gen_check_io(s, ot, pc_start - s->cs_base, |
6340 | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6341 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6342 | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6343 | } else { |
f115e911 | 6344 | gen_outs(s, ot); |
2e70f6ef PB |
6345 | if (use_icount) { |
6346 | gen_jmp(s, s->pc - s->cs_base); | |
6347 | } | |
2c0262af FB |
6348 | } |
6349 | break; | |
6350 | ||
6351 | /************************/ | |
6352 | /* port I/O */ | |
0573fbfc | 6353 | |
2c0262af FB |
6354 | case 0xe4: |
6355 | case 0xe5: | |
ab4e4aec | 6356 | ot = mo_b_d32(b, dflag); |
0af10c86 | 6357 | val = cpu_ldub_code(env, s->pc++); |
b8b6a50b FB |
6358 | gen_check_io(s, ot, pc_start - s->cs_base, |
6359 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6360 | if (use_icount) |
6361 | gen_io_start(); | |
1b90d56e | 6362 | tcg_gen_movi_i32(cpu_tmp2_i32, val); |
a7812ae4 | 6363 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6364 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6365 | if (use_icount) { |
6366 | gen_io_end(); | |
6367 | gen_jmp(s, s->pc - s->cs_base); | |
6368 | } | |
2c0262af FB |
6369 | break; |
6370 | case 0xe6: | |
6371 | case 0xe7: | |
ab4e4aec | 6372 | ot = mo_b_d32(b, dflag); |
0af10c86 | 6373 | val = cpu_ldub_code(env, s->pc++); |
b8b6a50b FB |
6374 | gen_check_io(s, ot, pc_start - s->cs_base, |
6375 | svm_is_rep(prefixes)); | |
57fec1fe | 6376 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6377 | |
2e70f6ef PB |
6378 | if (use_icount) |
6379 | gen_io_start(); | |
1b90d56e | 6380 | tcg_gen_movi_i32(cpu_tmp2_i32, val); |
b6abf97d | 6381 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6382 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6383 | if (use_icount) { |
6384 | gen_io_end(); | |
6385 | gen_jmp(s, s->pc - s->cs_base); | |
6386 | } | |
2c0262af FB |
6387 | break; |
6388 | case 0xec: | |
6389 | case 0xed: | |
ab4e4aec | 6390 | ot = mo_b_d32(b, dflag); |
40b90233 | 6391 | tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); |
b8b6a50b FB |
6392 | gen_check_io(s, ot, pc_start - s->cs_base, |
6393 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6394 | if (use_icount) |
6395 | gen_io_start(); | |
b6abf97d | 6396 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6397 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6398 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6399 | if (use_icount) { |
6400 | gen_io_end(); | |
6401 | gen_jmp(s, s->pc - s->cs_base); | |
6402 | } | |
2c0262af FB |
6403 | break; |
6404 | case 0xee: | |
6405 | case 0xef: | |
ab4e4aec | 6406 | ot = mo_b_d32(b, dflag); |
40b90233 | 6407 | tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); |
b8b6a50b FB |
6408 | gen_check_io(s, ot, pc_start - s->cs_base, |
6409 | svm_is_rep(prefixes)); | |
57fec1fe | 6410 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6411 | |
2e70f6ef PB |
6412 | if (use_icount) |
6413 | gen_io_start(); | |
b6abf97d | 6414 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6415 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6416 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6417 | if (use_icount) { |
6418 | gen_io_end(); | |
6419 | gen_jmp(s, s->pc - s->cs_base); | |
6420 | } | |
2c0262af FB |
6421 | break; |
6422 | ||
6423 | /************************/ | |
6424 | /* control */ | |
6425 | case 0xc2: /* ret im */ | |
0af10c86 | 6426 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6427 | s->pc += 2; |
6428 | gen_pop_T0(s); | |
ab4e4aec RH |
6429 | if (CODE64(s) && dflag != MO_16) { |
6430 | dflag = MO_64; | |
6431 | } | |
6432 | gen_stack_update(s, val + (1 << dflag)); | |
6433 | if (dflag == MO_16) { | |
40b90233 RH |
6434 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
6435 | } | |
2c0262af FB |
6436 | gen_op_jmp_T0(); |
6437 | gen_eob(s); | |
6438 | break; | |
6439 | case 0xc3: /* ret */ | |
6440 | gen_pop_T0(s); | |
6441 | gen_pop_update(s); | |
ab4e4aec | 6442 | if (dflag == MO_16) { |
40b90233 RH |
6443 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
6444 | } | |
2c0262af FB |
6445 | gen_op_jmp_T0(); |
6446 | gen_eob(s); | |
6447 | break; | |
6448 | case 0xca: /* lret im */ | |
0af10c86 | 6449 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6450 | s->pc += 2; |
6451 | do_lret: | |
6452 | if (s->pe && !s->vm86) { | |
773cdfcc | 6453 | gen_update_cc_op(s); |
14ce26e7 | 6454 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 6455 | gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1), |
a7812ae4 | 6456 | tcg_const_i32(val)); |
2c0262af FB |
6457 | } else { |
6458 | gen_stack_A0(s); | |
6459 | /* pop offset */ | |
ab4e4aec | 6460 | gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0); |
2c0262af FB |
6461 | /* NOTE: keeping EIP updated is not a problem in case of |
6462 | exception */ | |
6463 | gen_op_jmp_T0(); | |
6464 | /* pop selector */ | |
ab4e4aec RH |
6465 | gen_op_addl_A0_im(1 << dflag); |
6466 | gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0); | |
3bd7da9e | 6467 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af | 6468 | /* add stack offset */ |
ab4e4aec | 6469 | gen_stack_update(s, val + (2 << dflag)); |
2c0262af FB |
6470 | } |
6471 | gen_eob(s); | |
6472 | break; | |
6473 | case 0xcb: /* lret */ | |
6474 | val = 0; | |
6475 | goto do_lret; | |
6476 | case 0xcf: /* iret */ | |
872929aa | 6477 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); |
2c0262af FB |
6478 | if (!s->pe) { |
6479 | /* real mode */ | |
ab4e4aec | 6480 | gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); |
3ca51d07 | 6481 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 FB |
6482 | } else if (s->vm86) { |
6483 | if (s->iopl != 3) { | |
6484 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6485 | } else { | |
ab4e4aec | 6486 | gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); |
3ca51d07 | 6487 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 6488 | } |
2c0262af | 6489 | } else { |
773cdfcc | 6490 | gen_update_cc_op(s); |
14ce26e7 | 6491 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 6492 | gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1), |
a7812ae4 | 6493 | tcg_const_i32(s->pc - s->cs_base)); |
3ca51d07 | 6494 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6495 | } |
6496 | gen_eob(s); | |
6497 | break; | |
6498 | case 0xe8: /* call im */ | |
6499 | { | |
ab4e4aec | 6500 | if (dflag != MO_16) { |
4ba9938c | 6501 | tval = (int32_t)insn_get(env, s, MO_32); |
ab4e4aec | 6502 | } else { |
4ba9938c | 6503 | tval = (int16_t)insn_get(env, s, MO_16); |
ab4e4aec | 6504 | } |
2c0262af | 6505 | next_eip = s->pc - s->cs_base; |
14ce26e7 | 6506 | tval += next_eip; |
ab4e4aec | 6507 | if (dflag == MO_16) { |
14ce26e7 | 6508 | tval &= 0xffff; |
ab4e4aec | 6509 | } else if (!CODE64(s)) { |
99596385 | 6510 | tval &= 0xffffffff; |
ab4e4aec | 6511 | } |
cc0bce88 | 6512 | tcg_gen_movi_tl(cpu_T[0], next_eip); |
2c0262af | 6513 | gen_push_T0(s); |
14ce26e7 | 6514 | gen_jmp(s, tval); |
2c0262af FB |
6515 | } |
6516 | break; | |
6517 | case 0x9a: /* lcall im */ | |
6518 | { | |
6519 | unsigned int selector, offset; | |
3b46e624 | 6520 | |
14ce26e7 FB |
6521 | if (CODE64(s)) |
6522 | goto illegal_op; | |
ab4e4aec | 6523 | ot = dflag; |
0af10c86 | 6524 | offset = insn_get(env, s, ot); |
4ba9938c | 6525 | selector = insn_get(env, s, MO_16); |
3b46e624 | 6526 | |
1b90d56e | 6527 | tcg_gen_movi_tl(cpu_T[0], selector); |
0ae657b1 | 6528 | tcg_gen_movi_tl(cpu_T[1], offset); |
2c0262af FB |
6529 | } |
6530 | goto do_lcall; | |
ecada8a2 | 6531 | case 0xe9: /* jmp im */ |
ab4e4aec | 6532 | if (dflag != MO_16) { |
4ba9938c | 6533 | tval = (int32_t)insn_get(env, s, MO_32); |
ab4e4aec | 6534 | } else { |
4ba9938c | 6535 | tval = (int16_t)insn_get(env, s, MO_16); |
ab4e4aec | 6536 | } |
14ce26e7 | 6537 | tval += s->pc - s->cs_base; |
ab4e4aec | 6538 | if (dflag == MO_16) { |
14ce26e7 | 6539 | tval &= 0xffff; |
ab4e4aec | 6540 | } else if (!CODE64(s)) { |
32938e12 | 6541 | tval &= 0xffffffff; |
ab4e4aec | 6542 | } |
14ce26e7 | 6543 | gen_jmp(s, tval); |
2c0262af FB |
6544 | break; |
6545 | case 0xea: /* ljmp im */ | |
6546 | { | |
6547 | unsigned int selector, offset; | |
6548 | ||
14ce26e7 FB |
6549 | if (CODE64(s)) |
6550 | goto illegal_op; | |
ab4e4aec | 6551 | ot = dflag; |
0af10c86 | 6552 | offset = insn_get(env, s, ot); |
4ba9938c | 6553 | selector = insn_get(env, s, MO_16); |
3b46e624 | 6554 | |
1b90d56e | 6555 | tcg_gen_movi_tl(cpu_T[0], selector); |
0ae657b1 | 6556 | tcg_gen_movi_tl(cpu_T[1], offset); |
2c0262af FB |
6557 | } |
6558 | goto do_ljmp; | |
6559 | case 0xeb: /* jmp Jb */ | |
4ba9938c | 6560 | tval = (int8_t)insn_get(env, s, MO_8); |
14ce26e7 | 6561 | tval += s->pc - s->cs_base; |
ab4e4aec | 6562 | if (dflag == MO_16) { |
14ce26e7 | 6563 | tval &= 0xffff; |
ab4e4aec | 6564 | } |
14ce26e7 | 6565 | gen_jmp(s, tval); |
2c0262af FB |
6566 | break; |
6567 | case 0x70 ... 0x7f: /* jcc Jb */ | |
4ba9938c | 6568 | tval = (int8_t)insn_get(env, s, MO_8); |
2c0262af FB |
6569 | goto do_jcc; |
6570 | case 0x180 ... 0x18f: /* jcc Jv */ | |
ab4e4aec | 6571 | if (dflag != MO_16) { |
4ba9938c | 6572 | tval = (int32_t)insn_get(env, s, MO_32); |
2c0262af | 6573 | } else { |
4ba9938c | 6574 | tval = (int16_t)insn_get(env, s, MO_16); |
2c0262af FB |
6575 | } |
6576 | do_jcc: | |
6577 | next_eip = s->pc - s->cs_base; | |
14ce26e7 | 6578 | tval += next_eip; |
ab4e4aec | 6579 | if (dflag == MO_16) { |
14ce26e7 | 6580 | tval &= 0xffff; |
ab4e4aec | 6581 | } |
14ce26e7 | 6582 | gen_jcc(s, b, tval, next_eip); |
2c0262af FB |
6583 | break; |
6584 | ||
6585 | case 0x190 ... 0x19f: /* setcc Gv */ | |
0af10c86 | 6586 | modrm = cpu_ldub_code(env, s->pc++); |
cc8b6f5b | 6587 | gen_setcc1(s, b, cpu_T[0]); |
4ba9938c | 6588 | gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1); |
2c0262af FB |
6589 | break; |
6590 | case 0x140 ... 0x14f: /* cmov Gv, Ev */ | |
bff93281 PM |
6591 | if (!(s->cpuid_features & CPUID_CMOV)) { |
6592 | goto illegal_op; | |
6593 | } | |
ab4e4aec | 6594 | ot = dflag; |
f32d3781 PB |
6595 | modrm = cpu_ldub_code(env, s->pc++); |
6596 | reg = ((modrm >> 3) & 7) | rex_r; | |
6597 | gen_cmovcc1(env, s, ot, b, modrm, reg); | |
2c0262af | 6598 | break; |
3b46e624 | 6599 | |
2c0262af FB |
6600 | /************************/ |
6601 | /* flags */ | |
6602 | case 0x9c: /* pushf */ | |
872929aa | 6603 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); |
2c0262af FB |
6604 | if (s->vm86 && s->iopl != 3) { |
6605 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6606 | } else { | |
773cdfcc | 6607 | gen_update_cc_op(s); |
f0967a1a | 6608 | gen_helper_read_eflags(cpu_T[0], cpu_env); |
2c0262af FB |
6609 | gen_push_T0(s); |
6610 | } | |
6611 | break; | |
6612 | case 0x9d: /* popf */ | |
872929aa | 6613 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); |
2c0262af FB |
6614 | if (s->vm86 && s->iopl != 3) { |
6615 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6616 | } else { | |
6617 | gen_pop_T0(s); | |
6618 | if (s->cpl == 0) { | |
ab4e4aec | 6619 | if (dflag != MO_16) { |
f0967a1a BS |
6620 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6621 | tcg_const_i32((TF_MASK | AC_MASK | | |
6622 | ID_MASK | NT_MASK | | |
6623 | IF_MASK | | |
6624 | IOPL_MASK))); | |
2c0262af | 6625 | } else { |
f0967a1a BS |
6626 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6627 | tcg_const_i32((TF_MASK | AC_MASK | | |
6628 | ID_MASK | NT_MASK | | |
6629 | IF_MASK | IOPL_MASK) | |
6630 | & 0xffff)); | |
2c0262af FB |
6631 | } |
6632 | } else { | |
4136f33c | 6633 | if (s->cpl <= s->iopl) { |
ab4e4aec | 6634 | if (dflag != MO_16) { |
f0967a1a BS |
6635 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6636 | tcg_const_i32((TF_MASK | | |
6637 | AC_MASK | | |
6638 | ID_MASK | | |
6639 | NT_MASK | | |
6640 | IF_MASK))); | |
4136f33c | 6641 | } else { |
f0967a1a BS |
6642 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6643 | tcg_const_i32((TF_MASK | | |
6644 | AC_MASK | | |
6645 | ID_MASK | | |
6646 | NT_MASK | | |
6647 | IF_MASK) | |
6648 | & 0xffff)); | |
4136f33c | 6649 | } |
2c0262af | 6650 | } else { |
ab4e4aec | 6651 | if (dflag != MO_16) { |
f0967a1a BS |
6652 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6653 | tcg_const_i32((TF_MASK | AC_MASK | | |
6654 | ID_MASK | NT_MASK))); | |
4136f33c | 6655 | } else { |
f0967a1a BS |
6656 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6657 | tcg_const_i32((TF_MASK | AC_MASK | | |
6658 | ID_MASK | NT_MASK) | |
6659 | & 0xffff)); | |
4136f33c | 6660 | } |
2c0262af FB |
6661 | } |
6662 | } | |
6663 | gen_pop_update(s); | |
3ca51d07 | 6664 | set_cc_op(s, CC_OP_EFLAGS); |
a9321a4d | 6665 | /* abort translation because TF/AC flag may change */ |
14ce26e7 | 6666 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6667 | gen_eob(s); |
6668 | } | |
6669 | break; | |
6670 | case 0x9e: /* sahf */ | |
12e26b75 | 6671 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6672 | goto illegal_op; |
4ba9938c | 6673 | gen_op_mov_TN_reg(MO_8, 0, R_AH); |
d229edce | 6674 | gen_compute_eflags(s); |
bd7a7b33 FB |
6675 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); |
6676 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); | |
6677 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); | |
2c0262af FB |
6678 | break; |
6679 | case 0x9f: /* lahf */ | |
12e26b75 | 6680 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6681 | goto illegal_op; |
d229edce | 6682 | gen_compute_eflags(s); |
bd7a7b33 | 6683 | /* Note: gen_compute_eflags() only gives the condition codes */ |
d229edce | 6684 | tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02); |
4ba9938c | 6685 | gen_op_mov_reg_T0(MO_8, R_AH); |
2c0262af FB |
6686 | break; |
6687 | case 0xf5: /* cmc */ | |
d229edce | 6688 | gen_compute_eflags(s); |
bd7a7b33 | 6689 | tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6690 | break; |
6691 | case 0xf8: /* clc */ | |
d229edce | 6692 | gen_compute_eflags(s); |
bd7a7b33 | 6693 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); |
2c0262af FB |
6694 | break; |
6695 | case 0xf9: /* stc */ | |
d229edce | 6696 | gen_compute_eflags(s); |
bd7a7b33 | 6697 | tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6698 | break; |
6699 | case 0xfc: /* cld */ | |
b6abf97d | 6700 | tcg_gen_movi_i32(cpu_tmp2_i32, 1); |
317ac620 | 6701 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6702 | break; |
6703 | case 0xfd: /* std */ | |
b6abf97d | 6704 | tcg_gen_movi_i32(cpu_tmp2_i32, -1); |
317ac620 | 6705 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6706 | break; |
6707 | ||
6708 | /************************/ | |
6709 | /* bit operations */ | |
6710 | case 0x1ba: /* bt/bts/btr/btc Gv, im */ | |
ab4e4aec | 6711 | ot = dflag; |
0af10c86 | 6712 | modrm = cpu_ldub_code(env, s->pc++); |
33698e5f | 6713 | op = (modrm >> 3) & 7; |
2c0262af | 6714 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6715 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 6716 | if (mod != 3) { |
14ce26e7 | 6717 | s->rip_offset = 1; |
4eeb3939 | 6718 | gen_lea_modrm(env, s, modrm); |
909be183 | 6719 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 6720 | } else { |
57fec1fe | 6721 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
6722 | } |
6723 | /* load shift */ | |
0af10c86 | 6724 | val = cpu_ldub_code(env, s->pc++); |
0ae657b1 | 6725 | tcg_gen_movi_tl(cpu_T[1], val); |
2c0262af FB |
6726 | if (op < 4) |
6727 | goto illegal_op; | |
6728 | op -= 4; | |
f484d386 | 6729 | goto bt_op; |
2c0262af FB |
6730 | case 0x1a3: /* bt Gv, Ev */ |
6731 | op = 0; | |
6732 | goto do_btx; | |
6733 | case 0x1ab: /* bts */ | |
6734 | op = 1; | |
6735 | goto do_btx; | |
6736 | case 0x1b3: /* btr */ | |
6737 | op = 2; | |
6738 | goto do_btx; | |
6739 | case 0x1bb: /* btc */ | |
6740 | op = 3; | |
6741 | do_btx: | |
ab4e4aec | 6742 | ot = dflag; |
0af10c86 | 6743 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 6744 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 6745 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6746 | rm = (modrm & 7) | REX_B(s); |
4ba9938c | 6747 | gen_op_mov_TN_reg(MO_32, 1, reg); |
2c0262af | 6748 | if (mod != 3) { |
4eeb3939 | 6749 | gen_lea_modrm(env, s, modrm); |
2c0262af | 6750 | /* specific case: we need to add a displacement */ |
f484d386 FB |
6751 | gen_exts(ot, cpu_T[1]); |
6752 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); | |
6753 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); | |
6754 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
909be183 | 6755 | gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); |
2c0262af | 6756 | } else { |
57fec1fe | 6757 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 6758 | } |
f484d386 FB |
6759 | bt_op: |
6760 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); | |
6761 | switch(op) { | |
6762 | case 0: | |
6763 | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); | |
6764 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6765 | break; | |
6766 | case 1: | |
6767 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6768 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6769 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6770 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6771 | break; | |
6772 | case 2: | |
6773 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6774 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6775 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6776 | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); | |
6777 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6778 | break; | |
6779 | default: | |
6780 | case 3: | |
6781 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6782 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6783 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6784 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6785 | break; | |
6786 | } | |
3ca51d07 | 6787 | set_cc_op(s, CC_OP_SARB + ot); |
2c0262af | 6788 | if (op != 0) { |
fd8ca9f6 RH |
6789 | if (mod != 3) { |
6790 | gen_op_st_v(s, ot, cpu_T[0], cpu_A0); | |
6791 | } else { | |
57fec1fe | 6792 | gen_op_mov_reg_T0(ot, rm); |
fd8ca9f6 | 6793 | } |
f484d386 FB |
6794 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
6795 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
2c0262af FB |
6796 | } |
6797 | break; | |
321c5351 RH |
6798 | case 0x1bc: /* bsf / tzcnt */ |
6799 | case 0x1bd: /* bsr / lzcnt */ | |
ab4e4aec | 6800 | ot = dflag; |
321c5351 RH |
6801 | modrm = cpu_ldub_code(env, s->pc++); |
6802 | reg = ((modrm >> 3) & 7) | rex_r; | |
6803 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); | |
6804 | gen_extu(ot, cpu_T[0]); | |
6805 | ||
6806 | /* Note that lzcnt and tzcnt are in different extensions. */ | |
6807 | if ((prefixes & PREFIX_REPZ) | |
6808 | && (b & 1 | |
6809 | ? s->cpuid_ext3_features & CPUID_EXT3_ABM | |
6810 | : s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) { | |
6811 | int size = 8 << ot; | |
6812 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
6813 | if (b & 1) { | |
6814 | /* For lzcnt, reduce the target_ulong result by the | |
6815 | number of zeros that we expect to find at the top. */ | |
6816 | gen_helper_clz(cpu_T[0], cpu_T[0]); | |
6817 | tcg_gen_subi_tl(cpu_T[0], cpu_T[0], TARGET_LONG_BITS - size); | |
6191b059 | 6818 | } else { |
321c5351 RH |
6819 | /* For tzcnt, a zero input must return the operand size: |
6820 | force all bits outside the operand size to 1. */ | |
6821 | target_ulong mask = (target_ulong)-2 << (size - 1); | |
6822 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], mask); | |
6823 | gen_helper_ctz(cpu_T[0], cpu_T[0]); | |
6191b059 | 6824 | } |
321c5351 RH |
6825 | /* For lzcnt/tzcnt, C and Z bits are defined and are |
6826 | related to the result. */ | |
6827 | gen_op_update1_cc(); | |
6828 | set_cc_op(s, CC_OP_BMILGB + ot); | |
6829 | } else { | |
6830 | /* For bsr/bsf, only the Z bit is defined and it is related | |
6831 | to the input and not the result. */ | |
6832 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
6833 | set_cc_op(s, CC_OP_LOGICB + ot); | |
6834 | if (b & 1) { | |
6835 | /* For bsr, return the bit index of the first 1 bit, | |
6836 | not the count of leading zeros. */ | |
6837 | gen_helper_clz(cpu_T[0], cpu_T[0]); | |
6838 | tcg_gen_xori_tl(cpu_T[0], cpu_T[0], TARGET_LONG_BITS - 1); | |
6839 | } else { | |
6840 | gen_helper_ctz(cpu_T[0], cpu_T[0]); | |
6841 | } | |
6842 | /* ??? The manual says that the output is undefined when the | |
6843 | input is zero, but real hardware leaves it unchanged, and | |
6844 | real programs appear to depend on that. */ | |
6845 | tcg_gen_movi_tl(cpu_tmp0, 0); | |
6846 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[0], cpu_cc_dst, cpu_tmp0, | |
6847 | cpu_regs[reg], cpu_T[0]); | |
6191b059 | 6848 | } |
321c5351 | 6849 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
6850 | break; |
6851 | /************************/ | |
6852 | /* bcd */ | |
6853 | case 0x27: /* daa */ | |
14ce26e7 FB |
6854 | if (CODE64(s)) |
6855 | goto illegal_op; | |
773cdfcc | 6856 | gen_update_cc_op(s); |
7923057b | 6857 | gen_helper_daa(cpu_env); |
3ca51d07 | 6858 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6859 | break; |
6860 | case 0x2f: /* das */ | |
14ce26e7 FB |
6861 | if (CODE64(s)) |
6862 | goto illegal_op; | |
773cdfcc | 6863 | gen_update_cc_op(s); |
7923057b | 6864 | gen_helper_das(cpu_env); |
3ca51d07 | 6865 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6866 | break; |
6867 | case 0x37: /* aaa */ | |
14ce26e7 FB |
6868 | if (CODE64(s)) |
6869 | goto illegal_op; | |
773cdfcc | 6870 | gen_update_cc_op(s); |
7923057b | 6871 | gen_helper_aaa(cpu_env); |
3ca51d07 | 6872 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6873 | break; |
6874 | case 0x3f: /* aas */ | |
14ce26e7 FB |
6875 | if (CODE64(s)) |
6876 | goto illegal_op; | |
773cdfcc | 6877 | gen_update_cc_op(s); |
7923057b | 6878 | gen_helper_aas(cpu_env); |
3ca51d07 | 6879 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6880 | break; |
6881 | case 0xd4: /* aam */ | |
14ce26e7 FB |
6882 | if (CODE64(s)) |
6883 | goto illegal_op; | |
0af10c86 | 6884 | val = cpu_ldub_code(env, s->pc++); |
b6d7c3db TS |
6885 | if (val == 0) { |
6886 | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); | |
6887 | } else { | |
7923057b | 6888 | gen_helper_aam(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 6889 | set_cc_op(s, CC_OP_LOGICB); |
b6d7c3db | 6890 | } |
2c0262af FB |
6891 | break; |
6892 | case 0xd5: /* aad */ | |
14ce26e7 FB |
6893 | if (CODE64(s)) |
6894 | goto illegal_op; | |
0af10c86 | 6895 | val = cpu_ldub_code(env, s->pc++); |
7923057b | 6896 | gen_helper_aad(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 6897 | set_cc_op(s, CC_OP_LOGICB); |
2c0262af FB |
6898 | break; |
6899 | /************************/ | |
6900 | /* misc */ | |
6901 | case 0x90: /* nop */ | |
ab1f142b | 6902 | /* XXX: correct lock test for all insn */ |
7418027e | 6903 | if (prefixes & PREFIX_LOCK) { |
ab1f142b | 6904 | goto illegal_op; |
7418027e RH |
6905 | } |
6906 | /* If REX_B is set, then this is xchg eax, r8d, not a nop. */ | |
6907 | if (REX_B(s)) { | |
6908 | goto do_xchg_reg_eax; | |
6909 | } | |
0573fbfc | 6910 | if (prefixes & PREFIX_REPZ) { |
81f3053b PB |
6911 | gen_update_cc_op(s); |
6912 | gen_jmp_im(pc_start - s->cs_base); | |
6913 | gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); | |
6914 | s->is_jmp = DISAS_TB_JUMP; | |
0573fbfc | 6915 | } |
2c0262af FB |
6916 | break; |
6917 | case 0x9b: /* fwait */ | |
5fafdf24 | 6918 | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == |
7eee2a50 FB |
6919 | (HF_MP_MASK | HF_TS_MASK)) { |
6920 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
2ee73ac3 | 6921 | } else { |
773cdfcc | 6922 | gen_update_cc_op(s); |
14ce26e7 | 6923 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6924 | gen_helper_fwait(cpu_env); |
7eee2a50 | 6925 | } |
2c0262af FB |
6926 | break; |
6927 | case 0xcc: /* int3 */ | |
6928 | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); | |
6929 | break; | |
6930 | case 0xcd: /* int N */ | |
0af10c86 | 6931 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6932 | if (s->vm86 && s->iopl != 3) { |
5fafdf24 | 6933 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
f115e911 FB |
6934 | } else { |
6935 | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); | |
6936 | } | |
2c0262af FB |
6937 | break; |
6938 | case 0xce: /* into */ | |
14ce26e7 FB |
6939 | if (CODE64(s)) |
6940 | goto illegal_op; | |
773cdfcc | 6941 | gen_update_cc_op(s); |
a8ede8ba | 6942 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6943 | gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start)); |
2c0262af | 6944 | break; |
0b97134b | 6945 | #ifdef WANT_ICEBP |
2c0262af | 6946 | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
872929aa | 6947 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); |
aba9d61e | 6948 | #if 1 |
2c0262af | 6949 | gen_debug(s, pc_start - s->cs_base); |
aba9d61e FB |
6950 | #else |
6951 | /* start debug */ | |
0af10c86 | 6952 | tb_flush(env); |
24537a01 | 6953 | qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); |
aba9d61e | 6954 | #endif |
2c0262af | 6955 | break; |
0b97134b | 6956 | #endif |
2c0262af FB |
6957 | case 0xfa: /* cli */ |
6958 | if (!s->vm86) { | |
6959 | if (s->cpl <= s->iopl) { | |
f0967a1a | 6960 | gen_helper_cli(cpu_env); |
2c0262af FB |
6961 | } else { |
6962 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6963 | } | |
6964 | } else { | |
6965 | if (s->iopl == 3) { | |
f0967a1a | 6966 | gen_helper_cli(cpu_env); |
2c0262af FB |
6967 | } else { |
6968 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6969 | } | |
6970 | } | |
6971 | break; | |
6972 | case 0xfb: /* sti */ | |
6973 | if (!s->vm86) { | |
6974 | if (s->cpl <= s->iopl) { | |
6975 | gen_sti: | |
f0967a1a | 6976 | gen_helper_sti(cpu_env); |
2c0262af | 6977 | /* interruptions are enabled only the first insn after sti */ |
a2cc3b24 FB |
6978 | /* If several instructions disable interrupts, only the |
6979 | _first_ does it */ | |
6980 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 6981 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af | 6982 | /* give a chance to handle pending irqs */ |
14ce26e7 | 6983 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6984 | gen_eob(s); |
6985 | } else { | |
6986 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6987 | } | |
6988 | } else { | |
6989 | if (s->iopl == 3) { | |
6990 | goto gen_sti; | |
6991 | } else { | |
6992 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6993 | } | |
6994 | } | |
6995 | break; | |
6996 | case 0x62: /* bound */ | |
14ce26e7 FB |
6997 | if (CODE64(s)) |
6998 | goto illegal_op; | |
ab4e4aec | 6999 | ot = dflag; |
0af10c86 | 7000 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7001 | reg = (modrm >> 3) & 7; |
7002 | mod = (modrm >> 6) & 3; | |
7003 | if (mod == 3) | |
7004 | goto illegal_op; | |
57fec1fe | 7005 | gen_op_mov_TN_reg(ot, 0, reg); |
4eeb3939 | 7006 | gen_lea_modrm(env, s, modrm); |
14ce26e7 | 7007 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7008 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
4ba9938c | 7009 | if (ot == MO_16) { |
92fc4b58 BS |
7010 | gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32); |
7011 | } else { | |
7012 | gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32); | |
7013 | } | |
2c0262af FB |
7014 | break; |
7015 | case 0x1c8 ... 0x1cf: /* bswap reg */ | |
14ce26e7 FB |
7016 | reg = (b & 7) | REX_B(s); |
7017 | #ifdef TARGET_X86_64 | |
ab4e4aec | 7018 | if (dflag == MO_64) { |
4ba9938c | 7019 | gen_op_mov_TN_reg(MO_64, 0, reg); |
66896cb8 | 7020 | tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); |
4ba9938c | 7021 | gen_op_mov_reg_T0(MO_64, reg); |
5fafdf24 | 7022 | } else |
8777643e | 7023 | #endif |
57fec1fe | 7024 | { |
4ba9938c | 7025 | gen_op_mov_TN_reg(MO_32, 0, reg); |
8777643e AJ |
7026 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
7027 | tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); | |
4ba9938c | 7028 | gen_op_mov_reg_T0(MO_32, reg); |
14ce26e7 | 7029 | } |
2c0262af FB |
7030 | break; |
7031 | case 0xd6: /* salc */ | |
14ce26e7 FB |
7032 | if (CODE64(s)) |
7033 | goto illegal_op; | |
cc8b6f5b | 7034 | gen_compute_eflags_c(s, cpu_T[0]); |
bd7a7b33 | 7035 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 7036 | gen_op_mov_reg_T0(MO_8, R_EAX); |
2c0262af FB |
7037 | break; |
7038 | case 0xe0: /* loopnz */ | |
7039 | case 0xe1: /* loopz */ | |
2c0262af FB |
7040 | case 0xe2: /* loop */ |
7041 | case 0xe3: /* jecxz */ | |
14ce26e7 | 7042 | { |
6e0d8677 | 7043 | int l1, l2, l3; |
14ce26e7 | 7044 | |
4ba9938c | 7045 | tval = (int8_t)insn_get(env, s, MO_8); |
14ce26e7 FB |
7046 | next_eip = s->pc - s->cs_base; |
7047 | tval += next_eip; | |
ab4e4aec | 7048 | if (dflag == MO_16) { |
14ce26e7 | 7049 | tval &= 0xffff; |
ab4e4aec | 7050 | } |
3b46e624 | 7051 | |
14ce26e7 FB |
7052 | l1 = gen_new_label(); |
7053 | l2 = gen_new_label(); | |
6e0d8677 | 7054 | l3 = gen_new_label(); |
14ce26e7 | 7055 | b &= 3; |
6e0d8677 FB |
7056 | switch(b) { |
7057 | case 0: /* loopnz */ | |
7058 | case 1: /* loopz */ | |
1d71ddb1 RH |
7059 | gen_op_add_reg_im(s->aflag, R_ECX, -1); |
7060 | gen_op_jz_ecx(s->aflag, l3); | |
5bdb91b0 | 7061 | gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1); |
6e0d8677 FB |
7062 | break; |
7063 | case 2: /* loop */ | |
1d71ddb1 RH |
7064 | gen_op_add_reg_im(s->aflag, R_ECX, -1); |
7065 | gen_op_jnz_ecx(s->aflag, l1); | |
6e0d8677 FB |
7066 | break; |
7067 | default: | |
7068 | case 3: /* jcxz */ | |
1d71ddb1 | 7069 | gen_op_jz_ecx(s->aflag, l1); |
6e0d8677 | 7070 | break; |
14ce26e7 FB |
7071 | } |
7072 | ||
6e0d8677 | 7073 | gen_set_label(l3); |
14ce26e7 | 7074 | gen_jmp_im(next_eip); |
8e1c85e3 | 7075 | tcg_gen_br(l2); |
6e0d8677 | 7076 | |
14ce26e7 FB |
7077 | gen_set_label(l1); |
7078 | gen_jmp_im(tval); | |
7079 | gen_set_label(l2); | |
7080 | gen_eob(s); | |
7081 | } | |
2c0262af FB |
7082 | break; |
7083 | case 0x130: /* wrmsr */ | |
7084 | case 0x132: /* rdmsr */ | |
7085 | if (s->cpl != 0) { | |
7086 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7087 | } else { | |
773cdfcc | 7088 | gen_update_cc_op(s); |
872929aa | 7089 | gen_jmp_im(pc_start - s->cs_base); |
0573fbfc | 7090 | if (b & 2) { |
4a7443be | 7091 | gen_helper_rdmsr(cpu_env); |
0573fbfc | 7092 | } else { |
4a7443be | 7093 | gen_helper_wrmsr(cpu_env); |
0573fbfc | 7094 | } |
2c0262af FB |
7095 | } |
7096 | break; | |
7097 | case 0x131: /* rdtsc */ | |
773cdfcc | 7098 | gen_update_cc_op(s); |
ecada8a2 | 7099 | gen_jmp_im(pc_start - s->cs_base); |
efade670 PB |
7100 | if (use_icount) |
7101 | gen_io_start(); | |
4a7443be | 7102 | gen_helper_rdtsc(cpu_env); |
efade670 PB |
7103 | if (use_icount) { |
7104 | gen_io_end(); | |
7105 | gen_jmp(s, s->pc - s->cs_base); | |
7106 | } | |
2c0262af | 7107 | break; |
df01e0fc | 7108 | case 0x133: /* rdpmc */ |
773cdfcc | 7109 | gen_update_cc_op(s); |
df01e0fc | 7110 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7111 | gen_helper_rdpmc(cpu_env); |
df01e0fc | 7112 | break; |
023fe10d | 7113 | case 0x134: /* sysenter */ |
2436b61a | 7114 | /* For Intel SYSENTER is valid on 64-bit */ |
0af10c86 | 7115 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 7116 | goto illegal_op; |
023fe10d FB |
7117 | if (!s->pe) { |
7118 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7119 | } else { | |
728d803b | 7120 | gen_update_cc_op(s); |
14ce26e7 | 7121 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7122 | gen_helper_sysenter(cpu_env); |
023fe10d FB |
7123 | gen_eob(s); |
7124 | } | |
7125 | break; | |
7126 | case 0x135: /* sysexit */ | |
2436b61a | 7127 | /* For Intel SYSEXIT is valid on 64-bit */ |
0af10c86 | 7128 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 7129 | goto illegal_op; |
023fe10d FB |
7130 | if (!s->pe) { |
7131 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7132 | } else { | |
728d803b | 7133 | gen_update_cc_op(s); |
14ce26e7 | 7134 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 7135 | gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1)); |
023fe10d FB |
7136 | gen_eob(s); |
7137 | } | |
7138 | break; | |
14ce26e7 FB |
7139 | #ifdef TARGET_X86_64 |
7140 | case 0x105: /* syscall */ | |
7141 | /* XXX: is it usable in real mode ? */ | |
728d803b | 7142 | gen_update_cc_op(s); |
14ce26e7 | 7143 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7144 | gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start)); |
14ce26e7 FB |
7145 | gen_eob(s); |
7146 | break; | |
7147 | case 0x107: /* sysret */ | |
7148 | if (!s->pe) { | |
7149 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7150 | } else { | |
728d803b | 7151 | gen_update_cc_op(s); |
14ce26e7 | 7152 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 7153 | gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1)); |
aba9d61e | 7154 | /* condition codes are modified only in long mode */ |
3ca51d07 RH |
7155 | if (s->lma) { |
7156 | set_cc_op(s, CC_OP_EFLAGS); | |
7157 | } | |
14ce26e7 FB |
7158 | gen_eob(s); |
7159 | } | |
7160 | break; | |
7161 | #endif | |
2c0262af | 7162 | case 0x1a2: /* cpuid */ |
773cdfcc | 7163 | gen_update_cc_op(s); |
9575cb94 | 7164 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7165 | gen_helper_cpuid(cpu_env); |
2c0262af FB |
7166 | break; |
7167 | case 0xf4: /* hlt */ | |
7168 | if (s->cpl != 0) { | |
7169 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7170 | } else { | |
773cdfcc | 7171 | gen_update_cc_op(s); |
94451178 | 7172 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7173 | gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); |
5779406a | 7174 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
7175 | } |
7176 | break; | |
7177 | case 0x100: | |
0af10c86 | 7178 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7179 | mod = (modrm >> 6) & 3; |
7180 | op = (modrm >> 3) & 7; | |
7181 | switch(op) { | |
7182 | case 0: /* sldt */ | |
f115e911 FB |
7183 | if (!s->pe || s->vm86) |
7184 | goto illegal_op; | |
872929aa | 7185 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); |
651ba608 | 7186 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); |
ab4e4aec | 7187 | ot = mod == 3 ? dflag : MO_16; |
0af10c86 | 7188 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
7189 | break; |
7190 | case 2: /* lldt */ | |
f115e911 FB |
7191 | if (!s->pe || s->vm86) |
7192 | goto illegal_op; | |
2c0262af FB |
7193 | if (s->cpl != 0) { |
7194 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7195 | } else { | |
872929aa | 7196 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); |
4ba9938c | 7197 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
14ce26e7 | 7198 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7199 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7200 | gen_helper_lldt(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7201 | } |
7202 | break; | |
7203 | case 1: /* str */ | |
f115e911 FB |
7204 | if (!s->pe || s->vm86) |
7205 | goto illegal_op; | |
872929aa | 7206 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); |
651ba608 | 7207 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); |
ab4e4aec | 7208 | ot = mod == 3 ? dflag : MO_16; |
0af10c86 | 7209 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
7210 | break; |
7211 | case 3: /* ltr */ | |
f115e911 FB |
7212 | if (!s->pe || s->vm86) |
7213 | goto illegal_op; | |
2c0262af FB |
7214 | if (s->cpl != 0) { |
7215 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7216 | } else { | |
872929aa | 7217 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); |
4ba9938c | 7218 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
14ce26e7 | 7219 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7220 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7221 | gen_helper_ltr(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7222 | } |
7223 | break; | |
7224 | case 4: /* verr */ | |
7225 | case 5: /* verw */ | |
f115e911 FB |
7226 | if (!s->pe || s->vm86) |
7227 | goto illegal_op; | |
4ba9938c | 7228 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
773cdfcc | 7229 | gen_update_cc_op(s); |
2999a0b2 BS |
7230 | if (op == 4) { |
7231 | gen_helper_verr(cpu_env, cpu_T[0]); | |
7232 | } else { | |
7233 | gen_helper_verw(cpu_env, cpu_T[0]); | |
7234 | } | |
3ca51d07 | 7235 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 7236 | break; |
2c0262af FB |
7237 | default: |
7238 | goto illegal_op; | |
7239 | } | |
7240 | break; | |
7241 | case 0x101: | |
0af10c86 | 7242 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7243 | mod = (modrm >> 6) & 3; |
7244 | op = (modrm >> 3) & 7; | |
3d7374c5 | 7245 | rm = modrm & 7; |
2c0262af FB |
7246 | switch(op) { |
7247 | case 0: /* sgdt */ | |
2c0262af FB |
7248 | if (mod == 3) |
7249 | goto illegal_op; | |
872929aa | 7250 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); |
4eeb3939 | 7251 | gen_lea_modrm(env, s, modrm); |
651ba608 | 7252 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); |
fd8ca9f6 | 7253 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
aba9d61e | 7254 | gen_add_A0_im(s, 2); |
651ba608 | 7255 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); |
ab4e4aec | 7256 | if (dflag == MO_16) { |
f0706f0c RH |
7257 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff); |
7258 | } | |
fd8ca9f6 | 7259 | gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); |
2c0262af | 7260 | break; |
3d7374c5 FB |
7261 | case 1: |
7262 | if (mod == 3) { | |
7263 | switch (rm) { | |
7264 | case 0: /* monitor */ | |
7265 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7266 | s->cpl != 0) | |
7267 | goto illegal_op; | |
773cdfcc | 7268 | gen_update_cc_op(s); |
3d7374c5 | 7269 | gen_jmp_im(pc_start - s->cs_base); |
1d71ddb1 RH |
7270 | tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EAX]); |
7271 | gen_extu(s->aflag, cpu_A0); | |
3d7374c5 | 7272 | gen_add_A0_ds_seg(s); |
4a7443be | 7273 | gen_helper_monitor(cpu_env, cpu_A0); |
3d7374c5 FB |
7274 | break; |
7275 | case 1: /* mwait */ | |
7276 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7277 | s->cpl != 0) | |
7278 | goto illegal_op; | |
728d803b | 7279 | gen_update_cc_op(s); |
94451178 | 7280 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7281 | gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); |
3d7374c5 FB |
7282 | gen_eob(s); |
7283 | break; | |
a9321a4d PA |
7284 | case 2: /* clac */ |
7285 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7286 | s->cpl != 0) { | |
7287 | goto illegal_op; | |
7288 | } | |
7289 | gen_helper_clac(cpu_env); | |
7290 | gen_jmp_im(s->pc - s->cs_base); | |
7291 | gen_eob(s); | |
7292 | break; | |
7293 | case 3: /* stac */ | |
7294 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7295 | s->cpl != 0) { | |
7296 | goto illegal_op; | |
7297 | } | |
7298 | gen_helper_stac(cpu_env); | |
7299 | gen_jmp_im(s->pc - s->cs_base); | |
7300 | gen_eob(s); | |
7301 | break; | |
3d7374c5 FB |
7302 | default: |
7303 | goto illegal_op; | |
7304 | } | |
7305 | } else { /* sidt */ | |
872929aa | 7306 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); |
4eeb3939 | 7307 | gen_lea_modrm(env, s, modrm); |
651ba608 | 7308 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); |
fd8ca9f6 | 7309 | gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); |
3d7374c5 | 7310 | gen_add_A0_im(s, 2); |
651ba608 | 7311 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); |
ab4e4aec | 7312 | if (dflag == MO_16) { |
f0706f0c RH |
7313 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff); |
7314 | } | |
fd8ca9f6 | 7315 | gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); |
3d7374c5 FB |
7316 | } |
7317 | break; | |
2c0262af FB |
7318 | case 2: /* lgdt */ |
7319 | case 3: /* lidt */ | |
0573fbfc | 7320 | if (mod == 3) { |
773cdfcc | 7321 | gen_update_cc_op(s); |
872929aa | 7322 | gen_jmp_im(pc_start - s->cs_base); |
0573fbfc TS |
7323 | switch(rm) { |
7324 | case 0: /* VMRUN */ | |
872929aa FB |
7325 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7326 | goto illegal_op; | |
7327 | if (s->cpl != 0) { | |
7328 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
0573fbfc | 7329 | break; |
872929aa | 7330 | } else { |
1d71ddb1 | 7331 | gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), |
a7812ae4 | 7332 | tcg_const_i32(s->pc - pc_start)); |
db620f46 | 7333 | tcg_gen_exit_tb(0); |
5779406a | 7334 | s->is_jmp = DISAS_TB_JUMP; |
872929aa | 7335 | } |
0573fbfc TS |
7336 | break; |
7337 | case 1: /* VMMCALL */ | |
872929aa FB |
7338 | if (!(s->flags & HF_SVME_MASK)) |
7339 | goto illegal_op; | |
052e80d5 | 7340 | gen_helper_vmmcall(cpu_env); |
0573fbfc TS |
7341 | break; |
7342 | case 2: /* VMLOAD */ | |
872929aa FB |
7343 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7344 | goto illegal_op; | |
7345 | if (s->cpl != 0) { | |
7346 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7347 | break; | |
7348 | } else { | |
1d71ddb1 | 7349 | gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1)); |
872929aa | 7350 | } |
0573fbfc TS |
7351 | break; |
7352 | case 3: /* VMSAVE */ | |
872929aa FB |
7353 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7354 | goto illegal_op; | |
7355 | if (s->cpl != 0) { | |
7356 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7357 | break; | |
7358 | } else { | |
1d71ddb1 | 7359 | gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1)); |
872929aa | 7360 | } |
0573fbfc TS |
7361 | break; |
7362 | case 4: /* STGI */ | |
872929aa FB |
7363 | if ((!(s->flags & HF_SVME_MASK) && |
7364 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7365 | !s->pe) | |
7366 | goto illegal_op; | |
7367 | if (s->cpl != 0) { | |
7368 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7369 | break; | |
7370 | } else { | |
052e80d5 | 7371 | gen_helper_stgi(cpu_env); |
872929aa | 7372 | } |
0573fbfc TS |
7373 | break; |
7374 | case 5: /* CLGI */ | |
872929aa FB |
7375 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7376 | goto illegal_op; | |
7377 | if (s->cpl != 0) { | |
7378 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7379 | break; | |
7380 | } else { | |
052e80d5 | 7381 | gen_helper_clgi(cpu_env); |
872929aa | 7382 | } |
0573fbfc TS |
7383 | break; |
7384 | case 6: /* SKINIT */ | |
872929aa FB |
7385 | if ((!(s->flags & HF_SVME_MASK) && |
7386 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7387 | !s->pe) | |
7388 | goto illegal_op; | |
052e80d5 | 7389 | gen_helper_skinit(cpu_env); |
0573fbfc TS |
7390 | break; |
7391 | case 7: /* INVLPGA */ | |
872929aa FB |
7392 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7393 | goto illegal_op; | |
7394 | if (s->cpl != 0) { | |
7395 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7396 | break; | |
7397 | } else { | |
1d71ddb1 RH |
7398 | gen_helper_invlpga(cpu_env, |
7399 | tcg_const_i32(s->aflag - 1)); | |
872929aa | 7400 | } |
0573fbfc TS |
7401 | break; |
7402 | default: | |
7403 | goto illegal_op; | |
7404 | } | |
7405 | } else if (s->cpl != 0) { | |
2c0262af FB |
7406 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7407 | } else { | |
872929aa FB |
7408 | gen_svm_check_intercept(s, pc_start, |
7409 | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); | |
4eeb3939 | 7410 | gen_lea_modrm(env, s, modrm); |
0f712e10 | 7411 | gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0); |
aba9d61e | 7412 | gen_add_A0_im(s, 2); |
909be183 | 7413 | gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); |
ab4e4aec | 7414 | if (dflag == MO_16) { |
f0706f0c RH |
7415 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff); |
7416 | } | |
2c0262af | 7417 | if (op == 2) { |
651ba608 FB |
7418 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); |
7419 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); | |
2c0262af | 7420 | } else { |
651ba608 FB |
7421 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); |
7422 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); | |
2c0262af FB |
7423 | } |
7424 | } | |
7425 | break; | |
7426 | case 4: /* smsw */ | |
872929aa | 7427 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); |
e2542fe2 | 7428 | #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN |
f60d2728 | 7429 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); |
7430 | #else | |
651ba608 | 7431 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); |
f60d2728 | 7432 | #endif |
4ba9938c | 7433 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1); |
2c0262af FB |
7434 | break; |
7435 | case 6: /* lmsw */ | |
7436 | if (s->cpl != 0) { | |
7437 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7438 | } else { | |
872929aa | 7439 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
4ba9938c | 7440 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
4a7443be | 7441 | gen_helper_lmsw(cpu_env, cpu_T[0]); |
14ce26e7 | 7442 | gen_jmp_im(s->pc - s->cs_base); |
d71b9a8b | 7443 | gen_eob(s); |
2c0262af FB |
7444 | } |
7445 | break; | |
1b050077 AP |
7446 | case 7: |
7447 | if (mod != 3) { /* invlpg */ | |
7448 | if (s->cpl != 0) { | |
7449 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7450 | } else { | |
773cdfcc | 7451 | gen_update_cc_op(s); |
1b050077 | 7452 | gen_jmp_im(pc_start - s->cs_base); |
4eeb3939 | 7453 | gen_lea_modrm(env, s, modrm); |
4a7443be | 7454 | gen_helper_invlpg(cpu_env, cpu_A0); |
1b050077 AP |
7455 | gen_jmp_im(s->pc - s->cs_base); |
7456 | gen_eob(s); | |
7457 | } | |
2c0262af | 7458 | } else { |
1b050077 AP |
7459 | switch (rm) { |
7460 | case 0: /* swapgs */ | |
14ce26e7 | 7461 | #ifdef TARGET_X86_64 |
1b050077 AP |
7462 | if (CODE64(s)) { |
7463 | if (s->cpl != 0) { | |
7464 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7465 | } else { | |
7466 | tcg_gen_ld_tl(cpu_T[0], cpu_env, | |
7467 | offsetof(CPUX86State,segs[R_GS].base)); | |
7468 | tcg_gen_ld_tl(cpu_T[1], cpu_env, | |
7469 | offsetof(CPUX86State,kernelgsbase)); | |
7470 | tcg_gen_st_tl(cpu_T[1], cpu_env, | |
7471 | offsetof(CPUX86State,segs[R_GS].base)); | |
7472 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
7473 | offsetof(CPUX86State,kernelgsbase)); | |
7474 | } | |
5fafdf24 | 7475 | } else |
14ce26e7 FB |
7476 | #endif |
7477 | { | |
7478 | goto illegal_op; | |
7479 | } | |
1b050077 AP |
7480 | break; |
7481 | case 1: /* rdtscp */ | |
7482 | if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) | |
7483 | goto illegal_op; | |
773cdfcc | 7484 | gen_update_cc_op(s); |
9575cb94 | 7485 | gen_jmp_im(pc_start - s->cs_base); |
1b050077 AP |
7486 | if (use_icount) |
7487 | gen_io_start(); | |
4a7443be | 7488 | gen_helper_rdtscp(cpu_env); |
1b050077 AP |
7489 | if (use_icount) { |
7490 | gen_io_end(); | |
7491 | gen_jmp(s, s->pc - s->cs_base); | |
7492 | } | |
7493 | break; | |
7494 | default: | |
7495 | goto illegal_op; | |
14ce26e7 | 7496 | } |
2c0262af FB |
7497 | } |
7498 | break; | |
7499 | default: | |
7500 | goto illegal_op; | |
7501 | } | |
7502 | break; | |
3415a4dd FB |
7503 | case 0x108: /* invd */ |
7504 | case 0x109: /* wbinvd */ | |
7505 | if (s->cpl != 0) { | |
7506 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7507 | } else { | |
872929aa | 7508 | gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); |
3415a4dd FB |
7509 | /* nothing to do */ |
7510 | } | |
7511 | break; | |
14ce26e7 FB |
7512 | case 0x63: /* arpl or movslS (x86_64) */ |
7513 | #ifdef TARGET_X86_64 | |
7514 | if (CODE64(s)) { | |
7515 | int d_ot; | |
7516 | /* d_ot is the size of destination */ | |
ab4e4aec | 7517 | d_ot = dflag; |
14ce26e7 | 7518 | |
0af10c86 | 7519 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7520 | reg = ((modrm >> 3) & 7) | rex_r; |
7521 | mod = (modrm >> 6) & 3; | |
7522 | rm = (modrm & 7) | REX_B(s); | |
3b46e624 | 7523 | |
14ce26e7 | 7524 | if (mod == 3) { |
4ba9938c | 7525 | gen_op_mov_TN_reg(MO_32, 0, rm); |
14ce26e7 | 7526 | /* sign extend */ |
4ba9938c | 7527 | if (d_ot == MO_64) { |
e108dd01 | 7528 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4ba9938c | 7529 | } |
57fec1fe | 7530 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7531 | } else { |
4eeb3939 | 7532 | gen_lea_modrm(env, s, modrm); |
4b1fe067 | 7533 | gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0); |
57fec1fe | 7534 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7535 | } |
5fafdf24 | 7536 | } else |
14ce26e7 FB |
7537 | #endif |
7538 | { | |
3bd7da9e | 7539 | int label1; |
49d9fdcc | 7540 | TCGv t0, t1, t2, a0; |
1e4840bf | 7541 | |
14ce26e7 FB |
7542 | if (!s->pe || s->vm86) |
7543 | goto illegal_op; | |
a7812ae4 PB |
7544 | t0 = tcg_temp_local_new(); |
7545 | t1 = tcg_temp_local_new(); | |
7546 | t2 = tcg_temp_local_new(); | |
4ba9938c | 7547 | ot = MO_16; |
0af10c86 | 7548 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7549 | reg = (modrm >> 3) & 7; |
7550 | mod = (modrm >> 6) & 3; | |
7551 | rm = modrm & 7; | |
7552 | if (mod != 3) { | |
4eeb3939 | 7553 | gen_lea_modrm(env, s, modrm); |
323d1876 | 7554 | gen_op_ld_v(s, ot, t0, cpu_A0); |
49d9fdcc LD |
7555 | a0 = tcg_temp_local_new(); |
7556 | tcg_gen_mov_tl(a0, cpu_A0); | |
14ce26e7 | 7557 | } else { |
1e4840bf | 7558 | gen_op_mov_v_reg(ot, t0, rm); |
49d9fdcc | 7559 | TCGV_UNUSED(a0); |
14ce26e7 | 7560 | } |
1e4840bf FB |
7561 | gen_op_mov_v_reg(ot, t1, reg); |
7562 | tcg_gen_andi_tl(cpu_tmp0, t0, 3); | |
7563 | tcg_gen_andi_tl(t1, t1, 3); | |
7564 | tcg_gen_movi_tl(t2, 0); | |
3bd7da9e | 7565 | label1 = gen_new_label(); |
1e4840bf FB |
7566 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); |
7567 | tcg_gen_andi_tl(t0, t0, ~3); | |
7568 | tcg_gen_or_tl(t0, t0, t1); | |
7569 | tcg_gen_movi_tl(t2, CC_Z); | |
3bd7da9e | 7570 | gen_set_label(label1); |
14ce26e7 | 7571 | if (mod != 3) { |
323d1876 | 7572 | gen_op_st_v(s, ot, t0, a0); |
49d9fdcc LD |
7573 | tcg_temp_free(a0); |
7574 | } else { | |
1e4840bf | 7575 | gen_op_mov_reg_v(ot, rm, t0); |
14ce26e7 | 7576 | } |
d229edce | 7577 | gen_compute_eflags(s); |
3bd7da9e | 7578 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); |
1e4840bf | 7579 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); |
1e4840bf FB |
7580 | tcg_temp_free(t0); |
7581 | tcg_temp_free(t1); | |
7582 | tcg_temp_free(t2); | |
f115e911 | 7583 | } |
f115e911 | 7584 | break; |
2c0262af FB |
7585 | case 0x102: /* lar */ |
7586 | case 0x103: /* lsl */ | |
cec6843e FB |
7587 | { |
7588 | int label1; | |
1e4840bf | 7589 | TCGv t0; |
cec6843e FB |
7590 | if (!s->pe || s->vm86) |
7591 | goto illegal_op; | |
ab4e4aec | 7592 | ot = dflag != MO_16 ? MO_32 : MO_16; |
0af10c86 | 7593 | modrm = cpu_ldub_code(env, s->pc++); |
cec6843e | 7594 | reg = ((modrm >> 3) & 7) | rex_r; |
4ba9938c | 7595 | gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); |
a7812ae4 | 7596 | t0 = tcg_temp_local_new(); |
773cdfcc | 7597 | gen_update_cc_op(s); |
2999a0b2 BS |
7598 | if (b == 0x102) { |
7599 | gen_helper_lar(t0, cpu_env, cpu_T[0]); | |
7600 | } else { | |
7601 | gen_helper_lsl(t0, cpu_env, cpu_T[0]); | |
7602 | } | |
cec6843e FB |
7603 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); |
7604 | label1 = gen_new_label(); | |
cb63669a | 7605 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
1e4840bf | 7606 | gen_op_mov_reg_v(ot, reg, t0); |
cec6843e | 7607 | gen_set_label(label1); |
3ca51d07 | 7608 | set_cc_op(s, CC_OP_EFLAGS); |
1e4840bf | 7609 | tcg_temp_free(t0); |
cec6843e | 7610 | } |
2c0262af FB |
7611 | break; |
7612 | case 0x118: | |
0af10c86 | 7613 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7614 | mod = (modrm >> 6) & 3; |
7615 | op = (modrm >> 3) & 7; | |
7616 | switch(op) { | |
7617 | case 0: /* prefetchnta */ | |
7618 | case 1: /* prefetchnt0 */ | |
7619 | case 2: /* prefetchnt0 */ | |
7620 | case 3: /* prefetchnt0 */ | |
7621 | if (mod == 3) | |
7622 | goto illegal_op; | |
4eeb3939 | 7623 | gen_lea_modrm(env, s, modrm); |
2c0262af FB |
7624 | /* nothing more to do */ |
7625 | break; | |
e17a36ce | 7626 | default: /* nop (multi byte) */ |
0af10c86 | 7627 | gen_nop_modrm(env, s, modrm); |
e17a36ce | 7628 | break; |
2c0262af FB |
7629 | } |
7630 | break; | |
e17a36ce | 7631 | case 0x119 ... 0x11f: /* nop (multi byte) */ |
0af10c86 BS |
7632 | modrm = cpu_ldub_code(env, s->pc++); |
7633 | gen_nop_modrm(env, s, modrm); | |
e17a36ce | 7634 | break; |
2c0262af FB |
7635 | case 0x120: /* mov reg, crN */ |
7636 | case 0x122: /* mov crN, reg */ | |
7637 | if (s->cpl != 0) { | |
7638 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7639 | } else { | |
0af10c86 | 7640 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7641 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7642 | * AMD documentation (24594.pdf) and testing of | |
7643 | * intel 386 and 486 processors all show that the mod bits | |
7644 | * are assumed to be 1's, regardless of actual values. | |
7645 | */ | |
14ce26e7 FB |
7646 | rm = (modrm & 7) | REX_B(s); |
7647 | reg = ((modrm >> 3) & 7) | rex_r; | |
7648 | if (CODE64(s)) | |
4ba9938c | 7649 | ot = MO_64; |
14ce26e7 | 7650 | else |
4ba9938c | 7651 | ot = MO_32; |
ccd59d09 AP |
7652 | if ((prefixes & PREFIX_LOCK) && (reg == 0) && |
7653 | (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { | |
7654 | reg = 8; | |
7655 | } | |
2c0262af FB |
7656 | switch(reg) { |
7657 | case 0: | |
7658 | case 2: | |
7659 | case 3: | |
7660 | case 4: | |
9230e66e | 7661 | case 8: |
773cdfcc | 7662 | gen_update_cc_op(s); |
872929aa | 7663 | gen_jmp_im(pc_start - s->cs_base); |
2c0262af | 7664 | if (b & 2) { |
57fec1fe | 7665 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be BS |
7666 | gen_helper_write_crN(cpu_env, tcg_const_i32(reg), |
7667 | cpu_T[0]); | |
14ce26e7 | 7668 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7669 | gen_eob(s); |
7670 | } else { | |
4a7443be | 7671 | gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg)); |
57fec1fe | 7672 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7673 | } |
7674 | break; | |
7675 | default: | |
7676 | goto illegal_op; | |
7677 | } | |
7678 | } | |
7679 | break; | |
7680 | case 0x121: /* mov reg, drN */ | |
7681 | case 0x123: /* mov drN, reg */ | |
7682 | if (s->cpl != 0) { | |
7683 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7684 | } else { | |
0af10c86 | 7685 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7686 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7687 | * AMD documentation (24594.pdf) and testing of | |
7688 | * intel 386 and 486 processors all show that the mod bits | |
7689 | * are assumed to be 1's, regardless of actual values. | |
7690 | */ | |
14ce26e7 FB |
7691 | rm = (modrm & 7) | REX_B(s); |
7692 | reg = ((modrm >> 3) & 7) | rex_r; | |
7693 | if (CODE64(s)) | |
4ba9938c | 7694 | ot = MO_64; |
14ce26e7 | 7695 | else |
4ba9938c | 7696 | ot = MO_32; |
2c0262af | 7697 | /* XXX: do it dynamically with CR4.DE bit */ |
14ce26e7 | 7698 | if (reg == 4 || reg == 5 || reg >= 8) |
2c0262af FB |
7699 | goto illegal_op; |
7700 | if (b & 2) { | |
0573fbfc | 7701 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
57fec1fe | 7702 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be | 7703 | gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7704 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7705 | gen_eob(s); |
7706 | } else { | |
0573fbfc | 7707 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
651ba608 | 7708 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); |
57fec1fe | 7709 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7710 | } |
7711 | } | |
7712 | break; | |
7713 | case 0x106: /* clts */ | |
7714 | if (s->cpl != 0) { | |
7715 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7716 | } else { | |
0573fbfc | 7717 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
f0967a1a | 7718 | gen_helper_clts(cpu_env); |
7eee2a50 | 7719 | /* abort block because static cpu state changed */ |
14ce26e7 | 7720 | gen_jmp_im(s->pc - s->cs_base); |
7eee2a50 | 7721 | gen_eob(s); |
2c0262af FB |
7722 | } |
7723 | break; | |
222a3336 | 7724 | /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ |
664e0f19 FB |
7725 | case 0x1c3: /* MOVNTI reg, mem */ |
7726 | if (!(s->cpuid_features & CPUID_SSE2)) | |
14ce26e7 | 7727 | goto illegal_op; |
ab4e4aec | 7728 | ot = mo_64_32(dflag); |
0af10c86 | 7729 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7730 | mod = (modrm >> 6) & 3; |
7731 | if (mod == 3) | |
7732 | goto illegal_op; | |
7733 | reg = ((modrm >> 3) & 7) | rex_r; | |
7734 | /* generate a generic store */ | |
0af10c86 | 7735 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
14ce26e7 | 7736 | break; |
664e0f19 | 7737 | case 0x1ae: |
0af10c86 | 7738 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7739 | mod = (modrm >> 6) & 3; |
7740 | op = (modrm >> 3) & 7; | |
7741 | switch(op) { | |
7742 | case 0: /* fxsave */ | |
5fafdf24 | 7743 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7744 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7745 | goto illegal_op; |
09d85fb8 | 7746 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7747 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7748 | break; | |
7749 | } | |
4eeb3939 | 7750 | gen_lea_modrm(env, s, modrm); |
773cdfcc | 7751 | gen_update_cc_op(s); |
19e6c4b8 | 7752 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 7753 | gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64)); |
664e0f19 FB |
7754 | break; |
7755 | case 1: /* fxrstor */ | |
5fafdf24 | 7756 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7757 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7758 | goto illegal_op; |
09d85fb8 | 7759 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7760 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7761 | break; | |
7762 | } | |
4eeb3939 | 7763 | gen_lea_modrm(env, s, modrm); |
773cdfcc | 7764 | gen_update_cc_op(s); |
19e6c4b8 | 7765 | gen_jmp_im(pc_start - s->cs_base); |
ab4e4aec | 7766 | gen_helper_fxrstor(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64)); |
664e0f19 FB |
7767 | break; |
7768 | case 2: /* ldmxcsr */ | |
7769 | case 3: /* stmxcsr */ | |
7770 | if (s->flags & HF_TS_MASK) { | |
7771 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7772 | break; | |
14ce26e7 | 7773 | } |
664e0f19 FB |
7774 | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) || |
7775 | mod == 3) | |
14ce26e7 | 7776 | goto illegal_op; |
4eeb3939 | 7777 | gen_lea_modrm(env, s, modrm); |
664e0f19 | 7778 | if (op == 2) { |
80b02013 RH |
7779 | tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, |
7780 | s->mem_index, MO_LEUL); | |
d3eb5eae | 7781 | gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); |
14ce26e7 | 7782 | } else { |
651ba608 | 7783 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
fd8ca9f6 | 7784 | gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); |
14ce26e7 | 7785 | } |
664e0f19 FB |
7786 | break; |
7787 | case 5: /* lfence */ | |
7788 | case 6: /* mfence */ | |
8001c294 | 7789 | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) |
664e0f19 FB |
7790 | goto illegal_op; |
7791 | break; | |
8f091a59 FB |
7792 | case 7: /* sfence / clflush */ |
7793 | if ((modrm & 0xc7) == 0xc0) { | |
7794 | /* sfence */ | |
a35f3ec7 | 7795 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */ |
8f091a59 FB |
7796 | if (!(s->cpuid_features & CPUID_SSE)) |
7797 | goto illegal_op; | |
7798 | } else { | |
7799 | /* clflush */ | |
7800 | if (!(s->cpuid_features & CPUID_CLFLUSH)) | |
7801 | goto illegal_op; | |
4eeb3939 | 7802 | gen_lea_modrm(env, s, modrm); |
8f091a59 FB |
7803 | } |
7804 | break; | |
664e0f19 | 7805 | default: |
14ce26e7 FB |
7806 | goto illegal_op; |
7807 | } | |
7808 | break; | |
a35f3ec7 | 7809 | case 0x10d: /* 3DNow! prefetch(w) */ |
0af10c86 | 7810 | modrm = cpu_ldub_code(env, s->pc++); |
a35f3ec7 AJ |
7811 | mod = (modrm >> 6) & 3; |
7812 | if (mod == 3) | |
7813 | goto illegal_op; | |
4eeb3939 | 7814 | gen_lea_modrm(env, s, modrm); |
8f091a59 FB |
7815 | /* ignore for now */ |
7816 | break; | |
3b21e03e | 7817 | case 0x1aa: /* rsm */ |
872929aa | 7818 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); |
3b21e03e FB |
7819 | if (!(s->flags & HF_SMM_MASK)) |
7820 | goto illegal_op; | |
728d803b | 7821 | gen_update_cc_op(s); |
3b21e03e | 7822 | gen_jmp_im(s->pc - s->cs_base); |
608badfc | 7823 | gen_helper_rsm(cpu_env); |
3b21e03e FB |
7824 | gen_eob(s); |
7825 | break; | |
222a3336 AZ |
7826 | case 0x1b8: /* SSE4.2 popcnt */ |
7827 | if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != | |
7828 | PREFIX_REPZ) | |
7829 | goto illegal_op; | |
7830 | if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) | |
7831 | goto illegal_op; | |
7832 | ||
0af10c86 | 7833 | modrm = cpu_ldub_code(env, s->pc++); |
8b4a3df8 | 7834 | reg = ((modrm >> 3) & 7) | rex_r; |
222a3336 | 7835 | |
ab4e4aec | 7836 | if (s->prefix & PREFIX_DATA) { |
4ba9938c | 7837 | ot = MO_16; |
ab4e4aec RH |
7838 | } else { |
7839 | ot = mo_64_32(dflag); | |
7840 | } | |
222a3336 | 7841 | |
0af10c86 | 7842 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
d3eb5eae | 7843 | gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot)); |
222a3336 | 7844 | gen_op_mov_reg_T0(ot, reg); |
fdb0d09d | 7845 | |
3ca51d07 | 7846 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 | 7847 | break; |
a35f3ec7 AJ |
7848 | case 0x10e ... 0x10f: |
7849 | /* 3DNow! instructions, ignore prefixes */ | |
7850 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); | |
664e0f19 FB |
7851 | case 0x110 ... 0x117: |
7852 | case 0x128 ... 0x12f: | |
4242b1bd | 7853 | case 0x138 ... 0x13a: |
d9f4bb27 | 7854 | case 0x150 ... 0x179: |
664e0f19 FB |
7855 | case 0x17c ... 0x17f: |
7856 | case 0x1c2: | |
7857 | case 0x1c4 ... 0x1c6: | |
7858 | case 0x1d0 ... 0x1fe: | |
0af10c86 | 7859 | gen_sse(env, s, b, pc_start, rex_r); |
664e0f19 | 7860 | break; |
2c0262af FB |
7861 | default: |
7862 | goto illegal_op; | |
7863 | } | |
7864 | /* lock generation */ | |
7865 | if (s->prefix & PREFIX_LOCK) | |
a7812ae4 | 7866 | gen_helper_unlock(); |
2c0262af FB |
7867 | return s->pc; |
7868 | illegal_op: | |
ab1f142b | 7869 | if (s->prefix & PREFIX_LOCK) |
a7812ae4 | 7870 | gen_helper_unlock(); |
2c0262af FB |
7871 | /* XXX: ensure that no lock was generated */ |
7872 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
7873 | return s->pc; | |
7874 | } | |
7875 | ||
2c0262af FB |
7876 | void optimize_flags_init(void) |
7877 | { | |
a7812ae4 PB |
7878 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7879 | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 | 7880 | offsetof(CPUX86State, cc_op), "cc_op"); |
317ac620 | 7881 | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst), |
a7812ae4 | 7882 | "cc_dst"); |
a3251186 RH |
7883 | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src), |
7884 | "cc_src"); | |
988c3eb0 RH |
7885 | cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src2), |
7886 | "cc_src2"); | |
437a88a5 | 7887 | |
cc739bb0 LD |
7888 | #ifdef TARGET_X86_64 |
7889 | cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0, | |
317ac620 | 7890 | offsetof(CPUX86State, regs[R_EAX]), "rax"); |
cc739bb0 | 7891 | cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7892 | offsetof(CPUX86State, regs[R_ECX]), "rcx"); |
cc739bb0 | 7893 | cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7894 | offsetof(CPUX86State, regs[R_EDX]), "rdx"); |
cc739bb0 | 7895 | cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7896 | offsetof(CPUX86State, regs[R_EBX]), "rbx"); |
cc739bb0 | 7897 | cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7898 | offsetof(CPUX86State, regs[R_ESP]), "rsp"); |
cc739bb0 | 7899 | cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7900 | offsetof(CPUX86State, regs[R_EBP]), "rbp"); |
cc739bb0 | 7901 | cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7902 | offsetof(CPUX86State, regs[R_ESI]), "rsi"); |
cc739bb0 | 7903 | cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7904 | offsetof(CPUX86State, regs[R_EDI]), "rdi"); |
cc739bb0 | 7905 | cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7906 | offsetof(CPUX86State, regs[8]), "r8"); |
cc739bb0 | 7907 | cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7908 | offsetof(CPUX86State, regs[9]), "r9"); |
cc739bb0 | 7909 | cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7910 | offsetof(CPUX86State, regs[10]), "r10"); |
cc739bb0 | 7911 | cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7912 | offsetof(CPUX86State, regs[11]), "r11"); |
cc739bb0 | 7913 | cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7914 | offsetof(CPUX86State, regs[12]), "r12"); |
cc739bb0 | 7915 | cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7916 | offsetof(CPUX86State, regs[13]), "r13"); |
cc739bb0 | 7917 | cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7918 | offsetof(CPUX86State, regs[14]), "r14"); |
cc739bb0 | 7919 | cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7920 | offsetof(CPUX86State, regs[15]), "r15"); |
cc739bb0 LD |
7921 | #else |
7922 | cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 | 7923 | offsetof(CPUX86State, regs[R_EAX]), "eax"); |
cc739bb0 | 7924 | cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7925 | offsetof(CPUX86State, regs[R_ECX]), "ecx"); |
cc739bb0 | 7926 | cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7927 | offsetof(CPUX86State, regs[R_EDX]), "edx"); |
cc739bb0 | 7928 | cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7929 | offsetof(CPUX86State, regs[R_EBX]), "ebx"); |
cc739bb0 | 7930 | cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7931 | offsetof(CPUX86State, regs[R_ESP]), "esp"); |
cc739bb0 | 7932 | cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7933 | offsetof(CPUX86State, regs[R_EBP]), "ebp"); |
cc739bb0 | 7934 | cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7935 | offsetof(CPUX86State, regs[R_ESI]), "esi"); |
cc739bb0 | 7936 | cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7937 | offsetof(CPUX86State, regs[R_EDI]), "edi"); |
cc739bb0 | 7938 | #endif |
2c0262af FB |
7939 | } |
7940 | ||
7941 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for | |
7942 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
7943 | information for each intermediate instruction. */ | |
467215c2 | 7944 | static inline void gen_intermediate_code_internal(X86CPU *cpu, |
2cfc5f17 | 7945 | TranslationBlock *tb, |
467215c2 | 7946 | bool search_pc) |
2c0262af | 7947 | { |
ed2803da | 7948 | CPUState *cs = CPU(cpu); |
467215c2 | 7949 | CPUX86State *env = &cpu->env; |
2c0262af | 7950 | DisasContext dc1, *dc = &dc1; |
14ce26e7 | 7951 | target_ulong pc_ptr; |
2c0262af | 7952 | uint16_t *gen_opc_end; |
a1d1bb31 | 7953 | CPUBreakpoint *bp; |
7f5b7d3e | 7954 | int j, lj; |
c068688b | 7955 | uint64_t flags; |
14ce26e7 FB |
7956 | target_ulong pc_start; |
7957 | target_ulong cs_base; | |
2e70f6ef PB |
7958 | int num_insns; |
7959 | int max_insns; | |
3b46e624 | 7960 | |
2c0262af | 7961 | /* generate intermediate code */ |
14ce26e7 FB |
7962 | pc_start = tb->pc; |
7963 | cs_base = tb->cs_base; | |
2c0262af | 7964 | flags = tb->flags; |
3a1d9b8b | 7965 | |
4f31916f | 7966 | dc->pe = (flags >> HF_PE_SHIFT) & 1; |
2c0262af FB |
7967 | dc->code32 = (flags >> HF_CS32_SHIFT) & 1; |
7968 | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; | |
7969 | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; | |
7970 | dc->f_st = 0; | |
7971 | dc->vm86 = (flags >> VM_SHIFT) & 1; | |
7972 | dc->cpl = (flags >> HF_CPL_SHIFT) & 3; | |
7973 | dc->iopl = (flags >> IOPL_SHIFT) & 3; | |
7974 | dc->tf = (flags >> TF_SHIFT) & 1; | |
ed2803da | 7975 | dc->singlestep_enabled = cs->singlestep_enabled; |
2c0262af | 7976 | dc->cc_op = CC_OP_DYNAMIC; |
e207582f | 7977 | dc->cc_op_dirty = false; |
2c0262af FB |
7978 | dc->cs_base = cs_base; |
7979 | dc->tb = tb; | |
7980 | dc->popl_esp_hack = 0; | |
7981 | /* select memory access functions */ | |
7982 | dc->mem_index = 0; | |
7983 | if (flags & HF_SOFTMMU_MASK) { | |
5c42a7cd | 7984 | dc->mem_index = cpu_mmu_index(env); |
2c0262af | 7985 | } |
0514ef2f EH |
7986 | dc->cpuid_features = env->features[FEAT_1_EDX]; |
7987 | dc->cpuid_ext_features = env->features[FEAT_1_ECX]; | |
7988 | dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX]; | |
7989 | dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX]; | |
7990 | dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX]; | |
14ce26e7 FB |
7991 | #ifdef TARGET_X86_64 |
7992 | dc->lma = (flags >> HF_LMA_SHIFT) & 1; | |
7993 | dc->code64 = (flags >> HF_CS64_SHIFT) & 1; | |
7994 | #endif | |
7eee2a50 | 7995 | dc->flags = flags; |
ed2803da | 7996 | dc->jmp_opt = !(dc->tf || cs->singlestep_enabled || |
a2cc3b24 | 7997 | (flags & HF_INHIBIT_IRQ_MASK) |
415fa2ea | 7998 | #ifndef CONFIG_SOFTMMU |
2c0262af FB |
7999 | || (flags & HF_SOFTMMU_MASK) |
8000 | #endif | |
8001 | ); | |
4f31916f FB |
8002 | #if 0 |
8003 | /* check addseg logic */ | |
dc196a57 | 8004 | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) |
4f31916f FB |
8005 | printf("ERROR addseg\n"); |
8006 | #endif | |
8007 | ||
a7812ae4 PB |
8008 | cpu_T[0] = tcg_temp_new(); |
8009 | cpu_T[1] = tcg_temp_new(); | |
8010 | cpu_A0 = tcg_temp_new(); | |
a7812ae4 PB |
8011 | |
8012 | cpu_tmp0 = tcg_temp_new(); | |
8013 | cpu_tmp1_i64 = tcg_temp_new_i64(); | |
8014 | cpu_tmp2_i32 = tcg_temp_new_i32(); | |
8015 | cpu_tmp3_i32 = tcg_temp_new_i32(); | |
8016 | cpu_tmp4 = tcg_temp_new(); | |
a7812ae4 PB |
8017 | cpu_ptr0 = tcg_temp_new_ptr(); |
8018 | cpu_ptr1 = tcg_temp_new_ptr(); | |
a3251186 | 8019 | cpu_cc_srcT = tcg_temp_local_new(); |
57fec1fe | 8020 | |
92414b31 | 8021 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
8022 | |
8023 | dc->is_jmp = DISAS_NEXT; | |
8024 | pc_ptr = pc_start; | |
8025 | lj = -1; | |
2e70f6ef PB |
8026 | num_insns = 0; |
8027 | max_insns = tb->cflags & CF_COUNT_MASK; | |
8028 | if (max_insns == 0) | |
8029 | max_insns = CF_COUNT_MASK; | |
2c0262af | 8030 | |
806f352d | 8031 | gen_tb_start(); |
2c0262af | 8032 | for(;;) { |
72cf2d4f BS |
8033 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
8034 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a2397807 JK |
8035 | if (bp->pc == pc_ptr && |
8036 | !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { | |
2c0262af FB |
8037 | gen_debug(dc, pc_ptr - dc->cs_base); |
8038 | break; | |
8039 | } | |
8040 | } | |
8041 | } | |
8042 | if (search_pc) { | |
92414b31 | 8043 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
8044 | if (lj < j) { |
8045 | lj++; | |
8046 | while (lj < j) | |
ab1103de | 8047 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 8048 | } |
25983cad | 8049 | tcg_ctx.gen_opc_pc[lj] = pc_ptr; |
2c0262af | 8050 | gen_opc_cc_op[lj] = dc->cc_op; |
ab1103de | 8051 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 8052 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
2c0262af | 8053 | } |
2e70f6ef PB |
8054 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
8055 | gen_io_start(); | |
8056 | ||
0af10c86 | 8057 | pc_ptr = disas_insn(env, dc, pc_ptr); |
2e70f6ef | 8058 | num_insns++; |
2c0262af FB |
8059 | /* stop translation if indicated */ |
8060 | if (dc->is_jmp) | |
8061 | break; | |
8062 | /* if single step mode, we generate only one instruction and | |
8063 | generate an exception */ | |
a2cc3b24 FB |
8064 | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear |
8065 | the flag and abort the translation to give the irqs a | |
8066 | change to be happen */ | |
5fafdf24 | 8067 | if (dc->tf || dc->singlestep_enabled || |
2e70f6ef | 8068 | (flags & HF_INHIBIT_IRQ_MASK)) { |
14ce26e7 | 8069 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
8070 | gen_eob(dc); |
8071 | break; | |
8072 | } | |
8073 | /* if too long translation, stop generation too */ | |
efd7f486 | 8074 | if (tcg_ctx.gen_opc_ptr >= gen_opc_end || |
2e70f6ef PB |
8075 | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || |
8076 | num_insns >= max_insns) { | |
14ce26e7 | 8077 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
8078 | gen_eob(dc); |
8079 | break; | |
8080 | } | |
1b530a6d AJ |
8081 | if (singlestep) { |
8082 | gen_jmp_im(pc_ptr - dc->cs_base); | |
8083 | gen_eob(dc); | |
8084 | break; | |
8085 | } | |
2c0262af | 8086 | } |
2e70f6ef PB |
8087 | if (tb->cflags & CF_LAST_IO) |
8088 | gen_io_end(); | |
806f352d | 8089 | gen_tb_end(tb, num_insns); |
efd7f486 | 8090 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
2c0262af FB |
8091 | /* we don't forget to fill the last values */ |
8092 | if (search_pc) { | |
92414b31 | 8093 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
8094 | lj++; |
8095 | while (lj <= j) | |
ab1103de | 8096 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 8097 | } |
3b46e624 | 8098 | |
2c0262af | 8099 | #ifdef DEBUG_DISAS |
8fec2b8c | 8100 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
14ce26e7 | 8101 | int disas_flags; |
93fcfe39 AL |
8102 | qemu_log("----------------\n"); |
8103 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
14ce26e7 FB |
8104 | #ifdef TARGET_X86_64 |
8105 | if (dc->code64) | |
8106 | disas_flags = 2; | |
8107 | else | |
8108 | #endif | |
8109 | disas_flags = !dc->code32; | |
f4359b9f | 8110 | log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags); |
93fcfe39 | 8111 | qemu_log("\n"); |
2c0262af FB |
8112 | } |
8113 | #endif | |
8114 | ||
2e70f6ef | 8115 | if (!search_pc) { |
2c0262af | 8116 | tb->size = pc_ptr - pc_start; |
2e70f6ef PB |
8117 | tb->icount = num_insns; |
8118 | } | |
2c0262af FB |
8119 | } |
8120 | ||
317ac620 | 8121 | void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 8122 | { |
467215c2 | 8123 | gen_intermediate_code_internal(x86_env_get_cpu(env), tb, false); |
2c0262af FB |
8124 | } |
8125 | ||
317ac620 | 8126 | void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 8127 | { |
467215c2 | 8128 | gen_intermediate_code_internal(x86_env_get_cpu(env), tb, true); |
2c0262af FB |
8129 | } |
8130 | ||
317ac620 | 8131 | void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos) |
d2856f1a AJ |
8132 | { |
8133 | int cc_op; | |
8134 | #ifdef DEBUG_DISAS | |
8fec2b8c | 8135 | if (qemu_loglevel_mask(CPU_LOG_TB_OP)) { |
d2856f1a | 8136 | int i; |
93fcfe39 | 8137 | qemu_log("RESTORE:\n"); |
d2856f1a | 8138 | for(i = 0;i <= pc_pos; i++) { |
ab1103de | 8139 | if (tcg_ctx.gen_opc_instr_start[i]) { |
25983cad EV |
8140 | qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, |
8141 | tcg_ctx.gen_opc_pc[i]); | |
d2856f1a AJ |
8142 | } |
8143 | } | |
e87b7cb0 | 8144 | qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
25983cad | 8145 | pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base, |
d2856f1a AJ |
8146 | (uint32_t)tb->cs_base); |
8147 | } | |
8148 | #endif | |
25983cad | 8149 | env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base; |
d2856f1a AJ |
8150 | cc_op = gen_opc_cc_op[pc_pos]; |
8151 | if (cc_op != CC_OP_DYNAMIC) | |
8152 | env->cc_op = cc_op; | |
8153 | } |