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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 translation | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
2c0262af | 25 | |
bec93d72 | 26 | #include "qemu/host-utils.h" |
2c0262af | 27 | #include "cpu.h" |
76cad711 | 28 | #include "disas/disas.h" |
57fec1fe | 29 | #include "tcg-op.h" |
2c0262af | 30 | |
a7812ae4 PB |
31 | #include "helper.h" |
32 | #define GEN_HELPER 1 | |
33 | #include "helper.h" | |
34 | ||
2c0262af FB |
35 | #define PREFIX_REPZ 0x01 |
36 | #define PREFIX_REPNZ 0x02 | |
37 | #define PREFIX_LOCK 0x04 | |
38 | #define PREFIX_DATA 0x08 | |
39 | #define PREFIX_ADR 0x10 | |
40 | ||
14ce26e7 | 41 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
42 | #define CODE64(s) ((s)->code64) |
43 | #define REX_X(s) ((s)->rex_x) | |
44 | #define REX_B(s) ((s)->rex_b) | |
14ce26e7 | 45 | #else |
14ce26e7 FB |
46 | #define CODE64(s) 0 |
47 | #define REX_X(s) 0 | |
48 | #define REX_B(s) 0 | |
49 | #endif | |
50 | ||
bec93d72 RH |
51 | #ifdef TARGET_X86_64 |
52 | # define ctztl ctz64 | |
53 | # define clztl clz64 | |
54 | #else | |
55 | # define ctztl ctz32 | |
56 | # define clztl clz32 | |
57 | #endif | |
58 | ||
57fec1fe FB |
59 | //#define MACRO_TEST 1 |
60 | ||
57fec1fe | 61 | /* global register indexes */ |
a7812ae4 | 62 | static TCGv_ptr cpu_env; |
f5847c91 | 63 | static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst; |
a7812ae4 | 64 | static TCGv_i32 cpu_cc_op; |
cc739bb0 | 65 | static TCGv cpu_regs[CPU_NB_REGS]; |
1e4840bf | 66 | /* local temps */ |
3b9d3cf1 | 67 | static TCGv cpu_T[2]; |
57fec1fe | 68 | /* local register indexes (only used inside old micro ops) */ |
a7812ae4 PB |
69 | static TCGv cpu_tmp0, cpu_tmp4; |
70 | static TCGv_ptr cpu_ptr0, cpu_ptr1; | |
71 | static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; | |
72 | static TCGv_i64 cpu_tmp1_i64; | |
bedda79c | 73 | static TCGv cpu_tmp5; |
57fec1fe | 74 | |
1a7ff922 PB |
75 | static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
76 | ||
022c62cb | 77 | #include "exec/gen-icount.h" |
2e70f6ef | 78 | |
57fec1fe FB |
79 | #ifdef TARGET_X86_64 |
80 | static int x86_64_hregs; | |
ae063a68 FB |
81 | #endif |
82 | ||
2c0262af FB |
83 | typedef struct DisasContext { |
84 | /* current insn context */ | |
85 | int override; /* -1 if no override */ | |
86 | int prefix; | |
87 | int aflag, dflag; | |
14ce26e7 | 88 | target_ulong pc; /* pc = eip + cs_base */ |
2c0262af FB |
89 | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
90 | static state change (stop translation) */ | |
91 | /* current block context */ | |
14ce26e7 | 92 | target_ulong cs_base; /* base of CS segment */ |
2c0262af FB |
93 | int pe; /* protected mode */ |
94 | int code32; /* 32 bit code segment */ | |
14ce26e7 FB |
95 | #ifdef TARGET_X86_64 |
96 | int lma; /* long mode active */ | |
97 | int code64; /* 64 bit code segment */ | |
98 | int rex_x, rex_b; | |
99 | #endif | |
2c0262af | 100 | int ss32; /* 32 bit stack segment */ |
fee71888 | 101 | CCOp cc_op; /* current CC operation */ |
e207582f | 102 | bool cc_op_dirty; |
2c0262af FB |
103 | int addseg; /* non zero if either DS/ES/SS have a non zero base */ |
104 | int f_st; /* currently unused */ | |
105 | int vm86; /* vm86 mode */ | |
106 | int cpl; | |
107 | int iopl; | |
108 | int tf; /* TF cpu flag */ | |
34865134 | 109 | int singlestep_enabled; /* "hardware" single step enabled */ |
2c0262af FB |
110 | int jmp_opt; /* use direct block chaining for direct jumps */ |
111 | int mem_index; /* select memory access functions */ | |
c068688b | 112 | uint64_t flags; /* all execution flags */ |
2c0262af FB |
113 | struct TranslationBlock *tb; |
114 | int popl_esp_hack; /* for correct popl with esp base handling */ | |
14ce26e7 FB |
115 | int rip_offset; /* only used in x86_64, but left for simplicity */ |
116 | int cpuid_features; | |
3d7374c5 | 117 | int cpuid_ext_features; |
e771edab | 118 | int cpuid_ext2_features; |
12e26b75 | 119 | int cpuid_ext3_features; |
a9321a4d | 120 | int cpuid_7_0_ebx_features; |
2c0262af FB |
121 | } DisasContext; |
122 | ||
123 | static void gen_eob(DisasContext *s); | |
14ce26e7 FB |
124 | static void gen_jmp(DisasContext *s, target_ulong eip); |
125 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); | |
63633fe6 | 126 | static void gen_op(DisasContext *s1, int op, int ot, int d); |
2c0262af FB |
127 | |
128 | /* i386 arith/logic operations */ | |
129 | enum { | |
5fafdf24 TS |
130 | OP_ADDL, |
131 | OP_ORL, | |
132 | OP_ADCL, | |
2c0262af | 133 | OP_SBBL, |
5fafdf24 TS |
134 | OP_ANDL, |
135 | OP_SUBL, | |
136 | OP_XORL, | |
2c0262af FB |
137 | OP_CMPL, |
138 | }; | |
139 | ||
140 | /* i386 shift ops */ | |
141 | enum { | |
5fafdf24 TS |
142 | OP_ROL, |
143 | OP_ROR, | |
144 | OP_RCL, | |
145 | OP_RCR, | |
146 | OP_SHL, | |
147 | OP_SHR, | |
2c0262af FB |
148 | OP_SHL1, /* undocumented */ |
149 | OP_SAR = 7, | |
150 | }; | |
151 | ||
8e1c85e3 FB |
152 | enum { |
153 | JCC_O, | |
154 | JCC_B, | |
155 | JCC_Z, | |
156 | JCC_BE, | |
157 | JCC_S, | |
158 | JCC_P, | |
159 | JCC_L, | |
160 | JCC_LE, | |
161 | }; | |
162 | ||
2c0262af FB |
163 | /* operand size */ |
164 | enum { | |
165 | OT_BYTE = 0, | |
166 | OT_WORD, | |
5fafdf24 | 167 | OT_LONG, |
2c0262af FB |
168 | OT_QUAD, |
169 | }; | |
170 | ||
171 | enum { | |
172 | /* I386 int registers */ | |
173 | OR_EAX, /* MUST be even numbered */ | |
174 | OR_ECX, | |
175 | OR_EDX, | |
176 | OR_EBX, | |
177 | OR_ESP, | |
178 | OR_EBP, | |
179 | OR_ESI, | |
180 | OR_EDI, | |
14ce26e7 FB |
181 | |
182 | OR_TMP0 = 16, /* temporary operand register */ | |
2c0262af FB |
183 | OR_TMP1, |
184 | OR_A0, /* temporary register used when doing address evaluation */ | |
2c0262af FB |
185 | }; |
186 | ||
b666265b RH |
187 | enum { |
188 | USES_CC_DST = 1, | |
189 | USES_CC_SRC = 2, | |
190 | }; | |
191 | ||
192 | /* Bit set if the global variable is live after setting CC_OP to X. */ | |
193 | static const uint8_t cc_op_live[CC_OP_NB] = { | |
194 | [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC, | |
195 | [CC_OP_EFLAGS] = USES_CC_SRC, | |
196 | [CC_OP_MULB ... CC_OP_MULQ] = USES_CC_DST | USES_CC_SRC, | |
197 | [CC_OP_ADDB ... CC_OP_ADDQ] = USES_CC_DST | USES_CC_SRC, | |
198 | [CC_OP_ADCB ... CC_OP_ADCQ] = USES_CC_DST | USES_CC_SRC, | |
199 | [CC_OP_SUBB ... CC_OP_SUBQ] = USES_CC_DST | USES_CC_SRC, | |
200 | [CC_OP_SBBB ... CC_OP_SBBQ] = USES_CC_DST | USES_CC_SRC, | |
201 | [CC_OP_LOGICB ... CC_OP_LOGICQ] = USES_CC_DST, | |
202 | [CC_OP_INCB ... CC_OP_INCQ] = USES_CC_DST | USES_CC_SRC, | |
203 | [CC_OP_DECB ... CC_OP_DECQ] = USES_CC_DST | USES_CC_SRC, | |
204 | [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC, | |
205 | [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC, | |
206 | }; | |
207 | ||
e207582f | 208 | static void set_cc_op(DisasContext *s, CCOp op) |
3ca51d07 | 209 | { |
b666265b RH |
210 | int dead; |
211 | ||
212 | if (s->cc_op == op) { | |
213 | return; | |
214 | } | |
215 | ||
216 | /* Discard CC computation that will no longer be used. */ | |
217 | dead = cc_op_live[s->cc_op] & ~cc_op_live[op]; | |
218 | if (dead & USES_CC_DST) { | |
219 | tcg_gen_discard_tl(cpu_cc_dst); | |
e207582f | 220 | } |
b666265b RH |
221 | if (dead & USES_CC_SRC) { |
222 | tcg_gen_discard_tl(cpu_cc_src); | |
223 | } | |
224 | ||
225 | s->cc_op = op; | |
226 | /* The DYNAMIC setting is translator only, and should never be | |
227 | stored. Thus we always consider it clean. */ | |
228 | s->cc_op_dirty = (op != CC_OP_DYNAMIC); | |
e207582f RH |
229 | } |
230 | ||
e207582f RH |
231 | static void gen_update_cc_op(DisasContext *s) |
232 | { | |
233 | if (s->cc_op_dirty) { | |
773cdfcc | 234 | tcg_gen_movi_i32(cpu_cc_op, s->cc_op); |
e207582f RH |
235 | s->cc_op_dirty = false; |
236 | } | |
3ca51d07 RH |
237 | } |
238 | ||
57fec1fe FB |
239 | static inline void gen_op_movl_T0_0(void) |
240 | { | |
241 | tcg_gen_movi_tl(cpu_T[0], 0); | |
242 | } | |
243 | ||
244 | static inline void gen_op_movl_T0_im(int32_t val) | |
245 | { | |
246 | tcg_gen_movi_tl(cpu_T[0], val); | |
247 | } | |
248 | ||
249 | static inline void gen_op_movl_T0_imu(uint32_t val) | |
250 | { | |
251 | tcg_gen_movi_tl(cpu_T[0], val); | |
252 | } | |
253 | ||
254 | static inline void gen_op_movl_T1_im(int32_t val) | |
255 | { | |
256 | tcg_gen_movi_tl(cpu_T[1], val); | |
257 | } | |
258 | ||
259 | static inline void gen_op_movl_T1_imu(uint32_t val) | |
260 | { | |
261 | tcg_gen_movi_tl(cpu_T[1], val); | |
262 | } | |
263 | ||
264 | static inline void gen_op_movl_A0_im(uint32_t val) | |
265 | { | |
266 | tcg_gen_movi_tl(cpu_A0, val); | |
267 | } | |
268 | ||
269 | #ifdef TARGET_X86_64 | |
270 | static inline void gen_op_movq_A0_im(int64_t val) | |
271 | { | |
272 | tcg_gen_movi_tl(cpu_A0, val); | |
273 | } | |
274 | #endif | |
275 | ||
276 | static inline void gen_movtl_T0_im(target_ulong val) | |
277 | { | |
278 | tcg_gen_movi_tl(cpu_T[0], val); | |
279 | } | |
280 | ||
281 | static inline void gen_movtl_T1_im(target_ulong val) | |
282 | { | |
283 | tcg_gen_movi_tl(cpu_T[1], val); | |
284 | } | |
285 | ||
286 | static inline void gen_op_andl_T0_ffff(void) | |
287 | { | |
288 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
289 | } | |
290 | ||
291 | static inline void gen_op_andl_T0_im(uint32_t val) | |
292 | { | |
293 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); | |
294 | } | |
295 | ||
296 | static inline void gen_op_movl_T0_T1(void) | |
297 | { | |
298 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); | |
299 | } | |
300 | ||
301 | static inline void gen_op_andl_A0_ffff(void) | |
302 | { | |
303 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff); | |
304 | } | |
305 | ||
14ce26e7 FB |
306 | #ifdef TARGET_X86_64 |
307 | ||
308 | #define NB_OP_SIZES 4 | |
309 | ||
14ce26e7 FB |
310 | #else /* !TARGET_X86_64 */ |
311 | ||
312 | #define NB_OP_SIZES 3 | |
313 | ||
14ce26e7 FB |
314 | #endif /* !TARGET_X86_64 */ |
315 | ||
e2542fe2 | 316 | #if defined(HOST_WORDS_BIGENDIAN) |
57fec1fe FB |
317 | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
318 | #define REG_H_OFFSET (sizeof(target_ulong) - 2) | |
319 | #define REG_W_OFFSET (sizeof(target_ulong) - 2) | |
320 | #define REG_L_OFFSET (sizeof(target_ulong) - 4) | |
321 | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) | |
14ce26e7 | 322 | #else |
57fec1fe FB |
323 | #define REG_B_OFFSET 0 |
324 | #define REG_H_OFFSET 1 | |
325 | #define REG_W_OFFSET 0 | |
326 | #define REG_L_OFFSET 0 | |
327 | #define REG_LH_OFFSET 4 | |
14ce26e7 | 328 | #endif |
57fec1fe | 329 | |
96d7073f PM |
330 | /* In instruction encodings for byte register accesses the |
331 | * register number usually indicates "low 8 bits of register N"; | |
332 | * however there are some special cases where N 4..7 indicates | |
333 | * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return | |
334 | * true for this special case, false otherwise. | |
335 | */ | |
336 | static inline bool byte_reg_is_xH(int reg) | |
337 | { | |
338 | if (reg < 4) { | |
339 | return false; | |
340 | } | |
341 | #ifdef TARGET_X86_64 | |
342 | if (reg >= 8 || x86_64_hregs) { | |
343 | return false; | |
344 | } | |
345 | #endif | |
346 | return true; | |
347 | } | |
348 | ||
1e4840bf | 349 | static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) |
57fec1fe FB |
350 | { |
351 | switch(ot) { | |
352 | case OT_BYTE: | |
96d7073f | 353 | if (!byte_reg_is_xH(reg)) { |
c832e3de | 354 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); |
57fec1fe | 355 | } else { |
c832e3de | 356 | tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); |
57fec1fe FB |
357 | } |
358 | break; | |
359 | case OT_WORD: | |
c832e3de | 360 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16); |
57fec1fe | 361 | break; |
cc739bb0 | 362 | default: /* XXX this shouldn't be reached; abort? */ |
57fec1fe | 363 | case OT_LONG: |
cc739bb0 LD |
364 | /* For x86_64, this sets the higher half of register to zero. |
365 | For i386, this is equivalent to a mov. */ | |
366 | tcg_gen_ext32u_tl(cpu_regs[reg], t0); | |
57fec1fe | 367 | break; |
cc739bb0 | 368 | #ifdef TARGET_X86_64 |
57fec1fe | 369 | case OT_QUAD: |
cc739bb0 | 370 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
57fec1fe | 371 | break; |
14ce26e7 | 372 | #endif |
57fec1fe FB |
373 | } |
374 | } | |
2c0262af | 375 | |
57fec1fe FB |
376 | static inline void gen_op_mov_reg_T0(int ot, int reg) |
377 | { | |
1e4840bf | 378 | gen_op_mov_reg_v(ot, reg, cpu_T[0]); |
57fec1fe FB |
379 | } |
380 | ||
381 | static inline void gen_op_mov_reg_T1(int ot, int reg) | |
382 | { | |
1e4840bf | 383 | gen_op_mov_reg_v(ot, reg, cpu_T[1]); |
57fec1fe FB |
384 | } |
385 | ||
386 | static inline void gen_op_mov_reg_A0(int size, int reg) | |
387 | { | |
388 | switch(size) { | |
93ab25d7 | 389 | case OT_BYTE: |
c832e3de | 390 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16); |
57fec1fe | 391 | break; |
cc739bb0 | 392 | default: /* XXX this shouldn't be reached; abort? */ |
93ab25d7 | 393 | case OT_WORD: |
cc739bb0 LD |
394 | /* For x86_64, this sets the higher half of register to zero. |
395 | For i386, this is equivalent to a mov. */ | |
396 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0); | |
57fec1fe | 397 | break; |
cc739bb0 | 398 | #ifdef TARGET_X86_64 |
93ab25d7 | 399 | case OT_LONG: |
cc739bb0 | 400 | tcg_gen_mov_tl(cpu_regs[reg], cpu_A0); |
57fec1fe | 401 | break; |
14ce26e7 | 402 | #endif |
57fec1fe FB |
403 | } |
404 | } | |
405 | ||
1e4840bf | 406 | static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) |
57fec1fe | 407 | { |
96d7073f PM |
408 | if (ot == OT_BYTE && byte_reg_is_xH(reg)) { |
409 | tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); | |
410 | tcg_gen_ext8u_tl(t0, t0); | |
411 | } else { | |
cc739bb0 | 412 | tcg_gen_mov_tl(t0, cpu_regs[reg]); |
57fec1fe FB |
413 | } |
414 | } | |
415 | ||
1e4840bf FB |
416 | static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) |
417 | { | |
418 | gen_op_mov_v_reg(ot, cpu_T[t_index], reg); | |
419 | } | |
420 | ||
57fec1fe FB |
421 | static inline void gen_op_movl_A0_reg(int reg) |
422 | { | |
cc739bb0 | 423 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
424 | } |
425 | ||
426 | static inline void gen_op_addl_A0_im(int32_t val) | |
427 | { | |
428 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
14ce26e7 | 429 | #ifdef TARGET_X86_64 |
57fec1fe | 430 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); |
14ce26e7 | 431 | #endif |
57fec1fe | 432 | } |
2c0262af | 433 | |
14ce26e7 | 434 | #ifdef TARGET_X86_64 |
57fec1fe FB |
435 | static inline void gen_op_addq_A0_im(int64_t val) |
436 | { | |
437 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
438 | } | |
14ce26e7 | 439 | #endif |
57fec1fe FB |
440 | |
441 | static void gen_add_A0_im(DisasContext *s, int val) | |
442 | { | |
443 | #ifdef TARGET_X86_64 | |
444 | if (CODE64(s)) | |
445 | gen_op_addq_A0_im(val); | |
446 | else | |
447 | #endif | |
448 | gen_op_addl_A0_im(val); | |
449 | } | |
2c0262af | 450 | |
57fec1fe | 451 | static inline void gen_op_addl_T0_T1(void) |
2c0262af | 452 | { |
57fec1fe FB |
453 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
454 | } | |
455 | ||
456 | static inline void gen_op_jmp_T0(void) | |
457 | { | |
317ac620 | 458 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip)); |
57fec1fe FB |
459 | } |
460 | ||
6e0d8677 | 461 | static inline void gen_op_add_reg_im(int size, int reg, int32_t val) |
57fec1fe | 462 | { |
6e0d8677 | 463 | switch(size) { |
93ab25d7 | 464 | case OT_BYTE: |
cc739bb0 | 465 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
c832e3de | 466 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 | 467 | break; |
93ab25d7 | 468 | case OT_WORD: |
cc739bb0 LD |
469 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
470 | /* For x86_64, this sets the higher half of register to zero. | |
471 | For i386, this is equivalent to a nop. */ | |
472 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
473 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 FB |
474 | break; |
475 | #ifdef TARGET_X86_64 | |
93ab25d7 | 476 | case OT_LONG: |
cc739bb0 | 477 | tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val); |
6e0d8677 FB |
478 | break; |
479 | #endif | |
480 | } | |
57fec1fe FB |
481 | } |
482 | ||
6e0d8677 | 483 | static inline void gen_op_add_reg_T0(int size, int reg) |
57fec1fe | 484 | { |
6e0d8677 | 485 | switch(size) { |
93ab25d7 | 486 | case OT_BYTE: |
cc739bb0 | 487 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
c832e3de | 488 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 | 489 | break; |
93ab25d7 | 490 | case OT_WORD: |
cc739bb0 LD |
491 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
492 | /* For x86_64, this sets the higher half of register to zero. | |
493 | For i386, this is equivalent to a nop. */ | |
494 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
495 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 | 496 | break; |
14ce26e7 | 497 | #ifdef TARGET_X86_64 |
93ab25d7 | 498 | case OT_LONG: |
cc739bb0 | 499 | tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]); |
6e0d8677 | 500 | break; |
14ce26e7 | 501 | #endif |
6e0d8677 FB |
502 | } |
503 | } | |
57fec1fe | 504 | |
57fec1fe FB |
505 | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) |
506 | { | |
cc739bb0 LD |
507 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
508 | if (shift != 0) | |
57fec1fe FB |
509 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
510 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
cc739bb0 LD |
511 | /* For x86_64, this sets the higher half of register to zero. |
512 | For i386, this is equivalent to a nop. */ | |
513 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
57fec1fe | 514 | } |
2c0262af | 515 | |
57fec1fe FB |
516 | static inline void gen_op_movl_A0_seg(int reg) |
517 | { | |
317ac620 | 518 | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET); |
57fec1fe | 519 | } |
2c0262af | 520 | |
7162ab21 | 521 | static inline void gen_op_addl_A0_seg(DisasContext *s, int reg) |
57fec1fe | 522 | { |
317ac620 | 523 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 524 | #ifdef TARGET_X86_64 |
7162ab21 VC |
525 | if (CODE64(s)) { |
526 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
527 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
528 | } else { | |
529 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
530 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
531 | } | |
532 | #else | |
533 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe FB |
534 | #endif |
535 | } | |
2c0262af | 536 | |
14ce26e7 | 537 | #ifdef TARGET_X86_64 |
57fec1fe FB |
538 | static inline void gen_op_movq_A0_seg(int reg) |
539 | { | |
317ac620 | 540 | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 541 | } |
14ce26e7 | 542 | |
57fec1fe FB |
543 | static inline void gen_op_addq_A0_seg(int reg) |
544 | { | |
317ac620 | 545 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe FB |
546 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
547 | } | |
548 | ||
549 | static inline void gen_op_movq_A0_reg(int reg) | |
550 | { | |
cc739bb0 | 551 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
552 | } |
553 | ||
554 | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) | |
555 | { | |
cc739bb0 LD |
556 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
557 | if (shift != 0) | |
57fec1fe FB |
558 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
559 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
560 | } | |
14ce26e7 FB |
561 | #endif |
562 | ||
57fec1fe FB |
563 | static inline void gen_op_lds_T0_A0(int idx) |
564 | { | |
565 | int mem_index = (idx >> 2) - 1; | |
566 | switch(idx & 3) { | |
93ab25d7 | 567 | case OT_BYTE: |
57fec1fe FB |
568 | tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index); |
569 | break; | |
93ab25d7 | 570 | case OT_WORD: |
57fec1fe FB |
571 | tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index); |
572 | break; | |
573 | default: | |
93ab25d7 | 574 | case OT_LONG: |
57fec1fe FB |
575 | tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index); |
576 | break; | |
577 | } | |
578 | } | |
2c0262af | 579 | |
1e4840bf | 580 | static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) |
57fec1fe FB |
581 | { |
582 | int mem_index = (idx >> 2) - 1; | |
583 | switch(idx & 3) { | |
93ab25d7 | 584 | case OT_BYTE: |
1e4840bf | 585 | tcg_gen_qemu_ld8u(t0, a0, mem_index); |
57fec1fe | 586 | break; |
93ab25d7 | 587 | case OT_WORD: |
1e4840bf | 588 | tcg_gen_qemu_ld16u(t0, a0, mem_index); |
57fec1fe | 589 | break; |
93ab25d7 | 590 | case OT_LONG: |
1e4840bf | 591 | tcg_gen_qemu_ld32u(t0, a0, mem_index); |
57fec1fe FB |
592 | break; |
593 | default: | |
93ab25d7 | 594 | case OT_QUAD: |
a7812ae4 PB |
595 | /* Should never happen on 32-bit targets. */ |
596 | #ifdef TARGET_X86_64 | |
1e4840bf | 597 | tcg_gen_qemu_ld64(t0, a0, mem_index); |
a7812ae4 | 598 | #endif |
57fec1fe FB |
599 | break; |
600 | } | |
601 | } | |
2c0262af | 602 | |
1e4840bf FB |
603 | /* XXX: always use ldu or lds */ |
604 | static inline void gen_op_ld_T0_A0(int idx) | |
605 | { | |
606 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); | |
607 | } | |
608 | ||
57fec1fe FB |
609 | static inline void gen_op_ldu_T0_A0(int idx) |
610 | { | |
1e4840bf | 611 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 612 | } |
2c0262af | 613 | |
57fec1fe | 614 | static inline void gen_op_ld_T1_A0(int idx) |
1e4840bf FB |
615 | { |
616 | gen_op_ld_v(idx, cpu_T[1], cpu_A0); | |
617 | } | |
618 | ||
619 | static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) | |
57fec1fe FB |
620 | { |
621 | int mem_index = (idx >> 2) - 1; | |
622 | switch(idx & 3) { | |
93ab25d7 | 623 | case OT_BYTE: |
1e4840bf | 624 | tcg_gen_qemu_st8(t0, a0, mem_index); |
57fec1fe | 625 | break; |
93ab25d7 | 626 | case OT_WORD: |
1e4840bf | 627 | tcg_gen_qemu_st16(t0, a0, mem_index); |
57fec1fe | 628 | break; |
93ab25d7 | 629 | case OT_LONG: |
1e4840bf | 630 | tcg_gen_qemu_st32(t0, a0, mem_index); |
57fec1fe FB |
631 | break; |
632 | default: | |
93ab25d7 | 633 | case OT_QUAD: |
a7812ae4 PB |
634 | /* Should never happen on 32-bit targets. */ |
635 | #ifdef TARGET_X86_64 | |
1e4840bf | 636 | tcg_gen_qemu_st64(t0, a0, mem_index); |
a7812ae4 | 637 | #endif |
57fec1fe FB |
638 | break; |
639 | } | |
640 | } | |
4f31916f | 641 | |
57fec1fe FB |
642 | static inline void gen_op_st_T0_A0(int idx) |
643 | { | |
1e4840bf | 644 | gen_op_st_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 645 | } |
4f31916f | 646 | |
57fec1fe FB |
647 | static inline void gen_op_st_T1_A0(int idx) |
648 | { | |
1e4840bf | 649 | gen_op_st_v(idx, cpu_T[1], cpu_A0); |
57fec1fe | 650 | } |
4f31916f | 651 | |
14ce26e7 FB |
652 | static inline void gen_jmp_im(target_ulong pc) |
653 | { | |
57fec1fe | 654 | tcg_gen_movi_tl(cpu_tmp0, pc); |
317ac620 | 655 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip)); |
14ce26e7 FB |
656 | } |
657 | ||
2c0262af FB |
658 | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
659 | { | |
660 | int override; | |
661 | ||
662 | override = s->override; | |
14ce26e7 FB |
663 | #ifdef TARGET_X86_64 |
664 | if (s->aflag == 2) { | |
665 | if (override >= 0) { | |
57fec1fe FB |
666 | gen_op_movq_A0_seg(override); |
667 | gen_op_addq_A0_reg_sN(0, R_ESI); | |
14ce26e7 | 668 | } else { |
57fec1fe | 669 | gen_op_movq_A0_reg(R_ESI); |
14ce26e7 FB |
670 | } |
671 | } else | |
672 | #endif | |
2c0262af FB |
673 | if (s->aflag) { |
674 | /* 32 bit address */ | |
675 | if (s->addseg && override < 0) | |
676 | override = R_DS; | |
677 | if (override >= 0) { | |
57fec1fe FB |
678 | gen_op_movl_A0_seg(override); |
679 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af | 680 | } else { |
57fec1fe | 681 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
682 | } |
683 | } else { | |
684 | /* 16 address, always override */ | |
685 | if (override < 0) | |
686 | override = R_DS; | |
57fec1fe | 687 | gen_op_movl_A0_reg(R_ESI); |
2c0262af | 688 | gen_op_andl_A0_ffff(); |
7162ab21 | 689 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
690 | } |
691 | } | |
692 | ||
693 | static inline void gen_string_movl_A0_EDI(DisasContext *s) | |
694 | { | |
14ce26e7 FB |
695 | #ifdef TARGET_X86_64 |
696 | if (s->aflag == 2) { | |
57fec1fe | 697 | gen_op_movq_A0_reg(R_EDI); |
14ce26e7 FB |
698 | } else |
699 | #endif | |
2c0262af FB |
700 | if (s->aflag) { |
701 | if (s->addseg) { | |
57fec1fe FB |
702 | gen_op_movl_A0_seg(R_ES); |
703 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af | 704 | } else { |
57fec1fe | 705 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
706 | } |
707 | } else { | |
57fec1fe | 708 | gen_op_movl_A0_reg(R_EDI); |
2c0262af | 709 | gen_op_andl_A0_ffff(); |
7162ab21 | 710 | gen_op_addl_A0_seg(s, R_ES); |
2c0262af FB |
711 | } |
712 | } | |
713 | ||
6e0d8677 FB |
714 | static inline void gen_op_movl_T0_Dshift(int ot) |
715 | { | |
317ac620 | 716 | tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df)); |
6e0d8677 | 717 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); |
2c0262af FB |
718 | }; |
719 | ||
d824df34 | 720 | static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign) |
6e0d8677 | 721 | { |
d824df34 | 722 | switch (size) { |
6e0d8677 | 723 | case OT_BYTE: |
d824df34 PB |
724 | if (sign) { |
725 | tcg_gen_ext8s_tl(dst, src); | |
726 | } else { | |
727 | tcg_gen_ext8u_tl(dst, src); | |
728 | } | |
729 | return dst; | |
6e0d8677 | 730 | case OT_WORD: |
d824df34 PB |
731 | if (sign) { |
732 | tcg_gen_ext16s_tl(dst, src); | |
733 | } else { | |
734 | tcg_gen_ext16u_tl(dst, src); | |
735 | } | |
736 | return dst; | |
737 | #ifdef TARGET_X86_64 | |
6e0d8677 | 738 | case OT_LONG: |
d824df34 PB |
739 | if (sign) { |
740 | tcg_gen_ext32s_tl(dst, src); | |
741 | } else { | |
742 | tcg_gen_ext32u_tl(dst, src); | |
743 | } | |
744 | return dst; | |
745 | #endif | |
6e0d8677 | 746 | default: |
d824df34 | 747 | return src; |
6e0d8677 FB |
748 | } |
749 | } | |
3b46e624 | 750 | |
d824df34 PB |
751 | static void gen_extu(int ot, TCGv reg) |
752 | { | |
753 | gen_ext_tl(reg, reg, ot, false); | |
754 | } | |
755 | ||
6e0d8677 FB |
756 | static void gen_exts(int ot, TCGv reg) |
757 | { | |
d824df34 | 758 | gen_ext_tl(reg, reg, ot, true); |
6e0d8677 | 759 | } |
2c0262af | 760 | |
6e0d8677 FB |
761 | static inline void gen_op_jnz_ecx(int size, int label1) |
762 | { | |
cc739bb0 | 763 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 764 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 765 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); |
6e0d8677 FB |
766 | } |
767 | ||
768 | static inline void gen_op_jz_ecx(int size, int label1) | |
769 | { | |
cc739bb0 | 770 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 771 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 772 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
6e0d8677 | 773 | } |
2c0262af | 774 | |
a7812ae4 PB |
775 | static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n) |
776 | { | |
777 | switch (ot) { | |
93ab25d7 PB |
778 | case OT_BYTE: |
779 | gen_helper_inb(v, n); | |
780 | break; | |
781 | case OT_WORD: | |
782 | gen_helper_inw(v, n); | |
783 | break; | |
784 | case OT_LONG: | |
785 | gen_helper_inl(v, n); | |
786 | break; | |
a7812ae4 | 787 | } |
a7812ae4 | 788 | } |
2c0262af | 789 | |
a7812ae4 PB |
790 | static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n) |
791 | { | |
792 | switch (ot) { | |
93ab25d7 PB |
793 | case OT_BYTE: |
794 | gen_helper_outb(v, n); | |
795 | break; | |
796 | case OT_WORD: | |
797 | gen_helper_outw(v, n); | |
798 | break; | |
799 | case OT_LONG: | |
800 | gen_helper_outl(v, n); | |
801 | break; | |
a7812ae4 | 802 | } |
a7812ae4 | 803 | } |
f115e911 | 804 | |
b8b6a50b FB |
805 | static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, |
806 | uint32_t svm_flags) | |
f115e911 | 807 | { |
b8b6a50b FB |
808 | int state_saved; |
809 | target_ulong next_eip; | |
810 | ||
811 | state_saved = 0; | |
f115e911 | 812 | if (s->pe && (s->cpl > s->iopl || s->vm86)) { |
773cdfcc | 813 | gen_update_cc_op(s); |
14ce26e7 | 814 | gen_jmp_im(cur_eip); |
b8b6a50b | 815 | state_saved = 1; |
b6abf97d | 816 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 817 | switch (ot) { |
93ab25d7 | 818 | case OT_BYTE: |
4a7443be BS |
819 | gen_helper_check_iob(cpu_env, cpu_tmp2_i32); |
820 | break; | |
93ab25d7 | 821 | case OT_WORD: |
4a7443be BS |
822 | gen_helper_check_iow(cpu_env, cpu_tmp2_i32); |
823 | break; | |
93ab25d7 | 824 | case OT_LONG: |
4a7443be BS |
825 | gen_helper_check_iol(cpu_env, cpu_tmp2_i32); |
826 | break; | |
a7812ae4 | 827 | } |
b8b6a50b | 828 | } |
872929aa | 829 | if(s->flags & HF_SVMI_MASK) { |
b8b6a50b | 830 | if (!state_saved) { |
773cdfcc | 831 | gen_update_cc_op(s); |
b8b6a50b | 832 | gen_jmp_im(cur_eip); |
b8b6a50b FB |
833 | } |
834 | svm_flags |= (1 << (4 + ot)); | |
835 | next_eip = s->pc - s->cs_base; | |
b6abf97d | 836 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
052e80d5 BS |
837 | gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32, |
838 | tcg_const_i32(svm_flags), | |
a7812ae4 | 839 | tcg_const_i32(next_eip - cur_eip)); |
f115e911 FB |
840 | } |
841 | } | |
842 | ||
2c0262af FB |
843 | static inline void gen_movs(DisasContext *s, int ot) |
844 | { | |
845 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 846 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 847 | gen_string_movl_A0_EDI(s); |
57fec1fe | 848 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
849 | gen_op_movl_T0_Dshift(ot); |
850 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
851 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
852 | } |
853 | ||
b6abf97d FB |
854 | static void gen_op_update1_cc(void) |
855 | { | |
b6abf97d FB |
856 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
857 | } | |
858 | ||
859 | static void gen_op_update2_cc(void) | |
860 | { | |
861 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
862 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
863 | } | |
864 | ||
b6abf97d FB |
865 | static inline void gen_op_testl_T0_T1_cc(void) |
866 | { | |
b6abf97d FB |
867 | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
868 | } | |
869 | ||
870 | static void gen_op_update_neg_cc(void) | |
871 | { | |
872 | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]); | |
873 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
874 | } | |
875 | ||
d229edce RH |
876 | /* compute all eflags to cc_src */ |
877 | static void gen_compute_eflags(DisasContext *s) | |
8e1c85e3 | 878 | { |
d229edce RH |
879 | if (s->cc_op == CC_OP_EFLAGS) { |
880 | return; | |
881 | } | |
773cdfcc | 882 | gen_update_cc_op(s); |
f0967a1a | 883 | gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_env, cpu_cc_op); |
d229edce RH |
884 | set_cc_op(s, CC_OP_EFLAGS); |
885 | tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32); | |
8e1c85e3 FB |
886 | } |
887 | ||
bec93d72 RH |
888 | typedef struct CCPrepare { |
889 | TCGCond cond; | |
890 | TCGv reg; | |
891 | TCGv reg2; | |
892 | target_ulong imm; | |
893 | target_ulong mask; | |
894 | bool use_reg2; | |
895 | bool no_setcond; | |
896 | } CCPrepare; | |
897 | ||
06847f1f | 898 | /* compute eflags.C to reg */ |
bec93d72 | 899 | static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) |
06847f1f RH |
900 | { |
901 | TCGv t0, t1; | |
bec93d72 | 902 | int size, shift; |
06847f1f RH |
903 | |
904 | switch (s->cc_op) { | |
905 | case CC_OP_SUBB ... CC_OP_SUBQ: | |
906 | /* (DATA_TYPE)(CC_DST + CC_SRC) < (DATA_TYPE)CC_SRC */ | |
907 | size = s->cc_op - CC_OP_SUBB; | |
908 | t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
909 | /* If no temporary was used, be careful not to alias t1 and t0. */ | |
910 | t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg; | |
911 | tcg_gen_add_tl(t0, cpu_cc_dst, cpu_cc_src); | |
912 | gen_extu(size, t0); | |
913 | goto add_sub; | |
914 | ||
915 | case CC_OP_ADDB ... CC_OP_ADDQ: | |
916 | /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ | |
917 | size = s->cc_op - CC_OP_ADDB; | |
918 | t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
919 | t0 = gen_ext_tl(reg, cpu_cc_dst, size, false); | |
920 | add_sub: | |
bec93d72 RH |
921 | return (CCPrepare) { .cond = TCG_COND_LTU, .reg = t0, |
922 | .reg2 = t1, .mask = -1, .use_reg2 = true }; | |
06847f1f RH |
923 | |
924 | case CC_OP_SBBB ... CC_OP_SBBQ: | |
925 | /* (DATA_TYPE)(CC_DST + CC_SRC + 1) <= (DATA_TYPE)CC_SRC */ | |
926 | size = s->cc_op - CC_OP_SBBB; | |
927 | t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
928 | if (TCGV_EQUAL(t1, reg) && TCGV_EQUAL(reg, cpu_cc_src)) { | |
929 | tcg_gen_mov_tl(cpu_tmp0, cpu_cc_src); | |
930 | t1 = cpu_tmp0; | |
931 | } | |
932 | ||
933 | tcg_gen_add_tl(reg, cpu_cc_dst, cpu_cc_src); | |
934 | tcg_gen_addi_tl(reg, reg, 1); | |
935 | gen_extu(size, reg); | |
936 | t0 = reg; | |
937 | goto adc_sbb; | |
938 | ||
939 | case CC_OP_ADCB ... CC_OP_ADCQ: | |
940 | /* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */ | |
941 | size = s->cc_op - CC_OP_ADCB; | |
942 | t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
943 | t0 = gen_ext_tl(reg, cpu_cc_dst, size, false); | |
944 | adc_sbb: | |
bec93d72 RH |
945 | return (CCPrepare) { .cond = TCG_COND_LEU, .reg = t0, |
946 | .reg2 = t1, .mask = -1, .use_reg2 = true }; | |
06847f1f RH |
947 | |
948 | case CC_OP_LOGICB ... CC_OP_LOGICQ: | |
bec93d72 | 949 | return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; |
06847f1f RH |
950 | |
951 | case CC_OP_INCB ... CC_OP_INCQ: | |
952 | case CC_OP_DECB ... CC_OP_DECQ: | |
bec93d72 RH |
953 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
954 | .mask = -1, .no_setcond = true }; | |
06847f1f RH |
955 | |
956 | case CC_OP_SHLB ... CC_OP_SHLQ: | |
957 | /* (CC_SRC >> (DATA_BITS - 1)) & 1 */ | |
958 | size = s->cc_op - CC_OP_SHLB; | |
bec93d72 RH |
959 | shift = (8 << size) - 1; |
960 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, | |
961 | .mask = (target_ulong)1 << shift }; | |
06847f1f RH |
962 | |
963 | case CC_OP_MULB ... CC_OP_MULQ: | |
bec93d72 RH |
964 | return (CCPrepare) { .cond = TCG_COND_NE, |
965 | .reg = cpu_cc_src, .mask = -1 }; | |
06847f1f RH |
966 | |
967 | case CC_OP_EFLAGS: | |
968 | case CC_OP_SARB ... CC_OP_SARQ: | |
969 | /* CC_SRC & 1 */ | |
bec93d72 RH |
970 | return (CCPrepare) { .cond = TCG_COND_NE, |
971 | .reg = cpu_cc_src, .mask = CC_C }; | |
06847f1f RH |
972 | |
973 | default: | |
974 | /* The need to compute only C from CC_OP_DYNAMIC is important | |
975 | in efficiently implementing e.g. INC at the start of a TB. */ | |
976 | gen_update_cc_op(s); | |
977 | gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op); | |
978 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); | |
bec93d72 RH |
979 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, |
980 | .mask = -1, .no_setcond = true }; | |
06847f1f RH |
981 | } |
982 | } | |
983 | ||
1608ecca | 984 | /* compute eflags.P to reg */ |
bec93d72 | 985 | static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg) |
1608ecca | 986 | { |
d229edce | 987 | gen_compute_eflags(s); |
bec93d72 RH |
988 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
989 | .mask = CC_P }; | |
1608ecca PB |
990 | } |
991 | ||
992 | /* compute eflags.S to reg */ | |
bec93d72 | 993 | static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg) |
1608ecca | 994 | { |
086c4077 RH |
995 | switch (s->cc_op) { |
996 | case CC_OP_DYNAMIC: | |
997 | gen_compute_eflags(s); | |
998 | /* FALLTHRU */ | |
999 | case CC_OP_EFLAGS: | |
bec93d72 RH |
1000 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
1001 | .mask = CC_S }; | |
086c4077 RH |
1002 | default: |
1003 | { | |
1004 | int size = (s->cc_op - CC_OP_ADDB) & 3; | |
1005 | TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true); | |
bec93d72 | 1006 | return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 }; |
086c4077 | 1007 | } |
086c4077 | 1008 | } |
1608ecca PB |
1009 | } |
1010 | ||
1011 | /* compute eflags.O to reg */ | |
bec93d72 | 1012 | static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg) |
1608ecca | 1013 | { |
d229edce | 1014 | gen_compute_eflags(s); |
bec93d72 RH |
1015 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
1016 | .mask = CC_O }; | |
1608ecca PB |
1017 | } |
1018 | ||
1019 | /* compute eflags.Z to reg */ | |
bec93d72 | 1020 | static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) |
1608ecca | 1021 | { |
086c4077 RH |
1022 | switch (s->cc_op) { |
1023 | case CC_OP_DYNAMIC: | |
1024 | gen_compute_eflags(s); | |
1025 | /* FALLTHRU */ | |
1026 | case CC_OP_EFLAGS: | |
bec93d72 RH |
1027 | return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, |
1028 | .mask = CC_Z }; | |
086c4077 RH |
1029 | default: |
1030 | { | |
1031 | int size = (s->cc_op - CC_OP_ADDB) & 3; | |
1032 | TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false); | |
bec93d72 | 1033 | return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 }; |
086c4077 | 1034 | } |
bec93d72 RH |
1035 | } |
1036 | } | |
1037 | ||
c365395e PB |
1038 | /* perform a conditional store into register 'reg' according to jump opcode |
1039 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
276e6b5f | 1040 | static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) |
8e1c85e3 | 1041 | { |
c365395e | 1042 | int inv, jcc_op, size, cond; |
276e6b5f | 1043 | CCPrepare cc; |
c365395e PB |
1044 | TCGv t0; |
1045 | ||
1046 | inv = b & 1; | |
8e1c85e3 | 1047 | jcc_op = (b >> 1) & 7; |
c365395e PB |
1048 | |
1049 | switch (s->cc_op) { | |
69d1aa31 RH |
1050 | case CC_OP_SUBB ... CC_OP_SUBQ: |
1051 | /* We optimize relational operators for the cmp/jcc case. */ | |
c365395e PB |
1052 | size = s->cc_op - CC_OP_SUBB; |
1053 | switch (jcc_op) { | |
1054 | case JCC_BE: | |
c365395e PB |
1055 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); |
1056 | gen_extu(size, cpu_tmp4); | |
1057 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
276e6b5f RH |
1058 | cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4, |
1059 | .reg2 = t0, .mask = -1, .use_reg2 = true }; | |
c365395e | 1060 | break; |
8e1c85e3 | 1061 | |
c365395e | 1062 | case JCC_L: |
276e6b5f | 1063 | cond = TCG_COND_LT; |
c365395e PB |
1064 | goto fast_jcc_l; |
1065 | case JCC_LE: | |
276e6b5f | 1066 | cond = TCG_COND_LE; |
c365395e PB |
1067 | fast_jcc_l: |
1068 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
1069 | gen_exts(size, cpu_tmp4); | |
1070 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true); | |
276e6b5f RH |
1071 | cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4, |
1072 | .reg2 = t0, .mask = -1, .use_reg2 = true }; | |
c365395e | 1073 | break; |
8e1c85e3 | 1074 | |
c365395e | 1075 | default: |
8e1c85e3 | 1076 | goto slow_jcc; |
c365395e | 1077 | } |
8e1c85e3 | 1078 | break; |
c365395e | 1079 | |
8e1c85e3 FB |
1080 | default: |
1081 | slow_jcc: | |
69d1aa31 RH |
1082 | /* This actually generates good code for JC, JZ and JS. */ |
1083 | switch (jcc_op) { | |
1084 | case JCC_O: | |
1085 | cc = gen_prepare_eflags_o(s, reg); | |
1086 | break; | |
1087 | case JCC_B: | |
1088 | cc = gen_prepare_eflags_c(s, reg); | |
1089 | break; | |
1090 | case JCC_Z: | |
1091 | cc = gen_prepare_eflags_z(s, reg); | |
1092 | break; | |
1093 | case JCC_BE: | |
1094 | gen_compute_eflags(s); | |
1095 | cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, | |
1096 | .mask = CC_Z | CC_C }; | |
1097 | break; | |
1098 | case JCC_S: | |
1099 | cc = gen_prepare_eflags_s(s, reg); | |
1100 | break; | |
1101 | case JCC_P: | |
1102 | cc = gen_prepare_eflags_p(s, reg); | |
1103 | break; | |
1104 | case JCC_L: | |
1105 | gen_compute_eflags(s); | |
1106 | if (TCGV_EQUAL(reg, cpu_cc_src)) { | |
1107 | reg = cpu_tmp0; | |
1108 | } | |
1109 | tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ | |
1110 | tcg_gen_xor_tl(reg, reg, cpu_cc_src); | |
1111 | cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, | |
1112 | .mask = CC_S }; | |
1113 | break; | |
1114 | default: | |
1115 | case JCC_LE: | |
1116 | gen_compute_eflags(s); | |
1117 | if (TCGV_EQUAL(reg, cpu_cc_src)) { | |
1118 | reg = cpu_tmp0; | |
1119 | } | |
1120 | tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ | |
1121 | tcg_gen_xor_tl(reg, reg, cpu_cc_src); | |
1122 | cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, | |
1123 | .mask = CC_S | CC_Z }; | |
1124 | break; | |
1125 | } | |
c365395e | 1126 | break; |
8e1c85e3 | 1127 | } |
276e6b5f RH |
1128 | |
1129 | if (inv) { | |
1130 | cc.cond = tcg_invert_cond(cc.cond); | |
1131 | } | |
1132 | return cc; | |
8e1c85e3 FB |
1133 | } |
1134 | ||
cc8b6f5b PB |
1135 | static void gen_setcc1(DisasContext *s, int b, TCGv reg) |
1136 | { | |
1137 | CCPrepare cc = gen_prepare_cc(s, b, reg); | |
1138 | ||
1139 | if (cc.no_setcond) { | |
1140 | if (cc.cond == TCG_COND_EQ) { | |
1141 | tcg_gen_xori_tl(reg, cc.reg, 1); | |
1142 | } else { | |
1143 | tcg_gen_mov_tl(reg, cc.reg); | |
1144 | } | |
1145 | return; | |
1146 | } | |
1147 | ||
1148 | if (cc.cond == TCG_COND_NE && !cc.use_reg2 && cc.imm == 0 && | |
1149 | cc.mask != 0 && (cc.mask & (cc.mask - 1)) == 0) { | |
1150 | tcg_gen_shri_tl(reg, cc.reg, ctztl(cc.mask)); | |
1151 | tcg_gen_andi_tl(reg, reg, 1); | |
1152 | return; | |
1153 | } | |
1154 | if (cc.mask != -1) { | |
1155 | tcg_gen_andi_tl(reg, cc.reg, cc.mask); | |
1156 | cc.reg = reg; | |
1157 | } | |
1158 | if (cc.use_reg2) { | |
1159 | tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2); | |
1160 | } else { | |
1161 | tcg_gen_setcondi_tl(cc.cond, reg, cc.reg, cc.imm); | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg) | |
1166 | { | |
1167 | gen_setcc1(s, JCC_B << 1, reg); | |
1168 | } | |
276e6b5f | 1169 | |
8e1c85e3 FB |
1170 | /* generate a conditional jump to label 'l1' according to jump opcode |
1171 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
dc259201 RH |
1172 | static inline void gen_jcc1_noeob(DisasContext *s, int b, int l1) |
1173 | { | |
1174 | CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]); | |
1175 | ||
1176 | if (cc.mask != -1) { | |
1177 | tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask); | |
1178 | cc.reg = cpu_T[0]; | |
1179 | } | |
1180 | if (cc.use_reg2) { | |
1181 | tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); | |
1182 | } else { | |
1183 | tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1); | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | /* Generate a conditional jump to label 'l1' according to jump opcode | |
1188 | value 'b'. In the fast case, T0 is guaranted not to be used. | |
1189 | A translation block must end soon. */ | |
b27fc131 | 1190 | static inline void gen_jcc1(DisasContext *s, int b, int l1) |
8e1c85e3 | 1191 | { |
943131ca | 1192 | CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]); |
8e1c85e3 | 1193 | |
dc259201 | 1194 | gen_update_cc_op(s); |
943131ca PB |
1195 | if (cc.mask != -1) { |
1196 | tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask); | |
1197 | cc.reg = cpu_T[0]; | |
1198 | } | |
dc259201 | 1199 | set_cc_op(s, CC_OP_DYNAMIC); |
943131ca PB |
1200 | if (cc.use_reg2) { |
1201 | tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); | |
1202 | } else { | |
1203 | tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1); | |
8e1c85e3 FB |
1204 | } |
1205 | } | |
1206 | ||
14ce26e7 FB |
1207 | /* XXX: does not work with gdbstub "ice" single step - not a |
1208 | serious problem */ | |
1209 | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) | |
2c0262af | 1210 | { |
14ce26e7 FB |
1211 | int l1, l2; |
1212 | ||
1213 | l1 = gen_new_label(); | |
1214 | l2 = gen_new_label(); | |
6e0d8677 | 1215 | gen_op_jnz_ecx(s->aflag, l1); |
14ce26e7 FB |
1216 | gen_set_label(l2); |
1217 | gen_jmp_tb(s, next_eip, 1); | |
1218 | gen_set_label(l1); | |
1219 | return l2; | |
2c0262af FB |
1220 | } |
1221 | ||
1222 | static inline void gen_stos(DisasContext *s, int ot) | |
1223 | { | |
57fec1fe | 1224 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1225 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1226 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1227 | gen_op_movl_T0_Dshift(ot); |
1228 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1229 | } |
1230 | ||
1231 | static inline void gen_lods(DisasContext *s, int ot) | |
1232 | { | |
1233 | gen_string_movl_A0_ESI(s); | |
57fec1fe FB |
1234 | gen_op_ld_T0_A0(ot + s->mem_index); |
1235 | gen_op_mov_reg_T0(ot, R_EAX); | |
6e0d8677 FB |
1236 | gen_op_movl_T0_Dshift(ot); |
1237 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2c0262af FB |
1238 | } |
1239 | ||
1240 | static inline void gen_scas(DisasContext *s, int ot) | |
1241 | { | |
2c0262af | 1242 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1243 | gen_op_ld_T1_A0(ot + s->mem_index); |
63633fe6 | 1244 | gen_op(s, OP_CMPL, ot, R_EAX); |
6e0d8677 FB |
1245 | gen_op_movl_T0_Dshift(ot); |
1246 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1247 | } |
1248 | ||
1249 | static inline void gen_cmps(DisasContext *s, int ot) | |
1250 | { | |
2c0262af | 1251 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1252 | gen_op_ld_T1_A0(ot + s->mem_index); |
63633fe6 RH |
1253 | gen_string_movl_A0_ESI(s); |
1254 | gen_op(s, OP_CMPL, ot, OR_TMP0); | |
6e0d8677 FB |
1255 | gen_op_movl_T0_Dshift(ot); |
1256 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
1257 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1258 | } |
1259 | ||
1260 | static inline void gen_ins(DisasContext *s, int ot) | |
1261 | { | |
2e70f6ef PB |
1262 | if (use_icount) |
1263 | gen_io_start(); | |
2c0262af | 1264 | gen_string_movl_A0_EDI(s); |
6e0d8677 FB |
1265 | /* Note: we must do this dummy write first to be restartable in |
1266 | case of page fault. */ | |
9772c73b | 1267 | gen_op_movl_T0_0(); |
57fec1fe | 1268 | gen_op_st_T0_A0(ot + s->mem_index); |
b8b6a50b | 1269 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); |
b6abf97d FB |
1270 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1271 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
a7812ae4 | 1272 | gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 1273 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1274 | gen_op_movl_T0_Dshift(ot); |
1275 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2e70f6ef PB |
1276 | if (use_icount) |
1277 | gen_io_end(); | |
2c0262af FB |
1278 | } |
1279 | ||
1280 | static inline void gen_outs(DisasContext *s, int ot) | |
1281 | { | |
2e70f6ef PB |
1282 | if (use_icount) |
1283 | gen_io_start(); | |
2c0262af | 1284 | gen_string_movl_A0_ESI(s); |
57fec1fe | 1285 | gen_op_ld_T0_A0(ot + s->mem_index); |
b8b6a50b FB |
1286 | |
1287 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); | |
b6abf97d FB |
1288 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1289 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
1290 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); | |
a7812ae4 | 1291 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
b8b6a50b | 1292 | |
6e0d8677 FB |
1293 | gen_op_movl_T0_Dshift(ot); |
1294 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2e70f6ef PB |
1295 | if (use_icount) |
1296 | gen_io_end(); | |
2c0262af FB |
1297 | } |
1298 | ||
1299 | /* same method as Valgrind : we generate jumps to current or next | |
1300 | instruction */ | |
1301 | #define GEN_REPZ(op) \ | |
1302 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 | 1303 | target_ulong cur_eip, target_ulong next_eip) \ |
2c0262af | 1304 | { \ |
14ce26e7 | 1305 | int l2;\ |
2c0262af | 1306 | gen_update_cc_op(s); \ |
14ce26e7 | 1307 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1308 | gen_ ## op(s, ot); \ |
6e0d8677 | 1309 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af FB |
1310 | /* a loop would cause two single step exceptions if ECX = 1 \ |
1311 | before rep string_insn */ \ | |
1312 | if (!s->jmp_opt) \ | |
6e0d8677 | 1313 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1314 | gen_jmp(s, cur_eip); \ |
1315 | } | |
1316 | ||
1317 | #define GEN_REPZ2(op) \ | |
1318 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 FB |
1319 | target_ulong cur_eip, \ |
1320 | target_ulong next_eip, \ | |
2c0262af FB |
1321 | int nz) \ |
1322 | { \ | |
14ce26e7 | 1323 | int l2;\ |
2c0262af | 1324 | gen_update_cc_op(s); \ |
14ce26e7 | 1325 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1326 | gen_ ## op(s, ot); \ |
6e0d8677 | 1327 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
773cdfcc | 1328 | gen_update_cc_op(s); \ |
b27fc131 | 1329 | gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \ |
2c0262af | 1330 | if (!s->jmp_opt) \ |
6e0d8677 | 1331 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1332 | gen_jmp(s, cur_eip); \ |
1333 | } | |
1334 | ||
1335 | GEN_REPZ(movs) | |
1336 | GEN_REPZ(stos) | |
1337 | GEN_REPZ(lods) | |
1338 | GEN_REPZ(ins) | |
1339 | GEN_REPZ(outs) | |
1340 | GEN_REPZ2(scas) | |
1341 | GEN_REPZ2(cmps) | |
1342 | ||
a7812ae4 PB |
1343 | static void gen_helper_fp_arith_ST0_FT0(int op) |
1344 | { | |
1345 | switch (op) { | |
d3eb5eae BS |
1346 | case 0: |
1347 | gen_helper_fadd_ST0_FT0(cpu_env); | |
1348 | break; | |
1349 | case 1: | |
1350 | gen_helper_fmul_ST0_FT0(cpu_env); | |
1351 | break; | |
1352 | case 2: | |
1353 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1354 | break; | |
1355 | case 3: | |
1356 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1357 | break; | |
1358 | case 4: | |
1359 | gen_helper_fsub_ST0_FT0(cpu_env); | |
1360 | break; | |
1361 | case 5: | |
1362 | gen_helper_fsubr_ST0_FT0(cpu_env); | |
1363 | break; | |
1364 | case 6: | |
1365 | gen_helper_fdiv_ST0_FT0(cpu_env); | |
1366 | break; | |
1367 | case 7: | |
1368 | gen_helper_fdivr_ST0_FT0(cpu_env); | |
1369 | break; | |
a7812ae4 PB |
1370 | } |
1371 | } | |
2c0262af FB |
1372 | |
1373 | /* NOTE the exception in "r" op ordering */ | |
a7812ae4 PB |
1374 | static void gen_helper_fp_arith_STN_ST0(int op, int opreg) |
1375 | { | |
1376 | TCGv_i32 tmp = tcg_const_i32(opreg); | |
1377 | switch (op) { | |
d3eb5eae BS |
1378 | case 0: |
1379 | gen_helper_fadd_STN_ST0(cpu_env, tmp); | |
1380 | break; | |
1381 | case 1: | |
1382 | gen_helper_fmul_STN_ST0(cpu_env, tmp); | |
1383 | break; | |
1384 | case 4: | |
1385 | gen_helper_fsubr_STN_ST0(cpu_env, tmp); | |
1386 | break; | |
1387 | case 5: | |
1388 | gen_helper_fsub_STN_ST0(cpu_env, tmp); | |
1389 | break; | |
1390 | case 6: | |
1391 | gen_helper_fdivr_STN_ST0(cpu_env, tmp); | |
1392 | break; | |
1393 | case 7: | |
1394 | gen_helper_fdiv_STN_ST0(cpu_env, tmp); | |
1395 | break; | |
a7812ae4 PB |
1396 | } |
1397 | } | |
2c0262af FB |
1398 | |
1399 | /* if d == OR_TMP0, it means memory operand (address in A0) */ | |
1400 | static void gen_op(DisasContext *s1, int op, int ot, int d) | |
1401 | { | |
2c0262af | 1402 | if (d != OR_TMP0) { |
57fec1fe | 1403 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1404 | } else { |
57fec1fe | 1405 | gen_op_ld_T0_A0(ot + s1->mem_index); |
2c0262af FB |
1406 | } |
1407 | switch(op) { | |
1408 | case OP_ADCL: | |
cc8b6f5b | 1409 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1410 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1411 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1412 | if (d != OR_TMP0) | |
1413 | gen_op_mov_reg_T0(ot, d); | |
1414 | else | |
1415 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1416 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1417 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1418 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1419 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1420 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot); | |
3ca51d07 | 1421 | set_cc_op(s1, CC_OP_DYNAMIC); |
cad3a37d | 1422 | break; |
2c0262af | 1423 | case OP_SBBL: |
cc8b6f5b | 1424 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1425 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1426 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1427 | if (d != OR_TMP0) | |
57fec1fe | 1428 | gen_op_mov_reg_T0(ot, d); |
cad3a37d FB |
1429 | else |
1430 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1431 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1432 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1433 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1434 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1435 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot); | |
3ca51d07 | 1436 | set_cc_op(s1, CC_OP_DYNAMIC); |
cad3a37d | 1437 | break; |
2c0262af FB |
1438 | case OP_ADDL: |
1439 | gen_op_addl_T0_T1(); | |
cad3a37d FB |
1440 | if (d != OR_TMP0) |
1441 | gen_op_mov_reg_T0(ot, d); | |
1442 | else | |
1443 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1444 | gen_op_update2_cc(); | |
3ca51d07 | 1445 | set_cc_op(s1, CC_OP_ADDB + ot); |
2c0262af FB |
1446 | break; |
1447 | case OP_SUBL: | |
57fec1fe | 1448 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1449 | if (d != OR_TMP0) |
1450 | gen_op_mov_reg_T0(ot, d); | |
1451 | else | |
1452 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1453 | gen_op_update2_cc(); | |
3ca51d07 | 1454 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1455 | break; |
1456 | default: | |
1457 | case OP_ANDL: | |
57fec1fe | 1458 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1459 | if (d != OR_TMP0) |
1460 | gen_op_mov_reg_T0(ot, d); | |
1461 | else | |
1462 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1463 | gen_op_update1_cc(); | |
3ca51d07 | 1464 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1465 | break; |
2c0262af | 1466 | case OP_ORL: |
57fec1fe | 1467 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1468 | if (d != OR_TMP0) |
1469 | gen_op_mov_reg_T0(ot, d); | |
1470 | else | |
1471 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1472 | gen_op_update1_cc(); | |
3ca51d07 | 1473 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1474 | break; |
2c0262af | 1475 | case OP_XORL: |
57fec1fe | 1476 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1477 | if (d != OR_TMP0) |
1478 | gen_op_mov_reg_T0(ot, d); | |
1479 | else | |
1480 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1481 | gen_op_update1_cc(); | |
3ca51d07 | 1482 | set_cc_op(s1, CC_OP_LOGICB + ot); |
2c0262af FB |
1483 | break; |
1484 | case OP_CMPL: | |
63633fe6 RH |
1485 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); |
1486 | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
3ca51d07 | 1487 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1488 | break; |
1489 | } | |
b6abf97d FB |
1490 | } |
1491 | ||
2c0262af FB |
1492 | /* if d == OR_TMP0, it means memory operand (address in A0) */ |
1493 | static void gen_inc(DisasContext *s1, int ot, int d, int c) | |
1494 | { | |
1495 | if (d != OR_TMP0) | |
57fec1fe | 1496 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1497 | else |
57fec1fe | 1498 | gen_op_ld_T0_A0(ot + s1->mem_index); |
cc8b6f5b | 1499 | gen_compute_eflags_c(s1, cpu_cc_src); |
2c0262af | 1500 | if (c > 0) { |
b6abf97d | 1501 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
3ca51d07 | 1502 | set_cc_op(s1, CC_OP_INCB + ot); |
2c0262af | 1503 | } else { |
b6abf97d | 1504 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
3ca51d07 | 1505 | set_cc_op(s1, CC_OP_DECB + ot); |
2c0262af FB |
1506 | } |
1507 | if (d != OR_TMP0) | |
57fec1fe | 1508 | gen_op_mov_reg_T0(ot, d); |
2c0262af | 1509 | else |
57fec1fe | 1510 | gen_op_st_T0_A0(ot + s1->mem_index); |
cd31fefa | 1511 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
2c0262af FB |
1512 | } |
1513 | ||
b6abf97d FB |
1514 | static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
1515 | int is_right, int is_arith) | |
2c0262af | 1516 | { |
b6abf97d FB |
1517 | target_ulong mask; |
1518 | int shift_label; | |
82786041 | 1519 | TCGv t0, t1, t2; |
1e4840bf | 1520 | |
82786041 | 1521 | if (ot == OT_QUAD) { |
b6abf97d | 1522 | mask = 0x3f; |
82786041 | 1523 | } else { |
b6abf97d | 1524 | mask = 0x1f; |
82786041 | 1525 | } |
3b46e624 | 1526 | |
b6abf97d | 1527 | /* load */ |
82786041 | 1528 | if (op1 == OR_TMP0) { |
b6abf97d | 1529 | gen_op_ld_T0_A0(ot + s->mem_index); |
82786041 | 1530 | } else { |
b6abf97d | 1531 | gen_op_mov_TN_reg(ot, 0, op1); |
82786041 | 1532 | } |
b6abf97d | 1533 | |
82786041 RH |
1534 | t0 = tcg_temp_local_new(); |
1535 | t1 = tcg_temp_local_new(); | |
1536 | t2 = tcg_temp_local_new(); | |
b6abf97d | 1537 | |
82786041 | 1538 | tcg_gen_andi_tl(t2, cpu_T[1], mask); |
b6abf97d FB |
1539 | |
1540 | if (is_right) { | |
1541 | if (is_arith) { | |
f484d386 | 1542 | gen_exts(ot, cpu_T[0]); |
82786041 RH |
1543 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1544 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d | 1545 | } else { |
cad3a37d | 1546 | gen_extu(ot, cpu_T[0]); |
82786041 RH |
1547 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1548 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1549 | } |
1550 | } else { | |
82786041 RH |
1551 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1552 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1553 | } |
1554 | ||
1555 | /* store */ | |
82786041 | 1556 | if (op1 == OR_TMP0) { |
b6abf97d | 1557 | gen_op_st_T0_A0(ot + s->mem_index); |
82786041 | 1558 | } else { |
b6abf97d | 1559 | gen_op_mov_reg_T0(ot, op1); |
82786041 RH |
1560 | } |
1561 | ||
891a5133 | 1562 | /* Update eflags data because we cannot predict flags afterward. */ |
773cdfcc | 1563 | gen_update_cc_op(s); |
891a5133 | 1564 | set_cc_op(s, CC_OP_DYNAMIC); |
b6abf97d | 1565 | |
82786041 | 1566 | tcg_gen_mov_tl(t1, cpu_T[0]); |
1e4840bf | 1567 | |
b6abf97d | 1568 | shift_label = gen_new_label(); |
82786041 RH |
1569 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label); |
1570 | ||
1571 | tcg_gen_addi_tl(t2, t2, -1); | |
1572 | tcg_gen_mov_tl(cpu_cc_dst, t1); | |
1573 | ||
1574 | if (is_right) { | |
1575 | if (is_arith) { | |
1576 | tcg_gen_sar_tl(cpu_cc_src, t0, t2); | |
1577 | } else { | |
1578 | tcg_gen_shr_tl(cpu_cc_src, t0, t2); | |
1579 | } | |
1580 | } else { | |
1581 | tcg_gen_shl_tl(cpu_cc_src, t0, t2); | |
1582 | } | |
b6abf97d | 1583 | |
82786041 | 1584 | if (is_right) { |
b6abf97d | 1585 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
82786041 | 1586 | } else { |
b6abf97d | 1587 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
82786041 RH |
1588 | } |
1589 | ||
b6abf97d | 1590 | gen_set_label(shift_label); |
1e4840bf FB |
1591 | |
1592 | tcg_temp_free(t0); | |
1593 | tcg_temp_free(t1); | |
82786041 | 1594 | tcg_temp_free(t2); |
b6abf97d FB |
1595 | } |
1596 | ||
c1c37968 FB |
1597 | static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, |
1598 | int is_right, int is_arith) | |
1599 | { | |
1600 | int mask; | |
1601 | ||
1602 | if (ot == OT_QUAD) | |
1603 | mask = 0x3f; | |
1604 | else | |
1605 | mask = 0x1f; | |
1606 | ||
1607 | /* load */ | |
1608 | if (op1 == OR_TMP0) | |
1609 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1610 | else | |
1611 | gen_op_mov_TN_reg(ot, 0, op1); | |
1612 | ||
1613 | op2 &= mask; | |
1614 | if (op2 != 0) { | |
1615 | if (is_right) { | |
1616 | if (is_arith) { | |
1617 | gen_exts(ot, cpu_T[0]); | |
2a449d14 | 1618 | tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1619 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
1620 | } else { | |
1621 | gen_extu(ot, cpu_T[0]); | |
2a449d14 | 1622 | tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1623 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
1624 | } | |
1625 | } else { | |
2a449d14 | 1626 | tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1627 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
1628 | } | |
1629 | } | |
1630 | ||
1631 | /* store */ | |
1632 | if (op1 == OR_TMP0) | |
1633 | gen_op_st_T0_A0(ot + s->mem_index); | |
1634 | else | |
1635 | gen_op_mov_reg_T0(ot, op1); | |
1636 | ||
1637 | /* update eflags if non zero shift */ | |
1638 | if (op2 != 0) { | |
2a449d14 | 1639 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
c1c37968 | 1640 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
3ca51d07 | 1641 | set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot); |
c1c37968 FB |
1642 | } |
1643 | } | |
1644 | ||
b6abf97d FB |
1645 | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1646 | { | |
1647 | if (arg2 >= 0) | |
1648 | tcg_gen_shli_tl(ret, arg1, arg2); | |
1649 | else | |
1650 | tcg_gen_shri_tl(ret, arg1, -arg2); | |
1651 | } | |
1652 | ||
b6abf97d FB |
1653 | static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, |
1654 | int is_right) | |
1655 | { | |
1656 | target_ulong mask; | |
1657 | int label1, label2, data_bits; | |
1e4840bf FB |
1658 | TCGv t0, t1, t2, a0; |
1659 | ||
1660 | /* XXX: inefficient, but we must use local temps */ | |
a7812ae4 PB |
1661 | t0 = tcg_temp_local_new(); |
1662 | t1 = tcg_temp_local_new(); | |
1663 | t2 = tcg_temp_local_new(); | |
1664 | a0 = tcg_temp_local_new(); | |
1e4840bf | 1665 | |
b6abf97d FB |
1666 | if (ot == OT_QUAD) |
1667 | mask = 0x3f; | |
1668 | else | |
1669 | mask = 0x1f; | |
1670 | ||
1671 | /* load */ | |
1e4840bf FB |
1672 | if (op1 == OR_TMP0) { |
1673 | tcg_gen_mov_tl(a0, cpu_A0); | |
1674 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1675 | } else { | |
1676 | gen_op_mov_v_reg(ot, t0, op1); | |
1677 | } | |
b6abf97d | 1678 | |
1e4840bf FB |
1679 | tcg_gen_mov_tl(t1, cpu_T[1]); |
1680 | ||
1681 | tcg_gen_andi_tl(t1, t1, mask); | |
b6abf97d FB |
1682 | |
1683 | /* Must test zero case to avoid using undefined behaviour in TCG | |
1684 | shifts. */ | |
1685 | label1 = gen_new_label(); | |
1e4840bf | 1686 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1); |
b6abf97d FB |
1687 | |
1688 | if (ot <= OT_WORD) | |
1e4840bf | 1689 | tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); |
b6abf97d | 1690 | else |
1e4840bf | 1691 | tcg_gen_mov_tl(cpu_tmp0, t1); |
b6abf97d | 1692 | |
1e4840bf FB |
1693 | gen_extu(ot, t0); |
1694 | tcg_gen_mov_tl(t2, t0); | |
b6abf97d FB |
1695 | |
1696 | data_bits = 8 << ot; | |
1697 | /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX: | |
1698 | fix TCG definition) */ | |
1699 | if (is_right) { | |
1e4840bf | 1700 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1701 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1702 | tcg_gen_shl_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1703 | } else { |
1e4840bf | 1704 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1705 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1706 | tcg_gen_shr_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1707 | } |
1e4840bf | 1708 | tcg_gen_or_tl(t0, t0, cpu_tmp4); |
b6abf97d FB |
1709 | |
1710 | gen_set_label(label1); | |
1711 | /* store */ | |
1e4840bf FB |
1712 | if (op1 == OR_TMP0) { |
1713 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1714 | } else { | |
1715 | gen_op_mov_reg_v(ot, op1, t0); | |
1716 | } | |
b6abf97d | 1717 | |
0ff6addd | 1718 | /* update eflags. It is needed anyway most of the time, do it always. */ |
d229edce | 1719 | gen_compute_eflags(s); |
c7b3c873 | 1720 | assert(s->cc_op == CC_OP_EFLAGS); |
b6abf97d FB |
1721 | |
1722 | label2 = gen_new_label(); | |
1e4840bf | 1723 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2); |
b6abf97d | 1724 | |
b6abf97d | 1725 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
1e4840bf | 1726 | tcg_gen_xor_tl(cpu_tmp0, t2, t0); |
b6abf97d FB |
1727 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
1728 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1729 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1730 | if (is_right) { | |
1e4840bf | 1731 | tcg_gen_shri_tl(t0, t0, data_bits - 1); |
b6abf97d | 1732 | } |
1e4840bf FB |
1733 | tcg_gen_andi_tl(t0, t0, CC_C); |
1734 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
0ff6addd | 1735 | |
b6abf97d | 1736 | gen_set_label(label2); |
1e4840bf FB |
1737 | |
1738 | tcg_temp_free(t0); | |
1739 | tcg_temp_free(t1); | |
1740 | tcg_temp_free(t2); | |
1741 | tcg_temp_free(a0); | |
b6abf97d FB |
1742 | } |
1743 | ||
8cd6345d | 1744 | static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, |
1745 | int is_right) | |
1746 | { | |
1747 | int mask; | |
1748 | int data_bits; | |
1749 | TCGv t0, t1, a0; | |
1750 | ||
1751 | /* XXX: inefficient, but we must use local temps */ | |
1752 | t0 = tcg_temp_local_new(); | |
1753 | t1 = tcg_temp_local_new(); | |
1754 | a0 = tcg_temp_local_new(); | |
1755 | ||
1756 | if (ot == OT_QUAD) | |
1757 | mask = 0x3f; | |
1758 | else | |
1759 | mask = 0x1f; | |
1760 | ||
1761 | /* load */ | |
1762 | if (op1 == OR_TMP0) { | |
1763 | tcg_gen_mov_tl(a0, cpu_A0); | |
1764 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1765 | } else { | |
1766 | gen_op_mov_v_reg(ot, t0, op1); | |
1767 | } | |
1768 | ||
1769 | gen_extu(ot, t0); | |
1770 | tcg_gen_mov_tl(t1, t0); | |
1771 | ||
1772 | op2 &= mask; | |
1773 | data_bits = 8 << ot; | |
1774 | if (op2 != 0) { | |
1775 | int shift = op2 & ((1 << (3 + ot)) - 1); | |
1776 | if (is_right) { | |
1777 | tcg_gen_shri_tl(cpu_tmp4, t0, shift); | |
1778 | tcg_gen_shli_tl(t0, t0, data_bits - shift); | |
1779 | } | |
1780 | else { | |
1781 | tcg_gen_shli_tl(cpu_tmp4, t0, shift); | |
1782 | tcg_gen_shri_tl(t0, t0, data_bits - shift); | |
1783 | } | |
1784 | tcg_gen_or_tl(t0, t0, cpu_tmp4); | |
1785 | } | |
1786 | ||
1787 | /* store */ | |
1788 | if (op1 == OR_TMP0) { | |
1789 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1790 | } else { | |
1791 | gen_op_mov_reg_v(ot, op1, t0); | |
1792 | } | |
1793 | ||
1794 | if (op2 != 0) { | |
1795 | /* update eflags */ | |
d229edce | 1796 | gen_compute_eflags(s); |
c7b3c873 | 1797 | assert(s->cc_op == CC_OP_EFLAGS); |
0ff6addd | 1798 | |
8cd6345d | 1799 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
1800 | tcg_gen_xor_tl(cpu_tmp0, t1, t0); | |
1801 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); | |
1802 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1803 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1804 | if (is_right) { | |
1805 | tcg_gen_shri_tl(t0, t0, data_bits - 1); | |
1806 | } | |
1807 | tcg_gen_andi_tl(t0, t0, CC_C); | |
1808 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
8cd6345d | 1809 | } |
1810 | ||
1811 | tcg_temp_free(t0); | |
1812 | tcg_temp_free(t1); | |
1813 | tcg_temp_free(a0); | |
1814 | } | |
1815 | ||
b6abf97d FB |
1816 | /* XXX: add faster immediate = 1 case */ |
1817 | static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, | |
1818 | int is_right) | |
1819 | { | |
d229edce | 1820 | gen_compute_eflags(s); |
c7b3c873 | 1821 | assert(s->cc_op == CC_OP_EFLAGS); |
b6abf97d FB |
1822 | |
1823 | /* load */ | |
1824 | if (op1 == OR_TMP0) | |
1825 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1826 | else | |
1827 | gen_op_mov_TN_reg(ot, 0, op1); | |
1828 | ||
a7812ae4 PB |
1829 | if (is_right) { |
1830 | switch (ot) { | |
93ab25d7 | 1831 | case OT_BYTE: |
7923057b BS |
1832 | gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1833 | break; | |
93ab25d7 | 1834 | case OT_WORD: |
7923057b BS |
1835 | gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1836 | break; | |
93ab25d7 | 1837 | case OT_LONG: |
7923057b BS |
1838 | gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1839 | break; | |
a7812ae4 | 1840 | #ifdef TARGET_X86_64 |
93ab25d7 | 1841 | case OT_QUAD: |
7923057b BS |
1842 | gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1843 | break; | |
a7812ae4 PB |
1844 | #endif |
1845 | } | |
1846 | } else { | |
1847 | switch (ot) { | |
93ab25d7 | 1848 | case OT_BYTE: |
7923057b BS |
1849 | gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1850 | break; | |
93ab25d7 | 1851 | case OT_WORD: |
7923057b BS |
1852 | gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1853 | break; | |
93ab25d7 | 1854 | case OT_LONG: |
7923057b BS |
1855 | gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1856 | break; | |
a7812ae4 | 1857 | #ifdef TARGET_X86_64 |
93ab25d7 | 1858 | case OT_QUAD: |
7923057b BS |
1859 | gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1860 | break; | |
a7812ae4 PB |
1861 | #endif |
1862 | } | |
1863 | } | |
b6abf97d FB |
1864 | /* store */ |
1865 | if (op1 == OR_TMP0) | |
1866 | gen_op_st_T0_A0(ot + s->mem_index); | |
1867 | else | |
1868 | gen_op_mov_reg_T0(ot, op1); | |
b6abf97d FB |
1869 | } |
1870 | ||
1871 | /* XXX: add faster immediate case */ | |
3b9d3cf1 PB |
1872 | static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1, |
1873 | int is_right, TCGv count) | |
b6abf97d FB |
1874 | { |
1875 | int label1, label2, data_bits; | |
1876 | target_ulong mask; | |
1e4840bf FB |
1877 | TCGv t0, t1, t2, a0; |
1878 | ||
a7812ae4 PB |
1879 | t0 = tcg_temp_local_new(); |
1880 | t1 = tcg_temp_local_new(); | |
1881 | t2 = tcg_temp_local_new(); | |
1882 | a0 = tcg_temp_local_new(); | |
b6abf97d FB |
1883 | |
1884 | if (ot == OT_QUAD) | |
1885 | mask = 0x3f; | |
1886 | else | |
1887 | mask = 0x1f; | |
1888 | ||
1889 | /* load */ | |
1e4840bf FB |
1890 | if (op1 == OR_TMP0) { |
1891 | tcg_gen_mov_tl(a0, cpu_A0); | |
1892 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1893 | } else { | |
1894 | gen_op_mov_v_reg(ot, t0, op1); | |
1895 | } | |
b6abf97d | 1896 | |
3b9d3cf1 | 1897 | tcg_gen_andi_tl(t2, count, mask); |
1e4840bf | 1898 | tcg_gen_mov_tl(t1, cpu_T[1]); |
1e4840bf | 1899 | |
b6abf97d FB |
1900 | /* Must test zero case to avoid using undefined behaviour in TCG |
1901 | shifts. */ | |
1902 | label1 = gen_new_label(); | |
1e4840bf | 1903 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); |
b6abf97d | 1904 | |
1e4840bf | 1905 | tcg_gen_addi_tl(cpu_tmp5, t2, -1); |
b6abf97d FB |
1906 | if (ot == OT_WORD) { |
1907 | /* Note: we implement the Intel behaviour for shift count > 16 */ | |
1908 | if (is_right) { | |
1e4840bf FB |
1909 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1910 | tcg_gen_shli_tl(cpu_tmp0, t1, 16); | |
1911 | tcg_gen_or_tl(t0, t0, cpu_tmp0); | |
1912 | tcg_gen_ext32u_tl(t0, t0); | |
b6abf97d | 1913 | |
1e4840bf | 1914 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d FB |
1915 | |
1916 | /* only needed if count > 16, but a test would complicate */ | |
5b207c00 | 1917 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf | 1918 | tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5); |
b6abf97d | 1919 | |
1e4840bf | 1920 | tcg_gen_shr_tl(t0, t0, t2); |
b6abf97d | 1921 | |
1e4840bf | 1922 | tcg_gen_or_tl(t0, t0, cpu_tmp0); |
b6abf97d FB |
1923 | } else { |
1924 | /* XXX: not optimal */ | |
1e4840bf FB |
1925 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1926 | tcg_gen_shli_tl(t1, t1, 16); | |
1927 | tcg_gen_or_tl(t1, t1, t0); | |
1928 | tcg_gen_ext32u_tl(t1, t1); | |
b6abf97d | 1929 | |
1e4840bf | 1930 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
5b207c00 | 1931 | tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5); |
bedda79c AJ |
1932 | tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0); |
1933 | tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5); | |
b6abf97d | 1934 | |
1e4840bf | 1935 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1936 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf FB |
1937 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1938 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1939 | } |
1940 | } else { | |
1941 | data_bits = 8 << ot; | |
1942 | if (is_right) { | |
1943 | if (ot == OT_LONG) | |
1e4840bf | 1944 | tcg_gen_ext32u_tl(t0, t0); |
b6abf97d | 1945 | |
1e4840bf | 1946 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1947 | |
1e4840bf | 1948 | tcg_gen_shr_tl(t0, t0, t2); |
5b207c00 | 1949 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1950 | tcg_gen_shl_tl(t1, t1, cpu_tmp5); |
1951 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1952 | |
1953 | } else { | |
1954 | if (ot == OT_LONG) | |
1e4840bf | 1955 | tcg_gen_ext32u_tl(t1, t1); |
b6abf97d | 1956 | |
1e4840bf | 1957 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1958 | |
1e4840bf | 1959 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1960 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1961 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1962 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1963 | } |
1964 | } | |
1e4840bf | 1965 | tcg_gen_mov_tl(t1, cpu_tmp4); |
b6abf97d FB |
1966 | |
1967 | gen_set_label(label1); | |
1968 | /* store */ | |
1e4840bf FB |
1969 | if (op1 == OR_TMP0) { |
1970 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1971 | } else { | |
1972 | gen_op_mov_reg_v(ot, op1, t0); | |
1973 | } | |
b6abf97d | 1974 | |
891a5133 | 1975 | /* Update eflags data because we cannot predict flags afterward. */ |
773cdfcc | 1976 | gen_update_cc_op(s); |
891a5133 | 1977 | set_cc_op(s, CC_OP_DYNAMIC); |
b6abf97d FB |
1978 | |
1979 | label2 = gen_new_label(); | |
1e4840bf | 1980 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2); |
b6abf97d | 1981 | |
1e4840bf FB |
1982 | tcg_gen_mov_tl(cpu_cc_src, t1); |
1983 | tcg_gen_mov_tl(cpu_cc_dst, t0); | |
b6abf97d FB |
1984 | if (is_right) { |
1985 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); | |
1986 | } else { | |
1987 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); | |
1988 | } | |
1989 | gen_set_label(label2); | |
1e4840bf FB |
1990 | |
1991 | tcg_temp_free(t0); | |
1992 | tcg_temp_free(t1); | |
1993 | tcg_temp_free(t2); | |
1994 | tcg_temp_free(a0); | |
b6abf97d FB |
1995 | } |
1996 | ||
1997 | static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) | |
1998 | { | |
1999 | if (s != OR_TMP1) | |
2000 | gen_op_mov_TN_reg(ot, 1, s); | |
2001 | switch(op) { | |
2002 | case OP_ROL: | |
2003 | gen_rot_rm_T1(s1, ot, d, 0); | |
2004 | break; | |
2005 | case OP_ROR: | |
2006 | gen_rot_rm_T1(s1, ot, d, 1); | |
2007 | break; | |
2008 | case OP_SHL: | |
2009 | case OP_SHL1: | |
2010 | gen_shift_rm_T1(s1, ot, d, 0, 0); | |
2011 | break; | |
2012 | case OP_SHR: | |
2013 | gen_shift_rm_T1(s1, ot, d, 1, 0); | |
2014 | break; | |
2015 | case OP_SAR: | |
2016 | gen_shift_rm_T1(s1, ot, d, 1, 1); | |
2017 | break; | |
2018 | case OP_RCL: | |
2019 | gen_rotc_rm_T1(s1, ot, d, 0); | |
2020 | break; | |
2021 | case OP_RCR: | |
2022 | gen_rotc_rm_T1(s1, ot, d, 1); | |
2023 | break; | |
2024 | } | |
2c0262af FB |
2025 | } |
2026 | ||
2027 | static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) | |
2028 | { | |
c1c37968 | 2029 | switch(op) { |
8cd6345d | 2030 | case OP_ROL: |
2031 | gen_rot_rm_im(s1, ot, d, c, 0); | |
2032 | break; | |
2033 | case OP_ROR: | |
2034 | gen_rot_rm_im(s1, ot, d, c, 1); | |
2035 | break; | |
c1c37968 FB |
2036 | case OP_SHL: |
2037 | case OP_SHL1: | |
2038 | gen_shift_rm_im(s1, ot, d, c, 0, 0); | |
2039 | break; | |
2040 | case OP_SHR: | |
2041 | gen_shift_rm_im(s1, ot, d, c, 1, 0); | |
2042 | break; | |
2043 | case OP_SAR: | |
2044 | gen_shift_rm_im(s1, ot, d, c, 1, 1); | |
2045 | break; | |
2046 | default: | |
2047 | /* currently not optimized */ | |
2048 | gen_op_movl_T1_im(c); | |
2049 | gen_shift(s1, op, ot, d, OR_TMP1); | |
2050 | break; | |
2051 | } | |
2c0262af FB |
2052 | } |
2053 | ||
0af10c86 BS |
2054 | static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm, |
2055 | int *reg_ptr, int *offset_ptr) | |
2c0262af | 2056 | { |
14ce26e7 | 2057 | target_long disp; |
2c0262af | 2058 | int havesib; |
14ce26e7 | 2059 | int base; |
2c0262af FB |
2060 | int index; |
2061 | int scale; | |
2062 | int opreg; | |
2063 | int mod, rm, code, override, must_add_seg; | |
2064 | ||
2065 | override = s->override; | |
2066 | must_add_seg = s->addseg; | |
2067 | if (override >= 0) | |
2068 | must_add_seg = 1; | |
2069 | mod = (modrm >> 6) & 3; | |
2070 | rm = modrm & 7; | |
2071 | ||
2072 | if (s->aflag) { | |
2073 | ||
2074 | havesib = 0; | |
2075 | base = rm; | |
2076 | index = 0; | |
2077 | scale = 0; | |
3b46e624 | 2078 | |
2c0262af FB |
2079 | if (base == 4) { |
2080 | havesib = 1; | |
0af10c86 | 2081 | code = cpu_ldub_code(env, s->pc++); |
2c0262af | 2082 | scale = (code >> 6) & 3; |
14ce26e7 FB |
2083 | index = ((code >> 3) & 7) | REX_X(s); |
2084 | base = (code & 7); | |
2c0262af | 2085 | } |
14ce26e7 | 2086 | base |= REX_B(s); |
2c0262af FB |
2087 | |
2088 | switch (mod) { | |
2089 | case 0: | |
14ce26e7 | 2090 | if ((base & 7) == 5) { |
2c0262af | 2091 | base = -1; |
0af10c86 | 2092 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af | 2093 | s->pc += 4; |
14ce26e7 FB |
2094 | if (CODE64(s) && !havesib) { |
2095 | disp += s->pc + s->rip_offset; | |
2096 | } | |
2c0262af FB |
2097 | } else { |
2098 | disp = 0; | |
2099 | } | |
2100 | break; | |
2101 | case 1: | |
0af10c86 | 2102 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
2103 | break; |
2104 | default: | |
2105 | case 2: | |
0af10c86 | 2106 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af FB |
2107 | s->pc += 4; |
2108 | break; | |
2109 | } | |
3b46e624 | 2110 | |
2c0262af FB |
2111 | if (base >= 0) { |
2112 | /* for correct popl handling with esp */ | |
2113 | if (base == 4 && s->popl_esp_hack) | |
2114 | disp += s->popl_esp_hack; | |
14ce26e7 FB |
2115 | #ifdef TARGET_X86_64 |
2116 | if (s->aflag == 2) { | |
57fec1fe | 2117 | gen_op_movq_A0_reg(base); |
14ce26e7 | 2118 | if (disp != 0) { |
57fec1fe | 2119 | gen_op_addq_A0_im(disp); |
14ce26e7 | 2120 | } |
5fafdf24 | 2121 | } else |
14ce26e7 FB |
2122 | #endif |
2123 | { | |
57fec1fe | 2124 | gen_op_movl_A0_reg(base); |
14ce26e7 FB |
2125 | if (disp != 0) |
2126 | gen_op_addl_A0_im(disp); | |
2127 | } | |
2c0262af | 2128 | } else { |
14ce26e7 FB |
2129 | #ifdef TARGET_X86_64 |
2130 | if (s->aflag == 2) { | |
57fec1fe | 2131 | gen_op_movq_A0_im(disp); |
5fafdf24 | 2132 | } else |
14ce26e7 FB |
2133 | #endif |
2134 | { | |
2135 | gen_op_movl_A0_im(disp); | |
2136 | } | |
2c0262af | 2137 | } |
b16f827b AJ |
2138 | /* index == 4 means no index */ |
2139 | if (havesib && (index != 4)) { | |
14ce26e7 FB |
2140 | #ifdef TARGET_X86_64 |
2141 | if (s->aflag == 2) { | |
57fec1fe | 2142 | gen_op_addq_A0_reg_sN(scale, index); |
5fafdf24 | 2143 | } else |
14ce26e7 FB |
2144 | #endif |
2145 | { | |
57fec1fe | 2146 | gen_op_addl_A0_reg_sN(scale, index); |
14ce26e7 | 2147 | } |
2c0262af FB |
2148 | } |
2149 | if (must_add_seg) { | |
2150 | if (override < 0) { | |
2151 | if (base == R_EBP || base == R_ESP) | |
2152 | override = R_SS; | |
2153 | else | |
2154 | override = R_DS; | |
2155 | } | |
14ce26e7 FB |
2156 | #ifdef TARGET_X86_64 |
2157 | if (s->aflag == 2) { | |
57fec1fe | 2158 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2159 | } else |
14ce26e7 FB |
2160 | #endif |
2161 | { | |
7162ab21 | 2162 | gen_op_addl_A0_seg(s, override); |
14ce26e7 | 2163 | } |
2c0262af FB |
2164 | } |
2165 | } else { | |
2166 | switch (mod) { | |
2167 | case 0: | |
2168 | if (rm == 6) { | |
0af10c86 | 2169 | disp = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2170 | s->pc += 2; |
2171 | gen_op_movl_A0_im(disp); | |
2172 | rm = 0; /* avoid SS override */ | |
2173 | goto no_rm; | |
2174 | } else { | |
2175 | disp = 0; | |
2176 | } | |
2177 | break; | |
2178 | case 1: | |
0af10c86 | 2179 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
2180 | break; |
2181 | default: | |
2182 | case 2: | |
0af10c86 | 2183 | disp = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2184 | s->pc += 2; |
2185 | break; | |
2186 | } | |
2187 | switch(rm) { | |
2188 | case 0: | |
57fec1fe FB |
2189 | gen_op_movl_A0_reg(R_EBX); |
2190 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2191 | break; |
2192 | case 1: | |
57fec1fe FB |
2193 | gen_op_movl_A0_reg(R_EBX); |
2194 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2195 | break; |
2196 | case 2: | |
57fec1fe FB |
2197 | gen_op_movl_A0_reg(R_EBP); |
2198 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2199 | break; |
2200 | case 3: | |
57fec1fe FB |
2201 | gen_op_movl_A0_reg(R_EBP); |
2202 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2203 | break; |
2204 | case 4: | |
57fec1fe | 2205 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
2206 | break; |
2207 | case 5: | |
57fec1fe | 2208 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
2209 | break; |
2210 | case 6: | |
57fec1fe | 2211 | gen_op_movl_A0_reg(R_EBP); |
2c0262af FB |
2212 | break; |
2213 | default: | |
2214 | case 7: | |
57fec1fe | 2215 | gen_op_movl_A0_reg(R_EBX); |
2c0262af FB |
2216 | break; |
2217 | } | |
2218 | if (disp != 0) | |
2219 | gen_op_addl_A0_im(disp); | |
2220 | gen_op_andl_A0_ffff(); | |
2221 | no_rm: | |
2222 | if (must_add_seg) { | |
2223 | if (override < 0) { | |
2224 | if (rm == 2 || rm == 3 || rm == 6) | |
2225 | override = R_SS; | |
2226 | else | |
2227 | override = R_DS; | |
2228 | } | |
7162ab21 | 2229 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
2230 | } |
2231 | } | |
2232 | ||
2233 | opreg = OR_A0; | |
2234 | disp = 0; | |
2235 | *reg_ptr = opreg; | |
2236 | *offset_ptr = disp; | |
2237 | } | |
2238 | ||
0af10c86 | 2239 | static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) |
e17a36ce FB |
2240 | { |
2241 | int mod, rm, base, code; | |
2242 | ||
2243 | mod = (modrm >> 6) & 3; | |
2244 | if (mod == 3) | |
2245 | return; | |
2246 | rm = modrm & 7; | |
2247 | ||
2248 | if (s->aflag) { | |
2249 | ||
2250 | base = rm; | |
3b46e624 | 2251 | |
e17a36ce | 2252 | if (base == 4) { |
0af10c86 | 2253 | code = cpu_ldub_code(env, s->pc++); |
e17a36ce FB |
2254 | base = (code & 7); |
2255 | } | |
3b46e624 | 2256 | |
e17a36ce FB |
2257 | switch (mod) { |
2258 | case 0: | |
2259 | if (base == 5) { | |
2260 | s->pc += 4; | |
2261 | } | |
2262 | break; | |
2263 | case 1: | |
2264 | s->pc++; | |
2265 | break; | |
2266 | default: | |
2267 | case 2: | |
2268 | s->pc += 4; | |
2269 | break; | |
2270 | } | |
2271 | } else { | |
2272 | switch (mod) { | |
2273 | case 0: | |
2274 | if (rm == 6) { | |
2275 | s->pc += 2; | |
2276 | } | |
2277 | break; | |
2278 | case 1: | |
2279 | s->pc++; | |
2280 | break; | |
2281 | default: | |
2282 | case 2: | |
2283 | s->pc += 2; | |
2284 | break; | |
2285 | } | |
2286 | } | |
2287 | } | |
2288 | ||
664e0f19 FB |
2289 | /* used for LEA and MOV AX, mem */ |
2290 | static void gen_add_A0_ds_seg(DisasContext *s) | |
2291 | { | |
2292 | int override, must_add_seg; | |
2293 | must_add_seg = s->addseg; | |
2294 | override = R_DS; | |
2295 | if (s->override >= 0) { | |
2296 | override = s->override; | |
2297 | must_add_seg = 1; | |
664e0f19 FB |
2298 | } |
2299 | if (must_add_seg) { | |
8f091a59 FB |
2300 | #ifdef TARGET_X86_64 |
2301 | if (CODE64(s)) { | |
57fec1fe | 2302 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2303 | } else |
8f091a59 FB |
2304 | #endif |
2305 | { | |
7162ab21 | 2306 | gen_op_addl_A0_seg(s, override); |
8f091a59 | 2307 | } |
664e0f19 FB |
2308 | } |
2309 | } | |
2310 | ||
222a3336 | 2311 | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == |
2c0262af | 2312 | OR_TMP0 */ |
0af10c86 BS |
2313 | static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, |
2314 | int ot, int reg, int is_store) | |
2c0262af FB |
2315 | { |
2316 | int mod, rm, opreg, disp; | |
2317 | ||
2318 | mod = (modrm >> 6) & 3; | |
14ce26e7 | 2319 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
2320 | if (mod == 3) { |
2321 | if (is_store) { | |
2322 | if (reg != OR_TMP0) | |
57fec1fe FB |
2323 | gen_op_mov_TN_reg(ot, 0, reg); |
2324 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 2325 | } else { |
57fec1fe | 2326 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 2327 | if (reg != OR_TMP0) |
57fec1fe | 2328 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2329 | } |
2330 | } else { | |
0af10c86 | 2331 | gen_lea_modrm(env, s, modrm, &opreg, &disp); |
2c0262af FB |
2332 | if (is_store) { |
2333 | if (reg != OR_TMP0) | |
57fec1fe FB |
2334 | gen_op_mov_TN_reg(ot, 0, reg); |
2335 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 2336 | } else { |
57fec1fe | 2337 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 2338 | if (reg != OR_TMP0) |
57fec1fe | 2339 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2340 | } |
2341 | } | |
2342 | } | |
2343 | ||
0af10c86 | 2344 | static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot) |
2c0262af FB |
2345 | { |
2346 | uint32_t ret; | |
2347 | ||
2348 | switch(ot) { | |
2349 | case OT_BYTE: | |
0af10c86 | 2350 | ret = cpu_ldub_code(env, s->pc); |
2c0262af FB |
2351 | s->pc++; |
2352 | break; | |
2353 | case OT_WORD: | |
0af10c86 | 2354 | ret = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2355 | s->pc += 2; |
2356 | break; | |
2357 | default: | |
2358 | case OT_LONG: | |
0af10c86 | 2359 | ret = cpu_ldl_code(env, s->pc); |
2c0262af FB |
2360 | s->pc += 4; |
2361 | break; | |
2362 | } | |
2363 | return ret; | |
2364 | } | |
2365 | ||
14ce26e7 FB |
2366 | static inline int insn_const_size(unsigned int ot) |
2367 | { | |
2368 | if (ot <= OT_LONG) | |
2369 | return 1 << ot; | |
2370 | else | |
2371 | return 4; | |
2372 | } | |
2373 | ||
6e256c93 FB |
2374 | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2375 | { | |
2376 | TranslationBlock *tb; | |
2377 | target_ulong pc; | |
2378 | ||
2379 | pc = s->cs_base + eip; | |
2380 | tb = s->tb; | |
2381 | /* NOTE: we handle the case where the TB spans two pages here */ | |
2382 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) || | |
2383 | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { | |
2384 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 2385 | tcg_gen_goto_tb(tb_num); |
6e256c93 | 2386 | gen_jmp_im(eip); |
4b4a72e5 | 2387 | tcg_gen_exit_tb((tcg_target_long)tb + tb_num); |
6e256c93 FB |
2388 | } else { |
2389 | /* jump to another page: currently not optimized */ | |
2390 | gen_jmp_im(eip); | |
2391 | gen_eob(s); | |
2392 | } | |
2393 | } | |
2394 | ||
5fafdf24 | 2395 | static inline void gen_jcc(DisasContext *s, int b, |
14ce26e7 | 2396 | target_ulong val, target_ulong next_eip) |
2c0262af | 2397 | { |
b27fc131 | 2398 | int l1, l2; |
3b46e624 | 2399 | |
2c0262af | 2400 | if (s->jmp_opt) { |
14ce26e7 | 2401 | l1 = gen_new_label(); |
b27fc131 | 2402 | gen_jcc1(s, b, l1); |
dc259201 | 2403 | |
6e256c93 | 2404 | gen_goto_tb(s, 0, next_eip); |
14ce26e7 FB |
2405 | |
2406 | gen_set_label(l1); | |
6e256c93 | 2407 | gen_goto_tb(s, 1, val); |
5779406a | 2408 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2409 | } else { |
14ce26e7 FB |
2410 | l1 = gen_new_label(); |
2411 | l2 = gen_new_label(); | |
b27fc131 | 2412 | gen_jcc1(s, b, l1); |
8e1c85e3 | 2413 | |
14ce26e7 | 2414 | gen_jmp_im(next_eip); |
8e1c85e3 FB |
2415 | tcg_gen_br(l2); |
2416 | ||
14ce26e7 FB |
2417 | gen_set_label(l1); |
2418 | gen_jmp_im(val); | |
2419 | gen_set_label(l2); | |
2c0262af FB |
2420 | gen_eob(s); |
2421 | } | |
2422 | } | |
2423 | ||
f32d3781 PB |
2424 | static void gen_cmovcc1(CPUX86State *env, DisasContext *s, int ot, int b, |
2425 | int modrm, int reg) | |
2426 | { | |
57eb0cc8 | 2427 | CCPrepare cc; |
f32d3781 | 2428 | |
57eb0cc8 | 2429 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
f32d3781 | 2430 | |
57eb0cc8 RH |
2431 | cc = gen_prepare_cc(s, b, cpu_T[1]); |
2432 | if (cc.mask != -1) { | |
2433 | TCGv t0 = tcg_temp_new(); | |
2434 | tcg_gen_andi_tl(t0, cc.reg, cc.mask); | |
2435 | cc.reg = t0; | |
2436 | } | |
2437 | if (!cc.use_reg2) { | |
2438 | cc.reg2 = tcg_const_tl(cc.imm); | |
f32d3781 PB |
2439 | } |
2440 | ||
57eb0cc8 RH |
2441 | tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2, |
2442 | cpu_T[0], cpu_regs[reg]); | |
2443 | gen_op_mov_reg_T0(ot, reg); | |
2444 | ||
2445 | if (cc.mask != -1) { | |
2446 | tcg_temp_free(cc.reg); | |
2447 | } | |
2448 | if (!cc.use_reg2) { | |
2449 | tcg_temp_free(cc.reg2); | |
2450 | } | |
f32d3781 PB |
2451 | } |
2452 | ||
3bd7da9e FB |
2453 | static inline void gen_op_movl_T0_seg(int seg_reg) |
2454 | { | |
2455 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, | |
2456 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2457 | } | |
2458 | ||
2459 | static inline void gen_op_movl_seg_T0_vm(int seg_reg) | |
2460 | { | |
2461 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
2462 | tcg_gen_st32_tl(cpu_T[0], cpu_env, | |
2463 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2464 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); | |
2465 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
2466 | offsetof(CPUX86State,segs[seg_reg].base)); | |
2467 | } | |
2468 | ||
2c0262af FB |
2469 | /* move T0 to seg_reg and compute if the CPU state may change. Never |
2470 | call this function with seg_reg == R_CS */ | |
14ce26e7 | 2471 | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2c0262af | 2472 | { |
3415a4dd FB |
2473 | if (s->pe && !s->vm86) { |
2474 | /* XXX: optimize by finding processor state dynamically */ | |
773cdfcc | 2475 | gen_update_cc_op(s); |
14ce26e7 | 2476 | gen_jmp_im(cur_eip); |
b6abf97d | 2477 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 2478 | gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32); |
dc196a57 FB |
2479 | /* abort translation because the addseg value may change or |
2480 | because ss32 may change. For R_SS, translation must always | |
2481 | stop as a special handling must be done to disable hardware | |
2482 | interrupts for the next instruction */ | |
2483 | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) | |
5779406a | 2484 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2485 | } else { |
3bd7da9e | 2486 | gen_op_movl_seg_T0_vm(seg_reg); |
dc196a57 | 2487 | if (seg_reg == R_SS) |
5779406a | 2488 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2489 | } |
2c0262af FB |
2490 | } |
2491 | ||
0573fbfc TS |
2492 | static inline int svm_is_rep(int prefixes) |
2493 | { | |
2494 | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); | |
2495 | } | |
2496 | ||
872929aa | 2497 | static inline void |
0573fbfc | 2498 | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
b8b6a50b | 2499 | uint32_t type, uint64_t param) |
0573fbfc | 2500 | { |
872929aa FB |
2501 | /* no SVM activated; fast case */ |
2502 | if (likely(!(s->flags & HF_SVMI_MASK))) | |
2503 | return; | |
773cdfcc | 2504 | gen_update_cc_op(s); |
872929aa | 2505 | gen_jmp_im(pc_start - s->cs_base); |
052e80d5 | 2506 | gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), |
a7812ae4 | 2507 | tcg_const_i64(param)); |
0573fbfc TS |
2508 | } |
2509 | ||
872929aa | 2510 | static inline void |
0573fbfc TS |
2511 | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2512 | { | |
872929aa | 2513 | gen_svm_check_intercept_param(s, pc_start, type, 0); |
0573fbfc TS |
2514 | } |
2515 | ||
4f31916f FB |
2516 | static inline void gen_stack_update(DisasContext *s, int addend) |
2517 | { | |
14ce26e7 FB |
2518 | #ifdef TARGET_X86_64 |
2519 | if (CODE64(s)) { | |
6e0d8677 | 2520 | gen_op_add_reg_im(2, R_ESP, addend); |
14ce26e7 FB |
2521 | } else |
2522 | #endif | |
4f31916f | 2523 | if (s->ss32) { |
6e0d8677 | 2524 | gen_op_add_reg_im(1, R_ESP, addend); |
4f31916f | 2525 | } else { |
6e0d8677 | 2526 | gen_op_add_reg_im(0, R_ESP, addend); |
4f31916f FB |
2527 | } |
2528 | } | |
2529 | ||
2c0262af FB |
2530 | /* generate a push. It depends on ss32, addseg and dflag */ |
2531 | static void gen_push_T0(DisasContext *s) | |
2532 | { | |
14ce26e7 FB |
2533 | #ifdef TARGET_X86_64 |
2534 | if (CODE64(s)) { | |
57fec1fe | 2535 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2536 | if (s->dflag) { |
57fec1fe FB |
2537 | gen_op_addq_A0_im(-8); |
2538 | gen_op_st_T0_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2539 | } else { |
57fec1fe FB |
2540 | gen_op_addq_A0_im(-2); |
2541 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2542 | } |
57fec1fe | 2543 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2544 | } else |
14ce26e7 FB |
2545 | #endif |
2546 | { | |
57fec1fe | 2547 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2548 | if (!s->dflag) |
57fec1fe | 2549 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2550 | else |
57fec1fe | 2551 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2552 | if (s->ss32) { |
2553 | if (s->addseg) { | |
bbf662ee | 2554 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2555 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2556 | } |
2557 | } else { | |
2558 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2559 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2560 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2561 | } |
57fec1fe | 2562 | gen_op_st_T0_A0(s->dflag + 1 + s->mem_index); |
14ce26e7 | 2563 | if (s->ss32 && !s->addseg) |
57fec1fe | 2564 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 | 2565 | else |
57fec1fe | 2566 | gen_op_mov_reg_T1(s->ss32 + 1, R_ESP); |
2c0262af FB |
2567 | } |
2568 | } | |
2569 | ||
4f31916f FB |
2570 | /* generate a push. It depends on ss32, addseg and dflag */ |
2571 | /* slower version for T1, only used for call Ev */ | |
2572 | static void gen_push_T1(DisasContext *s) | |
2c0262af | 2573 | { |
14ce26e7 FB |
2574 | #ifdef TARGET_X86_64 |
2575 | if (CODE64(s)) { | |
57fec1fe | 2576 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2577 | if (s->dflag) { |
57fec1fe FB |
2578 | gen_op_addq_A0_im(-8); |
2579 | gen_op_st_T1_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2580 | } else { |
57fec1fe FB |
2581 | gen_op_addq_A0_im(-2); |
2582 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2583 | } |
57fec1fe | 2584 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2585 | } else |
14ce26e7 FB |
2586 | #endif |
2587 | { | |
57fec1fe | 2588 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2589 | if (!s->dflag) |
57fec1fe | 2590 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2591 | else |
57fec1fe | 2592 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2593 | if (s->ss32) { |
2594 | if (s->addseg) { | |
7162ab21 | 2595 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2596 | } |
2597 | } else { | |
2598 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2599 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2600 | } |
57fec1fe | 2601 | gen_op_st_T1_A0(s->dflag + 1 + s->mem_index); |
3b46e624 | 2602 | |
14ce26e7 | 2603 | if (s->ss32 && !s->addseg) |
57fec1fe | 2604 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 FB |
2605 | else |
2606 | gen_stack_update(s, (-2) << s->dflag); | |
2c0262af FB |
2607 | } |
2608 | } | |
2609 | ||
4f31916f FB |
2610 | /* two step pop is necessary for precise exceptions */ |
2611 | static void gen_pop_T0(DisasContext *s) | |
2c0262af | 2612 | { |
14ce26e7 FB |
2613 | #ifdef TARGET_X86_64 |
2614 | if (CODE64(s)) { | |
57fec1fe FB |
2615 | gen_op_movq_A0_reg(R_ESP); |
2616 | gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index); | |
5fafdf24 | 2617 | } else |
14ce26e7 FB |
2618 | #endif |
2619 | { | |
57fec1fe | 2620 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 FB |
2621 | if (s->ss32) { |
2622 | if (s->addseg) | |
7162ab21 | 2623 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2624 | } else { |
2625 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2626 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 | 2627 | } |
57fec1fe | 2628 | gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index); |
2c0262af FB |
2629 | } |
2630 | } | |
2631 | ||
2632 | static void gen_pop_update(DisasContext *s) | |
2633 | { | |
14ce26e7 | 2634 | #ifdef TARGET_X86_64 |
8f091a59 | 2635 | if (CODE64(s) && s->dflag) { |
14ce26e7 FB |
2636 | gen_stack_update(s, 8); |
2637 | } else | |
2638 | #endif | |
2639 | { | |
2640 | gen_stack_update(s, 2 << s->dflag); | |
2641 | } | |
2c0262af FB |
2642 | } |
2643 | ||
2644 | static void gen_stack_A0(DisasContext *s) | |
2645 | { | |
57fec1fe | 2646 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2647 | if (!s->ss32) |
2648 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2649 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2650 | if (s->addseg) |
7162ab21 | 2651 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2652 | } |
2653 | ||
2654 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2655 | static void gen_pusha(DisasContext *s) | |
2656 | { | |
2657 | int i; | |
57fec1fe | 2658 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2659 | gen_op_addl_A0_im(-16 << s->dflag); |
2660 | if (!s->ss32) | |
2661 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2662 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2663 | if (s->addseg) |
7162ab21 | 2664 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2665 | for(i = 0;i < 8; i++) { |
57fec1fe FB |
2666 | gen_op_mov_TN_reg(OT_LONG, 0, 7 - i); |
2667 | gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index); | |
2c0262af FB |
2668 | gen_op_addl_A0_im(2 << s->dflag); |
2669 | } | |
57fec1fe | 2670 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2671 | } |
2672 | ||
2673 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2674 | static void gen_popa(DisasContext *s) | |
2675 | { | |
2676 | int i; | |
57fec1fe | 2677 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2678 | if (!s->ss32) |
2679 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
2680 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2681 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); | |
2c0262af | 2682 | if (s->addseg) |
7162ab21 | 2683 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2684 | for(i = 0;i < 8; i++) { |
2685 | /* ESP is not reloaded */ | |
2686 | if (i != 3) { | |
57fec1fe FB |
2687 | gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2688 | gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i); | |
2c0262af FB |
2689 | } |
2690 | gen_op_addl_A0_im(2 << s->dflag); | |
2691 | } | |
57fec1fe | 2692 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2693 | } |
2694 | ||
2c0262af FB |
2695 | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2696 | { | |
61a8c4ec | 2697 | int ot, opsize; |
2c0262af | 2698 | |
2c0262af | 2699 | level &= 0x1f; |
8f091a59 FB |
2700 | #ifdef TARGET_X86_64 |
2701 | if (CODE64(s)) { | |
2702 | ot = s->dflag ? OT_QUAD : OT_WORD; | |
2703 | opsize = 1 << ot; | |
3b46e624 | 2704 | |
57fec1fe | 2705 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 | 2706 | gen_op_addq_A0_im(-opsize); |
bbf662ee | 2707 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 FB |
2708 | |
2709 | /* push bp */ | |
57fec1fe FB |
2710 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2711 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2712 | if (level) { |
b5b38f61 | 2713 | /* XXX: must save state */ |
2999a0b2 | 2714 | gen_helper_enter64_level(cpu_env, tcg_const_i32(level), |
a7812ae4 PB |
2715 | tcg_const_i32((ot == OT_QUAD)), |
2716 | cpu_T[1]); | |
8f091a59 | 2717 | } |
57fec1fe | 2718 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2719 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2720 | gen_op_mov_reg_T1(OT_QUAD, R_ESP); |
5fafdf24 | 2721 | } else |
8f091a59 FB |
2722 | #endif |
2723 | { | |
2724 | ot = s->dflag + OT_WORD; | |
2725 | opsize = 2 << s->dflag; | |
3b46e624 | 2726 | |
57fec1fe | 2727 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 FB |
2728 | gen_op_addl_A0_im(-opsize); |
2729 | if (!s->ss32) | |
2730 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2731 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 | 2732 | if (s->addseg) |
7162ab21 | 2733 | gen_op_addl_A0_seg(s, R_SS); |
8f091a59 | 2734 | /* push bp */ |
57fec1fe FB |
2735 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2736 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2737 | if (level) { |
b5b38f61 | 2738 | /* XXX: must save state */ |
2999a0b2 | 2739 | gen_helper_enter_level(cpu_env, tcg_const_i32(level), |
a7812ae4 PB |
2740 | tcg_const_i32(s->dflag), |
2741 | cpu_T[1]); | |
8f091a59 | 2742 | } |
57fec1fe | 2743 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2744 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2745 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af | 2746 | } |
2c0262af FB |
2747 | } |
2748 | ||
14ce26e7 | 2749 | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2c0262af | 2750 | { |
773cdfcc | 2751 | gen_update_cc_op(s); |
14ce26e7 | 2752 | gen_jmp_im(cur_eip); |
77b2bc2c | 2753 | gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); |
5779406a | 2754 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2755 | } |
2756 | ||
2757 | /* an interrupt is different from an exception because of the | |
7f75ffd3 | 2758 | privilege checks */ |
5fafdf24 | 2759 | static void gen_interrupt(DisasContext *s, int intno, |
14ce26e7 | 2760 | target_ulong cur_eip, target_ulong next_eip) |
2c0262af | 2761 | { |
773cdfcc | 2762 | gen_update_cc_op(s); |
14ce26e7 | 2763 | gen_jmp_im(cur_eip); |
77b2bc2c | 2764 | gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), |
a7812ae4 | 2765 | tcg_const_i32(next_eip - cur_eip)); |
5779406a | 2766 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2767 | } |
2768 | ||
14ce26e7 | 2769 | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2c0262af | 2770 | { |
773cdfcc | 2771 | gen_update_cc_op(s); |
14ce26e7 | 2772 | gen_jmp_im(cur_eip); |
4a7443be | 2773 | gen_helper_debug(cpu_env); |
5779406a | 2774 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2775 | } |
2776 | ||
2777 | /* generate a generic end of block. Trace exception is also generated | |
2778 | if needed */ | |
2779 | static void gen_eob(DisasContext *s) | |
2780 | { | |
773cdfcc | 2781 | gen_update_cc_op(s); |
a2cc3b24 | 2782 | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { |
f0967a1a | 2783 | gen_helper_reset_inhibit_irq(cpu_env); |
a2cc3b24 | 2784 | } |
a2397807 | 2785 | if (s->tb->flags & HF_RF_MASK) { |
f0967a1a | 2786 | gen_helper_reset_rf(cpu_env); |
a2397807 | 2787 | } |
34865134 | 2788 | if (s->singlestep_enabled) { |
4a7443be | 2789 | gen_helper_debug(cpu_env); |
34865134 | 2790 | } else if (s->tf) { |
4a7443be | 2791 | gen_helper_single_step(cpu_env); |
2c0262af | 2792 | } else { |
57fec1fe | 2793 | tcg_gen_exit_tb(0); |
2c0262af | 2794 | } |
5779406a | 2795 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2796 | } |
2797 | ||
2798 | /* generate a jump to eip. No segment change must happen before as a | |
2799 | direct call to the next block may occur */ | |
14ce26e7 | 2800 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2c0262af | 2801 | { |
2c0262af | 2802 | if (s->jmp_opt) { |
728d803b | 2803 | gen_update_cc_op(s); |
6e256c93 | 2804 | gen_goto_tb(s, tb_num, eip); |
5779406a | 2805 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2806 | } else { |
14ce26e7 | 2807 | gen_jmp_im(eip); |
2c0262af FB |
2808 | gen_eob(s); |
2809 | } | |
2810 | } | |
2811 | ||
14ce26e7 FB |
2812 | static void gen_jmp(DisasContext *s, target_ulong eip) |
2813 | { | |
2814 | gen_jmp_tb(s, eip, 0); | |
2815 | } | |
2816 | ||
8686c490 FB |
2817 | static inline void gen_ldq_env_A0(int idx, int offset) |
2818 | { | |
2819 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2820 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2821 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); | |
8686c490 | 2822 | } |
664e0f19 | 2823 | |
8686c490 FB |
2824 | static inline void gen_stq_env_A0(int idx, int offset) |
2825 | { | |
2826 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2827 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
2828 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2829 | } |
664e0f19 | 2830 | |
8686c490 FB |
2831 | static inline void gen_ldo_env_A0(int idx, int offset) |
2832 | { | |
2833 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2834 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2835 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); | |
8686c490 | 2836 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2837 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2838 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); | |
8686c490 | 2839 | } |
14ce26e7 | 2840 | |
8686c490 FB |
2841 | static inline void gen_sto_env_A0(int idx, int offset) |
2842 | { | |
2843 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2844 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
2845 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2846 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2847 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
2848 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index); | |
8686c490 | 2849 | } |
14ce26e7 | 2850 | |
5af45186 FB |
2851 | static inline void gen_op_movo(int d_offset, int s_offset) |
2852 | { | |
b6abf97d FB |
2853 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2854 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
2855 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8); | |
2856 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8); | |
5af45186 FB |
2857 | } |
2858 | ||
2859 | static inline void gen_op_movq(int d_offset, int s_offset) | |
2860 | { | |
b6abf97d FB |
2861 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2862 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 FB |
2863 | } |
2864 | ||
2865 | static inline void gen_op_movl(int d_offset, int s_offset) | |
2866 | { | |
b6abf97d FB |
2867 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2868 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); | |
5af45186 FB |
2869 | } |
2870 | ||
2871 | static inline void gen_op_movq_env_0(int d_offset) | |
2872 | { | |
b6abf97d FB |
2873 | tcg_gen_movi_i64(cpu_tmp1_i64, 0); |
2874 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 | 2875 | } |
664e0f19 | 2876 | |
d3eb5eae BS |
2877 | typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg); |
2878 | typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg); | |
2879 | typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val); | |
2880 | typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val); | |
2881 | typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b); | |
2882 | typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, | |
2883 | TCGv_i32 val); | |
c4baa050 | 2884 | typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val); |
d3eb5eae BS |
2885 | typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, |
2886 | TCGv val); | |
c4baa050 | 2887 | |
5af45186 FB |
2888 | #define SSE_SPECIAL ((void *)1) |
2889 | #define SSE_DUMMY ((void *)2) | |
664e0f19 | 2890 | |
a7812ae4 PB |
2891 | #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } |
2892 | #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ | |
2893 | gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } | |
5af45186 | 2894 | |
d3eb5eae | 2895 | static const SSEFunc_0_epp sse_op_table1[256][4] = { |
a35f3ec7 AJ |
2896 | /* 3DNow! extensions */ |
2897 | [0x0e] = { SSE_DUMMY }, /* femms */ | |
2898 | [0x0f] = { SSE_DUMMY }, /* pf... */ | |
664e0f19 FB |
2899 | /* pure SSE operations */ |
2900 | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
2901 | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
465e9838 | 2902 | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
664e0f19 | 2903 | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
a7812ae4 PB |
2904 | [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, |
2905 | [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2906 | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2907 | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ | |
2908 | ||
2909 | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2910 | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2911 | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ | |
d9f4bb27 | 2912 | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ |
664e0f19 FB |
2913 | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ |
2914 | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ | |
a7812ae4 PB |
2915 | [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, |
2916 | [0x2f] = { gen_helper_comiss, gen_helper_comisd }, | |
664e0f19 FB |
2917 | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2918 | [0x51] = SSE_FOP(sqrt), | |
a7812ae4 PB |
2919 | [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, |
2920 | [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, | |
2921 | [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ | |
2922 | [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ | |
2923 | [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ | |
2924 | [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ | |
664e0f19 FB |
2925 | [0x58] = SSE_FOP(add), |
2926 | [0x59] = SSE_FOP(mul), | |
a7812ae4 PB |
2927 | [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, |
2928 | gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, | |
2929 | [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, | |
664e0f19 FB |
2930 | [0x5c] = SSE_FOP(sub), |
2931 | [0x5d] = SSE_FOP(min), | |
2932 | [0x5e] = SSE_FOP(div), | |
2933 | [0x5f] = SSE_FOP(max), | |
2934 | ||
2935 | [0xc2] = SSE_FOP(cmpeq), | |
d3eb5eae BS |
2936 | [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps, |
2937 | (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ | |
664e0f19 | 2938 | |
222a3336 AZ |
2939 | [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */ |
2940 | [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */ | |
4242b1bd | 2941 | |
664e0f19 FB |
2942 | /* MMX ops and their SSE extensions */ |
2943 | [0x60] = MMX_OP2(punpcklbw), | |
2944 | [0x61] = MMX_OP2(punpcklwd), | |
2945 | [0x62] = MMX_OP2(punpckldq), | |
2946 | [0x63] = MMX_OP2(packsswb), | |
2947 | [0x64] = MMX_OP2(pcmpgtb), | |
2948 | [0x65] = MMX_OP2(pcmpgtw), | |
2949 | [0x66] = MMX_OP2(pcmpgtl), | |
2950 | [0x67] = MMX_OP2(packuswb), | |
2951 | [0x68] = MMX_OP2(punpckhbw), | |
2952 | [0x69] = MMX_OP2(punpckhwd), | |
2953 | [0x6a] = MMX_OP2(punpckhdq), | |
2954 | [0x6b] = MMX_OP2(packssdw), | |
a7812ae4 PB |
2955 | [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, |
2956 | [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2957 | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2958 | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ | |
d3eb5eae BS |
2959 | [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx, |
2960 | (SSEFunc_0_epp)gen_helper_pshufd_xmm, | |
2961 | (SSEFunc_0_epp)gen_helper_pshufhw_xmm, | |
2962 | (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2963 | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2964 | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ | |
2965 | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ | |
2966 | [0x74] = MMX_OP2(pcmpeqb), | |
2967 | [0x75] = MMX_OP2(pcmpeqw), | |
2968 | [0x76] = MMX_OP2(pcmpeql), | |
a35f3ec7 | 2969 | [0x77] = { SSE_DUMMY }, /* emms */ |
d9f4bb27 AP |
2970 | [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ |
2971 | [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, | |
a7812ae4 PB |
2972 | [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, |
2973 | [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, | |
664e0f19 FB |
2974 | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2975 | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ | |
2976 | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ | |
2977 | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ | |
a7812ae4 | 2978 | [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, |
664e0f19 FB |
2979 | [0xd1] = MMX_OP2(psrlw), |
2980 | [0xd2] = MMX_OP2(psrld), | |
2981 | [0xd3] = MMX_OP2(psrlq), | |
2982 | [0xd4] = MMX_OP2(paddq), | |
2983 | [0xd5] = MMX_OP2(pmullw), | |
2984 | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2985 | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ | |
2986 | [0xd8] = MMX_OP2(psubusb), | |
2987 | [0xd9] = MMX_OP2(psubusw), | |
2988 | [0xda] = MMX_OP2(pminub), | |
2989 | [0xdb] = MMX_OP2(pand), | |
2990 | [0xdc] = MMX_OP2(paddusb), | |
2991 | [0xdd] = MMX_OP2(paddusw), | |
2992 | [0xde] = MMX_OP2(pmaxub), | |
2993 | [0xdf] = MMX_OP2(pandn), | |
2994 | [0xe0] = MMX_OP2(pavgb), | |
2995 | [0xe1] = MMX_OP2(psraw), | |
2996 | [0xe2] = MMX_OP2(psrad), | |
2997 | [0xe3] = MMX_OP2(pavgw), | |
2998 | [0xe4] = MMX_OP2(pmulhuw), | |
2999 | [0xe5] = MMX_OP2(pmulhw), | |
a7812ae4 | 3000 | [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, |
664e0f19 FB |
3001 | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
3002 | [0xe8] = MMX_OP2(psubsb), | |
3003 | [0xe9] = MMX_OP2(psubsw), | |
3004 | [0xea] = MMX_OP2(pminsw), | |
3005 | [0xeb] = MMX_OP2(por), | |
3006 | [0xec] = MMX_OP2(paddsb), | |
3007 | [0xed] = MMX_OP2(paddsw), | |
3008 | [0xee] = MMX_OP2(pmaxsw), | |
3009 | [0xef] = MMX_OP2(pxor), | |
465e9838 | 3010 | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
664e0f19 FB |
3011 | [0xf1] = MMX_OP2(psllw), |
3012 | [0xf2] = MMX_OP2(pslld), | |
3013 | [0xf3] = MMX_OP2(psllq), | |
3014 | [0xf4] = MMX_OP2(pmuludq), | |
3015 | [0xf5] = MMX_OP2(pmaddwd), | |
3016 | [0xf6] = MMX_OP2(psadbw), | |
d3eb5eae BS |
3017 | [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx, |
3018 | (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */ | |
664e0f19 FB |
3019 | [0xf8] = MMX_OP2(psubb), |
3020 | [0xf9] = MMX_OP2(psubw), | |
3021 | [0xfa] = MMX_OP2(psubl), | |
3022 | [0xfb] = MMX_OP2(psubq), | |
3023 | [0xfc] = MMX_OP2(paddb), | |
3024 | [0xfd] = MMX_OP2(paddw), | |
3025 | [0xfe] = MMX_OP2(paddl), | |
3026 | }; | |
3027 | ||
d3eb5eae | 3028 | static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = { |
664e0f19 FB |
3029 | [0 + 2] = MMX_OP2(psrlw), |
3030 | [0 + 4] = MMX_OP2(psraw), | |
3031 | [0 + 6] = MMX_OP2(psllw), | |
3032 | [8 + 2] = MMX_OP2(psrld), | |
3033 | [8 + 4] = MMX_OP2(psrad), | |
3034 | [8 + 6] = MMX_OP2(pslld), | |
3035 | [16 + 2] = MMX_OP2(psrlq), | |
a7812ae4 | 3036 | [16 + 3] = { NULL, gen_helper_psrldq_xmm }, |
664e0f19 | 3037 | [16 + 6] = MMX_OP2(psllq), |
a7812ae4 | 3038 | [16 + 7] = { NULL, gen_helper_pslldq_xmm }, |
664e0f19 FB |
3039 | }; |
3040 | ||
d3eb5eae | 3041 | static const SSEFunc_0_epi sse_op_table3ai[] = { |
a7812ae4 | 3042 | gen_helper_cvtsi2ss, |
11f8cdbc | 3043 | gen_helper_cvtsi2sd |
c4baa050 | 3044 | }; |
a7812ae4 | 3045 | |
11f8cdbc | 3046 | #ifdef TARGET_X86_64 |
d3eb5eae | 3047 | static const SSEFunc_0_epl sse_op_table3aq[] = { |
11f8cdbc SW |
3048 | gen_helper_cvtsq2ss, |
3049 | gen_helper_cvtsq2sd | |
3050 | }; | |
3051 | #endif | |
3052 | ||
d3eb5eae | 3053 | static const SSEFunc_i_ep sse_op_table3bi[] = { |
a7812ae4 | 3054 | gen_helper_cvttss2si, |
a7812ae4 | 3055 | gen_helper_cvtss2si, |
bedc2ac1 | 3056 | gen_helper_cvttsd2si, |
11f8cdbc | 3057 | gen_helper_cvtsd2si |
664e0f19 | 3058 | }; |
3b46e624 | 3059 | |
11f8cdbc | 3060 | #ifdef TARGET_X86_64 |
d3eb5eae | 3061 | static const SSEFunc_l_ep sse_op_table3bq[] = { |
11f8cdbc | 3062 | gen_helper_cvttss2sq, |
11f8cdbc | 3063 | gen_helper_cvtss2sq, |
bedc2ac1 | 3064 | gen_helper_cvttsd2sq, |
11f8cdbc SW |
3065 | gen_helper_cvtsd2sq |
3066 | }; | |
3067 | #endif | |
3068 | ||
d3eb5eae | 3069 | static const SSEFunc_0_epp sse_op_table4[8][4] = { |
664e0f19 FB |
3070 | SSE_FOP(cmpeq), |
3071 | SSE_FOP(cmplt), | |
3072 | SSE_FOP(cmple), | |
3073 | SSE_FOP(cmpunord), | |
3074 | SSE_FOP(cmpneq), | |
3075 | SSE_FOP(cmpnlt), | |
3076 | SSE_FOP(cmpnle), | |
3077 | SSE_FOP(cmpord), | |
3078 | }; | |
3b46e624 | 3079 | |
d3eb5eae | 3080 | static const SSEFunc_0_epp sse_op_table5[256] = { |
a7812ae4 PB |
3081 | [0x0c] = gen_helper_pi2fw, |
3082 | [0x0d] = gen_helper_pi2fd, | |
3083 | [0x1c] = gen_helper_pf2iw, | |
3084 | [0x1d] = gen_helper_pf2id, | |
3085 | [0x8a] = gen_helper_pfnacc, | |
3086 | [0x8e] = gen_helper_pfpnacc, | |
3087 | [0x90] = gen_helper_pfcmpge, | |
3088 | [0x94] = gen_helper_pfmin, | |
3089 | [0x96] = gen_helper_pfrcp, | |
3090 | [0x97] = gen_helper_pfrsqrt, | |
3091 | [0x9a] = gen_helper_pfsub, | |
3092 | [0x9e] = gen_helper_pfadd, | |
3093 | [0xa0] = gen_helper_pfcmpgt, | |
3094 | [0xa4] = gen_helper_pfmax, | |
3095 | [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ | |
3096 | [0xa7] = gen_helper_movq, /* pfrsqit1 */ | |
3097 | [0xaa] = gen_helper_pfsubr, | |
3098 | [0xae] = gen_helper_pfacc, | |
3099 | [0xb0] = gen_helper_pfcmpeq, | |
3100 | [0xb4] = gen_helper_pfmul, | |
3101 | [0xb6] = gen_helper_movq, /* pfrcpit2 */ | |
3102 | [0xb7] = gen_helper_pmulhrw_mmx, | |
3103 | [0xbb] = gen_helper_pswapd, | |
3104 | [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ | |
a35f3ec7 AJ |
3105 | }; |
3106 | ||
d3eb5eae BS |
3107 | struct SSEOpHelper_epp { |
3108 | SSEFunc_0_epp op[2]; | |
c4baa050 BS |
3109 | uint32_t ext_mask; |
3110 | }; | |
3111 | ||
d3eb5eae BS |
3112 | struct SSEOpHelper_eppi { |
3113 | SSEFunc_0_eppi op[2]; | |
c4baa050 | 3114 | uint32_t ext_mask; |
222a3336 | 3115 | }; |
c4baa050 | 3116 | |
222a3336 | 3117 | #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 } |
a7812ae4 PB |
3118 | #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } |
3119 | #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } | |
222a3336 | 3120 | #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } |
c4baa050 | 3121 | |
d3eb5eae | 3122 | static const struct SSEOpHelper_epp sse_op_table6[256] = { |
222a3336 AZ |
3123 | [0x00] = SSSE3_OP(pshufb), |
3124 | [0x01] = SSSE3_OP(phaddw), | |
3125 | [0x02] = SSSE3_OP(phaddd), | |
3126 | [0x03] = SSSE3_OP(phaddsw), | |
3127 | [0x04] = SSSE3_OP(pmaddubsw), | |
3128 | [0x05] = SSSE3_OP(phsubw), | |
3129 | [0x06] = SSSE3_OP(phsubd), | |
3130 | [0x07] = SSSE3_OP(phsubsw), | |
3131 | [0x08] = SSSE3_OP(psignb), | |
3132 | [0x09] = SSSE3_OP(psignw), | |
3133 | [0x0a] = SSSE3_OP(psignd), | |
3134 | [0x0b] = SSSE3_OP(pmulhrsw), | |
3135 | [0x10] = SSE41_OP(pblendvb), | |
3136 | [0x14] = SSE41_OP(blendvps), | |
3137 | [0x15] = SSE41_OP(blendvpd), | |
3138 | [0x17] = SSE41_OP(ptest), | |
3139 | [0x1c] = SSSE3_OP(pabsb), | |
3140 | [0x1d] = SSSE3_OP(pabsw), | |
3141 | [0x1e] = SSSE3_OP(pabsd), | |
3142 | [0x20] = SSE41_OP(pmovsxbw), | |
3143 | [0x21] = SSE41_OP(pmovsxbd), | |
3144 | [0x22] = SSE41_OP(pmovsxbq), | |
3145 | [0x23] = SSE41_OP(pmovsxwd), | |
3146 | [0x24] = SSE41_OP(pmovsxwq), | |
3147 | [0x25] = SSE41_OP(pmovsxdq), | |
3148 | [0x28] = SSE41_OP(pmuldq), | |
3149 | [0x29] = SSE41_OP(pcmpeqq), | |
3150 | [0x2a] = SSE41_SPECIAL, /* movntqda */ | |
3151 | [0x2b] = SSE41_OP(packusdw), | |
3152 | [0x30] = SSE41_OP(pmovzxbw), | |
3153 | [0x31] = SSE41_OP(pmovzxbd), | |
3154 | [0x32] = SSE41_OP(pmovzxbq), | |
3155 | [0x33] = SSE41_OP(pmovzxwd), | |
3156 | [0x34] = SSE41_OP(pmovzxwq), | |
3157 | [0x35] = SSE41_OP(pmovzxdq), | |
3158 | [0x37] = SSE42_OP(pcmpgtq), | |
3159 | [0x38] = SSE41_OP(pminsb), | |
3160 | [0x39] = SSE41_OP(pminsd), | |
3161 | [0x3a] = SSE41_OP(pminuw), | |
3162 | [0x3b] = SSE41_OP(pminud), | |
3163 | [0x3c] = SSE41_OP(pmaxsb), | |
3164 | [0x3d] = SSE41_OP(pmaxsd), | |
3165 | [0x3e] = SSE41_OP(pmaxuw), | |
3166 | [0x3f] = SSE41_OP(pmaxud), | |
3167 | [0x40] = SSE41_OP(pmulld), | |
3168 | [0x41] = SSE41_OP(phminposuw), | |
4242b1bd AZ |
3169 | }; |
3170 | ||
d3eb5eae | 3171 | static const struct SSEOpHelper_eppi sse_op_table7[256] = { |
222a3336 AZ |
3172 | [0x08] = SSE41_OP(roundps), |
3173 | [0x09] = SSE41_OP(roundpd), | |
3174 | [0x0a] = SSE41_OP(roundss), | |
3175 | [0x0b] = SSE41_OP(roundsd), | |
3176 | [0x0c] = SSE41_OP(blendps), | |
3177 | [0x0d] = SSE41_OP(blendpd), | |
3178 | [0x0e] = SSE41_OP(pblendw), | |
3179 | [0x0f] = SSSE3_OP(palignr), | |
3180 | [0x14] = SSE41_SPECIAL, /* pextrb */ | |
3181 | [0x15] = SSE41_SPECIAL, /* pextrw */ | |
3182 | [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ | |
3183 | [0x17] = SSE41_SPECIAL, /* extractps */ | |
3184 | [0x20] = SSE41_SPECIAL, /* pinsrb */ | |
3185 | [0x21] = SSE41_SPECIAL, /* insertps */ | |
3186 | [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ | |
3187 | [0x40] = SSE41_OP(dpps), | |
3188 | [0x41] = SSE41_OP(dppd), | |
3189 | [0x42] = SSE41_OP(mpsadbw), | |
3190 | [0x60] = SSE42_OP(pcmpestrm), | |
3191 | [0x61] = SSE42_OP(pcmpestri), | |
3192 | [0x62] = SSE42_OP(pcmpistrm), | |
3193 | [0x63] = SSE42_OP(pcmpistri), | |
4242b1bd AZ |
3194 | }; |
3195 | ||
0af10c86 BS |
3196 | static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
3197 | target_ulong pc_start, int rex_r) | |
664e0f19 FB |
3198 | { |
3199 | int b1, op1_offset, op2_offset, is_xmm, val, ot; | |
3200 | int modrm, mod, rm, reg, reg_addr, offset_addr; | |
d3eb5eae BS |
3201 | SSEFunc_0_epp sse_fn_epp; |
3202 | SSEFunc_0_eppi sse_fn_eppi; | |
c4baa050 | 3203 | SSEFunc_0_ppi sse_fn_ppi; |
d3eb5eae | 3204 | SSEFunc_0_eppt sse_fn_eppt; |
664e0f19 FB |
3205 | |
3206 | b &= 0xff; | |
5fafdf24 | 3207 | if (s->prefix & PREFIX_DATA) |
664e0f19 | 3208 | b1 = 1; |
5fafdf24 | 3209 | else if (s->prefix & PREFIX_REPZ) |
664e0f19 | 3210 | b1 = 2; |
5fafdf24 | 3211 | else if (s->prefix & PREFIX_REPNZ) |
664e0f19 FB |
3212 | b1 = 3; |
3213 | else | |
3214 | b1 = 0; | |
d3eb5eae BS |
3215 | sse_fn_epp = sse_op_table1[b][b1]; |
3216 | if (!sse_fn_epp) { | |
664e0f19 | 3217 | goto illegal_op; |
c4baa050 | 3218 | } |
a35f3ec7 | 3219 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
664e0f19 FB |
3220 | is_xmm = 1; |
3221 | } else { | |
3222 | if (b1 == 0) { | |
3223 | /* MMX case */ | |
3224 | is_xmm = 0; | |
3225 | } else { | |
3226 | is_xmm = 1; | |
3227 | } | |
3228 | } | |
3229 | /* simple MMX/SSE operation */ | |
3230 | if (s->flags & HF_TS_MASK) { | |
3231 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
3232 | return; | |
3233 | } | |
3234 | if (s->flags & HF_EM_MASK) { | |
3235 | illegal_op: | |
3236 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
3237 | return; | |
3238 | } | |
3239 | if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) | |
4242b1bd AZ |
3240 | if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) |
3241 | goto illegal_op; | |
e771edab AJ |
3242 | if (b == 0x0e) { |
3243 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) | |
3244 | goto illegal_op; | |
3245 | /* femms */ | |
d3eb5eae | 3246 | gen_helper_emms(cpu_env); |
e771edab AJ |
3247 | return; |
3248 | } | |
3249 | if (b == 0x77) { | |
3250 | /* emms */ | |
d3eb5eae | 3251 | gen_helper_emms(cpu_env); |
664e0f19 FB |
3252 | return; |
3253 | } | |
3254 | /* prepare MMX state (XXX: optimize by storing fptt and fptags in | |
3255 | the static cpu state) */ | |
3256 | if (!is_xmm) { | |
d3eb5eae | 3257 | gen_helper_enter_mmx(cpu_env); |
664e0f19 FB |
3258 | } |
3259 | ||
0af10c86 | 3260 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3261 | reg = ((modrm >> 3) & 7); |
3262 | if (is_xmm) | |
3263 | reg |= rex_r; | |
3264 | mod = (modrm >> 6) & 3; | |
d3eb5eae | 3265 | if (sse_fn_epp == SSE_SPECIAL) { |
664e0f19 FB |
3266 | b |= (b1 << 8); |
3267 | switch(b) { | |
3268 | case 0x0e7: /* movntq */ | |
5fafdf24 | 3269 | if (mod == 3) |
664e0f19 | 3270 | goto illegal_op; |
0af10c86 | 3271 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3272 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3273 | break; |
3274 | case 0x1e7: /* movntdq */ | |
3275 | case 0x02b: /* movntps */ | |
3276 | case 0x12b: /* movntps */ | |
2e21e749 T |
3277 | if (mod == 3) |
3278 | goto illegal_op; | |
0af10c86 | 3279 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2e21e749 T |
3280 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3281 | break; | |
465e9838 FB |
3282 | case 0x3f0: /* lddqu */ |
3283 | if (mod == 3) | |
664e0f19 | 3284 | goto illegal_op; |
0af10c86 | 3285 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
c2254920 | 3286 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 | 3287 | break; |
d9f4bb27 AP |
3288 | case 0x22b: /* movntss */ |
3289 | case 0x32b: /* movntsd */ | |
3290 | if (mod == 3) | |
3291 | goto illegal_op; | |
0af10c86 | 3292 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
d9f4bb27 AP |
3293 | if (b1 & 1) { |
3294 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State, | |
3295 | xmm_regs[reg])); | |
3296 | } else { | |
3297 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3298 | xmm_regs[reg].XMM_L(0))); | |
3299 | gen_op_st_T0_A0(OT_LONG + s->mem_index); | |
3300 | } | |
3301 | break; | |
664e0f19 | 3302 | case 0x6e: /* movd mm, ea */ |
dabd98dd FB |
3303 | #ifdef TARGET_X86_64 |
3304 | if (s->dflag == 2) { | |
0af10c86 | 3305 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0); |
5af45186 | 3306 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); |
5fafdf24 | 3307 | } else |
dabd98dd FB |
3308 | #endif |
3309 | { | |
0af10c86 | 3310 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0); |
5af45186 FB |
3311 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3312 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
a7812ae4 PB |
3313 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3314 | gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); | |
dabd98dd | 3315 | } |
664e0f19 FB |
3316 | break; |
3317 | case 0x16e: /* movd xmm, ea */ | |
dabd98dd FB |
3318 | #ifdef TARGET_X86_64 |
3319 | if (s->dflag == 2) { | |
0af10c86 | 3320 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0); |
5af45186 FB |
3321 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3322 | offsetof(CPUX86State,xmm_regs[reg])); | |
a7812ae4 | 3323 | gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); |
5fafdf24 | 3324 | } else |
dabd98dd FB |
3325 | #endif |
3326 | { | |
0af10c86 | 3327 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0); |
5af45186 FB |
3328 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3329 | offsetof(CPUX86State,xmm_regs[reg])); | |
b6abf97d | 3330 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 3331 | gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); |
dabd98dd | 3332 | } |
664e0f19 FB |
3333 | break; |
3334 | case 0x6f: /* movq mm, ea */ | |
3335 | if (mod != 3) { | |
0af10c86 | 3336 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3337 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3338 | } else { |
3339 | rm = (modrm & 7); | |
b6abf97d | 3340 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3341 | offsetof(CPUX86State,fpregs[rm].mmx)); |
b6abf97d | 3342 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3343 | offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3344 | } |
3345 | break; | |
3346 | case 0x010: /* movups */ | |
3347 | case 0x110: /* movupd */ | |
3348 | case 0x028: /* movaps */ | |
3349 | case 0x128: /* movapd */ | |
3350 | case 0x16f: /* movdqa xmm, ea */ | |
3351 | case 0x26f: /* movdqu xmm, ea */ | |
3352 | if (mod != 3) { | |
0af10c86 | 3353 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3354 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3355 | } else { |
3356 | rm = (modrm & 7) | REX_B(s); | |
3357 | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), | |
3358 | offsetof(CPUX86State,xmm_regs[rm])); | |
3359 | } | |
3360 | break; | |
3361 | case 0x210: /* movss xmm, ea */ | |
3362 | if (mod != 3) { | |
0af10c86 | 3363 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 3364 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3365 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
664e0f19 | 3366 | gen_op_movl_T0_0(); |
651ba608 FB |
3367 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); |
3368 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3369 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3370 | } else { |
3371 | rm = (modrm & 7) | REX_B(s); | |
3372 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3373 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3374 | } | |
3375 | break; | |
3376 | case 0x310: /* movsd xmm, ea */ | |
3377 | if (mod != 3) { | |
0af10c86 | 3378 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3379 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 | 3380 | gen_op_movl_T0_0(); |
651ba608 FB |
3381 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3382 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3383 | } else { |
3384 | rm = (modrm & 7) | REX_B(s); | |
3385 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3386 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3387 | } | |
3388 | break; | |
3389 | case 0x012: /* movlps */ | |
3390 | case 0x112: /* movlpd */ | |
3391 | if (mod != 3) { | |
0af10c86 | 3392 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3393 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3394 | } else { |
3395 | /* movhlps */ | |
3396 | rm = (modrm & 7) | REX_B(s); | |
3397 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3398 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3399 | } | |
3400 | break; | |
465e9838 FB |
3401 | case 0x212: /* movsldup */ |
3402 | if (mod != 3) { | |
0af10c86 | 3403 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3404 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
465e9838 FB |
3405 | } else { |
3406 | rm = (modrm & 7) | REX_B(s); | |
3407 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3408 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3409 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3410 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); | |
3411 | } | |
3412 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3413 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3414 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3415 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3416 | break; | |
3417 | case 0x312: /* movddup */ | |
3418 | if (mod != 3) { | |
0af10c86 | 3419 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3420 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 FB |
3421 | } else { |
3422 | rm = (modrm & 7) | REX_B(s); | |
3423 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3424 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3425 | } | |
3426 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
ba6526df | 3427 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 | 3428 | break; |
664e0f19 FB |
3429 | case 0x016: /* movhps */ |
3430 | case 0x116: /* movhpd */ | |
3431 | if (mod != 3) { | |
0af10c86 | 3432 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3433 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3434 | } else { |
3435 | /* movlhps */ | |
3436 | rm = (modrm & 7) | REX_B(s); | |
3437 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
3438 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3439 | } | |
3440 | break; | |
3441 | case 0x216: /* movshdup */ | |
3442 | if (mod != 3) { | |
0af10c86 | 3443 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3444 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3445 | } else { |
3446 | rm = (modrm & 7) | REX_B(s); | |
3447 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3448 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); | |
3449 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3450 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); | |
3451 | } | |
3452 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3453 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); | |
3454 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3455 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
3456 | break; | |
d9f4bb27 AP |
3457 | case 0x178: |
3458 | case 0x378: | |
3459 | { | |
3460 | int bit_index, field_length; | |
3461 | ||
3462 | if (b1 == 1 && reg != 0) | |
3463 | goto illegal_op; | |
0af10c86 BS |
3464 | field_length = cpu_ldub_code(env, s->pc++) & 0x3F; |
3465 | bit_index = cpu_ldub_code(env, s->pc++) & 0x3F; | |
d9f4bb27 AP |
3466 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3467 | offsetof(CPUX86State,xmm_regs[reg])); | |
3468 | if (b1 == 1) | |
d3eb5eae BS |
3469 | gen_helper_extrq_i(cpu_env, cpu_ptr0, |
3470 | tcg_const_i32(bit_index), | |
3471 | tcg_const_i32(field_length)); | |
d9f4bb27 | 3472 | else |
d3eb5eae BS |
3473 | gen_helper_insertq_i(cpu_env, cpu_ptr0, |
3474 | tcg_const_i32(bit_index), | |
3475 | tcg_const_i32(field_length)); | |
d9f4bb27 AP |
3476 | } |
3477 | break; | |
664e0f19 | 3478 | case 0x7e: /* movd ea, mm */ |
dabd98dd FB |
3479 | #ifdef TARGET_X86_64 |
3480 | if (s->dflag == 2) { | |
5af45186 FB |
3481 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3482 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
0af10c86 | 3483 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3484 | } else |
dabd98dd FB |
3485 | #endif |
3486 | { | |
5af45186 FB |
3487 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3488 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); | |
0af10c86 | 3489 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1); |
dabd98dd | 3490 | } |
664e0f19 FB |
3491 | break; |
3492 | case 0x17e: /* movd ea, xmm */ | |
dabd98dd FB |
3493 | #ifdef TARGET_X86_64 |
3494 | if (s->dflag == 2) { | |
5af45186 FB |
3495 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3496 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
0af10c86 | 3497 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3498 | } else |
dabd98dd FB |
3499 | #endif |
3500 | { | |
5af45186 FB |
3501 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3502 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
0af10c86 | 3503 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1); |
dabd98dd | 3504 | } |
664e0f19 FB |
3505 | break; |
3506 | case 0x27e: /* movq xmm, ea */ | |
3507 | if (mod != 3) { | |
0af10c86 | 3508 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3509 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3510 | } else { |
3511 | rm = (modrm & 7) | REX_B(s); | |
3512 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3513 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3514 | } | |
3515 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
3516 | break; | |
3517 | case 0x7f: /* movq ea, mm */ | |
3518 | if (mod != 3) { | |
0af10c86 | 3519 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3520 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3521 | } else { |
3522 | rm = (modrm & 7); | |
3523 | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), | |
3524 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
3525 | } | |
3526 | break; | |
3527 | case 0x011: /* movups */ | |
3528 | case 0x111: /* movupd */ | |
3529 | case 0x029: /* movaps */ | |
3530 | case 0x129: /* movapd */ | |
3531 | case 0x17f: /* movdqa ea, xmm */ | |
3532 | case 0x27f: /* movdqu ea, xmm */ | |
3533 | if (mod != 3) { | |
0af10c86 | 3534 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3535 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3536 | } else { |
3537 | rm = (modrm & 7) | REX_B(s); | |
3538 | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), | |
3539 | offsetof(CPUX86State,xmm_regs[reg])); | |
3540 | } | |
3541 | break; | |
3542 | case 0x211: /* movss ea, xmm */ | |
3543 | if (mod != 3) { | |
0af10c86 | 3544 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
651ba608 | 3545 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
57fec1fe | 3546 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
664e0f19 FB |
3547 | } else { |
3548 | rm = (modrm & 7) | REX_B(s); | |
3549 | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), | |
3550 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3551 | } | |
3552 | break; | |
3553 | case 0x311: /* movsd ea, xmm */ | |
3554 | if (mod != 3) { | |
0af10c86 | 3555 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3556 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3557 | } else { |
3558 | rm = (modrm & 7) | REX_B(s); | |
3559 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3560 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3561 | } | |
3562 | break; | |
3563 | case 0x013: /* movlps */ | |
3564 | case 0x113: /* movlpd */ | |
3565 | if (mod != 3) { | |
0af10c86 | 3566 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3567 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3568 | } else { |
3569 | goto illegal_op; | |
3570 | } | |
3571 | break; | |
3572 | case 0x017: /* movhps */ | |
3573 | case 0x117: /* movhpd */ | |
3574 | if (mod != 3) { | |
0af10c86 | 3575 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3576 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3577 | } else { |
3578 | goto illegal_op; | |
3579 | } | |
3580 | break; | |
3581 | case 0x71: /* shift mm, im */ | |
3582 | case 0x72: | |
3583 | case 0x73: | |
3584 | case 0x171: /* shift xmm, im */ | |
3585 | case 0x172: | |
3586 | case 0x173: | |
c045af25 AK |
3587 | if (b1 >= 2) { |
3588 | goto illegal_op; | |
3589 | } | |
0af10c86 | 3590 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3591 | if (is_xmm) { |
3592 | gen_op_movl_T0_im(val); | |
651ba608 | 3593 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 | 3594 | gen_op_movl_T0_0(); |
651ba608 | 3595 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); |
664e0f19 FB |
3596 | op1_offset = offsetof(CPUX86State,xmm_t0); |
3597 | } else { | |
3598 | gen_op_movl_T0_im(val); | |
651ba608 | 3599 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); |
664e0f19 | 3600 | gen_op_movl_T0_0(); |
651ba608 | 3601 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); |
664e0f19 FB |
3602 | op1_offset = offsetof(CPUX86State,mmx_t0); |
3603 | } | |
d3eb5eae BS |
3604 | sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + |
3605 | (((modrm >> 3)) & 7)][b1]; | |
3606 | if (!sse_fn_epp) { | |
664e0f19 | 3607 | goto illegal_op; |
c4baa050 | 3608 | } |
664e0f19 FB |
3609 | if (is_xmm) { |
3610 | rm = (modrm & 7) | REX_B(s); | |
3611 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3612 | } else { | |
3613 | rm = (modrm & 7); | |
3614 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3615 | } | |
5af45186 FB |
3616 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3617 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); | |
d3eb5eae | 3618 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3619 | break; |
3620 | case 0x050: /* movmskps */ | |
664e0f19 | 3621 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3622 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3623 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3624 | gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3625 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3626 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3627 | break; |
3628 | case 0x150: /* movmskpd */ | |
664e0f19 | 3629 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3630 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3631 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3632 | gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3633 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3634 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3635 | break; |
3636 | case 0x02a: /* cvtpi2ps */ | |
3637 | case 0x12a: /* cvtpi2pd */ | |
d3eb5eae | 3638 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3639 | if (mod != 3) { |
0af10c86 | 3640 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 3641 | op2_offset = offsetof(CPUX86State,mmx_t0); |
8686c490 | 3642 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3643 | } else { |
3644 | rm = (modrm & 7); | |
3645 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3646 | } | |
3647 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3648 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3649 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3650 | switch(b >> 8) { |
3651 | case 0x0: | |
d3eb5eae | 3652 | gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3653 | break; |
3654 | default: | |
3655 | case 0x1: | |
d3eb5eae | 3656 | gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3657 | break; |
3658 | } | |
3659 | break; | |
3660 | case 0x22a: /* cvtsi2ss */ | |
3661 | case 0x32a: /* cvtsi2sd */ | |
3662 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
0af10c86 | 3663 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
664e0f19 | 3664 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
5af45186 | 3665 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
28e10711 | 3666 | if (ot == OT_LONG) { |
d3eb5eae | 3667 | SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1]; |
28e10711 | 3668 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 3669 | sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32); |
28e10711 | 3670 | } else { |
11f8cdbc | 3671 | #ifdef TARGET_X86_64 |
d3eb5eae BS |
3672 | SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1]; |
3673 | sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]); | |
11f8cdbc SW |
3674 | #else |
3675 | goto illegal_op; | |
3676 | #endif | |
28e10711 | 3677 | } |
664e0f19 FB |
3678 | break; |
3679 | case 0x02c: /* cvttps2pi */ | |
3680 | case 0x12c: /* cvttpd2pi */ | |
3681 | case 0x02d: /* cvtps2pi */ | |
3682 | case 0x12d: /* cvtpd2pi */ | |
d3eb5eae | 3683 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3684 | if (mod != 3) { |
0af10c86 | 3685 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 3686 | op2_offset = offsetof(CPUX86State,xmm_t0); |
8686c490 | 3687 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3688 | } else { |
3689 | rm = (modrm & 7) | REX_B(s); | |
3690 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3691 | } | |
3692 | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx); | |
5af45186 FB |
3693 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3694 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3695 | switch(b) { |
3696 | case 0x02c: | |
d3eb5eae | 3697 | gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3698 | break; |
3699 | case 0x12c: | |
d3eb5eae | 3700 | gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3701 | break; |
3702 | case 0x02d: | |
d3eb5eae | 3703 | gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3704 | break; |
3705 | case 0x12d: | |
d3eb5eae | 3706 | gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3707 | break; |
3708 | } | |
3709 | break; | |
3710 | case 0x22c: /* cvttss2si */ | |
3711 | case 0x32c: /* cvttsd2si */ | |
3712 | case 0x22d: /* cvtss2si */ | |
3713 | case 0x32d: /* cvtsd2si */ | |
3714 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
31313213 | 3715 | if (mod != 3) { |
0af10c86 | 3716 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
31313213 | 3717 | if ((b >> 8) & 1) { |
8686c490 | 3718 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))); |
31313213 | 3719 | } else { |
57fec1fe | 3720 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3721 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
31313213 FB |
3722 | } |
3723 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3724 | } else { | |
3725 | rm = (modrm & 7) | REX_B(s); | |
3726 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3727 | } | |
5af45186 FB |
3728 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3729 | if (ot == OT_LONG) { | |
d3eb5eae | 3730 | SSEFunc_i_ep sse_fn_i_ep = |
bedc2ac1 | 3731 | sse_op_table3bi[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3732 | sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3733 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
5af45186 | 3734 | } else { |
11f8cdbc | 3735 | #ifdef TARGET_X86_64 |
d3eb5eae | 3736 | SSEFunc_l_ep sse_fn_l_ep = |
bedc2ac1 | 3737 | sse_op_table3bq[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3738 | sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0); |
11f8cdbc SW |
3739 | #else |
3740 | goto illegal_op; | |
3741 | #endif | |
5af45186 | 3742 | } |
57fec1fe | 3743 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3744 | break; |
3745 | case 0xc4: /* pinsrw */ | |
5fafdf24 | 3746 | case 0x1c4: |
d1e42c5c | 3747 | s->rip_offset = 1; |
0af10c86 BS |
3748 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
3749 | val = cpu_ldub_code(env, s->pc++); | |
664e0f19 FB |
3750 | if (b1) { |
3751 | val &= 7; | |
5af45186 FB |
3752 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3753 | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); | |
664e0f19 FB |
3754 | } else { |
3755 | val &= 3; | |
5af45186 FB |
3756 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3757 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); | |
664e0f19 FB |
3758 | } |
3759 | break; | |
3760 | case 0xc5: /* pextrw */ | |
5fafdf24 | 3761 | case 0x1c5: |
664e0f19 FB |
3762 | if (mod != 3) |
3763 | goto illegal_op; | |
6dc2d0da | 3764 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
0af10c86 | 3765 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3766 | if (b1) { |
3767 | val &= 7; | |
3768 | rm = (modrm & 7) | REX_B(s); | |
5af45186 FB |
3769 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3770 | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); | |
664e0f19 FB |
3771 | } else { |
3772 | val &= 3; | |
3773 | rm = (modrm & 7); | |
5af45186 FB |
3774 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3775 | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); | |
664e0f19 FB |
3776 | } |
3777 | reg = ((modrm >> 3) & 7) | rex_r; | |
6dc2d0da | 3778 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3779 | break; |
3780 | case 0x1d6: /* movq ea, xmm */ | |
3781 | if (mod != 3) { | |
0af10c86 | 3782 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3783 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3784 | } else { |
3785 | rm = (modrm & 7) | REX_B(s); | |
3786 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3787 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3788 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3789 | } | |
3790 | break; | |
3791 | case 0x2d6: /* movq2dq */ | |
d3eb5eae | 3792 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3793 | rm = (modrm & 7); |
3794 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3795 | offsetof(CPUX86State,fpregs[rm].mmx)); | |
3796 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3797 | break; |
3798 | case 0x3d6: /* movdq2q */ | |
d3eb5eae | 3799 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3800 | rm = (modrm & 7) | REX_B(s); |
3801 | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), | |
3802 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
664e0f19 FB |
3803 | break; |
3804 | case 0xd7: /* pmovmskb */ | |
3805 | case 0x1d7: | |
3806 | if (mod != 3) | |
3807 | goto illegal_op; | |
3808 | if (b1) { | |
3809 | rm = (modrm & 7) | REX_B(s); | |
5af45186 | 3810 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
d3eb5eae | 3811 | gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 FB |
3812 | } else { |
3813 | rm = (modrm & 7); | |
5af45186 | 3814 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
d3eb5eae | 3815 | gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 | 3816 | } |
b6abf97d | 3817 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
664e0f19 | 3818 | reg = ((modrm >> 3) & 7) | rex_r; |
57fec1fe | 3819 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 | 3820 | break; |
4242b1bd | 3821 | case 0x138: |
000cacf6 AZ |
3822 | if (s->prefix & PREFIX_REPNZ) |
3823 | goto crc32; | |
3824 | case 0x038: | |
4242b1bd | 3825 | b = modrm; |
0af10c86 | 3826 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
3827 | rm = modrm & 7; |
3828 | reg = ((modrm >> 3) & 7) | rex_r; | |
3829 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3830 | if (b1 >= 2) { |
3831 | goto illegal_op; | |
3832 | } | |
4242b1bd | 3833 | |
d3eb5eae BS |
3834 | sse_fn_epp = sse_op_table6[b].op[b1]; |
3835 | if (!sse_fn_epp) { | |
4242b1bd | 3836 | goto illegal_op; |
c4baa050 | 3837 | } |
222a3336 AZ |
3838 | if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask)) |
3839 | goto illegal_op; | |
4242b1bd AZ |
3840 | |
3841 | if (b1) { | |
3842 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3843 | if (mod == 3) { | |
3844 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3845 | } else { | |
3846 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
0af10c86 | 3847 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
222a3336 AZ |
3848 | switch (b) { |
3849 | case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ | |
3850 | case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ | |
3851 | case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ | |
3852 | gen_ldq_env_A0(s->mem_index, op2_offset + | |
3853 | offsetof(XMMReg, XMM_Q(0))); | |
3854 | break; | |
3855 | case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ | |
3856 | case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ | |
a7812ae4 | 3857 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3858 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3859 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3860 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + |
3861 | offsetof(XMMReg, XMM_L(0))); | |
3862 | break; | |
3863 | case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ | |
3864 | tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, | |
3865 | (s->mem_index >> 2) - 1); | |
3866 | tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + | |
3867 | offsetof(XMMReg, XMM_W(0))); | |
3868 | break; | |
3869 | case 0x2a: /* movntqda */ | |
3870 | gen_ldo_env_A0(s->mem_index, op1_offset); | |
3871 | return; | |
3872 | default: | |
3873 | gen_ldo_env_A0(s->mem_index, op2_offset); | |
3874 | } | |
4242b1bd AZ |
3875 | } |
3876 | } else { | |
3877 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3878 | if (mod == 3) { | |
3879 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3880 | } else { | |
3881 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
0af10c86 | 3882 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4242b1bd AZ |
3883 | gen_ldq_env_A0(s->mem_index, op2_offset); |
3884 | } | |
3885 | } | |
d3eb5eae | 3886 | if (sse_fn_epp == SSE_SPECIAL) { |
222a3336 | 3887 | goto illegal_op; |
c4baa050 | 3888 | } |
222a3336 | 3889 | |
4242b1bd AZ |
3890 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3891 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 3892 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
222a3336 | 3893 | |
3ca51d07 RH |
3894 | if (b == 0x17) { |
3895 | set_cc_op(s, CC_OP_EFLAGS); | |
3896 | } | |
4242b1bd | 3897 | break; |
222a3336 AZ |
3898 | case 0x338: /* crc32 */ |
3899 | crc32: | |
3900 | b = modrm; | |
0af10c86 | 3901 | modrm = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
3902 | reg = ((modrm >> 3) & 7) | rex_r; |
3903 | ||
3904 | if (b != 0xf0 && b != 0xf1) | |
3905 | goto illegal_op; | |
3906 | if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) | |
4242b1bd AZ |
3907 | goto illegal_op; |
3908 | ||
222a3336 AZ |
3909 | if (b == 0xf0) |
3910 | ot = OT_BYTE; | |
3911 | else if (b == 0xf1 && s->dflag != 2) | |
3912 | if (s->prefix & PREFIX_DATA) | |
3913 | ot = OT_WORD; | |
3914 | else | |
3915 | ot = OT_LONG; | |
3916 | else | |
3917 | ot = OT_QUAD; | |
3918 | ||
3919 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
3920 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
0af10c86 | 3921 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
a7812ae4 PB |
3922 | gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, |
3923 | cpu_T[0], tcg_const_i32(8 << ot)); | |
222a3336 AZ |
3924 | |
3925 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3926 | gen_op_mov_reg_T0(ot, reg); | |
3927 | break; | |
3928 | case 0x03a: | |
3929 | case 0x13a: | |
4242b1bd | 3930 | b = modrm; |
0af10c86 | 3931 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
3932 | rm = modrm & 7; |
3933 | reg = ((modrm >> 3) & 7) | rex_r; | |
3934 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3935 | if (b1 >= 2) { |
3936 | goto illegal_op; | |
3937 | } | |
4242b1bd | 3938 | |
d3eb5eae BS |
3939 | sse_fn_eppi = sse_op_table7[b].op[b1]; |
3940 | if (!sse_fn_eppi) { | |
4242b1bd | 3941 | goto illegal_op; |
c4baa050 | 3942 | } |
222a3336 AZ |
3943 | if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) |
3944 | goto illegal_op; | |
3945 | ||
d3eb5eae | 3946 | if (sse_fn_eppi == SSE_SPECIAL) { |
222a3336 AZ |
3947 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
3948 | rm = (modrm & 7) | REX_B(s); | |
3949 | if (mod != 3) | |
0af10c86 | 3950 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
222a3336 | 3951 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 3952 | val = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
3953 | switch (b) { |
3954 | case 0x14: /* pextrb */ | |
3955 | tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3956 | xmm_regs[reg].XMM_B(val & 15))); | |
3957 | if (mod == 3) | |
3958 | gen_op_mov_reg_T0(ot, rm); | |
3959 | else | |
3960 | tcg_gen_qemu_st8(cpu_T[0], cpu_A0, | |
3961 | (s->mem_index >> 2) - 1); | |
3962 | break; | |
3963 | case 0x15: /* pextrw */ | |
3964 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3965 | xmm_regs[reg].XMM_W(val & 7))); | |
3966 | if (mod == 3) | |
3967 | gen_op_mov_reg_T0(ot, rm); | |
3968 | else | |
3969 | tcg_gen_qemu_st16(cpu_T[0], cpu_A0, | |
3970 | (s->mem_index >> 2) - 1); | |
3971 | break; | |
3972 | case 0x16: | |
3973 | if (ot == OT_LONG) { /* pextrd */ | |
3974 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, | |
3975 | offsetof(CPUX86State, | |
3976 | xmm_regs[reg].XMM_L(val & 3))); | |
a7812ae4 | 3977 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
222a3336 | 3978 | if (mod == 3) |
a7812ae4 | 3979 | gen_op_mov_reg_v(ot, rm, cpu_T[0]); |
222a3336 | 3980 | else |
a7812ae4 | 3981 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, |
222a3336 AZ |
3982 | (s->mem_index >> 2) - 1); |
3983 | } else { /* pextrq */ | |
a7812ae4 | 3984 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3985 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
3986 | offsetof(CPUX86State, | |
3987 | xmm_regs[reg].XMM_Q(val & 1))); | |
3988 | if (mod == 3) | |
3989 | gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); | |
3990 | else | |
3991 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, | |
3992 | (s->mem_index >> 2) - 1); | |
a7812ae4 PB |
3993 | #else |
3994 | goto illegal_op; | |
3995 | #endif | |
222a3336 AZ |
3996 | } |
3997 | break; | |
3998 | case 0x17: /* extractps */ | |
3999 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
4000 | xmm_regs[reg].XMM_L(val & 3))); | |
4001 | if (mod == 3) | |
4002 | gen_op_mov_reg_T0(ot, rm); | |
4003 | else | |
4004 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, | |
4005 | (s->mem_index >> 2) - 1); | |
4006 | break; | |
4007 | case 0x20: /* pinsrb */ | |
4008 | if (mod == 3) | |
4009 | gen_op_mov_TN_reg(OT_LONG, 0, rm); | |
4010 | else | |
a7812ae4 | 4011 | tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0, |
222a3336 | 4012 | (s->mem_index >> 2) - 1); |
a7812ae4 | 4013 | tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, |
222a3336 AZ |
4014 | xmm_regs[reg].XMM_B(val & 15))); |
4015 | break; | |
4016 | case 0x21: /* insertps */ | |
a7812ae4 | 4017 | if (mod == 3) { |
222a3336 AZ |
4018 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
4019 | offsetof(CPUX86State,xmm_regs[rm] | |
4020 | .XMM_L((val >> 6) & 3))); | |
a7812ae4 PB |
4021 | } else { |
4022 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, | |
222a3336 | 4023 | (s->mem_index >> 2) - 1); |
a7812ae4 PB |
4024 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
4025 | } | |
222a3336 AZ |
4026 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
4027 | offsetof(CPUX86State,xmm_regs[reg] | |
4028 | .XMM_L((val >> 4) & 3))); | |
4029 | if ((val >> 0) & 1) | |
4030 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4031 | cpu_env, offsetof(CPUX86State, | |
4032 | xmm_regs[reg].XMM_L(0))); | |
4033 | if ((val >> 1) & 1) | |
4034 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4035 | cpu_env, offsetof(CPUX86State, | |
4036 | xmm_regs[reg].XMM_L(1))); | |
4037 | if ((val >> 2) & 1) | |
4038 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4039 | cpu_env, offsetof(CPUX86State, | |
4040 | xmm_regs[reg].XMM_L(2))); | |
4041 | if ((val >> 3) & 1) | |
4042 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4043 | cpu_env, offsetof(CPUX86State, | |
4044 | xmm_regs[reg].XMM_L(3))); | |
4045 | break; | |
4046 | case 0x22: | |
4047 | if (ot == OT_LONG) { /* pinsrd */ | |
4048 | if (mod == 3) | |
a7812ae4 | 4049 | gen_op_mov_v_reg(ot, cpu_tmp0, rm); |
222a3336 | 4050 | else |
a7812ae4 | 4051 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 4052 | (s->mem_index >> 2) - 1); |
a7812ae4 | 4053 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
4054 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
4055 | offsetof(CPUX86State, | |
4056 | xmm_regs[reg].XMM_L(val & 3))); | |
4057 | } else { /* pinsrq */ | |
a7812ae4 | 4058 | #ifdef TARGET_X86_64 |
222a3336 AZ |
4059 | if (mod == 3) |
4060 | gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); | |
4061 | else | |
4062 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, | |
4063 | (s->mem_index >> 2) - 1); | |
4064 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, | |
4065 | offsetof(CPUX86State, | |
4066 | xmm_regs[reg].XMM_Q(val & 1))); | |
a7812ae4 PB |
4067 | #else |
4068 | goto illegal_op; | |
4069 | #endif | |
222a3336 AZ |
4070 | } |
4071 | break; | |
4072 | } | |
4073 | return; | |
4074 | } | |
4242b1bd AZ |
4075 | |
4076 | if (b1) { | |
4077 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4078 | if (mod == 3) { | |
4079 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
4080 | } else { | |
4081 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
0af10c86 | 4082 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4242b1bd AZ |
4083 | gen_ldo_env_A0(s->mem_index, op2_offset); |
4084 | } | |
4085 | } else { | |
4086 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4087 | if (mod == 3) { | |
4088 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4089 | } else { | |
4090 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
0af10c86 | 4091 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4242b1bd AZ |
4092 | gen_ldq_env_A0(s->mem_index, op2_offset); |
4093 | } | |
4094 | } | |
0af10c86 | 4095 | val = cpu_ldub_code(env, s->pc++); |
4242b1bd | 4096 | |
222a3336 | 4097 | if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ |
3ca51d07 | 4098 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 AZ |
4099 | |
4100 | if (s->dflag == 2) | |
4101 | /* The helper must use entire 64-bit gp registers */ | |
4102 | val |= 1 << 8; | |
4103 | } | |
4104 | ||
4242b1bd AZ |
4105 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4106 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4107 | sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
4242b1bd | 4108 | break; |
664e0f19 FB |
4109 | default: |
4110 | goto illegal_op; | |
4111 | } | |
4112 | } else { | |
4113 | /* generic MMX or SSE operation */ | |
d1e42c5c | 4114 | switch(b) { |
d1e42c5c FB |
4115 | case 0x70: /* pshufx insn */ |
4116 | case 0xc6: /* pshufx insn */ | |
4117 | case 0xc2: /* compare insns */ | |
4118 | s->rip_offset = 1; | |
4119 | break; | |
4120 | default: | |
4121 | break; | |
664e0f19 FB |
4122 | } |
4123 | if (is_xmm) { | |
4124 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4125 | if (mod != 3) { | |
0af10c86 | 4126 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 4127 | op2_offset = offsetof(CPUX86State,xmm_t0); |
480c1cdb | 4128 | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
664e0f19 FB |
4129 | b == 0xc2)) { |
4130 | /* specific case for SSE single instructions */ | |
4131 | if (b1 == 2) { | |
4132 | /* 32 bit access */ | |
57fec1fe | 4133 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 4134 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 FB |
4135 | } else { |
4136 | /* 64 bit access */ | |
8686c490 | 4137 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0))); |
664e0f19 FB |
4138 | } |
4139 | } else { | |
8686c490 | 4140 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
4141 | } |
4142 | } else { | |
4143 | rm = (modrm & 7) | REX_B(s); | |
4144 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
4145 | } | |
4146 | } else { | |
4147 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4148 | if (mod != 3) { | |
0af10c86 | 4149 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 4150 | op2_offset = offsetof(CPUX86State,mmx_t0); |
8686c490 | 4151 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
4152 | } else { |
4153 | rm = (modrm & 7); | |
4154 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4155 | } | |
4156 | } | |
4157 | switch(b) { | |
a35f3ec7 | 4158 | case 0x0f: /* 3DNow! data insns */ |
e771edab AJ |
4159 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) |
4160 | goto illegal_op; | |
0af10c86 | 4161 | val = cpu_ldub_code(env, s->pc++); |
d3eb5eae BS |
4162 | sse_fn_epp = sse_op_table5[val]; |
4163 | if (!sse_fn_epp) { | |
a35f3ec7 | 4164 | goto illegal_op; |
c4baa050 | 4165 | } |
5af45186 FB |
4166 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4167 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4168 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
a35f3ec7 | 4169 | break; |
664e0f19 FB |
4170 | case 0x70: /* pshufx insn */ |
4171 | case 0xc6: /* pshufx insn */ | |
0af10c86 | 4172 | val = cpu_ldub_code(env, s->pc++); |
5af45186 FB |
4173 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4174 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4175 | /* XXX: introduce a new table? */ |
d3eb5eae | 4176 | sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp; |
c4baa050 | 4177 | sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
664e0f19 FB |
4178 | break; |
4179 | case 0xc2: | |
4180 | /* compare insns */ | |
0af10c86 | 4181 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
4182 | if (val >= 8) |
4183 | goto illegal_op; | |
d3eb5eae | 4184 | sse_fn_epp = sse_op_table4[val][b1]; |
c4baa050 | 4185 | |
5af45186 FB |
4186 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4187 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4188 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 | 4189 | break; |
b8b6a50b FB |
4190 | case 0xf7: |
4191 | /* maskmov : we must prepare A0 */ | |
4192 | if (mod != 3) | |
4193 | goto illegal_op; | |
4194 | #ifdef TARGET_X86_64 | |
4195 | if (s->aflag == 2) { | |
4196 | gen_op_movq_A0_reg(R_EDI); | |
4197 | } else | |
4198 | #endif | |
4199 | { | |
4200 | gen_op_movl_A0_reg(R_EDI); | |
4201 | if (s->aflag == 0) | |
4202 | gen_op_andl_A0_ffff(); | |
4203 | } | |
4204 | gen_add_A0_ds_seg(s); | |
4205 | ||
4206 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); | |
4207 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4208 | /* XXX: introduce a new table? */ |
d3eb5eae BS |
4209 | sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp; |
4210 | sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0); | |
b8b6a50b | 4211 | break; |
664e0f19 | 4212 | default: |
5af45186 FB |
4213 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4214 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4215 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
4216 | break; |
4217 | } | |
4218 | if (b == 0x2e || b == 0x2f) { | |
3ca51d07 | 4219 | set_cc_op(s, CC_OP_EFLAGS); |
664e0f19 FB |
4220 | } |
4221 | } | |
4222 | } | |
4223 | ||
2c0262af FB |
4224 | /* convert one instruction. s->is_jmp is set if the translation must |
4225 | be stopped. Return the next pc value */ | |
0af10c86 BS |
4226 | static target_ulong disas_insn(CPUX86State *env, DisasContext *s, |
4227 | target_ulong pc_start) | |
2c0262af FB |
4228 | { |
4229 | int b, prefixes, aflag, dflag; | |
4230 | int shift, ot; | |
4231 | int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val; | |
14ce26e7 FB |
4232 | target_ulong next_eip, tval; |
4233 | int rex_w, rex_r; | |
2c0262af | 4234 | |
fdefe51c | 4235 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
70cff25e | 4236 | tcg_gen_debug_insn_start(pc_start); |
fdefe51c | 4237 | } |
2c0262af FB |
4238 | s->pc = pc_start; |
4239 | prefixes = 0; | |
4240 | aflag = s->code32; | |
4241 | dflag = s->code32; | |
4242 | s->override = -1; | |
14ce26e7 FB |
4243 | rex_w = -1; |
4244 | rex_r = 0; | |
4245 | #ifdef TARGET_X86_64 | |
4246 | s->rex_x = 0; | |
4247 | s->rex_b = 0; | |
5fafdf24 | 4248 | x86_64_hregs = 0; |
14ce26e7 FB |
4249 | #endif |
4250 | s->rip_offset = 0; /* for relative ip address */ | |
2c0262af | 4251 | next_byte: |
0af10c86 | 4252 | b = cpu_ldub_code(env, s->pc); |
2c0262af FB |
4253 | s->pc++; |
4254 | /* check prefixes */ | |
14ce26e7 FB |
4255 | #ifdef TARGET_X86_64 |
4256 | if (CODE64(s)) { | |
4257 | switch (b) { | |
4258 | case 0xf3: | |
4259 | prefixes |= PREFIX_REPZ; | |
4260 | goto next_byte; | |
4261 | case 0xf2: | |
4262 | prefixes |= PREFIX_REPNZ; | |
4263 | goto next_byte; | |
4264 | case 0xf0: | |
4265 | prefixes |= PREFIX_LOCK; | |
4266 | goto next_byte; | |
4267 | case 0x2e: | |
4268 | s->override = R_CS; | |
4269 | goto next_byte; | |
4270 | case 0x36: | |
4271 | s->override = R_SS; | |
4272 | goto next_byte; | |
4273 | case 0x3e: | |
4274 | s->override = R_DS; | |
4275 | goto next_byte; | |
4276 | case 0x26: | |
4277 | s->override = R_ES; | |
4278 | goto next_byte; | |
4279 | case 0x64: | |
4280 | s->override = R_FS; | |
4281 | goto next_byte; | |
4282 | case 0x65: | |
4283 | s->override = R_GS; | |
4284 | goto next_byte; | |
4285 | case 0x66: | |
4286 | prefixes |= PREFIX_DATA; | |
4287 | goto next_byte; | |
4288 | case 0x67: | |
4289 | prefixes |= PREFIX_ADR; | |
4290 | goto next_byte; | |
4291 | case 0x40 ... 0x4f: | |
4292 | /* REX prefix */ | |
4293 | rex_w = (b >> 3) & 1; | |
4294 | rex_r = (b & 0x4) << 1; | |
4295 | s->rex_x = (b & 0x2) << 2; | |
4296 | REX_B(s) = (b & 0x1) << 3; | |
4297 | x86_64_hregs = 1; /* select uniform byte register addressing */ | |
4298 | goto next_byte; | |
4299 | } | |
4300 | if (rex_w == 1) { | |
4301 | /* 0x66 is ignored if rex.w is set */ | |
4302 | dflag = 2; | |
4303 | } else { | |
4304 | if (prefixes & PREFIX_DATA) | |
4305 | dflag ^= 1; | |
4306 | } | |
4307 | if (!(prefixes & PREFIX_ADR)) | |
4308 | aflag = 2; | |
5fafdf24 | 4309 | } else |
14ce26e7 FB |
4310 | #endif |
4311 | { | |
4312 | switch (b) { | |
4313 | case 0xf3: | |
4314 | prefixes |= PREFIX_REPZ; | |
4315 | goto next_byte; | |
4316 | case 0xf2: | |
4317 | prefixes |= PREFIX_REPNZ; | |
4318 | goto next_byte; | |
4319 | case 0xf0: | |
4320 | prefixes |= PREFIX_LOCK; | |
4321 | goto next_byte; | |
4322 | case 0x2e: | |
4323 | s->override = R_CS; | |
4324 | goto next_byte; | |
4325 | case 0x36: | |
4326 | s->override = R_SS; | |
4327 | goto next_byte; | |
4328 | case 0x3e: | |
4329 | s->override = R_DS; | |
4330 | goto next_byte; | |
4331 | case 0x26: | |
4332 | s->override = R_ES; | |
4333 | goto next_byte; | |
4334 | case 0x64: | |
4335 | s->override = R_FS; | |
4336 | goto next_byte; | |
4337 | case 0x65: | |
4338 | s->override = R_GS; | |
4339 | goto next_byte; | |
4340 | case 0x66: | |
4341 | prefixes |= PREFIX_DATA; | |
4342 | goto next_byte; | |
4343 | case 0x67: | |
4344 | prefixes |= PREFIX_ADR; | |
4345 | goto next_byte; | |
4346 | } | |
4347 | if (prefixes & PREFIX_DATA) | |
4348 | dflag ^= 1; | |
4349 | if (prefixes & PREFIX_ADR) | |
4350 | aflag ^= 1; | |
2c0262af FB |
4351 | } |
4352 | ||
2c0262af FB |
4353 | s->prefix = prefixes; |
4354 | s->aflag = aflag; | |
4355 | s->dflag = dflag; | |
4356 | ||
4357 | /* lock generation */ | |
4358 | if (prefixes & PREFIX_LOCK) | |
a7812ae4 | 4359 | gen_helper_lock(); |
2c0262af FB |
4360 | |
4361 | /* now check op code */ | |
4362 | reswitch: | |
4363 | switch(b) { | |
4364 | case 0x0f: | |
4365 | /**************************/ | |
4366 | /* extended op code */ | |
0af10c86 | 4367 | b = cpu_ldub_code(env, s->pc++) | 0x100; |
2c0262af | 4368 | goto reswitch; |
3b46e624 | 4369 | |
2c0262af FB |
4370 | /**************************/ |
4371 | /* arith & logic */ | |
4372 | case 0x00 ... 0x05: | |
4373 | case 0x08 ... 0x0d: | |
4374 | case 0x10 ... 0x15: | |
4375 | case 0x18 ... 0x1d: | |
4376 | case 0x20 ... 0x25: | |
4377 | case 0x28 ... 0x2d: | |
4378 | case 0x30 ... 0x35: | |
4379 | case 0x38 ... 0x3d: | |
4380 | { | |
4381 | int op, f, val; | |
4382 | op = (b >> 3) & 7; | |
4383 | f = (b >> 1) & 3; | |
4384 | ||
4385 | if ((b & 1) == 0) | |
4386 | ot = OT_BYTE; | |
4387 | else | |
14ce26e7 | 4388 | ot = dflag + OT_WORD; |
3b46e624 | 4389 | |
2c0262af FB |
4390 | switch(f) { |
4391 | case 0: /* OP Ev, Gv */ | |
0af10c86 | 4392 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4393 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 4394 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4395 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4396 | if (mod != 3) { |
0af10c86 | 4397 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
4398 | opreg = OR_TMP0; |
4399 | } else if (op == OP_XORL && rm == reg) { | |
4400 | xor_zero: | |
4401 | /* xor reg, reg optimisation */ | |
4402 | gen_op_movl_T0_0(); | |
3ca51d07 | 4403 | set_cc_op(s, CC_OP_LOGICB + ot); |
57fec1fe | 4404 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
4405 | gen_op_update1_cc(); |
4406 | break; | |
4407 | } else { | |
4408 | opreg = rm; | |
4409 | } | |
57fec1fe | 4410 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4411 | gen_op(s, op, ot, opreg); |
4412 | break; | |
4413 | case 1: /* OP Gv, Ev */ | |
0af10c86 | 4414 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4415 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
4416 | reg = ((modrm >> 3) & 7) | rex_r; |
4417 | rm = (modrm & 7) | REX_B(s); | |
2c0262af | 4418 | if (mod != 3) { |
0af10c86 | 4419 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 4420 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af FB |
4421 | } else if (op == OP_XORL && rm == reg) { |
4422 | goto xor_zero; | |
4423 | } else { | |
57fec1fe | 4424 | gen_op_mov_TN_reg(ot, 1, rm); |
2c0262af FB |
4425 | } |
4426 | gen_op(s, op, ot, reg); | |
4427 | break; | |
4428 | case 2: /* OP A, Iv */ | |
0af10c86 | 4429 | val = insn_get(env, s, ot); |
2c0262af FB |
4430 | gen_op_movl_T1_im(val); |
4431 | gen_op(s, op, ot, OR_EAX); | |
4432 | break; | |
4433 | } | |
4434 | } | |
4435 | break; | |
4436 | ||
ec9d6075 FB |
4437 | case 0x82: |
4438 | if (CODE64(s)) | |
4439 | goto illegal_op; | |
2c0262af FB |
4440 | case 0x80: /* GRP1 */ |
4441 | case 0x81: | |
4442 | case 0x83: | |
4443 | { | |
4444 | int val; | |
4445 | ||
4446 | if ((b & 1) == 0) | |
4447 | ot = OT_BYTE; | |
4448 | else | |
14ce26e7 | 4449 | ot = dflag + OT_WORD; |
3b46e624 | 4450 | |
0af10c86 | 4451 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4452 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4453 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4454 | op = (modrm >> 3) & 7; |
3b46e624 | 4455 | |
2c0262af | 4456 | if (mod != 3) { |
14ce26e7 FB |
4457 | if (b == 0x83) |
4458 | s->rip_offset = 1; | |
4459 | else | |
4460 | s->rip_offset = insn_const_size(ot); | |
0af10c86 | 4461 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
4462 | opreg = OR_TMP0; |
4463 | } else { | |
14ce26e7 | 4464 | opreg = rm; |
2c0262af FB |
4465 | } |
4466 | ||
4467 | switch(b) { | |
4468 | default: | |
4469 | case 0x80: | |
4470 | case 0x81: | |
d64477af | 4471 | case 0x82: |
0af10c86 | 4472 | val = insn_get(env, s, ot); |
2c0262af FB |
4473 | break; |
4474 | case 0x83: | |
0af10c86 | 4475 | val = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
4476 | break; |
4477 | } | |
4478 | gen_op_movl_T1_im(val); | |
4479 | gen_op(s, op, ot, opreg); | |
4480 | } | |
4481 | break; | |
4482 | ||
4483 | /**************************/ | |
4484 | /* inc, dec, and other misc arith */ | |
4485 | case 0x40 ... 0x47: /* inc Gv */ | |
4486 | ot = dflag ? OT_LONG : OT_WORD; | |
4487 | gen_inc(s, ot, OR_EAX + (b & 7), 1); | |
4488 | break; | |
4489 | case 0x48 ... 0x4f: /* dec Gv */ | |
4490 | ot = dflag ? OT_LONG : OT_WORD; | |
4491 | gen_inc(s, ot, OR_EAX + (b & 7), -1); | |
4492 | break; | |
4493 | case 0xf6: /* GRP3 */ | |
4494 | case 0xf7: | |
4495 | if ((b & 1) == 0) | |
4496 | ot = OT_BYTE; | |
4497 | else | |
14ce26e7 | 4498 | ot = dflag + OT_WORD; |
2c0262af | 4499 | |
0af10c86 | 4500 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4501 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4502 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4503 | op = (modrm >> 3) & 7; |
4504 | if (mod != 3) { | |
14ce26e7 FB |
4505 | if (op == 0) |
4506 | s->rip_offset = insn_const_size(ot); | |
0af10c86 | 4507 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 4508 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4509 | } else { |
57fec1fe | 4510 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4511 | } |
4512 | ||
4513 | switch(op) { | |
4514 | case 0: /* test */ | |
0af10c86 | 4515 | val = insn_get(env, s, ot); |
2c0262af FB |
4516 | gen_op_movl_T1_im(val); |
4517 | gen_op_testl_T0_T1_cc(); | |
3ca51d07 | 4518 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af FB |
4519 | break; |
4520 | case 2: /* not */ | |
b6abf97d | 4521 | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4522 | if (mod != 3) { |
57fec1fe | 4523 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4524 | } else { |
57fec1fe | 4525 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4526 | } |
4527 | break; | |
4528 | case 3: /* neg */ | |
b6abf97d | 4529 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4530 | if (mod != 3) { |
57fec1fe | 4531 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4532 | } else { |
57fec1fe | 4533 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4534 | } |
4535 | gen_op_update_neg_cc(); | |
3ca51d07 | 4536 | set_cc_op(s, CC_OP_SUBB + ot); |
2c0262af FB |
4537 | break; |
4538 | case 4: /* mul */ | |
4539 | switch(ot) { | |
4540 | case OT_BYTE: | |
0211e5af FB |
4541 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4542 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); | |
4543 | tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); | |
4544 | /* XXX: use 32 bit mul which could be faster */ | |
4545 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4546 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4547 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4548 | tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); | |
3ca51d07 | 4549 | set_cc_op(s, CC_OP_MULB); |
2c0262af FB |
4550 | break; |
4551 | case OT_WORD: | |
0211e5af FB |
4552 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4553 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); | |
4554 | tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); | |
4555 | /* XXX: use 32 bit mul which could be faster */ | |
4556 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4557 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4558 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4559 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4560 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4561 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
3ca51d07 | 4562 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4563 | break; |
4564 | default: | |
4565 | case OT_LONG: | |
0211e5af FB |
4566 | #ifdef TARGET_X86_64 |
4567 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4568 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); | |
4569 | tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); | |
4570 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4571 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4572 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4573 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4574 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4575 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4576 | #else | |
4577 | { | |
a7812ae4 PB |
4578 | TCGv_i64 t0, t1; |
4579 | t0 = tcg_temp_new_i64(); | |
4580 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4581 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4582 | tcg_gen_extu_i32_i64(t0, cpu_T[0]); | |
4583 | tcg_gen_extu_i32_i64(t1, cpu_T[1]); | |
4584 | tcg_gen_mul_i64(t0, t0, t1); | |
4585 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4586 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4587 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4588 | tcg_gen_shri_i64(t0, t0, 32); | |
4589 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4590 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4591 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4592 | } | |
4593 | #endif | |
3ca51d07 | 4594 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4595 | break; |
14ce26e7 FB |
4596 | #ifdef TARGET_X86_64 |
4597 | case OT_QUAD: | |
7923057b | 4598 | gen_helper_mulq_EAX_T0(cpu_env, cpu_T[0]); |
3ca51d07 | 4599 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4600 | break; |
4601 | #endif | |
2c0262af | 4602 | } |
2c0262af FB |
4603 | break; |
4604 | case 5: /* imul */ | |
4605 | switch(ot) { | |
4606 | case OT_BYTE: | |
0211e5af FB |
4607 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4608 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4609 | tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); | |
4610 | /* XXX: use 32 bit mul which could be faster */ | |
4611 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4612 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4613 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4614 | tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]); | |
4615 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
3ca51d07 | 4616 | set_cc_op(s, CC_OP_MULB); |
2c0262af FB |
4617 | break; |
4618 | case OT_WORD: | |
0211e5af FB |
4619 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4620 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4621 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4622 | /* XXX: use 32 bit mul which could be faster */ | |
4623 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4624 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4625 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4626 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4627 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4628 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4629 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
3ca51d07 | 4630 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4631 | break; |
4632 | default: | |
4633 | case OT_LONG: | |
0211e5af FB |
4634 | #ifdef TARGET_X86_64 |
4635 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4636 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4637 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4638 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4639 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4640 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4641 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4642 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4643 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4644 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4645 | #else | |
4646 | { | |
a7812ae4 PB |
4647 | TCGv_i64 t0, t1; |
4648 | t0 = tcg_temp_new_i64(); | |
4649 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4650 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4651 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); | |
4652 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4653 | tcg_gen_mul_i64(t0, t0, t1); | |
4654 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4655 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4656 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4657 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4658 | tcg_gen_shri_i64(t0, t0, 32); | |
4659 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4660 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4661 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4662 | } | |
4663 | #endif | |
3ca51d07 | 4664 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4665 | break; |
14ce26e7 FB |
4666 | #ifdef TARGET_X86_64 |
4667 | case OT_QUAD: | |
7923057b | 4668 | gen_helper_imulq_EAX_T0(cpu_env, cpu_T[0]); |
3ca51d07 | 4669 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4670 | break; |
4671 | #endif | |
2c0262af | 4672 | } |
2c0262af FB |
4673 | break; |
4674 | case 6: /* div */ | |
4675 | switch(ot) { | |
4676 | case OT_BYTE: | |
14ce26e7 | 4677 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4678 | gen_helper_divb_AL(cpu_env, cpu_T[0]); |
2c0262af FB |
4679 | break; |
4680 | case OT_WORD: | |
14ce26e7 | 4681 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4682 | gen_helper_divw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4683 | break; |
4684 | default: | |
4685 | case OT_LONG: | |
14ce26e7 | 4686 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4687 | gen_helper_divl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4688 | break; |
4689 | #ifdef TARGET_X86_64 | |
4690 | case OT_QUAD: | |
4691 | gen_jmp_im(pc_start - s->cs_base); | |
7923057b | 4692 | gen_helper_divq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4693 | break; |
14ce26e7 | 4694 | #endif |
2c0262af FB |
4695 | } |
4696 | break; | |
4697 | case 7: /* idiv */ | |
4698 | switch(ot) { | |
4699 | case OT_BYTE: | |
14ce26e7 | 4700 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4701 | gen_helper_idivb_AL(cpu_env, cpu_T[0]); |
2c0262af FB |
4702 | break; |
4703 | case OT_WORD: | |
14ce26e7 | 4704 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4705 | gen_helper_idivw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4706 | break; |
4707 | default: | |
4708 | case OT_LONG: | |
14ce26e7 | 4709 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4710 | gen_helper_idivl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4711 | break; |
4712 | #ifdef TARGET_X86_64 | |
4713 | case OT_QUAD: | |
4714 | gen_jmp_im(pc_start - s->cs_base); | |
7923057b | 4715 | gen_helper_idivq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4716 | break; |
14ce26e7 | 4717 | #endif |
2c0262af FB |
4718 | } |
4719 | break; | |
4720 | default: | |
4721 | goto illegal_op; | |
4722 | } | |
4723 | break; | |
4724 | ||
4725 | case 0xfe: /* GRP4 */ | |
4726 | case 0xff: /* GRP5 */ | |
4727 | if ((b & 1) == 0) | |
4728 | ot = OT_BYTE; | |
4729 | else | |
14ce26e7 | 4730 | ot = dflag + OT_WORD; |
2c0262af | 4731 | |
0af10c86 | 4732 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4733 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4734 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4735 | op = (modrm >> 3) & 7; |
4736 | if (op >= 2 && b == 0xfe) { | |
4737 | goto illegal_op; | |
4738 | } | |
14ce26e7 | 4739 | if (CODE64(s)) { |
aba9d61e | 4740 | if (op == 2 || op == 4) { |
14ce26e7 FB |
4741 | /* operand size for jumps is 64 bit */ |
4742 | ot = OT_QUAD; | |
aba9d61e | 4743 | } else if (op == 3 || op == 5) { |
41b1e61f | 4744 | ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD; |
14ce26e7 FB |
4745 | } else if (op == 6) { |
4746 | /* default push size is 64 bit */ | |
4747 | ot = dflag ? OT_QUAD : OT_WORD; | |
4748 | } | |
4749 | } | |
2c0262af | 4750 | if (mod != 3) { |
0af10c86 | 4751 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 4752 | if (op >= 2 && op != 3 && op != 5) |
57fec1fe | 4753 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4754 | } else { |
57fec1fe | 4755 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4756 | } |
4757 | ||
4758 | switch(op) { | |
4759 | case 0: /* inc Ev */ | |
4760 | if (mod != 3) | |
4761 | opreg = OR_TMP0; | |
4762 | else | |
4763 | opreg = rm; | |
4764 | gen_inc(s, ot, opreg, 1); | |
4765 | break; | |
4766 | case 1: /* dec Ev */ | |
4767 | if (mod != 3) | |
4768 | opreg = OR_TMP0; | |
4769 | else | |
4770 | opreg = rm; | |
4771 | gen_inc(s, ot, opreg, -1); | |
4772 | break; | |
4773 | case 2: /* call Ev */ | |
4f31916f | 4774 | /* XXX: optimize if memory (no 'and' is necessary) */ |
2c0262af FB |
4775 | if (s->dflag == 0) |
4776 | gen_op_andl_T0_ffff(); | |
2c0262af | 4777 | next_eip = s->pc - s->cs_base; |
1ef38687 | 4778 | gen_movtl_T1_im(next_eip); |
4f31916f FB |
4779 | gen_push_T1(s); |
4780 | gen_op_jmp_T0(); | |
2c0262af FB |
4781 | gen_eob(s); |
4782 | break; | |
61382a50 | 4783 | case 3: /* lcall Ev */ |
57fec1fe | 4784 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4785 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4786 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4787 | do_lcall: |
4788 | if (s->pe && !s->vm86) { | |
773cdfcc | 4789 | gen_update_cc_op(s); |
14ce26e7 | 4790 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4791 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
4792 | gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
4793 | tcg_const_i32(dflag), | |
a7812ae4 | 4794 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 4795 | } else { |
b6abf97d | 4796 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
4797 | gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1], |
4798 | tcg_const_i32(dflag), | |
a7812ae4 | 4799 | tcg_const_i32(s->pc - s->cs_base)); |
2c0262af FB |
4800 | } |
4801 | gen_eob(s); | |
4802 | break; | |
4803 | case 4: /* jmp Ev */ | |
4804 | if (s->dflag == 0) | |
4805 | gen_op_andl_T0_ffff(); | |
4806 | gen_op_jmp_T0(); | |
4807 | gen_eob(s); | |
4808 | break; | |
4809 | case 5: /* ljmp Ev */ | |
57fec1fe | 4810 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4811 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4812 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4813 | do_ljmp: |
4814 | if (s->pe && !s->vm86) { | |
773cdfcc | 4815 | gen_update_cc_op(s); |
14ce26e7 | 4816 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4817 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 4818 | gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
a7812ae4 | 4819 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 4820 | } else { |
3bd7da9e | 4821 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
4822 | gen_op_movl_T0_T1(); |
4823 | gen_op_jmp_T0(); | |
4824 | } | |
4825 | gen_eob(s); | |
4826 | break; | |
4827 | case 6: /* push Ev */ | |
4828 | gen_push_T0(s); | |
4829 | break; | |
4830 | default: | |
4831 | goto illegal_op; | |
4832 | } | |
4833 | break; | |
4834 | ||
4835 | case 0x84: /* test Ev, Gv */ | |
5fafdf24 | 4836 | case 0x85: |
2c0262af FB |
4837 | if ((b & 1) == 0) |
4838 | ot = OT_BYTE; | |
4839 | else | |
14ce26e7 | 4840 | ot = dflag + OT_WORD; |
2c0262af | 4841 | |
0af10c86 | 4842 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4843 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 4844 | |
0af10c86 | 4845 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 4846 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af | 4847 | gen_op_testl_T0_T1_cc(); |
3ca51d07 | 4848 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 4849 | break; |
3b46e624 | 4850 | |
2c0262af FB |
4851 | case 0xa8: /* test eAX, Iv */ |
4852 | case 0xa9: | |
4853 | if ((b & 1) == 0) | |
4854 | ot = OT_BYTE; | |
4855 | else | |
14ce26e7 | 4856 | ot = dflag + OT_WORD; |
0af10c86 | 4857 | val = insn_get(env, s, ot); |
2c0262af | 4858 | |
57fec1fe | 4859 | gen_op_mov_TN_reg(ot, 0, OR_EAX); |
2c0262af FB |
4860 | gen_op_movl_T1_im(val); |
4861 | gen_op_testl_T0_T1_cc(); | |
3ca51d07 | 4862 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 4863 | break; |
3b46e624 | 4864 | |
2c0262af | 4865 | case 0x98: /* CWDE/CBW */ |
14ce26e7 FB |
4866 | #ifdef TARGET_X86_64 |
4867 | if (dflag == 2) { | |
e108dd01 FB |
4868 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
4869 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4870 | gen_op_mov_reg_T0(OT_QUAD, R_EAX); | |
14ce26e7 FB |
4871 | } else |
4872 | #endif | |
e108dd01 FB |
4873 | if (dflag == 1) { |
4874 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4875 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4876 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4877 | } else { | |
4878 | gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX); | |
4879 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4880 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4881 | } | |
2c0262af FB |
4882 | break; |
4883 | case 0x99: /* CDQ/CWD */ | |
14ce26e7 FB |
4884 | #ifdef TARGET_X86_64 |
4885 | if (dflag == 2) { | |
e108dd01 FB |
4886 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
4887 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); | |
4888 | gen_op_mov_reg_T0(OT_QUAD, R_EDX); | |
14ce26e7 FB |
4889 | } else |
4890 | #endif | |
e108dd01 FB |
4891 | if (dflag == 1) { |
4892 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); | |
4893 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4894 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); | |
4895 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4896 | } else { | |
4897 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4898 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4899 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); | |
4900 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4901 | } | |
2c0262af FB |
4902 | break; |
4903 | case 0x1af: /* imul Gv, Ev */ | |
4904 | case 0x69: /* imul Gv, Ev, I */ | |
4905 | case 0x6b: | |
14ce26e7 | 4906 | ot = dflag + OT_WORD; |
0af10c86 | 4907 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
4908 | reg = ((modrm >> 3) & 7) | rex_r; |
4909 | if (b == 0x69) | |
4910 | s->rip_offset = insn_const_size(ot); | |
4911 | else if (b == 0x6b) | |
4912 | s->rip_offset = 1; | |
0af10c86 | 4913 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
2c0262af | 4914 | if (b == 0x69) { |
0af10c86 | 4915 | val = insn_get(env, s, ot); |
2c0262af FB |
4916 | gen_op_movl_T1_im(val); |
4917 | } else if (b == 0x6b) { | |
0af10c86 | 4918 | val = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
4919 | gen_op_movl_T1_im(val); |
4920 | } else { | |
57fec1fe | 4921 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4922 | } |
4923 | ||
14ce26e7 FB |
4924 | #ifdef TARGET_X86_64 |
4925 | if (ot == OT_QUAD) { | |
7923057b | 4926 | gen_helper_imulq_T0_T1(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
14ce26e7 FB |
4927 | } else |
4928 | #endif | |
2c0262af | 4929 | if (ot == OT_LONG) { |
0211e5af FB |
4930 | #ifdef TARGET_X86_64 |
4931 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4932 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4933 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4934 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4935 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4936 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4937 | #else | |
4938 | { | |
a7812ae4 PB |
4939 | TCGv_i64 t0, t1; |
4940 | t0 = tcg_temp_new_i64(); | |
4941 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4942 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); |
4943 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4944 | tcg_gen_mul_i64(t0, t0, t1); | |
4945 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4946 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4947 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4948 | tcg_gen_shri_i64(t0, t0, 32); | |
4949 | tcg_gen_trunc_i64_i32(cpu_T[1], t0); | |
4950 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0); | |
4951 | } | |
4952 | #endif | |
2c0262af | 4953 | } else { |
0211e5af FB |
4954 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4955 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4956 | /* XXX: use 32 bit mul which could be faster */ | |
4957 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4958 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4959 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4960 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
2c0262af | 4961 | } |
57fec1fe | 4962 | gen_op_mov_reg_T0(ot, reg); |
3ca51d07 | 4963 | set_cc_op(s, CC_OP_MULB + ot); |
2c0262af FB |
4964 | break; |
4965 | case 0x1c0: | |
4966 | case 0x1c1: /* xadd Ev, Gv */ | |
4967 | if ((b & 1) == 0) | |
4968 | ot = OT_BYTE; | |
4969 | else | |
14ce26e7 | 4970 | ot = dflag + OT_WORD; |
0af10c86 | 4971 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4972 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
4973 | mod = (modrm >> 6) & 3; |
4974 | if (mod == 3) { | |
14ce26e7 | 4975 | rm = (modrm & 7) | REX_B(s); |
57fec1fe FB |
4976 | gen_op_mov_TN_reg(ot, 0, reg); |
4977 | gen_op_mov_TN_reg(ot, 1, rm); | |
2c0262af | 4978 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4979 | gen_op_mov_reg_T1(ot, reg); |
4980 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 4981 | } else { |
0af10c86 | 4982 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe FB |
4983 | gen_op_mov_TN_reg(ot, 0, reg); |
4984 | gen_op_ld_T1_A0(ot + s->mem_index); | |
2c0262af | 4985 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4986 | gen_op_st_T0_A0(ot + s->mem_index); |
4987 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af FB |
4988 | } |
4989 | gen_op_update2_cc(); | |
3ca51d07 | 4990 | set_cc_op(s, CC_OP_ADDB + ot); |
2c0262af FB |
4991 | break; |
4992 | case 0x1b0: | |
4993 | case 0x1b1: /* cmpxchg Ev, Gv */ | |
cad3a37d | 4994 | { |
1130328e | 4995 | int label1, label2; |
1e4840bf | 4996 | TCGv t0, t1, t2, a0; |
cad3a37d FB |
4997 | |
4998 | if ((b & 1) == 0) | |
4999 | ot = OT_BYTE; | |
5000 | else | |
5001 | ot = dflag + OT_WORD; | |
0af10c86 | 5002 | modrm = cpu_ldub_code(env, s->pc++); |
cad3a37d FB |
5003 | reg = ((modrm >> 3) & 7) | rex_r; |
5004 | mod = (modrm >> 6) & 3; | |
a7812ae4 PB |
5005 | t0 = tcg_temp_local_new(); |
5006 | t1 = tcg_temp_local_new(); | |
5007 | t2 = tcg_temp_local_new(); | |
5008 | a0 = tcg_temp_local_new(); | |
1e4840bf | 5009 | gen_op_mov_v_reg(ot, t1, reg); |
cad3a37d FB |
5010 | if (mod == 3) { |
5011 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 5012 | gen_op_mov_v_reg(ot, t0, rm); |
cad3a37d | 5013 | } else { |
0af10c86 | 5014 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
1e4840bf FB |
5015 | tcg_gen_mov_tl(a0, cpu_A0); |
5016 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
cad3a37d FB |
5017 | rm = 0; /* avoid warning */ |
5018 | } | |
5019 | label1 = gen_new_label(); | |
cc739bb0 | 5020 | tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0); |
1e4840bf FB |
5021 | gen_extu(ot, t2); |
5022 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); | |
f7e80adf | 5023 | label2 = gen_new_label(); |
cad3a37d | 5024 | if (mod == 3) { |
1e4840bf | 5025 | gen_op_mov_reg_v(ot, R_EAX, t0); |
1130328e FB |
5026 | tcg_gen_br(label2); |
5027 | gen_set_label(label1); | |
1e4840bf | 5028 | gen_op_mov_reg_v(ot, rm, t1); |
cad3a37d | 5029 | } else { |
f7e80adf AG |
5030 | /* perform no-op store cycle like physical cpu; must be |
5031 | before changing accumulator to ensure idempotency if | |
5032 | the store faults and the instruction is restarted */ | |
5033 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1e4840bf | 5034 | gen_op_mov_reg_v(ot, R_EAX, t0); |
f7e80adf | 5035 | tcg_gen_br(label2); |
1130328e | 5036 | gen_set_label(label1); |
1e4840bf | 5037 | gen_op_st_v(ot + s->mem_index, t1, a0); |
cad3a37d | 5038 | } |
f7e80adf | 5039 | gen_set_label(label2); |
1e4840bf FB |
5040 | tcg_gen_mov_tl(cpu_cc_src, t0); |
5041 | tcg_gen_mov_tl(cpu_cc_dst, t2); | |
3ca51d07 | 5042 | set_cc_op(s, CC_OP_SUBB + ot); |
1e4840bf FB |
5043 | tcg_temp_free(t0); |
5044 | tcg_temp_free(t1); | |
5045 | tcg_temp_free(t2); | |
5046 | tcg_temp_free(a0); | |
2c0262af | 5047 | } |
2c0262af FB |
5048 | break; |
5049 | case 0x1c7: /* cmpxchg8b */ | |
0af10c86 | 5050 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5051 | mod = (modrm >> 6) & 3; |
71c3558e | 5052 | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
2c0262af | 5053 | goto illegal_op; |
1b9d9ebb FB |
5054 | #ifdef TARGET_X86_64 |
5055 | if (dflag == 2) { | |
5056 | if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) | |
5057 | goto illegal_op; | |
5058 | gen_jmp_im(pc_start - s->cs_base); | |
773cdfcc | 5059 | gen_update_cc_op(s); |
0af10c86 | 5060 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
92fc4b58 | 5061 | gen_helper_cmpxchg16b(cpu_env, cpu_A0); |
1b9d9ebb FB |
5062 | } else |
5063 | #endif | |
5064 | { | |
5065 | if (!(s->cpuid_features & CPUID_CX8)) | |
5066 | goto illegal_op; | |
5067 | gen_jmp_im(pc_start - s->cs_base); | |
773cdfcc | 5068 | gen_update_cc_op(s); |
0af10c86 | 5069 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
92fc4b58 | 5070 | gen_helper_cmpxchg8b(cpu_env, cpu_A0); |
1b9d9ebb | 5071 | } |
3ca51d07 | 5072 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 5073 | break; |
3b46e624 | 5074 | |
2c0262af FB |
5075 | /**************************/ |
5076 | /* push/pop */ | |
5077 | case 0x50 ... 0x57: /* push */ | |
57fec1fe | 5078 | gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s)); |
2c0262af FB |
5079 | gen_push_T0(s); |
5080 | break; | |
5081 | case 0x58 ... 0x5f: /* pop */ | |
14ce26e7 FB |
5082 | if (CODE64(s)) { |
5083 | ot = dflag ? OT_QUAD : OT_WORD; | |
5084 | } else { | |
5085 | ot = dflag + OT_WORD; | |
5086 | } | |
2c0262af | 5087 | gen_pop_T0(s); |
77729c24 | 5088 | /* NOTE: order is important for pop %sp */ |
2c0262af | 5089 | gen_pop_update(s); |
57fec1fe | 5090 | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s)); |
2c0262af FB |
5091 | break; |
5092 | case 0x60: /* pusha */ | |
14ce26e7 FB |
5093 | if (CODE64(s)) |
5094 | goto illegal_op; | |
2c0262af FB |
5095 | gen_pusha(s); |
5096 | break; | |
5097 | case 0x61: /* popa */ | |
14ce26e7 FB |
5098 | if (CODE64(s)) |
5099 | goto illegal_op; | |
2c0262af FB |
5100 | gen_popa(s); |
5101 | break; | |
5102 | case 0x68: /* push Iv */ | |
5103 | case 0x6a: | |
14ce26e7 FB |
5104 | if (CODE64(s)) { |
5105 | ot = dflag ? OT_QUAD : OT_WORD; | |
5106 | } else { | |
5107 | ot = dflag + OT_WORD; | |
5108 | } | |
2c0262af | 5109 | if (b == 0x68) |
0af10c86 | 5110 | val = insn_get(env, s, ot); |
2c0262af | 5111 | else |
0af10c86 | 5112 | val = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
5113 | gen_op_movl_T0_im(val); |
5114 | gen_push_T0(s); | |
5115 | break; | |
5116 | case 0x8f: /* pop Ev */ | |
14ce26e7 FB |
5117 | if (CODE64(s)) { |
5118 | ot = dflag ? OT_QUAD : OT_WORD; | |
5119 | } else { | |
5120 | ot = dflag + OT_WORD; | |
5121 | } | |
0af10c86 | 5122 | modrm = cpu_ldub_code(env, s->pc++); |
77729c24 | 5123 | mod = (modrm >> 6) & 3; |
2c0262af | 5124 | gen_pop_T0(s); |
77729c24 FB |
5125 | if (mod == 3) { |
5126 | /* NOTE: order is important for pop %sp */ | |
5127 | gen_pop_update(s); | |
14ce26e7 | 5128 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 5129 | gen_op_mov_reg_T0(ot, rm); |
77729c24 FB |
5130 | } else { |
5131 | /* NOTE: order is important too for MMU exceptions */ | |
14ce26e7 | 5132 | s->popl_esp_hack = 1 << ot; |
0af10c86 | 5133 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
77729c24 FB |
5134 | s->popl_esp_hack = 0; |
5135 | gen_pop_update(s); | |
5136 | } | |
2c0262af FB |
5137 | break; |
5138 | case 0xc8: /* enter */ | |
5139 | { | |
5140 | int level; | |
0af10c86 | 5141 | val = cpu_lduw_code(env, s->pc); |
2c0262af | 5142 | s->pc += 2; |
0af10c86 | 5143 | level = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5144 | gen_enter(s, val, level); |
5145 | } | |
5146 | break; | |
5147 | case 0xc9: /* leave */ | |
5148 | /* XXX: exception not precise (ESP is updated before potential exception) */ | |
14ce26e7 | 5149 | if (CODE64(s)) { |
57fec1fe FB |
5150 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP); |
5151 | gen_op_mov_reg_T0(OT_QUAD, R_ESP); | |
14ce26e7 | 5152 | } else if (s->ss32) { |
57fec1fe FB |
5153 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
5154 | gen_op_mov_reg_T0(OT_LONG, R_ESP); | |
2c0262af | 5155 | } else { |
57fec1fe FB |
5156 | gen_op_mov_TN_reg(OT_WORD, 0, R_EBP); |
5157 | gen_op_mov_reg_T0(OT_WORD, R_ESP); | |
2c0262af FB |
5158 | } |
5159 | gen_pop_T0(s); | |
14ce26e7 FB |
5160 | if (CODE64(s)) { |
5161 | ot = dflag ? OT_QUAD : OT_WORD; | |
5162 | } else { | |
5163 | ot = dflag + OT_WORD; | |
5164 | } | |
57fec1fe | 5165 | gen_op_mov_reg_T0(ot, R_EBP); |
2c0262af FB |
5166 | gen_pop_update(s); |
5167 | break; | |
5168 | case 0x06: /* push es */ | |
5169 | case 0x0e: /* push cs */ | |
5170 | case 0x16: /* push ss */ | |
5171 | case 0x1e: /* push ds */ | |
14ce26e7 FB |
5172 | if (CODE64(s)) |
5173 | goto illegal_op; | |
2c0262af FB |
5174 | gen_op_movl_T0_seg(b >> 3); |
5175 | gen_push_T0(s); | |
5176 | break; | |
5177 | case 0x1a0: /* push fs */ | |
5178 | case 0x1a8: /* push gs */ | |
5179 | gen_op_movl_T0_seg((b >> 3) & 7); | |
5180 | gen_push_T0(s); | |
5181 | break; | |
5182 | case 0x07: /* pop es */ | |
5183 | case 0x17: /* pop ss */ | |
5184 | case 0x1f: /* pop ds */ | |
14ce26e7 FB |
5185 | if (CODE64(s)) |
5186 | goto illegal_op; | |
2c0262af FB |
5187 | reg = b >> 3; |
5188 | gen_pop_T0(s); | |
5189 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5190 | gen_pop_update(s); | |
5191 | if (reg == R_SS) { | |
a2cc3b24 FB |
5192 | /* if reg == SS, inhibit interrupts/trace. */ |
5193 | /* If several instructions disable interrupts, only the | |
5194 | _first_ does it */ | |
5195 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5196 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5197 | s->tf = 0; |
5198 | } | |
5199 | if (s->is_jmp) { | |
14ce26e7 | 5200 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5201 | gen_eob(s); |
5202 | } | |
5203 | break; | |
5204 | case 0x1a1: /* pop fs */ | |
5205 | case 0x1a9: /* pop gs */ | |
5206 | gen_pop_T0(s); | |
5207 | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); | |
5208 | gen_pop_update(s); | |
5209 | if (s->is_jmp) { | |
14ce26e7 | 5210 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5211 | gen_eob(s); |
5212 | } | |
5213 | break; | |
5214 | ||
5215 | /**************************/ | |
5216 | /* mov */ | |
5217 | case 0x88: | |
5218 | case 0x89: /* mov Gv, Ev */ | |
5219 | if ((b & 1) == 0) | |
5220 | ot = OT_BYTE; | |
5221 | else | |
14ce26e7 | 5222 | ot = dflag + OT_WORD; |
0af10c86 | 5223 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5224 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5225 | |
2c0262af | 5226 | /* generate a generic store */ |
0af10c86 | 5227 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
2c0262af FB |
5228 | break; |
5229 | case 0xc6: | |
5230 | case 0xc7: /* mov Ev, Iv */ | |
5231 | if ((b & 1) == 0) | |
5232 | ot = OT_BYTE; | |
5233 | else | |
14ce26e7 | 5234 | ot = dflag + OT_WORD; |
0af10c86 | 5235 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5236 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5237 | if (mod != 3) { |
5238 | s->rip_offset = insn_const_size(ot); | |
0af10c86 | 5239 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 5240 | } |
0af10c86 | 5241 | val = insn_get(env, s, ot); |
2c0262af FB |
5242 | gen_op_movl_T0_im(val); |
5243 | if (mod != 3) | |
57fec1fe | 5244 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 5245 | else |
57fec1fe | 5246 | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); |
2c0262af FB |
5247 | break; |
5248 | case 0x8a: | |
5249 | case 0x8b: /* mov Ev, Gv */ | |
5250 | if ((b & 1) == 0) | |
5251 | ot = OT_BYTE; | |
5252 | else | |
14ce26e7 | 5253 | ot = OT_WORD + dflag; |
0af10c86 | 5254 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5255 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5256 | |
0af10c86 | 5257 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5258 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
5259 | break; |
5260 | case 0x8e: /* mov seg, Gv */ | |
0af10c86 | 5261 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5262 | reg = (modrm >> 3) & 7; |
5263 | if (reg >= 6 || reg == R_CS) | |
5264 | goto illegal_op; | |
0af10c86 | 5265 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
2c0262af FB |
5266 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
5267 | if (reg == R_SS) { | |
5268 | /* if reg == SS, inhibit interrupts/trace */ | |
a2cc3b24 FB |
5269 | /* If several instructions disable interrupts, only the |
5270 | _first_ does it */ | |
5271 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5272 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5273 | s->tf = 0; |
5274 | } | |
5275 | if (s->is_jmp) { | |
14ce26e7 | 5276 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5277 | gen_eob(s); |
5278 | } | |
5279 | break; | |
5280 | case 0x8c: /* mov Gv, seg */ | |
0af10c86 | 5281 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5282 | reg = (modrm >> 3) & 7; |
5283 | mod = (modrm >> 6) & 3; | |
5284 | if (reg >= 6) | |
5285 | goto illegal_op; | |
5286 | gen_op_movl_T0_seg(reg); | |
14ce26e7 FB |
5287 | if (mod == 3) |
5288 | ot = OT_WORD + dflag; | |
5289 | else | |
5290 | ot = OT_WORD; | |
0af10c86 | 5291 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
5292 | break; |
5293 | ||
5294 | case 0x1b6: /* movzbS Gv, Eb */ | |
5295 | case 0x1b7: /* movzwS Gv, Eb */ | |
5296 | case 0x1be: /* movsbS Gv, Eb */ | |
5297 | case 0x1bf: /* movswS Gv, Eb */ | |
5298 | { | |
5299 | int d_ot; | |
5300 | /* d_ot is the size of destination */ | |
5301 | d_ot = dflag + OT_WORD; | |
5302 | /* ot is the size of source */ | |
5303 | ot = (b & 1) + OT_BYTE; | |
0af10c86 | 5304 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5305 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 5306 | mod = (modrm >> 6) & 3; |
14ce26e7 | 5307 | rm = (modrm & 7) | REX_B(s); |
3b46e624 | 5308 | |
2c0262af | 5309 | if (mod == 3) { |
57fec1fe | 5310 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
5311 | switch(ot | (b & 8)) { |
5312 | case OT_BYTE: | |
e108dd01 | 5313 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5314 | break; |
5315 | case OT_BYTE | 8: | |
e108dd01 | 5316 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5317 | break; |
5318 | case OT_WORD: | |
e108dd01 | 5319 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5320 | break; |
5321 | default: | |
5322 | case OT_WORD | 8: | |
e108dd01 | 5323 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5324 | break; |
5325 | } | |
57fec1fe | 5326 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af | 5327 | } else { |
0af10c86 | 5328 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 5329 | if (b & 8) { |
57fec1fe | 5330 | gen_op_lds_T0_A0(ot + s->mem_index); |
2c0262af | 5331 | } else { |
57fec1fe | 5332 | gen_op_ldu_T0_A0(ot + s->mem_index); |
2c0262af | 5333 | } |
57fec1fe | 5334 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5335 | } |
5336 | } | |
5337 | break; | |
5338 | ||
5339 | case 0x8d: /* lea */ | |
14ce26e7 | 5340 | ot = dflag + OT_WORD; |
0af10c86 | 5341 | modrm = cpu_ldub_code(env, s->pc++); |
3a1d9b8b FB |
5342 | mod = (modrm >> 6) & 3; |
5343 | if (mod == 3) | |
5344 | goto illegal_op; | |
14ce26e7 | 5345 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5346 | /* we must ensure that no segment is added */ |
5347 | s->override = -1; | |
5348 | val = s->addseg; | |
5349 | s->addseg = 0; | |
0af10c86 | 5350 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 5351 | s->addseg = val; |
57fec1fe | 5352 | gen_op_mov_reg_A0(ot - OT_WORD, reg); |
2c0262af | 5353 | break; |
3b46e624 | 5354 | |
2c0262af FB |
5355 | case 0xa0: /* mov EAX, Ov */ |
5356 | case 0xa1: | |
5357 | case 0xa2: /* mov Ov, EAX */ | |
5358 | case 0xa3: | |
2c0262af | 5359 | { |
14ce26e7 FB |
5360 | target_ulong offset_addr; |
5361 | ||
5362 | if ((b & 1) == 0) | |
5363 | ot = OT_BYTE; | |
5364 | else | |
5365 | ot = dflag + OT_WORD; | |
5366 | #ifdef TARGET_X86_64 | |
8f091a59 | 5367 | if (s->aflag == 2) { |
0af10c86 | 5368 | offset_addr = cpu_ldq_code(env, s->pc); |
14ce26e7 | 5369 | s->pc += 8; |
57fec1fe | 5370 | gen_op_movq_A0_im(offset_addr); |
5fafdf24 | 5371 | } else |
14ce26e7 FB |
5372 | #endif |
5373 | { | |
5374 | if (s->aflag) { | |
0af10c86 | 5375 | offset_addr = insn_get(env, s, OT_LONG); |
14ce26e7 | 5376 | } else { |
0af10c86 | 5377 | offset_addr = insn_get(env, s, OT_WORD); |
14ce26e7 FB |
5378 | } |
5379 | gen_op_movl_A0_im(offset_addr); | |
5380 | } | |
664e0f19 | 5381 | gen_add_A0_ds_seg(s); |
14ce26e7 | 5382 | if ((b & 2) == 0) { |
57fec1fe FB |
5383 | gen_op_ld_T0_A0(ot + s->mem_index); |
5384 | gen_op_mov_reg_T0(ot, R_EAX); | |
14ce26e7 | 5385 | } else { |
57fec1fe FB |
5386 | gen_op_mov_TN_reg(ot, 0, R_EAX); |
5387 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af FB |
5388 | } |
5389 | } | |
2c0262af FB |
5390 | break; |
5391 | case 0xd7: /* xlat */ | |
14ce26e7 | 5392 | #ifdef TARGET_X86_64 |
8f091a59 | 5393 | if (s->aflag == 2) { |
57fec1fe | 5394 | gen_op_movq_A0_reg(R_EBX); |
bbf662ee FB |
5395 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
5396 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5397 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
5fafdf24 | 5398 | } else |
14ce26e7 FB |
5399 | #endif |
5400 | { | |
57fec1fe | 5401 | gen_op_movl_A0_reg(R_EBX); |
bbf662ee FB |
5402 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
5403 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5404 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
14ce26e7 FB |
5405 | if (s->aflag == 0) |
5406 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
5407 | else |
5408 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
14ce26e7 | 5409 | } |
664e0f19 | 5410 | gen_add_A0_ds_seg(s); |
57fec1fe FB |
5411 | gen_op_ldu_T0_A0(OT_BYTE + s->mem_index); |
5412 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
5413 | break; |
5414 | case 0xb0 ... 0xb7: /* mov R, Ib */ | |
0af10c86 | 5415 | val = insn_get(env, s, OT_BYTE); |
2c0262af | 5416 | gen_op_movl_T0_im(val); |
57fec1fe | 5417 | gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s)); |
2c0262af FB |
5418 | break; |
5419 | case 0xb8 ... 0xbf: /* mov R, Iv */ | |
14ce26e7 FB |
5420 | #ifdef TARGET_X86_64 |
5421 | if (dflag == 2) { | |
5422 | uint64_t tmp; | |
5423 | /* 64 bit case */ | |
0af10c86 | 5424 | tmp = cpu_ldq_code(env, s->pc); |
14ce26e7 FB |
5425 | s->pc += 8; |
5426 | reg = (b & 7) | REX_B(s); | |
5427 | gen_movtl_T0_im(tmp); | |
57fec1fe | 5428 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 5429 | } else |
14ce26e7 FB |
5430 | #endif |
5431 | { | |
5432 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 5433 | val = insn_get(env, s, ot); |
14ce26e7 FB |
5434 | reg = (b & 7) | REX_B(s); |
5435 | gen_op_movl_T0_im(val); | |
57fec1fe | 5436 | gen_op_mov_reg_T0(ot, reg); |
14ce26e7 | 5437 | } |
2c0262af FB |
5438 | break; |
5439 | ||
5440 | case 0x91 ... 0x97: /* xchg R, EAX */ | |
7418027e | 5441 | do_xchg_reg_eax: |
14ce26e7 FB |
5442 | ot = dflag + OT_WORD; |
5443 | reg = (b & 7) | REX_B(s); | |
2c0262af FB |
5444 | rm = R_EAX; |
5445 | goto do_xchg_reg; | |
5446 | case 0x86: | |
5447 | case 0x87: /* xchg Ev, Gv */ | |
5448 | if ((b & 1) == 0) | |
5449 | ot = OT_BYTE; | |
5450 | else | |
14ce26e7 | 5451 | ot = dflag + OT_WORD; |
0af10c86 | 5452 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5453 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5454 | mod = (modrm >> 6) & 3; |
5455 | if (mod == 3) { | |
14ce26e7 | 5456 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 5457 | do_xchg_reg: |
57fec1fe FB |
5458 | gen_op_mov_TN_reg(ot, 0, reg); |
5459 | gen_op_mov_TN_reg(ot, 1, rm); | |
5460 | gen_op_mov_reg_T0(ot, rm); | |
5461 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af | 5462 | } else { |
0af10c86 | 5463 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 5464 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af FB |
5465 | /* for xchg, lock is implicit */ |
5466 | if (!(prefixes & PREFIX_LOCK)) | |
a7812ae4 | 5467 | gen_helper_lock(); |
57fec1fe FB |
5468 | gen_op_ld_T1_A0(ot + s->mem_index); |
5469 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 5470 | if (!(prefixes & PREFIX_LOCK)) |
a7812ae4 | 5471 | gen_helper_unlock(); |
57fec1fe | 5472 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5473 | } |
5474 | break; | |
5475 | case 0xc4: /* les Gv */ | |
14ce26e7 FB |
5476 | if (CODE64(s)) |
5477 | goto illegal_op; | |
2c0262af FB |
5478 | op = R_ES; |
5479 | goto do_lxx; | |
5480 | case 0xc5: /* lds Gv */ | |
14ce26e7 FB |
5481 | if (CODE64(s)) |
5482 | goto illegal_op; | |
2c0262af FB |
5483 | op = R_DS; |
5484 | goto do_lxx; | |
5485 | case 0x1b2: /* lss Gv */ | |
5486 | op = R_SS; | |
5487 | goto do_lxx; | |
5488 | case 0x1b4: /* lfs Gv */ | |
5489 | op = R_FS; | |
5490 | goto do_lxx; | |
5491 | case 0x1b5: /* lgs Gv */ | |
5492 | op = R_GS; | |
5493 | do_lxx: | |
5494 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 5495 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5496 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5497 | mod = (modrm >> 6) & 3; |
5498 | if (mod == 3) | |
5499 | goto illegal_op; | |
0af10c86 | 5500 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 5501 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 5502 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
2c0262af | 5503 | /* load the segment first to handle exceptions properly */ |
57fec1fe | 5504 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5505 | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
5506 | /* then put the data */ | |
57fec1fe | 5507 | gen_op_mov_reg_T1(ot, reg); |
2c0262af | 5508 | if (s->is_jmp) { |
14ce26e7 | 5509 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5510 | gen_eob(s); |
5511 | } | |
5512 | break; | |
3b46e624 | 5513 | |
2c0262af FB |
5514 | /************************/ |
5515 | /* shifts */ | |
5516 | case 0xc0: | |
5517 | case 0xc1: | |
5518 | /* shift Ev,Ib */ | |
5519 | shift = 2; | |
5520 | grp2: | |
5521 | { | |
5522 | if ((b & 1) == 0) | |
5523 | ot = OT_BYTE; | |
5524 | else | |
14ce26e7 | 5525 | ot = dflag + OT_WORD; |
3b46e624 | 5526 | |
0af10c86 | 5527 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5528 | mod = (modrm >> 6) & 3; |
2c0262af | 5529 | op = (modrm >> 3) & 7; |
3b46e624 | 5530 | |
2c0262af | 5531 | if (mod != 3) { |
14ce26e7 FB |
5532 | if (shift == 2) { |
5533 | s->rip_offset = 1; | |
5534 | } | |
0af10c86 | 5535 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
5536 | opreg = OR_TMP0; |
5537 | } else { | |
14ce26e7 | 5538 | opreg = (modrm & 7) | REX_B(s); |
2c0262af FB |
5539 | } |
5540 | ||
5541 | /* simpler op */ | |
5542 | if (shift == 0) { | |
5543 | gen_shift(s, op, ot, opreg, OR_ECX); | |
5544 | } else { | |
5545 | if (shift == 2) { | |
0af10c86 | 5546 | shift = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5547 | } |
5548 | gen_shifti(s, op, ot, opreg, shift); | |
5549 | } | |
5550 | } | |
5551 | break; | |
5552 | case 0xd0: | |
5553 | case 0xd1: | |
5554 | /* shift Ev,1 */ | |
5555 | shift = 1; | |
5556 | goto grp2; | |
5557 | case 0xd2: | |
5558 | case 0xd3: | |
5559 | /* shift Ev,cl */ | |
5560 | shift = 0; | |
5561 | goto grp2; | |
5562 | ||
5563 | case 0x1a4: /* shld imm */ | |
5564 | op = 0; | |
5565 | shift = 1; | |
5566 | goto do_shiftd; | |
5567 | case 0x1a5: /* shld cl */ | |
5568 | op = 0; | |
5569 | shift = 0; | |
5570 | goto do_shiftd; | |
5571 | case 0x1ac: /* shrd imm */ | |
5572 | op = 1; | |
5573 | shift = 1; | |
5574 | goto do_shiftd; | |
5575 | case 0x1ad: /* shrd cl */ | |
5576 | op = 1; | |
5577 | shift = 0; | |
5578 | do_shiftd: | |
14ce26e7 | 5579 | ot = dflag + OT_WORD; |
0af10c86 | 5580 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5581 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5582 | rm = (modrm & 7) | REX_B(s); |
5583 | reg = ((modrm >> 3) & 7) | rex_r; | |
2c0262af | 5584 | if (mod != 3) { |
0af10c86 | 5585 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
b6abf97d | 5586 | opreg = OR_TMP0; |
2c0262af | 5587 | } else { |
b6abf97d | 5588 | opreg = rm; |
2c0262af | 5589 | } |
57fec1fe | 5590 | gen_op_mov_TN_reg(ot, 1, reg); |
3b46e624 | 5591 | |
2c0262af | 5592 | if (shift) { |
3b9d3cf1 PB |
5593 | TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++)); |
5594 | gen_shiftd_rm_T1(s, ot, opreg, op, imm); | |
5595 | tcg_temp_free(imm); | |
2c0262af | 5596 | } else { |
3b9d3cf1 | 5597 | gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); |
2c0262af FB |
5598 | } |
5599 | break; | |
5600 | ||
5601 | /************************/ | |
5602 | /* floats */ | |
5fafdf24 | 5603 | case 0xd8 ... 0xdf: |
7eee2a50 FB |
5604 | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { |
5605 | /* if CR0.EM or CR0.TS are set, generate an FPU exception */ | |
5606 | /* XXX: what to do if illegal op ? */ | |
5607 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
5608 | break; | |
5609 | } | |
0af10c86 | 5610 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5611 | mod = (modrm >> 6) & 3; |
5612 | rm = modrm & 7; | |
5613 | op = ((b & 7) << 3) | ((modrm >> 3) & 7); | |
2c0262af FB |
5614 | if (mod != 3) { |
5615 | /* memory op */ | |
0af10c86 | 5616 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
5617 | switch(op) { |
5618 | case 0x00 ... 0x07: /* fxxxs */ | |
5619 | case 0x10 ... 0x17: /* fixxxl */ | |
5620 | case 0x20 ... 0x27: /* fxxxl */ | |
5621 | case 0x30 ... 0x37: /* fixxx */ | |
5622 | { | |
5623 | int op1; | |
5624 | op1 = op & 7; | |
5625 | ||
5626 | switch(op >> 4) { | |
5627 | case 0: | |
ba7cd150 | 5628 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5629 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5630 | gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5631 | break; |
5632 | case 1: | |
ba7cd150 | 5633 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5634 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5635 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5636 | break; |
5637 | case 2: | |
b6abf97d | 5638 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5639 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5640 | gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5641 | break; |
5642 | case 3: | |
5643 | default: | |
ba7cd150 | 5644 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5645 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5646 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5647 | break; |
5648 | } | |
3b46e624 | 5649 | |
a7812ae4 | 5650 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5651 | if (op1 == 3) { |
5652 | /* fcomp needs pop */ | |
d3eb5eae | 5653 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5654 | } |
5655 | } | |
5656 | break; | |
5657 | case 0x08: /* flds */ | |
5658 | case 0x0a: /* fsts */ | |
5659 | case 0x0b: /* fstps */ | |
465e9838 FB |
5660 | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
5661 | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ | |
5662 | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ | |
2c0262af FB |
5663 | switch(op & 7) { |
5664 | case 0: | |
5665 | switch(op >> 4) { | |
5666 | case 0: | |
ba7cd150 | 5667 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5668 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5669 | gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5670 | break; |
5671 | case 1: | |
ba7cd150 | 5672 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5673 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5674 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5675 | break; |
5676 | case 2: | |
b6abf97d | 5677 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5678 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5679 | gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5680 | break; |
5681 | case 3: | |
5682 | default: | |
ba7cd150 | 5683 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5684 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5685 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5686 | break; |
5687 | } | |
5688 | break; | |
465e9838 | 5689 | case 1: |
19e6c4b8 | 5690 | /* XXX: the corresponding CPUID bit must be tested ! */ |
465e9838 FB |
5691 | switch(op >> 4) { |
5692 | case 1: | |
d3eb5eae | 5693 | gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5694 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5695 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
465e9838 FB |
5696 | break; |
5697 | case 2: | |
d3eb5eae | 5698 | gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5699 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5700 | (s->mem_index >> 2) - 1); |
465e9838 FB |
5701 | break; |
5702 | case 3: | |
5703 | default: | |
d3eb5eae | 5704 | gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5705 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5706 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
19e6c4b8 | 5707 | break; |
465e9838 | 5708 | } |
d3eb5eae | 5709 | gen_helper_fpop(cpu_env); |
465e9838 | 5710 | break; |
2c0262af FB |
5711 | default: |
5712 | switch(op >> 4) { | |
5713 | case 0: | |
d3eb5eae | 5714 | gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5715 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5716 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5717 | break; |
5718 | case 1: | |
d3eb5eae | 5719 | gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5720 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5721 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5722 | break; |
5723 | case 2: | |
d3eb5eae | 5724 | gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5725 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5726 | (s->mem_index >> 2) - 1); |
2c0262af FB |
5727 | break; |
5728 | case 3: | |
5729 | default: | |
d3eb5eae | 5730 | gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5731 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5732 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5733 | break; |
5734 | } | |
5735 | if ((op & 7) == 3) | |
d3eb5eae | 5736 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5737 | break; |
5738 | } | |
5739 | break; | |
5740 | case 0x0c: /* fldenv mem */ | |
773cdfcc | 5741 | gen_update_cc_op(s); |
19e6c4b8 | 5742 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5743 | gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5744 | break; |
5745 | case 0x0d: /* fldcw mem */ | |
19e6c4b8 | 5746 | gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5747 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5748 | gen_helper_fldcw(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5749 | break; |
5750 | case 0x0e: /* fnstenv mem */ | |
773cdfcc | 5751 | gen_update_cc_op(s); |
19e6c4b8 | 5752 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5753 | gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5754 | break; |
5755 | case 0x0f: /* fnstcw mem */ | |
d3eb5eae | 5756 | gen_helper_fnstcw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5757 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5758 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5759 | break; |
5760 | case 0x1d: /* fldt mem */ | |
773cdfcc | 5761 | gen_update_cc_op(s); |
19e6c4b8 | 5762 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5763 | gen_helper_fldt_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5764 | break; |
5765 | case 0x1f: /* fstpt mem */ | |
773cdfcc | 5766 | gen_update_cc_op(s); |
19e6c4b8 | 5767 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
5768 | gen_helper_fstt_ST0(cpu_env, cpu_A0); |
5769 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5770 | break; |
5771 | case 0x2c: /* frstor mem */ | |
773cdfcc | 5772 | gen_update_cc_op(s); |
19e6c4b8 | 5773 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5774 | gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5775 | break; |
5776 | case 0x2e: /* fnsave mem */ | |
773cdfcc | 5777 | gen_update_cc_op(s); |
19e6c4b8 | 5778 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5779 | gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5780 | break; |
5781 | case 0x2f: /* fnstsw mem */ | |
d3eb5eae | 5782 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5783 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5784 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5785 | break; |
5786 | case 0x3c: /* fbld */ | |
773cdfcc | 5787 | gen_update_cc_op(s); |
19e6c4b8 | 5788 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5789 | gen_helper_fbld_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5790 | break; |
5791 | case 0x3e: /* fbstp */ | |
773cdfcc | 5792 | gen_update_cc_op(s); |
19e6c4b8 | 5793 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
5794 | gen_helper_fbst_ST0(cpu_env, cpu_A0); |
5795 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5796 | break; |
5797 | case 0x3d: /* fildll */ | |
b6abf97d | 5798 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5799 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5800 | gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5801 | break; |
5802 | case 0x3f: /* fistpll */ | |
d3eb5eae | 5803 | gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5804 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5805 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5806 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5807 | break; |
5808 | default: | |
5809 | goto illegal_op; | |
5810 | } | |
5811 | } else { | |
5812 | /* register float ops */ | |
5813 | opreg = rm; | |
5814 | ||
5815 | switch(op) { | |
5816 | case 0x08: /* fld sti */ | |
d3eb5eae BS |
5817 | gen_helper_fpush(cpu_env); |
5818 | gen_helper_fmov_ST0_STN(cpu_env, | |
5819 | tcg_const_i32((opreg + 1) & 7)); | |
2c0262af FB |
5820 | break; |
5821 | case 0x09: /* fxchg sti */ | |
c169c906 FB |
5822 | case 0x29: /* fxchg4 sti, undocumented op */ |
5823 | case 0x39: /* fxchg7 sti, undocumented op */ | |
d3eb5eae | 5824 | gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
5825 | break; |
5826 | case 0x0a: /* grp d9/2 */ | |
5827 | switch(rm) { | |
5828 | case 0: /* fnop */ | |
023fe10d | 5829 | /* check exceptions (FreeBSD FPU probe) */ |
773cdfcc | 5830 | gen_update_cc_op(s); |
14ce26e7 | 5831 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5832 | gen_helper_fwait(cpu_env); |
2c0262af FB |
5833 | break; |
5834 | default: | |
5835 | goto illegal_op; | |
5836 | } | |
5837 | break; | |
5838 | case 0x0c: /* grp d9/4 */ | |
5839 | switch(rm) { | |
5840 | case 0: /* fchs */ | |
d3eb5eae | 5841 | gen_helper_fchs_ST0(cpu_env); |
2c0262af FB |
5842 | break; |
5843 | case 1: /* fabs */ | |
d3eb5eae | 5844 | gen_helper_fabs_ST0(cpu_env); |
2c0262af FB |
5845 | break; |
5846 | case 4: /* ftst */ | |
d3eb5eae BS |
5847 | gen_helper_fldz_FT0(cpu_env); |
5848 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
5849 | break; |
5850 | case 5: /* fxam */ | |
d3eb5eae | 5851 | gen_helper_fxam_ST0(cpu_env); |
2c0262af FB |
5852 | break; |
5853 | default: | |
5854 | goto illegal_op; | |
5855 | } | |
5856 | break; | |
5857 | case 0x0d: /* grp d9/5 */ | |
5858 | { | |
5859 | switch(rm) { | |
5860 | case 0: | |
d3eb5eae BS |
5861 | gen_helper_fpush(cpu_env); |
5862 | gen_helper_fld1_ST0(cpu_env); | |
2c0262af FB |
5863 | break; |
5864 | case 1: | |
d3eb5eae BS |
5865 | gen_helper_fpush(cpu_env); |
5866 | gen_helper_fldl2t_ST0(cpu_env); | |
2c0262af FB |
5867 | break; |
5868 | case 2: | |
d3eb5eae BS |
5869 | gen_helper_fpush(cpu_env); |
5870 | gen_helper_fldl2e_ST0(cpu_env); | |
2c0262af FB |
5871 | break; |
5872 | case 3: | |
d3eb5eae BS |
5873 | gen_helper_fpush(cpu_env); |
5874 | gen_helper_fldpi_ST0(cpu_env); | |
2c0262af FB |
5875 | break; |
5876 | case 4: | |
d3eb5eae BS |
5877 | gen_helper_fpush(cpu_env); |
5878 | gen_helper_fldlg2_ST0(cpu_env); | |
2c0262af FB |
5879 | break; |
5880 | case 5: | |
d3eb5eae BS |
5881 | gen_helper_fpush(cpu_env); |
5882 | gen_helper_fldln2_ST0(cpu_env); | |
2c0262af FB |
5883 | break; |
5884 | case 6: | |
d3eb5eae BS |
5885 | gen_helper_fpush(cpu_env); |
5886 | gen_helper_fldz_ST0(cpu_env); | |
2c0262af FB |
5887 | break; |
5888 | default: | |
5889 | goto illegal_op; | |
5890 | } | |
5891 | } | |
5892 | break; | |
5893 | case 0x0e: /* grp d9/6 */ | |
5894 | switch(rm) { | |
5895 | case 0: /* f2xm1 */ | |
d3eb5eae | 5896 | gen_helper_f2xm1(cpu_env); |
2c0262af FB |
5897 | break; |
5898 | case 1: /* fyl2x */ | |
d3eb5eae | 5899 | gen_helper_fyl2x(cpu_env); |
2c0262af FB |
5900 | break; |
5901 | case 2: /* fptan */ | |
d3eb5eae | 5902 | gen_helper_fptan(cpu_env); |
2c0262af FB |
5903 | break; |
5904 | case 3: /* fpatan */ | |
d3eb5eae | 5905 | gen_helper_fpatan(cpu_env); |
2c0262af FB |
5906 | break; |
5907 | case 4: /* fxtract */ | |
d3eb5eae | 5908 | gen_helper_fxtract(cpu_env); |
2c0262af FB |
5909 | break; |
5910 | case 5: /* fprem1 */ | |
d3eb5eae | 5911 | gen_helper_fprem1(cpu_env); |
2c0262af FB |
5912 | break; |
5913 | case 6: /* fdecstp */ | |
d3eb5eae | 5914 | gen_helper_fdecstp(cpu_env); |
2c0262af FB |
5915 | break; |
5916 | default: | |
5917 | case 7: /* fincstp */ | |
d3eb5eae | 5918 | gen_helper_fincstp(cpu_env); |
2c0262af FB |
5919 | break; |
5920 | } | |
5921 | break; | |
5922 | case 0x0f: /* grp d9/7 */ | |
5923 | switch(rm) { | |
5924 | case 0: /* fprem */ | |
d3eb5eae | 5925 | gen_helper_fprem(cpu_env); |
2c0262af FB |
5926 | break; |
5927 | case 1: /* fyl2xp1 */ | |
d3eb5eae | 5928 | gen_helper_fyl2xp1(cpu_env); |
2c0262af FB |
5929 | break; |
5930 | case 2: /* fsqrt */ | |
d3eb5eae | 5931 | gen_helper_fsqrt(cpu_env); |
2c0262af FB |
5932 | break; |
5933 | case 3: /* fsincos */ | |
d3eb5eae | 5934 | gen_helper_fsincos(cpu_env); |
2c0262af FB |
5935 | break; |
5936 | case 5: /* fscale */ | |
d3eb5eae | 5937 | gen_helper_fscale(cpu_env); |
2c0262af FB |
5938 | break; |
5939 | case 4: /* frndint */ | |
d3eb5eae | 5940 | gen_helper_frndint(cpu_env); |
2c0262af FB |
5941 | break; |
5942 | case 6: /* fsin */ | |
d3eb5eae | 5943 | gen_helper_fsin(cpu_env); |
2c0262af FB |
5944 | break; |
5945 | default: | |
5946 | case 7: /* fcos */ | |
d3eb5eae | 5947 | gen_helper_fcos(cpu_env); |
2c0262af FB |
5948 | break; |
5949 | } | |
5950 | break; | |
5951 | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ | |
5952 | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ | |
5953 | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ | |
5954 | { | |
5955 | int op1; | |
3b46e624 | 5956 | |
2c0262af FB |
5957 | op1 = op & 7; |
5958 | if (op >= 0x20) { | |
a7812ae4 | 5959 | gen_helper_fp_arith_STN_ST0(op1, opreg); |
2c0262af | 5960 | if (op >= 0x30) |
d3eb5eae | 5961 | gen_helper_fpop(cpu_env); |
2c0262af | 5962 | } else { |
d3eb5eae | 5963 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
a7812ae4 | 5964 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5965 | } |
5966 | } | |
5967 | break; | |
5968 | case 0x02: /* fcom */ | |
c169c906 | 5969 | case 0x22: /* fcom2, undocumented op */ |
d3eb5eae BS |
5970 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5971 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
5972 | break; |
5973 | case 0x03: /* fcomp */ | |
c169c906 FB |
5974 | case 0x23: /* fcomp3, undocumented op */ |
5975 | case 0x32: /* fcomp5, undocumented op */ | |
d3eb5eae BS |
5976 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5977 | gen_helper_fcom_ST0_FT0(cpu_env); | |
5978 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5979 | break; |
5980 | case 0x15: /* da/5 */ | |
5981 | switch(rm) { | |
5982 | case 1: /* fucompp */ | |
d3eb5eae BS |
5983 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
5984 | gen_helper_fucom_ST0_FT0(cpu_env); | |
5985 | gen_helper_fpop(cpu_env); | |
5986 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5987 | break; |
5988 | default: | |
5989 | goto illegal_op; | |
5990 | } | |
5991 | break; | |
5992 | case 0x1c: | |
5993 | switch(rm) { | |
5994 | case 0: /* feni (287 only, just do nop here) */ | |
5995 | break; | |
5996 | case 1: /* fdisi (287 only, just do nop here) */ | |
5997 | break; | |
5998 | case 2: /* fclex */ | |
d3eb5eae | 5999 | gen_helper_fclex(cpu_env); |
2c0262af FB |
6000 | break; |
6001 | case 3: /* fninit */ | |
d3eb5eae | 6002 | gen_helper_fninit(cpu_env); |
2c0262af FB |
6003 | break; |
6004 | case 4: /* fsetpm (287 only, just do nop here) */ | |
6005 | break; | |
6006 | default: | |
6007 | goto illegal_op; | |
6008 | } | |
6009 | break; | |
6010 | case 0x1d: /* fucomi */ | |
773cdfcc | 6011 | gen_update_cc_op(s); |
d3eb5eae BS |
6012 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6013 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
3ca51d07 | 6014 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6015 | break; |
6016 | case 0x1e: /* fcomi */ | |
773cdfcc | 6017 | gen_update_cc_op(s); |
d3eb5eae BS |
6018 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6019 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
3ca51d07 | 6020 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 6021 | break; |
658c8bda | 6022 | case 0x28: /* ffree sti */ |
d3eb5eae | 6023 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
5fafdf24 | 6024 | break; |
2c0262af | 6025 | case 0x2a: /* fst sti */ |
d3eb5eae | 6026 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
6027 | break; |
6028 | case 0x2b: /* fstp sti */ | |
c169c906 FB |
6029 | case 0x0b: /* fstp1 sti, undocumented op */ |
6030 | case 0x3a: /* fstp8 sti, undocumented op */ | |
6031 | case 0x3b: /* fstp9 sti, undocumented op */ | |
d3eb5eae BS |
6032 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
6033 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6034 | break; |
6035 | case 0x2c: /* fucom st(i) */ | |
d3eb5eae BS |
6036 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6037 | gen_helper_fucom_ST0_FT0(cpu_env); | |
2c0262af FB |
6038 | break; |
6039 | case 0x2d: /* fucomp st(i) */ | |
d3eb5eae BS |
6040 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6041 | gen_helper_fucom_ST0_FT0(cpu_env); | |
6042 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6043 | break; |
6044 | case 0x33: /* de/3 */ | |
6045 | switch(rm) { | |
6046 | case 1: /* fcompp */ | |
d3eb5eae BS |
6047 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
6048 | gen_helper_fcom_ST0_FT0(cpu_env); | |
6049 | gen_helper_fpop(cpu_env); | |
6050 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6051 | break; |
6052 | default: | |
6053 | goto illegal_op; | |
6054 | } | |
6055 | break; | |
c169c906 | 6056 | case 0x38: /* ffreep sti, undocumented op */ |
d3eb5eae BS |
6057 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
6058 | gen_helper_fpop(cpu_env); | |
c169c906 | 6059 | break; |
2c0262af FB |
6060 | case 0x3c: /* df/4 */ |
6061 | switch(rm) { | |
6062 | case 0: | |
d3eb5eae | 6063 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 6064 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 6065 | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
2c0262af FB |
6066 | break; |
6067 | default: | |
6068 | goto illegal_op; | |
6069 | } | |
6070 | break; | |
6071 | case 0x3d: /* fucomip */ | |
773cdfcc | 6072 | gen_update_cc_op(s); |
d3eb5eae BS |
6073 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6074 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
6075 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 6076 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6077 | break; |
6078 | case 0x3e: /* fcomip */ | |
773cdfcc | 6079 | gen_update_cc_op(s); |
d3eb5eae BS |
6080 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6081 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
6082 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 6083 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 6084 | break; |
a2cc3b24 FB |
6085 | case 0x10 ... 0x13: /* fcmovxx */ |
6086 | case 0x18 ... 0x1b: | |
6087 | { | |
19e6c4b8 | 6088 | int op1, l1; |
d70040bc | 6089 | static const uint8_t fcmov_cc[8] = { |
a2cc3b24 FB |
6090 | (JCC_B << 1), |
6091 | (JCC_Z << 1), | |
6092 | (JCC_BE << 1), | |
6093 | (JCC_P << 1), | |
6094 | }; | |
1e4840bf | 6095 | op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); |
19e6c4b8 | 6096 | l1 = gen_new_label(); |
dc259201 | 6097 | gen_jcc1_noeob(s, op1, l1); |
d3eb5eae | 6098 | gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
19e6c4b8 | 6099 | gen_set_label(l1); |
a2cc3b24 FB |
6100 | } |
6101 | break; | |
2c0262af FB |
6102 | default: |
6103 | goto illegal_op; | |
6104 | } | |
6105 | } | |
6106 | break; | |
6107 | /************************/ | |
6108 | /* string ops */ | |
6109 | ||
6110 | case 0xa4: /* movsS */ | |
6111 | case 0xa5: | |
6112 | if ((b & 1) == 0) | |
6113 | ot = OT_BYTE; | |
6114 | else | |
14ce26e7 | 6115 | ot = dflag + OT_WORD; |
2c0262af FB |
6116 | |
6117 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6118 | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6119 | } else { | |
6120 | gen_movs(s, ot); | |
6121 | } | |
6122 | break; | |
3b46e624 | 6123 | |
2c0262af FB |
6124 | case 0xaa: /* stosS */ |
6125 | case 0xab: | |
6126 | if ((b & 1) == 0) | |
6127 | ot = OT_BYTE; | |
6128 | else | |
14ce26e7 | 6129 | ot = dflag + OT_WORD; |
2c0262af FB |
6130 | |
6131 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6132 | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6133 | } else { | |
6134 | gen_stos(s, ot); | |
6135 | } | |
6136 | break; | |
6137 | case 0xac: /* lodsS */ | |
6138 | case 0xad: | |
6139 | if ((b & 1) == 0) | |
6140 | ot = OT_BYTE; | |
6141 | else | |
14ce26e7 | 6142 | ot = dflag + OT_WORD; |
2c0262af FB |
6143 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6144 | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6145 | } else { | |
6146 | gen_lods(s, ot); | |
6147 | } | |
6148 | break; | |
6149 | case 0xae: /* scasS */ | |
6150 | case 0xaf: | |
6151 | if ((b & 1) == 0) | |
6152 | ot = OT_BYTE; | |
6153 | else | |
14ce26e7 | 6154 | ot = dflag + OT_WORD; |
2c0262af FB |
6155 | if (prefixes & PREFIX_REPNZ) { |
6156 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6157 | } else if (prefixes & PREFIX_REPZ) { | |
6158 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6159 | } else { | |
6160 | gen_scas(s, ot); | |
2c0262af FB |
6161 | } |
6162 | break; | |
6163 | ||
6164 | case 0xa6: /* cmpsS */ | |
6165 | case 0xa7: | |
6166 | if ((b & 1) == 0) | |
6167 | ot = OT_BYTE; | |
6168 | else | |
14ce26e7 | 6169 | ot = dflag + OT_WORD; |
2c0262af FB |
6170 | if (prefixes & PREFIX_REPNZ) { |
6171 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6172 | } else if (prefixes & PREFIX_REPZ) { | |
6173 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6174 | } else { | |
6175 | gen_cmps(s, ot); | |
2c0262af FB |
6176 | } |
6177 | break; | |
6178 | case 0x6c: /* insS */ | |
6179 | case 0x6d: | |
f115e911 FB |
6180 | if ((b & 1) == 0) |
6181 | ot = OT_BYTE; | |
6182 | else | |
6183 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6184 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6185 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6186 | gen_check_io(s, ot, pc_start - s->cs_base, |
6187 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6188 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6189 | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6190 | } else { |
f115e911 | 6191 | gen_ins(s, ot); |
2e70f6ef PB |
6192 | if (use_icount) { |
6193 | gen_jmp(s, s->pc - s->cs_base); | |
6194 | } | |
2c0262af FB |
6195 | } |
6196 | break; | |
6197 | case 0x6e: /* outsS */ | |
6198 | case 0x6f: | |
f115e911 FB |
6199 | if ((b & 1) == 0) |
6200 | ot = OT_BYTE; | |
6201 | else | |
6202 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6203 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6204 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6205 | gen_check_io(s, ot, pc_start - s->cs_base, |
6206 | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6207 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6208 | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6209 | } else { |
f115e911 | 6210 | gen_outs(s, ot); |
2e70f6ef PB |
6211 | if (use_icount) { |
6212 | gen_jmp(s, s->pc - s->cs_base); | |
6213 | } | |
2c0262af FB |
6214 | } |
6215 | break; | |
6216 | ||
6217 | /************************/ | |
6218 | /* port I/O */ | |
0573fbfc | 6219 | |
2c0262af FB |
6220 | case 0xe4: |
6221 | case 0xe5: | |
f115e911 FB |
6222 | if ((b & 1) == 0) |
6223 | ot = OT_BYTE; | |
6224 | else | |
6225 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 6226 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6227 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6228 | gen_check_io(s, ot, pc_start - s->cs_base, |
6229 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6230 | if (use_icount) |
6231 | gen_io_start(); | |
b6abf97d | 6232 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6233 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6234 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6235 | if (use_icount) { |
6236 | gen_io_end(); | |
6237 | gen_jmp(s, s->pc - s->cs_base); | |
6238 | } | |
2c0262af FB |
6239 | break; |
6240 | case 0xe6: | |
6241 | case 0xe7: | |
f115e911 FB |
6242 | if ((b & 1) == 0) |
6243 | ot = OT_BYTE; | |
6244 | else | |
6245 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 6246 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6247 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6248 | gen_check_io(s, ot, pc_start - s->cs_base, |
6249 | svm_is_rep(prefixes)); | |
57fec1fe | 6250 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6251 | |
2e70f6ef PB |
6252 | if (use_icount) |
6253 | gen_io_start(); | |
b6abf97d | 6254 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6255 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6256 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6257 | if (use_icount) { |
6258 | gen_io_end(); | |
6259 | gen_jmp(s, s->pc - s->cs_base); | |
6260 | } | |
2c0262af FB |
6261 | break; |
6262 | case 0xec: | |
6263 | case 0xed: | |
f115e911 FB |
6264 | if ((b & 1) == 0) |
6265 | ot = OT_BYTE; | |
6266 | else | |
6267 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6268 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6269 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6270 | gen_check_io(s, ot, pc_start - s->cs_base, |
6271 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6272 | if (use_icount) |
6273 | gen_io_start(); | |
b6abf97d | 6274 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6275 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6276 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6277 | if (use_icount) { |
6278 | gen_io_end(); | |
6279 | gen_jmp(s, s->pc - s->cs_base); | |
6280 | } | |
2c0262af FB |
6281 | break; |
6282 | case 0xee: | |
6283 | case 0xef: | |
f115e911 FB |
6284 | if ((b & 1) == 0) |
6285 | ot = OT_BYTE; | |
6286 | else | |
6287 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6288 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6289 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6290 | gen_check_io(s, ot, pc_start - s->cs_base, |
6291 | svm_is_rep(prefixes)); | |
57fec1fe | 6292 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6293 | |
2e70f6ef PB |
6294 | if (use_icount) |
6295 | gen_io_start(); | |
b6abf97d | 6296 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6297 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6298 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6299 | if (use_icount) { |
6300 | gen_io_end(); | |
6301 | gen_jmp(s, s->pc - s->cs_base); | |
6302 | } | |
2c0262af FB |
6303 | break; |
6304 | ||
6305 | /************************/ | |
6306 | /* control */ | |
6307 | case 0xc2: /* ret im */ | |
0af10c86 | 6308 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6309 | s->pc += 2; |
6310 | gen_pop_T0(s); | |
8f091a59 FB |
6311 | if (CODE64(s) && s->dflag) |
6312 | s->dflag = 2; | |
2c0262af FB |
6313 | gen_stack_update(s, val + (2 << s->dflag)); |
6314 | if (s->dflag == 0) | |
6315 | gen_op_andl_T0_ffff(); | |
6316 | gen_op_jmp_T0(); | |
6317 | gen_eob(s); | |
6318 | break; | |
6319 | case 0xc3: /* ret */ | |
6320 | gen_pop_T0(s); | |
6321 | gen_pop_update(s); | |
6322 | if (s->dflag == 0) | |
6323 | gen_op_andl_T0_ffff(); | |
6324 | gen_op_jmp_T0(); | |
6325 | gen_eob(s); | |
6326 | break; | |
6327 | case 0xca: /* lret im */ | |
0af10c86 | 6328 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6329 | s->pc += 2; |
6330 | do_lret: | |
6331 | if (s->pe && !s->vm86) { | |
773cdfcc | 6332 | gen_update_cc_op(s); |
14ce26e7 | 6333 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6334 | gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6335 | tcg_const_i32(val)); |
2c0262af FB |
6336 | } else { |
6337 | gen_stack_A0(s); | |
6338 | /* pop offset */ | |
57fec1fe | 6339 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
2c0262af FB |
6340 | if (s->dflag == 0) |
6341 | gen_op_andl_T0_ffff(); | |
6342 | /* NOTE: keeping EIP updated is not a problem in case of | |
6343 | exception */ | |
6344 | gen_op_jmp_T0(); | |
6345 | /* pop selector */ | |
6346 | gen_op_addl_A0_im(2 << s->dflag); | |
57fec1fe | 6347 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
3bd7da9e | 6348 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
6349 | /* add stack offset */ |
6350 | gen_stack_update(s, val + (4 << s->dflag)); | |
6351 | } | |
6352 | gen_eob(s); | |
6353 | break; | |
6354 | case 0xcb: /* lret */ | |
6355 | val = 0; | |
6356 | goto do_lret; | |
6357 | case 0xcf: /* iret */ | |
872929aa | 6358 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); |
2c0262af FB |
6359 | if (!s->pe) { |
6360 | /* real mode */ | |
2999a0b2 | 6361 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
3ca51d07 | 6362 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 FB |
6363 | } else if (s->vm86) { |
6364 | if (s->iopl != 3) { | |
6365 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6366 | } else { | |
2999a0b2 | 6367 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
3ca51d07 | 6368 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 6369 | } |
2c0262af | 6370 | } else { |
773cdfcc | 6371 | gen_update_cc_op(s); |
14ce26e7 | 6372 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6373 | gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6374 | tcg_const_i32(s->pc - s->cs_base)); |
3ca51d07 | 6375 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6376 | } |
6377 | gen_eob(s); | |
6378 | break; | |
6379 | case 0xe8: /* call im */ | |
6380 | { | |
14ce26e7 | 6381 | if (dflag) |
0af10c86 | 6382 | tval = (int32_t)insn_get(env, s, OT_LONG); |
14ce26e7 | 6383 | else |
0af10c86 | 6384 | tval = (int16_t)insn_get(env, s, OT_WORD); |
2c0262af | 6385 | next_eip = s->pc - s->cs_base; |
14ce26e7 | 6386 | tval += next_eip; |
2c0262af | 6387 | if (s->dflag == 0) |
14ce26e7 | 6388 | tval &= 0xffff; |
99596385 AJ |
6389 | else if(!CODE64(s)) |
6390 | tval &= 0xffffffff; | |
14ce26e7 | 6391 | gen_movtl_T0_im(next_eip); |
2c0262af | 6392 | gen_push_T0(s); |
14ce26e7 | 6393 | gen_jmp(s, tval); |
2c0262af FB |
6394 | } |
6395 | break; | |
6396 | case 0x9a: /* lcall im */ | |
6397 | { | |
6398 | unsigned int selector, offset; | |
3b46e624 | 6399 | |
14ce26e7 FB |
6400 | if (CODE64(s)) |
6401 | goto illegal_op; | |
2c0262af | 6402 | ot = dflag ? OT_LONG : OT_WORD; |
0af10c86 BS |
6403 | offset = insn_get(env, s, ot); |
6404 | selector = insn_get(env, s, OT_WORD); | |
3b46e624 | 6405 | |
2c0262af | 6406 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6407 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6408 | } |
6409 | goto do_lcall; | |
ecada8a2 | 6410 | case 0xe9: /* jmp im */ |
14ce26e7 | 6411 | if (dflag) |
0af10c86 | 6412 | tval = (int32_t)insn_get(env, s, OT_LONG); |
14ce26e7 | 6413 | else |
0af10c86 | 6414 | tval = (int16_t)insn_get(env, s, OT_WORD); |
14ce26e7 | 6415 | tval += s->pc - s->cs_base; |
2c0262af | 6416 | if (s->dflag == 0) |
14ce26e7 | 6417 | tval &= 0xffff; |
32938e12 AJ |
6418 | else if(!CODE64(s)) |
6419 | tval &= 0xffffffff; | |
14ce26e7 | 6420 | gen_jmp(s, tval); |
2c0262af FB |
6421 | break; |
6422 | case 0xea: /* ljmp im */ | |
6423 | { | |
6424 | unsigned int selector, offset; | |
6425 | ||
14ce26e7 FB |
6426 | if (CODE64(s)) |
6427 | goto illegal_op; | |
2c0262af | 6428 | ot = dflag ? OT_LONG : OT_WORD; |
0af10c86 BS |
6429 | offset = insn_get(env, s, ot); |
6430 | selector = insn_get(env, s, OT_WORD); | |
3b46e624 | 6431 | |
2c0262af | 6432 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6433 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6434 | } |
6435 | goto do_ljmp; | |
6436 | case 0xeb: /* jmp Jb */ | |
0af10c86 | 6437 | tval = (int8_t)insn_get(env, s, OT_BYTE); |
14ce26e7 | 6438 | tval += s->pc - s->cs_base; |
2c0262af | 6439 | if (s->dflag == 0) |
14ce26e7 FB |
6440 | tval &= 0xffff; |
6441 | gen_jmp(s, tval); | |
2c0262af FB |
6442 | break; |
6443 | case 0x70 ... 0x7f: /* jcc Jb */ | |
0af10c86 | 6444 | tval = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
6445 | goto do_jcc; |
6446 | case 0x180 ... 0x18f: /* jcc Jv */ | |
6447 | if (dflag) { | |
0af10c86 | 6448 | tval = (int32_t)insn_get(env, s, OT_LONG); |
2c0262af | 6449 | } else { |
0af10c86 | 6450 | tval = (int16_t)insn_get(env, s, OT_WORD); |
2c0262af FB |
6451 | } |
6452 | do_jcc: | |
6453 | next_eip = s->pc - s->cs_base; | |
14ce26e7 | 6454 | tval += next_eip; |
2c0262af | 6455 | if (s->dflag == 0) |
14ce26e7 FB |
6456 | tval &= 0xffff; |
6457 | gen_jcc(s, b, tval, next_eip); | |
2c0262af FB |
6458 | break; |
6459 | ||
6460 | case 0x190 ... 0x19f: /* setcc Gv */ | |
0af10c86 | 6461 | modrm = cpu_ldub_code(env, s->pc++); |
cc8b6f5b | 6462 | gen_setcc1(s, b, cpu_T[0]); |
0af10c86 | 6463 | gen_ldst_modrm(env, s, modrm, OT_BYTE, OR_TMP0, 1); |
2c0262af FB |
6464 | break; |
6465 | case 0x140 ... 0x14f: /* cmov Gv, Ev */ | |
f32d3781 PB |
6466 | ot = dflag + OT_WORD; |
6467 | modrm = cpu_ldub_code(env, s->pc++); | |
6468 | reg = ((modrm >> 3) & 7) | rex_r; | |
6469 | gen_cmovcc1(env, s, ot, b, modrm, reg); | |
2c0262af | 6470 | break; |
3b46e624 | 6471 | |
2c0262af FB |
6472 | /************************/ |
6473 | /* flags */ | |
6474 | case 0x9c: /* pushf */ | |
872929aa | 6475 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); |
2c0262af FB |
6476 | if (s->vm86 && s->iopl != 3) { |
6477 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6478 | } else { | |
773cdfcc | 6479 | gen_update_cc_op(s); |
f0967a1a | 6480 | gen_helper_read_eflags(cpu_T[0], cpu_env); |
2c0262af FB |
6481 | gen_push_T0(s); |
6482 | } | |
6483 | break; | |
6484 | case 0x9d: /* popf */ | |
872929aa | 6485 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); |
2c0262af FB |
6486 | if (s->vm86 && s->iopl != 3) { |
6487 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6488 | } else { | |
6489 | gen_pop_T0(s); | |
6490 | if (s->cpl == 0) { | |
6491 | if (s->dflag) { | |
f0967a1a BS |
6492 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6493 | tcg_const_i32((TF_MASK | AC_MASK | | |
6494 | ID_MASK | NT_MASK | | |
6495 | IF_MASK | | |
6496 | IOPL_MASK))); | |
2c0262af | 6497 | } else { |
f0967a1a BS |
6498 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6499 | tcg_const_i32((TF_MASK | AC_MASK | | |
6500 | ID_MASK | NT_MASK | | |
6501 | IF_MASK | IOPL_MASK) | |
6502 | & 0xffff)); | |
2c0262af FB |
6503 | } |
6504 | } else { | |
4136f33c FB |
6505 | if (s->cpl <= s->iopl) { |
6506 | if (s->dflag) { | |
f0967a1a BS |
6507 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6508 | tcg_const_i32((TF_MASK | | |
6509 | AC_MASK | | |
6510 | ID_MASK | | |
6511 | NT_MASK | | |
6512 | IF_MASK))); | |
4136f33c | 6513 | } else { |
f0967a1a BS |
6514 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6515 | tcg_const_i32((TF_MASK | | |
6516 | AC_MASK | | |
6517 | ID_MASK | | |
6518 | NT_MASK | | |
6519 | IF_MASK) | |
6520 | & 0xffff)); | |
4136f33c | 6521 | } |
2c0262af | 6522 | } else { |
4136f33c | 6523 | if (s->dflag) { |
f0967a1a BS |
6524 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6525 | tcg_const_i32((TF_MASK | AC_MASK | | |
6526 | ID_MASK | NT_MASK))); | |
4136f33c | 6527 | } else { |
f0967a1a BS |
6528 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6529 | tcg_const_i32((TF_MASK | AC_MASK | | |
6530 | ID_MASK | NT_MASK) | |
6531 | & 0xffff)); | |
4136f33c | 6532 | } |
2c0262af FB |
6533 | } |
6534 | } | |
6535 | gen_pop_update(s); | |
3ca51d07 | 6536 | set_cc_op(s, CC_OP_EFLAGS); |
a9321a4d | 6537 | /* abort translation because TF/AC flag may change */ |
14ce26e7 | 6538 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6539 | gen_eob(s); |
6540 | } | |
6541 | break; | |
6542 | case 0x9e: /* sahf */ | |
12e26b75 | 6543 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6544 | goto illegal_op; |
57fec1fe | 6545 | gen_op_mov_TN_reg(OT_BYTE, 0, R_AH); |
d229edce | 6546 | gen_compute_eflags(s); |
bd7a7b33 FB |
6547 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); |
6548 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); | |
6549 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); | |
2c0262af FB |
6550 | break; |
6551 | case 0x9f: /* lahf */ | |
12e26b75 | 6552 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6553 | goto illegal_op; |
d229edce | 6554 | gen_compute_eflags(s); |
bd7a7b33 | 6555 | /* Note: gen_compute_eflags() only gives the condition codes */ |
d229edce | 6556 | tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02); |
57fec1fe | 6557 | gen_op_mov_reg_T0(OT_BYTE, R_AH); |
2c0262af FB |
6558 | break; |
6559 | case 0xf5: /* cmc */ | |
d229edce | 6560 | gen_compute_eflags(s); |
bd7a7b33 | 6561 | tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6562 | break; |
6563 | case 0xf8: /* clc */ | |
d229edce | 6564 | gen_compute_eflags(s); |
bd7a7b33 | 6565 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); |
2c0262af FB |
6566 | break; |
6567 | case 0xf9: /* stc */ | |
d229edce | 6568 | gen_compute_eflags(s); |
bd7a7b33 | 6569 | tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6570 | break; |
6571 | case 0xfc: /* cld */ | |
b6abf97d | 6572 | tcg_gen_movi_i32(cpu_tmp2_i32, 1); |
317ac620 | 6573 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6574 | break; |
6575 | case 0xfd: /* std */ | |
b6abf97d | 6576 | tcg_gen_movi_i32(cpu_tmp2_i32, -1); |
317ac620 | 6577 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6578 | break; |
6579 | ||
6580 | /************************/ | |
6581 | /* bit operations */ | |
6582 | case 0x1ba: /* bt/bts/btr/btc Gv, im */ | |
14ce26e7 | 6583 | ot = dflag + OT_WORD; |
0af10c86 | 6584 | modrm = cpu_ldub_code(env, s->pc++); |
33698e5f | 6585 | op = (modrm >> 3) & 7; |
2c0262af | 6586 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6587 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 6588 | if (mod != 3) { |
14ce26e7 | 6589 | s->rip_offset = 1; |
0af10c86 | 6590 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 6591 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6592 | } else { |
57fec1fe | 6593 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
6594 | } |
6595 | /* load shift */ | |
0af10c86 | 6596 | val = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
6597 | gen_op_movl_T1_im(val); |
6598 | if (op < 4) | |
6599 | goto illegal_op; | |
6600 | op -= 4; | |
f484d386 | 6601 | goto bt_op; |
2c0262af FB |
6602 | case 0x1a3: /* bt Gv, Ev */ |
6603 | op = 0; | |
6604 | goto do_btx; | |
6605 | case 0x1ab: /* bts */ | |
6606 | op = 1; | |
6607 | goto do_btx; | |
6608 | case 0x1b3: /* btr */ | |
6609 | op = 2; | |
6610 | goto do_btx; | |
6611 | case 0x1bb: /* btc */ | |
6612 | op = 3; | |
6613 | do_btx: | |
14ce26e7 | 6614 | ot = dflag + OT_WORD; |
0af10c86 | 6615 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 6616 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 6617 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6618 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 6619 | gen_op_mov_TN_reg(OT_LONG, 1, reg); |
2c0262af | 6620 | if (mod != 3) { |
0af10c86 | 6621 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 6622 | /* specific case: we need to add a displacement */ |
f484d386 FB |
6623 | gen_exts(ot, cpu_T[1]); |
6624 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); | |
6625 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); | |
6626 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe | 6627 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6628 | } else { |
57fec1fe | 6629 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 6630 | } |
f484d386 FB |
6631 | bt_op: |
6632 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); | |
6633 | switch(op) { | |
6634 | case 0: | |
6635 | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); | |
6636 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6637 | break; | |
6638 | case 1: | |
6639 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6640 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6641 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6642 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6643 | break; | |
6644 | case 2: | |
6645 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6646 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6647 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6648 | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); | |
6649 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6650 | break; | |
6651 | default: | |
6652 | case 3: | |
6653 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6654 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6655 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6656 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6657 | break; | |
6658 | } | |
3ca51d07 | 6659 | set_cc_op(s, CC_OP_SARB + ot); |
2c0262af FB |
6660 | if (op != 0) { |
6661 | if (mod != 3) | |
57fec1fe | 6662 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 6663 | else |
57fec1fe | 6664 | gen_op_mov_reg_T0(ot, rm); |
f484d386 FB |
6665 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
6666 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
2c0262af FB |
6667 | } |
6668 | break; | |
6669 | case 0x1bc: /* bsf */ | |
6670 | case 0x1bd: /* bsr */ | |
6191b059 FB |
6671 | { |
6672 | int label1; | |
1e4840bf FB |
6673 | TCGv t0; |
6674 | ||
6191b059 | 6675 | ot = dflag + OT_WORD; |
0af10c86 | 6676 | modrm = cpu_ldub_code(env, s->pc++); |
6191b059 | 6677 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 6678 | gen_ldst_modrm(env, s,modrm, ot, OR_TMP0, 0); |
6191b059 | 6679 | gen_extu(ot, cpu_T[0]); |
a7812ae4 | 6680 | t0 = tcg_temp_local_new(); |
1e4840bf | 6681 | tcg_gen_mov_tl(t0, cpu_T[0]); |
31501a71 AP |
6682 | if ((b & 1) && (prefixes & PREFIX_REPZ) && |
6683 | (s->cpuid_ext3_features & CPUID_EXT3_ABM)) { | |
6684 | switch(ot) { | |
6685 | case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0, | |
6686 | tcg_const_i32(16)); break; | |
6687 | case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0, | |
6688 | tcg_const_i32(32)); break; | |
6689 | case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0, | |
6690 | tcg_const_i32(64)); break; | |
6691 | } | |
6692 | gen_op_mov_reg_T0(ot, reg); | |
6191b059 | 6693 | } else { |
31501a71 AP |
6694 | label1 = gen_new_label(); |
6695 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6696 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1); | |
6697 | if (b & 1) { | |
6698 | gen_helper_bsr(cpu_T[0], t0); | |
6699 | } else { | |
6700 | gen_helper_bsf(cpu_T[0], t0); | |
6701 | } | |
6702 | gen_op_mov_reg_T0(ot, reg); | |
6703 | tcg_gen_movi_tl(cpu_cc_dst, 1); | |
6704 | gen_set_label(label1); | |
3ca51d07 | 6705 | set_cc_op(s, CC_OP_LOGICB + ot); |
6191b059 | 6706 | } |
1e4840bf | 6707 | tcg_temp_free(t0); |
6191b059 | 6708 | } |
2c0262af FB |
6709 | break; |
6710 | /************************/ | |
6711 | /* bcd */ | |
6712 | case 0x27: /* daa */ | |
14ce26e7 FB |
6713 | if (CODE64(s)) |
6714 | goto illegal_op; | |
773cdfcc | 6715 | gen_update_cc_op(s); |
7923057b | 6716 | gen_helper_daa(cpu_env); |
3ca51d07 | 6717 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6718 | break; |
6719 | case 0x2f: /* das */ | |
14ce26e7 FB |
6720 | if (CODE64(s)) |
6721 | goto illegal_op; | |
773cdfcc | 6722 | gen_update_cc_op(s); |
7923057b | 6723 | gen_helper_das(cpu_env); |
3ca51d07 | 6724 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6725 | break; |
6726 | case 0x37: /* aaa */ | |
14ce26e7 FB |
6727 | if (CODE64(s)) |
6728 | goto illegal_op; | |
773cdfcc | 6729 | gen_update_cc_op(s); |
7923057b | 6730 | gen_helper_aaa(cpu_env); |
3ca51d07 | 6731 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6732 | break; |
6733 | case 0x3f: /* aas */ | |
14ce26e7 FB |
6734 | if (CODE64(s)) |
6735 | goto illegal_op; | |
773cdfcc | 6736 | gen_update_cc_op(s); |
7923057b | 6737 | gen_helper_aas(cpu_env); |
3ca51d07 | 6738 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6739 | break; |
6740 | case 0xd4: /* aam */ | |
14ce26e7 FB |
6741 | if (CODE64(s)) |
6742 | goto illegal_op; | |
0af10c86 | 6743 | val = cpu_ldub_code(env, s->pc++); |
b6d7c3db TS |
6744 | if (val == 0) { |
6745 | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); | |
6746 | } else { | |
7923057b | 6747 | gen_helper_aam(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 6748 | set_cc_op(s, CC_OP_LOGICB); |
b6d7c3db | 6749 | } |
2c0262af FB |
6750 | break; |
6751 | case 0xd5: /* aad */ | |
14ce26e7 FB |
6752 | if (CODE64(s)) |
6753 | goto illegal_op; | |
0af10c86 | 6754 | val = cpu_ldub_code(env, s->pc++); |
7923057b | 6755 | gen_helper_aad(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 6756 | set_cc_op(s, CC_OP_LOGICB); |
2c0262af FB |
6757 | break; |
6758 | /************************/ | |
6759 | /* misc */ | |
6760 | case 0x90: /* nop */ | |
ab1f142b | 6761 | /* XXX: correct lock test for all insn */ |
7418027e | 6762 | if (prefixes & PREFIX_LOCK) { |
ab1f142b | 6763 | goto illegal_op; |
7418027e RH |
6764 | } |
6765 | /* If REX_B is set, then this is xchg eax, r8d, not a nop. */ | |
6766 | if (REX_B(s)) { | |
6767 | goto do_xchg_reg_eax; | |
6768 | } | |
0573fbfc TS |
6769 | if (prefixes & PREFIX_REPZ) { |
6770 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE); | |
6771 | } | |
2c0262af FB |
6772 | break; |
6773 | case 0x9b: /* fwait */ | |
5fafdf24 | 6774 | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == |
7eee2a50 FB |
6775 | (HF_MP_MASK | HF_TS_MASK)) { |
6776 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
2ee73ac3 | 6777 | } else { |
773cdfcc | 6778 | gen_update_cc_op(s); |
14ce26e7 | 6779 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6780 | gen_helper_fwait(cpu_env); |
7eee2a50 | 6781 | } |
2c0262af FB |
6782 | break; |
6783 | case 0xcc: /* int3 */ | |
6784 | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); | |
6785 | break; | |
6786 | case 0xcd: /* int N */ | |
0af10c86 | 6787 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6788 | if (s->vm86 && s->iopl != 3) { |
5fafdf24 | 6789 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
f115e911 FB |
6790 | } else { |
6791 | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); | |
6792 | } | |
2c0262af FB |
6793 | break; |
6794 | case 0xce: /* into */ | |
14ce26e7 FB |
6795 | if (CODE64(s)) |
6796 | goto illegal_op; | |
773cdfcc | 6797 | gen_update_cc_op(s); |
a8ede8ba | 6798 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6799 | gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start)); |
2c0262af | 6800 | break; |
0b97134b | 6801 | #ifdef WANT_ICEBP |
2c0262af | 6802 | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
872929aa | 6803 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); |
aba9d61e | 6804 | #if 1 |
2c0262af | 6805 | gen_debug(s, pc_start - s->cs_base); |
aba9d61e FB |
6806 | #else |
6807 | /* start debug */ | |
0af10c86 | 6808 | tb_flush(env); |
24537a01 | 6809 | qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); |
aba9d61e | 6810 | #endif |
2c0262af | 6811 | break; |
0b97134b | 6812 | #endif |
2c0262af FB |
6813 | case 0xfa: /* cli */ |
6814 | if (!s->vm86) { | |
6815 | if (s->cpl <= s->iopl) { | |
f0967a1a | 6816 | gen_helper_cli(cpu_env); |
2c0262af FB |
6817 | } else { |
6818 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6819 | } | |
6820 | } else { | |
6821 | if (s->iopl == 3) { | |
f0967a1a | 6822 | gen_helper_cli(cpu_env); |
2c0262af FB |
6823 | } else { |
6824 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6825 | } | |
6826 | } | |
6827 | break; | |
6828 | case 0xfb: /* sti */ | |
6829 | if (!s->vm86) { | |
6830 | if (s->cpl <= s->iopl) { | |
6831 | gen_sti: | |
f0967a1a | 6832 | gen_helper_sti(cpu_env); |
2c0262af | 6833 | /* interruptions are enabled only the first insn after sti */ |
a2cc3b24 FB |
6834 | /* If several instructions disable interrupts, only the |
6835 | _first_ does it */ | |
6836 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 6837 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af | 6838 | /* give a chance to handle pending irqs */ |
14ce26e7 | 6839 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6840 | gen_eob(s); |
6841 | } else { | |
6842 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6843 | } | |
6844 | } else { | |
6845 | if (s->iopl == 3) { | |
6846 | goto gen_sti; | |
6847 | } else { | |
6848 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6849 | } | |
6850 | } | |
6851 | break; | |
6852 | case 0x62: /* bound */ | |
14ce26e7 FB |
6853 | if (CODE64(s)) |
6854 | goto illegal_op; | |
2c0262af | 6855 | ot = dflag ? OT_LONG : OT_WORD; |
0af10c86 | 6856 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
6857 | reg = (modrm >> 3) & 7; |
6858 | mod = (modrm >> 6) & 3; | |
6859 | if (mod == 3) | |
6860 | goto illegal_op; | |
57fec1fe | 6861 | gen_op_mov_TN_reg(ot, 0, reg); |
0af10c86 | 6862 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 6863 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6864 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
92fc4b58 BS |
6865 | if (ot == OT_WORD) { |
6866 | gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32); | |
6867 | } else { | |
6868 | gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32); | |
6869 | } | |
2c0262af FB |
6870 | break; |
6871 | case 0x1c8 ... 0x1cf: /* bswap reg */ | |
14ce26e7 FB |
6872 | reg = (b & 7) | REX_B(s); |
6873 | #ifdef TARGET_X86_64 | |
6874 | if (dflag == 2) { | |
57fec1fe | 6875 | gen_op_mov_TN_reg(OT_QUAD, 0, reg); |
66896cb8 | 6876 | tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); |
57fec1fe | 6877 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 6878 | } else |
8777643e | 6879 | #endif |
57fec1fe FB |
6880 | { |
6881 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
8777643e AJ |
6882 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
6883 | tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); | |
57fec1fe | 6884 | gen_op_mov_reg_T0(OT_LONG, reg); |
14ce26e7 | 6885 | } |
2c0262af FB |
6886 | break; |
6887 | case 0xd6: /* salc */ | |
14ce26e7 FB |
6888 | if (CODE64(s)) |
6889 | goto illegal_op; | |
cc8b6f5b | 6890 | gen_compute_eflags_c(s, cpu_T[0]); |
bd7a7b33 FB |
6891 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
6892 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
6893 | break; |
6894 | case 0xe0: /* loopnz */ | |
6895 | case 0xe1: /* loopz */ | |
2c0262af FB |
6896 | case 0xe2: /* loop */ |
6897 | case 0xe3: /* jecxz */ | |
14ce26e7 | 6898 | { |
6e0d8677 | 6899 | int l1, l2, l3; |
14ce26e7 | 6900 | |
0af10c86 | 6901 | tval = (int8_t)insn_get(env, s, OT_BYTE); |
14ce26e7 FB |
6902 | next_eip = s->pc - s->cs_base; |
6903 | tval += next_eip; | |
6904 | if (s->dflag == 0) | |
6905 | tval &= 0xffff; | |
3b46e624 | 6906 | |
14ce26e7 FB |
6907 | l1 = gen_new_label(); |
6908 | l2 = gen_new_label(); | |
6e0d8677 | 6909 | l3 = gen_new_label(); |
14ce26e7 | 6910 | b &= 3; |
6e0d8677 FB |
6911 | switch(b) { |
6912 | case 0: /* loopnz */ | |
6913 | case 1: /* loopz */ | |
6e0d8677 FB |
6914 | gen_op_add_reg_im(s->aflag, R_ECX, -1); |
6915 | gen_op_jz_ecx(s->aflag, l3); | |
5bdb91b0 | 6916 | gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1); |
6e0d8677 FB |
6917 | break; |
6918 | case 2: /* loop */ | |
6919 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
6920 | gen_op_jnz_ecx(s->aflag, l1); | |
6921 | break; | |
6922 | default: | |
6923 | case 3: /* jcxz */ | |
6924 | gen_op_jz_ecx(s->aflag, l1); | |
6925 | break; | |
14ce26e7 FB |
6926 | } |
6927 | ||
6e0d8677 | 6928 | gen_set_label(l3); |
14ce26e7 | 6929 | gen_jmp_im(next_eip); |
8e1c85e3 | 6930 | tcg_gen_br(l2); |
6e0d8677 | 6931 | |
14ce26e7 FB |
6932 | gen_set_label(l1); |
6933 | gen_jmp_im(tval); | |
6934 | gen_set_label(l2); | |
6935 | gen_eob(s); | |
6936 | } | |
2c0262af FB |
6937 | break; |
6938 | case 0x130: /* wrmsr */ | |
6939 | case 0x132: /* rdmsr */ | |
6940 | if (s->cpl != 0) { | |
6941 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6942 | } else { | |
773cdfcc | 6943 | gen_update_cc_op(s); |
872929aa | 6944 | gen_jmp_im(pc_start - s->cs_base); |
0573fbfc | 6945 | if (b & 2) { |
4a7443be | 6946 | gen_helper_rdmsr(cpu_env); |
0573fbfc | 6947 | } else { |
4a7443be | 6948 | gen_helper_wrmsr(cpu_env); |
0573fbfc | 6949 | } |
2c0262af FB |
6950 | } |
6951 | break; | |
6952 | case 0x131: /* rdtsc */ | |
773cdfcc | 6953 | gen_update_cc_op(s); |
ecada8a2 | 6954 | gen_jmp_im(pc_start - s->cs_base); |
efade670 PB |
6955 | if (use_icount) |
6956 | gen_io_start(); | |
4a7443be | 6957 | gen_helper_rdtsc(cpu_env); |
efade670 PB |
6958 | if (use_icount) { |
6959 | gen_io_end(); | |
6960 | gen_jmp(s, s->pc - s->cs_base); | |
6961 | } | |
2c0262af | 6962 | break; |
df01e0fc | 6963 | case 0x133: /* rdpmc */ |
773cdfcc | 6964 | gen_update_cc_op(s); |
df01e0fc | 6965 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6966 | gen_helper_rdpmc(cpu_env); |
df01e0fc | 6967 | break; |
023fe10d | 6968 | case 0x134: /* sysenter */ |
2436b61a | 6969 | /* For Intel SYSENTER is valid on 64-bit */ |
0af10c86 | 6970 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 6971 | goto illegal_op; |
023fe10d FB |
6972 | if (!s->pe) { |
6973 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6974 | } else { | |
728d803b | 6975 | gen_update_cc_op(s); |
14ce26e7 | 6976 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6977 | gen_helper_sysenter(cpu_env); |
023fe10d FB |
6978 | gen_eob(s); |
6979 | } | |
6980 | break; | |
6981 | case 0x135: /* sysexit */ | |
2436b61a | 6982 | /* For Intel SYSEXIT is valid on 64-bit */ |
0af10c86 | 6983 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 6984 | goto illegal_op; |
023fe10d FB |
6985 | if (!s->pe) { |
6986 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6987 | } else { | |
728d803b | 6988 | gen_update_cc_op(s); |
14ce26e7 | 6989 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6990 | gen_helper_sysexit(cpu_env, tcg_const_i32(dflag)); |
023fe10d FB |
6991 | gen_eob(s); |
6992 | } | |
6993 | break; | |
14ce26e7 FB |
6994 | #ifdef TARGET_X86_64 |
6995 | case 0x105: /* syscall */ | |
6996 | /* XXX: is it usable in real mode ? */ | |
728d803b | 6997 | gen_update_cc_op(s); |
14ce26e7 | 6998 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6999 | gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start)); |
14ce26e7 FB |
7000 | gen_eob(s); |
7001 | break; | |
7002 | case 0x107: /* sysret */ | |
7003 | if (!s->pe) { | |
7004 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7005 | } else { | |
728d803b | 7006 | gen_update_cc_op(s); |
14ce26e7 | 7007 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7008 | gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag)); |
aba9d61e | 7009 | /* condition codes are modified only in long mode */ |
3ca51d07 RH |
7010 | if (s->lma) { |
7011 | set_cc_op(s, CC_OP_EFLAGS); | |
7012 | } | |
14ce26e7 FB |
7013 | gen_eob(s); |
7014 | } | |
7015 | break; | |
7016 | #endif | |
2c0262af | 7017 | case 0x1a2: /* cpuid */ |
773cdfcc | 7018 | gen_update_cc_op(s); |
9575cb94 | 7019 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7020 | gen_helper_cpuid(cpu_env); |
2c0262af FB |
7021 | break; |
7022 | case 0xf4: /* hlt */ | |
7023 | if (s->cpl != 0) { | |
7024 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7025 | } else { | |
773cdfcc | 7026 | gen_update_cc_op(s); |
94451178 | 7027 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7028 | gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); |
5779406a | 7029 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
7030 | } |
7031 | break; | |
7032 | case 0x100: | |
0af10c86 | 7033 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7034 | mod = (modrm >> 6) & 3; |
7035 | op = (modrm >> 3) & 7; | |
7036 | switch(op) { | |
7037 | case 0: /* sldt */ | |
f115e911 FB |
7038 | if (!s->pe || s->vm86) |
7039 | goto illegal_op; | |
872929aa | 7040 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); |
651ba608 | 7041 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); |
2c0262af FB |
7042 | ot = OT_WORD; |
7043 | if (mod == 3) | |
7044 | ot += s->dflag; | |
0af10c86 | 7045 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
7046 | break; |
7047 | case 2: /* lldt */ | |
f115e911 FB |
7048 | if (!s->pe || s->vm86) |
7049 | goto illegal_op; | |
2c0262af FB |
7050 | if (s->cpl != 0) { |
7051 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7052 | } else { | |
872929aa | 7053 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); |
0af10c86 | 7054 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 7055 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7056 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7057 | gen_helper_lldt(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7058 | } |
7059 | break; | |
7060 | case 1: /* str */ | |
f115e911 FB |
7061 | if (!s->pe || s->vm86) |
7062 | goto illegal_op; | |
872929aa | 7063 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); |
651ba608 | 7064 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); |
2c0262af FB |
7065 | ot = OT_WORD; |
7066 | if (mod == 3) | |
7067 | ot += s->dflag; | |
0af10c86 | 7068 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
7069 | break; |
7070 | case 3: /* ltr */ | |
f115e911 FB |
7071 | if (!s->pe || s->vm86) |
7072 | goto illegal_op; | |
2c0262af FB |
7073 | if (s->cpl != 0) { |
7074 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7075 | } else { | |
872929aa | 7076 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); |
0af10c86 | 7077 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 7078 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7079 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7080 | gen_helper_ltr(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7081 | } |
7082 | break; | |
7083 | case 4: /* verr */ | |
7084 | case 5: /* verw */ | |
f115e911 FB |
7085 | if (!s->pe || s->vm86) |
7086 | goto illegal_op; | |
0af10c86 | 7087 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
773cdfcc | 7088 | gen_update_cc_op(s); |
2999a0b2 BS |
7089 | if (op == 4) { |
7090 | gen_helper_verr(cpu_env, cpu_T[0]); | |
7091 | } else { | |
7092 | gen_helper_verw(cpu_env, cpu_T[0]); | |
7093 | } | |
3ca51d07 | 7094 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 7095 | break; |
2c0262af FB |
7096 | default: |
7097 | goto illegal_op; | |
7098 | } | |
7099 | break; | |
7100 | case 0x101: | |
0af10c86 | 7101 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7102 | mod = (modrm >> 6) & 3; |
7103 | op = (modrm >> 3) & 7; | |
3d7374c5 | 7104 | rm = modrm & 7; |
2c0262af FB |
7105 | switch(op) { |
7106 | case 0: /* sgdt */ | |
2c0262af FB |
7107 | if (mod == 3) |
7108 | goto illegal_op; | |
872929aa | 7109 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); |
0af10c86 | 7110 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
651ba608 | 7111 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); |
57fec1fe | 7112 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
aba9d61e | 7113 | gen_add_A0_im(s, 2); |
651ba608 | 7114 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); |
2c0262af FB |
7115 | if (!s->dflag) |
7116 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7117 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af | 7118 | break; |
3d7374c5 FB |
7119 | case 1: |
7120 | if (mod == 3) { | |
7121 | switch (rm) { | |
7122 | case 0: /* monitor */ | |
7123 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7124 | s->cpl != 0) | |
7125 | goto illegal_op; | |
773cdfcc | 7126 | gen_update_cc_op(s); |
3d7374c5 FB |
7127 | gen_jmp_im(pc_start - s->cs_base); |
7128 | #ifdef TARGET_X86_64 | |
7129 | if (s->aflag == 2) { | |
bbf662ee | 7130 | gen_op_movq_A0_reg(R_EAX); |
5fafdf24 | 7131 | } else |
3d7374c5 FB |
7132 | #endif |
7133 | { | |
bbf662ee | 7134 | gen_op_movl_A0_reg(R_EAX); |
3d7374c5 FB |
7135 | if (s->aflag == 0) |
7136 | gen_op_andl_A0_ffff(); | |
7137 | } | |
7138 | gen_add_A0_ds_seg(s); | |
4a7443be | 7139 | gen_helper_monitor(cpu_env, cpu_A0); |
3d7374c5 FB |
7140 | break; |
7141 | case 1: /* mwait */ | |
7142 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7143 | s->cpl != 0) | |
7144 | goto illegal_op; | |
728d803b | 7145 | gen_update_cc_op(s); |
94451178 | 7146 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7147 | gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); |
3d7374c5 FB |
7148 | gen_eob(s); |
7149 | break; | |
a9321a4d PA |
7150 | case 2: /* clac */ |
7151 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7152 | s->cpl != 0) { | |
7153 | goto illegal_op; | |
7154 | } | |
7155 | gen_helper_clac(cpu_env); | |
7156 | gen_jmp_im(s->pc - s->cs_base); | |
7157 | gen_eob(s); | |
7158 | break; | |
7159 | case 3: /* stac */ | |
7160 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7161 | s->cpl != 0) { | |
7162 | goto illegal_op; | |
7163 | } | |
7164 | gen_helper_stac(cpu_env); | |
7165 | gen_jmp_im(s->pc - s->cs_base); | |
7166 | gen_eob(s); | |
7167 | break; | |
3d7374c5 FB |
7168 | default: |
7169 | goto illegal_op; | |
7170 | } | |
7171 | } else { /* sidt */ | |
872929aa | 7172 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); |
0af10c86 | 7173 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
651ba608 | 7174 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); |
57fec1fe | 7175 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
3d7374c5 | 7176 | gen_add_A0_im(s, 2); |
651ba608 | 7177 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); |
3d7374c5 FB |
7178 | if (!s->dflag) |
7179 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7180 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
3d7374c5 FB |
7181 | } |
7182 | break; | |
2c0262af FB |
7183 | case 2: /* lgdt */ |
7184 | case 3: /* lidt */ | |
0573fbfc | 7185 | if (mod == 3) { |
773cdfcc | 7186 | gen_update_cc_op(s); |
872929aa | 7187 | gen_jmp_im(pc_start - s->cs_base); |
0573fbfc TS |
7188 | switch(rm) { |
7189 | case 0: /* VMRUN */ | |
872929aa FB |
7190 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7191 | goto illegal_op; | |
7192 | if (s->cpl != 0) { | |
7193 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
0573fbfc | 7194 | break; |
872929aa | 7195 | } else { |
052e80d5 | 7196 | gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag), |
a7812ae4 | 7197 | tcg_const_i32(s->pc - pc_start)); |
db620f46 | 7198 | tcg_gen_exit_tb(0); |
5779406a | 7199 | s->is_jmp = DISAS_TB_JUMP; |
872929aa | 7200 | } |
0573fbfc TS |
7201 | break; |
7202 | case 1: /* VMMCALL */ | |
872929aa FB |
7203 | if (!(s->flags & HF_SVME_MASK)) |
7204 | goto illegal_op; | |
052e80d5 | 7205 | gen_helper_vmmcall(cpu_env); |
0573fbfc TS |
7206 | break; |
7207 | case 2: /* VMLOAD */ | |
872929aa FB |
7208 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7209 | goto illegal_op; | |
7210 | if (s->cpl != 0) { | |
7211 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7212 | break; | |
7213 | } else { | |
052e80d5 | 7214 | gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7215 | } |
0573fbfc TS |
7216 | break; |
7217 | case 3: /* VMSAVE */ | |
872929aa FB |
7218 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7219 | goto illegal_op; | |
7220 | if (s->cpl != 0) { | |
7221 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7222 | break; | |
7223 | } else { | |
052e80d5 | 7224 | gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7225 | } |
0573fbfc TS |
7226 | break; |
7227 | case 4: /* STGI */ | |
872929aa FB |
7228 | if ((!(s->flags & HF_SVME_MASK) && |
7229 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7230 | !s->pe) | |
7231 | goto illegal_op; | |
7232 | if (s->cpl != 0) { | |
7233 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7234 | break; | |
7235 | } else { | |
052e80d5 | 7236 | gen_helper_stgi(cpu_env); |
872929aa | 7237 | } |
0573fbfc TS |
7238 | break; |
7239 | case 5: /* CLGI */ | |
872929aa FB |
7240 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7241 | goto illegal_op; | |
7242 | if (s->cpl != 0) { | |
7243 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7244 | break; | |
7245 | } else { | |
052e80d5 | 7246 | gen_helper_clgi(cpu_env); |
872929aa | 7247 | } |
0573fbfc TS |
7248 | break; |
7249 | case 6: /* SKINIT */ | |
872929aa FB |
7250 | if ((!(s->flags & HF_SVME_MASK) && |
7251 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7252 | !s->pe) | |
7253 | goto illegal_op; | |
052e80d5 | 7254 | gen_helper_skinit(cpu_env); |
0573fbfc TS |
7255 | break; |
7256 | case 7: /* INVLPGA */ | |
872929aa FB |
7257 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7258 | goto illegal_op; | |
7259 | if (s->cpl != 0) { | |
7260 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7261 | break; | |
7262 | } else { | |
052e80d5 | 7263 | gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7264 | } |
0573fbfc TS |
7265 | break; |
7266 | default: | |
7267 | goto illegal_op; | |
7268 | } | |
7269 | } else if (s->cpl != 0) { | |
2c0262af FB |
7270 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7271 | } else { | |
872929aa FB |
7272 | gen_svm_check_intercept(s, pc_start, |
7273 | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); | |
0af10c86 | 7274 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 7275 | gen_op_ld_T1_A0(OT_WORD + s->mem_index); |
aba9d61e | 7276 | gen_add_A0_im(s, 2); |
57fec1fe | 7277 | gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af FB |
7278 | if (!s->dflag) |
7279 | gen_op_andl_T0_im(0xffffff); | |
7280 | if (op == 2) { | |
651ba608 FB |
7281 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); |
7282 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); | |
2c0262af | 7283 | } else { |
651ba608 FB |
7284 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); |
7285 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); | |
2c0262af FB |
7286 | } |
7287 | } | |
7288 | break; | |
7289 | case 4: /* smsw */ | |
872929aa | 7290 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); |
e2542fe2 | 7291 | #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN |
f60d2728 | 7292 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); |
7293 | #else | |
651ba608 | 7294 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); |
f60d2728 | 7295 | #endif |
0af10c86 | 7296 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 1); |
2c0262af FB |
7297 | break; |
7298 | case 6: /* lmsw */ | |
7299 | if (s->cpl != 0) { | |
7300 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7301 | } else { | |
872929aa | 7302 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
0af10c86 | 7303 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
4a7443be | 7304 | gen_helper_lmsw(cpu_env, cpu_T[0]); |
14ce26e7 | 7305 | gen_jmp_im(s->pc - s->cs_base); |
d71b9a8b | 7306 | gen_eob(s); |
2c0262af FB |
7307 | } |
7308 | break; | |
1b050077 AP |
7309 | case 7: |
7310 | if (mod != 3) { /* invlpg */ | |
7311 | if (s->cpl != 0) { | |
7312 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7313 | } else { | |
773cdfcc | 7314 | gen_update_cc_op(s); |
1b050077 | 7315 | gen_jmp_im(pc_start - s->cs_base); |
0af10c86 | 7316 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4a7443be | 7317 | gen_helper_invlpg(cpu_env, cpu_A0); |
1b050077 AP |
7318 | gen_jmp_im(s->pc - s->cs_base); |
7319 | gen_eob(s); | |
7320 | } | |
2c0262af | 7321 | } else { |
1b050077 AP |
7322 | switch (rm) { |
7323 | case 0: /* swapgs */ | |
14ce26e7 | 7324 | #ifdef TARGET_X86_64 |
1b050077 AP |
7325 | if (CODE64(s)) { |
7326 | if (s->cpl != 0) { | |
7327 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7328 | } else { | |
7329 | tcg_gen_ld_tl(cpu_T[0], cpu_env, | |
7330 | offsetof(CPUX86State,segs[R_GS].base)); | |
7331 | tcg_gen_ld_tl(cpu_T[1], cpu_env, | |
7332 | offsetof(CPUX86State,kernelgsbase)); | |
7333 | tcg_gen_st_tl(cpu_T[1], cpu_env, | |
7334 | offsetof(CPUX86State,segs[R_GS].base)); | |
7335 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
7336 | offsetof(CPUX86State,kernelgsbase)); | |
7337 | } | |
5fafdf24 | 7338 | } else |
14ce26e7 FB |
7339 | #endif |
7340 | { | |
7341 | goto illegal_op; | |
7342 | } | |
1b050077 AP |
7343 | break; |
7344 | case 1: /* rdtscp */ | |
7345 | if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) | |
7346 | goto illegal_op; | |
773cdfcc | 7347 | gen_update_cc_op(s); |
9575cb94 | 7348 | gen_jmp_im(pc_start - s->cs_base); |
1b050077 AP |
7349 | if (use_icount) |
7350 | gen_io_start(); | |
4a7443be | 7351 | gen_helper_rdtscp(cpu_env); |
1b050077 AP |
7352 | if (use_icount) { |
7353 | gen_io_end(); | |
7354 | gen_jmp(s, s->pc - s->cs_base); | |
7355 | } | |
7356 | break; | |
7357 | default: | |
7358 | goto illegal_op; | |
14ce26e7 | 7359 | } |
2c0262af FB |
7360 | } |
7361 | break; | |
7362 | default: | |
7363 | goto illegal_op; | |
7364 | } | |
7365 | break; | |
3415a4dd FB |
7366 | case 0x108: /* invd */ |
7367 | case 0x109: /* wbinvd */ | |
7368 | if (s->cpl != 0) { | |
7369 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7370 | } else { | |
872929aa | 7371 | gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); |
3415a4dd FB |
7372 | /* nothing to do */ |
7373 | } | |
7374 | break; | |
14ce26e7 FB |
7375 | case 0x63: /* arpl or movslS (x86_64) */ |
7376 | #ifdef TARGET_X86_64 | |
7377 | if (CODE64(s)) { | |
7378 | int d_ot; | |
7379 | /* d_ot is the size of destination */ | |
7380 | d_ot = dflag + OT_WORD; | |
7381 | ||
0af10c86 | 7382 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7383 | reg = ((modrm >> 3) & 7) | rex_r; |
7384 | mod = (modrm >> 6) & 3; | |
7385 | rm = (modrm & 7) | REX_B(s); | |
3b46e624 | 7386 | |
14ce26e7 | 7387 | if (mod == 3) { |
57fec1fe | 7388 | gen_op_mov_TN_reg(OT_LONG, 0, rm); |
14ce26e7 FB |
7389 | /* sign extend */ |
7390 | if (d_ot == OT_QUAD) | |
e108dd01 | 7391 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
57fec1fe | 7392 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7393 | } else { |
0af10c86 | 7394 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 7395 | if (d_ot == OT_QUAD) { |
57fec1fe | 7396 | gen_op_lds_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7397 | } else { |
57fec1fe | 7398 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7399 | } |
57fec1fe | 7400 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7401 | } |
5fafdf24 | 7402 | } else |
14ce26e7 FB |
7403 | #endif |
7404 | { | |
3bd7da9e | 7405 | int label1; |
49d9fdcc | 7406 | TCGv t0, t1, t2, a0; |
1e4840bf | 7407 | |
14ce26e7 FB |
7408 | if (!s->pe || s->vm86) |
7409 | goto illegal_op; | |
a7812ae4 PB |
7410 | t0 = tcg_temp_local_new(); |
7411 | t1 = tcg_temp_local_new(); | |
7412 | t2 = tcg_temp_local_new(); | |
3bd7da9e | 7413 | ot = OT_WORD; |
0af10c86 | 7414 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7415 | reg = (modrm >> 3) & 7; |
7416 | mod = (modrm >> 6) & 3; | |
7417 | rm = modrm & 7; | |
7418 | if (mod != 3) { | |
0af10c86 | 7419 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
1e4840bf | 7420 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
49d9fdcc LD |
7421 | a0 = tcg_temp_local_new(); |
7422 | tcg_gen_mov_tl(a0, cpu_A0); | |
14ce26e7 | 7423 | } else { |
1e4840bf | 7424 | gen_op_mov_v_reg(ot, t0, rm); |
49d9fdcc | 7425 | TCGV_UNUSED(a0); |
14ce26e7 | 7426 | } |
1e4840bf FB |
7427 | gen_op_mov_v_reg(ot, t1, reg); |
7428 | tcg_gen_andi_tl(cpu_tmp0, t0, 3); | |
7429 | tcg_gen_andi_tl(t1, t1, 3); | |
7430 | tcg_gen_movi_tl(t2, 0); | |
3bd7da9e | 7431 | label1 = gen_new_label(); |
1e4840bf FB |
7432 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); |
7433 | tcg_gen_andi_tl(t0, t0, ~3); | |
7434 | tcg_gen_or_tl(t0, t0, t1); | |
7435 | tcg_gen_movi_tl(t2, CC_Z); | |
3bd7da9e | 7436 | gen_set_label(label1); |
14ce26e7 | 7437 | if (mod != 3) { |
49d9fdcc LD |
7438 | gen_op_st_v(ot + s->mem_index, t0, a0); |
7439 | tcg_temp_free(a0); | |
7440 | } else { | |
1e4840bf | 7441 | gen_op_mov_reg_v(ot, rm, t0); |
14ce26e7 | 7442 | } |
d229edce | 7443 | gen_compute_eflags(s); |
3bd7da9e | 7444 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); |
1e4840bf | 7445 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); |
1e4840bf FB |
7446 | tcg_temp_free(t0); |
7447 | tcg_temp_free(t1); | |
7448 | tcg_temp_free(t2); | |
f115e911 | 7449 | } |
f115e911 | 7450 | break; |
2c0262af FB |
7451 | case 0x102: /* lar */ |
7452 | case 0x103: /* lsl */ | |
cec6843e FB |
7453 | { |
7454 | int label1; | |
1e4840bf | 7455 | TCGv t0; |
cec6843e FB |
7456 | if (!s->pe || s->vm86) |
7457 | goto illegal_op; | |
7458 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 7459 | modrm = cpu_ldub_code(env, s->pc++); |
cec6843e | 7460 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 7461 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
a7812ae4 | 7462 | t0 = tcg_temp_local_new(); |
773cdfcc | 7463 | gen_update_cc_op(s); |
2999a0b2 BS |
7464 | if (b == 0x102) { |
7465 | gen_helper_lar(t0, cpu_env, cpu_T[0]); | |
7466 | } else { | |
7467 | gen_helper_lsl(t0, cpu_env, cpu_T[0]); | |
7468 | } | |
cec6843e FB |
7469 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); |
7470 | label1 = gen_new_label(); | |
cb63669a | 7471 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
1e4840bf | 7472 | gen_op_mov_reg_v(ot, reg, t0); |
cec6843e | 7473 | gen_set_label(label1); |
3ca51d07 | 7474 | set_cc_op(s, CC_OP_EFLAGS); |
1e4840bf | 7475 | tcg_temp_free(t0); |
cec6843e | 7476 | } |
2c0262af FB |
7477 | break; |
7478 | case 0x118: | |
0af10c86 | 7479 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7480 | mod = (modrm >> 6) & 3; |
7481 | op = (modrm >> 3) & 7; | |
7482 | switch(op) { | |
7483 | case 0: /* prefetchnta */ | |
7484 | case 1: /* prefetchnt0 */ | |
7485 | case 2: /* prefetchnt0 */ | |
7486 | case 3: /* prefetchnt0 */ | |
7487 | if (mod == 3) | |
7488 | goto illegal_op; | |
0af10c86 | 7489 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
7490 | /* nothing more to do */ |
7491 | break; | |
e17a36ce | 7492 | default: /* nop (multi byte) */ |
0af10c86 | 7493 | gen_nop_modrm(env, s, modrm); |
e17a36ce | 7494 | break; |
2c0262af FB |
7495 | } |
7496 | break; | |
e17a36ce | 7497 | case 0x119 ... 0x11f: /* nop (multi byte) */ |
0af10c86 BS |
7498 | modrm = cpu_ldub_code(env, s->pc++); |
7499 | gen_nop_modrm(env, s, modrm); | |
e17a36ce | 7500 | break; |
2c0262af FB |
7501 | case 0x120: /* mov reg, crN */ |
7502 | case 0x122: /* mov crN, reg */ | |
7503 | if (s->cpl != 0) { | |
7504 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7505 | } else { | |
0af10c86 | 7506 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7507 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7508 | * AMD documentation (24594.pdf) and testing of | |
7509 | * intel 386 and 486 processors all show that the mod bits | |
7510 | * are assumed to be 1's, regardless of actual values. | |
7511 | */ | |
14ce26e7 FB |
7512 | rm = (modrm & 7) | REX_B(s); |
7513 | reg = ((modrm >> 3) & 7) | rex_r; | |
7514 | if (CODE64(s)) | |
7515 | ot = OT_QUAD; | |
7516 | else | |
7517 | ot = OT_LONG; | |
ccd59d09 AP |
7518 | if ((prefixes & PREFIX_LOCK) && (reg == 0) && |
7519 | (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { | |
7520 | reg = 8; | |
7521 | } | |
2c0262af FB |
7522 | switch(reg) { |
7523 | case 0: | |
7524 | case 2: | |
7525 | case 3: | |
7526 | case 4: | |
9230e66e | 7527 | case 8: |
773cdfcc | 7528 | gen_update_cc_op(s); |
872929aa | 7529 | gen_jmp_im(pc_start - s->cs_base); |
2c0262af | 7530 | if (b & 2) { |
57fec1fe | 7531 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be BS |
7532 | gen_helper_write_crN(cpu_env, tcg_const_i32(reg), |
7533 | cpu_T[0]); | |
14ce26e7 | 7534 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7535 | gen_eob(s); |
7536 | } else { | |
4a7443be | 7537 | gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg)); |
57fec1fe | 7538 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7539 | } |
7540 | break; | |
7541 | default: | |
7542 | goto illegal_op; | |
7543 | } | |
7544 | } | |
7545 | break; | |
7546 | case 0x121: /* mov reg, drN */ | |
7547 | case 0x123: /* mov drN, reg */ | |
7548 | if (s->cpl != 0) { | |
7549 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7550 | } else { | |
0af10c86 | 7551 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7552 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7553 | * AMD documentation (24594.pdf) and testing of | |
7554 | * intel 386 and 486 processors all show that the mod bits | |
7555 | * are assumed to be 1's, regardless of actual values. | |
7556 | */ | |
14ce26e7 FB |
7557 | rm = (modrm & 7) | REX_B(s); |
7558 | reg = ((modrm >> 3) & 7) | rex_r; | |
7559 | if (CODE64(s)) | |
7560 | ot = OT_QUAD; | |
7561 | else | |
7562 | ot = OT_LONG; | |
2c0262af | 7563 | /* XXX: do it dynamically with CR4.DE bit */ |
14ce26e7 | 7564 | if (reg == 4 || reg == 5 || reg >= 8) |
2c0262af FB |
7565 | goto illegal_op; |
7566 | if (b & 2) { | |
0573fbfc | 7567 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
57fec1fe | 7568 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be | 7569 | gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7570 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7571 | gen_eob(s); |
7572 | } else { | |
0573fbfc | 7573 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
651ba608 | 7574 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); |
57fec1fe | 7575 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7576 | } |
7577 | } | |
7578 | break; | |
7579 | case 0x106: /* clts */ | |
7580 | if (s->cpl != 0) { | |
7581 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7582 | } else { | |
0573fbfc | 7583 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
f0967a1a | 7584 | gen_helper_clts(cpu_env); |
7eee2a50 | 7585 | /* abort block because static cpu state changed */ |
14ce26e7 | 7586 | gen_jmp_im(s->pc - s->cs_base); |
7eee2a50 | 7587 | gen_eob(s); |
2c0262af FB |
7588 | } |
7589 | break; | |
222a3336 | 7590 | /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ |
664e0f19 FB |
7591 | case 0x1c3: /* MOVNTI reg, mem */ |
7592 | if (!(s->cpuid_features & CPUID_SSE2)) | |
14ce26e7 | 7593 | goto illegal_op; |
664e0f19 | 7594 | ot = s->dflag == 2 ? OT_QUAD : OT_LONG; |
0af10c86 | 7595 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7596 | mod = (modrm >> 6) & 3; |
7597 | if (mod == 3) | |
7598 | goto illegal_op; | |
7599 | reg = ((modrm >> 3) & 7) | rex_r; | |
7600 | /* generate a generic store */ | |
0af10c86 | 7601 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
14ce26e7 | 7602 | break; |
664e0f19 | 7603 | case 0x1ae: |
0af10c86 | 7604 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7605 | mod = (modrm >> 6) & 3; |
7606 | op = (modrm >> 3) & 7; | |
7607 | switch(op) { | |
7608 | case 0: /* fxsave */ | |
5fafdf24 | 7609 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7610 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7611 | goto illegal_op; |
09d85fb8 | 7612 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7613 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7614 | break; | |
7615 | } | |
0af10c86 | 7616 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
773cdfcc | 7617 | gen_update_cc_op(s); |
19e6c4b8 | 7618 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 7619 | gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2))); |
664e0f19 FB |
7620 | break; |
7621 | case 1: /* fxrstor */ | |
5fafdf24 | 7622 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7623 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7624 | goto illegal_op; |
09d85fb8 | 7625 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7626 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7627 | break; | |
7628 | } | |
0af10c86 | 7629 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
773cdfcc | 7630 | gen_update_cc_op(s); |
19e6c4b8 | 7631 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae BS |
7632 | gen_helper_fxrstor(cpu_env, cpu_A0, |
7633 | tcg_const_i32((s->dflag == 2))); | |
664e0f19 FB |
7634 | break; |
7635 | case 2: /* ldmxcsr */ | |
7636 | case 3: /* stmxcsr */ | |
7637 | if (s->flags & HF_TS_MASK) { | |
7638 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7639 | break; | |
14ce26e7 | 7640 | } |
664e0f19 FB |
7641 | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) || |
7642 | mod == 3) | |
14ce26e7 | 7643 | goto illegal_op; |
0af10c86 | 7644 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 7645 | if (op == 2) { |
57fec1fe | 7646 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
20f8bd48 | 7647 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 7648 | gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); |
14ce26e7 | 7649 | } else { |
651ba608 | 7650 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
57fec1fe | 7651 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7652 | } |
664e0f19 FB |
7653 | break; |
7654 | case 5: /* lfence */ | |
7655 | case 6: /* mfence */ | |
8001c294 | 7656 | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) |
664e0f19 FB |
7657 | goto illegal_op; |
7658 | break; | |
8f091a59 FB |
7659 | case 7: /* sfence / clflush */ |
7660 | if ((modrm & 0xc7) == 0xc0) { | |
7661 | /* sfence */ | |
a35f3ec7 | 7662 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */ |
8f091a59 FB |
7663 | if (!(s->cpuid_features & CPUID_SSE)) |
7664 | goto illegal_op; | |
7665 | } else { | |
7666 | /* clflush */ | |
7667 | if (!(s->cpuid_features & CPUID_CLFLUSH)) | |
7668 | goto illegal_op; | |
0af10c86 | 7669 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8f091a59 FB |
7670 | } |
7671 | break; | |
664e0f19 | 7672 | default: |
14ce26e7 FB |
7673 | goto illegal_op; |
7674 | } | |
7675 | break; | |
a35f3ec7 | 7676 | case 0x10d: /* 3DNow! prefetch(w) */ |
0af10c86 | 7677 | modrm = cpu_ldub_code(env, s->pc++); |
a35f3ec7 AJ |
7678 | mod = (modrm >> 6) & 3; |
7679 | if (mod == 3) | |
7680 | goto illegal_op; | |
0af10c86 | 7681 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8f091a59 FB |
7682 | /* ignore for now */ |
7683 | break; | |
3b21e03e | 7684 | case 0x1aa: /* rsm */ |
872929aa | 7685 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); |
3b21e03e FB |
7686 | if (!(s->flags & HF_SMM_MASK)) |
7687 | goto illegal_op; | |
728d803b | 7688 | gen_update_cc_op(s); |
3b21e03e | 7689 | gen_jmp_im(s->pc - s->cs_base); |
608badfc | 7690 | gen_helper_rsm(cpu_env); |
3b21e03e FB |
7691 | gen_eob(s); |
7692 | break; | |
222a3336 AZ |
7693 | case 0x1b8: /* SSE4.2 popcnt */ |
7694 | if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != | |
7695 | PREFIX_REPZ) | |
7696 | goto illegal_op; | |
7697 | if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) | |
7698 | goto illegal_op; | |
7699 | ||
0af10c86 | 7700 | modrm = cpu_ldub_code(env, s->pc++); |
8b4a3df8 | 7701 | reg = ((modrm >> 3) & 7) | rex_r; |
222a3336 AZ |
7702 | |
7703 | if (s->prefix & PREFIX_DATA) | |
7704 | ot = OT_WORD; | |
7705 | else if (s->dflag != 2) | |
7706 | ot = OT_LONG; | |
7707 | else | |
7708 | ot = OT_QUAD; | |
7709 | ||
0af10c86 | 7710 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
d3eb5eae | 7711 | gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot)); |
222a3336 | 7712 | gen_op_mov_reg_T0(ot, reg); |
fdb0d09d | 7713 | |
3ca51d07 | 7714 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 | 7715 | break; |
a35f3ec7 AJ |
7716 | case 0x10e ... 0x10f: |
7717 | /* 3DNow! instructions, ignore prefixes */ | |
7718 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); | |
664e0f19 FB |
7719 | case 0x110 ... 0x117: |
7720 | case 0x128 ... 0x12f: | |
4242b1bd | 7721 | case 0x138 ... 0x13a: |
d9f4bb27 | 7722 | case 0x150 ... 0x179: |
664e0f19 FB |
7723 | case 0x17c ... 0x17f: |
7724 | case 0x1c2: | |
7725 | case 0x1c4 ... 0x1c6: | |
7726 | case 0x1d0 ... 0x1fe: | |
0af10c86 | 7727 | gen_sse(env, s, b, pc_start, rex_r); |
664e0f19 | 7728 | break; |
2c0262af FB |
7729 | default: |
7730 | goto illegal_op; | |
7731 | } | |
7732 | /* lock generation */ | |
7733 | if (s->prefix & PREFIX_LOCK) | |
a7812ae4 | 7734 | gen_helper_unlock(); |
2c0262af FB |
7735 | return s->pc; |
7736 | illegal_op: | |
ab1f142b | 7737 | if (s->prefix & PREFIX_LOCK) |
a7812ae4 | 7738 | gen_helper_unlock(); |
2c0262af FB |
7739 | /* XXX: ensure that no lock was generated */ |
7740 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
7741 | return s->pc; | |
7742 | } | |
7743 | ||
2c0262af FB |
7744 | void optimize_flags_init(void) |
7745 | { | |
a7812ae4 PB |
7746 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7747 | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 AF |
7748 | offsetof(CPUX86State, cc_op), "cc_op"); |
7749 | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src), | |
a7812ae4 | 7750 | "cc_src"); |
317ac620 | 7751 | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst), |
a7812ae4 | 7752 | "cc_dst"); |
437a88a5 | 7753 | |
cc739bb0 LD |
7754 | #ifdef TARGET_X86_64 |
7755 | cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0, | |
317ac620 | 7756 | offsetof(CPUX86State, regs[R_EAX]), "rax"); |
cc739bb0 | 7757 | cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7758 | offsetof(CPUX86State, regs[R_ECX]), "rcx"); |
cc739bb0 | 7759 | cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7760 | offsetof(CPUX86State, regs[R_EDX]), "rdx"); |
cc739bb0 | 7761 | cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7762 | offsetof(CPUX86State, regs[R_EBX]), "rbx"); |
cc739bb0 | 7763 | cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7764 | offsetof(CPUX86State, regs[R_ESP]), "rsp"); |
cc739bb0 | 7765 | cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7766 | offsetof(CPUX86State, regs[R_EBP]), "rbp"); |
cc739bb0 | 7767 | cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7768 | offsetof(CPUX86State, regs[R_ESI]), "rsi"); |
cc739bb0 | 7769 | cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7770 | offsetof(CPUX86State, regs[R_EDI]), "rdi"); |
cc739bb0 | 7771 | cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7772 | offsetof(CPUX86State, regs[8]), "r8"); |
cc739bb0 | 7773 | cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7774 | offsetof(CPUX86State, regs[9]), "r9"); |
cc739bb0 | 7775 | cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7776 | offsetof(CPUX86State, regs[10]), "r10"); |
cc739bb0 | 7777 | cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7778 | offsetof(CPUX86State, regs[11]), "r11"); |
cc739bb0 | 7779 | cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7780 | offsetof(CPUX86State, regs[12]), "r12"); |
cc739bb0 | 7781 | cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7782 | offsetof(CPUX86State, regs[13]), "r13"); |
cc739bb0 | 7783 | cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7784 | offsetof(CPUX86State, regs[14]), "r14"); |
cc739bb0 | 7785 | cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7786 | offsetof(CPUX86State, regs[15]), "r15"); |
cc739bb0 LD |
7787 | #else |
7788 | cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 | 7789 | offsetof(CPUX86State, regs[R_EAX]), "eax"); |
cc739bb0 | 7790 | cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7791 | offsetof(CPUX86State, regs[R_ECX]), "ecx"); |
cc739bb0 | 7792 | cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7793 | offsetof(CPUX86State, regs[R_EDX]), "edx"); |
cc739bb0 | 7794 | cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7795 | offsetof(CPUX86State, regs[R_EBX]), "ebx"); |
cc739bb0 | 7796 | cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7797 | offsetof(CPUX86State, regs[R_ESP]), "esp"); |
cc739bb0 | 7798 | cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7799 | offsetof(CPUX86State, regs[R_EBP]), "ebp"); |
cc739bb0 | 7800 | cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7801 | offsetof(CPUX86State, regs[R_ESI]), "esi"); |
cc739bb0 | 7802 | cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7803 | offsetof(CPUX86State, regs[R_EDI]), "edi"); |
cc739bb0 LD |
7804 | #endif |
7805 | ||
437a88a5 | 7806 | /* register helpers */ |
a7812ae4 | 7807 | #define GEN_HELPER 2 |
437a88a5 | 7808 | #include "helper.h" |
2c0262af FB |
7809 | } |
7810 | ||
7811 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for | |
7812 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
7813 | information for each intermediate instruction. */ | |
317ac620 | 7814 | static inline void gen_intermediate_code_internal(CPUX86State *env, |
2cfc5f17 TS |
7815 | TranslationBlock *tb, |
7816 | int search_pc) | |
2c0262af FB |
7817 | { |
7818 | DisasContext dc1, *dc = &dc1; | |
14ce26e7 | 7819 | target_ulong pc_ptr; |
2c0262af | 7820 | uint16_t *gen_opc_end; |
a1d1bb31 | 7821 | CPUBreakpoint *bp; |
7f5b7d3e | 7822 | int j, lj; |
c068688b | 7823 | uint64_t flags; |
14ce26e7 FB |
7824 | target_ulong pc_start; |
7825 | target_ulong cs_base; | |
2e70f6ef PB |
7826 | int num_insns; |
7827 | int max_insns; | |
3b46e624 | 7828 | |
2c0262af | 7829 | /* generate intermediate code */ |
14ce26e7 FB |
7830 | pc_start = tb->pc; |
7831 | cs_base = tb->cs_base; | |
2c0262af | 7832 | flags = tb->flags; |
3a1d9b8b | 7833 | |
4f31916f | 7834 | dc->pe = (flags >> HF_PE_SHIFT) & 1; |
2c0262af FB |
7835 | dc->code32 = (flags >> HF_CS32_SHIFT) & 1; |
7836 | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; | |
7837 | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; | |
7838 | dc->f_st = 0; | |
7839 | dc->vm86 = (flags >> VM_SHIFT) & 1; | |
7840 | dc->cpl = (flags >> HF_CPL_SHIFT) & 3; | |
7841 | dc->iopl = (flags >> IOPL_SHIFT) & 3; | |
7842 | dc->tf = (flags >> TF_SHIFT) & 1; | |
34865134 | 7843 | dc->singlestep_enabled = env->singlestep_enabled; |
2c0262af | 7844 | dc->cc_op = CC_OP_DYNAMIC; |
e207582f | 7845 | dc->cc_op_dirty = false; |
2c0262af FB |
7846 | dc->cs_base = cs_base; |
7847 | dc->tb = tb; | |
7848 | dc->popl_esp_hack = 0; | |
7849 | /* select memory access functions */ | |
7850 | dc->mem_index = 0; | |
7851 | if (flags & HF_SOFTMMU_MASK) { | |
a9321a4d | 7852 | dc->mem_index = (cpu_mmu_index(env) + 1) << 2; |
2c0262af | 7853 | } |
14ce26e7 | 7854 | dc->cpuid_features = env->cpuid_features; |
3d7374c5 | 7855 | dc->cpuid_ext_features = env->cpuid_ext_features; |
e771edab | 7856 | dc->cpuid_ext2_features = env->cpuid_ext2_features; |
12e26b75 | 7857 | dc->cpuid_ext3_features = env->cpuid_ext3_features; |
a9321a4d | 7858 | dc->cpuid_7_0_ebx_features = env->cpuid_7_0_ebx_features; |
14ce26e7 FB |
7859 | #ifdef TARGET_X86_64 |
7860 | dc->lma = (flags >> HF_LMA_SHIFT) & 1; | |
7861 | dc->code64 = (flags >> HF_CS64_SHIFT) & 1; | |
7862 | #endif | |
7eee2a50 | 7863 | dc->flags = flags; |
a2cc3b24 FB |
7864 | dc->jmp_opt = !(dc->tf || env->singlestep_enabled || |
7865 | (flags & HF_INHIBIT_IRQ_MASK) | |
415fa2ea | 7866 | #ifndef CONFIG_SOFTMMU |
2c0262af FB |
7867 | || (flags & HF_SOFTMMU_MASK) |
7868 | #endif | |
7869 | ); | |
4f31916f FB |
7870 | #if 0 |
7871 | /* check addseg logic */ | |
dc196a57 | 7872 | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) |
4f31916f FB |
7873 | printf("ERROR addseg\n"); |
7874 | #endif | |
7875 | ||
a7812ae4 PB |
7876 | cpu_T[0] = tcg_temp_new(); |
7877 | cpu_T[1] = tcg_temp_new(); | |
7878 | cpu_A0 = tcg_temp_new(); | |
a7812ae4 PB |
7879 | |
7880 | cpu_tmp0 = tcg_temp_new(); | |
7881 | cpu_tmp1_i64 = tcg_temp_new_i64(); | |
7882 | cpu_tmp2_i32 = tcg_temp_new_i32(); | |
7883 | cpu_tmp3_i32 = tcg_temp_new_i32(); | |
7884 | cpu_tmp4 = tcg_temp_new(); | |
7885 | cpu_tmp5 = tcg_temp_new(); | |
a7812ae4 PB |
7886 | cpu_ptr0 = tcg_temp_new_ptr(); |
7887 | cpu_ptr1 = tcg_temp_new_ptr(); | |
57fec1fe | 7888 | |
92414b31 | 7889 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
7890 | |
7891 | dc->is_jmp = DISAS_NEXT; | |
7892 | pc_ptr = pc_start; | |
7893 | lj = -1; | |
2e70f6ef PB |
7894 | num_insns = 0; |
7895 | max_insns = tb->cflags & CF_COUNT_MASK; | |
7896 | if (max_insns == 0) | |
7897 | max_insns = CF_COUNT_MASK; | |
2c0262af | 7898 | |
2e70f6ef | 7899 | gen_icount_start(); |
2c0262af | 7900 | for(;;) { |
72cf2d4f BS |
7901 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
7902 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a2397807 JK |
7903 | if (bp->pc == pc_ptr && |
7904 | !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { | |
2c0262af FB |
7905 | gen_debug(dc, pc_ptr - dc->cs_base); |
7906 | break; | |
7907 | } | |
7908 | } | |
7909 | } | |
7910 | if (search_pc) { | |
92414b31 | 7911 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
7912 | if (lj < j) { |
7913 | lj++; | |
7914 | while (lj < j) | |
ab1103de | 7915 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 7916 | } |
25983cad | 7917 | tcg_ctx.gen_opc_pc[lj] = pc_ptr; |
2c0262af | 7918 | gen_opc_cc_op[lj] = dc->cc_op; |
ab1103de | 7919 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 7920 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
2c0262af | 7921 | } |
2e70f6ef PB |
7922 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
7923 | gen_io_start(); | |
7924 | ||
0af10c86 | 7925 | pc_ptr = disas_insn(env, dc, pc_ptr); |
2e70f6ef | 7926 | num_insns++; |
2c0262af FB |
7927 | /* stop translation if indicated */ |
7928 | if (dc->is_jmp) | |
7929 | break; | |
7930 | /* if single step mode, we generate only one instruction and | |
7931 | generate an exception */ | |
a2cc3b24 FB |
7932 | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear |
7933 | the flag and abort the translation to give the irqs a | |
7934 | change to be happen */ | |
5fafdf24 | 7935 | if (dc->tf || dc->singlestep_enabled || |
2e70f6ef | 7936 | (flags & HF_INHIBIT_IRQ_MASK)) { |
14ce26e7 | 7937 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7938 | gen_eob(dc); |
7939 | break; | |
7940 | } | |
7941 | /* if too long translation, stop generation too */ | |
efd7f486 | 7942 | if (tcg_ctx.gen_opc_ptr >= gen_opc_end || |
2e70f6ef PB |
7943 | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || |
7944 | num_insns >= max_insns) { | |
14ce26e7 | 7945 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7946 | gen_eob(dc); |
7947 | break; | |
7948 | } | |
1b530a6d AJ |
7949 | if (singlestep) { |
7950 | gen_jmp_im(pc_ptr - dc->cs_base); | |
7951 | gen_eob(dc); | |
7952 | break; | |
7953 | } | |
2c0262af | 7954 | } |
2e70f6ef PB |
7955 | if (tb->cflags & CF_LAST_IO) |
7956 | gen_io_end(); | |
7957 | gen_icount_end(tb, num_insns); | |
efd7f486 | 7958 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
2c0262af FB |
7959 | /* we don't forget to fill the last values */ |
7960 | if (search_pc) { | |
92414b31 | 7961 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
7962 | lj++; |
7963 | while (lj <= j) | |
ab1103de | 7964 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 7965 | } |
3b46e624 | 7966 | |
2c0262af | 7967 | #ifdef DEBUG_DISAS |
8fec2b8c | 7968 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
14ce26e7 | 7969 | int disas_flags; |
93fcfe39 AL |
7970 | qemu_log("----------------\n"); |
7971 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
14ce26e7 FB |
7972 | #ifdef TARGET_X86_64 |
7973 | if (dc->code64) | |
7974 | disas_flags = 2; | |
7975 | else | |
7976 | #endif | |
7977 | disas_flags = !dc->code32; | |
f4359b9f | 7978 | log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags); |
93fcfe39 | 7979 | qemu_log("\n"); |
2c0262af FB |
7980 | } |
7981 | #endif | |
7982 | ||
2e70f6ef | 7983 | if (!search_pc) { |
2c0262af | 7984 | tb->size = pc_ptr - pc_start; |
2e70f6ef PB |
7985 | tb->icount = num_insns; |
7986 | } | |
2c0262af FB |
7987 | } |
7988 | ||
317ac620 | 7989 | void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 7990 | { |
2cfc5f17 | 7991 | gen_intermediate_code_internal(env, tb, 0); |
2c0262af FB |
7992 | } |
7993 | ||
317ac620 | 7994 | void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 7995 | { |
2cfc5f17 | 7996 | gen_intermediate_code_internal(env, tb, 1); |
2c0262af FB |
7997 | } |
7998 | ||
317ac620 | 7999 | void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos) |
d2856f1a AJ |
8000 | { |
8001 | int cc_op; | |
8002 | #ifdef DEBUG_DISAS | |
8fec2b8c | 8003 | if (qemu_loglevel_mask(CPU_LOG_TB_OP)) { |
d2856f1a | 8004 | int i; |
93fcfe39 | 8005 | qemu_log("RESTORE:\n"); |
d2856f1a | 8006 | for(i = 0;i <= pc_pos; i++) { |
ab1103de | 8007 | if (tcg_ctx.gen_opc_instr_start[i]) { |
25983cad EV |
8008 | qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, |
8009 | tcg_ctx.gen_opc_pc[i]); | |
d2856f1a AJ |
8010 | } |
8011 | } | |
e87b7cb0 | 8012 | qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
25983cad | 8013 | pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base, |
d2856f1a AJ |
8014 | (uint32_t)tb->cs_base); |
8015 | } | |
8016 | #endif | |
25983cad | 8017 | env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base; |
d2856f1a AJ |
8018 | cc_op = gen_opc_cc_op[pc_pos]; |
8019 | if (cc_op != CC_OP_DYNAMIC) | |
8020 | env->cc_op = cc_op; | |
8021 | } |