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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 translation | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
2c0262af FB |
25 | |
26 | #include "cpu.h" | |
27 | #include "exec-all.h" | |
28 | #include "disas.h" | |
57fec1fe | 29 | #include "tcg-op.h" |
2c0262af | 30 | |
a7812ae4 PB |
31 | #include "helper.h" |
32 | #define GEN_HELPER 1 | |
33 | #include "helper.h" | |
34 | ||
2c0262af FB |
35 | #define PREFIX_REPZ 0x01 |
36 | #define PREFIX_REPNZ 0x02 | |
37 | #define PREFIX_LOCK 0x04 | |
38 | #define PREFIX_DATA 0x08 | |
39 | #define PREFIX_ADR 0x10 | |
40 | ||
14ce26e7 FB |
41 | #ifdef TARGET_X86_64 |
42 | #define X86_64_ONLY(x) x | |
001faf32 | 43 | #define X86_64_DEF(...) __VA_ARGS__ |
14ce26e7 FB |
44 | #define CODE64(s) ((s)->code64) |
45 | #define REX_X(s) ((s)->rex_x) | |
46 | #define REX_B(s) ((s)->rex_b) | |
47 | /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */ | |
48 | #if 1 | |
49 | #define BUGGY_64(x) NULL | |
50 | #endif | |
51 | #else | |
52 | #define X86_64_ONLY(x) NULL | |
001faf32 | 53 | #define X86_64_DEF(...) |
14ce26e7 FB |
54 | #define CODE64(s) 0 |
55 | #define REX_X(s) 0 | |
56 | #define REX_B(s) 0 | |
57 | #endif | |
58 | ||
57fec1fe FB |
59 | //#define MACRO_TEST 1 |
60 | ||
57fec1fe | 61 | /* global register indexes */ |
a7812ae4 PB |
62 | static TCGv_ptr cpu_env; |
63 | static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp; | |
64 | static TCGv_i32 cpu_cc_op; | |
cc739bb0 | 65 | static TCGv cpu_regs[CPU_NB_REGS]; |
1e4840bf FB |
66 | /* local temps */ |
67 | static TCGv cpu_T[2], cpu_T3; | |
57fec1fe | 68 | /* local register indexes (only used inside old micro ops) */ |
a7812ae4 PB |
69 | static TCGv cpu_tmp0, cpu_tmp4; |
70 | static TCGv_ptr cpu_ptr0, cpu_ptr1; | |
71 | static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; | |
72 | static TCGv_i64 cpu_tmp1_i64; | |
bedda79c | 73 | static TCGv cpu_tmp5; |
57fec1fe | 74 | |
2e70f6ef PB |
75 | #include "gen-icount.h" |
76 | ||
57fec1fe FB |
77 | #ifdef TARGET_X86_64 |
78 | static int x86_64_hregs; | |
ae063a68 FB |
79 | #endif |
80 | ||
2c0262af FB |
81 | typedef struct DisasContext { |
82 | /* current insn context */ | |
83 | int override; /* -1 if no override */ | |
84 | int prefix; | |
85 | int aflag, dflag; | |
14ce26e7 | 86 | target_ulong pc; /* pc = eip + cs_base */ |
2c0262af FB |
87 | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
88 | static state change (stop translation) */ | |
89 | /* current block context */ | |
14ce26e7 | 90 | target_ulong cs_base; /* base of CS segment */ |
2c0262af FB |
91 | int pe; /* protected mode */ |
92 | int code32; /* 32 bit code segment */ | |
14ce26e7 FB |
93 | #ifdef TARGET_X86_64 |
94 | int lma; /* long mode active */ | |
95 | int code64; /* 64 bit code segment */ | |
96 | int rex_x, rex_b; | |
97 | #endif | |
2c0262af FB |
98 | int ss32; /* 32 bit stack segment */ |
99 | int cc_op; /* current CC operation */ | |
100 | int addseg; /* non zero if either DS/ES/SS have a non zero base */ | |
101 | int f_st; /* currently unused */ | |
102 | int vm86; /* vm86 mode */ | |
103 | int cpl; | |
104 | int iopl; | |
105 | int tf; /* TF cpu flag */ | |
34865134 | 106 | int singlestep_enabled; /* "hardware" single step enabled */ |
2c0262af FB |
107 | int jmp_opt; /* use direct block chaining for direct jumps */ |
108 | int mem_index; /* select memory access functions */ | |
c068688b | 109 | uint64_t flags; /* all execution flags */ |
2c0262af FB |
110 | struct TranslationBlock *tb; |
111 | int popl_esp_hack; /* for correct popl with esp base handling */ | |
14ce26e7 FB |
112 | int rip_offset; /* only used in x86_64, but left for simplicity */ |
113 | int cpuid_features; | |
3d7374c5 | 114 | int cpuid_ext_features; |
e771edab | 115 | int cpuid_ext2_features; |
12e26b75 | 116 | int cpuid_ext3_features; |
2c0262af FB |
117 | } DisasContext; |
118 | ||
119 | static void gen_eob(DisasContext *s); | |
14ce26e7 FB |
120 | static void gen_jmp(DisasContext *s, target_ulong eip); |
121 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); | |
2c0262af FB |
122 | |
123 | /* i386 arith/logic operations */ | |
124 | enum { | |
5fafdf24 TS |
125 | OP_ADDL, |
126 | OP_ORL, | |
127 | OP_ADCL, | |
2c0262af | 128 | OP_SBBL, |
5fafdf24 TS |
129 | OP_ANDL, |
130 | OP_SUBL, | |
131 | OP_XORL, | |
2c0262af FB |
132 | OP_CMPL, |
133 | }; | |
134 | ||
135 | /* i386 shift ops */ | |
136 | enum { | |
5fafdf24 TS |
137 | OP_ROL, |
138 | OP_ROR, | |
139 | OP_RCL, | |
140 | OP_RCR, | |
141 | OP_SHL, | |
142 | OP_SHR, | |
2c0262af FB |
143 | OP_SHL1, /* undocumented */ |
144 | OP_SAR = 7, | |
145 | }; | |
146 | ||
8e1c85e3 FB |
147 | enum { |
148 | JCC_O, | |
149 | JCC_B, | |
150 | JCC_Z, | |
151 | JCC_BE, | |
152 | JCC_S, | |
153 | JCC_P, | |
154 | JCC_L, | |
155 | JCC_LE, | |
156 | }; | |
157 | ||
2c0262af FB |
158 | /* operand size */ |
159 | enum { | |
160 | OT_BYTE = 0, | |
161 | OT_WORD, | |
5fafdf24 | 162 | OT_LONG, |
2c0262af FB |
163 | OT_QUAD, |
164 | }; | |
165 | ||
166 | enum { | |
167 | /* I386 int registers */ | |
168 | OR_EAX, /* MUST be even numbered */ | |
169 | OR_ECX, | |
170 | OR_EDX, | |
171 | OR_EBX, | |
172 | OR_ESP, | |
173 | OR_EBP, | |
174 | OR_ESI, | |
175 | OR_EDI, | |
14ce26e7 FB |
176 | |
177 | OR_TMP0 = 16, /* temporary operand register */ | |
2c0262af FB |
178 | OR_TMP1, |
179 | OR_A0, /* temporary register used when doing address evaluation */ | |
2c0262af FB |
180 | }; |
181 | ||
57fec1fe FB |
182 | static inline void gen_op_movl_T0_0(void) |
183 | { | |
184 | tcg_gen_movi_tl(cpu_T[0], 0); | |
185 | } | |
186 | ||
187 | static inline void gen_op_movl_T0_im(int32_t val) | |
188 | { | |
189 | tcg_gen_movi_tl(cpu_T[0], val); | |
190 | } | |
191 | ||
192 | static inline void gen_op_movl_T0_imu(uint32_t val) | |
193 | { | |
194 | tcg_gen_movi_tl(cpu_T[0], val); | |
195 | } | |
196 | ||
197 | static inline void gen_op_movl_T1_im(int32_t val) | |
198 | { | |
199 | tcg_gen_movi_tl(cpu_T[1], val); | |
200 | } | |
201 | ||
202 | static inline void gen_op_movl_T1_imu(uint32_t val) | |
203 | { | |
204 | tcg_gen_movi_tl(cpu_T[1], val); | |
205 | } | |
206 | ||
207 | static inline void gen_op_movl_A0_im(uint32_t val) | |
208 | { | |
209 | tcg_gen_movi_tl(cpu_A0, val); | |
210 | } | |
211 | ||
212 | #ifdef TARGET_X86_64 | |
213 | static inline void gen_op_movq_A0_im(int64_t val) | |
214 | { | |
215 | tcg_gen_movi_tl(cpu_A0, val); | |
216 | } | |
217 | #endif | |
218 | ||
219 | static inline void gen_movtl_T0_im(target_ulong val) | |
220 | { | |
221 | tcg_gen_movi_tl(cpu_T[0], val); | |
222 | } | |
223 | ||
224 | static inline void gen_movtl_T1_im(target_ulong val) | |
225 | { | |
226 | tcg_gen_movi_tl(cpu_T[1], val); | |
227 | } | |
228 | ||
229 | static inline void gen_op_andl_T0_ffff(void) | |
230 | { | |
231 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
232 | } | |
233 | ||
234 | static inline void gen_op_andl_T0_im(uint32_t val) | |
235 | { | |
236 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); | |
237 | } | |
238 | ||
239 | static inline void gen_op_movl_T0_T1(void) | |
240 | { | |
241 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); | |
242 | } | |
243 | ||
244 | static inline void gen_op_andl_A0_ffff(void) | |
245 | { | |
246 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff); | |
247 | } | |
248 | ||
14ce26e7 FB |
249 | #ifdef TARGET_X86_64 |
250 | ||
251 | #define NB_OP_SIZES 4 | |
252 | ||
14ce26e7 FB |
253 | #else /* !TARGET_X86_64 */ |
254 | ||
255 | #define NB_OP_SIZES 3 | |
256 | ||
14ce26e7 FB |
257 | #endif /* !TARGET_X86_64 */ |
258 | ||
e2542fe2 | 259 | #if defined(HOST_WORDS_BIGENDIAN) |
57fec1fe FB |
260 | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
261 | #define REG_H_OFFSET (sizeof(target_ulong) - 2) | |
262 | #define REG_W_OFFSET (sizeof(target_ulong) - 2) | |
263 | #define REG_L_OFFSET (sizeof(target_ulong) - 4) | |
264 | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) | |
14ce26e7 | 265 | #else |
57fec1fe FB |
266 | #define REG_B_OFFSET 0 |
267 | #define REG_H_OFFSET 1 | |
268 | #define REG_W_OFFSET 0 | |
269 | #define REG_L_OFFSET 0 | |
270 | #define REG_LH_OFFSET 4 | |
14ce26e7 | 271 | #endif |
57fec1fe | 272 | |
1e4840bf | 273 | static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) |
57fec1fe | 274 | { |
cc739bb0 LD |
275 | TCGv tmp; |
276 | ||
57fec1fe FB |
277 | switch(ot) { |
278 | case OT_BYTE: | |
cc739bb0 LD |
279 | tmp = tcg_temp_new(); |
280 | tcg_gen_ext8u_tl(tmp, t0); | |
57fec1fe | 281 | if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { |
cc739bb0 LD |
282 | tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xff); |
283 | tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp); | |
57fec1fe | 284 | } else { |
cc739bb0 LD |
285 | tcg_gen_shli_tl(tmp, tmp, 8); |
286 | tcg_gen_andi_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], ~0xff00); | |
287 | tcg_gen_or_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], tmp); | |
57fec1fe | 288 | } |
cc739bb0 | 289 | tcg_temp_free(tmp); |
57fec1fe FB |
290 | break; |
291 | case OT_WORD: | |
cc739bb0 LD |
292 | tmp = tcg_temp_new(); |
293 | tcg_gen_ext16u_tl(tmp, t0); | |
294 | tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff); | |
295 | tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp); | |
296 | tcg_temp_free(tmp); | |
57fec1fe | 297 | break; |
cc739bb0 | 298 | default: /* XXX this shouldn't be reached; abort? */ |
57fec1fe | 299 | case OT_LONG: |
cc739bb0 LD |
300 | /* For x86_64, this sets the higher half of register to zero. |
301 | For i386, this is equivalent to a mov. */ | |
302 | tcg_gen_ext32u_tl(cpu_regs[reg], t0); | |
57fec1fe | 303 | break; |
cc739bb0 | 304 | #ifdef TARGET_X86_64 |
57fec1fe | 305 | case OT_QUAD: |
cc739bb0 | 306 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
57fec1fe | 307 | break; |
14ce26e7 | 308 | #endif |
57fec1fe FB |
309 | } |
310 | } | |
2c0262af | 311 | |
57fec1fe FB |
312 | static inline void gen_op_mov_reg_T0(int ot, int reg) |
313 | { | |
1e4840bf | 314 | gen_op_mov_reg_v(ot, reg, cpu_T[0]); |
57fec1fe FB |
315 | } |
316 | ||
317 | static inline void gen_op_mov_reg_T1(int ot, int reg) | |
318 | { | |
1e4840bf | 319 | gen_op_mov_reg_v(ot, reg, cpu_T[1]); |
57fec1fe FB |
320 | } |
321 | ||
322 | static inline void gen_op_mov_reg_A0(int size, int reg) | |
323 | { | |
cc739bb0 LD |
324 | TCGv tmp; |
325 | ||
57fec1fe FB |
326 | switch(size) { |
327 | case 0: | |
cc739bb0 LD |
328 | tmp = tcg_temp_new(); |
329 | tcg_gen_ext16u_tl(tmp, cpu_A0); | |
330 | tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff); | |
331 | tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp); | |
332 | tcg_temp_free(tmp); | |
57fec1fe | 333 | break; |
cc739bb0 | 334 | default: /* XXX this shouldn't be reached; abort? */ |
57fec1fe | 335 | case 1: |
cc739bb0 LD |
336 | /* For x86_64, this sets the higher half of register to zero. |
337 | For i386, this is equivalent to a mov. */ | |
338 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0); | |
57fec1fe | 339 | break; |
cc739bb0 | 340 | #ifdef TARGET_X86_64 |
57fec1fe | 341 | case 2: |
cc739bb0 | 342 | tcg_gen_mov_tl(cpu_regs[reg], cpu_A0); |
57fec1fe | 343 | break; |
14ce26e7 | 344 | #endif |
57fec1fe FB |
345 | } |
346 | } | |
347 | ||
1e4840bf | 348 | static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) |
57fec1fe FB |
349 | { |
350 | switch(ot) { | |
351 | case OT_BYTE: | |
352 | if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { | |
353 | goto std_case; | |
354 | } else { | |
cc739bb0 LD |
355 | tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); |
356 | tcg_gen_ext8u_tl(t0, t0); | |
57fec1fe FB |
357 | } |
358 | break; | |
359 | default: | |
360 | std_case: | |
cc739bb0 | 361 | tcg_gen_mov_tl(t0, cpu_regs[reg]); |
57fec1fe FB |
362 | break; |
363 | } | |
364 | } | |
365 | ||
1e4840bf FB |
366 | static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) |
367 | { | |
368 | gen_op_mov_v_reg(ot, cpu_T[t_index], reg); | |
369 | } | |
370 | ||
57fec1fe FB |
371 | static inline void gen_op_movl_A0_reg(int reg) |
372 | { | |
cc739bb0 | 373 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
374 | } |
375 | ||
376 | static inline void gen_op_addl_A0_im(int32_t val) | |
377 | { | |
378 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
14ce26e7 | 379 | #ifdef TARGET_X86_64 |
57fec1fe | 380 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); |
14ce26e7 | 381 | #endif |
57fec1fe | 382 | } |
2c0262af | 383 | |
14ce26e7 | 384 | #ifdef TARGET_X86_64 |
57fec1fe FB |
385 | static inline void gen_op_addq_A0_im(int64_t val) |
386 | { | |
387 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
388 | } | |
14ce26e7 | 389 | #endif |
57fec1fe FB |
390 | |
391 | static void gen_add_A0_im(DisasContext *s, int val) | |
392 | { | |
393 | #ifdef TARGET_X86_64 | |
394 | if (CODE64(s)) | |
395 | gen_op_addq_A0_im(val); | |
396 | else | |
397 | #endif | |
398 | gen_op_addl_A0_im(val); | |
399 | } | |
2c0262af | 400 | |
57fec1fe | 401 | static inline void gen_op_addl_T0_T1(void) |
2c0262af | 402 | { |
57fec1fe FB |
403 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
404 | } | |
405 | ||
406 | static inline void gen_op_jmp_T0(void) | |
407 | { | |
408 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip)); | |
409 | } | |
410 | ||
6e0d8677 | 411 | static inline void gen_op_add_reg_im(int size, int reg, int32_t val) |
57fec1fe | 412 | { |
6e0d8677 FB |
413 | switch(size) { |
414 | case 0: | |
cc739bb0 LD |
415 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
416 | tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0); | |
417 | tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff); | |
418 | tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0); | |
6e0d8677 FB |
419 | break; |
420 | case 1: | |
cc739bb0 LD |
421 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
422 | /* For x86_64, this sets the higher half of register to zero. | |
423 | For i386, this is equivalent to a nop. */ | |
424 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
425 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 FB |
426 | break; |
427 | #ifdef TARGET_X86_64 | |
428 | case 2: | |
cc739bb0 | 429 | tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val); |
6e0d8677 FB |
430 | break; |
431 | #endif | |
432 | } | |
57fec1fe FB |
433 | } |
434 | ||
6e0d8677 | 435 | static inline void gen_op_add_reg_T0(int size, int reg) |
57fec1fe | 436 | { |
6e0d8677 FB |
437 | switch(size) { |
438 | case 0: | |
cc739bb0 LD |
439 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
440 | tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0); | |
441 | tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff); | |
442 | tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0); | |
6e0d8677 FB |
443 | break; |
444 | case 1: | |
cc739bb0 LD |
445 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
446 | /* For x86_64, this sets the higher half of register to zero. | |
447 | For i386, this is equivalent to a nop. */ | |
448 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
449 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 | 450 | break; |
14ce26e7 | 451 | #ifdef TARGET_X86_64 |
6e0d8677 | 452 | case 2: |
cc739bb0 | 453 | tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]); |
6e0d8677 | 454 | break; |
14ce26e7 | 455 | #endif |
6e0d8677 FB |
456 | } |
457 | } | |
57fec1fe FB |
458 | |
459 | static inline void gen_op_set_cc_op(int32_t val) | |
460 | { | |
b6abf97d | 461 | tcg_gen_movi_i32(cpu_cc_op, val); |
57fec1fe FB |
462 | } |
463 | ||
464 | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) | |
465 | { | |
cc739bb0 LD |
466 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
467 | if (shift != 0) | |
57fec1fe FB |
468 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
469 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
cc739bb0 LD |
470 | /* For x86_64, this sets the higher half of register to zero. |
471 | For i386, this is equivalent to a nop. */ | |
472 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
57fec1fe | 473 | } |
2c0262af | 474 | |
57fec1fe FB |
475 | static inline void gen_op_movl_A0_seg(int reg) |
476 | { | |
477 | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET); | |
478 | } | |
2c0262af | 479 | |
57fec1fe FB |
480 | static inline void gen_op_addl_A0_seg(int reg) |
481 | { | |
482 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); | |
483 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
484 | #ifdef TARGET_X86_64 | |
485 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
486 | #endif | |
487 | } | |
2c0262af | 488 | |
14ce26e7 | 489 | #ifdef TARGET_X86_64 |
57fec1fe FB |
490 | static inline void gen_op_movq_A0_seg(int reg) |
491 | { | |
492 | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base)); | |
493 | } | |
14ce26e7 | 494 | |
57fec1fe FB |
495 | static inline void gen_op_addq_A0_seg(int reg) |
496 | { | |
497 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); | |
498 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
499 | } | |
500 | ||
501 | static inline void gen_op_movq_A0_reg(int reg) | |
502 | { | |
cc739bb0 | 503 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
504 | } |
505 | ||
506 | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) | |
507 | { | |
cc739bb0 LD |
508 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
509 | if (shift != 0) | |
57fec1fe FB |
510 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
511 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
512 | } | |
14ce26e7 FB |
513 | #endif |
514 | ||
57fec1fe FB |
515 | static inline void gen_op_lds_T0_A0(int idx) |
516 | { | |
517 | int mem_index = (idx >> 2) - 1; | |
518 | switch(idx & 3) { | |
519 | case 0: | |
520 | tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index); | |
521 | break; | |
522 | case 1: | |
523 | tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index); | |
524 | break; | |
525 | default: | |
526 | case 2: | |
527 | tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index); | |
528 | break; | |
529 | } | |
530 | } | |
2c0262af | 531 | |
1e4840bf | 532 | static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) |
57fec1fe FB |
533 | { |
534 | int mem_index = (idx >> 2) - 1; | |
535 | switch(idx & 3) { | |
536 | case 0: | |
1e4840bf | 537 | tcg_gen_qemu_ld8u(t0, a0, mem_index); |
57fec1fe FB |
538 | break; |
539 | case 1: | |
1e4840bf | 540 | tcg_gen_qemu_ld16u(t0, a0, mem_index); |
57fec1fe FB |
541 | break; |
542 | case 2: | |
1e4840bf | 543 | tcg_gen_qemu_ld32u(t0, a0, mem_index); |
57fec1fe FB |
544 | break; |
545 | default: | |
546 | case 3: | |
a7812ae4 PB |
547 | /* Should never happen on 32-bit targets. */ |
548 | #ifdef TARGET_X86_64 | |
1e4840bf | 549 | tcg_gen_qemu_ld64(t0, a0, mem_index); |
a7812ae4 | 550 | #endif |
57fec1fe FB |
551 | break; |
552 | } | |
553 | } | |
2c0262af | 554 | |
1e4840bf FB |
555 | /* XXX: always use ldu or lds */ |
556 | static inline void gen_op_ld_T0_A0(int idx) | |
557 | { | |
558 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); | |
559 | } | |
560 | ||
57fec1fe FB |
561 | static inline void gen_op_ldu_T0_A0(int idx) |
562 | { | |
1e4840bf | 563 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 564 | } |
2c0262af | 565 | |
57fec1fe | 566 | static inline void gen_op_ld_T1_A0(int idx) |
1e4840bf FB |
567 | { |
568 | gen_op_ld_v(idx, cpu_T[1], cpu_A0); | |
569 | } | |
570 | ||
571 | static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) | |
57fec1fe FB |
572 | { |
573 | int mem_index = (idx >> 2) - 1; | |
574 | switch(idx & 3) { | |
575 | case 0: | |
1e4840bf | 576 | tcg_gen_qemu_st8(t0, a0, mem_index); |
57fec1fe FB |
577 | break; |
578 | case 1: | |
1e4840bf | 579 | tcg_gen_qemu_st16(t0, a0, mem_index); |
57fec1fe FB |
580 | break; |
581 | case 2: | |
1e4840bf | 582 | tcg_gen_qemu_st32(t0, a0, mem_index); |
57fec1fe FB |
583 | break; |
584 | default: | |
585 | case 3: | |
a7812ae4 PB |
586 | /* Should never happen on 32-bit targets. */ |
587 | #ifdef TARGET_X86_64 | |
1e4840bf | 588 | tcg_gen_qemu_st64(t0, a0, mem_index); |
a7812ae4 | 589 | #endif |
57fec1fe FB |
590 | break; |
591 | } | |
592 | } | |
4f31916f | 593 | |
57fec1fe FB |
594 | static inline void gen_op_st_T0_A0(int idx) |
595 | { | |
1e4840bf | 596 | gen_op_st_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 597 | } |
4f31916f | 598 | |
57fec1fe FB |
599 | static inline void gen_op_st_T1_A0(int idx) |
600 | { | |
1e4840bf | 601 | gen_op_st_v(idx, cpu_T[1], cpu_A0); |
57fec1fe | 602 | } |
4f31916f | 603 | |
14ce26e7 FB |
604 | static inline void gen_jmp_im(target_ulong pc) |
605 | { | |
57fec1fe FB |
606 | tcg_gen_movi_tl(cpu_tmp0, pc); |
607 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip)); | |
14ce26e7 FB |
608 | } |
609 | ||
2c0262af FB |
610 | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
611 | { | |
612 | int override; | |
613 | ||
614 | override = s->override; | |
14ce26e7 FB |
615 | #ifdef TARGET_X86_64 |
616 | if (s->aflag == 2) { | |
617 | if (override >= 0) { | |
57fec1fe FB |
618 | gen_op_movq_A0_seg(override); |
619 | gen_op_addq_A0_reg_sN(0, R_ESI); | |
14ce26e7 | 620 | } else { |
57fec1fe | 621 | gen_op_movq_A0_reg(R_ESI); |
14ce26e7 FB |
622 | } |
623 | } else | |
624 | #endif | |
2c0262af FB |
625 | if (s->aflag) { |
626 | /* 32 bit address */ | |
627 | if (s->addseg && override < 0) | |
628 | override = R_DS; | |
629 | if (override >= 0) { | |
57fec1fe FB |
630 | gen_op_movl_A0_seg(override); |
631 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af | 632 | } else { |
57fec1fe | 633 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
634 | } |
635 | } else { | |
636 | /* 16 address, always override */ | |
637 | if (override < 0) | |
638 | override = R_DS; | |
57fec1fe | 639 | gen_op_movl_A0_reg(R_ESI); |
2c0262af | 640 | gen_op_andl_A0_ffff(); |
57fec1fe | 641 | gen_op_addl_A0_seg(override); |
2c0262af FB |
642 | } |
643 | } | |
644 | ||
645 | static inline void gen_string_movl_A0_EDI(DisasContext *s) | |
646 | { | |
14ce26e7 FB |
647 | #ifdef TARGET_X86_64 |
648 | if (s->aflag == 2) { | |
57fec1fe | 649 | gen_op_movq_A0_reg(R_EDI); |
14ce26e7 FB |
650 | } else |
651 | #endif | |
2c0262af FB |
652 | if (s->aflag) { |
653 | if (s->addseg) { | |
57fec1fe FB |
654 | gen_op_movl_A0_seg(R_ES); |
655 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af | 656 | } else { |
57fec1fe | 657 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
658 | } |
659 | } else { | |
57fec1fe | 660 | gen_op_movl_A0_reg(R_EDI); |
2c0262af | 661 | gen_op_andl_A0_ffff(); |
57fec1fe | 662 | gen_op_addl_A0_seg(R_ES); |
2c0262af FB |
663 | } |
664 | } | |
665 | ||
6e0d8677 FB |
666 | static inline void gen_op_movl_T0_Dshift(int ot) |
667 | { | |
668 | tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df)); | |
669 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); | |
2c0262af FB |
670 | }; |
671 | ||
6e0d8677 FB |
672 | static void gen_extu(int ot, TCGv reg) |
673 | { | |
674 | switch(ot) { | |
675 | case OT_BYTE: | |
676 | tcg_gen_ext8u_tl(reg, reg); | |
677 | break; | |
678 | case OT_WORD: | |
679 | tcg_gen_ext16u_tl(reg, reg); | |
680 | break; | |
681 | case OT_LONG: | |
682 | tcg_gen_ext32u_tl(reg, reg); | |
683 | break; | |
684 | default: | |
685 | break; | |
686 | } | |
687 | } | |
3b46e624 | 688 | |
6e0d8677 FB |
689 | static void gen_exts(int ot, TCGv reg) |
690 | { | |
691 | switch(ot) { | |
692 | case OT_BYTE: | |
693 | tcg_gen_ext8s_tl(reg, reg); | |
694 | break; | |
695 | case OT_WORD: | |
696 | tcg_gen_ext16s_tl(reg, reg); | |
697 | break; | |
698 | case OT_LONG: | |
699 | tcg_gen_ext32s_tl(reg, reg); | |
700 | break; | |
701 | default: | |
702 | break; | |
703 | } | |
704 | } | |
2c0262af | 705 | |
6e0d8677 FB |
706 | static inline void gen_op_jnz_ecx(int size, int label1) |
707 | { | |
cc739bb0 | 708 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 709 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 710 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); |
6e0d8677 FB |
711 | } |
712 | ||
713 | static inline void gen_op_jz_ecx(int size, int label1) | |
714 | { | |
cc739bb0 | 715 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 716 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 717 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
6e0d8677 | 718 | } |
2c0262af | 719 | |
a7812ae4 PB |
720 | static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n) |
721 | { | |
722 | switch (ot) { | |
723 | case 0: gen_helper_inb(v, n); break; | |
724 | case 1: gen_helper_inw(v, n); break; | |
725 | case 2: gen_helper_inl(v, n); break; | |
726 | } | |
2c0262af | 727 | |
a7812ae4 | 728 | } |
2c0262af | 729 | |
a7812ae4 PB |
730 | static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n) |
731 | { | |
732 | switch (ot) { | |
733 | case 0: gen_helper_outb(v, n); break; | |
734 | case 1: gen_helper_outw(v, n); break; | |
735 | case 2: gen_helper_outl(v, n); break; | |
736 | } | |
737 | ||
738 | } | |
f115e911 | 739 | |
b8b6a50b FB |
740 | static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, |
741 | uint32_t svm_flags) | |
f115e911 | 742 | { |
b8b6a50b FB |
743 | int state_saved; |
744 | target_ulong next_eip; | |
745 | ||
746 | state_saved = 0; | |
f115e911 FB |
747 | if (s->pe && (s->cpl > s->iopl || s->vm86)) { |
748 | if (s->cc_op != CC_OP_DYNAMIC) | |
749 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 750 | gen_jmp_im(cur_eip); |
b8b6a50b | 751 | state_saved = 1; |
b6abf97d | 752 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
753 | switch (ot) { |
754 | case 0: gen_helper_check_iob(cpu_tmp2_i32); break; | |
755 | case 1: gen_helper_check_iow(cpu_tmp2_i32); break; | |
756 | case 2: gen_helper_check_iol(cpu_tmp2_i32); break; | |
757 | } | |
b8b6a50b | 758 | } |
872929aa | 759 | if(s->flags & HF_SVMI_MASK) { |
b8b6a50b FB |
760 | if (!state_saved) { |
761 | if (s->cc_op != CC_OP_DYNAMIC) | |
762 | gen_op_set_cc_op(s->cc_op); | |
763 | gen_jmp_im(cur_eip); | |
764 | state_saved = 1; | |
765 | } | |
766 | svm_flags |= (1 << (4 + ot)); | |
767 | next_eip = s->pc - s->cs_base; | |
b6abf97d | 768 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
769 | gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags), |
770 | tcg_const_i32(next_eip - cur_eip)); | |
f115e911 FB |
771 | } |
772 | } | |
773 | ||
2c0262af FB |
774 | static inline void gen_movs(DisasContext *s, int ot) |
775 | { | |
776 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 777 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 778 | gen_string_movl_A0_EDI(s); |
57fec1fe | 779 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
780 | gen_op_movl_T0_Dshift(ot); |
781 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
782 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
783 | } |
784 | ||
785 | static inline void gen_update_cc_op(DisasContext *s) | |
786 | { | |
787 | if (s->cc_op != CC_OP_DYNAMIC) { | |
788 | gen_op_set_cc_op(s->cc_op); | |
789 | s->cc_op = CC_OP_DYNAMIC; | |
790 | } | |
791 | } | |
792 | ||
b6abf97d FB |
793 | static void gen_op_update1_cc(void) |
794 | { | |
795 | tcg_gen_discard_tl(cpu_cc_src); | |
796 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
797 | } | |
798 | ||
799 | static void gen_op_update2_cc(void) | |
800 | { | |
801 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
802 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
803 | } | |
804 | ||
805 | static inline void gen_op_cmpl_T0_T1_cc(void) | |
806 | { | |
807 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
808 | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
809 | } | |
810 | ||
811 | static inline void gen_op_testl_T0_T1_cc(void) | |
812 | { | |
813 | tcg_gen_discard_tl(cpu_cc_src); | |
814 | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
815 | } | |
816 | ||
817 | static void gen_op_update_neg_cc(void) | |
818 | { | |
819 | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]); | |
820 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
821 | } | |
822 | ||
8e1c85e3 FB |
823 | /* compute eflags.C to reg */ |
824 | static void gen_compute_eflags_c(TCGv reg) | |
825 | { | |
a7812ae4 | 826 | gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op); |
8e1c85e3 FB |
827 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
828 | } | |
829 | ||
830 | /* compute all eflags to cc_src */ | |
831 | static void gen_compute_eflags(TCGv reg) | |
832 | { | |
a7812ae4 | 833 | gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op); |
8e1c85e3 FB |
834 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
835 | } | |
836 | ||
1e4840bf | 837 | static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) |
8e1c85e3 | 838 | { |
1e4840bf FB |
839 | if (s->cc_op != CC_OP_DYNAMIC) |
840 | gen_op_set_cc_op(s->cc_op); | |
841 | switch(jcc_op) { | |
8e1c85e3 FB |
842 | case JCC_O: |
843 | gen_compute_eflags(cpu_T[0]); | |
844 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11); | |
845 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
846 | break; | |
847 | case JCC_B: | |
848 | gen_compute_eflags_c(cpu_T[0]); | |
849 | break; | |
850 | case JCC_Z: | |
851 | gen_compute_eflags(cpu_T[0]); | |
852 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6); | |
853 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
854 | break; | |
855 | case JCC_BE: | |
856 | gen_compute_eflags(cpu_tmp0); | |
857 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6); | |
858 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
859 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
860 | break; | |
861 | case JCC_S: | |
862 | gen_compute_eflags(cpu_T[0]); | |
863 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7); | |
864 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
865 | break; | |
866 | case JCC_P: | |
867 | gen_compute_eflags(cpu_T[0]); | |
868 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2); | |
869 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
870 | break; | |
871 | case JCC_L: | |
872 | gen_compute_eflags(cpu_tmp0); | |
873 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ | |
874 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */ | |
875 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
876 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
877 | break; | |
878 | default: | |
879 | case JCC_LE: | |
880 | gen_compute_eflags(cpu_tmp0); | |
881 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ | |
882 | tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */ | |
883 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */ | |
884 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
885 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
886 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
887 | break; | |
888 | } | |
889 | } | |
890 | ||
891 | /* return true if setcc_slow is not needed (WARNING: must be kept in | |
892 | sync with gen_jcc1) */ | |
893 | static int is_fast_jcc_case(DisasContext *s, int b) | |
894 | { | |
895 | int jcc_op; | |
896 | jcc_op = (b >> 1) & 7; | |
897 | switch(s->cc_op) { | |
898 | /* we optimize the cmp/jcc case */ | |
899 | case CC_OP_SUBB: | |
900 | case CC_OP_SUBW: | |
901 | case CC_OP_SUBL: | |
902 | case CC_OP_SUBQ: | |
903 | if (jcc_op == JCC_O || jcc_op == JCC_P) | |
904 | goto slow_jcc; | |
905 | break; | |
906 | ||
907 | /* some jumps are easy to compute */ | |
908 | case CC_OP_ADDB: | |
909 | case CC_OP_ADDW: | |
910 | case CC_OP_ADDL: | |
911 | case CC_OP_ADDQ: | |
912 | ||
913 | case CC_OP_LOGICB: | |
914 | case CC_OP_LOGICW: | |
915 | case CC_OP_LOGICL: | |
916 | case CC_OP_LOGICQ: | |
917 | ||
918 | case CC_OP_INCB: | |
919 | case CC_OP_INCW: | |
920 | case CC_OP_INCL: | |
921 | case CC_OP_INCQ: | |
922 | ||
923 | case CC_OP_DECB: | |
924 | case CC_OP_DECW: | |
925 | case CC_OP_DECL: | |
926 | case CC_OP_DECQ: | |
927 | ||
928 | case CC_OP_SHLB: | |
929 | case CC_OP_SHLW: | |
930 | case CC_OP_SHLL: | |
931 | case CC_OP_SHLQ: | |
932 | if (jcc_op != JCC_Z && jcc_op != JCC_S) | |
933 | goto slow_jcc; | |
934 | break; | |
935 | default: | |
936 | slow_jcc: | |
937 | return 0; | |
938 | } | |
939 | return 1; | |
940 | } | |
941 | ||
942 | /* generate a conditional jump to label 'l1' according to jump opcode | |
943 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
944 | static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1) | |
945 | { | |
946 | int inv, jcc_op, size, cond; | |
947 | TCGv t0; | |
948 | ||
949 | inv = b & 1; | |
950 | jcc_op = (b >> 1) & 7; | |
951 | ||
952 | switch(cc_op) { | |
953 | /* we optimize the cmp/jcc case */ | |
954 | case CC_OP_SUBB: | |
955 | case CC_OP_SUBW: | |
956 | case CC_OP_SUBL: | |
957 | case CC_OP_SUBQ: | |
958 | ||
959 | size = cc_op - CC_OP_SUBB; | |
960 | switch(jcc_op) { | |
961 | case JCC_Z: | |
962 | fast_jcc_z: | |
963 | switch(size) { | |
964 | case 0: | |
965 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff); | |
966 | t0 = cpu_tmp0; | |
967 | break; | |
968 | case 1: | |
969 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff); | |
970 | t0 = cpu_tmp0; | |
971 | break; | |
972 | #ifdef TARGET_X86_64 | |
973 | case 2: | |
974 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff); | |
975 | t0 = cpu_tmp0; | |
976 | break; | |
977 | #endif | |
978 | default: | |
979 | t0 = cpu_cc_dst; | |
980 | break; | |
981 | } | |
cb63669a | 982 | tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1); |
8e1c85e3 FB |
983 | break; |
984 | case JCC_S: | |
985 | fast_jcc_s: | |
986 | switch(size) { | |
987 | case 0: | |
988 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80); | |
cb63669a PB |
989 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
990 | 0, l1); | |
8e1c85e3 FB |
991 | break; |
992 | case 1: | |
993 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000); | |
cb63669a PB |
994 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
995 | 0, l1); | |
8e1c85e3 FB |
996 | break; |
997 | #ifdef TARGET_X86_64 | |
998 | case 2: | |
999 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000); | |
cb63669a PB |
1000 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
1001 | 0, l1); | |
8e1c85e3 FB |
1002 | break; |
1003 | #endif | |
1004 | default: | |
cb63669a PB |
1005 | tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, |
1006 | 0, l1); | |
8e1c85e3 FB |
1007 | break; |
1008 | } | |
1009 | break; | |
1010 | ||
1011 | case JCC_B: | |
1012 | cond = inv ? TCG_COND_GEU : TCG_COND_LTU; | |
1013 | goto fast_jcc_b; | |
1014 | case JCC_BE: | |
1015 | cond = inv ? TCG_COND_GTU : TCG_COND_LEU; | |
1016 | fast_jcc_b: | |
1017 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
1018 | switch(size) { | |
1019 | case 0: | |
1020 | t0 = cpu_tmp0; | |
1021 | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff); | |
1022 | tcg_gen_andi_tl(t0, cpu_cc_src, 0xff); | |
1023 | break; | |
1024 | case 1: | |
1025 | t0 = cpu_tmp0; | |
1026 | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff); | |
1027 | tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff); | |
1028 | break; | |
1029 | #ifdef TARGET_X86_64 | |
1030 | case 2: | |
1031 | t0 = cpu_tmp0; | |
1032 | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff); | |
1033 | tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff); | |
1034 | break; | |
1035 | #endif | |
1036 | default: | |
1037 | t0 = cpu_cc_src; | |
1038 | break; | |
1039 | } | |
1040 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); | |
1041 | break; | |
1042 | ||
1043 | case JCC_L: | |
1044 | cond = inv ? TCG_COND_GE : TCG_COND_LT; | |
1045 | goto fast_jcc_l; | |
1046 | case JCC_LE: | |
1047 | cond = inv ? TCG_COND_GT : TCG_COND_LE; | |
1048 | fast_jcc_l: | |
1049 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
1050 | switch(size) { | |
1051 | case 0: | |
1052 | t0 = cpu_tmp0; | |
1053 | tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4); | |
1054 | tcg_gen_ext8s_tl(t0, cpu_cc_src); | |
1055 | break; | |
1056 | case 1: | |
1057 | t0 = cpu_tmp0; | |
1058 | tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4); | |
1059 | tcg_gen_ext16s_tl(t0, cpu_cc_src); | |
1060 | break; | |
1061 | #ifdef TARGET_X86_64 | |
1062 | case 2: | |
1063 | t0 = cpu_tmp0; | |
1064 | tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4); | |
1065 | tcg_gen_ext32s_tl(t0, cpu_cc_src); | |
1066 | break; | |
1067 | #endif | |
1068 | default: | |
1069 | t0 = cpu_cc_src; | |
1070 | break; | |
1071 | } | |
1072 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); | |
1073 | break; | |
1074 | ||
1075 | default: | |
1076 | goto slow_jcc; | |
1077 | } | |
1078 | break; | |
1079 | ||
1080 | /* some jumps are easy to compute */ | |
1081 | case CC_OP_ADDB: | |
1082 | case CC_OP_ADDW: | |
1083 | case CC_OP_ADDL: | |
1084 | case CC_OP_ADDQ: | |
1085 | ||
1086 | case CC_OP_ADCB: | |
1087 | case CC_OP_ADCW: | |
1088 | case CC_OP_ADCL: | |
1089 | case CC_OP_ADCQ: | |
1090 | ||
1091 | case CC_OP_SBBB: | |
1092 | case CC_OP_SBBW: | |
1093 | case CC_OP_SBBL: | |
1094 | case CC_OP_SBBQ: | |
1095 | ||
1096 | case CC_OP_LOGICB: | |
1097 | case CC_OP_LOGICW: | |
1098 | case CC_OP_LOGICL: | |
1099 | case CC_OP_LOGICQ: | |
1100 | ||
1101 | case CC_OP_INCB: | |
1102 | case CC_OP_INCW: | |
1103 | case CC_OP_INCL: | |
1104 | case CC_OP_INCQ: | |
1105 | ||
1106 | case CC_OP_DECB: | |
1107 | case CC_OP_DECW: | |
1108 | case CC_OP_DECL: | |
1109 | case CC_OP_DECQ: | |
1110 | ||
1111 | case CC_OP_SHLB: | |
1112 | case CC_OP_SHLW: | |
1113 | case CC_OP_SHLL: | |
1114 | case CC_OP_SHLQ: | |
1115 | ||
1116 | case CC_OP_SARB: | |
1117 | case CC_OP_SARW: | |
1118 | case CC_OP_SARL: | |
1119 | case CC_OP_SARQ: | |
1120 | switch(jcc_op) { | |
1121 | case JCC_Z: | |
1122 | size = (cc_op - CC_OP_ADDB) & 3; | |
1123 | goto fast_jcc_z; | |
1124 | case JCC_S: | |
1125 | size = (cc_op - CC_OP_ADDB) & 3; | |
1126 | goto fast_jcc_s; | |
1127 | default: | |
1128 | goto slow_jcc; | |
1129 | } | |
1130 | break; | |
1131 | default: | |
1132 | slow_jcc: | |
1e4840bf | 1133 | gen_setcc_slow_T0(s, jcc_op); |
cb63669a PB |
1134 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, |
1135 | cpu_T[0], 0, l1); | |
8e1c85e3 FB |
1136 | break; |
1137 | } | |
1138 | } | |
1139 | ||
14ce26e7 FB |
1140 | /* XXX: does not work with gdbstub "ice" single step - not a |
1141 | serious problem */ | |
1142 | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) | |
2c0262af | 1143 | { |
14ce26e7 FB |
1144 | int l1, l2; |
1145 | ||
1146 | l1 = gen_new_label(); | |
1147 | l2 = gen_new_label(); | |
6e0d8677 | 1148 | gen_op_jnz_ecx(s->aflag, l1); |
14ce26e7 FB |
1149 | gen_set_label(l2); |
1150 | gen_jmp_tb(s, next_eip, 1); | |
1151 | gen_set_label(l1); | |
1152 | return l2; | |
2c0262af FB |
1153 | } |
1154 | ||
1155 | static inline void gen_stos(DisasContext *s, int ot) | |
1156 | { | |
57fec1fe | 1157 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1158 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1159 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1160 | gen_op_movl_T0_Dshift(ot); |
1161 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1162 | } |
1163 | ||
1164 | static inline void gen_lods(DisasContext *s, int ot) | |
1165 | { | |
1166 | gen_string_movl_A0_ESI(s); | |
57fec1fe FB |
1167 | gen_op_ld_T0_A0(ot + s->mem_index); |
1168 | gen_op_mov_reg_T0(ot, R_EAX); | |
6e0d8677 FB |
1169 | gen_op_movl_T0_Dshift(ot); |
1170 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2c0262af FB |
1171 | } |
1172 | ||
1173 | static inline void gen_scas(DisasContext *s, int ot) | |
1174 | { | |
57fec1fe | 1175 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1176 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1177 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1178 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1179 | gen_op_movl_T0_Dshift(ot); |
1180 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1181 | } |
1182 | ||
1183 | static inline void gen_cmps(DisasContext *s, int ot) | |
1184 | { | |
1185 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 1186 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 1187 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1188 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1189 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1190 | gen_op_movl_T0_Dshift(ot); |
1191 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
1192 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1193 | } |
1194 | ||
1195 | static inline void gen_ins(DisasContext *s, int ot) | |
1196 | { | |
2e70f6ef PB |
1197 | if (use_icount) |
1198 | gen_io_start(); | |
2c0262af | 1199 | gen_string_movl_A0_EDI(s); |
6e0d8677 FB |
1200 | /* Note: we must do this dummy write first to be restartable in |
1201 | case of page fault. */ | |
9772c73b | 1202 | gen_op_movl_T0_0(); |
57fec1fe | 1203 | gen_op_st_T0_A0(ot + s->mem_index); |
b8b6a50b | 1204 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); |
b6abf97d FB |
1205 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1206 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
a7812ae4 | 1207 | gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 1208 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1209 | gen_op_movl_T0_Dshift(ot); |
1210 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2e70f6ef PB |
1211 | if (use_icount) |
1212 | gen_io_end(); | |
2c0262af FB |
1213 | } |
1214 | ||
1215 | static inline void gen_outs(DisasContext *s, int ot) | |
1216 | { | |
2e70f6ef PB |
1217 | if (use_icount) |
1218 | gen_io_start(); | |
2c0262af | 1219 | gen_string_movl_A0_ESI(s); |
57fec1fe | 1220 | gen_op_ld_T0_A0(ot + s->mem_index); |
b8b6a50b FB |
1221 | |
1222 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); | |
b6abf97d FB |
1223 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1224 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
1225 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); | |
a7812ae4 | 1226 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
b8b6a50b | 1227 | |
6e0d8677 FB |
1228 | gen_op_movl_T0_Dshift(ot); |
1229 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2e70f6ef PB |
1230 | if (use_icount) |
1231 | gen_io_end(); | |
2c0262af FB |
1232 | } |
1233 | ||
1234 | /* same method as Valgrind : we generate jumps to current or next | |
1235 | instruction */ | |
1236 | #define GEN_REPZ(op) \ | |
1237 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 | 1238 | target_ulong cur_eip, target_ulong next_eip) \ |
2c0262af | 1239 | { \ |
14ce26e7 | 1240 | int l2;\ |
2c0262af | 1241 | gen_update_cc_op(s); \ |
14ce26e7 | 1242 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1243 | gen_ ## op(s, ot); \ |
6e0d8677 | 1244 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af FB |
1245 | /* a loop would cause two single step exceptions if ECX = 1 \ |
1246 | before rep string_insn */ \ | |
1247 | if (!s->jmp_opt) \ | |
6e0d8677 | 1248 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1249 | gen_jmp(s, cur_eip); \ |
1250 | } | |
1251 | ||
1252 | #define GEN_REPZ2(op) \ | |
1253 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 FB |
1254 | target_ulong cur_eip, \ |
1255 | target_ulong next_eip, \ | |
2c0262af FB |
1256 | int nz) \ |
1257 | { \ | |
14ce26e7 | 1258 | int l2;\ |
2c0262af | 1259 | gen_update_cc_op(s); \ |
14ce26e7 | 1260 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1261 | gen_ ## op(s, ot); \ |
6e0d8677 | 1262 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af | 1263 | gen_op_set_cc_op(CC_OP_SUBB + ot); \ |
8e1c85e3 | 1264 | gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \ |
2c0262af | 1265 | if (!s->jmp_opt) \ |
6e0d8677 | 1266 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1267 | gen_jmp(s, cur_eip); \ |
1268 | } | |
1269 | ||
1270 | GEN_REPZ(movs) | |
1271 | GEN_REPZ(stos) | |
1272 | GEN_REPZ(lods) | |
1273 | GEN_REPZ(ins) | |
1274 | GEN_REPZ(outs) | |
1275 | GEN_REPZ2(scas) | |
1276 | GEN_REPZ2(cmps) | |
1277 | ||
a7812ae4 PB |
1278 | static void gen_helper_fp_arith_ST0_FT0(int op) |
1279 | { | |
1280 | switch (op) { | |
1281 | case 0: gen_helper_fadd_ST0_FT0(); break; | |
1282 | case 1: gen_helper_fmul_ST0_FT0(); break; | |
1283 | case 2: gen_helper_fcom_ST0_FT0(); break; | |
1284 | case 3: gen_helper_fcom_ST0_FT0(); break; | |
1285 | case 4: gen_helper_fsub_ST0_FT0(); break; | |
1286 | case 5: gen_helper_fsubr_ST0_FT0(); break; | |
1287 | case 6: gen_helper_fdiv_ST0_FT0(); break; | |
1288 | case 7: gen_helper_fdivr_ST0_FT0(); break; | |
1289 | } | |
1290 | } | |
2c0262af FB |
1291 | |
1292 | /* NOTE the exception in "r" op ordering */ | |
a7812ae4 PB |
1293 | static void gen_helper_fp_arith_STN_ST0(int op, int opreg) |
1294 | { | |
1295 | TCGv_i32 tmp = tcg_const_i32(opreg); | |
1296 | switch (op) { | |
1297 | case 0: gen_helper_fadd_STN_ST0(tmp); break; | |
1298 | case 1: gen_helper_fmul_STN_ST0(tmp); break; | |
1299 | case 4: gen_helper_fsubr_STN_ST0(tmp); break; | |
1300 | case 5: gen_helper_fsub_STN_ST0(tmp); break; | |
1301 | case 6: gen_helper_fdivr_STN_ST0(tmp); break; | |
1302 | case 7: gen_helper_fdiv_STN_ST0(tmp); break; | |
1303 | } | |
1304 | } | |
2c0262af FB |
1305 | |
1306 | /* if d == OR_TMP0, it means memory operand (address in A0) */ | |
1307 | static void gen_op(DisasContext *s1, int op, int ot, int d) | |
1308 | { | |
2c0262af | 1309 | if (d != OR_TMP0) { |
57fec1fe | 1310 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1311 | } else { |
57fec1fe | 1312 | gen_op_ld_T0_A0(ot + s1->mem_index); |
2c0262af FB |
1313 | } |
1314 | switch(op) { | |
1315 | case OP_ADCL: | |
cad3a37d FB |
1316 | if (s1->cc_op != CC_OP_DYNAMIC) |
1317 | gen_op_set_cc_op(s1->cc_op); | |
1318 | gen_compute_eflags_c(cpu_tmp4); | |
1319 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1320 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1321 | if (d != OR_TMP0) | |
1322 | gen_op_mov_reg_T0(ot, d); | |
1323 | else | |
1324 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1325 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1326 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1327 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1328 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1329 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot); | |
1330 | s1->cc_op = CC_OP_DYNAMIC; | |
1331 | break; | |
2c0262af FB |
1332 | case OP_SBBL: |
1333 | if (s1->cc_op != CC_OP_DYNAMIC) | |
1334 | gen_op_set_cc_op(s1->cc_op); | |
cad3a37d FB |
1335 | gen_compute_eflags_c(cpu_tmp4); |
1336 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1337 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1338 | if (d != OR_TMP0) | |
57fec1fe | 1339 | gen_op_mov_reg_T0(ot, d); |
cad3a37d FB |
1340 | else |
1341 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1342 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1343 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1344 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1345 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1346 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot); | |
2c0262af | 1347 | s1->cc_op = CC_OP_DYNAMIC; |
cad3a37d | 1348 | break; |
2c0262af FB |
1349 | case OP_ADDL: |
1350 | gen_op_addl_T0_T1(); | |
cad3a37d FB |
1351 | if (d != OR_TMP0) |
1352 | gen_op_mov_reg_T0(ot, d); | |
1353 | else | |
1354 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1355 | gen_op_update2_cc(); | |
2c0262af | 1356 | s1->cc_op = CC_OP_ADDB + ot; |
2c0262af FB |
1357 | break; |
1358 | case OP_SUBL: | |
57fec1fe | 1359 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1360 | if (d != OR_TMP0) |
1361 | gen_op_mov_reg_T0(ot, d); | |
1362 | else | |
1363 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1364 | gen_op_update2_cc(); | |
2c0262af | 1365 | s1->cc_op = CC_OP_SUBB + ot; |
2c0262af FB |
1366 | break; |
1367 | default: | |
1368 | case OP_ANDL: | |
57fec1fe | 1369 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1370 | if (d != OR_TMP0) |
1371 | gen_op_mov_reg_T0(ot, d); | |
1372 | else | |
1373 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1374 | gen_op_update1_cc(); | |
57fec1fe | 1375 | s1->cc_op = CC_OP_LOGICB + ot; |
57fec1fe | 1376 | break; |
2c0262af | 1377 | case OP_ORL: |
57fec1fe | 1378 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1379 | if (d != OR_TMP0) |
1380 | gen_op_mov_reg_T0(ot, d); | |
1381 | else | |
1382 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1383 | gen_op_update1_cc(); | |
57fec1fe | 1384 | s1->cc_op = CC_OP_LOGICB + ot; |
57fec1fe | 1385 | break; |
2c0262af | 1386 | case OP_XORL: |
57fec1fe | 1387 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1388 | if (d != OR_TMP0) |
1389 | gen_op_mov_reg_T0(ot, d); | |
1390 | else | |
1391 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1392 | gen_op_update1_cc(); | |
2c0262af | 1393 | s1->cc_op = CC_OP_LOGICB + ot; |
2c0262af FB |
1394 | break; |
1395 | case OP_CMPL: | |
1396 | gen_op_cmpl_T0_T1_cc(); | |
1397 | s1->cc_op = CC_OP_SUBB + ot; | |
2c0262af FB |
1398 | break; |
1399 | } | |
b6abf97d FB |
1400 | } |
1401 | ||
2c0262af FB |
1402 | /* if d == OR_TMP0, it means memory operand (address in A0) */ |
1403 | static void gen_inc(DisasContext *s1, int ot, int d, int c) | |
1404 | { | |
1405 | if (d != OR_TMP0) | |
57fec1fe | 1406 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1407 | else |
57fec1fe | 1408 | gen_op_ld_T0_A0(ot + s1->mem_index); |
2c0262af FB |
1409 | if (s1->cc_op != CC_OP_DYNAMIC) |
1410 | gen_op_set_cc_op(s1->cc_op); | |
1411 | if (c > 0) { | |
b6abf97d | 1412 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
2c0262af FB |
1413 | s1->cc_op = CC_OP_INCB + ot; |
1414 | } else { | |
b6abf97d | 1415 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
2c0262af FB |
1416 | s1->cc_op = CC_OP_DECB + ot; |
1417 | } | |
1418 | if (d != OR_TMP0) | |
57fec1fe | 1419 | gen_op_mov_reg_T0(ot, d); |
2c0262af | 1420 | else |
57fec1fe | 1421 | gen_op_st_T0_A0(ot + s1->mem_index); |
b6abf97d | 1422 | gen_compute_eflags_c(cpu_cc_src); |
cd31fefa | 1423 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
2c0262af FB |
1424 | } |
1425 | ||
b6abf97d FB |
1426 | static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
1427 | int is_right, int is_arith) | |
2c0262af | 1428 | { |
b6abf97d FB |
1429 | target_ulong mask; |
1430 | int shift_label; | |
1e4840bf FB |
1431 | TCGv t0, t1; |
1432 | ||
b6abf97d FB |
1433 | if (ot == OT_QUAD) |
1434 | mask = 0x3f; | |
2c0262af | 1435 | else |
b6abf97d | 1436 | mask = 0x1f; |
3b46e624 | 1437 | |
b6abf97d FB |
1438 | /* load */ |
1439 | if (op1 == OR_TMP0) | |
1440 | gen_op_ld_T0_A0(ot + s->mem_index); | |
2c0262af | 1441 | else |
b6abf97d FB |
1442 | gen_op_mov_TN_reg(ot, 0, op1); |
1443 | ||
1444 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); | |
1445 | ||
1446 | tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1); | |
1447 | ||
1448 | if (is_right) { | |
1449 | if (is_arith) { | |
f484d386 | 1450 | gen_exts(ot, cpu_T[0]); |
b6abf97d FB |
1451 | tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5); |
1452 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1453 | } else { | |
cad3a37d | 1454 | gen_extu(ot, cpu_T[0]); |
b6abf97d FB |
1455 | tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5); |
1456 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1457 | } | |
1458 | } else { | |
1459 | tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5); | |
1460 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1461 | } | |
1462 | ||
1463 | /* store */ | |
1464 | if (op1 == OR_TMP0) | |
1465 | gen_op_st_T0_A0(ot + s->mem_index); | |
1466 | else | |
1467 | gen_op_mov_reg_T0(ot, op1); | |
1468 | ||
1469 | /* update eflags if non zero shift */ | |
1470 | if (s->cc_op != CC_OP_DYNAMIC) | |
1471 | gen_op_set_cc_op(s->cc_op); | |
1472 | ||
1e4840bf | 1473 | /* XXX: inefficient */ |
a7812ae4 PB |
1474 | t0 = tcg_temp_local_new(); |
1475 | t1 = tcg_temp_local_new(); | |
1e4840bf FB |
1476 | |
1477 | tcg_gen_mov_tl(t0, cpu_T[0]); | |
1478 | tcg_gen_mov_tl(t1, cpu_T3); | |
1479 | ||
b6abf97d | 1480 | shift_label = gen_new_label(); |
cb63669a | 1481 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label); |
b6abf97d | 1482 | |
1e4840bf FB |
1483 | tcg_gen_mov_tl(cpu_cc_src, t1); |
1484 | tcg_gen_mov_tl(cpu_cc_dst, t0); | |
b6abf97d FB |
1485 | if (is_right) |
1486 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); | |
1487 | else | |
1488 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); | |
1489 | ||
1490 | gen_set_label(shift_label); | |
1491 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1e4840bf FB |
1492 | |
1493 | tcg_temp_free(t0); | |
1494 | tcg_temp_free(t1); | |
b6abf97d FB |
1495 | } |
1496 | ||
c1c37968 FB |
1497 | static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, |
1498 | int is_right, int is_arith) | |
1499 | { | |
1500 | int mask; | |
1501 | ||
1502 | if (ot == OT_QUAD) | |
1503 | mask = 0x3f; | |
1504 | else | |
1505 | mask = 0x1f; | |
1506 | ||
1507 | /* load */ | |
1508 | if (op1 == OR_TMP0) | |
1509 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1510 | else | |
1511 | gen_op_mov_TN_reg(ot, 0, op1); | |
1512 | ||
1513 | op2 &= mask; | |
1514 | if (op2 != 0) { | |
1515 | if (is_right) { | |
1516 | if (is_arith) { | |
1517 | gen_exts(ot, cpu_T[0]); | |
2a449d14 | 1518 | tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1519 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
1520 | } else { | |
1521 | gen_extu(ot, cpu_T[0]); | |
2a449d14 | 1522 | tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1523 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
1524 | } | |
1525 | } else { | |
2a449d14 | 1526 | tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1527 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
1528 | } | |
1529 | } | |
1530 | ||
1531 | /* store */ | |
1532 | if (op1 == OR_TMP0) | |
1533 | gen_op_st_T0_A0(ot + s->mem_index); | |
1534 | else | |
1535 | gen_op_mov_reg_T0(ot, op1); | |
1536 | ||
1537 | /* update eflags if non zero shift */ | |
1538 | if (op2 != 0) { | |
2a449d14 | 1539 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
c1c37968 FB |
1540 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
1541 | if (is_right) | |
1542 | s->cc_op = CC_OP_SARB + ot; | |
1543 | else | |
1544 | s->cc_op = CC_OP_SHLB + ot; | |
1545 | } | |
1546 | } | |
1547 | ||
b6abf97d FB |
1548 | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1549 | { | |
1550 | if (arg2 >= 0) | |
1551 | tcg_gen_shli_tl(ret, arg1, arg2); | |
1552 | else | |
1553 | tcg_gen_shri_tl(ret, arg1, -arg2); | |
1554 | } | |
1555 | ||
b6abf97d FB |
1556 | static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, |
1557 | int is_right) | |
1558 | { | |
1559 | target_ulong mask; | |
1560 | int label1, label2, data_bits; | |
1e4840bf FB |
1561 | TCGv t0, t1, t2, a0; |
1562 | ||
1563 | /* XXX: inefficient, but we must use local temps */ | |
a7812ae4 PB |
1564 | t0 = tcg_temp_local_new(); |
1565 | t1 = tcg_temp_local_new(); | |
1566 | t2 = tcg_temp_local_new(); | |
1567 | a0 = tcg_temp_local_new(); | |
1e4840bf | 1568 | |
b6abf97d FB |
1569 | if (ot == OT_QUAD) |
1570 | mask = 0x3f; | |
1571 | else | |
1572 | mask = 0x1f; | |
1573 | ||
1574 | /* load */ | |
1e4840bf FB |
1575 | if (op1 == OR_TMP0) { |
1576 | tcg_gen_mov_tl(a0, cpu_A0); | |
1577 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1578 | } else { | |
1579 | gen_op_mov_v_reg(ot, t0, op1); | |
1580 | } | |
b6abf97d | 1581 | |
1e4840bf FB |
1582 | tcg_gen_mov_tl(t1, cpu_T[1]); |
1583 | ||
1584 | tcg_gen_andi_tl(t1, t1, mask); | |
b6abf97d FB |
1585 | |
1586 | /* Must test zero case to avoid using undefined behaviour in TCG | |
1587 | shifts. */ | |
1588 | label1 = gen_new_label(); | |
1e4840bf | 1589 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1); |
b6abf97d FB |
1590 | |
1591 | if (ot <= OT_WORD) | |
1e4840bf | 1592 | tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); |
b6abf97d | 1593 | else |
1e4840bf | 1594 | tcg_gen_mov_tl(cpu_tmp0, t1); |
b6abf97d | 1595 | |
1e4840bf FB |
1596 | gen_extu(ot, t0); |
1597 | tcg_gen_mov_tl(t2, t0); | |
b6abf97d FB |
1598 | |
1599 | data_bits = 8 << ot; | |
1600 | /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX: | |
1601 | fix TCG definition) */ | |
1602 | if (is_right) { | |
1e4840bf | 1603 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1604 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1605 | tcg_gen_shl_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1606 | } else { |
1e4840bf | 1607 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1608 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1609 | tcg_gen_shr_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1610 | } |
1e4840bf | 1611 | tcg_gen_or_tl(t0, t0, cpu_tmp4); |
b6abf97d FB |
1612 | |
1613 | gen_set_label(label1); | |
1614 | /* store */ | |
1e4840bf FB |
1615 | if (op1 == OR_TMP0) { |
1616 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1617 | } else { | |
1618 | gen_op_mov_reg_v(ot, op1, t0); | |
1619 | } | |
b6abf97d FB |
1620 | |
1621 | /* update eflags */ | |
1622 | if (s->cc_op != CC_OP_DYNAMIC) | |
1623 | gen_op_set_cc_op(s->cc_op); | |
1624 | ||
1625 | label2 = gen_new_label(); | |
1e4840bf | 1626 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2); |
b6abf97d FB |
1627 | |
1628 | gen_compute_eflags(cpu_cc_src); | |
1629 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); | |
1e4840bf | 1630 | tcg_gen_xor_tl(cpu_tmp0, t2, t0); |
b6abf97d FB |
1631 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
1632 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1633 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1634 | if (is_right) { | |
1e4840bf | 1635 | tcg_gen_shri_tl(t0, t0, data_bits - 1); |
b6abf97d | 1636 | } |
1e4840bf FB |
1637 | tcg_gen_andi_tl(t0, t0, CC_C); |
1638 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
b6abf97d FB |
1639 | |
1640 | tcg_gen_discard_tl(cpu_cc_dst); | |
1641 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); | |
1642 | ||
1643 | gen_set_label(label2); | |
1644 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1e4840bf FB |
1645 | |
1646 | tcg_temp_free(t0); | |
1647 | tcg_temp_free(t1); | |
1648 | tcg_temp_free(t2); | |
1649 | tcg_temp_free(a0); | |
b6abf97d FB |
1650 | } |
1651 | ||
8cd6345d | 1652 | static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, |
1653 | int is_right) | |
1654 | { | |
1655 | int mask; | |
1656 | int data_bits; | |
1657 | TCGv t0, t1, a0; | |
1658 | ||
1659 | /* XXX: inefficient, but we must use local temps */ | |
1660 | t0 = tcg_temp_local_new(); | |
1661 | t1 = tcg_temp_local_new(); | |
1662 | a0 = tcg_temp_local_new(); | |
1663 | ||
1664 | if (ot == OT_QUAD) | |
1665 | mask = 0x3f; | |
1666 | else | |
1667 | mask = 0x1f; | |
1668 | ||
1669 | /* load */ | |
1670 | if (op1 == OR_TMP0) { | |
1671 | tcg_gen_mov_tl(a0, cpu_A0); | |
1672 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1673 | } else { | |
1674 | gen_op_mov_v_reg(ot, t0, op1); | |
1675 | } | |
1676 | ||
1677 | gen_extu(ot, t0); | |
1678 | tcg_gen_mov_tl(t1, t0); | |
1679 | ||
1680 | op2 &= mask; | |
1681 | data_bits = 8 << ot; | |
1682 | if (op2 != 0) { | |
1683 | int shift = op2 & ((1 << (3 + ot)) - 1); | |
1684 | if (is_right) { | |
1685 | tcg_gen_shri_tl(cpu_tmp4, t0, shift); | |
1686 | tcg_gen_shli_tl(t0, t0, data_bits - shift); | |
1687 | } | |
1688 | else { | |
1689 | tcg_gen_shli_tl(cpu_tmp4, t0, shift); | |
1690 | tcg_gen_shri_tl(t0, t0, data_bits - shift); | |
1691 | } | |
1692 | tcg_gen_or_tl(t0, t0, cpu_tmp4); | |
1693 | } | |
1694 | ||
1695 | /* store */ | |
1696 | if (op1 == OR_TMP0) { | |
1697 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1698 | } else { | |
1699 | gen_op_mov_reg_v(ot, op1, t0); | |
1700 | } | |
1701 | ||
1702 | if (op2 != 0) { | |
1703 | /* update eflags */ | |
1704 | if (s->cc_op != CC_OP_DYNAMIC) | |
1705 | gen_op_set_cc_op(s->cc_op); | |
1706 | ||
1707 | gen_compute_eflags(cpu_cc_src); | |
1708 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); | |
1709 | tcg_gen_xor_tl(cpu_tmp0, t1, t0); | |
1710 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); | |
1711 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1712 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1713 | if (is_right) { | |
1714 | tcg_gen_shri_tl(t0, t0, data_bits - 1); | |
1715 | } | |
1716 | tcg_gen_andi_tl(t0, t0, CC_C); | |
1717 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
1718 | ||
1719 | tcg_gen_discard_tl(cpu_cc_dst); | |
1720 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); | |
1721 | s->cc_op = CC_OP_EFLAGS; | |
1722 | } | |
1723 | ||
1724 | tcg_temp_free(t0); | |
1725 | tcg_temp_free(t1); | |
1726 | tcg_temp_free(a0); | |
1727 | } | |
1728 | ||
b6abf97d FB |
1729 | /* XXX: add faster immediate = 1 case */ |
1730 | static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, | |
1731 | int is_right) | |
1732 | { | |
1733 | int label1; | |
1734 | ||
1735 | if (s->cc_op != CC_OP_DYNAMIC) | |
1736 | gen_op_set_cc_op(s->cc_op); | |
1737 | ||
1738 | /* load */ | |
1739 | if (op1 == OR_TMP0) | |
1740 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1741 | else | |
1742 | gen_op_mov_TN_reg(ot, 0, op1); | |
1743 | ||
a7812ae4 PB |
1744 | if (is_right) { |
1745 | switch (ot) { | |
1746 | case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1747 | case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1748 | case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1749 | #ifdef TARGET_X86_64 | |
1750 | case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1751 | #endif | |
1752 | } | |
1753 | } else { | |
1754 | switch (ot) { | |
1755 | case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1756 | case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1757 | case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1758 | #ifdef TARGET_X86_64 | |
1759 | case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1760 | #endif | |
1761 | } | |
1762 | } | |
b6abf97d FB |
1763 | /* store */ |
1764 | if (op1 == OR_TMP0) | |
1765 | gen_op_st_T0_A0(ot + s->mem_index); | |
1766 | else | |
1767 | gen_op_mov_reg_T0(ot, op1); | |
1768 | ||
1769 | /* update eflags */ | |
1770 | label1 = gen_new_label(); | |
1e4840bf | 1771 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1); |
b6abf97d | 1772 | |
1e4840bf | 1773 | tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp); |
b6abf97d FB |
1774 | tcg_gen_discard_tl(cpu_cc_dst); |
1775 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); | |
1776 | ||
1777 | gen_set_label(label1); | |
1778 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1779 | } | |
1780 | ||
1781 | /* XXX: add faster immediate case */ | |
1782 | static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, | |
1783 | int is_right) | |
1784 | { | |
1785 | int label1, label2, data_bits; | |
1786 | target_ulong mask; | |
1e4840bf FB |
1787 | TCGv t0, t1, t2, a0; |
1788 | ||
a7812ae4 PB |
1789 | t0 = tcg_temp_local_new(); |
1790 | t1 = tcg_temp_local_new(); | |
1791 | t2 = tcg_temp_local_new(); | |
1792 | a0 = tcg_temp_local_new(); | |
b6abf97d FB |
1793 | |
1794 | if (ot == OT_QUAD) | |
1795 | mask = 0x3f; | |
1796 | else | |
1797 | mask = 0x1f; | |
1798 | ||
1799 | /* load */ | |
1e4840bf FB |
1800 | if (op1 == OR_TMP0) { |
1801 | tcg_gen_mov_tl(a0, cpu_A0); | |
1802 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1803 | } else { | |
1804 | gen_op_mov_v_reg(ot, t0, op1); | |
1805 | } | |
b6abf97d FB |
1806 | |
1807 | tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); | |
1e4840bf FB |
1808 | |
1809 | tcg_gen_mov_tl(t1, cpu_T[1]); | |
1810 | tcg_gen_mov_tl(t2, cpu_T3); | |
1811 | ||
b6abf97d FB |
1812 | /* Must test zero case to avoid using undefined behaviour in TCG |
1813 | shifts. */ | |
1814 | label1 = gen_new_label(); | |
1e4840bf | 1815 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); |
b6abf97d | 1816 | |
1e4840bf | 1817 | tcg_gen_addi_tl(cpu_tmp5, t2, -1); |
b6abf97d FB |
1818 | if (ot == OT_WORD) { |
1819 | /* Note: we implement the Intel behaviour for shift count > 16 */ | |
1820 | if (is_right) { | |
1e4840bf FB |
1821 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1822 | tcg_gen_shli_tl(cpu_tmp0, t1, 16); | |
1823 | tcg_gen_or_tl(t0, t0, cpu_tmp0); | |
1824 | tcg_gen_ext32u_tl(t0, t0); | |
b6abf97d | 1825 | |
1e4840bf | 1826 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d FB |
1827 | |
1828 | /* only needed if count > 16, but a test would complicate */ | |
5b207c00 | 1829 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf | 1830 | tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5); |
b6abf97d | 1831 | |
1e4840bf | 1832 | tcg_gen_shr_tl(t0, t0, t2); |
b6abf97d | 1833 | |
1e4840bf | 1834 | tcg_gen_or_tl(t0, t0, cpu_tmp0); |
b6abf97d FB |
1835 | } else { |
1836 | /* XXX: not optimal */ | |
1e4840bf FB |
1837 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1838 | tcg_gen_shli_tl(t1, t1, 16); | |
1839 | tcg_gen_or_tl(t1, t1, t0); | |
1840 | tcg_gen_ext32u_tl(t1, t1); | |
b6abf97d | 1841 | |
1e4840bf | 1842 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
5b207c00 | 1843 | tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5); |
bedda79c AJ |
1844 | tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0); |
1845 | tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5); | |
b6abf97d | 1846 | |
1e4840bf | 1847 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1848 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf FB |
1849 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1850 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1851 | } |
1852 | } else { | |
1853 | data_bits = 8 << ot; | |
1854 | if (is_right) { | |
1855 | if (ot == OT_LONG) | |
1e4840bf | 1856 | tcg_gen_ext32u_tl(t0, t0); |
b6abf97d | 1857 | |
1e4840bf | 1858 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1859 | |
1e4840bf | 1860 | tcg_gen_shr_tl(t0, t0, t2); |
5b207c00 | 1861 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1862 | tcg_gen_shl_tl(t1, t1, cpu_tmp5); |
1863 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1864 | |
1865 | } else { | |
1866 | if (ot == OT_LONG) | |
1e4840bf | 1867 | tcg_gen_ext32u_tl(t1, t1); |
b6abf97d | 1868 | |
1e4840bf | 1869 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1870 | |
1e4840bf | 1871 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1872 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1873 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1874 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1875 | } |
1876 | } | |
1e4840bf | 1877 | tcg_gen_mov_tl(t1, cpu_tmp4); |
b6abf97d FB |
1878 | |
1879 | gen_set_label(label1); | |
1880 | /* store */ | |
1e4840bf FB |
1881 | if (op1 == OR_TMP0) { |
1882 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1883 | } else { | |
1884 | gen_op_mov_reg_v(ot, op1, t0); | |
1885 | } | |
b6abf97d FB |
1886 | |
1887 | /* update eflags */ | |
1888 | if (s->cc_op != CC_OP_DYNAMIC) | |
1889 | gen_op_set_cc_op(s->cc_op); | |
1890 | ||
1891 | label2 = gen_new_label(); | |
1e4840bf | 1892 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2); |
b6abf97d | 1893 | |
1e4840bf FB |
1894 | tcg_gen_mov_tl(cpu_cc_src, t1); |
1895 | tcg_gen_mov_tl(cpu_cc_dst, t0); | |
b6abf97d FB |
1896 | if (is_right) { |
1897 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); | |
1898 | } else { | |
1899 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); | |
1900 | } | |
1901 | gen_set_label(label2); | |
1902 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1e4840bf FB |
1903 | |
1904 | tcg_temp_free(t0); | |
1905 | tcg_temp_free(t1); | |
1906 | tcg_temp_free(t2); | |
1907 | tcg_temp_free(a0); | |
b6abf97d FB |
1908 | } |
1909 | ||
1910 | static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) | |
1911 | { | |
1912 | if (s != OR_TMP1) | |
1913 | gen_op_mov_TN_reg(ot, 1, s); | |
1914 | switch(op) { | |
1915 | case OP_ROL: | |
1916 | gen_rot_rm_T1(s1, ot, d, 0); | |
1917 | break; | |
1918 | case OP_ROR: | |
1919 | gen_rot_rm_T1(s1, ot, d, 1); | |
1920 | break; | |
1921 | case OP_SHL: | |
1922 | case OP_SHL1: | |
1923 | gen_shift_rm_T1(s1, ot, d, 0, 0); | |
1924 | break; | |
1925 | case OP_SHR: | |
1926 | gen_shift_rm_T1(s1, ot, d, 1, 0); | |
1927 | break; | |
1928 | case OP_SAR: | |
1929 | gen_shift_rm_T1(s1, ot, d, 1, 1); | |
1930 | break; | |
1931 | case OP_RCL: | |
1932 | gen_rotc_rm_T1(s1, ot, d, 0); | |
1933 | break; | |
1934 | case OP_RCR: | |
1935 | gen_rotc_rm_T1(s1, ot, d, 1); | |
1936 | break; | |
1937 | } | |
2c0262af FB |
1938 | } |
1939 | ||
1940 | static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) | |
1941 | { | |
c1c37968 | 1942 | switch(op) { |
8cd6345d | 1943 | case OP_ROL: |
1944 | gen_rot_rm_im(s1, ot, d, c, 0); | |
1945 | break; | |
1946 | case OP_ROR: | |
1947 | gen_rot_rm_im(s1, ot, d, c, 1); | |
1948 | break; | |
c1c37968 FB |
1949 | case OP_SHL: |
1950 | case OP_SHL1: | |
1951 | gen_shift_rm_im(s1, ot, d, c, 0, 0); | |
1952 | break; | |
1953 | case OP_SHR: | |
1954 | gen_shift_rm_im(s1, ot, d, c, 1, 0); | |
1955 | break; | |
1956 | case OP_SAR: | |
1957 | gen_shift_rm_im(s1, ot, d, c, 1, 1); | |
1958 | break; | |
1959 | default: | |
1960 | /* currently not optimized */ | |
1961 | gen_op_movl_T1_im(c); | |
1962 | gen_shift(s1, op, ot, d, OR_TMP1); | |
1963 | break; | |
1964 | } | |
2c0262af FB |
1965 | } |
1966 | ||
1967 | static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr) | |
1968 | { | |
14ce26e7 | 1969 | target_long disp; |
2c0262af | 1970 | int havesib; |
14ce26e7 | 1971 | int base; |
2c0262af FB |
1972 | int index; |
1973 | int scale; | |
1974 | int opreg; | |
1975 | int mod, rm, code, override, must_add_seg; | |
1976 | ||
1977 | override = s->override; | |
1978 | must_add_seg = s->addseg; | |
1979 | if (override >= 0) | |
1980 | must_add_seg = 1; | |
1981 | mod = (modrm >> 6) & 3; | |
1982 | rm = modrm & 7; | |
1983 | ||
1984 | if (s->aflag) { | |
1985 | ||
1986 | havesib = 0; | |
1987 | base = rm; | |
1988 | index = 0; | |
1989 | scale = 0; | |
3b46e624 | 1990 | |
2c0262af FB |
1991 | if (base == 4) { |
1992 | havesib = 1; | |
61382a50 | 1993 | code = ldub_code(s->pc++); |
2c0262af | 1994 | scale = (code >> 6) & 3; |
14ce26e7 FB |
1995 | index = ((code >> 3) & 7) | REX_X(s); |
1996 | base = (code & 7); | |
2c0262af | 1997 | } |
14ce26e7 | 1998 | base |= REX_B(s); |
2c0262af FB |
1999 | |
2000 | switch (mod) { | |
2001 | case 0: | |
14ce26e7 | 2002 | if ((base & 7) == 5) { |
2c0262af | 2003 | base = -1; |
14ce26e7 | 2004 | disp = (int32_t)ldl_code(s->pc); |
2c0262af | 2005 | s->pc += 4; |
14ce26e7 FB |
2006 | if (CODE64(s) && !havesib) { |
2007 | disp += s->pc + s->rip_offset; | |
2008 | } | |
2c0262af FB |
2009 | } else { |
2010 | disp = 0; | |
2011 | } | |
2012 | break; | |
2013 | case 1: | |
61382a50 | 2014 | disp = (int8_t)ldub_code(s->pc++); |
2c0262af FB |
2015 | break; |
2016 | default: | |
2017 | case 2: | |
61382a50 | 2018 | disp = ldl_code(s->pc); |
2c0262af FB |
2019 | s->pc += 4; |
2020 | break; | |
2021 | } | |
3b46e624 | 2022 | |
2c0262af FB |
2023 | if (base >= 0) { |
2024 | /* for correct popl handling with esp */ | |
2025 | if (base == 4 && s->popl_esp_hack) | |
2026 | disp += s->popl_esp_hack; | |
14ce26e7 FB |
2027 | #ifdef TARGET_X86_64 |
2028 | if (s->aflag == 2) { | |
57fec1fe | 2029 | gen_op_movq_A0_reg(base); |
14ce26e7 | 2030 | if (disp != 0) { |
57fec1fe | 2031 | gen_op_addq_A0_im(disp); |
14ce26e7 | 2032 | } |
5fafdf24 | 2033 | } else |
14ce26e7 FB |
2034 | #endif |
2035 | { | |
57fec1fe | 2036 | gen_op_movl_A0_reg(base); |
14ce26e7 FB |
2037 | if (disp != 0) |
2038 | gen_op_addl_A0_im(disp); | |
2039 | } | |
2c0262af | 2040 | } else { |
14ce26e7 FB |
2041 | #ifdef TARGET_X86_64 |
2042 | if (s->aflag == 2) { | |
57fec1fe | 2043 | gen_op_movq_A0_im(disp); |
5fafdf24 | 2044 | } else |
14ce26e7 FB |
2045 | #endif |
2046 | { | |
2047 | gen_op_movl_A0_im(disp); | |
2048 | } | |
2c0262af FB |
2049 | } |
2050 | /* XXX: index == 4 is always invalid */ | |
2051 | if (havesib && (index != 4 || scale != 0)) { | |
14ce26e7 FB |
2052 | #ifdef TARGET_X86_64 |
2053 | if (s->aflag == 2) { | |
57fec1fe | 2054 | gen_op_addq_A0_reg_sN(scale, index); |
5fafdf24 | 2055 | } else |
14ce26e7 FB |
2056 | #endif |
2057 | { | |
57fec1fe | 2058 | gen_op_addl_A0_reg_sN(scale, index); |
14ce26e7 | 2059 | } |
2c0262af FB |
2060 | } |
2061 | if (must_add_seg) { | |
2062 | if (override < 0) { | |
2063 | if (base == R_EBP || base == R_ESP) | |
2064 | override = R_SS; | |
2065 | else | |
2066 | override = R_DS; | |
2067 | } | |
14ce26e7 FB |
2068 | #ifdef TARGET_X86_64 |
2069 | if (s->aflag == 2) { | |
57fec1fe | 2070 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2071 | } else |
14ce26e7 FB |
2072 | #endif |
2073 | { | |
57fec1fe | 2074 | gen_op_addl_A0_seg(override); |
14ce26e7 | 2075 | } |
2c0262af FB |
2076 | } |
2077 | } else { | |
2078 | switch (mod) { | |
2079 | case 0: | |
2080 | if (rm == 6) { | |
61382a50 | 2081 | disp = lduw_code(s->pc); |
2c0262af FB |
2082 | s->pc += 2; |
2083 | gen_op_movl_A0_im(disp); | |
2084 | rm = 0; /* avoid SS override */ | |
2085 | goto no_rm; | |
2086 | } else { | |
2087 | disp = 0; | |
2088 | } | |
2089 | break; | |
2090 | case 1: | |
61382a50 | 2091 | disp = (int8_t)ldub_code(s->pc++); |
2c0262af FB |
2092 | break; |
2093 | default: | |
2094 | case 2: | |
61382a50 | 2095 | disp = lduw_code(s->pc); |
2c0262af FB |
2096 | s->pc += 2; |
2097 | break; | |
2098 | } | |
2099 | switch(rm) { | |
2100 | case 0: | |
57fec1fe FB |
2101 | gen_op_movl_A0_reg(R_EBX); |
2102 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2103 | break; |
2104 | case 1: | |
57fec1fe FB |
2105 | gen_op_movl_A0_reg(R_EBX); |
2106 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2107 | break; |
2108 | case 2: | |
57fec1fe FB |
2109 | gen_op_movl_A0_reg(R_EBP); |
2110 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2111 | break; |
2112 | case 3: | |
57fec1fe FB |
2113 | gen_op_movl_A0_reg(R_EBP); |
2114 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2115 | break; |
2116 | case 4: | |
57fec1fe | 2117 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
2118 | break; |
2119 | case 5: | |
57fec1fe | 2120 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
2121 | break; |
2122 | case 6: | |
57fec1fe | 2123 | gen_op_movl_A0_reg(R_EBP); |
2c0262af FB |
2124 | break; |
2125 | default: | |
2126 | case 7: | |
57fec1fe | 2127 | gen_op_movl_A0_reg(R_EBX); |
2c0262af FB |
2128 | break; |
2129 | } | |
2130 | if (disp != 0) | |
2131 | gen_op_addl_A0_im(disp); | |
2132 | gen_op_andl_A0_ffff(); | |
2133 | no_rm: | |
2134 | if (must_add_seg) { | |
2135 | if (override < 0) { | |
2136 | if (rm == 2 || rm == 3 || rm == 6) | |
2137 | override = R_SS; | |
2138 | else | |
2139 | override = R_DS; | |
2140 | } | |
57fec1fe | 2141 | gen_op_addl_A0_seg(override); |
2c0262af FB |
2142 | } |
2143 | } | |
2144 | ||
2145 | opreg = OR_A0; | |
2146 | disp = 0; | |
2147 | *reg_ptr = opreg; | |
2148 | *offset_ptr = disp; | |
2149 | } | |
2150 | ||
e17a36ce FB |
2151 | static void gen_nop_modrm(DisasContext *s, int modrm) |
2152 | { | |
2153 | int mod, rm, base, code; | |
2154 | ||
2155 | mod = (modrm >> 6) & 3; | |
2156 | if (mod == 3) | |
2157 | return; | |
2158 | rm = modrm & 7; | |
2159 | ||
2160 | if (s->aflag) { | |
2161 | ||
2162 | base = rm; | |
3b46e624 | 2163 | |
e17a36ce FB |
2164 | if (base == 4) { |
2165 | code = ldub_code(s->pc++); | |
2166 | base = (code & 7); | |
2167 | } | |
3b46e624 | 2168 | |
e17a36ce FB |
2169 | switch (mod) { |
2170 | case 0: | |
2171 | if (base == 5) { | |
2172 | s->pc += 4; | |
2173 | } | |
2174 | break; | |
2175 | case 1: | |
2176 | s->pc++; | |
2177 | break; | |
2178 | default: | |
2179 | case 2: | |
2180 | s->pc += 4; | |
2181 | break; | |
2182 | } | |
2183 | } else { | |
2184 | switch (mod) { | |
2185 | case 0: | |
2186 | if (rm == 6) { | |
2187 | s->pc += 2; | |
2188 | } | |
2189 | break; | |
2190 | case 1: | |
2191 | s->pc++; | |
2192 | break; | |
2193 | default: | |
2194 | case 2: | |
2195 | s->pc += 2; | |
2196 | break; | |
2197 | } | |
2198 | } | |
2199 | } | |
2200 | ||
664e0f19 FB |
2201 | /* used for LEA and MOV AX, mem */ |
2202 | static void gen_add_A0_ds_seg(DisasContext *s) | |
2203 | { | |
2204 | int override, must_add_seg; | |
2205 | must_add_seg = s->addseg; | |
2206 | override = R_DS; | |
2207 | if (s->override >= 0) { | |
2208 | override = s->override; | |
2209 | must_add_seg = 1; | |
2210 | } else { | |
2211 | override = R_DS; | |
2212 | } | |
2213 | if (must_add_seg) { | |
8f091a59 FB |
2214 | #ifdef TARGET_X86_64 |
2215 | if (CODE64(s)) { | |
57fec1fe | 2216 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2217 | } else |
8f091a59 FB |
2218 | #endif |
2219 | { | |
57fec1fe | 2220 | gen_op_addl_A0_seg(override); |
8f091a59 | 2221 | } |
664e0f19 FB |
2222 | } |
2223 | } | |
2224 | ||
222a3336 | 2225 | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == |
2c0262af FB |
2226 | OR_TMP0 */ |
2227 | static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store) | |
2228 | { | |
2229 | int mod, rm, opreg, disp; | |
2230 | ||
2231 | mod = (modrm >> 6) & 3; | |
14ce26e7 | 2232 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
2233 | if (mod == 3) { |
2234 | if (is_store) { | |
2235 | if (reg != OR_TMP0) | |
57fec1fe FB |
2236 | gen_op_mov_TN_reg(ot, 0, reg); |
2237 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 2238 | } else { |
57fec1fe | 2239 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 2240 | if (reg != OR_TMP0) |
57fec1fe | 2241 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2242 | } |
2243 | } else { | |
2244 | gen_lea_modrm(s, modrm, &opreg, &disp); | |
2245 | if (is_store) { | |
2246 | if (reg != OR_TMP0) | |
57fec1fe FB |
2247 | gen_op_mov_TN_reg(ot, 0, reg); |
2248 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 2249 | } else { |
57fec1fe | 2250 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 2251 | if (reg != OR_TMP0) |
57fec1fe | 2252 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2253 | } |
2254 | } | |
2255 | } | |
2256 | ||
2257 | static inline uint32_t insn_get(DisasContext *s, int ot) | |
2258 | { | |
2259 | uint32_t ret; | |
2260 | ||
2261 | switch(ot) { | |
2262 | case OT_BYTE: | |
61382a50 | 2263 | ret = ldub_code(s->pc); |
2c0262af FB |
2264 | s->pc++; |
2265 | break; | |
2266 | case OT_WORD: | |
61382a50 | 2267 | ret = lduw_code(s->pc); |
2c0262af FB |
2268 | s->pc += 2; |
2269 | break; | |
2270 | default: | |
2271 | case OT_LONG: | |
61382a50 | 2272 | ret = ldl_code(s->pc); |
2c0262af FB |
2273 | s->pc += 4; |
2274 | break; | |
2275 | } | |
2276 | return ret; | |
2277 | } | |
2278 | ||
14ce26e7 FB |
2279 | static inline int insn_const_size(unsigned int ot) |
2280 | { | |
2281 | if (ot <= OT_LONG) | |
2282 | return 1 << ot; | |
2283 | else | |
2284 | return 4; | |
2285 | } | |
2286 | ||
6e256c93 FB |
2287 | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2288 | { | |
2289 | TranslationBlock *tb; | |
2290 | target_ulong pc; | |
2291 | ||
2292 | pc = s->cs_base + eip; | |
2293 | tb = s->tb; | |
2294 | /* NOTE: we handle the case where the TB spans two pages here */ | |
2295 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) || | |
2296 | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { | |
2297 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 2298 | tcg_gen_goto_tb(tb_num); |
6e256c93 | 2299 | gen_jmp_im(eip); |
57fec1fe | 2300 | tcg_gen_exit_tb((long)tb + tb_num); |
6e256c93 FB |
2301 | } else { |
2302 | /* jump to another page: currently not optimized */ | |
2303 | gen_jmp_im(eip); | |
2304 | gen_eob(s); | |
2305 | } | |
2306 | } | |
2307 | ||
5fafdf24 | 2308 | static inline void gen_jcc(DisasContext *s, int b, |
14ce26e7 | 2309 | target_ulong val, target_ulong next_eip) |
2c0262af | 2310 | { |
8e1c85e3 | 2311 | int l1, l2, cc_op; |
3b46e624 | 2312 | |
8e1c85e3 FB |
2313 | cc_op = s->cc_op; |
2314 | if (s->cc_op != CC_OP_DYNAMIC) { | |
2315 | gen_op_set_cc_op(s->cc_op); | |
2316 | s->cc_op = CC_OP_DYNAMIC; | |
2317 | } | |
2c0262af | 2318 | if (s->jmp_opt) { |
14ce26e7 | 2319 | l1 = gen_new_label(); |
8e1c85e3 FB |
2320 | gen_jcc1(s, cc_op, b, l1); |
2321 | ||
6e256c93 | 2322 | gen_goto_tb(s, 0, next_eip); |
14ce26e7 FB |
2323 | |
2324 | gen_set_label(l1); | |
6e256c93 | 2325 | gen_goto_tb(s, 1, val); |
2c0262af FB |
2326 | s->is_jmp = 3; |
2327 | } else { | |
14ce26e7 | 2328 | |
14ce26e7 FB |
2329 | l1 = gen_new_label(); |
2330 | l2 = gen_new_label(); | |
8e1c85e3 FB |
2331 | gen_jcc1(s, cc_op, b, l1); |
2332 | ||
14ce26e7 | 2333 | gen_jmp_im(next_eip); |
8e1c85e3 FB |
2334 | tcg_gen_br(l2); |
2335 | ||
14ce26e7 FB |
2336 | gen_set_label(l1); |
2337 | gen_jmp_im(val); | |
2338 | gen_set_label(l2); | |
2c0262af FB |
2339 | gen_eob(s); |
2340 | } | |
2341 | } | |
2342 | ||
2343 | static void gen_setcc(DisasContext *s, int b) | |
2344 | { | |
8e1c85e3 | 2345 | int inv, jcc_op, l1; |
1e4840bf | 2346 | TCGv t0; |
14ce26e7 | 2347 | |
8e1c85e3 FB |
2348 | if (is_fast_jcc_case(s, b)) { |
2349 | /* nominal case: we use a jump */ | |
1e4840bf | 2350 | /* XXX: make it faster by adding new instructions in TCG */ |
a7812ae4 | 2351 | t0 = tcg_temp_local_new(); |
1e4840bf | 2352 | tcg_gen_movi_tl(t0, 0); |
8e1c85e3 FB |
2353 | l1 = gen_new_label(); |
2354 | gen_jcc1(s, s->cc_op, b ^ 1, l1); | |
1e4840bf | 2355 | tcg_gen_movi_tl(t0, 1); |
8e1c85e3 | 2356 | gen_set_label(l1); |
1e4840bf FB |
2357 | tcg_gen_mov_tl(cpu_T[0], t0); |
2358 | tcg_temp_free(t0); | |
8e1c85e3 FB |
2359 | } else { |
2360 | /* slow case: it is more efficient not to generate a jump, | |
2361 | although it is questionnable whether this optimization is | |
2362 | worth to */ | |
2363 | inv = b & 1; | |
2364 | jcc_op = (b >> 1) & 7; | |
1e4840bf | 2365 | gen_setcc_slow_T0(s, jcc_op); |
8e1c85e3 FB |
2366 | if (inv) { |
2367 | tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1); | |
2368 | } | |
2c0262af FB |
2369 | } |
2370 | } | |
2371 | ||
3bd7da9e FB |
2372 | static inline void gen_op_movl_T0_seg(int seg_reg) |
2373 | { | |
2374 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, | |
2375 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2376 | } | |
2377 | ||
2378 | static inline void gen_op_movl_seg_T0_vm(int seg_reg) | |
2379 | { | |
2380 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
2381 | tcg_gen_st32_tl(cpu_T[0], cpu_env, | |
2382 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2383 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); | |
2384 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
2385 | offsetof(CPUX86State,segs[seg_reg].base)); | |
2386 | } | |
2387 | ||
2c0262af FB |
2388 | /* move T0 to seg_reg and compute if the CPU state may change. Never |
2389 | call this function with seg_reg == R_CS */ | |
14ce26e7 | 2390 | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2c0262af | 2391 | { |
3415a4dd FB |
2392 | if (s->pe && !s->vm86) { |
2393 | /* XXX: optimize by finding processor state dynamically */ | |
2394 | if (s->cc_op != CC_OP_DYNAMIC) | |
2395 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2396 | gen_jmp_im(cur_eip); |
b6abf97d | 2397 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 2398 | gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32); |
dc196a57 FB |
2399 | /* abort translation because the addseg value may change or |
2400 | because ss32 may change. For R_SS, translation must always | |
2401 | stop as a special handling must be done to disable hardware | |
2402 | interrupts for the next instruction */ | |
2403 | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) | |
2404 | s->is_jmp = 3; | |
3415a4dd | 2405 | } else { |
3bd7da9e | 2406 | gen_op_movl_seg_T0_vm(seg_reg); |
dc196a57 FB |
2407 | if (seg_reg == R_SS) |
2408 | s->is_jmp = 3; | |
3415a4dd | 2409 | } |
2c0262af FB |
2410 | } |
2411 | ||
0573fbfc TS |
2412 | static inline int svm_is_rep(int prefixes) |
2413 | { | |
2414 | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); | |
2415 | } | |
2416 | ||
872929aa | 2417 | static inline void |
0573fbfc | 2418 | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
b8b6a50b | 2419 | uint32_t type, uint64_t param) |
0573fbfc | 2420 | { |
872929aa FB |
2421 | /* no SVM activated; fast case */ |
2422 | if (likely(!(s->flags & HF_SVMI_MASK))) | |
2423 | return; | |
2424 | if (s->cc_op != CC_OP_DYNAMIC) | |
2425 | gen_op_set_cc_op(s->cc_op); | |
2426 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 PB |
2427 | gen_helper_svm_check_intercept_param(tcg_const_i32(type), |
2428 | tcg_const_i64(param)); | |
0573fbfc TS |
2429 | } |
2430 | ||
872929aa | 2431 | static inline void |
0573fbfc TS |
2432 | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2433 | { | |
872929aa | 2434 | gen_svm_check_intercept_param(s, pc_start, type, 0); |
0573fbfc TS |
2435 | } |
2436 | ||
4f31916f FB |
2437 | static inline void gen_stack_update(DisasContext *s, int addend) |
2438 | { | |
14ce26e7 FB |
2439 | #ifdef TARGET_X86_64 |
2440 | if (CODE64(s)) { | |
6e0d8677 | 2441 | gen_op_add_reg_im(2, R_ESP, addend); |
14ce26e7 FB |
2442 | } else |
2443 | #endif | |
4f31916f | 2444 | if (s->ss32) { |
6e0d8677 | 2445 | gen_op_add_reg_im(1, R_ESP, addend); |
4f31916f | 2446 | } else { |
6e0d8677 | 2447 | gen_op_add_reg_im(0, R_ESP, addend); |
4f31916f FB |
2448 | } |
2449 | } | |
2450 | ||
2c0262af FB |
2451 | /* generate a push. It depends on ss32, addseg and dflag */ |
2452 | static void gen_push_T0(DisasContext *s) | |
2453 | { | |
14ce26e7 FB |
2454 | #ifdef TARGET_X86_64 |
2455 | if (CODE64(s)) { | |
57fec1fe | 2456 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2457 | if (s->dflag) { |
57fec1fe FB |
2458 | gen_op_addq_A0_im(-8); |
2459 | gen_op_st_T0_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2460 | } else { |
57fec1fe FB |
2461 | gen_op_addq_A0_im(-2); |
2462 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2463 | } |
57fec1fe | 2464 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2465 | } else |
14ce26e7 FB |
2466 | #endif |
2467 | { | |
57fec1fe | 2468 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2469 | if (!s->dflag) |
57fec1fe | 2470 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2471 | else |
57fec1fe | 2472 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2473 | if (s->ss32) { |
2474 | if (s->addseg) { | |
bbf662ee | 2475 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
57fec1fe | 2476 | gen_op_addl_A0_seg(R_SS); |
14ce26e7 FB |
2477 | } |
2478 | } else { | |
2479 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2480 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
57fec1fe | 2481 | gen_op_addl_A0_seg(R_SS); |
2c0262af | 2482 | } |
57fec1fe | 2483 | gen_op_st_T0_A0(s->dflag + 1 + s->mem_index); |
14ce26e7 | 2484 | if (s->ss32 && !s->addseg) |
57fec1fe | 2485 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 | 2486 | else |
57fec1fe | 2487 | gen_op_mov_reg_T1(s->ss32 + 1, R_ESP); |
2c0262af FB |
2488 | } |
2489 | } | |
2490 | ||
4f31916f FB |
2491 | /* generate a push. It depends on ss32, addseg and dflag */ |
2492 | /* slower version for T1, only used for call Ev */ | |
2493 | static void gen_push_T1(DisasContext *s) | |
2c0262af | 2494 | { |
14ce26e7 FB |
2495 | #ifdef TARGET_X86_64 |
2496 | if (CODE64(s)) { | |
57fec1fe | 2497 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2498 | if (s->dflag) { |
57fec1fe FB |
2499 | gen_op_addq_A0_im(-8); |
2500 | gen_op_st_T1_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2501 | } else { |
57fec1fe FB |
2502 | gen_op_addq_A0_im(-2); |
2503 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2504 | } |
57fec1fe | 2505 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2506 | } else |
14ce26e7 FB |
2507 | #endif |
2508 | { | |
57fec1fe | 2509 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2510 | if (!s->dflag) |
57fec1fe | 2511 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2512 | else |
57fec1fe | 2513 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2514 | if (s->ss32) { |
2515 | if (s->addseg) { | |
57fec1fe | 2516 | gen_op_addl_A0_seg(R_SS); |
14ce26e7 FB |
2517 | } |
2518 | } else { | |
2519 | gen_op_andl_A0_ffff(); | |
57fec1fe | 2520 | gen_op_addl_A0_seg(R_SS); |
2c0262af | 2521 | } |
57fec1fe | 2522 | gen_op_st_T1_A0(s->dflag + 1 + s->mem_index); |
3b46e624 | 2523 | |
14ce26e7 | 2524 | if (s->ss32 && !s->addseg) |
57fec1fe | 2525 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 FB |
2526 | else |
2527 | gen_stack_update(s, (-2) << s->dflag); | |
2c0262af FB |
2528 | } |
2529 | } | |
2530 | ||
4f31916f FB |
2531 | /* two step pop is necessary for precise exceptions */ |
2532 | static void gen_pop_T0(DisasContext *s) | |
2c0262af | 2533 | { |
14ce26e7 FB |
2534 | #ifdef TARGET_X86_64 |
2535 | if (CODE64(s)) { | |
57fec1fe FB |
2536 | gen_op_movq_A0_reg(R_ESP); |
2537 | gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index); | |
5fafdf24 | 2538 | } else |
14ce26e7 FB |
2539 | #endif |
2540 | { | |
57fec1fe | 2541 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 FB |
2542 | if (s->ss32) { |
2543 | if (s->addseg) | |
57fec1fe | 2544 | gen_op_addl_A0_seg(R_SS); |
14ce26e7 FB |
2545 | } else { |
2546 | gen_op_andl_A0_ffff(); | |
57fec1fe | 2547 | gen_op_addl_A0_seg(R_SS); |
14ce26e7 | 2548 | } |
57fec1fe | 2549 | gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index); |
2c0262af FB |
2550 | } |
2551 | } | |
2552 | ||
2553 | static void gen_pop_update(DisasContext *s) | |
2554 | { | |
14ce26e7 | 2555 | #ifdef TARGET_X86_64 |
8f091a59 | 2556 | if (CODE64(s) && s->dflag) { |
14ce26e7 FB |
2557 | gen_stack_update(s, 8); |
2558 | } else | |
2559 | #endif | |
2560 | { | |
2561 | gen_stack_update(s, 2 << s->dflag); | |
2562 | } | |
2c0262af FB |
2563 | } |
2564 | ||
2565 | static void gen_stack_A0(DisasContext *s) | |
2566 | { | |
57fec1fe | 2567 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2568 | if (!s->ss32) |
2569 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2570 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2571 | if (s->addseg) |
57fec1fe | 2572 | gen_op_addl_A0_seg(R_SS); |
2c0262af FB |
2573 | } |
2574 | ||
2575 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2576 | static void gen_pusha(DisasContext *s) | |
2577 | { | |
2578 | int i; | |
57fec1fe | 2579 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2580 | gen_op_addl_A0_im(-16 << s->dflag); |
2581 | if (!s->ss32) | |
2582 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2583 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2584 | if (s->addseg) |
57fec1fe | 2585 | gen_op_addl_A0_seg(R_SS); |
2c0262af | 2586 | for(i = 0;i < 8; i++) { |
57fec1fe FB |
2587 | gen_op_mov_TN_reg(OT_LONG, 0, 7 - i); |
2588 | gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index); | |
2c0262af FB |
2589 | gen_op_addl_A0_im(2 << s->dflag); |
2590 | } | |
57fec1fe | 2591 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2592 | } |
2593 | ||
2594 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2595 | static void gen_popa(DisasContext *s) | |
2596 | { | |
2597 | int i; | |
57fec1fe | 2598 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2599 | if (!s->ss32) |
2600 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
2601 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2602 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); | |
2c0262af | 2603 | if (s->addseg) |
57fec1fe | 2604 | gen_op_addl_A0_seg(R_SS); |
2c0262af FB |
2605 | for(i = 0;i < 8; i++) { |
2606 | /* ESP is not reloaded */ | |
2607 | if (i != 3) { | |
57fec1fe FB |
2608 | gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2609 | gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i); | |
2c0262af FB |
2610 | } |
2611 | gen_op_addl_A0_im(2 << s->dflag); | |
2612 | } | |
57fec1fe | 2613 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2614 | } |
2615 | ||
2c0262af FB |
2616 | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2617 | { | |
61a8c4ec | 2618 | int ot, opsize; |
2c0262af | 2619 | |
2c0262af | 2620 | level &= 0x1f; |
8f091a59 FB |
2621 | #ifdef TARGET_X86_64 |
2622 | if (CODE64(s)) { | |
2623 | ot = s->dflag ? OT_QUAD : OT_WORD; | |
2624 | opsize = 1 << ot; | |
3b46e624 | 2625 | |
57fec1fe | 2626 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 | 2627 | gen_op_addq_A0_im(-opsize); |
bbf662ee | 2628 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 FB |
2629 | |
2630 | /* push bp */ | |
57fec1fe FB |
2631 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2632 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2633 | if (level) { |
b5b38f61 | 2634 | /* XXX: must save state */ |
a7812ae4 PB |
2635 | gen_helper_enter64_level(tcg_const_i32(level), |
2636 | tcg_const_i32((ot == OT_QUAD)), | |
2637 | cpu_T[1]); | |
8f091a59 | 2638 | } |
57fec1fe | 2639 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2640 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2641 | gen_op_mov_reg_T1(OT_QUAD, R_ESP); |
5fafdf24 | 2642 | } else |
8f091a59 FB |
2643 | #endif |
2644 | { | |
2645 | ot = s->dflag + OT_WORD; | |
2646 | opsize = 2 << s->dflag; | |
3b46e624 | 2647 | |
57fec1fe | 2648 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 FB |
2649 | gen_op_addl_A0_im(-opsize); |
2650 | if (!s->ss32) | |
2651 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2652 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 | 2653 | if (s->addseg) |
57fec1fe | 2654 | gen_op_addl_A0_seg(R_SS); |
8f091a59 | 2655 | /* push bp */ |
57fec1fe FB |
2656 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2657 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2658 | if (level) { |
b5b38f61 | 2659 | /* XXX: must save state */ |
a7812ae4 PB |
2660 | gen_helper_enter_level(tcg_const_i32(level), |
2661 | tcg_const_i32(s->dflag), | |
2662 | cpu_T[1]); | |
8f091a59 | 2663 | } |
57fec1fe | 2664 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2665 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2666 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af | 2667 | } |
2c0262af FB |
2668 | } |
2669 | ||
14ce26e7 | 2670 | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2c0262af FB |
2671 | { |
2672 | if (s->cc_op != CC_OP_DYNAMIC) | |
2673 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2674 | gen_jmp_im(cur_eip); |
a7812ae4 | 2675 | gen_helper_raise_exception(tcg_const_i32(trapno)); |
2c0262af FB |
2676 | s->is_jmp = 3; |
2677 | } | |
2678 | ||
2679 | /* an interrupt is different from an exception because of the | |
7f75ffd3 | 2680 | privilege checks */ |
5fafdf24 | 2681 | static void gen_interrupt(DisasContext *s, int intno, |
14ce26e7 | 2682 | target_ulong cur_eip, target_ulong next_eip) |
2c0262af FB |
2683 | { |
2684 | if (s->cc_op != CC_OP_DYNAMIC) | |
2685 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2686 | gen_jmp_im(cur_eip); |
a7812ae4 PB |
2687 | gen_helper_raise_interrupt(tcg_const_i32(intno), |
2688 | tcg_const_i32(next_eip - cur_eip)); | |
2c0262af FB |
2689 | s->is_jmp = 3; |
2690 | } | |
2691 | ||
14ce26e7 | 2692 | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2c0262af FB |
2693 | { |
2694 | if (s->cc_op != CC_OP_DYNAMIC) | |
2695 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2696 | gen_jmp_im(cur_eip); |
a7812ae4 | 2697 | gen_helper_debug(); |
2c0262af FB |
2698 | s->is_jmp = 3; |
2699 | } | |
2700 | ||
2701 | /* generate a generic end of block. Trace exception is also generated | |
2702 | if needed */ | |
2703 | static void gen_eob(DisasContext *s) | |
2704 | { | |
2705 | if (s->cc_op != CC_OP_DYNAMIC) | |
2706 | gen_op_set_cc_op(s->cc_op); | |
a2cc3b24 | 2707 | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { |
a7812ae4 | 2708 | gen_helper_reset_inhibit_irq(); |
a2cc3b24 | 2709 | } |
a2397807 JK |
2710 | if (s->tb->flags & HF_RF_MASK) { |
2711 | gen_helper_reset_rf(); | |
2712 | } | |
34865134 | 2713 | if (s->singlestep_enabled) { |
a7812ae4 | 2714 | gen_helper_debug(); |
34865134 | 2715 | } else if (s->tf) { |
a7812ae4 | 2716 | gen_helper_single_step(); |
2c0262af | 2717 | } else { |
57fec1fe | 2718 | tcg_gen_exit_tb(0); |
2c0262af FB |
2719 | } |
2720 | s->is_jmp = 3; | |
2721 | } | |
2722 | ||
2723 | /* generate a jump to eip. No segment change must happen before as a | |
2724 | direct call to the next block may occur */ | |
14ce26e7 | 2725 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2c0262af | 2726 | { |
2c0262af | 2727 | if (s->jmp_opt) { |
6e256c93 | 2728 | if (s->cc_op != CC_OP_DYNAMIC) { |
2c0262af | 2729 | gen_op_set_cc_op(s->cc_op); |
6e256c93 FB |
2730 | s->cc_op = CC_OP_DYNAMIC; |
2731 | } | |
2732 | gen_goto_tb(s, tb_num, eip); | |
2c0262af FB |
2733 | s->is_jmp = 3; |
2734 | } else { | |
14ce26e7 | 2735 | gen_jmp_im(eip); |
2c0262af FB |
2736 | gen_eob(s); |
2737 | } | |
2738 | } | |
2739 | ||
14ce26e7 FB |
2740 | static void gen_jmp(DisasContext *s, target_ulong eip) |
2741 | { | |
2742 | gen_jmp_tb(s, eip, 0); | |
2743 | } | |
2744 | ||
8686c490 FB |
2745 | static inline void gen_ldq_env_A0(int idx, int offset) |
2746 | { | |
2747 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2748 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2749 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); | |
8686c490 | 2750 | } |
664e0f19 | 2751 | |
8686c490 FB |
2752 | static inline void gen_stq_env_A0(int idx, int offset) |
2753 | { | |
2754 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2755 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
2756 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2757 | } |
664e0f19 | 2758 | |
8686c490 FB |
2759 | static inline void gen_ldo_env_A0(int idx, int offset) |
2760 | { | |
2761 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2762 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2763 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); | |
8686c490 | 2764 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2765 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2766 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); | |
8686c490 | 2767 | } |
14ce26e7 | 2768 | |
8686c490 FB |
2769 | static inline void gen_sto_env_A0(int idx, int offset) |
2770 | { | |
2771 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2772 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
2773 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2774 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2775 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
2776 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index); | |
8686c490 | 2777 | } |
14ce26e7 | 2778 | |
5af45186 FB |
2779 | static inline void gen_op_movo(int d_offset, int s_offset) |
2780 | { | |
b6abf97d FB |
2781 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2782 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
2783 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8); | |
2784 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8); | |
5af45186 FB |
2785 | } |
2786 | ||
2787 | static inline void gen_op_movq(int d_offset, int s_offset) | |
2788 | { | |
b6abf97d FB |
2789 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2790 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 FB |
2791 | } |
2792 | ||
2793 | static inline void gen_op_movl(int d_offset, int s_offset) | |
2794 | { | |
b6abf97d FB |
2795 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2796 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); | |
5af45186 FB |
2797 | } |
2798 | ||
2799 | static inline void gen_op_movq_env_0(int d_offset) | |
2800 | { | |
b6abf97d FB |
2801 | tcg_gen_movi_i64(cpu_tmp1_i64, 0); |
2802 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 | 2803 | } |
664e0f19 | 2804 | |
5af45186 FB |
2805 | #define SSE_SPECIAL ((void *)1) |
2806 | #define SSE_DUMMY ((void *)2) | |
664e0f19 | 2807 | |
a7812ae4 PB |
2808 | #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } |
2809 | #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ | |
2810 | gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } | |
5af45186 FB |
2811 | |
2812 | static void *sse_op_table1[256][4] = { | |
a35f3ec7 AJ |
2813 | /* 3DNow! extensions */ |
2814 | [0x0e] = { SSE_DUMMY }, /* femms */ | |
2815 | [0x0f] = { SSE_DUMMY }, /* pf... */ | |
664e0f19 FB |
2816 | /* pure SSE operations */ |
2817 | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
2818 | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
465e9838 | 2819 | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
664e0f19 | 2820 | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
a7812ae4 PB |
2821 | [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, |
2822 | [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2823 | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2824 | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ | |
2825 | ||
2826 | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2827 | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2828 | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ | |
2829 | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */ | |
2830 | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ | |
2831 | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ | |
a7812ae4 PB |
2832 | [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, |
2833 | [0x2f] = { gen_helper_comiss, gen_helper_comisd }, | |
664e0f19 FB |
2834 | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2835 | [0x51] = SSE_FOP(sqrt), | |
a7812ae4 PB |
2836 | [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, |
2837 | [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, | |
2838 | [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ | |
2839 | [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ | |
2840 | [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ | |
2841 | [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ | |
664e0f19 FB |
2842 | [0x58] = SSE_FOP(add), |
2843 | [0x59] = SSE_FOP(mul), | |
a7812ae4 PB |
2844 | [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, |
2845 | gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, | |
2846 | [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, | |
664e0f19 FB |
2847 | [0x5c] = SSE_FOP(sub), |
2848 | [0x5d] = SSE_FOP(min), | |
2849 | [0x5e] = SSE_FOP(div), | |
2850 | [0x5f] = SSE_FOP(max), | |
2851 | ||
2852 | [0xc2] = SSE_FOP(cmpeq), | |
a7812ae4 | 2853 | [0xc6] = { gen_helper_shufps, gen_helper_shufpd }, |
664e0f19 | 2854 | |
222a3336 AZ |
2855 | [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */ |
2856 | [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */ | |
4242b1bd | 2857 | |
664e0f19 FB |
2858 | /* MMX ops and their SSE extensions */ |
2859 | [0x60] = MMX_OP2(punpcklbw), | |
2860 | [0x61] = MMX_OP2(punpcklwd), | |
2861 | [0x62] = MMX_OP2(punpckldq), | |
2862 | [0x63] = MMX_OP2(packsswb), | |
2863 | [0x64] = MMX_OP2(pcmpgtb), | |
2864 | [0x65] = MMX_OP2(pcmpgtw), | |
2865 | [0x66] = MMX_OP2(pcmpgtl), | |
2866 | [0x67] = MMX_OP2(packuswb), | |
2867 | [0x68] = MMX_OP2(punpckhbw), | |
2868 | [0x69] = MMX_OP2(punpckhwd), | |
2869 | [0x6a] = MMX_OP2(punpckhdq), | |
2870 | [0x6b] = MMX_OP2(packssdw), | |
a7812ae4 PB |
2871 | [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, |
2872 | [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2873 | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2874 | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ | |
a7812ae4 PB |
2875 | [0x70] = { gen_helper_pshufw_mmx, |
2876 | gen_helper_pshufd_xmm, | |
2877 | gen_helper_pshufhw_xmm, | |
2878 | gen_helper_pshuflw_xmm }, | |
664e0f19 FB |
2879 | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2880 | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ | |
2881 | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ | |
2882 | [0x74] = MMX_OP2(pcmpeqb), | |
2883 | [0x75] = MMX_OP2(pcmpeqw), | |
2884 | [0x76] = MMX_OP2(pcmpeql), | |
a35f3ec7 | 2885 | [0x77] = { SSE_DUMMY }, /* emms */ |
a7812ae4 PB |
2886 | [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, |
2887 | [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, | |
664e0f19 FB |
2888 | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2889 | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ | |
2890 | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ | |
2891 | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ | |
a7812ae4 | 2892 | [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, |
664e0f19 FB |
2893 | [0xd1] = MMX_OP2(psrlw), |
2894 | [0xd2] = MMX_OP2(psrld), | |
2895 | [0xd3] = MMX_OP2(psrlq), | |
2896 | [0xd4] = MMX_OP2(paddq), | |
2897 | [0xd5] = MMX_OP2(pmullw), | |
2898 | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2899 | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ | |
2900 | [0xd8] = MMX_OP2(psubusb), | |
2901 | [0xd9] = MMX_OP2(psubusw), | |
2902 | [0xda] = MMX_OP2(pminub), | |
2903 | [0xdb] = MMX_OP2(pand), | |
2904 | [0xdc] = MMX_OP2(paddusb), | |
2905 | [0xdd] = MMX_OP2(paddusw), | |
2906 | [0xde] = MMX_OP2(pmaxub), | |
2907 | [0xdf] = MMX_OP2(pandn), | |
2908 | [0xe0] = MMX_OP2(pavgb), | |
2909 | [0xe1] = MMX_OP2(psraw), | |
2910 | [0xe2] = MMX_OP2(psrad), | |
2911 | [0xe3] = MMX_OP2(pavgw), | |
2912 | [0xe4] = MMX_OP2(pmulhuw), | |
2913 | [0xe5] = MMX_OP2(pmulhw), | |
a7812ae4 | 2914 | [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, |
664e0f19 FB |
2915 | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
2916 | [0xe8] = MMX_OP2(psubsb), | |
2917 | [0xe9] = MMX_OP2(psubsw), | |
2918 | [0xea] = MMX_OP2(pminsw), | |
2919 | [0xeb] = MMX_OP2(por), | |
2920 | [0xec] = MMX_OP2(paddsb), | |
2921 | [0xed] = MMX_OP2(paddsw), | |
2922 | [0xee] = MMX_OP2(pmaxsw), | |
2923 | [0xef] = MMX_OP2(pxor), | |
465e9838 | 2924 | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
664e0f19 FB |
2925 | [0xf1] = MMX_OP2(psllw), |
2926 | [0xf2] = MMX_OP2(pslld), | |
2927 | [0xf3] = MMX_OP2(psllq), | |
2928 | [0xf4] = MMX_OP2(pmuludq), | |
2929 | [0xf5] = MMX_OP2(pmaddwd), | |
2930 | [0xf6] = MMX_OP2(psadbw), | |
2931 | [0xf7] = MMX_OP2(maskmov), | |
2932 | [0xf8] = MMX_OP2(psubb), | |
2933 | [0xf9] = MMX_OP2(psubw), | |
2934 | [0xfa] = MMX_OP2(psubl), | |
2935 | [0xfb] = MMX_OP2(psubq), | |
2936 | [0xfc] = MMX_OP2(paddb), | |
2937 | [0xfd] = MMX_OP2(paddw), | |
2938 | [0xfe] = MMX_OP2(paddl), | |
2939 | }; | |
2940 | ||
5af45186 | 2941 | static void *sse_op_table2[3 * 8][2] = { |
664e0f19 FB |
2942 | [0 + 2] = MMX_OP2(psrlw), |
2943 | [0 + 4] = MMX_OP2(psraw), | |
2944 | [0 + 6] = MMX_OP2(psllw), | |
2945 | [8 + 2] = MMX_OP2(psrld), | |
2946 | [8 + 4] = MMX_OP2(psrad), | |
2947 | [8 + 6] = MMX_OP2(pslld), | |
2948 | [16 + 2] = MMX_OP2(psrlq), | |
a7812ae4 | 2949 | [16 + 3] = { NULL, gen_helper_psrldq_xmm }, |
664e0f19 | 2950 | [16 + 6] = MMX_OP2(psllq), |
a7812ae4 | 2951 | [16 + 7] = { NULL, gen_helper_pslldq_xmm }, |
664e0f19 FB |
2952 | }; |
2953 | ||
5af45186 | 2954 | static void *sse_op_table3[4 * 3] = { |
a7812ae4 PB |
2955 | gen_helper_cvtsi2ss, |
2956 | gen_helper_cvtsi2sd, | |
2957 | X86_64_ONLY(gen_helper_cvtsq2ss), | |
2958 | X86_64_ONLY(gen_helper_cvtsq2sd), | |
2959 | ||
2960 | gen_helper_cvttss2si, | |
2961 | gen_helper_cvttsd2si, | |
2962 | X86_64_ONLY(gen_helper_cvttss2sq), | |
2963 | X86_64_ONLY(gen_helper_cvttsd2sq), | |
2964 | ||
2965 | gen_helper_cvtss2si, | |
2966 | gen_helper_cvtsd2si, | |
2967 | X86_64_ONLY(gen_helper_cvtss2sq), | |
2968 | X86_64_ONLY(gen_helper_cvtsd2sq), | |
664e0f19 | 2969 | }; |
3b46e624 | 2970 | |
5af45186 | 2971 | static void *sse_op_table4[8][4] = { |
664e0f19 FB |
2972 | SSE_FOP(cmpeq), |
2973 | SSE_FOP(cmplt), | |
2974 | SSE_FOP(cmple), | |
2975 | SSE_FOP(cmpunord), | |
2976 | SSE_FOP(cmpneq), | |
2977 | SSE_FOP(cmpnlt), | |
2978 | SSE_FOP(cmpnle), | |
2979 | SSE_FOP(cmpord), | |
2980 | }; | |
3b46e624 | 2981 | |
5af45186 | 2982 | static void *sse_op_table5[256] = { |
a7812ae4 PB |
2983 | [0x0c] = gen_helper_pi2fw, |
2984 | [0x0d] = gen_helper_pi2fd, | |
2985 | [0x1c] = gen_helper_pf2iw, | |
2986 | [0x1d] = gen_helper_pf2id, | |
2987 | [0x8a] = gen_helper_pfnacc, | |
2988 | [0x8e] = gen_helper_pfpnacc, | |
2989 | [0x90] = gen_helper_pfcmpge, | |
2990 | [0x94] = gen_helper_pfmin, | |
2991 | [0x96] = gen_helper_pfrcp, | |
2992 | [0x97] = gen_helper_pfrsqrt, | |
2993 | [0x9a] = gen_helper_pfsub, | |
2994 | [0x9e] = gen_helper_pfadd, | |
2995 | [0xa0] = gen_helper_pfcmpgt, | |
2996 | [0xa4] = gen_helper_pfmax, | |
2997 | [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ | |
2998 | [0xa7] = gen_helper_movq, /* pfrsqit1 */ | |
2999 | [0xaa] = gen_helper_pfsubr, | |
3000 | [0xae] = gen_helper_pfacc, | |
3001 | [0xb0] = gen_helper_pfcmpeq, | |
3002 | [0xb4] = gen_helper_pfmul, | |
3003 | [0xb6] = gen_helper_movq, /* pfrcpit2 */ | |
3004 | [0xb7] = gen_helper_pmulhrw_mmx, | |
3005 | [0xbb] = gen_helper_pswapd, | |
3006 | [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ | |
a35f3ec7 AJ |
3007 | }; |
3008 | ||
222a3336 AZ |
3009 | struct sse_op_helper_s { |
3010 | void *op[2]; uint32_t ext_mask; | |
3011 | }; | |
3012 | #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 } | |
a7812ae4 PB |
3013 | #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } |
3014 | #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } | |
222a3336 AZ |
3015 | #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } |
3016 | static struct sse_op_helper_s sse_op_table6[256] = { | |
3017 | [0x00] = SSSE3_OP(pshufb), | |
3018 | [0x01] = SSSE3_OP(phaddw), | |
3019 | [0x02] = SSSE3_OP(phaddd), | |
3020 | [0x03] = SSSE3_OP(phaddsw), | |
3021 | [0x04] = SSSE3_OP(pmaddubsw), | |
3022 | [0x05] = SSSE3_OP(phsubw), | |
3023 | [0x06] = SSSE3_OP(phsubd), | |
3024 | [0x07] = SSSE3_OP(phsubsw), | |
3025 | [0x08] = SSSE3_OP(psignb), | |
3026 | [0x09] = SSSE3_OP(psignw), | |
3027 | [0x0a] = SSSE3_OP(psignd), | |
3028 | [0x0b] = SSSE3_OP(pmulhrsw), | |
3029 | [0x10] = SSE41_OP(pblendvb), | |
3030 | [0x14] = SSE41_OP(blendvps), | |
3031 | [0x15] = SSE41_OP(blendvpd), | |
3032 | [0x17] = SSE41_OP(ptest), | |
3033 | [0x1c] = SSSE3_OP(pabsb), | |
3034 | [0x1d] = SSSE3_OP(pabsw), | |
3035 | [0x1e] = SSSE3_OP(pabsd), | |
3036 | [0x20] = SSE41_OP(pmovsxbw), | |
3037 | [0x21] = SSE41_OP(pmovsxbd), | |
3038 | [0x22] = SSE41_OP(pmovsxbq), | |
3039 | [0x23] = SSE41_OP(pmovsxwd), | |
3040 | [0x24] = SSE41_OP(pmovsxwq), | |
3041 | [0x25] = SSE41_OP(pmovsxdq), | |
3042 | [0x28] = SSE41_OP(pmuldq), | |
3043 | [0x29] = SSE41_OP(pcmpeqq), | |
3044 | [0x2a] = SSE41_SPECIAL, /* movntqda */ | |
3045 | [0x2b] = SSE41_OP(packusdw), | |
3046 | [0x30] = SSE41_OP(pmovzxbw), | |
3047 | [0x31] = SSE41_OP(pmovzxbd), | |
3048 | [0x32] = SSE41_OP(pmovzxbq), | |
3049 | [0x33] = SSE41_OP(pmovzxwd), | |
3050 | [0x34] = SSE41_OP(pmovzxwq), | |
3051 | [0x35] = SSE41_OP(pmovzxdq), | |
3052 | [0x37] = SSE42_OP(pcmpgtq), | |
3053 | [0x38] = SSE41_OP(pminsb), | |
3054 | [0x39] = SSE41_OP(pminsd), | |
3055 | [0x3a] = SSE41_OP(pminuw), | |
3056 | [0x3b] = SSE41_OP(pminud), | |
3057 | [0x3c] = SSE41_OP(pmaxsb), | |
3058 | [0x3d] = SSE41_OP(pmaxsd), | |
3059 | [0x3e] = SSE41_OP(pmaxuw), | |
3060 | [0x3f] = SSE41_OP(pmaxud), | |
3061 | [0x40] = SSE41_OP(pmulld), | |
3062 | [0x41] = SSE41_OP(phminposuw), | |
4242b1bd AZ |
3063 | }; |
3064 | ||
222a3336 AZ |
3065 | static struct sse_op_helper_s sse_op_table7[256] = { |
3066 | [0x08] = SSE41_OP(roundps), | |
3067 | [0x09] = SSE41_OP(roundpd), | |
3068 | [0x0a] = SSE41_OP(roundss), | |
3069 | [0x0b] = SSE41_OP(roundsd), | |
3070 | [0x0c] = SSE41_OP(blendps), | |
3071 | [0x0d] = SSE41_OP(blendpd), | |
3072 | [0x0e] = SSE41_OP(pblendw), | |
3073 | [0x0f] = SSSE3_OP(palignr), | |
3074 | [0x14] = SSE41_SPECIAL, /* pextrb */ | |
3075 | [0x15] = SSE41_SPECIAL, /* pextrw */ | |
3076 | [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ | |
3077 | [0x17] = SSE41_SPECIAL, /* extractps */ | |
3078 | [0x20] = SSE41_SPECIAL, /* pinsrb */ | |
3079 | [0x21] = SSE41_SPECIAL, /* insertps */ | |
3080 | [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ | |
3081 | [0x40] = SSE41_OP(dpps), | |
3082 | [0x41] = SSE41_OP(dppd), | |
3083 | [0x42] = SSE41_OP(mpsadbw), | |
3084 | [0x60] = SSE42_OP(pcmpestrm), | |
3085 | [0x61] = SSE42_OP(pcmpestri), | |
3086 | [0x62] = SSE42_OP(pcmpistrm), | |
3087 | [0x63] = SSE42_OP(pcmpistri), | |
4242b1bd AZ |
3088 | }; |
3089 | ||
664e0f19 FB |
3090 | static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) |
3091 | { | |
3092 | int b1, op1_offset, op2_offset, is_xmm, val, ot; | |
3093 | int modrm, mod, rm, reg, reg_addr, offset_addr; | |
5af45186 | 3094 | void *sse_op2; |
664e0f19 FB |
3095 | |
3096 | b &= 0xff; | |
5fafdf24 | 3097 | if (s->prefix & PREFIX_DATA) |
664e0f19 | 3098 | b1 = 1; |
5fafdf24 | 3099 | else if (s->prefix & PREFIX_REPZ) |
664e0f19 | 3100 | b1 = 2; |
5fafdf24 | 3101 | else if (s->prefix & PREFIX_REPNZ) |
664e0f19 FB |
3102 | b1 = 3; |
3103 | else | |
3104 | b1 = 0; | |
3105 | sse_op2 = sse_op_table1[b][b1]; | |
5fafdf24 | 3106 | if (!sse_op2) |
664e0f19 | 3107 | goto illegal_op; |
a35f3ec7 | 3108 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
664e0f19 FB |
3109 | is_xmm = 1; |
3110 | } else { | |
3111 | if (b1 == 0) { | |
3112 | /* MMX case */ | |
3113 | is_xmm = 0; | |
3114 | } else { | |
3115 | is_xmm = 1; | |
3116 | } | |
3117 | } | |
3118 | /* simple MMX/SSE operation */ | |
3119 | if (s->flags & HF_TS_MASK) { | |
3120 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
3121 | return; | |
3122 | } | |
3123 | if (s->flags & HF_EM_MASK) { | |
3124 | illegal_op: | |
3125 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
3126 | return; | |
3127 | } | |
3128 | if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) | |
4242b1bd AZ |
3129 | if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) |
3130 | goto illegal_op; | |
e771edab AJ |
3131 | if (b == 0x0e) { |
3132 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) | |
3133 | goto illegal_op; | |
3134 | /* femms */ | |
a7812ae4 | 3135 | gen_helper_emms(); |
e771edab AJ |
3136 | return; |
3137 | } | |
3138 | if (b == 0x77) { | |
3139 | /* emms */ | |
a7812ae4 | 3140 | gen_helper_emms(); |
664e0f19 FB |
3141 | return; |
3142 | } | |
3143 | /* prepare MMX state (XXX: optimize by storing fptt and fptags in | |
3144 | the static cpu state) */ | |
3145 | if (!is_xmm) { | |
a7812ae4 | 3146 | gen_helper_enter_mmx(); |
664e0f19 FB |
3147 | } |
3148 | ||
3149 | modrm = ldub_code(s->pc++); | |
3150 | reg = ((modrm >> 3) & 7); | |
3151 | if (is_xmm) | |
3152 | reg |= rex_r; | |
3153 | mod = (modrm >> 6) & 3; | |
3154 | if (sse_op2 == SSE_SPECIAL) { | |
3155 | b |= (b1 << 8); | |
3156 | switch(b) { | |
3157 | case 0x0e7: /* movntq */ | |
5fafdf24 | 3158 | if (mod == 3) |
664e0f19 FB |
3159 | goto illegal_op; |
3160 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3161 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3162 | break; |
3163 | case 0x1e7: /* movntdq */ | |
3164 | case 0x02b: /* movntps */ | |
3165 | case 0x12b: /* movntps */ | |
465e9838 FB |
3166 | case 0x3f0: /* lddqu */ |
3167 | if (mod == 3) | |
664e0f19 FB |
3168 | goto illegal_op; |
3169 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3170 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3171 | break; |
3172 | case 0x6e: /* movd mm, ea */ | |
dabd98dd FB |
3173 | #ifdef TARGET_X86_64 |
3174 | if (s->dflag == 2) { | |
3175 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); | |
5af45186 | 3176 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); |
5fafdf24 | 3177 | } else |
dabd98dd FB |
3178 | #endif |
3179 | { | |
3180 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); | |
5af45186 FB |
3181 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3182 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
a7812ae4 PB |
3183 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3184 | gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); | |
dabd98dd | 3185 | } |
664e0f19 FB |
3186 | break; |
3187 | case 0x16e: /* movd xmm, ea */ | |
dabd98dd FB |
3188 | #ifdef TARGET_X86_64 |
3189 | if (s->dflag == 2) { | |
3190 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); | |
5af45186 FB |
3191 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3192 | offsetof(CPUX86State,xmm_regs[reg])); | |
a7812ae4 | 3193 | gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); |
5fafdf24 | 3194 | } else |
dabd98dd FB |
3195 | #endif |
3196 | { | |
3197 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); | |
5af45186 FB |
3198 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3199 | offsetof(CPUX86State,xmm_regs[reg])); | |
b6abf97d | 3200 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 3201 | gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); |
dabd98dd | 3202 | } |
664e0f19 FB |
3203 | break; |
3204 | case 0x6f: /* movq mm, ea */ | |
3205 | if (mod != 3) { | |
3206 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3207 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3208 | } else { |
3209 | rm = (modrm & 7); | |
b6abf97d | 3210 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3211 | offsetof(CPUX86State,fpregs[rm].mmx)); |
b6abf97d | 3212 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3213 | offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3214 | } |
3215 | break; | |
3216 | case 0x010: /* movups */ | |
3217 | case 0x110: /* movupd */ | |
3218 | case 0x028: /* movaps */ | |
3219 | case 0x128: /* movapd */ | |
3220 | case 0x16f: /* movdqa xmm, ea */ | |
3221 | case 0x26f: /* movdqu xmm, ea */ | |
3222 | if (mod != 3) { | |
3223 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3224 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3225 | } else { |
3226 | rm = (modrm & 7) | REX_B(s); | |
3227 | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), | |
3228 | offsetof(CPUX86State,xmm_regs[rm])); | |
3229 | } | |
3230 | break; | |
3231 | case 0x210: /* movss xmm, ea */ | |
3232 | if (mod != 3) { | |
3233 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 3234 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3235 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
664e0f19 | 3236 | gen_op_movl_T0_0(); |
651ba608 FB |
3237 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); |
3238 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3239 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3240 | } else { |
3241 | rm = (modrm & 7) | REX_B(s); | |
3242 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3243 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3244 | } | |
3245 | break; | |
3246 | case 0x310: /* movsd xmm, ea */ | |
3247 | if (mod != 3) { | |
3248 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3249 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 | 3250 | gen_op_movl_T0_0(); |
651ba608 FB |
3251 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3252 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3253 | } else { |
3254 | rm = (modrm & 7) | REX_B(s); | |
3255 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3256 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3257 | } | |
3258 | break; | |
3259 | case 0x012: /* movlps */ | |
3260 | case 0x112: /* movlpd */ | |
3261 | if (mod != 3) { | |
3262 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3263 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3264 | } else { |
3265 | /* movhlps */ | |
3266 | rm = (modrm & 7) | REX_B(s); | |
3267 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3268 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3269 | } | |
3270 | break; | |
465e9838 FB |
3271 | case 0x212: /* movsldup */ |
3272 | if (mod != 3) { | |
3273 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3274 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
465e9838 FB |
3275 | } else { |
3276 | rm = (modrm & 7) | REX_B(s); | |
3277 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3278 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3279 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3280 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); | |
3281 | } | |
3282 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3283 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3284 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3285 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3286 | break; | |
3287 | case 0x312: /* movddup */ | |
3288 | if (mod != 3) { | |
3289 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3290 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 FB |
3291 | } else { |
3292 | rm = (modrm & 7) | REX_B(s); | |
3293 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3294 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3295 | } | |
3296 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
ba6526df | 3297 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 | 3298 | break; |
664e0f19 FB |
3299 | case 0x016: /* movhps */ |
3300 | case 0x116: /* movhpd */ | |
3301 | if (mod != 3) { | |
3302 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3303 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3304 | } else { |
3305 | /* movlhps */ | |
3306 | rm = (modrm & 7) | REX_B(s); | |
3307 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
3308 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3309 | } | |
3310 | break; | |
3311 | case 0x216: /* movshdup */ | |
3312 | if (mod != 3) { | |
3313 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3314 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3315 | } else { |
3316 | rm = (modrm & 7) | REX_B(s); | |
3317 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3318 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); | |
3319 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3320 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); | |
3321 | } | |
3322 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3323 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); | |
3324 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3325 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
3326 | break; | |
3327 | case 0x7e: /* movd ea, mm */ | |
dabd98dd FB |
3328 | #ifdef TARGET_X86_64 |
3329 | if (s->dflag == 2) { | |
5af45186 FB |
3330 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3331 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
dabd98dd | 3332 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3333 | } else |
dabd98dd FB |
3334 | #endif |
3335 | { | |
5af45186 FB |
3336 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3337 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); | |
dabd98dd FB |
3338 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); |
3339 | } | |
664e0f19 FB |
3340 | break; |
3341 | case 0x17e: /* movd ea, xmm */ | |
dabd98dd FB |
3342 | #ifdef TARGET_X86_64 |
3343 | if (s->dflag == 2) { | |
5af45186 FB |
3344 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3345 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
dabd98dd | 3346 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3347 | } else |
dabd98dd FB |
3348 | #endif |
3349 | { | |
5af45186 FB |
3350 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3351 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
dabd98dd FB |
3352 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); |
3353 | } | |
664e0f19 FB |
3354 | break; |
3355 | case 0x27e: /* movq xmm, ea */ | |
3356 | if (mod != 3) { | |
3357 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3358 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3359 | } else { |
3360 | rm = (modrm & 7) | REX_B(s); | |
3361 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3362 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3363 | } | |
3364 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
3365 | break; | |
3366 | case 0x7f: /* movq ea, mm */ | |
3367 | if (mod != 3) { | |
3368 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3369 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3370 | } else { |
3371 | rm = (modrm & 7); | |
3372 | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), | |
3373 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
3374 | } | |
3375 | break; | |
3376 | case 0x011: /* movups */ | |
3377 | case 0x111: /* movupd */ | |
3378 | case 0x029: /* movaps */ | |
3379 | case 0x129: /* movapd */ | |
3380 | case 0x17f: /* movdqa ea, xmm */ | |
3381 | case 0x27f: /* movdqu ea, xmm */ | |
3382 | if (mod != 3) { | |
3383 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3384 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3385 | } else { |
3386 | rm = (modrm & 7) | REX_B(s); | |
3387 | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), | |
3388 | offsetof(CPUX86State,xmm_regs[reg])); | |
3389 | } | |
3390 | break; | |
3391 | case 0x211: /* movss ea, xmm */ | |
3392 | if (mod != 3) { | |
3393 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
651ba608 | 3394 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
57fec1fe | 3395 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
664e0f19 FB |
3396 | } else { |
3397 | rm = (modrm & 7) | REX_B(s); | |
3398 | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), | |
3399 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3400 | } | |
3401 | break; | |
3402 | case 0x311: /* movsd ea, xmm */ | |
3403 | if (mod != 3) { | |
3404 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3405 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3406 | } else { |
3407 | rm = (modrm & 7) | REX_B(s); | |
3408 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3409 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3410 | } | |
3411 | break; | |
3412 | case 0x013: /* movlps */ | |
3413 | case 0x113: /* movlpd */ | |
3414 | if (mod != 3) { | |
3415 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3416 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3417 | } else { |
3418 | goto illegal_op; | |
3419 | } | |
3420 | break; | |
3421 | case 0x017: /* movhps */ | |
3422 | case 0x117: /* movhpd */ | |
3423 | if (mod != 3) { | |
3424 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3425 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3426 | } else { |
3427 | goto illegal_op; | |
3428 | } | |
3429 | break; | |
3430 | case 0x71: /* shift mm, im */ | |
3431 | case 0x72: | |
3432 | case 0x73: | |
3433 | case 0x171: /* shift xmm, im */ | |
3434 | case 0x172: | |
3435 | case 0x173: | |
3436 | val = ldub_code(s->pc++); | |
3437 | if (is_xmm) { | |
3438 | gen_op_movl_T0_im(val); | |
651ba608 | 3439 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 | 3440 | gen_op_movl_T0_0(); |
651ba608 | 3441 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); |
664e0f19 FB |
3442 | op1_offset = offsetof(CPUX86State,xmm_t0); |
3443 | } else { | |
3444 | gen_op_movl_T0_im(val); | |
651ba608 | 3445 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); |
664e0f19 | 3446 | gen_op_movl_T0_0(); |
651ba608 | 3447 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); |
664e0f19 FB |
3448 | op1_offset = offsetof(CPUX86State,mmx_t0); |
3449 | } | |
3450 | sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1]; | |
3451 | if (!sse_op2) | |
3452 | goto illegal_op; | |
3453 | if (is_xmm) { | |
3454 | rm = (modrm & 7) | REX_B(s); | |
3455 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3456 | } else { | |
3457 | rm = (modrm & 7); | |
3458 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3459 | } | |
5af45186 FB |
3460 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3461 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); | |
a7812ae4 | 3462 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3463 | break; |
3464 | case 0x050: /* movmskps */ | |
664e0f19 | 3465 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3466 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3467 | offsetof(CPUX86State,xmm_regs[rm])); | |
a7812ae4 | 3468 | gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0); |
b6abf97d | 3469 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3470 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3471 | break; |
3472 | case 0x150: /* movmskpd */ | |
664e0f19 | 3473 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3474 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3475 | offsetof(CPUX86State,xmm_regs[rm])); | |
a7812ae4 | 3476 | gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0); |
b6abf97d | 3477 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3478 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3479 | break; |
3480 | case 0x02a: /* cvtpi2ps */ | |
3481 | case 0x12a: /* cvtpi2pd */ | |
a7812ae4 | 3482 | gen_helper_enter_mmx(); |
664e0f19 FB |
3483 | if (mod != 3) { |
3484 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3485 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
8686c490 | 3486 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3487 | } else { |
3488 | rm = (modrm & 7); | |
3489 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3490 | } | |
3491 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3492 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3493 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3494 | switch(b >> 8) { |
3495 | case 0x0: | |
a7812ae4 | 3496 | gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3497 | break; |
3498 | default: | |
3499 | case 0x1: | |
a7812ae4 | 3500 | gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3501 | break; |
3502 | } | |
3503 | break; | |
3504 | case 0x22a: /* cvtsi2ss */ | |
3505 | case 0x32a: /* cvtsi2sd */ | |
3506 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3507 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
3508 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3509 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3510 | sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)]; | |
28e10711 FB |
3511 | if (ot == OT_LONG) { |
3512 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
a7812ae4 | 3513 | ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32); |
28e10711 | 3514 | } else { |
a7812ae4 | 3515 | ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]); |
28e10711 | 3516 | } |
664e0f19 FB |
3517 | break; |
3518 | case 0x02c: /* cvttps2pi */ | |
3519 | case 0x12c: /* cvttpd2pi */ | |
3520 | case 0x02d: /* cvtps2pi */ | |
3521 | case 0x12d: /* cvtpd2pi */ | |
a7812ae4 | 3522 | gen_helper_enter_mmx(); |
664e0f19 FB |
3523 | if (mod != 3) { |
3524 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3525 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
8686c490 | 3526 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3527 | } else { |
3528 | rm = (modrm & 7) | REX_B(s); | |
3529 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3530 | } | |
3531 | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx); | |
5af45186 FB |
3532 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3533 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3534 | switch(b) { |
3535 | case 0x02c: | |
a7812ae4 | 3536 | gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3537 | break; |
3538 | case 0x12c: | |
a7812ae4 | 3539 | gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3540 | break; |
3541 | case 0x02d: | |
a7812ae4 | 3542 | gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3543 | break; |
3544 | case 0x12d: | |
a7812ae4 | 3545 | gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3546 | break; |
3547 | } | |
3548 | break; | |
3549 | case 0x22c: /* cvttss2si */ | |
3550 | case 0x32c: /* cvttsd2si */ | |
3551 | case 0x22d: /* cvtss2si */ | |
3552 | case 0x32d: /* cvtsd2si */ | |
3553 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
31313213 FB |
3554 | if (mod != 3) { |
3555 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3556 | if ((b >> 8) & 1) { | |
8686c490 | 3557 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))); |
31313213 | 3558 | } else { |
57fec1fe | 3559 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3560 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
31313213 FB |
3561 | } |
3562 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3563 | } else { | |
3564 | rm = (modrm & 7) | REX_B(s); | |
3565 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3566 | } | |
5af45186 FB |
3567 | sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 + |
3568 | (b & 1) * 4]; | |
3569 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); | |
3570 | if (ot == OT_LONG) { | |
a7812ae4 | 3571 | ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0); |
b6abf97d | 3572 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
5af45186 | 3573 | } else { |
a7812ae4 | 3574 | ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0); |
5af45186 | 3575 | } |
57fec1fe | 3576 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3577 | break; |
3578 | case 0xc4: /* pinsrw */ | |
5fafdf24 | 3579 | case 0x1c4: |
d1e42c5c | 3580 | s->rip_offset = 1; |
664e0f19 FB |
3581 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
3582 | val = ldub_code(s->pc++); | |
3583 | if (b1) { | |
3584 | val &= 7; | |
5af45186 FB |
3585 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3586 | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); | |
664e0f19 FB |
3587 | } else { |
3588 | val &= 3; | |
5af45186 FB |
3589 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3590 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); | |
664e0f19 FB |
3591 | } |
3592 | break; | |
3593 | case 0xc5: /* pextrw */ | |
5fafdf24 | 3594 | case 0x1c5: |
664e0f19 FB |
3595 | if (mod != 3) |
3596 | goto illegal_op; | |
6dc2d0da | 3597 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
664e0f19 FB |
3598 | val = ldub_code(s->pc++); |
3599 | if (b1) { | |
3600 | val &= 7; | |
3601 | rm = (modrm & 7) | REX_B(s); | |
5af45186 FB |
3602 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3603 | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); | |
664e0f19 FB |
3604 | } else { |
3605 | val &= 3; | |
3606 | rm = (modrm & 7); | |
5af45186 FB |
3607 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3608 | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); | |
664e0f19 FB |
3609 | } |
3610 | reg = ((modrm >> 3) & 7) | rex_r; | |
6dc2d0da | 3611 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3612 | break; |
3613 | case 0x1d6: /* movq ea, xmm */ | |
3614 | if (mod != 3) { | |
3615 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3616 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3617 | } else { |
3618 | rm = (modrm & 7) | REX_B(s); | |
3619 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3620 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3621 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3622 | } | |
3623 | break; | |
3624 | case 0x2d6: /* movq2dq */ | |
a7812ae4 | 3625 | gen_helper_enter_mmx(); |
480c1cdb FB |
3626 | rm = (modrm & 7); |
3627 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3628 | offsetof(CPUX86State,fpregs[rm].mmx)); | |
3629 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3630 | break; |
3631 | case 0x3d6: /* movdq2q */ | |
a7812ae4 | 3632 | gen_helper_enter_mmx(); |
480c1cdb FB |
3633 | rm = (modrm & 7) | REX_B(s); |
3634 | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), | |
3635 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
664e0f19 FB |
3636 | break; |
3637 | case 0xd7: /* pmovmskb */ | |
3638 | case 0x1d7: | |
3639 | if (mod != 3) | |
3640 | goto illegal_op; | |
3641 | if (b1) { | |
3642 | rm = (modrm & 7) | REX_B(s); | |
5af45186 | 3643 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
a7812ae4 | 3644 | gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0); |
664e0f19 FB |
3645 | } else { |
3646 | rm = (modrm & 7); | |
5af45186 | 3647 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
a7812ae4 | 3648 | gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0); |
664e0f19 | 3649 | } |
b6abf97d | 3650 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
664e0f19 | 3651 | reg = ((modrm >> 3) & 7) | rex_r; |
57fec1fe | 3652 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 | 3653 | break; |
4242b1bd | 3654 | case 0x138: |
000cacf6 AZ |
3655 | if (s->prefix & PREFIX_REPNZ) |
3656 | goto crc32; | |
3657 | case 0x038: | |
4242b1bd AZ |
3658 | b = modrm; |
3659 | modrm = ldub_code(s->pc++); | |
3660 | rm = modrm & 7; | |
3661 | reg = ((modrm >> 3) & 7) | rex_r; | |
3662 | mod = (modrm >> 6) & 3; | |
3663 | ||
222a3336 | 3664 | sse_op2 = sse_op_table6[b].op[b1]; |
4242b1bd AZ |
3665 | if (!sse_op2) |
3666 | goto illegal_op; | |
222a3336 AZ |
3667 | if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask)) |
3668 | goto illegal_op; | |
4242b1bd AZ |
3669 | |
3670 | if (b1) { | |
3671 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3672 | if (mod == 3) { | |
3673 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3674 | } else { | |
3675 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3676 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
222a3336 AZ |
3677 | switch (b) { |
3678 | case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ | |
3679 | case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ | |
3680 | case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ | |
3681 | gen_ldq_env_A0(s->mem_index, op2_offset + | |
3682 | offsetof(XMMReg, XMM_Q(0))); | |
3683 | break; | |
3684 | case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ | |
3685 | case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ | |
a7812ae4 | 3686 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3687 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3688 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3689 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + |
3690 | offsetof(XMMReg, XMM_L(0))); | |
3691 | break; | |
3692 | case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ | |
3693 | tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, | |
3694 | (s->mem_index >> 2) - 1); | |
3695 | tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + | |
3696 | offsetof(XMMReg, XMM_W(0))); | |
3697 | break; | |
3698 | case 0x2a: /* movntqda */ | |
3699 | gen_ldo_env_A0(s->mem_index, op1_offset); | |
3700 | return; | |
3701 | default: | |
3702 | gen_ldo_env_A0(s->mem_index, op2_offset); | |
3703 | } | |
4242b1bd AZ |
3704 | } |
3705 | } else { | |
3706 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3707 | if (mod == 3) { | |
3708 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3709 | } else { | |
3710 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
3711 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3712 | gen_ldq_env_A0(s->mem_index, op2_offset); | |
3713 | } | |
3714 | } | |
222a3336 AZ |
3715 | if (sse_op2 == SSE_SPECIAL) |
3716 | goto illegal_op; | |
3717 | ||
4242b1bd AZ |
3718 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3719 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 3720 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
222a3336 AZ |
3721 | |
3722 | if (b == 0x17) | |
3723 | s->cc_op = CC_OP_EFLAGS; | |
4242b1bd | 3724 | break; |
222a3336 AZ |
3725 | case 0x338: /* crc32 */ |
3726 | crc32: | |
3727 | b = modrm; | |
3728 | modrm = ldub_code(s->pc++); | |
3729 | reg = ((modrm >> 3) & 7) | rex_r; | |
3730 | ||
3731 | if (b != 0xf0 && b != 0xf1) | |
3732 | goto illegal_op; | |
3733 | if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) | |
4242b1bd AZ |
3734 | goto illegal_op; |
3735 | ||
222a3336 AZ |
3736 | if (b == 0xf0) |
3737 | ot = OT_BYTE; | |
3738 | else if (b == 0xf1 && s->dflag != 2) | |
3739 | if (s->prefix & PREFIX_DATA) | |
3740 | ot = OT_WORD; | |
3741 | else | |
3742 | ot = OT_LONG; | |
3743 | else | |
3744 | ot = OT_QUAD; | |
3745 | ||
3746 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
3747 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
3748 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
a7812ae4 PB |
3749 | gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, |
3750 | cpu_T[0], tcg_const_i32(8 << ot)); | |
222a3336 AZ |
3751 | |
3752 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3753 | gen_op_mov_reg_T0(ot, reg); | |
3754 | break; | |
3755 | case 0x03a: | |
3756 | case 0x13a: | |
4242b1bd AZ |
3757 | b = modrm; |
3758 | modrm = ldub_code(s->pc++); | |
3759 | rm = modrm & 7; | |
3760 | reg = ((modrm >> 3) & 7) | rex_r; | |
3761 | mod = (modrm >> 6) & 3; | |
3762 | ||
222a3336 | 3763 | sse_op2 = sse_op_table7[b].op[b1]; |
4242b1bd AZ |
3764 | if (!sse_op2) |
3765 | goto illegal_op; | |
222a3336 AZ |
3766 | if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) |
3767 | goto illegal_op; | |
3768 | ||
3769 | if (sse_op2 == SSE_SPECIAL) { | |
3770 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3771 | rm = (modrm & 7) | REX_B(s); | |
3772 | if (mod != 3) | |
3773 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3774 | reg = ((modrm >> 3) & 7) | rex_r; | |
3775 | val = ldub_code(s->pc++); | |
3776 | switch (b) { | |
3777 | case 0x14: /* pextrb */ | |
3778 | tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3779 | xmm_regs[reg].XMM_B(val & 15))); | |
3780 | if (mod == 3) | |
3781 | gen_op_mov_reg_T0(ot, rm); | |
3782 | else | |
3783 | tcg_gen_qemu_st8(cpu_T[0], cpu_A0, | |
3784 | (s->mem_index >> 2) - 1); | |
3785 | break; | |
3786 | case 0x15: /* pextrw */ | |
3787 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3788 | xmm_regs[reg].XMM_W(val & 7))); | |
3789 | if (mod == 3) | |
3790 | gen_op_mov_reg_T0(ot, rm); | |
3791 | else | |
3792 | tcg_gen_qemu_st16(cpu_T[0], cpu_A0, | |
3793 | (s->mem_index >> 2) - 1); | |
3794 | break; | |
3795 | case 0x16: | |
3796 | if (ot == OT_LONG) { /* pextrd */ | |
3797 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, | |
3798 | offsetof(CPUX86State, | |
3799 | xmm_regs[reg].XMM_L(val & 3))); | |
a7812ae4 | 3800 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
222a3336 | 3801 | if (mod == 3) |
a7812ae4 | 3802 | gen_op_mov_reg_v(ot, rm, cpu_T[0]); |
222a3336 | 3803 | else |
a7812ae4 | 3804 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, |
222a3336 AZ |
3805 | (s->mem_index >> 2) - 1); |
3806 | } else { /* pextrq */ | |
a7812ae4 | 3807 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3808 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
3809 | offsetof(CPUX86State, | |
3810 | xmm_regs[reg].XMM_Q(val & 1))); | |
3811 | if (mod == 3) | |
3812 | gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); | |
3813 | else | |
3814 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, | |
3815 | (s->mem_index >> 2) - 1); | |
a7812ae4 PB |
3816 | #else |
3817 | goto illegal_op; | |
3818 | #endif | |
222a3336 AZ |
3819 | } |
3820 | break; | |
3821 | case 0x17: /* extractps */ | |
3822 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3823 | xmm_regs[reg].XMM_L(val & 3))); | |
3824 | if (mod == 3) | |
3825 | gen_op_mov_reg_T0(ot, rm); | |
3826 | else | |
3827 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, | |
3828 | (s->mem_index >> 2) - 1); | |
3829 | break; | |
3830 | case 0x20: /* pinsrb */ | |
3831 | if (mod == 3) | |
3832 | gen_op_mov_TN_reg(OT_LONG, 0, rm); | |
3833 | else | |
a7812ae4 | 3834 | tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0, |
222a3336 | 3835 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3836 | tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, |
222a3336 AZ |
3837 | xmm_regs[reg].XMM_B(val & 15))); |
3838 | break; | |
3839 | case 0x21: /* insertps */ | |
a7812ae4 | 3840 | if (mod == 3) { |
222a3336 AZ |
3841 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
3842 | offsetof(CPUX86State,xmm_regs[rm] | |
3843 | .XMM_L((val >> 6) & 3))); | |
a7812ae4 PB |
3844 | } else { |
3845 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, | |
222a3336 | 3846 | (s->mem_index >> 2) - 1); |
a7812ae4 PB |
3847 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
3848 | } | |
222a3336 AZ |
3849 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3850 | offsetof(CPUX86State,xmm_regs[reg] | |
3851 | .XMM_L((val >> 4) & 3))); | |
3852 | if ((val >> 0) & 1) | |
3853 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3854 | cpu_env, offsetof(CPUX86State, | |
3855 | xmm_regs[reg].XMM_L(0))); | |
3856 | if ((val >> 1) & 1) | |
3857 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3858 | cpu_env, offsetof(CPUX86State, | |
3859 | xmm_regs[reg].XMM_L(1))); | |
3860 | if ((val >> 2) & 1) | |
3861 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3862 | cpu_env, offsetof(CPUX86State, | |
3863 | xmm_regs[reg].XMM_L(2))); | |
3864 | if ((val >> 3) & 1) | |
3865 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3866 | cpu_env, offsetof(CPUX86State, | |
3867 | xmm_regs[reg].XMM_L(3))); | |
3868 | break; | |
3869 | case 0x22: | |
3870 | if (ot == OT_LONG) { /* pinsrd */ | |
3871 | if (mod == 3) | |
a7812ae4 | 3872 | gen_op_mov_v_reg(ot, cpu_tmp0, rm); |
222a3336 | 3873 | else |
a7812ae4 | 3874 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3875 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3876 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3877 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3878 | offsetof(CPUX86State, | |
3879 | xmm_regs[reg].XMM_L(val & 3))); | |
3880 | } else { /* pinsrq */ | |
a7812ae4 | 3881 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3882 | if (mod == 3) |
3883 | gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); | |
3884 | else | |
3885 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, | |
3886 | (s->mem_index >> 2) - 1); | |
3887 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, | |
3888 | offsetof(CPUX86State, | |
3889 | xmm_regs[reg].XMM_Q(val & 1))); | |
a7812ae4 PB |
3890 | #else |
3891 | goto illegal_op; | |
3892 | #endif | |
222a3336 AZ |
3893 | } |
3894 | break; | |
3895 | } | |
3896 | return; | |
3897 | } | |
4242b1bd AZ |
3898 | |
3899 | if (b1) { | |
3900 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3901 | if (mod == 3) { | |
3902 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3903 | } else { | |
3904 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3905 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3906 | gen_ldo_env_A0(s->mem_index, op2_offset); | |
3907 | } | |
3908 | } else { | |
3909 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3910 | if (mod == 3) { | |
3911 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3912 | } else { | |
3913 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
3914 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3915 | gen_ldq_env_A0(s->mem_index, op2_offset); | |
3916 | } | |
3917 | } | |
3918 | val = ldub_code(s->pc++); | |
3919 | ||
222a3336 AZ |
3920 | if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ |
3921 | s->cc_op = CC_OP_EFLAGS; | |
3922 | ||
3923 | if (s->dflag == 2) | |
3924 | /* The helper must use entire 64-bit gp registers */ | |
3925 | val |= 1 << 8; | |
3926 | } | |
3927 | ||
4242b1bd AZ |
3928 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3929 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 3930 | ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
4242b1bd | 3931 | break; |
664e0f19 FB |
3932 | default: |
3933 | goto illegal_op; | |
3934 | } | |
3935 | } else { | |
3936 | /* generic MMX or SSE operation */ | |
d1e42c5c | 3937 | switch(b) { |
d1e42c5c FB |
3938 | case 0x70: /* pshufx insn */ |
3939 | case 0xc6: /* pshufx insn */ | |
3940 | case 0xc2: /* compare insns */ | |
3941 | s->rip_offset = 1; | |
3942 | break; | |
3943 | default: | |
3944 | break; | |
664e0f19 FB |
3945 | } |
3946 | if (is_xmm) { | |
3947 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3948 | if (mod != 3) { | |
3949 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3950 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
480c1cdb | 3951 | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
664e0f19 FB |
3952 | b == 0xc2)) { |
3953 | /* specific case for SSE single instructions */ | |
3954 | if (b1 == 2) { | |
3955 | /* 32 bit access */ | |
57fec1fe | 3956 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3957 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 FB |
3958 | } else { |
3959 | /* 64 bit access */ | |
8686c490 | 3960 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0))); |
664e0f19 FB |
3961 | } |
3962 | } else { | |
8686c490 | 3963 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3964 | } |
3965 | } else { | |
3966 | rm = (modrm & 7) | REX_B(s); | |
3967 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3968 | } | |
3969 | } else { | |
3970 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3971 | if (mod != 3) { | |
3972 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3973 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
8686c490 | 3974 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3975 | } else { |
3976 | rm = (modrm & 7); | |
3977 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3978 | } | |
3979 | } | |
3980 | switch(b) { | |
a35f3ec7 | 3981 | case 0x0f: /* 3DNow! data insns */ |
e771edab AJ |
3982 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) |
3983 | goto illegal_op; | |
a35f3ec7 AJ |
3984 | val = ldub_code(s->pc++); |
3985 | sse_op2 = sse_op_table5[val]; | |
3986 | if (!sse_op2) | |
3987 | goto illegal_op; | |
5af45186 FB |
3988 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3989 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 3990 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
a35f3ec7 | 3991 | break; |
664e0f19 FB |
3992 | case 0x70: /* pshufx insn */ |
3993 | case 0xc6: /* pshufx insn */ | |
3994 | val = ldub_code(s->pc++); | |
5af45186 FB |
3995 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3996 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 3997 | ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
664e0f19 FB |
3998 | break; |
3999 | case 0xc2: | |
4000 | /* compare insns */ | |
4001 | val = ldub_code(s->pc++); | |
4002 | if (val >= 8) | |
4003 | goto illegal_op; | |
4004 | sse_op2 = sse_op_table4[val][b1]; | |
5af45186 FB |
4005 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4006 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 4007 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
664e0f19 | 4008 | break; |
b8b6a50b FB |
4009 | case 0xf7: |
4010 | /* maskmov : we must prepare A0 */ | |
4011 | if (mod != 3) | |
4012 | goto illegal_op; | |
4013 | #ifdef TARGET_X86_64 | |
4014 | if (s->aflag == 2) { | |
4015 | gen_op_movq_A0_reg(R_EDI); | |
4016 | } else | |
4017 | #endif | |
4018 | { | |
4019 | gen_op_movl_A0_reg(R_EDI); | |
4020 | if (s->aflag == 0) | |
4021 | gen_op_andl_A0_ffff(); | |
4022 | } | |
4023 | gen_add_A0_ds_seg(s); | |
4024 | ||
4025 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); | |
4026 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 4027 | ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0); |
b8b6a50b | 4028 | break; |
664e0f19 | 4029 | default: |
5af45186 FB |
4030 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4031 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 4032 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
4033 | break; |
4034 | } | |
4035 | if (b == 0x2e || b == 0x2f) { | |
4036 | s->cc_op = CC_OP_EFLAGS; | |
4037 | } | |
4038 | } | |
4039 | } | |
4040 | ||
2c0262af FB |
4041 | /* convert one instruction. s->is_jmp is set if the translation must |
4042 | be stopped. Return the next pc value */ | |
14ce26e7 | 4043 | static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) |
2c0262af FB |
4044 | { |
4045 | int b, prefixes, aflag, dflag; | |
4046 | int shift, ot; | |
4047 | int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val; | |
14ce26e7 FB |
4048 | target_ulong next_eip, tval; |
4049 | int rex_w, rex_r; | |
2c0262af | 4050 | |
8fec2b8c | 4051 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) |
70cff25e | 4052 | tcg_gen_debug_insn_start(pc_start); |
2c0262af FB |
4053 | s->pc = pc_start; |
4054 | prefixes = 0; | |
4055 | aflag = s->code32; | |
4056 | dflag = s->code32; | |
4057 | s->override = -1; | |
14ce26e7 FB |
4058 | rex_w = -1; |
4059 | rex_r = 0; | |
4060 | #ifdef TARGET_X86_64 | |
4061 | s->rex_x = 0; | |
4062 | s->rex_b = 0; | |
5fafdf24 | 4063 | x86_64_hregs = 0; |
14ce26e7 FB |
4064 | #endif |
4065 | s->rip_offset = 0; /* for relative ip address */ | |
2c0262af | 4066 | next_byte: |
61382a50 | 4067 | b = ldub_code(s->pc); |
2c0262af FB |
4068 | s->pc++; |
4069 | /* check prefixes */ | |
14ce26e7 FB |
4070 | #ifdef TARGET_X86_64 |
4071 | if (CODE64(s)) { | |
4072 | switch (b) { | |
4073 | case 0xf3: | |
4074 | prefixes |= PREFIX_REPZ; | |
4075 | goto next_byte; | |
4076 | case 0xf2: | |
4077 | prefixes |= PREFIX_REPNZ; | |
4078 | goto next_byte; | |
4079 | case 0xf0: | |
4080 | prefixes |= PREFIX_LOCK; | |
4081 | goto next_byte; | |
4082 | case 0x2e: | |
4083 | s->override = R_CS; | |
4084 | goto next_byte; | |
4085 | case 0x36: | |
4086 | s->override = R_SS; | |
4087 | goto next_byte; | |
4088 | case 0x3e: | |
4089 | s->override = R_DS; | |
4090 | goto next_byte; | |
4091 | case 0x26: | |
4092 | s->override = R_ES; | |
4093 | goto next_byte; | |
4094 | case 0x64: | |
4095 | s->override = R_FS; | |
4096 | goto next_byte; | |
4097 | case 0x65: | |
4098 | s->override = R_GS; | |
4099 | goto next_byte; | |
4100 | case 0x66: | |
4101 | prefixes |= PREFIX_DATA; | |
4102 | goto next_byte; | |
4103 | case 0x67: | |
4104 | prefixes |= PREFIX_ADR; | |
4105 | goto next_byte; | |
4106 | case 0x40 ... 0x4f: | |
4107 | /* REX prefix */ | |
4108 | rex_w = (b >> 3) & 1; | |
4109 | rex_r = (b & 0x4) << 1; | |
4110 | s->rex_x = (b & 0x2) << 2; | |
4111 | REX_B(s) = (b & 0x1) << 3; | |
4112 | x86_64_hregs = 1; /* select uniform byte register addressing */ | |
4113 | goto next_byte; | |
4114 | } | |
4115 | if (rex_w == 1) { | |
4116 | /* 0x66 is ignored if rex.w is set */ | |
4117 | dflag = 2; | |
4118 | } else { | |
4119 | if (prefixes & PREFIX_DATA) | |
4120 | dflag ^= 1; | |
4121 | } | |
4122 | if (!(prefixes & PREFIX_ADR)) | |
4123 | aflag = 2; | |
5fafdf24 | 4124 | } else |
14ce26e7 FB |
4125 | #endif |
4126 | { | |
4127 | switch (b) { | |
4128 | case 0xf3: | |
4129 | prefixes |= PREFIX_REPZ; | |
4130 | goto next_byte; | |
4131 | case 0xf2: | |
4132 | prefixes |= PREFIX_REPNZ; | |
4133 | goto next_byte; | |
4134 | case 0xf0: | |
4135 | prefixes |= PREFIX_LOCK; | |
4136 | goto next_byte; | |
4137 | case 0x2e: | |
4138 | s->override = R_CS; | |
4139 | goto next_byte; | |
4140 | case 0x36: | |
4141 | s->override = R_SS; | |
4142 | goto next_byte; | |
4143 | case 0x3e: | |
4144 | s->override = R_DS; | |
4145 | goto next_byte; | |
4146 | case 0x26: | |
4147 | s->override = R_ES; | |
4148 | goto next_byte; | |
4149 | case 0x64: | |
4150 | s->override = R_FS; | |
4151 | goto next_byte; | |
4152 | case 0x65: | |
4153 | s->override = R_GS; | |
4154 | goto next_byte; | |
4155 | case 0x66: | |
4156 | prefixes |= PREFIX_DATA; | |
4157 | goto next_byte; | |
4158 | case 0x67: | |
4159 | prefixes |= PREFIX_ADR; | |
4160 | goto next_byte; | |
4161 | } | |
4162 | if (prefixes & PREFIX_DATA) | |
4163 | dflag ^= 1; | |
4164 | if (prefixes & PREFIX_ADR) | |
4165 | aflag ^= 1; | |
2c0262af FB |
4166 | } |
4167 | ||
2c0262af FB |
4168 | s->prefix = prefixes; |
4169 | s->aflag = aflag; | |
4170 | s->dflag = dflag; | |
4171 | ||
4172 | /* lock generation */ | |
4173 | if (prefixes & PREFIX_LOCK) | |
a7812ae4 | 4174 | gen_helper_lock(); |
2c0262af FB |
4175 | |
4176 | /* now check op code */ | |
4177 | reswitch: | |
4178 | switch(b) { | |
4179 | case 0x0f: | |
4180 | /**************************/ | |
4181 | /* extended op code */ | |
61382a50 | 4182 | b = ldub_code(s->pc++) | 0x100; |
2c0262af | 4183 | goto reswitch; |
3b46e624 | 4184 | |
2c0262af FB |
4185 | /**************************/ |
4186 | /* arith & logic */ | |
4187 | case 0x00 ... 0x05: | |
4188 | case 0x08 ... 0x0d: | |
4189 | case 0x10 ... 0x15: | |
4190 | case 0x18 ... 0x1d: | |
4191 | case 0x20 ... 0x25: | |
4192 | case 0x28 ... 0x2d: | |
4193 | case 0x30 ... 0x35: | |
4194 | case 0x38 ... 0x3d: | |
4195 | { | |
4196 | int op, f, val; | |
4197 | op = (b >> 3) & 7; | |
4198 | f = (b >> 1) & 3; | |
4199 | ||
4200 | if ((b & 1) == 0) | |
4201 | ot = OT_BYTE; | |
4202 | else | |
14ce26e7 | 4203 | ot = dflag + OT_WORD; |
3b46e624 | 4204 | |
2c0262af FB |
4205 | switch(f) { |
4206 | case 0: /* OP Ev, Gv */ | |
61382a50 | 4207 | modrm = ldub_code(s->pc++); |
14ce26e7 | 4208 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 4209 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4210 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4211 | if (mod != 3) { |
4212 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4213 | opreg = OR_TMP0; | |
4214 | } else if (op == OP_XORL && rm == reg) { | |
4215 | xor_zero: | |
4216 | /* xor reg, reg optimisation */ | |
4217 | gen_op_movl_T0_0(); | |
4218 | s->cc_op = CC_OP_LOGICB + ot; | |
57fec1fe | 4219 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
4220 | gen_op_update1_cc(); |
4221 | break; | |
4222 | } else { | |
4223 | opreg = rm; | |
4224 | } | |
57fec1fe | 4225 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4226 | gen_op(s, op, ot, opreg); |
4227 | break; | |
4228 | case 1: /* OP Gv, Ev */ | |
61382a50 | 4229 | modrm = ldub_code(s->pc++); |
2c0262af | 4230 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
4231 | reg = ((modrm >> 3) & 7) | rex_r; |
4232 | rm = (modrm & 7) | REX_B(s); | |
2c0262af FB |
4233 | if (mod != 3) { |
4234 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 4235 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af FB |
4236 | } else if (op == OP_XORL && rm == reg) { |
4237 | goto xor_zero; | |
4238 | } else { | |
57fec1fe | 4239 | gen_op_mov_TN_reg(ot, 1, rm); |
2c0262af FB |
4240 | } |
4241 | gen_op(s, op, ot, reg); | |
4242 | break; | |
4243 | case 2: /* OP A, Iv */ | |
4244 | val = insn_get(s, ot); | |
4245 | gen_op_movl_T1_im(val); | |
4246 | gen_op(s, op, ot, OR_EAX); | |
4247 | break; | |
4248 | } | |
4249 | } | |
4250 | break; | |
4251 | ||
ec9d6075 FB |
4252 | case 0x82: |
4253 | if (CODE64(s)) | |
4254 | goto illegal_op; | |
2c0262af FB |
4255 | case 0x80: /* GRP1 */ |
4256 | case 0x81: | |
4257 | case 0x83: | |
4258 | { | |
4259 | int val; | |
4260 | ||
4261 | if ((b & 1) == 0) | |
4262 | ot = OT_BYTE; | |
4263 | else | |
14ce26e7 | 4264 | ot = dflag + OT_WORD; |
3b46e624 | 4265 | |
61382a50 | 4266 | modrm = ldub_code(s->pc++); |
2c0262af | 4267 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4268 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4269 | op = (modrm >> 3) & 7; |
3b46e624 | 4270 | |
2c0262af | 4271 | if (mod != 3) { |
14ce26e7 FB |
4272 | if (b == 0x83) |
4273 | s->rip_offset = 1; | |
4274 | else | |
4275 | s->rip_offset = insn_const_size(ot); | |
2c0262af FB |
4276 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4277 | opreg = OR_TMP0; | |
4278 | } else { | |
14ce26e7 | 4279 | opreg = rm; |
2c0262af FB |
4280 | } |
4281 | ||
4282 | switch(b) { | |
4283 | default: | |
4284 | case 0x80: | |
4285 | case 0x81: | |
d64477af | 4286 | case 0x82: |
2c0262af FB |
4287 | val = insn_get(s, ot); |
4288 | break; | |
4289 | case 0x83: | |
4290 | val = (int8_t)insn_get(s, OT_BYTE); | |
4291 | break; | |
4292 | } | |
4293 | gen_op_movl_T1_im(val); | |
4294 | gen_op(s, op, ot, opreg); | |
4295 | } | |
4296 | break; | |
4297 | ||
4298 | /**************************/ | |
4299 | /* inc, dec, and other misc arith */ | |
4300 | case 0x40 ... 0x47: /* inc Gv */ | |
4301 | ot = dflag ? OT_LONG : OT_WORD; | |
4302 | gen_inc(s, ot, OR_EAX + (b & 7), 1); | |
4303 | break; | |
4304 | case 0x48 ... 0x4f: /* dec Gv */ | |
4305 | ot = dflag ? OT_LONG : OT_WORD; | |
4306 | gen_inc(s, ot, OR_EAX + (b & 7), -1); | |
4307 | break; | |
4308 | case 0xf6: /* GRP3 */ | |
4309 | case 0xf7: | |
4310 | if ((b & 1) == 0) | |
4311 | ot = OT_BYTE; | |
4312 | else | |
14ce26e7 | 4313 | ot = dflag + OT_WORD; |
2c0262af | 4314 | |
61382a50 | 4315 | modrm = ldub_code(s->pc++); |
2c0262af | 4316 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4317 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4318 | op = (modrm >> 3) & 7; |
4319 | if (mod != 3) { | |
14ce26e7 FB |
4320 | if (op == 0) |
4321 | s->rip_offset = insn_const_size(ot); | |
2c0262af | 4322 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
57fec1fe | 4323 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4324 | } else { |
57fec1fe | 4325 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4326 | } |
4327 | ||
4328 | switch(op) { | |
4329 | case 0: /* test */ | |
4330 | val = insn_get(s, ot); | |
4331 | gen_op_movl_T1_im(val); | |
4332 | gen_op_testl_T0_T1_cc(); | |
4333 | s->cc_op = CC_OP_LOGICB + ot; | |
4334 | break; | |
4335 | case 2: /* not */ | |
b6abf97d | 4336 | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4337 | if (mod != 3) { |
57fec1fe | 4338 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4339 | } else { |
57fec1fe | 4340 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4341 | } |
4342 | break; | |
4343 | case 3: /* neg */ | |
b6abf97d | 4344 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4345 | if (mod != 3) { |
57fec1fe | 4346 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4347 | } else { |
57fec1fe | 4348 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4349 | } |
4350 | gen_op_update_neg_cc(); | |
4351 | s->cc_op = CC_OP_SUBB + ot; | |
4352 | break; | |
4353 | case 4: /* mul */ | |
4354 | switch(ot) { | |
4355 | case OT_BYTE: | |
0211e5af FB |
4356 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4357 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); | |
4358 | tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); | |
4359 | /* XXX: use 32 bit mul which could be faster */ | |
4360 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4361 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4362 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4363 | tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); | |
d36cd60e | 4364 | s->cc_op = CC_OP_MULB; |
2c0262af FB |
4365 | break; |
4366 | case OT_WORD: | |
0211e5af FB |
4367 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4368 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); | |
4369 | tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); | |
4370 | /* XXX: use 32 bit mul which could be faster */ | |
4371 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4372 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4373 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4374 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4375 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4376 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
d36cd60e | 4377 | s->cc_op = CC_OP_MULW; |
2c0262af FB |
4378 | break; |
4379 | default: | |
4380 | case OT_LONG: | |
0211e5af FB |
4381 | #ifdef TARGET_X86_64 |
4382 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4383 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); | |
4384 | tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); | |
4385 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4386 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4387 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4388 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4389 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4390 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4391 | #else | |
4392 | { | |
a7812ae4 PB |
4393 | TCGv_i64 t0, t1; |
4394 | t0 = tcg_temp_new_i64(); | |
4395 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4396 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4397 | tcg_gen_extu_i32_i64(t0, cpu_T[0]); | |
4398 | tcg_gen_extu_i32_i64(t1, cpu_T[1]); | |
4399 | tcg_gen_mul_i64(t0, t0, t1); | |
4400 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4401 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4402 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4403 | tcg_gen_shri_i64(t0, t0, 32); | |
4404 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4405 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4406 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4407 | } | |
4408 | #endif | |
d36cd60e | 4409 | s->cc_op = CC_OP_MULL; |
2c0262af | 4410 | break; |
14ce26e7 FB |
4411 | #ifdef TARGET_X86_64 |
4412 | case OT_QUAD: | |
a7812ae4 | 4413 | gen_helper_mulq_EAX_T0(cpu_T[0]); |
14ce26e7 FB |
4414 | s->cc_op = CC_OP_MULQ; |
4415 | break; | |
4416 | #endif | |
2c0262af | 4417 | } |
2c0262af FB |
4418 | break; |
4419 | case 5: /* imul */ | |
4420 | switch(ot) { | |
4421 | case OT_BYTE: | |
0211e5af FB |
4422 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4423 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4424 | tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); | |
4425 | /* XXX: use 32 bit mul which could be faster */ | |
4426 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4427 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4428 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4429 | tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]); | |
4430 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
d36cd60e | 4431 | s->cc_op = CC_OP_MULB; |
2c0262af FB |
4432 | break; |
4433 | case OT_WORD: | |
0211e5af FB |
4434 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4435 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4436 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4437 | /* XXX: use 32 bit mul which could be faster */ | |
4438 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4439 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4440 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4441 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4442 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4443 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4444 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
d36cd60e | 4445 | s->cc_op = CC_OP_MULW; |
2c0262af FB |
4446 | break; |
4447 | default: | |
4448 | case OT_LONG: | |
0211e5af FB |
4449 | #ifdef TARGET_X86_64 |
4450 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4451 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4452 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4453 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4454 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4455 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4456 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4457 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4458 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4459 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4460 | #else | |
4461 | { | |
a7812ae4 PB |
4462 | TCGv_i64 t0, t1; |
4463 | t0 = tcg_temp_new_i64(); | |
4464 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4465 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4466 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); | |
4467 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4468 | tcg_gen_mul_i64(t0, t0, t1); | |
4469 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4470 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4471 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4472 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4473 | tcg_gen_shri_i64(t0, t0, 32); | |
4474 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4475 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4476 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4477 | } | |
4478 | #endif | |
d36cd60e | 4479 | s->cc_op = CC_OP_MULL; |
2c0262af | 4480 | break; |
14ce26e7 FB |
4481 | #ifdef TARGET_X86_64 |
4482 | case OT_QUAD: | |
a7812ae4 | 4483 | gen_helper_imulq_EAX_T0(cpu_T[0]); |
14ce26e7 FB |
4484 | s->cc_op = CC_OP_MULQ; |
4485 | break; | |
4486 | #endif | |
2c0262af | 4487 | } |
2c0262af FB |
4488 | break; |
4489 | case 6: /* div */ | |
4490 | switch(ot) { | |
4491 | case OT_BYTE: | |
14ce26e7 | 4492 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4493 | gen_helper_divb_AL(cpu_T[0]); |
2c0262af FB |
4494 | break; |
4495 | case OT_WORD: | |
14ce26e7 | 4496 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4497 | gen_helper_divw_AX(cpu_T[0]); |
2c0262af FB |
4498 | break; |
4499 | default: | |
4500 | case OT_LONG: | |
14ce26e7 | 4501 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4502 | gen_helper_divl_EAX(cpu_T[0]); |
14ce26e7 FB |
4503 | break; |
4504 | #ifdef TARGET_X86_64 | |
4505 | case OT_QUAD: | |
4506 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 4507 | gen_helper_divq_EAX(cpu_T[0]); |
2c0262af | 4508 | break; |
14ce26e7 | 4509 | #endif |
2c0262af FB |
4510 | } |
4511 | break; | |
4512 | case 7: /* idiv */ | |
4513 | switch(ot) { | |
4514 | case OT_BYTE: | |
14ce26e7 | 4515 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4516 | gen_helper_idivb_AL(cpu_T[0]); |
2c0262af FB |
4517 | break; |
4518 | case OT_WORD: | |
14ce26e7 | 4519 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4520 | gen_helper_idivw_AX(cpu_T[0]); |
2c0262af FB |
4521 | break; |
4522 | default: | |
4523 | case OT_LONG: | |
14ce26e7 | 4524 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4525 | gen_helper_idivl_EAX(cpu_T[0]); |
14ce26e7 FB |
4526 | break; |
4527 | #ifdef TARGET_X86_64 | |
4528 | case OT_QUAD: | |
4529 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 4530 | gen_helper_idivq_EAX(cpu_T[0]); |
2c0262af | 4531 | break; |
14ce26e7 | 4532 | #endif |
2c0262af FB |
4533 | } |
4534 | break; | |
4535 | default: | |
4536 | goto illegal_op; | |
4537 | } | |
4538 | break; | |
4539 | ||
4540 | case 0xfe: /* GRP4 */ | |
4541 | case 0xff: /* GRP5 */ | |
4542 | if ((b & 1) == 0) | |
4543 | ot = OT_BYTE; | |
4544 | else | |
14ce26e7 | 4545 | ot = dflag + OT_WORD; |
2c0262af | 4546 | |
61382a50 | 4547 | modrm = ldub_code(s->pc++); |
2c0262af | 4548 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4549 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4550 | op = (modrm >> 3) & 7; |
4551 | if (op >= 2 && b == 0xfe) { | |
4552 | goto illegal_op; | |
4553 | } | |
14ce26e7 | 4554 | if (CODE64(s)) { |
aba9d61e | 4555 | if (op == 2 || op == 4) { |
14ce26e7 FB |
4556 | /* operand size for jumps is 64 bit */ |
4557 | ot = OT_QUAD; | |
aba9d61e FB |
4558 | } else if (op == 3 || op == 5) { |
4559 | /* for call calls, the operand is 16 or 32 bit, even | |
4560 | in long mode */ | |
4561 | ot = dflag ? OT_LONG : OT_WORD; | |
14ce26e7 FB |
4562 | } else if (op == 6) { |
4563 | /* default push size is 64 bit */ | |
4564 | ot = dflag ? OT_QUAD : OT_WORD; | |
4565 | } | |
4566 | } | |
2c0262af FB |
4567 | if (mod != 3) { |
4568 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4569 | if (op >= 2 && op != 3 && op != 5) | |
57fec1fe | 4570 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4571 | } else { |
57fec1fe | 4572 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4573 | } |
4574 | ||
4575 | switch(op) { | |
4576 | case 0: /* inc Ev */ | |
4577 | if (mod != 3) | |
4578 | opreg = OR_TMP0; | |
4579 | else | |
4580 | opreg = rm; | |
4581 | gen_inc(s, ot, opreg, 1); | |
4582 | break; | |
4583 | case 1: /* dec Ev */ | |
4584 | if (mod != 3) | |
4585 | opreg = OR_TMP0; | |
4586 | else | |
4587 | opreg = rm; | |
4588 | gen_inc(s, ot, opreg, -1); | |
4589 | break; | |
4590 | case 2: /* call Ev */ | |
4f31916f | 4591 | /* XXX: optimize if memory (no 'and' is necessary) */ |
2c0262af FB |
4592 | if (s->dflag == 0) |
4593 | gen_op_andl_T0_ffff(); | |
2c0262af | 4594 | next_eip = s->pc - s->cs_base; |
1ef38687 | 4595 | gen_movtl_T1_im(next_eip); |
4f31916f FB |
4596 | gen_push_T1(s); |
4597 | gen_op_jmp_T0(); | |
2c0262af FB |
4598 | gen_eob(s); |
4599 | break; | |
61382a50 | 4600 | case 3: /* lcall Ev */ |
57fec1fe | 4601 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4602 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4603 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4604 | do_lcall: |
4605 | if (s->pe && !s->vm86) { | |
4606 | if (s->cc_op != CC_OP_DYNAMIC) | |
4607 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 4608 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4609 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
4610 | gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1], |
4611 | tcg_const_i32(dflag), | |
4612 | tcg_const_i32(s->pc - pc_start)); | |
2c0262af | 4613 | } else { |
b6abf97d | 4614 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
4615 | gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1], |
4616 | tcg_const_i32(dflag), | |
4617 | tcg_const_i32(s->pc - s->cs_base)); | |
2c0262af FB |
4618 | } |
4619 | gen_eob(s); | |
4620 | break; | |
4621 | case 4: /* jmp Ev */ | |
4622 | if (s->dflag == 0) | |
4623 | gen_op_andl_T0_ffff(); | |
4624 | gen_op_jmp_T0(); | |
4625 | gen_eob(s); | |
4626 | break; | |
4627 | case 5: /* ljmp Ev */ | |
57fec1fe | 4628 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4629 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4630 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4631 | do_ljmp: |
4632 | if (s->pe && !s->vm86) { | |
4633 | if (s->cc_op != CC_OP_DYNAMIC) | |
4634 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 4635 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4636 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
4637 | gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1], |
4638 | tcg_const_i32(s->pc - pc_start)); | |
2c0262af | 4639 | } else { |
3bd7da9e | 4640 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
4641 | gen_op_movl_T0_T1(); |
4642 | gen_op_jmp_T0(); | |
4643 | } | |
4644 | gen_eob(s); | |
4645 | break; | |
4646 | case 6: /* push Ev */ | |
4647 | gen_push_T0(s); | |
4648 | break; | |
4649 | default: | |
4650 | goto illegal_op; | |
4651 | } | |
4652 | break; | |
4653 | ||
4654 | case 0x84: /* test Ev, Gv */ | |
5fafdf24 | 4655 | case 0x85: |
2c0262af FB |
4656 | if ((b & 1) == 0) |
4657 | ot = OT_BYTE; | |
4658 | else | |
14ce26e7 | 4659 | ot = dflag + OT_WORD; |
2c0262af | 4660 | |
61382a50 | 4661 | modrm = ldub_code(s->pc++); |
2c0262af | 4662 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
4663 | rm = (modrm & 7) | REX_B(s); |
4664 | reg = ((modrm >> 3) & 7) | rex_r; | |
3b46e624 | 4665 | |
2c0262af | 4666 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 4667 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4668 | gen_op_testl_T0_T1_cc(); |
4669 | s->cc_op = CC_OP_LOGICB + ot; | |
4670 | break; | |
3b46e624 | 4671 | |
2c0262af FB |
4672 | case 0xa8: /* test eAX, Iv */ |
4673 | case 0xa9: | |
4674 | if ((b & 1) == 0) | |
4675 | ot = OT_BYTE; | |
4676 | else | |
14ce26e7 | 4677 | ot = dflag + OT_WORD; |
2c0262af FB |
4678 | val = insn_get(s, ot); |
4679 | ||
57fec1fe | 4680 | gen_op_mov_TN_reg(ot, 0, OR_EAX); |
2c0262af FB |
4681 | gen_op_movl_T1_im(val); |
4682 | gen_op_testl_T0_T1_cc(); | |
4683 | s->cc_op = CC_OP_LOGICB + ot; | |
4684 | break; | |
3b46e624 | 4685 | |
2c0262af | 4686 | case 0x98: /* CWDE/CBW */ |
14ce26e7 FB |
4687 | #ifdef TARGET_X86_64 |
4688 | if (dflag == 2) { | |
e108dd01 FB |
4689 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
4690 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4691 | gen_op_mov_reg_T0(OT_QUAD, R_EAX); | |
14ce26e7 FB |
4692 | } else |
4693 | #endif | |
e108dd01 FB |
4694 | if (dflag == 1) { |
4695 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4696 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4697 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4698 | } else { | |
4699 | gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX); | |
4700 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4701 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4702 | } | |
2c0262af FB |
4703 | break; |
4704 | case 0x99: /* CDQ/CWD */ | |
14ce26e7 FB |
4705 | #ifdef TARGET_X86_64 |
4706 | if (dflag == 2) { | |
e108dd01 FB |
4707 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
4708 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); | |
4709 | gen_op_mov_reg_T0(OT_QUAD, R_EDX); | |
14ce26e7 FB |
4710 | } else |
4711 | #endif | |
e108dd01 FB |
4712 | if (dflag == 1) { |
4713 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); | |
4714 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4715 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); | |
4716 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4717 | } else { | |
4718 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4719 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4720 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); | |
4721 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4722 | } | |
2c0262af FB |
4723 | break; |
4724 | case 0x1af: /* imul Gv, Ev */ | |
4725 | case 0x69: /* imul Gv, Ev, I */ | |
4726 | case 0x6b: | |
14ce26e7 | 4727 | ot = dflag + OT_WORD; |
61382a50 | 4728 | modrm = ldub_code(s->pc++); |
14ce26e7 FB |
4729 | reg = ((modrm >> 3) & 7) | rex_r; |
4730 | if (b == 0x69) | |
4731 | s->rip_offset = insn_const_size(ot); | |
4732 | else if (b == 0x6b) | |
4733 | s->rip_offset = 1; | |
2c0262af FB |
4734 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); |
4735 | if (b == 0x69) { | |
4736 | val = insn_get(s, ot); | |
4737 | gen_op_movl_T1_im(val); | |
4738 | } else if (b == 0x6b) { | |
d64477af | 4739 | val = (int8_t)insn_get(s, OT_BYTE); |
2c0262af FB |
4740 | gen_op_movl_T1_im(val); |
4741 | } else { | |
57fec1fe | 4742 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4743 | } |
4744 | ||
14ce26e7 FB |
4745 | #ifdef TARGET_X86_64 |
4746 | if (ot == OT_QUAD) { | |
a7812ae4 | 4747 | gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]); |
14ce26e7 FB |
4748 | } else |
4749 | #endif | |
2c0262af | 4750 | if (ot == OT_LONG) { |
0211e5af FB |
4751 | #ifdef TARGET_X86_64 |
4752 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4753 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4754 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4755 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4756 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4757 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4758 | #else | |
4759 | { | |
a7812ae4 PB |
4760 | TCGv_i64 t0, t1; |
4761 | t0 = tcg_temp_new_i64(); | |
4762 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4763 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); |
4764 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4765 | tcg_gen_mul_i64(t0, t0, t1); | |
4766 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4767 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4768 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4769 | tcg_gen_shri_i64(t0, t0, 32); | |
4770 | tcg_gen_trunc_i64_i32(cpu_T[1], t0); | |
4771 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0); | |
4772 | } | |
4773 | #endif | |
2c0262af | 4774 | } else { |
0211e5af FB |
4775 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4776 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4777 | /* XXX: use 32 bit mul which could be faster */ | |
4778 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4779 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4780 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4781 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
2c0262af | 4782 | } |
57fec1fe | 4783 | gen_op_mov_reg_T0(ot, reg); |
d36cd60e | 4784 | s->cc_op = CC_OP_MULB + ot; |
2c0262af FB |
4785 | break; |
4786 | case 0x1c0: | |
4787 | case 0x1c1: /* xadd Ev, Gv */ | |
4788 | if ((b & 1) == 0) | |
4789 | ot = OT_BYTE; | |
4790 | else | |
14ce26e7 | 4791 | ot = dflag + OT_WORD; |
61382a50 | 4792 | modrm = ldub_code(s->pc++); |
14ce26e7 | 4793 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
4794 | mod = (modrm >> 6) & 3; |
4795 | if (mod == 3) { | |
14ce26e7 | 4796 | rm = (modrm & 7) | REX_B(s); |
57fec1fe FB |
4797 | gen_op_mov_TN_reg(ot, 0, reg); |
4798 | gen_op_mov_TN_reg(ot, 1, rm); | |
2c0262af | 4799 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4800 | gen_op_mov_reg_T1(ot, reg); |
4801 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af FB |
4802 | } else { |
4803 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe FB |
4804 | gen_op_mov_TN_reg(ot, 0, reg); |
4805 | gen_op_ld_T1_A0(ot + s->mem_index); | |
2c0262af | 4806 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4807 | gen_op_st_T0_A0(ot + s->mem_index); |
4808 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af FB |
4809 | } |
4810 | gen_op_update2_cc(); | |
4811 | s->cc_op = CC_OP_ADDB + ot; | |
4812 | break; | |
4813 | case 0x1b0: | |
4814 | case 0x1b1: /* cmpxchg Ev, Gv */ | |
cad3a37d | 4815 | { |
1130328e | 4816 | int label1, label2; |
1e4840bf | 4817 | TCGv t0, t1, t2, a0; |
cad3a37d FB |
4818 | |
4819 | if ((b & 1) == 0) | |
4820 | ot = OT_BYTE; | |
4821 | else | |
4822 | ot = dflag + OT_WORD; | |
4823 | modrm = ldub_code(s->pc++); | |
4824 | reg = ((modrm >> 3) & 7) | rex_r; | |
4825 | mod = (modrm >> 6) & 3; | |
a7812ae4 PB |
4826 | t0 = tcg_temp_local_new(); |
4827 | t1 = tcg_temp_local_new(); | |
4828 | t2 = tcg_temp_local_new(); | |
4829 | a0 = tcg_temp_local_new(); | |
1e4840bf | 4830 | gen_op_mov_v_reg(ot, t1, reg); |
cad3a37d FB |
4831 | if (mod == 3) { |
4832 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 4833 | gen_op_mov_v_reg(ot, t0, rm); |
cad3a37d FB |
4834 | } else { |
4835 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
1e4840bf FB |
4836 | tcg_gen_mov_tl(a0, cpu_A0); |
4837 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
cad3a37d FB |
4838 | rm = 0; /* avoid warning */ |
4839 | } | |
4840 | label1 = gen_new_label(); | |
cc739bb0 | 4841 | tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0); |
1e4840bf FB |
4842 | gen_extu(ot, t2); |
4843 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); | |
cad3a37d | 4844 | if (mod == 3) { |
1130328e | 4845 | label2 = gen_new_label(); |
1e4840bf | 4846 | gen_op_mov_reg_v(ot, R_EAX, t0); |
1130328e FB |
4847 | tcg_gen_br(label2); |
4848 | gen_set_label(label1); | |
1e4840bf | 4849 | gen_op_mov_reg_v(ot, rm, t1); |
1130328e | 4850 | gen_set_label(label2); |
cad3a37d | 4851 | } else { |
1e4840bf FB |
4852 | tcg_gen_mov_tl(t1, t0); |
4853 | gen_op_mov_reg_v(ot, R_EAX, t0); | |
1130328e FB |
4854 | gen_set_label(label1); |
4855 | /* always store */ | |
1e4840bf | 4856 | gen_op_st_v(ot + s->mem_index, t1, a0); |
cad3a37d | 4857 | } |
1e4840bf FB |
4858 | tcg_gen_mov_tl(cpu_cc_src, t0); |
4859 | tcg_gen_mov_tl(cpu_cc_dst, t2); | |
cad3a37d | 4860 | s->cc_op = CC_OP_SUBB + ot; |
1e4840bf FB |
4861 | tcg_temp_free(t0); |
4862 | tcg_temp_free(t1); | |
4863 | tcg_temp_free(t2); | |
4864 | tcg_temp_free(a0); | |
2c0262af | 4865 | } |
2c0262af FB |
4866 | break; |
4867 | case 0x1c7: /* cmpxchg8b */ | |
61382a50 | 4868 | modrm = ldub_code(s->pc++); |
2c0262af | 4869 | mod = (modrm >> 6) & 3; |
71c3558e | 4870 | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
2c0262af | 4871 | goto illegal_op; |
1b9d9ebb FB |
4872 | #ifdef TARGET_X86_64 |
4873 | if (dflag == 2) { | |
4874 | if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) | |
4875 | goto illegal_op; | |
4876 | gen_jmp_im(pc_start - s->cs_base); | |
4877 | if (s->cc_op != CC_OP_DYNAMIC) | |
4878 | gen_op_set_cc_op(s->cc_op); | |
4879 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
a7812ae4 | 4880 | gen_helper_cmpxchg16b(cpu_A0); |
1b9d9ebb FB |
4881 | } else |
4882 | #endif | |
4883 | { | |
4884 | if (!(s->cpuid_features & CPUID_CX8)) | |
4885 | goto illegal_op; | |
4886 | gen_jmp_im(pc_start - s->cs_base); | |
4887 | if (s->cc_op != CC_OP_DYNAMIC) | |
4888 | gen_op_set_cc_op(s->cc_op); | |
4889 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
a7812ae4 | 4890 | gen_helper_cmpxchg8b(cpu_A0); |
1b9d9ebb | 4891 | } |
2c0262af FB |
4892 | s->cc_op = CC_OP_EFLAGS; |
4893 | break; | |
3b46e624 | 4894 | |
2c0262af FB |
4895 | /**************************/ |
4896 | /* push/pop */ | |
4897 | case 0x50 ... 0x57: /* push */ | |
57fec1fe | 4898 | gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s)); |
2c0262af FB |
4899 | gen_push_T0(s); |
4900 | break; | |
4901 | case 0x58 ... 0x5f: /* pop */ | |
14ce26e7 FB |
4902 | if (CODE64(s)) { |
4903 | ot = dflag ? OT_QUAD : OT_WORD; | |
4904 | } else { | |
4905 | ot = dflag + OT_WORD; | |
4906 | } | |
2c0262af | 4907 | gen_pop_T0(s); |
77729c24 | 4908 | /* NOTE: order is important for pop %sp */ |
2c0262af | 4909 | gen_pop_update(s); |
57fec1fe | 4910 | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s)); |
2c0262af FB |
4911 | break; |
4912 | case 0x60: /* pusha */ | |
14ce26e7 FB |
4913 | if (CODE64(s)) |
4914 | goto illegal_op; | |
2c0262af FB |
4915 | gen_pusha(s); |
4916 | break; | |
4917 | case 0x61: /* popa */ | |
14ce26e7 FB |
4918 | if (CODE64(s)) |
4919 | goto illegal_op; | |
2c0262af FB |
4920 | gen_popa(s); |
4921 | break; | |
4922 | case 0x68: /* push Iv */ | |
4923 | case 0x6a: | |
14ce26e7 FB |
4924 | if (CODE64(s)) { |
4925 | ot = dflag ? OT_QUAD : OT_WORD; | |
4926 | } else { | |
4927 | ot = dflag + OT_WORD; | |
4928 | } | |
2c0262af FB |
4929 | if (b == 0x68) |
4930 | val = insn_get(s, ot); | |
4931 | else | |
4932 | val = (int8_t)insn_get(s, OT_BYTE); | |
4933 | gen_op_movl_T0_im(val); | |
4934 | gen_push_T0(s); | |
4935 | break; | |
4936 | case 0x8f: /* pop Ev */ | |
14ce26e7 FB |
4937 | if (CODE64(s)) { |
4938 | ot = dflag ? OT_QUAD : OT_WORD; | |
4939 | } else { | |
4940 | ot = dflag + OT_WORD; | |
4941 | } | |
61382a50 | 4942 | modrm = ldub_code(s->pc++); |
77729c24 | 4943 | mod = (modrm >> 6) & 3; |
2c0262af | 4944 | gen_pop_T0(s); |
77729c24 FB |
4945 | if (mod == 3) { |
4946 | /* NOTE: order is important for pop %sp */ | |
4947 | gen_pop_update(s); | |
14ce26e7 | 4948 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 4949 | gen_op_mov_reg_T0(ot, rm); |
77729c24 FB |
4950 | } else { |
4951 | /* NOTE: order is important too for MMU exceptions */ | |
14ce26e7 | 4952 | s->popl_esp_hack = 1 << ot; |
77729c24 FB |
4953 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); |
4954 | s->popl_esp_hack = 0; | |
4955 | gen_pop_update(s); | |
4956 | } | |
2c0262af FB |
4957 | break; |
4958 | case 0xc8: /* enter */ | |
4959 | { | |
4960 | int level; | |
61382a50 | 4961 | val = lduw_code(s->pc); |
2c0262af | 4962 | s->pc += 2; |
61382a50 | 4963 | level = ldub_code(s->pc++); |
2c0262af FB |
4964 | gen_enter(s, val, level); |
4965 | } | |
4966 | break; | |
4967 | case 0xc9: /* leave */ | |
4968 | /* XXX: exception not precise (ESP is updated before potential exception) */ | |
14ce26e7 | 4969 | if (CODE64(s)) { |
57fec1fe FB |
4970 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP); |
4971 | gen_op_mov_reg_T0(OT_QUAD, R_ESP); | |
14ce26e7 | 4972 | } else if (s->ss32) { |
57fec1fe FB |
4973 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
4974 | gen_op_mov_reg_T0(OT_LONG, R_ESP); | |
2c0262af | 4975 | } else { |
57fec1fe FB |
4976 | gen_op_mov_TN_reg(OT_WORD, 0, R_EBP); |
4977 | gen_op_mov_reg_T0(OT_WORD, R_ESP); | |
2c0262af FB |
4978 | } |
4979 | gen_pop_T0(s); | |
14ce26e7 FB |
4980 | if (CODE64(s)) { |
4981 | ot = dflag ? OT_QUAD : OT_WORD; | |
4982 | } else { | |
4983 | ot = dflag + OT_WORD; | |
4984 | } | |
57fec1fe | 4985 | gen_op_mov_reg_T0(ot, R_EBP); |
2c0262af FB |
4986 | gen_pop_update(s); |
4987 | break; | |
4988 | case 0x06: /* push es */ | |
4989 | case 0x0e: /* push cs */ | |
4990 | case 0x16: /* push ss */ | |
4991 | case 0x1e: /* push ds */ | |
14ce26e7 FB |
4992 | if (CODE64(s)) |
4993 | goto illegal_op; | |
2c0262af FB |
4994 | gen_op_movl_T0_seg(b >> 3); |
4995 | gen_push_T0(s); | |
4996 | break; | |
4997 | case 0x1a0: /* push fs */ | |
4998 | case 0x1a8: /* push gs */ | |
4999 | gen_op_movl_T0_seg((b >> 3) & 7); | |
5000 | gen_push_T0(s); | |
5001 | break; | |
5002 | case 0x07: /* pop es */ | |
5003 | case 0x17: /* pop ss */ | |
5004 | case 0x1f: /* pop ds */ | |
14ce26e7 FB |
5005 | if (CODE64(s)) |
5006 | goto illegal_op; | |
2c0262af FB |
5007 | reg = b >> 3; |
5008 | gen_pop_T0(s); | |
5009 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5010 | gen_pop_update(s); | |
5011 | if (reg == R_SS) { | |
a2cc3b24 FB |
5012 | /* if reg == SS, inhibit interrupts/trace. */ |
5013 | /* If several instructions disable interrupts, only the | |
5014 | _first_ does it */ | |
5015 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
a7812ae4 | 5016 | gen_helper_set_inhibit_irq(); |
2c0262af FB |
5017 | s->tf = 0; |
5018 | } | |
5019 | if (s->is_jmp) { | |
14ce26e7 | 5020 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5021 | gen_eob(s); |
5022 | } | |
5023 | break; | |
5024 | case 0x1a1: /* pop fs */ | |
5025 | case 0x1a9: /* pop gs */ | |
5026 | gen_pop_T0(s); | |
5027 | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); | |
5028 | gen_pop_update(s); | |
5029 | if (s->is_jmp) { | |
14ce26e7 | 5030 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5031 | gen_eob(s); |
5032 | } | |
5033 | break; | |
5034 | ||
5035 | /**************************/ | |
5036 | /* mov */ | |
5037 | case 0x88: | |
5038 | case 0x89: /* mov Gv, Ev */ | |
5039 | if ((b & 1) == 0) | |
5040 | ot = OT_BYTE; | |
5041 | else | |
14ce26e7 | 5042 | ot = dflag + OT_WORD; |
61382a50 | 5043 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5044 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5045 | |
2c0262af | 5046 | /* generate a generic store */ |
14ce26e7 | 5047 | gen_ldst_modrm(s, modrm, ot, reg, 1); |
2c0262af FB |
5048 | break; |
5049 | case 0xc6: | |
5050 | case 0xc7: /* mov Ev, Iv */ | |
5051 | if ((b & 1) == 0) | |
5052 | ot = OT_BYTE; | |
5053 | else | |
14ce26e7 | 5054 | ot = dflag + OT_WORD; |
61382a50 | 5055 | modrm = ldub_code(s->pc++); |
2c0262af | 5056 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5057 | if (mod != 3) { |
5058 | s->rip_offset = insn_const_size(ot); | |
2c0262af | 5059 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 5060 | } |
2c0262af FB |
5061 | val = insn_get(s, ot); |
5062 | gen_op_movl_T0_im(val); | |
5063 | if (mod != 3) | |
57fec1fe | 5064 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 5065 | else |
57fec1fe | 5066 | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); |
2c0262af FB |
5067 | break; |
5068 | case 0x8a: | |
5069 | case 0x8b: /* mov Ev, Gv */ | |
5070 | if ((b & 1) == 0) | |
5071 | ot = OT_BYTE; | |
5072 | else | |
14ce26e7 | 5073 | ot = OT_WORD + dflag; |
61382a50 | 5074 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5075 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5076 | |
2c0262af | 5077 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5078 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
5079 | break; |
5080 | case 0x8e: /* mov seg, Gv */ | |
61382a50 | 5081 | modrm = ldub_code(s->pc++); |
2c0262af FB |
5082 | reg = (modrm >> 3) & 7; |
5083 | if (reg >= 6 || reg == R_CS) | |
5084 | goto illegal_op; | |
5085 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); | |
5086 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5087 | if (reg == R_SS) { | |
5088 | /* if reg == SS, inhibit interrupts/trace */ | |
a2cc3b24 FB |
5089 | /* If several instructions disable interrupts, only the |
5090 | _first_ does it */ | |
5091 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
a7812ae4 | 5092 | gen_helper_set_inhibit_irq(); |
2c0262af FB |
5093 | s->tf = 0; |
5094 | } | |
5095 | if (s->is_jmp) { | |
14ce26e7 | 5096 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5097 | gen_eob(s); |
5098 | } | |
5099 | break; | |
5100 | case 0x8c: /* mov Gv, seg */ | |
61382a50 | 5101 | modrm = ldub_code(s->pc++); |
2c0262af FB |
5102 | reg = (modrm >> 3) & 7; |
5103 | mod = (modrm >> 6) & 3; | |
5104 | if (reg >= 6) | |
5105 | goto illegal_op; | |
5106 | gen_op_movl_T0_seg(reg); | |
14ce26e7 FB |
5107 | if (mod == 3) |
5108 | ot = OT_WORD + dflag; | |
5109 | else | |
5110 | ot = OT_WORD; | |
2c0262af FB |
5111 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); |
5112 | break; | |
5113 | ||
5114 | case 0x1b6: /* movzbS Gv, Eb */ | |
5115 | case 0x1b7: /* movzwS Gv, Eb */ | |
5116 | case 0x1be: /* movsbS Gv, Eb */ | |
5117 | case 0x1bf: /* movswS Gv, Eb */ | |
5118 | { | |
5119 | int d_ot; | |
5120 | /* d_ot is the size of destination */ | |
5121 | d_ot = dflag + OT_WORD; | |
5122 | /* ot is the size of source */ | |
5123 | ot = (b & 1) + OT_BYTE; | |
61382a50 | 5124 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5125 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 5126 | mod = (modrm >> 6) & 3; |
14ce26e7 | 5127 | rm = (modrm & 7) | REX_B(s); |
3b46e624 | 5128 | |
2c0262af | 5129 | if (mod == 3) { |
57fec1fe | 5130 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
5131 | switch(ot | (b & 8)) { |
5132 | case OT_BYTE: | |
e108dd01 | 5133 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5134 | break; |
5135 | case OT_BYTE | 8: | |
e108dd01 | 5136 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5137 | break; |
5138 | case OT_WORD: | |
e108dd01 | 5139 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5140 | break; |
5141 | default: | |
5142 | case OT_WORD | 8: | |
e108dd01 | 5143 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5144 | break; |
5145 | } | |
57fec1fe | 5146 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5147 | } else { |
5148 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
5149 | if (b & 8) { | |
57fec1fe | 5150 | gen_op_lds_T0_A0(ot + s->mem_index); |
2c0262af | 5151 | } else { |
57fec1fe | 5152 | gen_op_ldu_T0_A0(ot + s->mem_index); |
2c0262af | 5153 | } |
57fec1fe | 5154 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5155 | } |
5156 | } | |
5157 | break; | |
5158 | ||
5159 | case 0x8d: /* lea */ | |
14ce26e7 | 5160 | ot = dflag + OT_WORD; |
61382a50 | 5161 | modrm = ldub_code(s->pc++); |
3a1d9b8b FB |
5162 | mod = (modrm >> 6) & 3; |
5163 | if (mod == 3) | |
5164 | goto illegal_op; | |
14ce26e7 | 5165 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5166 | /* we must ensure that no segment is added */ |
5167 | s->override = -1; | |
5168 | val = s->addseg; | |
5169 | s->addseg = 0; | |
5170 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
5171 | s->addseg = val; | |
57fec1fe | 5172 | gen_op_mov_reg_A0(ot - OT_WORD, reg); |
2c0262af | 5173 | break; |
3b46e624 | 5174 | |
2c0262af FB |
5175 | case 0xa0: /* mov EAX, Ov */ |
5176 | case 0xa1: | |
5177 | case 0xa2: /* mov Ov, EAX */ | |
5178 | case 0xa3: | |
2c0262af | 5179 | { |
14ce26e7 FB |
5180 | target_ulong offset_addr; |
5181 | ||
5182 | if ((b & 1) == 0) | |
5183 | ot = OT_BYTE; | |
5184 | else | |
5185 | ot = dflag + OT_WORD; | |
5186 | #ifdef TARGET_X86_64 | |
8f091a59 | 5187 | if (s->aflag == 2) { |
14ce26e7 FB |
5188 | offset_addr = ldq_code(s->pc); |
5189 | s->pc += 8; | |
57fec1fe | 5190 | gen_op_movq_A0_im(offset_addr); |
5fafdf24 | 5191 | } else |
14ce26e7 FB |
5192 | #endif |
5193 | { | |
5194 | if (s->aflag) { | |
5195 | offset_addr = insn_get(s, OT_LONG); | |
5196 | } else { | |
5197 | offset_addr = insn_get(s, OT_WORD); | |
5198 | } | |
5199 | gen_op_movl_A0_im(offset_addr); | |
5200 | } | |
664e0f19 | 5201 | gen_add_A0_ds_seg(s); |
14ce26e7 | 5202 | if ((b & 2) == 0) { |
57fec1fe FB |
5203 | gen_op_ld_T0_A0(ot + s->mem_index); |
5204 | gen_op_mov_reg_T0(ot, R_EAX); | |
14ce26e7 | 5205 | } else { |
57fec1fe FB |
5206 | gen_op_mov_TN_reg(ot, 0, R_EAX); |
5207 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af FB |
5208 | } |
5209 | } | |
2c0262af FB |
5210 | break; |
5211 | case 0xd7: /* xlat */ | |
14ce26e7 | 5212 | #ifdef TARGET_X86_64 |
8f091a59 | 5213 | if (s->aflag == 2) { |
57fec1fe | 5214 | gen_op_movq_A0_reg(R_EBX); |
bbf662ee FB |
5215 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
5216 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5217 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
5fafdf24 | 5218 | } else |
14ce26e7 FB |
5219 | #endif |
5220 | { | |
57fec1fe | 5221 | gen_op_movl_A0_reg(R_EBX); |
bbf662ee FB |
5222 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
5223 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5224 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
14ce26e7 FB |
5225 | if (s->aflag == 0) |
5226 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
5227 | else |
5228 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
14ce26e7 | 5229 | } |
664e0f19 | 5230 | gen_add_A0_ds_seg(s); |
57fec1fe FB |
5231 | gen_op_ldu_T0_A0(OT_BYTE + s->mem_index); |
5232 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
5233 | break; |
5234 | case 0xb0 ... 0xb7: /* mov R, Ib */ | |
5235 | val = insn_get(s, OT_BYTE); | |
5236 | gen_op_movl_T0_im(val); | |
57fec1fe | 5237 | gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s)); |
2c0262af FB |
5238 | break; |
5239 | case 0xb8 ... 0xbf: /* mov R, Iv */ | |
14ce26e7 FB |
5240 | #ifdef TARGET_X86_64 |
5241 | if (dflag == 2) { | |
5242 | uint64_t tmp; | |
5243 | /* 64 bit case */ | |
5244 | tmp = ldq_code(s->pc); | |
5245 | s->pc += 8; | |
5246 | reg = (b & 7) | REX_B(s); | |
5247 | gen_movtl_T0_im(tmp); | |
57fec1fe | 5248 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 5249 | } else |
14ce26e7 FB |
5250 | #endif |
5251 | { | |
5252 | ot = dflag ? OT_LONG : OT_WORD; | |
5253 | val = insn_get(s, ot); | |
5254 | reg = (b & 7) | REX_B(s); | |
5255 | gen_op_movl_T0_im(val); | |
57fec1fe | 5256 | gen_op_mov_reg_T0(ot, reg); |
14ce26e7 | 5257 | } |
2c0262af FB |
5258 | break; |
5259 | ||
5260 | case 0x91 ... 0x97: /* xchg R, EAX */ | |
14ce26e7 FB |
5261 | ot = dflag + OT_WORD; |
5262 | reg = (b & 7) | REX_B(s); | |
2c0262af FB |
5263 | rm = R_EAX; |
5264 | goto do_xchg_reg; | |
5265 | case 0x86: | |
5266 | case 0x87: /* xchg Ev, Gv */ | |
5267 | if ((b & 1) == 0) | |
5268 | ot = OT_BYTE; | |
5269 | else | |
14ce26e7 | 5270 | ot = dflag + OT_WORD; |
61382a50 | 5271 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5272 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5273 | mod = (modrm >> 6) & 3; |
5274 | if (mod == 3) { | |
14ce26e7 | 5275 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 5276 | do_xchg_reg: |
57fec1fe FB |
5277 | gen_op_mov_TN_reg(ot, 0, reg); |
5278 | gen_op_mov_TN_reg(ot, 1, rm); | |
5279 | gen_op_mov_reg_T0(ot, rm); | |
5280 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af FB |
5281 | } else { |
5282 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 5283 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af FB |
5284 | /* for xchg, lock is implicit */ |
5285 | if (!(prefixes & PREFIX_LOCK)) | |
a7812ae4 | 5286 | gen_helper_lock(); |
57fec1fe FB |
5287 | gen_op_ld_T1_A0(ot + s->mem_index); |
5288 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 5289 | if (!(prefixes & PREFIX_LOCK)) |
a7812ae4 | 5290 | gen_helper_unlock(); |
57fec1fe | 5291 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5292 | } |
5293 | break; | |
5294 | case 0xc4: /* les Gv */ | |
14ce26e7 FB |
5295 | if (CODE64(s)) |
5296 | goto illegal_op; | |
2c0262af FB |
5297 | op = R_ES; |
5298 | goto do_lxx; | |
5299 | case 0xc5: /* lds Gv */ | |
14ce26e7 FB |
5300 | if (CODE64(s)) |
5301 | goto illegal_op; | |
2c0262af FB |
5302 | op = R_DS; |
5303 | goto do_lxx; | |
5304 | case 0x1b2: /* lss Gv */ | |
5305 | op = R_SS; | |
5306 | goto do_lxx; | |
5307 | case 0x1b4: /* lfs Gv */ | |
5308 | op = R_FS; | |
5309 | goto do_lxx; | |
5310 | case 0x1b5: /* lgs Gv */ | |
5311 | op = R_GS; | |
5312 | do_lxx: | |
5313 | ot = dflag ? OT_LONG : OT_WORD; | |
61382a50 | 5314 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5315 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5316 | mod = (modrm >> 6) & 3; |
5317 | if (mod == 3) | |
5318 | goto illegal_op; | |
5319 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 5320 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 5321 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
2c0262af | 5322 | /* load the segment first to handle exceptions properly */ |
57fec1fe | 5323 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5324 | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
5325 | /* then put the data */ | |
57fec1fe | 5326 | gen_op_mov_reg_T1(ot, reg); |
2c0262af | 5327 | if (s->is_jmp) { |
14ce26e7 | 5328 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5329 | gen_eob(s); |
5330 | } | |
5331 | break; | |
3b46e624 | 5332 | |
2c0262af FB |
5333 | /************************/ |
5334 | /* shifts */ | |
5335 | case 0xc0: | |
5336 | case 0xc1: | |
5337 | /* shift Ev,Ib */ | |
5338 | shift = 2; | |
5339 | grp2: | |
5340 | { | |
5341 | if ((b & 1) == 0) | |
5342 | ot = OT_BYTE; | |
5343 | else | |
14ce26e7 | 5344 | ot = dflag + OT_WORD; |
3b46e624 | 5345 | |
61382a50 | 5346 | modrm = ldub_code(s->pc++); |
2c0262af | 5347 | mod = (modrm >> 6) & 3; |
2c0262af | 5348 | op = (modrm >> 3) & 7; |
3b46e624 | 5349 | |
2c0262af | 5350 | if (mod != 3) { |
14ce26e7 FB |
5351 | if (shift == 2) { |
5352 | s->rip_offset = 1; | |
5353 | } | |
2c0262af FB |
5354 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5355 | opreg = OR_TMP0; | |
5356 | } else { | |
14ce26e7 | 5357 | opreg = (modrm & 7) | REX_B(s); |
2c0262af FB |
5358 | } |
5359 | ||
5360 | /* simpler op */ | |
5361 | if (shift == 0) { | |
5362 | gen_shift(s, op, ot, opreg, OR_ECX); | |
5363 | } else { | |
5364 | if (shift == 2) { | |
61382a50 | 5365 | shift = ldub_code(s->pc++); |
2c0262af FB |
5366 | } |
5367 | gen_shifti(s, op, ot, opreg, shift); | |
5368 | } | |
5369 | } | |
5370 | break; | |
5371 | case 0xd0: | |
5372 | case 0xd1: | |
5373 | /* shift Ev,1 */ | |
5374 | shift = 1; | |
5375 | goto grp2; | |
5376 | case 0xd2: | |
5377 | case 0xd3: | |
5378 | /* shift Ev,cl */ | |
5379 | shift = 0; | |
5380 | goto grp2; | |
5381 | ||
5382 | case 0x1a4: /* shld imm */ | |
5383 | op = 0; | |
5384 | shift = 1; | |
5385 | goto do_shiftd; | |
5386 | case 0x1a5: /* shld cl */ | |
5387 | op = 0; | |
5388 | shift = 0; | |
5389 | goto do_shiftd; | |
5390 | case 0x1ac: /* shrd imm */ | |
5391 | op = 1; | |
5392 | shift = 1; | |
5393 | goto do_shiftd; | |
5394 | case 0x1ad: /* shrd cl */ | |
5395 | op = 1; | |
5396 | shift = 0; | |
5397 | do_shiftd: | |
14ce26e7 | 5398 | ot = dflag + OT_WORD; |
61382a50 | 5399 | modrm = ldub_code(s->pc++); |
2c0262af | 5400 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5401 | rm = (modrm & 7) | REX_B(s); |
5402 | reg = ((modrm >> 3) & 7) | rex_r; | |
2c0262af FB |
5403 | if (mod != 3) { |
5404 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
b6abf97d | 5405 | opreg = OR_TMP0; |
2c0262af | 5406 | } else { |
b6abf97d | 5407 | opreg = rm; |
2c0262af | 5408 | } |
57fec1fe | 5409 | gen_op_mov_TN_reg(ot, 1, reg); |
3b46e624 | 5410 | |
2c0262af | 5411 | if (shift) { |
61382a50 | 5412 | val = ldub_code(s->pc++); |
b6abf97d | 5413 | tcg_gen_movi_tl(cpu_T3, val); |
2c0262af | 5414 | } else { |
cc739bb0 | 5415 | tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]); |
2c0262af | 5416 | } |
b6abf97d | 5417 | gen_shiftd_rm_T1_T3(s, ot, opreg, op); |
2c0262af FB |
5418 | break; |
5419 | ||
5420 | /************************/ | |
5421 | /* floats */ | |
5fafdf24 | 5422 | case 0xd8 ... 0xdf: |
7eee2a50 FB |
5423 | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { |
5424 | /* if CR0.EM or CR0.TS are set, generate an FPU exception */ | |
5425 | /* XXX: what to do if illegal op ? */ | |
5426 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
5427 | break; | |
5428 | } | |
61382a50 | 5429 | modrm = ldub_code(s->pc++); |
2c0262af FB |
5430 | mod = (modrm >> 6) & 3; |
5431 | rm = modrm & 7; | |
5432 | op = ((b & 7) << 3) | ((modrm >> 3) & 7); | |
2c0262af FB |
5433 | if (mod != 3) { |
5434 | /* memory op */ | |
5435 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
5436 | switch(op) { | |
5437 | case 0x00 ... 0x07: /* fxxxs */ | |
5438 | case 0x10 ... 0x17: /* fixxxl */ | |
5439 | case 0x20 ... 0x27: /* fxxxl */ | |
5440 | case 0x30 ... 0x37: /* fixxx */ | |
5441 | { | |
5442 | int op1; | |
5443 | op1 = op & 7; | |
5444 | ||
5445 | switch(op >> 4) { | |
5446 | case 0: | |
ba7cd150 | 5447 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5448 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5449 | gen_helper_flds_FT0(cpu_tmp2_i32); |
2c0262af FB |
5450 | break; |
5451 | case 1: | |
ba7cd150 | 5452 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5453 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5454 | gen_helper_fildl_FT0(cpu_tmp2_i32); |
2c0262af FB |
5455 | break; |
5456 | case 2: | |
b6abf97d | 5457 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5458 | (s->mem_index >> 2) - 1); |
a7812ae4 | 5459 | gen_helper_fldl_FT0(cpu_tmp1_i64); |
2c0262af FB |
5460 | break; |
5461 | case 3: | |
5462 | default: | |
ba7cd150 | 5463 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5464 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5465 | gen_helper_fildl_FT0(cpu_tmp2_i32); |
2c0262af FB |
5466 | break; |
5467 | } | |
3b46e624 | 5468 | |
a7812ae4 | 5469 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5470 | if (op1 == 3) { |
5471 | /* fcomp needs pop */ | |
a7812ae4 | 5472 | gen_helper_fpop(); |
2c0262af FB |
5473 | } |
5474 | } | |
5475 | break; | |
5476 | case 0x08: /* flds */ | |
5477 | case 0x0a: /* fsts */ | |
5478 | case 0x0b: /* fstps */ | |
465e9838 FB |
5479 | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
5480 | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ | |
5481 | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ | |
2c0262af FB |
5482 | switch(op & 7) { |
5483 | case 0: | |
5484 | switch(op >> 4) { | |
5485 | case 0: | |
ba7cd150 | 5486 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5487 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5488 | gen_helper_flds_ST0(cpu_tmp2_i32); |
2c0262af FB |
5489 | break; |
5490 | case 1: | |
ba7cd150 | 5491 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5492 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5493 | gen_helper_fildl_ST0(cpu_tmp2_i32); |
2c0262af FB |
5494 | break; |
5495 | case 2: | |
b6abf97d | 5496 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5497 | (s->mem_index >> 2) - 1); |
a7812ae4 | 5498 | gen_helper_fldl_ST0(cpu_tmp1_i64); |
2c0262af FB |
5499 | break; |
5500 | case 3: | |
5501 | default: | |
ba7cd150 | 5502 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5503 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5504 | gen_helper_fildl_ST0(cpu_tmp2_i32); |
2c0262af FB |
5505 | break; |
5506 | } | |
5507 | break; | |
465e9838 | 5508 | case 1: |
19e6c4b8 | 5509 | /* XXX: the corresponding CPUID bit must be tested ! */ |
465e9838 FB |
5510 | switch(op >> 4) { |
5511 | case 1: | |
a7812ae4 | 5512 | gen_helper_fisttl_ST0(cpu_tmp2_i32); |
b6abf97d | 5513 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5514 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
465e9838 FB |
5515 | break; |
5516 | case 2: | |
a7812ae4 | 5517 | gen_helper_fisttll_ST0(cpu_tmp1_i64); |
b6abf97d | 5518 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5519 | (s->mem_index >> 2) - 1); |
465e9838 FB |
5520 | break; |
5521 | case 3: | |
5522 | default: | |
a7812ae4 | 5523 | gen_helper_fistt_ST0(cpu_tmp2_i32); |
b6abf97d | 5524 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5525 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
19e6c4b8 | 5526 | break; |
465e9838 | 5527 | } |
a7812ae4 | 5528 | gen_helper_fpop(); |
465e9838 | 5529 | break; |
2c0262af FB |
5530 | default: |
5531 | switch(op >> 4) { | |
5532 | case 0: | |
a7812ae4 | 5533 | gen_helper_fsts_ST0(cpu_tmp2_i32); |
b6abf97d | 5534 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5535 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5536 | break; |
5537 | case 1: | |
a7812ae4 | 5538 | gen_helper_fistl_ST0(cpu_tmp2_i32); |
b6abf97d | 5539 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5540 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5541 | break; |
5542 | case 2: | |
a7812ae4 | 5543 | gen_helper_fstl_ST0(cpu_tmp1_i64); |
b6abf97d | 5544 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5545 | (s->mem_index >> 2) - 1); |
2c0262af FB |
5546 | break; |
5547 | case 3: | |
5548 | default: | |
a7812ae4 | 5549 | gen_helper_fist_ST0(cpu_tmp2_i32); |
b6abf97d | 5550 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5551 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5552 | break; |
5553 | } | |
5554 | if ((op & 7) == 3) | |
a7812ae4 | 5555 | gen_helper_fpop(); |
2c0262af FB |
5556 | break; |
5557 | } | |
5558 | break; | |
5559 | case 0x0c: /* fldenv mem */ | |
19e6c4b8 FB |
5560 | if (s->cc_op != CC_OP_DYNAMIC) |
5561 | gen_op_set_cc_op(s->cc_op); | |
5562 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5563 | gen_helper_fldenv( |
19e6c4b8 | 5564 | cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5565 | break; |
5566 | case 0x0d: /* fldcw mem */ | |
19e6c4b8 | 5567 | gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5568 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5569 | gen_helper_fldcw(cpu_tmp2_i32); |
2c0262af FB |
5570 | break; |
5571 | case 0x0e: /* fnstenv mem */ | |
19e6c4b8 FB |
5572 | if (s->cc_op != CC_OP_DYNAMIC) |
5573 | gen_op_set_cc_op(s->cc_op); | |
5574 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5575 | gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5576 | break; |
5577 | case 0x0f: /* fnstcw mem */ | |
a7812ae4 | 5578 | gen_helper_fnstcw(cpu_tmp2_i32); |
b6abf97d | 5579 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5580 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5581 | break; |
5582 | case 0x1d: /* fldt mem */ | |
19e6c4b8 FB |
5583 | if (s->cc_op != CC_OP_DYNAMIC) |
5584 | gen_op_set_cc_op(s->cc_op); | |
5585 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5586 | gen_helper_fldt_ST0(cpu_A0); |
2c0262af FB |
5587 | break; |
5588 | case 0x1f: /* fstpt mem */ | |
19e6c4b8 FB |
5589 | if (s->cc_op != CC_OP_DYNAMIC) |
5590 | gen_op_set_cc_op(s->cc_op); | |
5591 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 PB |
5592 | gen_helper_fstt_ST0(cpu_A0); |
5593 | gen_helper_fpop(); | |
2c0262af FB |
5594 | break; |
5595 | case 0x2c: /* frstor mem */ | |
19e6c4b8 FB |
5596 | if (s->cc_op != CC_OP_DYNAMIC) |
5597 | gen_op_set_cc_op(s->cc_op); | |
5598 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5599 | gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5600 | break; |
5601 | case 0x2e: /* fnsave mem */ | |
19e6c4b8 FB |
5602 | if (s->cc_op != CC_OP_DYNAMIC) |
5603 | gen_op_set_cc_op(s->cc_op); | |
5604 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5605 | gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5606 | break; |
5607 | case 0x2f: /* fnstsw mem */ | |
a7812ae4 | 5608 | gen_helper_fnstsw(cpu_tmp2_i32); |
b6abf97d | 5609 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5610 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5611 | break; |
5612 | case 0x3c: /* fbld */ | |
19e6c4b8 FB |
5613 | if (s->cc_op != CC_OP_DYNAMIC) |
5614 | gen_op_set_cc_op(s->cc_op); | |
5615 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5616 | gen_helper_fbld_ST0(cpu_A0); |
2c0262af FB |
5617 | break; |
5618 | case 0x3e: /* fbstp */ | |
19e6c4b8 FB |
5619 | if (s->cc_op != CC_OP_DYNAMIC) |
5620 | gen_op_set_cc_op(s->cc_op); | |
5621 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 PB |
5622 | gen_helper_fbst_ST0(cpu_A0); |
5623 | gen_helper_fpop(); | |
2c0262af FB |
5624 | break; |
5625 | case 0x3d: /* fildll */ | |
b6abf97d | 5626 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5627 | (s->mem_index >> 2) - 1); |
a7812ae4 | 5628 | gen_helper_fildll_ST0(cpu_tmp1_i64); |
2c0262af FB |
5629 | break; |
5630 | case 0x3f: /* fistpll */ | |
a7812ae4 | 5631 | gen_helper_fistll_ST0(cpu_tmp1_i64); |
b6abf97d | 5632 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5633 | (s->mem_index >> 2) - 1); |
a7812ae4 | 5634 | gen_helper_fpop(); |
2c0262af FB |
5635 | break; |
5636 | default: | |
5637 | goto illegal_op; | |
5638 | } | |
5639 | } else { | |
5640 | /* register float ops */ | |
5641 | opreg = rm; | |
5642 | ||
5643 | switch(op) { | |
5644 | case 0x08: /* fld sti */ | |
a7812ae4 PB |
5645 | gen_helper_fpush(); |
5646 | gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7)); | |
2c0262af FB |
5647 | break; |
5648 | case 0x09: /* fxchg sti */ | |
c169c906 FB |
5649 | case 0x29: /* fxchg4 sti, undocumented op */ |
5650 | case 0x39: /* fxchg7 sti, undocumented op */ | |
a7812ae4 | 5651 | gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg)); |
2c0262af FB |
5652 | break; |
5653 | case 0x0a: /* grp d9/2 */ | |
5654 | switch(rm) { | |
5655 | case 0: /* fnop */ | |
023fe10d FB |
5656 | /* check exceptions (FreeBSD FPU probe) */ |
5657 | if (s->cc_op != CC_OP_DYNAMIC) | |
5658 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 5659 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 5660 | gen_helper_fwait(); |
2c0262af FB |
5661 | break; |
5662 | default: | |
5663 | goto illegal_op; | |
5664 | } | |
5665 | break; | |
5666 | case 0x0c: /* grp d9/4 */ | |
5667 | switch(rm) { | |
5668 | case 0: /* fchs */ | |
a7812ae4 | 5669 | gen_helper_fchs_ST0(); |
2c0262af FB |
5670 | break; |
5671 | case 1: /* fabs */ | |
a7812ae4 | 5672 | gen_helper_fabs_ST0(); |
2c0262af FB |
5673 | break; |
5674 | case 4: /* ftst */ | |
a7812ae4 PB |
5675 | gen_helper_fldz_FT0(); |
5676 | gen_helper_fcom_ST0_FT0(); | |
2c0262af FB |
5677 | break; |
5678 | case 5: /* fxam */ | |
a7812ae4 | 5679 | gen_helper_fxam_ST0(); |
2c0262af FB |
5680 | break; |
5681 | default: | |
5682 | goto illegal_op; | |
5683 | } | |
5684 | break; | |
5685 | case 0x0d: /* grp d9/5 */ | |
5686 | { | |
5687 | switch(rm) { | |
5688 | case 0: | |
a7812ae4 PB |
5689 | gen_helper_fpush(); |
5690 | gen_helper_fld1_ST0(); | |
2c0262af FB |
5691 | break; |
5692 | case 1: | |
a7812ae4 PB |
5693 | gen_helper_fpush(); |
5694 | gen_helper_fldl2t_ST0(); | |
2c0262af FB |
5695 | break; |
5696 | case 2: | |
a7812ae4 PB |
5697 | gen_helper_fpush(); |
5698 | gen_helper_fldl2e_ST0(); | |
2c0262af FB |
5699 | break; |
5700 | case 3: | |
a7812ae4 PB |
5701 | gen_helper_fpush(); |
5702 | gen_helper_fldpi_ST0(); | |
2c0262af FB |
5703 | break; |
5704 | case 4: | |
a7812ae4 PB |
5705 | gen_helper_fpush(); |
5706 | gen_helper_fldlg2_ST0(); | |
2c0262af FB |
5707 | break; |
5708 | case 5: | |
a7812ae4 PB |
5709 | gen_helper_fpush(); |
5710 | gen_helper_fldln2_ST0(); | |
2c0262af FB |
5711 | break; |
5712 | case 6: | |
a7812ae4 PB |
5713 | gen_helper_fpush(); |
5714 | gen_helper_fldz_ST0(); | |
2c0262af FB |
5715 | break; |
5716 | default: | |
5717 | goto illegal_op; | |
5718 | } | |
5719 | } | |
5720 | break; | |
5721 | case 0x0e: /* grp d9/6 */ | |
5722 | switch(rm) { | |
5723 | case 0: /* f2xm1 */ | |
a7812ae4 | 5724 | gen_helper_f2xm1(); |
2c0262af FB |
5725 | break; |
5726 | case 1: /* fyl2x */ | |
a7812ae4 | 5727 | gen_helper_fyl2x(); |
2c0262af FB |
5728 | break; |
5729 | case 2: /* fptan */ | |
a7812ae4 | 5730 | gen_helper_fptan(); |
2c0262af FB |
5731 | break; |
5732 | case 3: /* fpatan */ | |
a7812ae4 | 5733 | gen_helper_fpatan(); |
2c0262af FB |
5734 | break; |
5735 | case 4: /* fxtract */ | |
a7812ae4 | 5736 | gen_helper_fxtract(); |
2c0262af FB |
5737 | break; |
5738 | case 5: /* fprem1 */ | |
a7812ae4 | 5739 | gen_helper_fprem1(); |
2c0262af FB |
5740 | break; |
5741 | case 6: /* fdecstp */ | |
a7812ae4 | 5742 | gen_helper_fdecstp(); |
2c0262af FB |
5743 | break; |
5744 | default: | |
5745 | case 7: /* fincstp */ | |
a7812ae4 | 5746 | gen_helper_fincstp(); |
2c0262af FB |
5747 | break; |
5748 | } | |
5749 | break; | |
5750 | case 0x0f: /* grp d9/7 */ | |
5751 | switch(rm) { | |
5752 | case 0: /* fprem */ | |
a7812ae4 | 5753 | gen_helper_fprem(); |
2c0262af FB |
5754 | break; |
5755 | case 1: /* fyl2xp1 */ | |
a7812ae4 | 5756 | gen_helper_fyl2xp1(); |
2c0262af FB |
5757 | break; |
5758 | case 2: /* fsqrt */ | |
a7812ae4 | 5759 | gen_helper_fsqrt(); |
2c0262af FB |
5760 | break; |
5761 | case 3: /* fsincos */ | |
a7812ae4 | 5762 | gen_helper_fsincos(); |
2c0262af FB |
5763 | break; |
5764 | case 5: /* fscale */ | |
a7812ae4 | 5765 | gen_helper_fscale(); |
2c0262af FB |
5766 | break; |
5767 | case 4: /* frndint */ | |
a7812ae4 | 5768 | gen_helper_frndint(); |
2c0262af FB |
5769 | break; |
5770 | case 6: /* fsin */ | |
a7812ae4 | 5771 | gen_helper_fsin(); |
2c0262af FB |
5772 | break; |
5773 | default: | |
5774 | case 7: /* fcos */ | |
a7812ae4 | 5775 | gen_helper_fcos(); |
2c0262af FB |
5776 | break; |
5777 | } | |
5778 | break; | |
5779 | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ | |
5780 | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ | |
5781 | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ | |
5782 | { | |
5783 | int op1; | |
3b46e624 | 5784 | |
2c0262af FB |
5785 | op1 = op & 7; |
5786 | if (op >= 0x20) { | |
a7812ae4 | 5787 | gen_helper_fp_arith_STN_ST0(op1, opreg); |
2c0262af | 5788 | if (op >= 0x30) |
a7812ae4 | 5789 | gen_helper_fpop(); |
2c0262af | 5790 | } else { |
a7812ae4 PB |
5791 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5792 | gen_helper_fp_arith_ST0_FT0(op1); | |
2c0262af FB |
5793 | } |
5794 | } | |
5795 | break; | |
5796 | case 0x02: /* fcom */ | |
c169c906 | 5797 | case 0x22: /* fcom2, undocumented op */ |
a7812ae4 PB |
5798 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5799 | gen_helper_fcom_ST0_FT0(); | |
2c0262af FB |
5800 | break; |
5801 | case 0x03: /* fcomp */ | |
c169c906 FB |
5802 | case 0x23: /* fcomp3, undocumented op */ |
5803 | case 0x32: /* fcomp5, undocumented op */ | |
a7812ae4 PB |
5804 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5805 | gen_helper_fcom_ST0_FT0(); | |
5806 | gen_helper_fpop(); | |
2c0262af FB |
5807 | break; |
5808 | case 0x15: /* da/5 */ | |
5809 | switch(rm) { | |
5810 | case 1: /* fucompp */ | |
a7812ae4 PB |
5811 | gen_helper_fmov_FT0_STN(tcg_const_i32(1)); |
5812 | gen_helper_fucom_ST0_FT0(); | |
5813 | gen_helper_fpop(); | |
5814 | gen_helper_fpop(); | |
2c0262af FB |
5815 | break; |
5816 | default: | |
5817 | goto illegal_op; | |
5818 | } | |
5819 | break; | |
5820 | case 0x1c: | |
5821 | switch(rm) { | |
5822 | case 0: /* feni (287 only, just do nop here) */ | |
5823 | break; | |
5824 | case 1: /* fdisi (287 only, just do nop here) */ | |
5825 | break; | |
5826 | case 2: /* fclex */ | |
a7812ae4 | 5827 | gen_helper_fclex(); |
2c0262af FB |
5828 | break; |
5829 | case 3: /* fninit */ | |
a7812ae4 | 5830 | gen_helper_fninit(); |
2c0262af FB |
5831 | break; |
5832 | case 4: /* fsetpm (287 only, just do nop here) */ | |
5833 | break; | |
5834 | default: | |
5835 | goto illegal_op; | |
5836 | } | |
5837 | break; | |
5838 | case 0x1d: /* fucomi */ | |
5839 | if (s->cc_op != CC_OP_DYNAMIC) | |
5840 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 PB |
5841 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5842 | gen_helper_fucomi_ST0_FT0(); | |
2c0262af FB |
5843 | s->cc_op = CC_OP_EFLAGS; |
5844 | break; | |
5845 | case 0x1e: /* fcomi */ | |
5846 | if (s->cc_op != CC_OP_DYNAMIC) | |
5847 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 PB |
5848 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5849 | gen_helper_fcomi_ST0_FT0(); | |
2c0262af FB |
5850 | s->cc_op = CC_OP_EFLAGS; |
5851 | break; | |
658c8bda | 5852 | case 0x28: /* ffree sti */ |
a7812ae4 | 5853 | gen_helper_ffree_STN(tcg_const_i32(opreg)); |
5fafdf24 | 5854 | break; |
2c0262af | 5855 | case 0x2a: /* fst sti */ |
a7812ae4 | 5856 | gen_helper_fmov_STN_ST0(tcg_const_i32(opreg)); |
2c0262af FB |
5857 | break; |
5858 | case 0x2b: /* fstp sti */ | |
c169c906 FB |
5859 | case 0x0b: /* fstp1 sti, undocumented op */ |
5860 | case 0x3a: /* fstp8 sti, undocumented op */ | |
5861 | case 0x3b: /* fstp9 sti, undocumented op */ | |
a7812ae4 PB |
5862 | gen_helper_fmov_STN_ST0(tcg_const_i32(opreg)); |
5863 | gen_helper_fpop(); | |
2c0262af FB |
5864 | break; |
5865 | case 0x2c: /* fucom st(i) */ | |
a7812ae4 PB |
5866 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5867 | gen_helper_fucom_ST0_FT0(); | |
2c0262af FB |
5868 | break; |
5869 | case 0x2d: /* fucomp st(i) */ | |
a7812ae4 PB |
5870 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5871 | gen_helper_fucom_ST0_FT0(); | |
5872 | gen_helper_fpop(); | |
2c0262af FB |
5873 | break; |
5874 | case 0x33: /* de/3 */ | |
5875 | switch(rm) { | |
5876 | case 1: /* fcompp */ | |
a7812ae4 PB |
5877 | gen_helper_fmov_FT0_STN(tcg_const_i32(1)); |
5878 | gen_helper_fcom_ST0_FT0(); | |
5879 | gen_helper_fpop(); | |
5880 | gen_helper_fpop(); | |
2c0262af FB |
5881 | break; |
5882 | default: | |
5883 | goto illegal_op; | |
5884 | } | |
5885 | break; | |
c169c906 | 5886 | case 0x38: /* ffreep sti, undocumented op */ |
a7812ae4 PB |
5887 | gen_helper_ffree_STN(tcg_const_i32(opreg)); |
5888 | gen_helper_fpop(); | |
c169c906 | 5889 | break; |
2c0262af FB |
5890 | case 0x3c: /* df/4 */ |
5891 | switch(rm) { | |
5892 | case 0: | |
a7812ae4 | 5893 | gen_helper_fnstsw(cpu_tmp2_i32); |
b6abf97d | 5894 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5895 | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
2c0262af FB |
5896 | break; |
5897 | default: | |
5898 | goto illegal_op; | |
5899 | } | |
5900 | break; | |
5901 | case 0x3d: /* fucomip */ | |
5902 | if (s->cc_op != CC_OP_DYNAMIC) | |
5903 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 PB |
5904 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5905 | gen_helper_fucomi_ST0_FT0(); | |
5906 | gen_helper_fpop(); | |
2c0262af FB |
5907 | s->cc_op = CC_OP_EFLAGS; |
5908 | break; | |
5909 | case 0x3e: /* fcomip */ | |
5910 | if (s->cc_op != CC_OP_DYNAMIC) | |
5911 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 PB |
5912 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5913 | gen_helper_fcomi_ST0_FT0(); | |
5914 | gen_helper_fpop(); | |
2c0262af FB |
5915 | s->cc_op = CC_OP_EFLAGS; |
5916 | break; | |
a2cc3b24 FB |
5917 | case 0x10 ... 0x13: /* fcmovxx */ |
5918 | case 0x18 ... 0x1b: | |
5919 | { | |
19e6c4b8 | 5920 | int op1, l1; |
d70040bc | 5921 | static const uint8_t fcmov_cc[8] = { |
a2cc3b24 FB |
5922 | (JCC_B << 1), |
5923 | (JCC_Z << 1), | |
5924 | (JCC_BE << 1), | |
5925 | (JCC_P << 1), | |
5926 | }; | |
1e4840bf | 5927 | op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); |
19e6c4b8 | 5928 | l1 = gen_new_label(); |
1e4840bf | 5929 | gen_jcc1(s, s->cc_op, op1, l1); |
a7812ae4 | 5930 | gen_helper_fmov_ST0_STN(tcg_const_i32(opreg)); |
19e6c4b8 | 5931 | gen_set_label(l1); |
a2cc3b24 FB |
5932 | } |
5933 | break; | |
2c0262af FB |
5934 | default: |
5935 | goto illegal_op; | |
5936 | } | |
5937 | } | |
5938 | break; | |
5939 | /************************/ | |
5940 | /* string ops */ | |
5941 | ||
5942 | case 0xa4: /* movsS */ | |
5943 | case 0xa5: | |
5944 | if ((b & 1) == 0) | |
5945 | ot = OT_BYTE; | |
5946 | else | |
14ce26e7 | 5947 | ot = dflag + OT_WORD; |
2c0262af FB |
5948 | |
5949 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
5950 | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
5951 | } else { | |
5952 | gen_movs(s, ot); | |
5953 | } | |
5954 | break; | |
3b46e624 | 5955 | |
2c0262af FB |
5956 | case 0xaa: /* stosS */ |
5957 | case 0xab: | |
5958 | if ((b & 1) == 0) | |
5959 | ot = OT_BYTE; | |
5960 | else | |
14ce26e7 | 5961 | ot = dflag + OT_WORD; |
2c0262af FB |
5962 | |
5963 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
5964 | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
5965 | } else { | |
5966 | gen_stos(s, ot); | |
5967 | } | |
5968 | break; | |
5969 | case 0xac: /* lodsS */ | |
5970 | case 0xad: | |
5971 | if ((b & 1) == 0) | |
5972 | ot = OT_BYTE; | |
5973 | else | |
14ce26e7 | 5974 | ot = dflag + OT_WORD; |
2c0262af FB |
5975 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
5976 | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
5977 | } else { | |
5978 | gen_lods(s, ot); | |
5979 | } | |
5980 | break; | |
5981 | case 0xae: /* scasS */ | |
5982 | case 0xaf: | |
5983 | if ((b & 1) == 0) | |
5984 | ot = OT_BYTE; | |
5985 | else | |
14ce26e7 | 5986 | ot = dflag + OT_WORD; |
2c0262af FB |
5987 | if (prefixes & PREFIX_REPNZ) { |
5988 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
5989 | } else if (prefixes & PREFIX_REPZ) { | |
5990 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
5991 | } else { | |
5992 | gen_scas(s, ot); | |
5993 | s->cc_op = CC_OP_SUBB + ot; | |
5994 | } | |
5995 | break; | |
5996 | ||
5997 | case 0xa6: /* cmpsS */ | |
5998 | case 0xa7: | |
5999 | if ((b & 1) == 0) | |
6000 | ot = OT_BYTE; | |
6001 | else | |
14ce26e7 | 6002 | ot = dflag + OT_WORD; |
2c0262af FB |
6003 | if (prefixes & PREFIX_REPNZ) { |
6004 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6005 | } else if (prefixes & PREFIX_REPZ) { | |
6006 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6007 | } else { | |
6008 | gen_cmps(s, ot); | |
6009 | s->cc_op = CC_OP_SUBB + ot; | |
6010 | } | |
6011 | break; | |
6012 | case 0x6c: /* insS */ | |
6013 | case 0x6d: | |
f115e911 FB |
6014 | if ((b & 1) == 0) |
6015 | ot = OT_BYTE; | |
6016 | else | |
6017 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6018 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6019 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6020 | gen_check_io(s, ot, pc_start - s->cs_base, |
6021 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6022 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6023 | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6024 | } else { |
f115e911 | 6025 | gen_ins(s, ot); |
2e70f6ef PB |
6026 | if (use_icount) { |
6027 | gen_jmp(s, s->pc - s->cs_base); | |
6028 | } | |
2c0262af FB |
6029 | } |
6030 | break; | |
6031 | case 0x6e: /* outsS */ | |
6032 | case 0x6f: | |
f115e911 FB |
6033 | if ((b & 1) == 0) |
6034 | ot = OT_BYTE; | |
6035 | else | |
6036 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6037 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6038 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6039 | gen_check_io(s, ot, pc_start - s->cs_base, |
6040 | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6041 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6042 | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6043 | } else { |
f115e911 | 6044 | gen_outs(s, ot); |
2e70f6ef PB |
6045 | if (use_icount) { |
6046 | gen_jmp(s, s->pc - s->cs_base); | |
6047 | } | |
2c0262af FB |
6048 | } |
6049 | break; | |
6050 | ||
6051 | /************************/ | |
6052 | /* port I/O */ | |
0573fbfc | 6053 | |
2c0262af FB |
6054 | case 0xe4: |
6055 | case 0xe5: | |
f115e911 FB |
6056 | if ((b & 1) == 0) |
6057 | ot = OT_BYTE; | |
6058 | else | |
6059 | ot = dflag ? OT_LONG : OT_WORD; | |
6060 | val = ldub_code(s->pc++); | |
6061 | gen_op_movl_T0_im(val); | |
b8b6a50b FB |
6062 | gen_check_io(s, ot, pc_start - s->cs_base, |
6063 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6064 | if (use_icount) |
6065 | gen_io_start(); | |
b6abf97d | 6066 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6067 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6068 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6069 | if (use_icount) { |
6070 | gen_io_end(); | |
6071 | gen_jmp(s, s->pc - s->cs_base); | |
6072 | } | |
2c0262af FB |
6073 | break; |
6074 | case 0xe6: | |
6075 | case 0xe7: | |
f115e911 FB |
6076 | if ((b & 1) == 0) |
6077 | ot = OT_BYTE; | |
6078 | else | |
6079 | ot = dflag ? OT_LONG : OT_WORD; | |
6080 | val = ldub_code(s->pc++); | |
6081 | gen_op_movl_T0_im(val); | |
b8b6a50b FB |
6082 | gen_check_io(s, ot, pc_start - s->cs_base, |
6083 | svm_is_rep(prefixes)); | |
57fec1fe | 6084 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6085 | |
2e70f6ef PB |
6086 | if (use_icount) |
6087 | gen_io_start(); | |
b6abf97d FB |
6088 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
6089 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
6090 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); | |
a7812ae4 | 6091 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6092 | if (use_icount) { |
6093 | gen_io_end(); | |
6094 | gen_jmp(s, s->pc - s->cs_base); | |
6095 | } | |
2c0262af FB |
6096 | break; |
6097 | case 0xec: | |
6098 | case 0xed: | |
f115e911 FB |
6099 | if ((b & 1) == 0) |
6100 | ot = OT_BYTE; | |
6101 | else | |
6102 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6103 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6104 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6105 | gen_check_io(s, ot, pc_start - s->cs_base, |
6106 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6107 | if (use_icount) |
6108 | gen_io_start(); | |
b6abf97d | 6109 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6110 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6111 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6112 | if (use_icount) { |
6113 | gen_io_end(); | |
6114 | gen_jmp(s, s->pc - s->cs_base); | |
6115 | } | |
2c0262af FB |
6116 | break; |
6117 | case 0xee: | |
6118 | case 0xef: | |
f115e911 FB |
6119 | if ((b & 1) == 0) |
6120 | ot = OT_BYTE; | |
6121 | else | |
6122 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6123 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6124 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6125 | gen_check_io(s, ot, pc_start - s->cs_base, |
6126 | svm_is_rep(prefixes)); | |
57fec1fe | 6127 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6128 | |
2e70f6ef PB |
6129 | if (use_icount) |
6130 | gen_io_start(); | |
b6abf97d FB |
6131 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
6132 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
6133 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); | |
a7812ae4 | 6134 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6135 | if (use_icount) { |
6136 | gen_io_end(); | |
6137 | gen_jmp(s, s->pc - s->cs_base); | |
6138 | } | |
2c0262af FB |
6139 | break; |
6140 | ||
6141 | /************************/ | |
6142 | /* control */ | |
6143 | case 0xc2: /* ret im */ | |
61382a50 | 6144 | val = ldsw_code(s->pc); |
2c0262af FB |
6145 | s->pc += 2; |
6146 | gen_pop_T0(s); | |
8f091a59 FB |
6147 | if (CODE64(s) && s->dflag) |
6148 | s->dflag = 2; | |
2c0262af FB |
6149 | gen_stack_update(s, val + (2 << s->dflag)); |
6150 | if (s->dflag == 0) | |
6151 | gen_op_andl_T0_ffff(); | |
6152 | gen_op_jmp_T0(); | |
6153 | gen_eob(s); | |
6154 | break; | |
6155 | case 0xc3: /* ret */ | |
6156 | gen_pop_T0(s); | |
6157 | gen_pop_update(s); | |
6158 | if (s->dflag == 0) | |
6159 | gen_op_andl_T0_ffff(); | |
6160 | gen_op_jmp_T0(); | |
6161 | gen_eob(s); | |
6162 | break; | |
6163 | case 0xca: /* lret im */ | |
61382a50 | 6164 | val = ldsw_code(s->pc); |
2c0262af FB |
6165 | s->pc += 2; |
6166 | do_lret: | |
6167 | if (s->pe && !s->vm86) { | |
6168 | if (s->cc_op != CC_OP_DYNAMIC) | |
6169 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6170 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 PB |
6171 | gen_helper_lret_protected(tcg_const_i32(s->dflag), |
6172 | tcg_const_i32(val)); | |
2c0262af FB |
6173 | } else { |
6174 | gen_stack_A0(s); | |
6175 | /* pop offset */ | |
57fec1fe | 6176 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
2c0262af FB |
6177 | if (s->dflag == 0) |
6178 | gen_op_andl_T0_ffff(); | |
6179 | /* NOTE: keeping EIP updated is not a problem in case of | |
6180 | exception */ | |
6181 | gen_op_jmp_T0(); | |
6182 | /* pop selector */ | |
6183 | gen_op_addl_A0_im(2 << s->dflag); | |
57fec1fe | 6184 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
3bd7da9e | 6185 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
6186 | /* add stack offset */ |
6187 | gen_stack_update(s, val + (4 << s->dflag)); | |
6188 | } | |
6189 | gen_eob(s); | |
6190 | break; | |
6191 | case 0xcb: /* lret */ | |
6192 | val = 0; | |
6193 | goto do_lret; | |
6194 | case 0xcf: /* iret */ | |
872929aa | 6195 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); |
2c0262af FB |
6196 | if (!s->pe) { |
6197 | /* real mode */ | |
a7812ae4 | 6198 | gen_helper_iret_real(tcg_const_i32(s->dflag)); |
2c0262af | 6199 | s->cc_op = CC_OP_EFLAGS; |
f115e911 FB |
6200 | } else if (s->vm86) { |
6201 | if (s->iopl != 3) { | |
6202 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6203 | } else { | |
a7812ae4 | 6204 | gen_helper_iret_real(tcg_const_i32(s->dflag)); |
f115e911 FB |
6205 | s->cc_op = CC_OP_EFLAGS; |
6206 | } | |
2c0262af FB |
6207 | } else { |
6208 | if (s->cc_op != CC_OP_DYNAMIC) | |
6209 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6210 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 PB |
6211 | gen_helper_iret_protected(tcg_const_i32(s->dflag), |
6212 | tcg_const_i32(s->pc - s->cs_base)); | |
2c0262af FB |
6213 | s->cc_op = CC_OP_EFLAGS; |
6214 | } | |
6215 | gen_eob(s); | |
6216 | break; | |
6217 | case 0xe8: /* call im */ | |
6218 | { | |
14ce26e7 FB |
6219 | if (dflag) |
6220 | tval = (int32_t)insn_get(s, OT_LONG); | |
6221 | else | |
6222 | tval = (int16_t)insn_get(s, OT_WORD); | |
2c0262af | 6223 | next_eip = s->pc - s->cs_base; |
14ce26e7 | 6224 | tval += next_eip; |
2c0262af | 6225 | if (s->dflag == 0) |
14ce26e7 FB |
6226 | tval &= 0xffff; |
6227 | gen_movtl_T0_im(next_eip); | |
2c0262af | 6228 | gen_push_T0(s); |
14ce26e7 | 6229 | gen_jmp(s, tval); |
2c0262af FB |
6230 | } |
6231 | break; | |
6232 | case 0x9a: /* lcall im */ | |
6233 | { | |
6234 | unsigned int selector, offset; | |
3b46e624 | 6235 | |
14ce26e7 FB |
6236 | if (CODE64(s)) |
6237 | goto illegal_op; | |
2c0262af FB |
6238 | ot = dflag ? OT_LONG : OT_WORD; |
6239 | offset = insn_get(s, ot); | |
6240 | selector = insn_get(s, OT_WORD); | |
3b46e624 | 6241 | |
2c0262af | 6242 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6243 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6244 | } |
6245 | goto do_lcall; | |
ecada8a2 | 6246 | case 0xe9: /* jmp im */ |
14ce26e7 FB |
6247 | if (dflag) |
6248 | tval = (int32_t)insn_get(s, OT_LONG); | |
6249 | else | |
6250 | tval = (int16_t)insn_get(s, OT_WORD); | |
6251 | tval += s->pc - s->cs_base; | |
2c0262af | 6252 | if (s->dflag == 0) |
14ce26e7 | 6253 | tval &= 0xffff; |
32938e12 AJ |
6254 | else if(!CODE64(s)) |
6255 | tval &= 0xffffffff; | |
14ce26e7 | 6256 | gen_jmp(s, tval); |
2c0262af FB |
6257 | break; |
6258 | case 0xea: /* ljmp im */ | |
6259 | { | |
6260 | unsigned int selector, offset; | |
6261 | ||
14ce26e7 FB |
6262 | if (CODE64(s)) |
6263 | goto illegal_op; | |
2c0262af FB |
6264 | ot = dflag ? OT_LONG : OT_WORD; |
6265 | offset = insn_get(s, ot); | |
6266 | selector = insn_get(s, OT_WORD); | |
3b46e624 | 6267 | |
2c0262af | 6268 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6269 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6270 | } |
6271 | goto do_ljmp; | |
6272 | case 0xeb: /* jmp Jb */ | |
14ce26e7 FB |
6273 | tval = (int8_t)insn_get(s, OT_BYTE); |
6274 | tval += s->pc - s->cs_base; | |
2c0262af | 6275 | if (s->dflag == 0) |
14ce26e7 FB |
6276 | tval &= 0xffff; |
6277 | gen_jmp(s, tval); | |
2c0262af FB |
6278 | break; |
6279 | case 0x70 ... 0x7f: /* jcc Jb */ | |
14ce26e7 | 6280 | tval = (int8_t)insn_get(s, OT_BYTE); |
2c0262af FB |
6281 | goto do_jcc; |
6282 | case 0x180 ... 0x18f: /* jcc Jv */ | |
6283 | if (dflag) { | |
14ce26e7 | 6284 | tval = (int32_t)insn_get(s, OT_LONG); |
2c0262af | 6285 | } else { |
5fafdf24 | 6286 | tval = (int16_t)insn_get(s, OT_WORD); |
2c0262af FB |
6287 | } |
6288 | do_jcc: | |
6289 | next_eip = s->pc - s->cs_base; | |
14ce26e7 | 6290 | tval += next_eip; |
2c0262af | 6291 | if (s->dflag == 0) |
14ce26e7 FB |
6292 | tval &= 0xffff; |
6293 | gen_jcc(s, b, tval, next_eip); | |
2c0262af FB |
6294 | break; |
6295 | ||
6296 | case 0x190 ... 0x19f: /* setcc Gv */ | |
61382a50 | 6297 | modrm = ldub_code(s->pc++); |
2c0262af FB |
6298 | gen_setcc(s, b); |
6299 | gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1); | |
6300 | break; | |
6301 | case 0x140 ... 0x14f: /* cmov Gv, Ev */ | |
8e1c85e3 FB |
6302 | { |
6303 | int l1; | |
1e4840bf FB |
6304 | TCGv t0; |
6305 | ||
8e1c85e3 FB |
6306 | ot = dflag + OT_WORD; |
6307 | modrm = ldub_code(s->pc++); | |
6308 | reg = ((modrm >> 3) & 7) | rex_r; | |
6309 | mod = (modrm >> 6) & 3; | |
a7812ae4 | 6310 | t0 = tcg_temp_local_new(); |
8e1c85e3 FB |
6311 | if (mod != 3) { |
6312 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
1e4840bf | 6313 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
8e1c85e3 FB |
6314 | } else { |
6315 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 6316 | gen_op_mov_v_reg(ot, t0, rm); |
8e1c85e3 | 6317 | } |
8e1c85e3 FB |
6318 | #ifdef TARGET_X86_64 |
6319 | if (ot == OT_LONG) { | |
6320 | /* XXX: specific Intel behaviour ? */ | |
6321 | l1 = gen_new_label(); | |
6322 | gen_jcc1(s, s->cc_op, b ^ 1, l1); | |
cc739bb0 | 6323 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
8e1c85e3 | 6324 | gen_set_label(l1); |
cc739bb0 | 6325 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]); |
8e1c85e3 FB |
6326 | } else |
6327 | #endif | |
6328 | { | |
6329 | l1 = gen_new_label(); | |
6330 | gen_jcc1(s, s->cc_op, b ^ 1, l1); | |
1e4840bf | 6331 | gen_op_mov_reg_v(ot, reg, t0); |
8e1c85e3 FB |
6332 | gen_set_label(l1); |
6333 | } | |
1e4840bf | 6334 | tcg_temp_free(t0); |
2c0262af | 6335 | } |
2c0262af | 6336 | break; |
3b46e624 | 6337 | |
2c0262af FB |
6338 | /************************/ |
6339 | /* flags */ | |
6340 | case 0x9c: /* pushf */ | |
872929aa | 6341 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); |
2c0262af FB |
6342 | if (s->vm86 && s->iopl != 3) { |
6343 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6344 | } else { | |
6345 | if (s->cc_op != CC_OP_DYNAMIC) | |
6346 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6347 | gen_helper_read_eflags(cpu_T[0]); |
2c0262af FB |
6348 | gen_push_T0(s); |
6349 | } | |
6350 | break; | |
6351 | case 0x9d: /* popf */ | |
872929aa | 6352 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); |
2c0262af FB |
6353 | if (s->vm86 && s->iopl != 3) { |
6354 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6355 | } else { | |
6356 | gen_pop_T0(s); | |
6357 | if (s->cpl == 0) { | |
6358 | if (s->dflag) { | |
a7812ae4 | 6359 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6360 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK))); |
2c0262af | 6361 | } else { |
a7812ae4 | 6362 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6363 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff)); |
2c0262af FB |
6364 | } |
6365 | } else { | |
4136f33c FB |
6366 | if (s->cpl <= s->iopl) { |
6367 | if (s->dflag) { | |
a7812ae4 | 6368 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6369 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK))); |
4136f33c | 6370 | } else { |
a7812ae4 | 6371 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6372 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff)); |
4136f33c | 6373 | } |
2c0262af | 6374 | } else { |
4136f33c | 6375 | if (s->dflag) { |
a7812ae4 | 6376 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6377 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK))); |
4136f33c | 6378 | } else { |
a7812ae4 | 6379 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6380 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff)); |
4136f33c | 6381 | } |
2c0262af FB |
6382 | } |
6383 | } | |
6384 | gen_pop_update(s); | |
6385 | s->cc_op = CC_OP_EFLAGS; | |
6386 | /* abort translation because TF flag may change */ | |
14ce26e7 | 6387 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6388 | gen_eob(s); |
6389 | } | |
6390 | break; | |
6391 | case 0x9e: /* sahf */ | |
12e26b75 | 6392 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6393 | goto illegal_op; |
57fec1fe | 6394 | gen_op_mov_TN_reg(OT_BYTE, 0, R_AH); |
2c0262af FB |
6395 | if (s->cc_op != CC_OP_DYNAMIC) |
6396 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6397 | gen_compute_eflags(cpu_cc_src); |
6398 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); | |
6399 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); | |
6400 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); | |
2c0262af FB |
6401 | s->cc_op = CC_OP_EFLAGS; |
6402 | break; | |
6403 | case 0x9f: /* lahf */ | |
12e26b75 | 6404 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6405 | goto illegal_op; |
2c0262af FB |
6406 | if (s->cc_op != CC_OP_DYNAMIC) |
6407 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6408 | gen_compute_eflags(cpu_T[0]); |
6409 | /* Note: gen_compute_eflags() only gives the condition codes */ | |
6410 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02); | |
57fec1fe | 6411 | gen_op_mov_reg_T0(OT_BYTE, R_AH); |
2c0262af FB |
6412 | break; |
6413 | case 0xf5: /* cmc */ | |
6414 | if (s->cc_op != CC_OP_DYNAMIC) | |
6415 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6416 | gen_compute_eflags(cpu_cc_src); |
6417 | tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); | |
2c0262af FB |
6418 | s->cc_op = CC_OP_EFLAGS; |
6419 | break; | |
6420 | case 0xf8: /* clc */ | |
6421 | if (s->cc_op != CC_OP_DYNAMIC) | |
6422 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6423 | gen_compute_eflags(cpu_cc_src); |
6424 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); | |
2c0262af FB |
6425 | s->cc_op = CC_OP_EFLAGS; |
6426 | break; | |
6427 | case 0xf9: /* stc */ | |
6428 | if (s->cc_op != CC_OP_DYNAMIC) | |
6429 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6430 | gen_compute_eflags(cpu_cc_src); |
6431 | tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); | |
2c0262af FB |
6432 | s->cc_op = CC_OP_EFLAGS; |
6433 | break; | |
6434 | case 0xfc: /* cld */ | |
b6abf97d FB |
6435 | tcg_gen_movi_i32(cpu_tmp2_i32, 1); |
6436 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); | |
2c0262af FB |
6437 | break; |
6438 | case 0xfd: /* std */ | |
b6abf97d FB |
6439 | tcg_gen_movi_i32(cpu_tmp2_i32, -1); |
6440 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); | |
2c0262af FB |
6441 | break; |
6442 | ||
6443 | /************************/ | |
6444 | /* bit operations */ | |
6445 | case 0x1ba: /* bt/bts/btr/btc Gv, im */ | |
14ce26e7 | 6446 | ot = dflag + OT_WORD; |
61382a50 | 6447 | modrm = ldub_code(s->pc++); |
33698e5f | 6448 | op = (modrm >> 3) & 7; |
2c0262af | 6449 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6450 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 6451 | if (mod != 3) { |
14ce26e7 | 6452 | s->rip_offset = 1; |
2c0262af | 6453 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
57fec1fe | 6454 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6455 | } else { |
57fec1fe | 6456 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
6457 | } |
6458 | /* load shift */ | |
61382a50 | 6459 | val = ldub_code(s->pc++); |
2c0262af FB |
6460 | gen_op_movl_T1_im(val); |
6461 | if (op < 4) | |
6462 | goto illegal_op; | |
6463 | op -= 4; | |
f484d386 | 6464 | goto bt_op; |
2c0262af FB |
6465 | case 0x1a3: /* bt Gv, Ev */ |
6466 | op = 0; | |
6467 | goto do_btx; | |
6468 | case 0x1ab: /* bts */ | |
6469 | op = 1; | |
6470 | goto do_btx; | |
6471 | case 0x1b3: /* btr */ | |
6472 | op = 2; | |
6473 | goto do_btx; | |
6474 | case 0x1bb: /* btc */ | |
6475 | op = 3; | |
6476 | do_btx: | |
14ce26e7 | 6477 | ot = dflag + OT_WORD; |
61382a50 | 6478 | modrm = ldub_code(s->pc++); |
14ce26e7 | 6479 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 6480 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6481 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 6482 | gen_op_mov_TN_reg(OT_LONG, 1, reg); |
2c0262af FB |
6483 | if (mod != 3) { |
6484 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
6485 | /* specific case: we need to add a displacement */ | |
f484d386 FB |
6486 | gen_exts(ot, cpu_T[1]); |
6487 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); | |
6488 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); | |
6489 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe | 6490 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6491 | } else { |
57fec1fe | 6492 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 6493 | } |
f484d386 FB |
6494 | bt_op: |
6495 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); | |
6496 | switch(op) { | |
6497 | case 0: | |
6498 | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); | |
6499 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6500 | break; | |
6501 | case 1: | |
6502 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6503 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6504 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6505 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6506 | break; | |
6507 | case 2: | |
6508 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6509 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6510 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6511 | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); | |
6512 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6513 | break; | |
6514 | default: | |
6515 | case 3: | |
6516 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6517 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6518 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6519 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6520 | break; | |
6521 | } | |
2c0262af FB |
6522 | s->cc_op = CC_OP_SARB + ot; |
6523 | if (op != 0) { | |
6524 | if (mod != 3) | |
57fec1fe | 6525 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 6526 | else |
57fec1fe | 6527 | gen_op_mov_reg_T0(ot, rm); |
f484d386 FB |
6528 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
6529 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
2c0262af FB |
6530 | } |
6531 | break; | |
6532 | case 0x1bc: /* bsf */ | |
6533 | case 0x1bd: /* bsr */ | |
6191b059 FB |
6534 | { |
6535 | int label1; | |
1e4840bf FB |
6536 | TCGv t0; |
6537 | ||
6191b059 FB |
6538 | ot = dflag + OT_WORD; |
6539 | modrm = ldub_code(s->pc++); | |
6540 | reg = ((modrm >> 3) & 7) | rex_r; | |
6541 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
6542 | gen_extu(ot, cpu_T[0]); | |
6543 | label1 = gen_new_label(); | |
6544 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
a7812ae4 | 6545 | t0 = tcg_temp_local_new(); |
1e4840bf FB |
6546 | tcg_gen_mov_tl(t0, cpu_T[0]); |
6547 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1); | |
6191b059 | 6548 | if (b & 1) { |
a7812ae4 | 6549 | gen_helper_bsr(cpu_T[0], t0); |
6191b059 | 6550 | } else { |
a7812ae4 | 6551 | gen_helper_bsf(cpu_T[0], t0); |
6191b059 FB |
6552 | } |
6553 | gen_op_mov_reg_T0(ot, reg); | |
6554 | tcg_gen_movi_tl(cpu_cc_dst, 1); | |
6555 | gen_set_label(label1); | |
6556 | tcg_gen_discard_tl(cpu_cc_src); | |
6557 | s->cc_op = CC_OP_LOGICB + ot; | |
1e4840bf | 6558 | tcg_temp_free(t0); |
6191b059 | 6559 | } |
2c0262af FB |
6560 | break; |
6561 | /************************/ | |
6562 | /* bcd */ | |
6563 | case 0x27: /* daa */ | |
14ce26e7 FB |
6564 | if (CODE64(s)) |
6565 | goto illegal_op; | |
2c0262af FB |
6566 | if (s->cc_op != CC_OP_DYNAMIC) |
6567 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6568 | gen_helper_daa(); |
2c0262af FB |
6569 | s->cc_op = CC_OP_EFLAGS; |
6570 | break; | |
6571 | case 0x2f: /* das */ | |
14ce26e7 FB |
6572 | if (CODE64(s)) |
6573 | goto illegal_op; | |
2c0262af FB |
6574 | if (s->cc_op != CC_OP_DYNAMIC) |
6575 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6576 | gen_helper_das(); |
2c0262af FB |
6577 | s->cc_op = CC_OP_EFLAGS; |
6578 | break; | |
6579 | case 0x37: /* aaa */ | |
14ce26e7 FB |
6580 | if (CODE64(s)) |
6581 | goto illegal_op; | |
2c0262af FB |
6582 | if (s->cc_op != CC_OP_DYNAMIC) |
6583 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6584 | gen_helper_aaa(); |
2c0262af FB |
6585 | s->cc_op = CC_OP_EFLAGS; |
6586 | break; | |
6587 | case 0x3f: /* aas */ | |
14ce26e7 FB |
6588 | if (CODE64(s)) |
6589 | goto illegal_op; | |
2c0262af FB |
6590 | if (s->cc_op != CC_OP_DYNAMIC) |
6591 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6592 | gen_helper_aas(); |
2c0262af FB |
6593 | s->cc_op = CC_OP_EFLAGS; |
6594 | break; | |
6595 | case 0xd4: /* aam */ | |
14ce26e7 FB |
6596 | if (CODE64(s)) |
6597 | goto illegal_op; | |
61382a50 | 6598 | val = ldub_code(s->pc++); |
b6d7c3db TS |
6599 | if (val == 0) { |
6600 | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); | |
6601 | } else { | |
a7812ae4 | 6602 | gen_helper_aam(tcg_const_i32(val)); |
b6d7c3db TS |
6603 | s->cc_op = CC_OP_LOGICB; |
6604 | } | |
2c0262af FB |
6605 | break; |
6606 | case 0xd5: /* aad */ | |
14ce26e7 FB |
6607 | if (CODE64(s)) |
6608 | goto illegal_op; | |
61382a50 | 6609 | val = ldub_code(s->pc++); |
a7812ae4 | 6610 | gen_helper_aad(tcg_const_i32(val)); |
2c0262af FB |
6611 | s->cc_op = CC_OP_LOGICB; |
6612 | break; | |
6613 | /************************/ | |
6614 | /* misc */ | |
6615 | case 0x90: /* nop */ | |
14ce26e7 | 6616 | /* XXX: xchg + rex handling */ |
ab1f142b FB |
6617 | /* XXX: correct lock test for all insn */ |
6618 | if (prefixes & PREFIX_LOCK) | |
6619 | goto illegal_op; | |
0573fbfc TS |
6620 | if (prefixes & PREFIX_REPZ) { |
6621 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE); | |
6622 | } | |
2c0262af FB |
6623 | break; |
6624 | case 0x9b: /* fwait */ | |
5fafdf24 | 6625 | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == |
7eee2a50 FB |
6626 | (HF_MP_MASK | HF_TS_MASK)) { |
6627 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
2ee73ac3 FB |
6628 | } else { |
6629 | if (s->cc_op != CC_OP_DYNAMIC) | |
6630 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6631 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6632 | gen_helper_fwait(); |
7eee2a50 | 6633 | } |
2c0262af FB |
6634 | break; |
6635 | case 0xcc: /* int3 */ | |
6636 | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); | |
6637 | break; | |
6638 | case 0xcd: /* int N */ | |
61382a50 | 6639 | val = ldub_code(s->pc++); |
f115e911 | 6640 | if (s->vm86 && s->iopl != 3) { |
5fafdf24 | 6641 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
f115e911 FB |
6642 | } else { |
6643 | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); | |
6644 | } | |
2c0262af FB |
6645 | break; |
6646 | case 0xce: /* into */ | |
14ce26e7 FB |
6647 | if (CODE64(s)) |
6648 | goto illegal_op; | |
2c0262af FB |
6649 | if (s->cc_op != CC_OP_DYNAMIC) |
6650 | gen_op_set_cc_op(s->cc_op); | |
a8ede8ba | 6651 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6652 | gen_helper_into(tcg_const_i32(s->pc - pc_start)); |
2c0262af | 6653 | break; |
0b97134b | 6654 | #ifdef WANT_ICEBP |
2c0262af | 6655 | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
872929aa | 6656 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); |
aba9d61e | 6657 | #if 1 |
2c0262af | 6658 | gen_debug(s, pc_start - s->cs_base); |
aba9d61e FB |
6659 | #else |
6660 | /* start debug */ | |
6661 | tb_flush(cpu_single_env); | |
6662 | cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); | |
6663 | #endif | |
2c0262af | 6664 | break; |
0b97134b | 6665 | #endif |
2c0262af FB |
6666 | case 0xfa: /* cli */ |
6667 | if (!s->vm86) { | |
6668 | if (s->cpl <= s->iopl) { | |
a7812ae4 | 6669 | gen_helper_cli(); |
2c0262af FB |
6670 | } else { |
6671 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6672 | } | |
6673 | } else { | |
6674 | if (s->iopl == 3) { | |
a7812ae4 | 6675 | gen_helper_cli(); |
2c0262af FB |
6676 | } else { |
6677 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6678 | } | |
6679 | } | |
6680 | break; | |
6681 | case 0xfb: /* sti */ | |
6682 | if (!s->vm86) { | |
6683 | if (s->cpl <= s->iopl) { | |
6684 | gen_sti: | |
a7812ae4 | 6685 | gen_helper_sti(); |
2c0262af | 6686 | /* interruptions are enabled only the first insn after sti */ |
a2cc3b24 FB |
6687 | /* If several instructions disable interrupts, only the |
6688 | _first_ does it */ | |
6689 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
a7812ae4 | 6690 | gen_helper_set_inhibit_irq(); |
2c0262af | 6691 | /* give a chance to handle pending irqs */ |
14ce26e7 | 6692 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6693 | gen_eob(s); |
6694 | } else { | |
6695 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6696 | } | |
6697 | } else { | |
6698 | if (s->iopl == 3) { | |
6699 | goto gen_sti; | |
6700 | } else { | |
6701 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6702 | } | |
6703 | } | |
6704 | break; | |
6705 | case 0x62: /* bound */ | |
14ce26e7 FB |
6706 | if (CODE64(s)) |
6707 | goto illegal_op; | |
2c0262af | 6708 | ot = dflag ? OT_LONG : OT_WORD; |
61382a50 | 6709 | modrm = ldub_code(s->pc++); |
2c0262af FB |
6710 | reg = (modrm >> 3) & 7; |
6711 | mod = (modrm >> 6) & 3; | |
6712 | if (mod == 3) | |
6713 | goto illegal_op; | |
57fec1fe | 6714 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af | 6715 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 6716 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6717 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2c0262af | 6718 | if (ot == OT_WORD) |
a7812ae4 | 6719 | gen_helper_boundw(cpu_A0, cpu_tmp2_i32); |
2c0262af | 6720 | else |
a7812ae4 | 6721 | gen_helper_boundl(cpu_A0, cpu_tmp2_i32); |
2c0262af FB |
6722 | break; |
6723 | case 0x1c8 ... 0x1cf: /* bswap reg */ | |
14ce26e7 FB |
6724 | reg = (b & 7) | REX_B(s); |
6725 | #ifdef TARGET_X86_64 | |
6726 | if (dflag == 2) { | |
57fec1fe | 6727 | gen_op_mov_TN_reg(OT_QUAD, 0, reg); |
66896cb8 | 6728 | tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); |
57fec1fe | 6729 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 6730 | } else |
8777643e | 6731 | #endif |
57fec1fe FB |
6732 | { |
6733 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
8777643e AJ |
6734 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
6735 | tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); | |
57fec1fe | 6736 | gen_op_mov_reg_T0(OT_LONG, reg); |
14ce26e7 | 6737 | } |
2c0262af FB |
6738 | break; |
6739 | case 0xd6: /* salc */ | |
14ce26e7 FB |
6740 | if (CODE64(s)) |
6741 | goto illegal_op; | |
2c0262af FB |
6742 | if (s->cc_op != CC_OP_DYNAMIC) |
6743 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6744 | gen_compute_eflags_c(cpu_T[0]); |
6745 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); | |
6746 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
6747 | break; |
6748 | case 0xe0: /* loopnz */ | |
6749 | case 0xe1: /* loopz */ | |
2c0262af FB |
6750 | case 0xe2: /* loop */ |
6751 | case 0xe3: /* jecxz */ | |
14ce26e7 | 6752 | { |
6e0d8677 | 6753 | int l1, l2, l3; |
14ce26e7 FB |
6754 | |
6755 | tval = (int8_t)insn_get(s, OT_BYTE); | |
6756 | next_eip = s->pc - s->cs_base; | |
6757 | tval += next_eip; | |
6758 | if (s->dflag == 0) | |
6759 | tval &= 0xffff; | |
3b46e624 | 6760 | |
14ce26e7 FB |
6761 | l1 = gen_new_label(); |
6762 | l2 = gen_new_label(); | |
6e0d8677 | 6763 | l3 = gen_new_label(); |
14ce26e7 | 6764 | b &= 3; |
6e0d8677 FB |
6765 | switch(b) { |
6766 | case 0: /* loopnz */ | |
6767 | case 1: /* loopz */ | |
6768 | if (s->cc_op != CC_OP_DYNAMIC) | |
6769 | gen_op_set_cc_op(s->cc_op); | |
6770 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
6771 | gen_op_jz_ecx(s->aflag, l3); | |
6772 | gen_compute_eflags(cpu_tmp0); | |
6773 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z); | |
6774 | if (b == 0) { | |
cb63669a | 6775 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
6e0d8677 | 6776 | } else { |
cb63669a | 6777 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1); |
6e0d8677 FB |
6778 | } |
6779 | break; | |
6780 | case 2: /* loop */ | |
6781 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
6782 | gen_op_jnz_ecx(s->aflag, l1); | |
6783 | break; | |
6784 | default: | |
6785 | case 3: /* jcxz */ | |
6786 | gen_op_jz_ecx(s->aflag, l1); | |
6787 | break; | |
14ce26e7 FB |
6788 | } |
6789 | ||
6e0d8677 | 6790 | gen_set_label(l3); |
14ce26e7 | 6791 | gen_jmp_im(next_eip); |
8e1c85e3 | 6792 | tcg_gen_br(l2); |
6e0d8677 | 6793 | |
14ce26e7 FB |
6794 | gen_set_label(l1); |
6795 | gen_jmp_im(tval); | |
6796 | gen_set_label(l2); | |
6797 | gen_eob(s); | |
6798 | } | |
2c0262af FB |
6799 | break; |
6800 | case 0x130: /* wrmsr */ | |
6801 | case 0x132: /* rdmsr */ | |
6802 | if (s->cpl != 0) { | |
6803 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6804 | } else { | |
872929aa FB |
6805 | if (s->cc_op != CC_OP_DYNAMIC) |
6806 | gen_op_set_cc_op(s->cc_op); | |
6807 | gen_jmp_im(pc_start - s->cs_base); | |
0573fbfc | 6808 | if (b & 2) { |
a7812ae4 | 6809 | gen_helper_rdmsr(); |
0573fbfc | 6810 | } else { |
a7812ae4 | 6811 | gen_helper_wrmsr(); |
0573fbfc | 6812 | } |
2c0262af FB |
6813 | } |
6814 | break; | |
6815 | case 0x131: /* rdtsc */ | |
872929aa FB |
6816 | if (s->cc_op != CC_OP_DYNAMIC) |
6817 | gen_op_set_cc_op(s->cc_op); | |
ecada8a2 | 6818 | gen_jmp_im(pc_start - s->cs_base); |
efade670 PB |
6819 | if (use_icount) |
6820 | gen_io_start(); | |
a7812ae4 | 6821 | gen_helper_rdtsc(); |
efade670 PB |
6822 | if (use_icount) { |
6823 | gen_io_end(); | |
6824 | gen_jmp(s, s->pc - s->cs_base); | |
6825 | } | |
2c0262af | 6826 | break; |
df01e0fc | 6827 | case 0x133: /* rdpmc */ |
872929aa FB |
6828 | if (s->cc_op != CC_OP_DYNAMIC) |
6829 | gen_op_set_cc_op(s->cc_op); | |
df01e0fc | 6830 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6831 | gen_helper_rdpmc(); |
df01e0fc | 6832 | break; |
023fe10d | 6833 | case 0x134: /* sysenter */ |
2436b61a AZ |
6834 | /* For Intel SYSENTER is valid on 64-bit */ |
6835 | if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) | |
14ce26e7 | 6836 | goto illegal_op; |
023fe10d FB |
6837 | if (!s->pe) { |
6838 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6839 | } else { | |
6840 | if (s->cc_op != CC_OP_DYNAMIC) { | |
6841 | gen_op_set_cc_op(s->cc_op); | |
6842 | s->cc_op = CC_OP_DYNAMIC; | |
6843 | } | |
14ce26e7 | 6844 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6845 | gen_helper_sysenter(); |
023fe10d FB |
6846 | gen_eob(s); |
6847 | } | |
6848 | break; | |
6849 | case 0x135: /* sysexit */ | |
2436b61a AZ |
6850 | /* For Intel SYSEXIT is valid on 64-bit */ |
6851 | if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) | |
14ce26e7 | 6852 | goto illegal_op; |
023fe10d FB |
6853 | if (!s->pe) { |
6854 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6855 | } else { | |
6856 | if (s->cc_op != CC_OP_DYNAMIC) { | |
6857 | gen_op_set_cc_op(s->cc_op); | |
6858 | s->cc_op = CC_OP_DYNAMIC; | |
6859 | } | |
14ce26e7 | 6860 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6861 | gen_helper_sysexit(tcg_const_i32(dflag)); |
023fe10d FB |
6862 | gen_eob(s); |
6863 | } | |
6864 | break; | |
14ce26e7 FB |
6865 | #ifdef TARGET_X86_64 |
6866 | case 0x105: /* syscall */ | |
6867 | /* XXX: is it usable in real mode ? */ | |
6868 | if (s->cc_op != CC_OP_DYNAMIC) { | |
6869 | gen_op_set_cc_op(s->cc_op); | |
6870 | s->cc_op = CC_OP_DYNAMIC; | |
6871 | } | |
6872 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 6873 | gen_helper_syscall(tcg_const_i32(s->pc - pc_start)); |
14ce26e7 FB |
6874 | gen_eob(s); |
6875 | break; | |
6876 | case 0x107: /* sysret */ | |
6877 | if (!s->pe) { | |
6878 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6879 | } else { | |
6880 | if (s->cc_op != CC_OP_DYNAMIC) { | |
6881 | gen_op_set_cc_op(s->cc_op); | |
6882 | s->cc_op = CC_OP_DYNAMIC; | |
6883 | } | |
6884 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 6885 | gen_helper_sysret(tcg_const_i32(s->dflag)); |
aba9d61e FB |
6886 | /* condition codes are modified only in long mode */ |
6887 | if (s->lma) | |
6888 | s->cc_op = CC_OP_EFLAGS; | |
14ce26e7 FB |
6889 | gen_eob(s); |
6890 | } | |
6891 | break; | |
6892 | #endif | |
2c0262af | 6893 | case 0x1a2: /* cpuid */ |
9575cb94 FB |
6894 | if (s->cc_op != CC_OP_DYNAMIC) |
6895 | gen_op_set_cc_op(s->cc_op); | |
6896 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 6897 | gen_helper_cpuid(); |
2c0262af FB |
6898 | break; |
6899 | case 0xf4: /* hlt */ | |
6900 | if (s->cpl != 0) { | |
6901 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6902 | } else { | |
6903 | if (s->cc_op != CC_OP_DYNAMIC) | |
6904 | gen_op_set_cc_op(s->cc_op); | |
94451178 | 6905 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6906 | gen_helper_hlt(tcg_const_i32(s->pc - pc_start)); |
2c0262af FB |
6907 | s->is_jmp = 3; |
6908 | } | |
6909 | break; | |
6910 | case 0x100: | |
61382a50 | 6911 | modrm = ldub_code(s->pc++); |
2c0262af FB |
6912 | mod = (modrm >> 6) & 3; |
6913 | op = (modrm >> 3) & 7; | |
6914 | switch(op) { | |
6915 | case 0: /* sldt */ | |
f115e911 FB |
6916 | if (!s->pe || s->vm86) |
6917 | goto illegal_op; | |
872929aa | 6918 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); |
651ba608 | 6919 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); |
2c0262af FB |
6920 | ot = OT_WORD; |
6921 | if (mod == 3) | |
6922 | ot += s->dflag; | |
6923 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); | |
6924 | break; | |
6925 | case 2: /* lldt */ | |
f115e911 FB |
6926 | if (!s->pe || s->vm86) |
6927 | goto illegal_op; | |
2c0262af FB |
6928 | if (s->cpl != 0) { |
6929 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6930 | } else { | |
872929aa | 6931 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); |
2c0262af | 6932 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 6933 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6934 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6935 | gen_helper_lldt(cpu_tmp2_i32); |
2c0262af FB |
6936 | } |
6937 | break; | |
6938 | case 1: /* str */ | |
f115e911 FB |
6939 | if (!s->pe || s->vm86) |
6940 | goto illegal_op; | |
872929aa | 6941 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); |
651ba608 | 6942 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); |
2c0262af FB |
6943 | ot = OT_WORD; |
6944 | if (mod == 3) | |
6945 | ot += s->dflag; | |
6946 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); | |
6947 | break; | |
6948 | case 3: /* ltr */ | |
f115e911 FB |
6949 | if (!s->pe || s->vm86) |
6950 | goto illegal_op; | |
2c0262af FB |
6951 | if (s->cpl != 0) { |
6952 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6953 | } else { | |
872929aa | 6954 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); |
2c0262af | 6955 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 6956 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6957 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6958 | gen_helper_ltr(cpu_tmp2_i32); |
2c0262af FB |
6959 | } |
6960 | break; | |
6961 | case 4: /* verr */ | |
6962 | case 5: /* verw */ | |
f115e911 FB |
6963 | if (!s->pe || s->vm86) |
6964 | goto illegal_op; | |
6965 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); | |
6966 | if (s->cc_op != CC_OP_DYNAMIC) | |
6967 | gen_op_set_cc_op(s->cc_op); | |
6968 | if (op == 4) | |
a7812ae4 | 6969 | gen_helper_verr(cpu_T[0]); |
f115e911 | 6970 | else |
a7812ae4 | 6971 | gen_helper_verw(cpu_T[0]); |
f115e911 FB |
6972 | s->cc_op = CC_OP_EFLAGS; |
6973 | break; | |
2c0262af FB |
6974 | default: |
6975 | goto illegal_op; | |
6976 | } | |
6977 | break; | |
6978 | case 0x101: | |
61382a50 | 6979 | modrm = ldub_code(s->pc++); |
2c0262af FB |
6980 | mod = (modrm >> 6) & 3; |
6981 | op = (modrm >> 3) & 7; | |
3d7374c5 | 6982 | rm = modrm & 7; |
2c0262af FB |
6983 | switch(op) { |
6984 | case 0: /* sgdt */ | |
2c0262af FB |
6985 | if (mod == 3) |
6986 | goto illegal_op; | |
872929aa | 6987 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); |
2c0262af | 6988 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
651ba608 | 6989 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); |
57fec1fe | 6990 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
aba9d61e | 6991 | gen_add_A0_im(s, 2); |
651ba608 | 6992 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); |
2c0262af FB |
6993 | if (!s->dflag) |
6994 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 6995 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af | 6996 | break; |
3d7374c5 FB |
6997 | case 1: |
6998 | if (mod == 3) { | |
6999 | switch (rm) { | |
7000 | case 0: /* monitor */ | |
7001 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7002 | s->cpl != 0) | |
7003 | goto illegal_op; | |
94451178 FB |
7004 | if (s->cc_op != CC_OP_DYNAMIC) |
7005 | gen_op_set_cc_op(s->cc_op); | |
3d7374c5 FB |
7006 | gen_jmp_im(pc_start - s->cs_base); |
7007 | #ifdef TARGET_X86_64 | |
7008 | if (s->aflag == 2) { | |
bbf662ee | 7009 | gen_op_movq_A0_reg(R_EAX); |
5fafdf24 | 7010 | } else |
3d7374c5 FB |
7011 | #endif |
7012 | { | |
bbf662ee | 7013 | gen_op_movl_A0_reg(R_EAX); |
3d7374c5 FB |
7014 | if (s->aflag == 0) |
7015 | gen_op_andl_A0_ffff(); | |
7016 | } | |
7017 | gen_add_A0_ds_seg(s); | |
a7812ae4 | 7018 | gen_helper_monitor(cpu_A0); |
3d7374c5 FB |
7019 | break; |
7020 | case 1: /* mwait */ | |
7021 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7022 | s->cpl != 0) | |
7023 | goto illegal_op; | |
7024 | if (s->cc_op != CC_OP_DYNAMIC) { | |
7025 | gen_op_set_cc_op(s->cc_op); | |
7026 | s->cc_op = CC_OP_DYNAMIC; | |
7027 | } | |
94451178 | 7028 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 7029 | gen_helper_mwait(tcg_const_i32(s->pc - pc_start)); |
3d7374c5 FB |
7030 | gen_eob(s); |
7031 | break; | |
7032 | default: | |
7033 | goto illegal_op; | |
7034 | } | |
7035 | } else { /* sidt */ | |
872929aa | 7036 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); |
3d7374c5 | 7037 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
651ba608 | 7038 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); |
57fec1fe | 7039 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
3d7374c5 | 7040 | gen_add_A0_im(s, 2); |
651ba608 | 7041 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); |
3d7374c5 FB |
7042 | if (!s->dflag) |
7043 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7044 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
3d7374c5 FB |
7045 | } |
7046 | break; | |
2c0262af FB |
7047 | case 2: /* lgdt */ |
7048 | case 3: /* lidt */ | |
0573fbfc | 7049 | if (mod == 3) { |
872929aa FB |
7050 | if (s->cc_op != CC_OP_DYNAMIC) |
7051 | gen_op_set_cc_op(s->cc_op); | |
7052 | gen_jmp_im(pc_start - s->cs_base); | |
0573fbfc TS |
7053 | switch(rm) { |
7054 | case 0: /* VMRUN */ | |
872929aa FB |
7055 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7056 | goto illegal_op; | |
7057 | if (s->cpl != 0) { | |
7058 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
0573fbfc | 7059 | break; |
872929aa | 7060 | } else { |
a7812ae4 PB |
7061 | gen_helper_vmrun(tcg_const_i32(s->aflag), |
7062 | tcg_const_i32(s->pc - pc_start)); | |
db620f46 FB |
7063 | tcg_gen_exit_tb(0); |
7064 | s->is_jmp = 3; | |
872929aa | 7065 | } |
0573fbfc TS |
7066 | break; |
7067 | case 1: /* VMMCALL */ | |
872929aa FB |
7068 | if (!(s->flags & HF_SVME_MASK)) |
7069 | goto illegal_op; | |
a7812ae4 | 7070 | gen_helper_vmmcall(); |
0573fbfc TS |
7071 | break; |
7072 | case 2: /* VMLOAD */ | |
872929aa FB |
7073 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7074 | goto illegal_op; | |
7075 | if (s->cpl != 0) { | |
7076 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7077 | break; | |
7078 | } else { | |
a7812ae4 | 7079 | gen_helper_vmload(tcg_const_i32(s->aflag)); |
872929aa | 7080 | } |
0573fbfc TS |
7081 | break; |
7082 | case 3: /* VMSAVE */ | |
872929aa FB |
7083 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7084 | goto illegal_op; | |
7085 | if (s->cpl != 0) { | |
7086 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7087 | break; | |
7088 | } else { | |
a7812ae4 | 7089 | gen_helper_vmsave(tcg_const_i32(s->aflag)); |
872929aa | 7090 | } |
0573fbfc TS |
7091 | break; |
7092 | case 4: /* STGI */ | |
872929aa FB |
7093 | if ((!(s->flags & HF_SVME_MASK) && |
7094 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7095 | !s->pe) | |
7096 | goto illegal_op; | |
7097 | if (s->cpl != 0) { | |
7098 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7099 | break; | |
7100 | } else { | |
a7812ae4 | 7101 | gen_helper_stgi(); |
872929aa | 7102 | } |
0573fbfc TS |
7103 | break; |
7104 | case 5: /* CLGI */ | |
872929aa FB |
7105 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7106 | goto illegal_op; | |
7107 | if (s->cpl != 0) { | |
7108 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7109 | break; | |
7110 | } else { | |
a7812ae4 | 7111 | gen_helper_clgi(); |
872929aa | 7112 | } |
0573fbfc TS |
7113 | break; |
7114 | case 6: /* SKINIT */ | |
872929aa FB |
7115 | if ((!(s->flags & HF_SVME_MASK) && |
7116 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7117 | !s->pe) | |
7118 | goto illegal_op; | |
a7812ae4 | 7119 | gen_helper_skinit(); |
0573fbfc TS |
7120 | break; |
7121 | case 7: /* INVLPGA */ | |
872929aa FB |
7122 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7123 | goto illegal_op; | |
7124 | if (s->cpl != 0) { | |
7125 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7126 | break; | |
7127 | } else { | |
a7812ae4 | 7128 | gen_helper_invlpga(tcg_const_i32(s->aflag)); |
872929aa | 7129 | } |
0573fbfc TS |
7130 | break; |
7131 | default: | |
7132 | goto illegal_op; | |
7133 | } | |
7134 | } else if (s->cpl != 0) { | |
2c0262af FB |
7135 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7136 | } else { | |
872929aa FB |
7137 | gen_svm_check_intercept(s, pc_start, |
7138 | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); | |
2c0262af | 7139 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
57fec1fe | 7140 | gen_op_ld_T1_A0(OT_WORD + s->mem_index); |
aba9d61e | 7141 | gen_add_A0_im(s, 2); |
57fec1fe | 7142 | gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af FB |
7143 | if (!s->dflag) |
7144 | gen_op_andl_T0_im(0xffffff); | |
7145 | if (op == 2) { | |
651ba608 FB |
7146 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); |
7147 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); | |
2c0262af | 7148 | } else { |
651ba608 FB |
7149 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); |
7150 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); | |
2c0262af FB |
7151 | } |
7152 | } | |
7153 | break; | |
7154 | case 4: /* smsw */ | |
872929aa | 7155 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); |
e2542fe2 | 7156 | #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN |
f60d2728 | 7157 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); |
7158 | #else | |
651ba608 | 7159 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); |
f60d2728 | 7160 | #endif |
2c0262af FB |
7161 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1); |
7162 | break; | |
7163 | case 6: /* lmsw */ | |
7164 | if (s->cpl != 0) { | |
7165 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7166 | } else { | |
872929aa | 7167 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
2c0262af | 7168 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
a7812ae4 | 7169 | gen_helper_lmsw(cpu_T[0]); |
14ce26e7 | 7170 | gen_jmp_im(s->pc - s->cs_base); |
d71b9a8b | 7171 | gen_eob(s); |
2c0262af FB |
7172 | } |
7173 | break; | |
7174 | case 7: /* invlpg */ | |
7175 | if (s->cpl != 0) { | |
7176 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7177 | } else { | |
14ce26e7 FB |
7178 | if (mod == 3) { |
7179 | #ifdef TARGET_X86_64 | |
3d7374c5 | 7180 | if (CODE64(s) && rm == 0) { |
14ce26e7 | 7181 | /* swapgs */ |
651ba608 FB |
7182 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base)); |
7183 | tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase)); | |
7184 | tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base)); | |
7185 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase)); | |
5fafdf24 | 7186 | } else |
14ce26e7 FB |
7187 | #endif |
7188 | { | |
7189 | goto illegal_op; | |
7190 | } | |
7191 | } else { | |
9575cb94 FB |
7192 | if (s->cc_op != CC_OP_DYNAMIC) |
7193 | gen_op_set_cc_op(s->cc_op); | |
7194 | gen_jmp_im(pc_start - s->cs_base); | |
14ce26e7 | 7195 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
a7812ae4 | 7196 | gen_helper_invlpg(cpu_A0); |
14ce26e7 FB |
7197 | gen_jmp_im(s->pc - s->cs_base); |
7198 | gen_eob(s); | |
7199 | } | |
2c0262af FB |
7200 | } |
7201 | break; | |
7202 | default: | |
7203 | goto illegal_op; | |
7204 | } | |
7205 | break; | |
3415a4dd FB |
7206 | case 0x108: /* invd */ |
7207 | case 0x109: /* wbinvd */ | |
7208 | if (s->cpl != 0) { | |
7209 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7210 | } else { | |
872929aa | 7211 | gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); |
3415a4dd FB |
7212 | /* nothing to do */ |
7213 | } | |
7214 | break; | |
14ce26e7 FB |
7215 | case 0x63: /* arpl or movslS (x86_64) */ |
7216 | #ifdef TARGET_X86_64 | |
7217 | if (CODE64(s)) { | |
7218 | int d_ot; | |
7219 | /* d_ot is the size of destination */ | |
7220 | d_ot = dflag + OT_WORD; | |
7221 | ||
7222 | modrm = ldub_code(s->pc++); | |
7223 | reg = ((modrm >> 3) & 7) | rex_r; | |
7224 | mod = (modrm >> 6) & 3; | |
7225 | rm = (modrm & 7) | REX_B(s); | |
3b46e624 | 7226 | |
14ce26e7 | 7227 | if (mod == 3) { |
57fec1fe | 7228 | gen_op_mov_TN_reg(OT_LONG, 0, rm); |
14ce26e7 FB |
7229 | /* sign extend */ |
7230 | if (d_ot == OT_QUAD) | |
e108dd01 | 7231 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
57fec1fe | 7232 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 FB |
7233 | } else { |
7234 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7235 | if (d_ot == OT_QUAD) { | |
57fec1fe | 7236 | gen_op_lds_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7237 | } else { |
57fec1fe | 7238 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7239 | } |
57fec1fe | 7240 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7241 | } |
5fafdf24 | 7242 | } else |
14ce26e7 FB |
7243 | #endif |
7244 | { | |
3bd7da9e | 7245 | int label1; |
1e4840bf FB |
7246 | TCGv t0, t1, t2; |
7247 | ||
14ce26e7 FB |
7248 | if (!s->pe || s->vm86) |
7249 | goto illegal_op; | |
a7812ae4 PB |
7250 | t0 = tcg_temp_local_new(); |
7251 | t1 = tcg_temp_local_new(); | |
7252 | t2 = tcg_temp_local_new(); | |
3bd7da9e | 7253 | ot = OT_WORD; |
14ce26e7 FB |
7254 | modrm = ldub_code(s->pc++); |
7255 | reg = (modrm >> 3) & 7; | |
7256 | mod = (modrm >> 6) & 3; | |
7257 | rm = modrm & 7; | |
7258 | if (mod != 3) { | |
7259 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
1e4840bf | 7260 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
14ce26e7 | 7261 | } else { |
1e4840bf | 7262 | gen_op_mov_v_reg(ot, t0, rm); |
14ce26e7 | 7263 | } |
1e4840bf FB |
7264 | gen_op_mov_v_reg(ot, t1, reg); |
7265 | tcg_gen_andi_tl(cpu_tmp0, t0, 3); | |
7266 | tcg_gen_andi_tl(t1, t1, 3); | |
7267 | tcg_gen_movi_tl(t2, 0); | |
3bd7da9e | 7268 | label1 = gen_new_label(); |
1e4840bf FB |
7269 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); |
7270 | tcg_gen_andi_tl(t0, t0, ~3); | |
7271 | tcg_gen_or_tl(t0, t0, t1); | |
7272 | tcg_gen_movi_tl(t2, CC_Z); | |
3bd7da9e | 7273 | gen_set_label(label1); |
14ce26e7 | 7274 | if (mod != 3) { |
1e4840bf | 7275 | gen_op_st_v(ot + s->mem_index, t0, cpu_A0); |
14ce26e7 | 7276 | } else { |
1e4840bf | 7277 | gen_op_mov_reg_v(ot, rm, t0); |
14ce26e7 | 7278 | } |
3bd7da9e FB |
7279 | if (s->cc_op != CC_OP_DYNAMIC) |
7280 | gen_op_set_cc_op(s->cc_op); | |
7281 | gen_compute_eflags(cpu_cc_src); | |
7282 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); | |
1e4840bf | 7283 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); |
3bd7da9e | 7284 | s->cc_op = CC_OP_EFLAGS; |
1e4840bf FB |
7285 | tcg_temp_free(t0); |
7286 | tcg_temp_free(t1); | |
7287 | tcg_temp_free(t2); | |
f115e911 | 7288 | } |
f115e911 | 7289 | break; |
2c0262af FB |
7290 | case 0x102: /* lar */ |
7291 | case 0x103: /* lsl */ | |
cec6843e FB |
7292 | { |
7293 | int label1; | |
1e4840bf | 7294 | TCGv t0; |
cec6843e FB |
7295 | if (!s->pe || s->vm86) |
7296 | goto illegal_op; | |
7297 | ot = dflag ? OT_LONG : OT_WORD; | |
7298 | modrm = ldub_code(s->pc++); | |
7299 | reg = ((modrm >> 3) & 7) | rex_r; | |
7300 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); | |
a7812ae4 | 7301 | t0 = tcg_temp_local_new(); |
cec6843e FB |
7302 | if (s->cc_op != CC_OP_DYNAMIC) |
7303 | gen_op_set_cc_op(s->cc_op); | |
7304 | if (b == 0x102) | |
a7812ae4 | 7305 | gen_helper_lar(t0, cpu_T[0]); |
cec6843e | 7306 | else |
a7812ae4 | 7307 | gen_helper_lsl(t0, cpu_T[0]); |
cec6843e FB |
7308 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); |
7309 | label1 = gen_new_label(); | |
cb63669a | 7310 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
1e4840bf | 7311 | gen_op_mov_reg_v(ot, reg, t0); |
cec6843e FB |
7312 | gen_set_label(label1); |
7313 | s->cc_op = CC_OP_EFLAGS; | |
1e4840bf | 7314 | tcg_temp_free(t0); |
cec6843e | 7315 | } |
2c0262af FB |
7316 | break; |
7317 | case 0x118: | |
61382a50 | 7318 | modrm = ldub_code(s->pc++); |
2c0262af FB |
7319 | mod = (modrm >> 6) & 3; |
7320 | op = (modrm >> 3) & 7; | |
7321 | switch(op) { | |
7322 | case 0: /* prefetchnta */ | |
7323 | case 1: /* prefetchnt0 */ | |
7324 | case 2: /* prefetchnt0 */ | |
7325 | case 3: /* prefetchnt0 */ | |
7326 | if (mod == 3) | |
7327 | goto illegal_op; | |
7328 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7329 | /* nothing more to do */ | |
7330 | break; | |
e17a36ce FB |
7331 | default: /* nop (multi byte) */ |
7332 | gen_nop_modrm(s, modrm); | |
7333 | break; | |
2c0262af FB |
7334 | } |
7335 | break; | |
e17a36ce FB |
7336 | case 0x119 ... 0x11f: /* nop (multi byte) */ |
7337 | modrm = ldub_code(s->pc++); | |
7338 | gen_nop_modrm(s, modrm); | |
7339 | break; | |
2c0262af FB |
7340 | case 0x120: /* mov reg, crN */ |
7341 | case 0x122: /* mov crN, reg */ | |
7342 | if (s->cpl != 0) { | |
7343 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7344 | } else { | |
61382a50 | 7345 | modrm = ldub_code(s->pc++); |
2c0262af FB |
7346 | if ((modrm & 0xc0) != 0xc0) |
7347 | goto illegal_op; | |
14ce26e7 FB |
7348 | rm = (modrm & 7) | REX_B(s); |
7349 | reg = ((modrm >> 3) & 7) | rex_r; | |
7350 | if (CODE64(s)) | |
7351 | ot = OT_QUAD; | |
7352 | else | |
7353 | ot = OT_LONG; | |
ccd59d09 AP |
7354 | if ((prefixes & PREFIX_LOCK) && (reg == 0) && |
7355 | (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { | |
7356 | reg = 8; | |
7357 | } | |
2c0262af FB |
7358 | switch(reg) { |
7359 | case 0: | |
7360 | case 2: | |
7361 | case 3: | |
7362 | case 4: | |
9230e66e | 7363 | case 8: |
872929aa FB |
7364 | if (s->cc_op != CC_OP_DYNAMIC) |
7365 | gen_op_set_cc_op(s->cc_op); | |
7366 | gen_jmp_im(pc_start - s->cs_base); | |
2c0262af | 7367 | if (b & 2) { |
57fec1fe | 7368 | gen_op_mov_TN_reg(ot, 0, rm); |
a7812ae4 | 7369 | gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7370 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7371 | gen_eob(s); |
7372 | } else { | |
a7812ae4 | 7373 | gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg)); |
57fec1fe | 7374 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7375 | } |
7376 | break; | |
7377 | default: | |
7378 | goto illegal_op; | |
7379 | } | |
7380 | } | |
7381 | break; | |
7382 | case 0x121: /* mov reg, drN */ | |
7383 | case 0x123: /* mov drN, reg */ | |
7384 | if (s->cpl != 0) { | |
7385 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7386 | } else { | |
61382a50 | 7387 | modrm = ldub_code(s->pc++); |
2c0262af FB |
7388 | if ((modrm & 0xc0) != 0xc0) |
7389 | goto illegal_op; | |
14ce26e7 FB |
7390 | rm = (modrm & 7) | REX_B(s); |
7391 | reg = ((modrm >> 3) & 7) | rex_r; | |
7392 | if (CODE64(s)) | |
7393 | ot = OT_QUAD; | |
7394 | else | |
7395 | ot = OT_LONG; | |
2c0262af | 7396 | /* XXX: do it dynamically with CR4.DE bit */ |
14ce26e7 | 7397 | if (reg == 4 || reg == 5 || reg >= 8) |
2c0262af FB |
7398 | goto illegal_op; |
7399 | if (b & 2) { | |
0573fbfc | 7400 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
57fec1fe | 7401 | gen_op_mov_TN_reg(ot, 0, rm); |
a7812ae4 | 7402 | gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7403 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7404 | gen_eob(s); |
7405 | } else { | |
0573fbfc | 7406 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
651ba608 | 7407 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); |
57fec1fe | 7408 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7409 | } |
7410 | } | |
7411 | break; | |
7412 | case 0x106: /* clts */ | |
7413 | if (s->cpl != 0) { | |
7414 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7415 | } else { | |
0573fbfc | 7416 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
a7812ae4 | 7417 | gen_helper_clts(); |
7eee2a50 | 7418 | /* abort block because static cpu state changed */ |
14ce26e7 | 7419 | gen_jmp_im(s->pc - s->cs_base); |
7eee2a50 | 7420 | gen_eob(s); |
2c0262af FB |
7421 | } |
7422 | break; | |
222a3336 | 7423 | /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ |
664e0f19 FB |
7424 | case 0x1c3: /* MOVNTI reg, mem */ |
7425 | if (!(s->cpuid_features & CPUID_SSE2)) | |
14ce26e7 | 7426 | goto illegal_op; |
664e0f19 FB |
7427 | ot = s->dflag == 2 ? OT_QUAD : OT_LONG; |
7428 | modrm = ldub_code(s->pc++); | |
7429 | mod = (modrm >> 6) & 3; | |
7430 | if (mod == 3) | |
7431 | goto illegal_op; | |
7432 | reg = ((modrm >> 3) & 7) | rex_r; | |
7433 | /* generate a generic store */ | |
7434 | gen_ldst_modrm(s, modrm, ot, reg, 1); | |
14ce26e7 | 7435 | break; |
664e0f19 FB |
7436 | case 0x1ae: |
7437 | modrm = ldub_code(s->pc++); | |
7438 | mod = (modrm >> 6) & 3; | |
7439 | op = (modrm >> 3) & 7; | |
7440 | switch(op) { | |
7441 | case 0: /* fxsave */ | |
5fafdf24 | 7442 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
0fd14b72 | 7443 | (s->flags & HF_EM_MASK)) |
14ce26e7 | 7444 | goto illegal_op; |
0fd14b72 FB |
7445 | if (s->flags & HF_TS_MASK) { |
7446 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7447 | break; | |
7448 | } | |
664e0f19 | 7449 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
19e6c4b8 FB |
7450 | if (s->cc_op != CC_OP_DYNAMIC) |
7451 | gen_op_set_cc_op(s->cc_op); | |
7452 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 7453 | gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2))); |
664e0f19 FB |
7454 | break; |
7455 | case 1: /* fxrstor */ | |
5fafdf24 | 7456 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
0fd14b72 | 7457 | (s->flags & HF_EM_MASK)) |
14ce26e7 | 7458 | goto illegal_op; |
0fd14b72 FB |
7459 | if (s->flags & HF_TS_MASK) { |
7460 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7461 | break; | |
7462 | } | |
664e0f19 | 7463 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
19e6c4b8 FB |
7464 | if (s->cc_op != CC_OP_DYNAMIC) |
7465 | gen_op_set_cc_op(s->cc_op); | |
7466 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 7467 | gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2))); |
664e0f19 FB |
7468 | break; |
7469 | case 2: /* ldmxcsr */ | |
7470 | case 3: /* stmxcsr */ | |
7471 | if (s->flags & HF_TS_MASK) { | |
7472 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7473 | break; | |
14ce26e7 | 7474 | } |
664e0f19 FB |
7475 | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) || |
7476 | mod == 3) | |
14ce26e7 | 7477 | goto illegal_op; |
664e0f19 FB |
7478 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7479 | if (op == 2) { | |
57fec1fe | 7480 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 7481 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
14ce26e7 | 7482 | } else { |
651ba608 | 7483 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
57fec1fe | 7484 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7485 | } |
664e0f19 FB |
7486 | break; |
7487 | case 5: /* lfence */ | |
7488 | case 6: /* mfence */ | |
664e0f19 FB |
7489 | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE)) |
7490 | goto illegal_op; | |
7491 | break; | |
8f091a59 FB |
7492 | case 7: /* sfence / clflush */ |
7493 | if ((modrm & 0xc7) == 0xc0) { | |
7494 | /* sfence */ | |
a35f3ec7 | 7495 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */ |
8f091a59 FB |
7496 | if (!(s->cpuid_features & CPUID_SSE)) |
7497 | goto illegal_op; | |
7498 | } else { | |
7499 | /* clflush */ | |
7500 | if (!(s->cpuid_features & CPUID_CLFLUSH)) | |
7501 | goto illegal_op; | |
7502 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7503 | } | |
7504 | break; | |
664e0f19 | 7505 | default: |
14ce26e7 FB |
7506 | goto illegal_op; |
7507 | } | |
7508 | break; | |
a35f3ec7 | 7509 | case 0x10d: /* 3DNow! prefetch(w) */ |
8f091a59 | 7510 | modrm = ldub_code(s->pc++); |
a35f3ec7 AJ |
7511 | mod = (modrm >> 6) & 3; |
7512 | if (mod == 3) | |
7513 | goto illegal_op; | |
8f091a59 FB |
7514 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7515 | /* ignore for now */ | |
7516 | break; | |
3b21e03e | 7517 | case 0x1aa: /* rsm */ |
872929aa | 7518 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); |
3b21e03e FB |
7519 | if (!(s->flags & HF_SMM_MASK)) |
7520 | goto illegal_op; | |
7521 | if (s->cc_op != CC_OP_DYNAMIC) { | |
7522 | gen_op_set_cc_op(s->cc_op); | |
7523 | s->cc_op = CC_OP_DYNAMIC; | |
7524 | } | |
7525 | gen_jmp_im(s->pc - s->cs_base); | |
a7812ae4 | 7526 | gen_helper_rsm(); |
3b21e03e FB |
7527 | gen_eob(s); |
7528 | break; | |
222a3336 AZ |
7529 | case 0x1b8: /* SSE4.2 popcnt */ |
7530 | if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != | |
7531 | PREFIX_REPZ) | |
7532 | goto illegal_op; | |
7533 | if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) | |
7534 | goto illegal_op; | |
7535 | ||
7536 | modrm = ldub_code(s->pc++); | |
7537 | reg = ((modrm >> 3) & 7); | |
7538 | ||
7539 | if (s->prefix & PREFIX_DATA) | |
7540 | ot = OT_WORD; | |
7541 | else if (s->dflag != 2) | |
7542 | ot = OT_LONG; | |
7543 | else | |
7544 | ot = OT_QUAD; | |
7545 | ||
7546 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
a7812ae4 | 7547 | gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot)); |
222a3336 | 7548 | gen_op_mov_reg_T0(ot, reg); |
fdb0d09d AZ |
7549 | |
7550 | s->cc_op = CC_OP_EFLAGS; | |
222a3336 | 7551 | break; |
a35f3ec7 AJ |
7552 | case 0x10e ... 0x10f: |
7553 | /* 3DNow! instructions, ignore prefixes */ | |
7554 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); | |
664e0f19 FB |
7555 | case 0x110 ... 0x117: |
7556 | case 0x128 ... 0x12f: | |
4242b1bd | 7557 | case 0x138 ... 0x13a: |
664e0f19 FB |
7558 | case 0x150 ... 0x177: |
7559 | case 0x17c ... 0x17f: | |
7560 | case 0x1c2: | |
7561 | case 0x1c4 ... 0x1c6: | |
7562 | case 0x1d0 ... 0x1fe: | |
7563 | gen_sse(s, b, pc_start, rex_r); | |
7564 | break; | |
2c0262af FB |
7565 | default: |
7566 | goto illegal_op; | |
7567 | } | |
7568 | /* lock generation */ | |
7569 | if (s->prefix & PREFIX_LOCK) | |
a7812ae4 | 7570 | gen_helper_unlock(); |
2c0262af FB |
7571 | return s->pc; |
7572 | illegal_op: | |
ab1f142b | 7573 | if (s->prefix & PREFIX_LOCK) |
a7812ae4 | 7574 | gen_helper_unlock(); |
2c0262af FB |
7575 | /* XXX: ensure that no lock was generated */ |
7576 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
7577 | return s->pc; | |
7578 | } | |
7579 | ||
2c0262af FB |
7580 | void optimize_flags_init(void) |
7581 | { | |
b6abf97d FB |
7582 | #if TCG_TARGET_REG_BITS == 32 |
7583 | assert(sizeof(CCTable) == (1 << 3)); | |
7584 | #else | |
7585 | assert(sizeof(CCTable) == (1 << 4)); | |
7586 | #endif | |
a7812ae4 PB |
7587 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7588 | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, | |
7589 | offsetof(CPUState, cc_op), "cc_op"); | |
7590 | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), | |
7591 | "cc_src"); | |
7592 | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), | |
7593 | "cc_dst"); | |
7594 | cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp), | |
7595 | "cc_tmp"); | |
437a88a5 | 7596 | |
cc739bb0 LD |
7597 | #ifdef TARGET_X86_64 |
7598 | cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0, | |
7599 | offsetof(CPUState, regs[R_EAX]), "rax"); | |
7600 | cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0, | |
7601 | offsetof(CPUState, regs[R_ECX]), "rcx"); | |
7602 | cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0, | |
7603 | offsetof(CPUState, regs[R_EDX]), "rdx"); | |
7604 | cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0, | |
7605 | offsetof(CPUState, regs[R_EBX]), "rbx"); | |
7606 | cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0, | |
7607 | offsetof(CPUState, regs[R_ESP]), "rsp"); | |
7608 | cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0, | |
7609 | offsetof(CPUState, regs[R_EBP]), "rbp"); | |
7610 | cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0, | |
7611 | offsetof(CPUState, regs[R_ESI]), "rsi"); | |
7612 | cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0, | |
7613 | offsetof(CPUState, regs[R_EDI]), "rdi"); | |
7614 | cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0, | |
7615 | offsetof(CPUState, regs[8]), "r8"); | |
7616 | cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0, | |
7617 | offsetof(CPUState, regs[9]), "r9"); | |
7618 | cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0, | |
7619 | offsetof(CPUState, regs[10]), "r10"); | |
7620 | cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0, | |
7621 | offsetof(CPUState, regs[11]), "r11"); | |
7622 | cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0, | |
7623 | offsetof(CPUState, regs[12]), "r12"); | |
7624 | cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0, | |
7625 | offsetof(CPUState, regs[13]), "r13"); | |
7626 | cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0, | |
7627 | offsetof(CPUState, regs[14]), "r14"); | |
7628 | cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0, | |
7629 | offsetof(CPUState, regs[15]), "r15"); | |
7630 | #else | |
7631 | cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0, | |
7632 | offsetof(CPUState, regs[R_EAX]), "eax"); | |
7633 | cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0, | |
7634 | offsetof(CPUState, regs[R_ECX]), "ecx"); | |
7635 | cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0, | |
7636 | offsetof(CPUState, regs[R_EDX]), "edx"); | |
7637 | cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0, | |
7638 | offsetof(CPUState, regs[R_EBX]), "ebx"); | |
7639 | cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0, | |
7640 | offsetof(CPUState, regs[R_ESP]), "esp"); | |
7641 | cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0, | |
7642 | offsetof(CPUState, regs[R_EBP]), "ebp"); | |
7643 | cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0, | |
7644 | offsetof(CPUState, regs[R_ESI]), "esi"); | |
7645 | cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, | |
7646 | offsetof(CPUState, regs[R_EDI]), "edi"); | |
7647 | #endif | |
7648 | ||
437a88a5 | 7649 | /* register helpers */ |
a7812ae4 | 7650 | #define GEN_HELPER 2 |
437a88a5 | 7651 | #include "helper.h" |
2c0262af FB |
7652 | } |
7653 | ||
7654 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for | |
7655 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
7656 | information for each intermediate instruction. */ | |
2cfc5f17 TS |
7657 | static inline void gen_intermediate_code_internal(CPUState *env, |
7658 | TranslationBlock *tb, | |
7659 | int search_pc) | |
2c0262af FB |
7660 | { |
7661 | DisasContext dc1, *dc = &dc1; | |
14ce26e7 | 7662 | target_ulong pc_ptr; |
2c0262af | 7663 | uint16_t *gen_opc_end; |
a1d1bb31 | 7664 | CPUBreakpoint *bp; |
c068688b JM |
7665 | int j, lj, cflags; |
7666 | uint64_t flags; | |
14ce26e7 FB |
7667 | target_ulong pc_start; |
7668 | target_ulong cs_base; | |
2e70f6ef PB |
7669 | int num_insns; |
7670 | int max_insns; | |
3b46e624 | 7671 | |
2c0262af | 7672 | /* generate intermediate code */ |
14ce26e7 FB |
7673 | pc_start = tb->pc; |
7674 | cs_base = tb->cs_base; | |
2c0262af | 7675 | flags = tb->flags; |
d720b93d | 7676 | cflags = tb->cflags; |
3a1d9b8b | 7677 | |
4f31916f | 7678 | dc->pe = (flags >> HF_PE_SHIFT) & 1; |
2c0262af FB |
7679 | dc->code32 = (flags >> HF_CS32_SHIFT) & 1; |
7680 | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; | |
7681 | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; | |
7682 | dc->f_st = 0; | |
7683 | dc->vm86 = (flags >> VM_SHIFT) & 1; | |
7684 | dc->cpl = (flags >> HF_CPL_SHIFT) & 3; | |
7685 | dc->iopl = (flags >> IOPL_SHIFT) & 3; | |
7686 | dc->tf = (flags >> TF_SHIFT) & 1; | |
34865134 | 7687 | dc->singlestep_enabled = env->singlestep_enabled; |
2c0262af FB |
7688 | dc->cc_op = CC_OP_DYNAMIC; |
7689 | dc->cs_base = cs_base; | |
7690 | dc->tb = tb; | |
7691 | dc->popl_esp_hack = 0; | |
7692 | /* select memory access functions */ | |
7693 | dc->mem_index = 0; | |
7694 | if (flags & HF_SOFTMMU_MASK) { | |
7695 | if (dc->cpl == 3) | |
14ce26e7 | 7696 | dc->mem_index = 2 * 4; |
2c0262af | 7697 | else |
14ce26e7 | 7698 | dc->mem_index = 1 * 4; |
2c0262af | 7699 | } |
14ce26e7 | 7700 | dc->cpuid_features = env->cpuid_features; |
3d7374c5 | 7701 | dc->cpuid_ext_features = env->cpuid_ext_features; |
e771edab | 7702 | dc->cpuid_ext2_features = env->cpuid_ext2_features; |
12e26b75 | 7703 | dc->cpuid_ext3_features = env->cpuid_ext3_features; |
14ce26e7 FB |
7704 | #ifdef TARGET_X86_64 |
7705 | dc->lma = (flags >> HF_LMA_SHIFT) & 1; | |
7706 | dc->code64 = (flags >> HF_CS64_SHIFT) & 1; | |
7707 | #endif | |
7eee2a50 | 7708 | dc->flags = flags; |
a2cc3b24 FB |
7709 | dc->jmp_opt = !(dc->tf || env->singlestep_enabled || |
7710 | (flags & HF_INHIBIT_IRQ_MASK) | |
415fa2ea | 7711 | #ifndef CONFIG_SOFTMMU |
2c0262af FB |
7712 | || (flags & HF_SOFTMMU_MASK) |
7713 | #endif | |
7714 | ); | |
4f31916f FB |
7715 | #if 0 |
7716 | /* check addseg logic */ | |
dc196a57 | 7717 | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) |
4f31916f FB |
7718 | printf("ERROR addseg\n"); |
7719 | #endif | |
7720 | ||
a7812ae4 PB |
7721 | cpu_T[0] = tcg_temp_new(); |
7722 | cpu_T[1] = tcg_temp_new(); | |
7723 | cpu_A0 = tcg_temp_new(); | |
7724 | cpu_T3 = tcg_temp_new(); | |
7725 | ||
7726 | cpu_tmp0 = tcg_temp_new(); | |
7727 | cpu_tmp1_i64 = tcg_temp_new_i64(); | |
7728 | cpu_tmp2_i32 = tcg_temp_new_i32(); | |
7729 | cpu_tmp3_i32 = tcg_temp_new_i32(); | |
7730 | cpu_tmp4 = tcg_temp_new(); | |
7731 | cpu_tmp5 = tcg_temp_new(); | |
a7812ae4 PB |
7732 | cpu_ptr0 = tcg_temp_new_ptr(); |
7733 | cpu_ptr1 = tcg_temp_new_ptr(); | |
57fec1fe | 7734 | |
2c0262af | 7735 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
7736 | |
7737 | dc->is_jmp = DISAS_NEXT; | |
7738 | pc_ptr = pc_start; | |
7739 | lj = -1; | |
2e70f6ef PB |
7740 | num_insns = 0; |
7741 | max_insns = tb->cflags & CF_COUNT_MASK; | |
7742 | if (max_insns == 0) | |
7743 | max_insns = CF_COUNT_MASK; | |
2c0262af | 7744 | |
2e70f6ef | 7745 | gen_icount_start(); |
2c0262af | 7746 | for(;;) { |
72cf2d4f BS |
7747 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
7748 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a2397807 JK |
7749 | if (bp->pc == pc_ptr && |
7750 | !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { | |
2c0262af FB |
7751 | gen_debug(dc, pc_ptr - dc->cs_base); |
7752 | break; | |
7753 | } | |
7754 | } | |
7755 | } | |
7756 | if (search_pc) { | |
7757 | j = gen_opc_ptr - gen_opc_buf; | |
7758 | if (lj < j) { | |
7759 | lj++; | |
7760 | while (lj < j) | |
7761 | gen_opc_instr_start[lj++] = 0; | |
7762 | } | |
14ce26e7 | 7763 | gen_opc_pc[lj] = pc_ptr; |
2c0262af FB |
7764 | gen_opc_cc_op[lj] = dc->cc_op; |
7765 | gen_opc_instr_start[lj] = 1; | |
2e70f6ef | 7766 | gen_opc_icount[lj] = num_insns; |
2c0262af | 7767 | } |
2e70f6ef PB |
7768 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
7769 | gen_io_start(); | |
7770 | ||
2c0262af | 7771 | pc_ptr = disas_insn(dc, pc_ptr); |
2e70f6ef | 7772 | num_insns++; |
2c0262af FB |
7773 | /* stop translation if indicated */ |
7774 | if (dc->is_jmp) | |
7775 | break; | |
7776 | /* if single step mode, we generate only one instruction and | |
7777 | generate an exception */ | |
a2cc3b24 FB |
7778 | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear |
7779 | the flag and abort the translation to give the irqs a | |
7780 | change to be happen */ | |
5fafdf24 | 7781 | if (dc->tf || dc->singlestep_enabled || |
2e70f6ef | 7782 | (flags & HF_INHIBIT_IRQ_MASK)) { |
14ce26e7 | 7783 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7784 | gen_eob(dc); |
7785 | break; | |
7786 | } | |
7787 | /* if too long translation, stop generation too */ | |
7788 | if (gen_opc_ptr >= gen_opc_end || | |
2e70f6ef PB |
7789 | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || |
7790 | num_insns >= max_insns) { | |
14ce26e7 | 7791 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7792 | gen_eob(dc); |
7793 | break; | |
7794 | } | |
1b530a6d AJ |
7795 | if (singlestep) { |
7796 | gen_jmp_im(pc_ptr - dc->cs_base); | |
7797 | gen_eob(dc); | |
7798 | break; | |
7799 | } | |
2c0262af | 7800 | } |
2e70f6ef PB |
7801 | if (tb->cflags & CF_LAST_IO) |
7802 | gen_io_end(); | |
7803 | gen_icount_end(tb, num_insns); | |
2c0262af FB |
7804 | *gen_opc_ptr = INDEX_op_end; |
7805 | /* we don't forget to fill the last values */ | |
7806 | if (search_pc) { | |
7807 | j = gen_opc_ptr - gen_opc_buf; | |
7808 | lj++; | |
7809 | while (lj <= j) | |
7810 | gen_opc_instr_start[lj++] = 0; | |
7811 | } | |
3b46e624 | 7812 | |
2c0262af | 7813 | #ifdef DEBUG_DISAS |
93fcfe39 | 7814 | log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP); |
8fec2b8c | 7815 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
14ce26e7 | 7816 | int disas_flags; |
93fcfe39 AL |
7817 | qemu_log("----------------\n"); |
7818 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
14ce26e7 FB |
7819 | #ifdef TARGET_X86_64 |
7820 | if (dc->code64) | |
7821 | disas_flags = 2; | |
7822 | else | |
7823 | #endif | |
7824 | disas_flags = !dc->code32; | |
93fcfe39 AL |
7825 | log_target_disas(pc_start, pc_ptr - pc_start, disas_flags); |
7826 | qemu_log("\n"); | |
2c0262af FB |
7827 | } |
7828 | #endif | |
7829 | ||
2e70f6ef | 7830 | if (!search_pc) { |
2c0262af | 7831 | tb->size = pc_ptr - pc_start; |
2e70f6ef PB |
7832 | tb->icount = num_insns; |
7833 | } | |
2c0262af FB |
7834 | } |
7835 | ||
2cfc5f17 | 7836 | void gen_intermediate_code(CPUState *env, TranslationBlock *tb) |
2c0262af | 7837 | { |
2cfc5f17 | 7838 | gen_intermediate_code_internal(env, tb, 0); |
2c0262af FB |
7839 | } |
7840 | ||
2cfc5f17 | 7841 | void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) |
2c0262af | 7842 | { |
2cfc5f17 | 7843 | gen_intermediate_code_internal(env, tb, 1); |
2c0262af FB |
7844 | } |
7845 | ||
d2856f1a AJ |
7846 | void gen_pc_load(CPUState *env, TranslationBlock *tb, |
7847 | unsigned long searched_pc, int pc_pos, void *puc) | |
7848 | { | |
7849 | int cc_op; | |
7850 | #ifdef DEBUG_DISAS | |
8fec2b8c | 7851 | if (qemu_loglevel_mask(CPU_LOG_TB_OP)) { |
d2856f1a | 7852 | int i; |
93fcfe39 | 7853 | qemu_log("RESTORE:\n"); |
d2856f1a AJ |
7854 | for(i = 0;i <= pc_pos; i++) { |
7855 | if (gen_opc_instr_start[i]) { | |
93fcfe39 | 7856 | qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]); |
d2856f1a AJ |
7857 | } |
7858 | } | |
93fcfe39 | 7859 | qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
d2856f1a AJ |
7860 | searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base, |
7861 | (uint32_t)tb->cs_base); | |
7862 | } | |
7863 | #endif | |
7864 | env->eip = gen_opc_pc[pc_pos] - tb->cs_base; | |
7865 | cc_op = gen_opc_cc_op[pc_pos]; | |
7866 | if (cc_op != CC_OP_DYNAMIC) | |
7867 | env->cc_op = cc_op; | |
7868 | } |