[mirror_qemu.git] / target-lm32 / cpu.h

/*
 *  LatticeMico32 virtual CPU header.
 *
 *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef CPU_LM32_H
#define CPU_LM32_H

#define TARGET_LONG_BITS 32

#define CPUArchState struct CPULM32State

#include "config.h"
#include "qemu-common.h"
#include "exec/cpu-defs.h"
struct CPULM32State;
typedef struct CPULM32State CPULM32State;

#define TARGET_HAS_ICE 1

#define ELF_MACHINE EM_LATTICEMICO32

#define NB_MMU_MODES 1
#define TARGET_PAGE_BITS 12
static inline int cpu_mmu_index(CPULM32State *env)
{
    return 0;
}

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

/* Exceptions indices */
enum {
    EXCP_RESET = 0,
    EXCP_BREAKPOINT,
    EXCP_INSN_BUS_ERROR,
    EXCP_WATCHPOINT,
    EXCP_DATA_BUS_ERROR,
    EXCP_DIVIDE_BY_ZERO,
    EXCP_IRQ,
    EXCP_SYSTEMCALL
};

/* Registers */
enum {
    R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10,
    R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20,
    R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30,
    R_R31
};

/* Register aliases */
enum {
    R_GP = R_R26,
    R_FP = R_R27,
    R_SP = R_R28,
    R_RA = R_R29,
    R_EA = R_R30,
    R_BA = R_R31
};

/* IE flags */
enum {
    IE_IE  = (1<<0),
    IE_EIE = (1<<1),
    IE_BIE = (1<<2),
};

/* DC flags */
enum {
    DC_SS  = (1<<0),
    DC_RE  = (1<<1),
    DC_C0  = (1<<2),
    DC_C1  = (1<<3),
    DC_C2  = (1<<4),
    DC_C3  = (1<<5),
};

/* CFG mask */
enum {
    CFG_M         = (1<<0),
    CFG_D         = (1<<1),
    CFG_S         = (1<<2),
    CFG_U         = (1<<3),
    CFG_X         = (1<<4),
    CFG_CC        = (1<<5),
    CFG_IC        = (1<<6),
    CFG_DC        = (1<<7),
    CFG_G         = (1<<8),
    CFG_H         = (1<<9),
    CFG_R         = (1<<10),
    CFG_J         = (1<<11),
    CFG_INT_SHIFT = 12,
    CFG_BP_SHIFT  = 18,
    CFG_WP_SHIFT  = 22,
    CFG_REV_SHIFT = 26,
};

/* CSRs */
enum {
    CSR_IE   = 0x00,
    CSR_IM   = 0x01,
    CSR_IP   = 0x02,
    CSR_ICC  = 0x03,
    CSR_DCC  = 0x04,
    CSR_CC   = 0x05,
    CSR_CFG  = 0x06,
    CSR_EBA  = 0x07,
    CSR_DC   = 0x08,
    CSR_DEBA = 0x09,
    CSR_JTX  = 0x0e,
    CSR_JRX  = 0x0f,
    CSR_BP0  = 0x10,
    CSR_BP1  = 0x11,
    CSR_BP2  = 0x12,
    CSR_BP3  = 0x13,
    CSR_WP0  = 0x18,
    CSR_WP1  = 0x19,
    CSR_WP2  = 0x1a,
    CSR_WP3  = 0x1b,
};

enum {
    LM32_FEATURE_MULTIPLY     =  1,
    LM32_FEATURE_DIVIDE       =  2,
    LM32_FEATURE_SHIFT        =  4,
    LM32_FEATURE_SIGN_EXTEND  =  8,
    LM32_FEATURE_I_CACHE      = 16,
    LM32_FEATURE_D_CACHE      = 32,
    LM32_FEATURE_CYCLE_COUNT  = 64,
};

enum {
    LM32_FLAG_IGNORE_MSB = 1,
};

struct CPULM32State {
    /* general registers */
    uint32_t regs[32];

    /* special registers */
    uint32_t pc;        /* program counter */
    uint32_t ie;        /* interrupt enable */
    uint32_t icc;       /* instruction cache control */
    uint32_t dcc;       /* data cache control */
    uint32_t cc;        /* cycle counter */
    uint32_t cfg;       /* configuration */

    /* debug registers */
    uint32_t dc;        /* debug control */
    uint32_t bp[4];     /* breakpoint addresses */
    uint32_t wp[4];     /* watchpoint addresses */

    CPU_COMMON

    uint32_t eba;       /* exception base address */
    uint32_t deba;      /* debug exception base address */

    /* interrupt controller handle for callbacks */
    DeviceState *pic_state;
    /* JTAG UART handle for callbacks */
    DeviceState *juart_state;

    /* processor core features */
    uint32_t features;
    uint32_t flags;
    uint8_t num_bps;
    uint8_t num_wps;

};

#include "cpu-qom.h"

LM32CPU *cpu_lm32_init(const char *cpu_model);
void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_lm32_exec(CPULM32State *s);
void cpu_lm32_close(CPULM32State *s);
void do_interrupt(CPULM32State *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_lm32_signal_handler(int host_signum, void *pinfo,
                          void *puc);
void lm32_translate_init(void);
void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);

static inline CPULM32State *cpu_init(const char *cpu_model)
{
    LM32CPU *cpu = cpu_lm32_init(cpu_model);
    if (cpu == NULL) {
        return NULL;
    }
    return &cpu->env;
}

#define cpu_list cpu_lm32_list
#define cpu_exec cpu_lm32_exec
#define cpu_gen_code cpu_lm32_gen_code
#define cpu_signal_handler cpu_lm32_signal_handler

#define CPU_SAVE_VERSION 1

int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
                              int mmu_idx);
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPULM32State *env, target_ulong newsp)
{
    if (newsp) {
        env->regs[R_SP] = newsp;
    }
    env->regs[R_R1] = 0;
}
#endif

static inline void cpu_set_tls(CPULM32State *env, target_ulong newtls)
{
}

static inline int cpu_interrupts_enabled(CPULM32State *env)
{
    return env->ie & IE_IE;
}

#include "exec/cpu-all.h"

static inline target_ulong cpu_get_pc(CPULM32State *env)
{
    return env->pc;
}

static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    *flags = 0;
}

static inline bool cpu_has_work(CPUState *cpu)
{
    CPULM32State *env = &LM32_CPU(cpu)->env;

    return env->interrupt_request & CPU_INTERRUPT_HARD;
}

#include "exec/exec-all.h"

static inline void cpu_pc_from_tb(CPULM32State *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
}

#endif
Commit	Line	Data
81ea0e13 MW	1	/*
	2	* LatticeMico32 virtual CPU header.
	3	*
	4	* Copyright (c) 2010 Michael Walle <michael@walle.cc>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef CPU_LM32_H
	21	#define CPU_LM32_H
	22
	23	#define TARGET_LONG_BITS 32
	24
9349b4f9	25	#define CPUArchState struct CPULM32State
81ea0e13	26
60ed8d29	27	#include "config.h"
81ea0e13	28	#include "qemu-common.h"
022c62cb	29	#include "exec/cpu-defs.h"
81ea0e13	30	struct CPULM32State;
9b9a970a	31	typedef struct CPULM32State CPULM32State;
81ea0e13 MW	32
	33	#define TARGET_HAS_ICE 1
	34
	35	#define ELF_MACHINE EM_LATTICEMICO32
	36
	37	#define NB_MMU_MODES 1
	38	#define TARGET_PAGE_BITS 12
6393c08d	39	static inline int cpu_mmu_index(CPULM32State *env)
81ea0e13 MW	40	{
	41	return 0;
	42	}
	43
	44	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	45	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	46
	47	/* Exceptions indices */
	48	enum {
	49	EXCP_RESET = 0,
	50	EXCP_BREAKPOINT,
	51	EXCP_INSN_BUS_ERROR,
	52	EXCP_WATCHPOINT,
	53	EXCP_DATA_BUS_ERROR,
	54	EXCP_DIVIDE_BY_ZERO,
	55	EXCP_IRQ,
	56	EXCP_SYSTEMCALL
	57	};
	58
	59	/* Registers */
	60	enum {
	61	R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10,
	62	R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20,
	63	R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30,
	64	R_R31
	65	};
	66
	67	/* Register aliases */
	68	enum {
	69	R_GP = R_R26,
	70	R_FP = R_R27,
	71	R_SP = R_R28,
	72	R_RA = R_R29,
	73	R_EA = R_R30,
	74	R_BA = R_R31
	75	};
	76
	77	/* IE flags */
	78	enum {
	79	IE_IE = (1<<0),
	80	IE_EIE = (1<<1),
	81	IE_BIE = (1<<2),
	82	};
	83
	84	/* DC flags */
	85	enum {
	86	DC_SS = (1<<0),
	87	DC_RE = (1<<1),
	88	DC_C0 = (1<<2),
	89	DC_C1 = (1<<3),
	90	DC_C2 = (1<<4),
	91	DC_C3 = (1<<5),
	92	};
	93
	94	/* CFG mask */
	95	enum {
	96	CFG_M = (1<<0),
	97	CFG_D = (1<<1),
	98	CFG_S = (1<<2),
	99	CFG_U = (1<<3),
	100	CFG_X = (1<<4),
	101	CFG_CC = (1<<5),
	102	CFG_IC = (1<<6),
	103	CFG_DC = (1<<7),
104	CFG_G = (1<<8),
105	CFG_H = (1<<9),
106	CFG_R = (1<<10),
107	CFG_J = (1<<11),
108	CFG_INT_SHIFT = 12,
109	CFG_BP_SHIFT = 18,
110	CFG_WP_SHIFT = 22,
111	CFG_REV_SHIFT = 26,
112	};
113
114	/* CSRs */
115	enum {
116	CSR_IE = 0x00,
117	CSR_IM = 0x01,
118	CSR_IP = 0x02,
119	CSR_ICC = 0x03,
120	CSR_DCC = 0x04,
121	CSR_CC = 0x05,
122	CSR_CFG = 0x06,
123	CSR_EBA = 0x07,
124	CSR_DC = 0x08,
125	CSR_DEBA = 0x09,
126	CSR_JTX = 0x0e,
127	CSR_JRX = 0x0f,
128	CSR_BP0 = 0x10,
129	CSR_BP1 = 0x11,
130	CSR_BP2 = 0x12,
131	CSR_BP3 = 0x13,
132	CSR_WP0 = 0x18,
133	CSR_WP1 = 0x19,
134	CSR_WP2 = 0x1a,
135	CSR_WP3 = 0x1b,
136	};
137
138	enum {
139	LM32_FEATURE_MULTIPLY = 1,
140	LM32_FEATURE_DIVIDE = 2,
141	LM32_FEATURE_SHIFT = 4,
142	LM32_FEATURE_SIGN_EXTEND = 8,
143	LM32_FEATURE_I_CACHE = 16,
144	LM32_FEATURE_D_CACHE = 32,
145	LM32_FEATURE_CYCLE_COUNT = 64,
146	};
147
148	enum {
149	LM32_FLAG_IGNORE_MSB = 1,
150	};
151
ae7d54d4	152	struct CPULM32State {
81ea0e13 MW	153	/* general registers */
	154	uint32_t regs[32];
	155
	156	/* special registers */
	157	uint32_t pc; /* program counter */
	158	uint32_t ie; /* interrupt enable */
	159	uint32_t icc; /* instruction cache control */
	160	uint32_t dcc; /* data cache control */
	161	uint32_t cc; /* cycle counter */
	162	uint32_t cfg; /* configuration */
	163
	164	/* debug registers */
	165	uint32_t dc; /* debug control */
	166	uint32_t bp[4]; /* breakpoint addresses */
	167	uint32_t wp[4]; /* watchpoint addresses */
	168
	169	CPU_COMMON
	170
	171	uint32_t eba; /* exception base address */
	172	uint32_t deba; /* debug exception base address */
	173
	174	/* interrupt controller handle for callbacks */
	175	DeviceState *pic_state;
	176	/* JTAG UART handle for callbacks */
	177	DeviceState *juart_state;
	178
	179	/* processor core features */
	180	uint32_t features;
	181	uint32_t flags;
	182	uint8_t num_bps;
	183	uint8_t num_wps;
	184
ae7d54d4	185	};
81ea0e13	186
fc0ced2f	187	#include "cpu-qom.h"
81ea0e13	188
0347d689	189	LM32CPU cpu_lm32_init(const char cpu_model);
81ea0e13	190	void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
6393c08d AF	191	int cpu_lm32_exec(CPULM32State *s);
	192	void cpu_lm32_close(CPULM32State *s);
	193	void do_interrupt(CPULM32State *env);
81ea0e13 MW	194	/* you can call this signal handler from your SIGBUS and SIGSEGV
	195	signal handlers to inform the virtual CPU of exceptions. non zero
	196	is returned if the signal was handled by the virtual CPU. */
	197	int cpu_lm32_signal_handler(int host_signum, void *pinfo,
	198	void *puc);
	199	void lm32_translate_init(void);
6393c08d	200	void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
81ea0e13	201
0347d689 AF	202	static inline CPULM32State cpu_init(const char cpu_model)
	203	{
	204	LM32CPU *cpu = cpu_lm32_init(cpu_model);
	205	if (cpu == NULL) {
	206	return NULL;
	207	}
	208	return &cpu->env;
	209	}
	210
81ea0e13	211	#define cpu_list cpu_lm32_list
81ea0e13 MW	212	#define cpu_exec cpu_lm32_exec
	213	#define cpu_gen_code cpu_lm32_gen_code
	214	#define cpu_signal_handler cpu_lm32_signal_handler
	215
	216	#define CPU_SAVE_VERSION 1
	217
6393c08d	218	int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
97b348e7	219	int mmu_idx);
81ea0e13 MW	220	#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
	221
	222	#if defined(CONFIG_USER_ONLY)
6393c08d	223	static inline void cpu_clone_regs(CPULM32State *env, target_ulong newsp)
81ea0e13 MW	224	{
	225	if (newsp) {
	226	env->regs[R_SP] = newsp;
	227	}
	228	env->regs[R_R1] = 0;
	229	}
	230	#endif
	231
6393c08d	232	static inline void cpu_set_tls(CPULM32State *env, target_ulong newtls)
81ea0e13 MW	233	{
	234	}
	235
6393c08d	236	static inline int cpu_interrupts_enabled(CPULM32State *env)
81ea0e13 MW	237	{
	238	return env->ie & IE_IE;
	239	}
	240
022c62cb	241	#include "exec/cpu-all.h"
81ea0e13	242
6393c08d	243	static inline target_ulong cpu_get_pc(CPULM32State *env)
81ea0e13 MW	244	{
	245	return env->pc;
	246	}
	247
6393c08d	248	static inline void cpu_get_tb_cpu_state(CPULM32State env, target_ulong pc,
81ea0e13 MW	249	target_ulong cs_base, int flags)
	250	{
	251	*pc = env->pc;
	252	*cs_base = 0;
	253	*flags = 0;
	254	}
f081c76c	255
3993c6bd	256	static inline bool cpu_has_work(CPUState *cpu)
f081c76c	257	{
3993c6bd AF	258	CPULM32State *env = &LM32_CPU(cpu)->env;
3993c6bd AF	259
f081c76c BS	260	return env->interrupt_request & CPU_INTERRUPT_HARD;
	261	}
	262
022c62cb	263	#include "exec/exec-all.h"
f081c76c	264
6393c08d	265	static inline void cpu_pc_from_tb(CPULM32State env, TranslationBlock tb)
f081c76c BS	266	{
	267	env->pc = tb->pc;
	268	}
	269
81ea0e13	270	#endif