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Merge remote-tracking branch 'jasowang/tags/net-pull-request' into staging
[mirror_qemu.git] / target-lm32 / translate.c
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17c0fa3d
MW		 1/*
2 * LatticeMico32 main translation routines.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
ea99dde1 20#include "qemu/osdep.h"
17c0fa3d 21#include "cpu.h"
76cad711 22#include "disas/disas.h"
2ef6175a 23#include "exec/helper-proto.h"
63c91552 24#include "exec/exec-all.h"
17c0fa3d 25#include "tcg-op.h"
17c0fa3d 26
f08b6170 27#include "exec/cpu_ldst.h"
0d09e41a 28#include "hw/lm32/lm32_pic.h"
17c0fa3d 29
2ef6175a 30#include "exec/helper-gen.h"
17c0fa3d 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
a7e30d84
LV		 34
35
19f846b1
MW		 36#define DISAS_LM32 0
37
38#define LOG_DIS(...) \
39 do { \
40 if (DISAS_LM32) { \
41 qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
42 } \
43 } while (0)
17c0fa3d
MW		 44
45#define EXTRACT_FIELD(src, start, end) \
46 (((src) >> start) & ((1 << (end - start + 1)) - 1))
47
48#define MEM_INDEX 0
49
1bcea73e 50static TCGv_env cpu_env;
17c0fa3d
MW		 51static TCGv cpu_R[32];
52static TCGv cpu_pc;
53static TCGv cpu_ie;
54static TCGv cpu_icc;
55static TCGv cpu_dcc;
56static TCGv cpu_cc;
57static TCGv cpu_cfg;
58static TCGv cpu_eba;
59static TCGv cpu_dc;
60static TCGv cpu_deba;
61static TCGv cpu_bp[4];
62static TCGv cpu_wp[4];
63
022c62cb 64#include "exec/gen-icount.h"
17c0fa3d
MW		 65
66enum {
67 OP_FMT_RI,
68 OP_FMT_RR,
69 OP_FMT_CR,
70 OP_FMT_I
71};
72
73/* This is the state at translation time. */
74typedef struct DisasContext {
17c0fa3d
MW		 75 target_ulong pc;
76
77 /* Decoder. */
78 int format;
79 uint32_t ir;
80 uint8_t opcode;
81 uint8_t r0, r1, r2, csr;
82 uint16_t imm5;
83 uint16_t imm16;
84 uint32_t imm26;
85
86 unsigned int delayed_branch;
87 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
88 int is_jmp;
89
17c0fa3d
MW		 90 struct TranslationBlock *tb;
91 int singlestep_enabled;
34f4aa83
MW		 92
93 uint32_t features;
94 uint8_t num_breakpoints;
95 uint8_t num_watchpoints;
17c0fa3d
MW		 96} DisasContext;
97
98static const char *regnames[] = {
99 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
101 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
102 "r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra",
103 "r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0",
104 "wp1", "wp2", "wp3"
105};
106
107static inline int zero_extend(unsigned int val, int width)
108{
109 return val & ((1 << width) - 1);
110}
111
112static inline int sign_extend(unsigned int val, int width)
113{
114 int sval;
115
116 /* LSL. */
117 val <<= 32 - width;
118 sval = val;
119 /* ASR. */
120 sval >>= 32 - width;
121
122 return sval;
123}
124
125static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
126{
127 TCGv_i32 tmp = tcg_const_i32(index);
128
32ac0ca2 129 gen_helper_raise_exception(cpu_env, tmp);
17c0fa3d
MW		 130 tcg_temp_free_i32(tmp);
131}
132
667ff961
MW		 133static inline void t_gen_illegal_insn(DisasContext *dc)
134{
135 tcg_gen_movi_tl(cpu_pc, dc->pc);
136 gen_helper_ill(cpu_env);
137}
138
90aa39a1 139static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
17c0fa3d 140{
90aa39a1
SF		 141 if (unlikely(dc->singlestep_enabled)) {
142 return false;
143 }
144
145#ifndef CONFIG_USER_ONLY
146 return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
147#else
148 return true;
149#endif
150}
17c0fa3d 151
90aa39a1
SF		 152static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
153{
154 if (use_goto_tb(dc, dest)) {
17c0fa3d
MW		 155 tcg_gen_goto_tb(n);
156 tcg_gen_movi_tl(cpu_pc, dest);
90aa39a1 157 tcg_gen_exit_tb((uintptr_t)dc->tb + n);
17c0fa3d
MW		 158 } else {
159 tcg_gen_movi_tl(cpu_pc, dest);
160 if (dc->singlestep_enabled) {
161 t_gen_raise_exception(dc, EXCP_DEBUG);
162 }
163 tcg_gen_exit_tb(0);
164 }
165}
166
167static void dec_add(DisasContext *dc)
168{
169 if (dc->format == OP_FMT_RI) {
170 if (dc->r0 == R_R0) {
171 if (dc->r1 == R_R0 && dc->imm16 == 0) {
172 LOG_DIS("nop\n");
173 } else {
174 LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16));
175 }
176 } else {
177 LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
178 sign_extend(dc->imm16, 16));
179 }
180 } else {
181 LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
182 }
183
184 if (dc->format == OP_FMT_RI) {
185 tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
186 sign_extend(dc->imm16, 16));
187 } else {
188 tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
189 }
190}
191
192static void dec_and(DisasContext *dc)
193{
194 if (dc->format == OP_FMT_RI) {
195 LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
196 zero_extend(dc->imm16, 16));
197 } else {
198 LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
199 }
200
201 if (dc->format == OP_FMT_RI) {
202 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
203 zero_extend(dc->imm16, 16));
204 } else {
205 if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
206 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
32ac0ca2 207 gen_helper_hlt(cpu_env);
17c0fa3d
MW		 208 } else {
209 tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
210 }
211 }
212}
213
214static void dec_andhi(DisasContext *dc)
215{
95f7983b 216 LOG_DIS("andhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
17c0fa3d
MW		 217
218 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
219}
220
221static void dec_b(DisasContext *dc)
222{
223 if (dc->r0 == R_RA) {
224 LOG_DIS("ret\n");
225 } else if (dc->r0 == R_EA) {
226 LOG_DIS("eret\n");
227 } else if (dc->r0 == R_BA) {
228 LOG_DIS("bret\n");
229 } else {
230 LOG_DIS("b r%d\n", dc->r0);
231 }
232
233 /* restore IE.IE in case of an eret */
234 if (dc->r0 == R_EA) {
235 TCGv t0 = tcg_temp_new();
42a268c2 236 TCGLabel *l1 = gen_new_label();
17c0fa3d
MW		 237 tcg_gen_andi_tl(t0, cpu_ie, IE_EIE);
238 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
239 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1);
240 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
241 gen_set_label(l1);
242 tcg_temp_free(t0);
243 } else if (dc->r0 == R_BA) {
244 TCGv t0 = tcg_temp_new();
42a268c2 245 TCGLabel *l1 = gen_new_label();
17c0fa3d
MW		 246 tcg_gen_andi_tl(t0, cpu_ie, IE_BIE);
247 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
248 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1);
249 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
250 gen_set_label(l1);
251 tcg_temp_free(t0);
252 }
253 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
254
255 dc->is_jmp = DISAS_JUMP;
256}
257
258static void dec_bi(DisasContext *dc)
259{
260 LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26));
261
262 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
263
264 dc->is_jmp = DISAS_TB_JUMP;
265}
266
267static inline void gen_cond_branch(DisasContext *dc, int cond)
268{
42a268c2 269 TCGLabel *l1 = gen_new_label();
17c0fa3d
MW		 270 tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1);
271 gen_goto_tb(dc, 0, dc->pc + 4);
272 gen_set_label(l1);
273 gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16)));
274 dc->is_jmp = DISAS_TB_JUMP;
275}
276
277static void dec_be(DisasContext *dc)
278{
95f7983b 279 LOG_DIS("be r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 280 sign_extend(dc->imm16, 16) * 4);
281
282 gen_cond_branch(dc, TCG_COND_EQ);
283}
284
285static void dec_bg(DisasContext *dc)
286{
95f7983b 287 LOG_DIS("bg r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 288 sign_extend(dc->imm16, 16 * 4));
289
290 gen_cond_branch(dc, TCG_COND_GT);
291}
292
293static void dec_bge(DisasContext *dc)
294{
95f7983b 295 LOG_DIS("bge r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 296 sign_extend(dc->imm16, 16) * 4);
297
298 gen_cond_branch(dc, TCG_COND_GE);
299}
300
301static void dec_bgeu(DisasContext *dc)
302{
95f7983b 303 LOG_DIS("bgeu r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 304 sign_extend(dc->imm16, 16) * 4);
305
306 gen_cond_branch(dc, TCG_COND_GEU);
307}
308
309static void dec_bgu(DisasContext *dc)
310{
95f7983b 311 LOG_DIS("bgu r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 312 sign_extend(dc->imm16, 16) * 4);
313
314 gen_cond_branch(dc, TCG_COND_GTU);
315}
316
317static void dec_bne(DisasContext *dc)
318{
95f7983b 319 LOG_DIS("bne r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 320 sign_extend(dc->imm16, 16) * 4);
321
322 gen_cond_branch(dc, TCG_COND_NE);
323}
324
325static void dec_call(DisasContext *dc)
326{
327 LOG_DIS("call r%d\n", dc->r0);
328
329 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
330 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
331
332 dc->is_jmp = DISAS_JUMP;
333}
334
335static void dec_calli(DisasContext *dc)
336{
337 LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4);
338
339 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
340 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
341
342 dc->is_jmp = DISAS_TB_JUMP;
343}
344
345static inline void gen_compare(DisasContext *dc, int cond)
346{
df5eb7d2 347 int i;
17c0fa3d
MW		 348
349 if (dc->format == OP_FMT_RI) {
df5eb7d2
MW		 350 switch (cond) {
351 case TCG_COND_GEU:
352 case TCG_COND_GTU:
353 i = zero_extend(dc->imm16, 16);
354 break;
355 default:
356 i = sign_extend(dc->imm16, 16);
357 break;
358 }
359
0a04e11f 360 tcg_gen_setcondi_tl(cond, cpu_R[dc->r1], cpu_R[dc->r0], i);
17c0fa3d 361 } else {
0a04e11f 362 tcg_gen_setcond_tl(cond, cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
17c0fa3d
MW		 363 }
364}
365
366static void dec_cmpe(DisasContext *dc)
367{
368 if (dc->format == OP_FMT_RI) {
95f7983b 369 LOG_DIS("cmpei r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 370 sign_extend(dc->imm16, 16));
371 } else {
372 LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
373 }
374
375 gen_compare(dc, TCG_COND_EQ);
376}
377
378static void dec_cmpg(DisasContext *dc)
379{
380 if (dc->format == OP_FMT_RI) {
95f7983b 381 LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 382 sign_extend(dc->imm16, 16));
383 } else {
384 LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
385 }
386
387 gen_compare(dc, TCG_COND_GT);
388}
389
390static void dec_cmpge(DisasContext *dc)
391{
392 if (dc->format == OP_FMT_RI) {
95f7983b 393 LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 394 sign_extend(dc->imm16, 16));
395 } else {
396 LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
397 }
398
399 gen_compare(dc, TCG_COND_GE);
400}
401
402static void dec_cmpgeu(DisasContext *dc)
403{
404 if (dc->format == OP_FMT_RI) {
95f7983b 405 LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r1, dc->r0,
df5eb7d2 406 zero_extend(dc->imm16, 16));
17c0fa3d
MW		 407 } else {
408 LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
409 }
410
411 gen_compare(dc, TCG_COND_GEU);
412}
413
414static void dec_cmpgu(DisasContext *dc)
415{
416 if (dc->format == OP_FMT_RI) {
95f7983b 417 LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r1, dc->r0,
df5eb7d2 418 zero_extend(dc->imm16, 16));
17c0fa3d
MW		 419 } else {
420 LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
421 }
422
423 gen_compare(dc, TCG_COND_GTU);
424}
425
426static void dec_cmpne(DisasContext *dc)
427{
428 if (dc->format == OP_FMT_RI) {
95f7983b 429 LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 430 sign_extend(dc->imm16, 16));
431 } else {
432 LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
433 }
434
435 gen_compare(dc, TCG_COND_NE);
436}
437
438static void dec_divu(DisasContext *dc)
439{
42a268c2 440 TCGLabel *l1;
17c0fa3d
MW		 441
442 LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
443
34f4aa83 444 if (!(dc->features & LM32_FEATURE_DIVIDE)) {
3604a76f 445 qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
667ff961 446 t_gen_illegal_insn(dc);
3604a76f 447 return;
17c0fa3d
MW		 448 }
449
450 l1 = gen_new_label();
451 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
452 tcg_gen_movi_tl(cpu_pc, dc->pc);
453 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
454 gen_set_label(l1);
455 tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
456}
457
458static void dec_lb(DisasContext *dc)
459{
460 TCGv t0;
461
462 LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
463
464 t0 = tcg_temp_new();
465 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
466 tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX);
467 tcg_temp_free(t0);
468}
469
470static void dec_lbu(DisasContext *dc)
471{
472 TCGv t0;
473
474 LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
475
476 t0 = tcg_temp_new();
477 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
478 tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX);
479 tcg_temp_free(t0);
480}
481
482static void dec_lh(DisasContext *dc)
483{
484 TCGv t0;
485
486 LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
487
488 t0 = tcg_temp_new();
489 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
490 tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX);
491 tcg_temp_free(t0);
492}
493
494static void dec_lhu(DisasContext *dc)
495{
496 TCGv t0;
497
498 LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
499
500 t0 = tcg_temp_new();
501 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
502 tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX);
503 tcg_temp_free(t0);
504}
505
506static void dec_lw(DisasContext *dc)
507{
508 TCGv t0;
509
510 LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16));
511
512 t0 = tcg_temp_new();
513 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
514 tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX);
515 tcg_temp_free(t0);
516}
517
518static void dec_modu(DisasContext *dc)
519{
42a268c2 520 TCGLabel *l1;
17c0fa3d
MW		 521
522 LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
523
34f4aa83 524 if (!(dc->features & LM32_FEATURE_DIVIDE)) {
3604a76f 525 qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
667ff961 526 t_gen_illegal_insn(dc);
3604a76f 527 return;
17c0fa3d
MW		 528 }
529
530 l1 = gen_new_label();
531 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
532 tcg_gen_movi_tl(cpu_pc, dc->pc);
533 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
534 gen_set_label(l1);
535 tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
536}
537
538static void dec_mul(DisasContext *dc)
539{
540 if (dc->format == OP_FMT_RI) {
95f7983b 541 LOG_DIS("muli r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 542 sign_extend(dc->imm16, 16));
543 } else {
544 LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
545 }
546
34f4aa83 547 if (!(dc->features & LM32_FEATURE_MULTIPLY)) {
3604a76f
MW		 548 qemu_log_mask(LOG_GUEST_ERROR,
549 "hardware multiplier is not available\n");
667ff961 550 t_gen_illegal_insn(dc);
3604a76f 551 return;
17c0fa3d
MW		 552 }
553
554 if (dc->format == OP_FMT_RI) {
555 tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0],
556 sign_extend(dc->imm16, 16));
557 } else {
558 tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
559 }
560}
561
562static void dec_nor(DisasContext *dc)
563{
564 if (dc->format == OP_FMT_RI) {
95f7983b 565 LOG_DIS("nori r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 566 zero_extend(dc->imm16, 16));
567 } else {
568 LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
569 }
570
571 if (dc->format == OP_FMT_RI) {
572 TCGv t0 = tcg_temp_new();
573 tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
574 tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0);
575 tcg_temp_free(t0);
576 } else {
577 tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
578 }
579}
580
581static void dec_or(DisasContext *dc)
582{
583 if (dc->format == OP_FMT_RI) {
584 LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
585 zero_extend(dc->imm16, 16));
586 } else {
587 if (dc->r1 == R_R0) {
588 LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
589 } else {
590 LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
591 }
592 }
593
594 if (dc->format == OP_FMT_RI) {
595 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
596 zero_extend(dc->imm16, 16));
597 } else {
598 tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
599 }
600}
601
602static void dec_orhi(DisasContext *dc)
603{
604 if (dc->r0 == R_R0) {
605 LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
606 } else {
607 LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
608 }
609
610 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
611}
612
fcda9863 613static void dec_scall(DisasContext *dc)
17c0fa3d 614{
667ff961
MW		 615 switch (dc->imm5) {
616 case 2:
17c0fa3d 617 LOG_DIS("break\n");
17c0fa3d
MW		 618 tcg_gen_movi_tl(cpu_pc, dc->pc);
619 t_gen_raise_exception(dc, EXCP_BREAKPOINT);
667ff961
MW		 620 break;
621 case 7:
622 LOG_DIS("scall\n");
623 tcg_gen_movi_tl(cpu_pc, dc->pc);
624 t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
625 break;
626 default:
627 qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode @0x%x", dc->pc);
628 t_gen_illegal_insn(dc);
629 break;
17c0fa3d
MW		 630 }
631}
632
633static void dec_rcsr(DisasContext *dc)
634{
635 LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
636
637 switch (dc->csr) {
638 case CSR_IE:
639 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
640 break;
641 case CSR_IM:
32ac0ca2 642 gen_helper_rcsr_im(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 643 break;
644 case CSR_IP:
32ac0ca2 645 gen_helper_rcsr_ip(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 646 break;
647 case CSR_CC:
648 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
649 break;
650 case CSR_CFG:
651 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg);
652 break;
653 case CSR_EBA:
654 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba);
655 break;
656 case CSR_DC:
657 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc);
658 break;
659 case CSR_DEBA:
660 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
661 break;
662 case CSR_JTX:
32ac0ca2 663 gen_helper_rcsr_jtx(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 664 break;
665 case CSR_JRX:
32ac0ca2 666 gen_helper_rcsr_jrx(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 667 break;
668 case CSR_ICC:
669 case CSR_DCC:
670 case CSR_BP0:
671 case CSR_BP1:
672 case CSR_BP2:
673 case CSR_BP3:
674 case CSR_WP0:
675 case CSR_WP1:
676 case CSR_WP2:
677 case CSR_WP3:
3604a76f 678 qemu_log_mask(LOG_GUEST_ERROR, "invalid read access csr=%x\n", dc->csr);
17c0fa3d
MW		 679 break;
680 default:
3604a76f 681 qemu_log_mask(LOG_GUEST_ERROR, "read_csr: unknown csr=%x\n", dc->csr);
17c0fa3d
MW		 682 break;
683 }
684}
685
686static void dec_sb(DisasContext *dc)
687{
688 TCGv t0;
689
690 LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
691
692 t0 = tcg_temp_new();
693 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
694 tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX);
695 tcg_temp_free(t0);
696}
697
698static void dec_sextb(DisasContext *dc)
699{
700 LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
701
34f4aa83 702 if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
3604a76f
MW		 703 qemu_log_mask(LOG_GUEST_ERROR,
704 "hardware sign extender is not available\n");
667ff961 705 t_gen_illegal_insn(dc);
3604a76f 706 return;
17c0fa3d
MW		 707 }
708
709 tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
710}
711
712static void dec_sexth(DisasContext *dc)
713{
714 LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
715
34f4aa83 716 if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
3604a76f
MW		 717 qemu_log_mask(LOG_GUEST_ERROR,
718 "hardware sign extender is not available\n");
667ff961 719 t_gen_illegal_insn(dc);
3604a76f 720 return;
17c0fa3d
MW		 721 }
722
723 tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
724}
725
726static void dec_sh(DisasContext *dc)
727{
728 TCGv t0;
729
730 LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
731
732 t0 = tcg_temp_new();
733 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
734 tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX);
735 tcg_temp_free(t0);
736}
737
738static void dec_sl(DisasContext *dc)
739{
740 if (dc->format == OP_FMT_RI) {
741 LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
742 } else {
743 LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
744 }
745
34f4aa83 746 if (!(dc->features & LM32_FEATURE_SHIFT)) {
3604a76f 747 qemu_log_mask(LOG_GUEST_ERROR, "hardware shifter is not available\n");
667ff961 748 t_gen_illegal_insn(dc);
3604a76f 749 return;
17c0fa3d
MW		 750 }
751
752 if (dc->format == OP_FMT_RI) {
753 tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
754 } else {
755 TCGv t0 = tcg_temp_new();
756 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
757 tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
758 tcg_temp_free(t0);
759 }
760}
761
762static void dec_sr(DisasContext *dc)
763{
764 if (dc->format == OP_FMT_RI) {
765 LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
766 } else {
767 LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
768 }
769
667ff961
MW		 770 /* The real CPU (w/o hardware shifter) only supports right shift by exactly
771 * one bit */
17c0fa3d 772 if (dc->format == OP_FMT_RI) {
667ff961
MW		 773 if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
774 qemu_log_mask(LOG_GUEST_ERROR,
775 "hardware shifter is not available\n");
776 t_gen_illegal_insn(dc);
777 return;
778 }
17c0fa3d
MW		 779 tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
780 } else {
42a268c2
RH		 781 TCGLabel *l1 = gen_new_label();
782 TCGLabel *l2 = gen_new_label();
667ff961 783 TCGv t0 = tcg_temp_local_new();
17c0fa3d 784 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
667ff961
MW		 785
786 if (!(dc->features & LM32_FEATURE_SHIFT)) {
787 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
788 t_gen_illegal_insn(dc);
789 tcg_gen_br(l2);
790 }
791
792 gen_set_label(l1);
17c0fa3d 793 tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
667ff961
MW		 794 gen_set_label(l2);
795
17c0fa3d
MW		 796 tcg_temp_free(t0);
797 }
798}
799
800static void dec_sru(DisasContext *dc)
801{
802 if (dc->format == OP_FMT_RI) {
803 LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
804 } else {
805 LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
806 }
807
17c0fa3d 808 if (dc->format == OP_FMT_RI) {
667ff961
MW		 809 if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
810 qemu_log_mask(LOG_GUEST_ERROR,
811 "hardware shifter is not available\n");
812 t_gen_illegal_insn(dc);
813 return;
814 }
17c0fa3d
MW		 815 tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
816 } else {
42a268c2
RH		 817 TCGLabel *l1 = gen_new_label();
818 TCGLabel *l2 = gen_new_label();
667ff961 819 TCGv t0 = tcg_temp_local_new();
17c0fa3d 820 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
667ff961
MW		 821
822 if (!(dc->features & LM32_FEATURE_SHIFT)) {
823 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
824 t_gen_illegal_insn(dc);
825 tcg_gen_br(l2);
826 }
827
828 gen_set_label(l1);
17c0fa3d 829 tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
667ff961
MW		 830 gen_set_label(l2);
831
17c0fa3d
MW		 832 tcg_temp_free(t0);
833 }
834}
835
836static void dec_sub(DisasContext *dc)
837{
838 LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
839
840 tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
841}
842
843static void dec_sw(DisasContext *dc)
844{
845 TCGv t0;
846
847 LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1);
848
849 t0 = tcg_temp_new();
850 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
851 tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX);
852 tcg_temp_free(t0);
853}
854
855static void dec_user(DisasContext *dc)
856{
857 LOG_DIS("user");
858
3604a76f 859 qemu_log_mask(LOG_GUEST_ERROR, "user instruction undefined\n");
667ff961 860 t_gen_illegal_insn(dc);
17c0fa3d
MW		 861}
862
863static void dec_wcsr(DisasContext *dc)
864{
865 int no;
866
49285e11 867 LOG_DIS("wcsr %d, r%d\n", dc->csr, dc->r1);
17c0fa3d
MW		 868
869 switch (dc->csr) {
870 case CSR_IE:
871 tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]);
872 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
873 dc->is_jmp = DISAS_UPDATE;
874 break;
875 case CSR_IM:
876 /* mark as an io operation because it could cause an interrupt */
bd79255d 877 if (dc->tb->cflags & CF_USE_ICOUNT) {
17c0fa3d
MW		 878 gen_io_start();
879 }
32ac0ca2 880 gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
17c0fa3d 881 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
bd79255d 882 if (dc->tb->cflags & CF_USE_ICOUNT) {
17c0fa3d
MW		 883 gen_io_end();
884 }
885 dc->is_jmp = DISAS_UPDATE;
886 break;
887 case CSR_IP:
888 /* mark as an io operation because it could cause an interrupt */
bd79255d 889 if (dc->tb->cflags & CF_USE_ICOUNT) {
17c0fa3d
MW		 890 gen_io_start();
891 }
32ac0ca2 892 gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
17c0fa3d 893 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
bd79255d 894 if (dc->tb->cflags & CF_USE_ICOUNT) {
17c0fa3d
MW		 895 gen_io_end();
896 }
897 dc->is_jmp = DISAS_UPDATE;
898 break;
899 case CSR_ICC:
900 /* TODO */
901 break;
902 case CSR_DCC:
903 /* TODO */
904 break;
905 case CSR_EBA:
906 tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]);
907 break;
908 case CSR_DEBA:
909 tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
910 break;
911 case CSR_JTX:
32ac0ca2 912 gen_helper_wcsr_jtx(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 913 break;
914 case CSR_JRX:
32ac0ca2 915 gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 916 break;
917 case CSR_DC:
3dd3a2b9 918 gen_helper_wcsr_dc(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 919 break;
920 case CSR_BP0:
921 case CSR_BP1:
922 case CSR_BP2:
923 case CSR_BP3:
924 no = dc->csr - CSR_BP0;
34f4aa83 925 if (dc->num_breakpoints <= no) {
3604a76f
MW		 926 qemu_log_mask(LOG_GUEST_ERROR,
927 "breakpoint #%i is not available\n", no);
667ff961 928 t_gen_illegal_insn(dc);
3604a76f 929 break;
17c0fa3d 930 }
3dd3a2b9 931 gen_helper_wcsr_bp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
17c0fa3d
MW		 932 break;
933 case CSR_WP0:
934 case CSR_WP1:
935 case CSR_WP2:
936 case CSR_WP3:
937 no = dc->csr - CSR_WP0;
34f4aa83 938 if (dc->num_watchpoints <= no) {
3604a76f
MW		 939 qemu_log_mask(LOG_GUEST_ERROR,
940 "watchpoint #%i is not available\n", no);
667ff961 941 t_gen_illegal_insn(dc);
3604a76f 942 break;
17c0fa3d 943 }
3dd3a2b9 944 gen_helper_wcsr_wp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
17c0fa3d
MW		 945 break;
946 case CSR_CC:
947 case CSR_CFG:
3604a76f
MW		 948 qemu_log_mask(LOG_GUEST_ERROR, "invalid write access csr=%x\n",
949 dc->csr);
17c0fa3d
MW		 950 break;
951 default:
3604a76f
MW		 952 qemu_log_mask(LOG_GUEST_ERROR, "write_csr: unknown csr=%x\n",
953 dc->csr);
17c0fa3d
MW		 954 break;
955 }
956}
957
958static void dec_xnor(DisasContext *dc)
959{
960 if (dc->format == OP_FMT_RI) {
95f7983b 961 LOG_DIS("xnori r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 962 zero_extend(dc->imm16, 16));
963 } else {
964 if (dc->r1 == R_R0) {
965 LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
966 } else {
967 LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
968 }
969 }
970
971 if (dc->format == OP_FMT_RI) {
972 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
973 zero_extend(dc->imm16, 16));
974 tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]);
975 } else {
976 tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
977 }
978}
979
980static void dec_xor(DisasContext *dc)
981{
982 if (dc->format == OP_FMT_RI) {
95f7983b 983 LOG_DIS("xori r%d, r%d, %d\n", dc->r1, dc->r0,
17c0fa3d
MW		 984 zero_extend(dc->imm16, 16));
985 } else {
986 LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
987 }
988
989 if (dc->format == OP_FMT_RI) {
990 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
991 zero_extend(dc->imm16, 16));
992 } else {
993 tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
994 }
995}
996
a5086f95
MW		 997static void dec_ill(DisasContext *dc)
998{
3604a76f 999 qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode 0x%02x\n", dc->opcode);
667ff961 1000 t_gen_illegal_insn(dc);
a5086f95 1001}
17c0fa3d 1002
a5086f95 1003typedef void (*DecoderInfo)(DisasContext *dc);
17c0fa3d 1004static const DecoderInfo decinfo[] = {
a5086f95
MW		 1005 dec_sru, dec_nor, dec_mul, dec_sh, dec_lb, dec_sr, dec_xor, dec_lh,
1006 dec_and, dec_xnor, dec_lw, dec_lhu, dec_sb, dec_add, dec_or, dec_sl,
1007 dec_lbu, dec_be, dec_bg, dec_bge, dec_bgeu, dec_bgu, dec_sw, dec_bne,
1008 dec_andhi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_orhi,
1009 dec_cmpne,
1010 dec_sru, dec_nor, dec_mul, dec_divu, dec_rcsr, dec_sr, dec_xor, dec_ill,
1011 dec_and, dec_xnor, dec_ill, dec_scall, dec_sextb, dec_add, dec_or, dec_sl,
1012 dec_b, dec_modu, dec_sub, dec_user, dec_wcsr, dec_ill, dec_call, dec_sexth,
1013 dec_bi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_calli,
1014 dec_cmpne
17c0fa3d
MW		 1015};
1016
32ac0ca2 1017static inline void decode(DisasContext *dc, uint32_t ir)
17c0fa3d 1018{
32ac0ca2 1019 dc->ir = ir;
17c0fa3d
MW		 1020 LOG_DIS("%8.8x\t", dc->ir);
1021
17c0fa3d
MW		 1022 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1023
1024 dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
1025 dc->imm16 = EXTRACT_FIELD(ir, 0, 15);
1026 dc->imm26 = EXTRACT_FIELD(ir, 0, 25);
1027
1028 dc->csr = EXTRACT_FIELD(ir, 21, 25);
1029 dc->r0 = EXTRACT_FIELD(ir, 21, 25);
1030 dc->r1 = EXTRACT_FIELD(ir, 16, 20);
1031 dc->r2 = EXTRACT_FIELD(ir, 11, 15);
1032
1033 /* bit 31 seems to indicate insn type. */
1034 if (ir & (1 << 31)) {
1035 dc->format = OP_FMT_RR;
1036 } else {
1037 dc->format = OP_FMT_RI;
1038 }
1039
a5086f95
MW		 1040 assert(ARRAY_SIZE(decinfo) == 64);
1041 assert(dc->opcode < 64);
17c0fa3d 1042
a5086f95 1043 decinfo[dc->opcode](dc);
17c0fa3d
MW		 1044}
1045
17c0fa3d 1046/* generate intermediate code for basic block 'tb'. */
4e5e1215 1047void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
17c0fa3d 1048{
4e5e1215 1049 LM32CPU *cpu = lm32_env_get_cpu(env);
ed2803da 1050 CPUState *cs = CPU(cpu);
17c0fa3d 1051 struct DisasContext ctx, *dc = &ctx;
17c0fa3d 1052 uint32_t pc_start;
17c0fa3d
MW		 1053 uint32_t next_page_start;
1054 int num_insns;
1055 int max_insns;
1056
17c0fa3d 1057 pc_start = tb->pc;
34f4aa83
MW		 1058 dc->features = cpu->features;
1059 dc->num_breakpoints = cpu->num_breakpoints;
1060 dc->num_watchpoints = cpu->num_watchpoints;
17c0fa3d
MW		 1061 dc->tb = tb;
1062
17c0fa3d
MW		 1063 dc->is_jmp = DISAS_NEXT;
1064 dc->pc = pc_start;
ed2803da 1065 dc->singlestep_enabled = cs->singlestep_enabled;
17c0fa3d
MW		 1066
1067 if (pc_start & 3) {
3604a76f
MW		 1068 qemu_log_mask(LOG_GUEST_ERROR,
1069 "unaligned PC=%x. Ignoring lowest bits.\n", pc_start);
1070 pc_start &= ~3;
17c0fa3d
MW		 1071 }
1072
17c0fa3d 1073 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
17c0fa3d
MW		 1074 num_insns = 0;
1075 max_insns = tb->cflags & CF_COUNT_MASK;
1076 if (max_insns == 0) {
1077 max_insns = CF_COUNT_MASK;
1078 }
190ce7fb
RH		 1079 if (max_insns > TCG_MAX_INSNS) {
1080 max_insns = TCG_MAX_INSNS;
1081 }
17c0fa3d 1082
cd42d5b2 1083 gen_tb_start(tb);
17c0fa3d 1084 do {
667b8e29 1085 tcg_gen_insn_start(dc->pc);
959082fc 1086 num_insns++;
17c0fa3d 1087
b933066a
RH		 1088 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
1089 tcg_gen_movi_tl(cpu_pc, dc->pc);
1090 t_gen_raise_exception(dc, EXCP_DEBUG);
1091 dc->is_jmp = DISAS_UPDATE;
522a0d4e
RH		 1092 /* The address covered by the breakpoint must be included in
1093 [tb->pc, tb->pc + tb->size) in order to for it to be
1094 properly cleared -- thus we increment the PC here so that
1095 the logic setting tb->size below does the right thing. */
1096 dc->pc += 4;
b933066a
RH		 1097 break;
1098 }
1099
17c0fa3d
MW		 1100 /* Pretty disas. */
1101 LOG_DIS("%8.8x:\t", dc->pc);
1102
959082fc 1103 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
17c0fa3d
MW		 1104 gen_io_start();
1105 }
1106
32ac0ca2 1107 decode(dc, cpu_ldl_code(env, dc->pc));
17c0fa3d 1108 dc->pc += 4;
17c0fa3d 1109 } while (!dc->is_jmp
fe700adb 1110 && !tcg_op_buf_full()
ed2803da 1111 && !cs->singlestep_enabled
17c0fa3d
MW		 1112 && !singlestep
1113 && (dc->pc < next_page_start)
1114 && num_insns < max_insns);
1115
1116 if (tb->cflags & CF_LAST_IO) {
1117 gen_io_end();
1118 }
1119
ed2803da 1120 if (unlikely(cs->singlestep_enabled)) {
17c0fa3d
MW		 1121 if (dc->is_jmp == DISAS_NEXT) {
1122 tcg_gen_movi_tl(cpu_pc, dc->pc);
1123 }
1124 t_gen_raise_exception(dc, EXCP_DEBUG);
1125 } else {
1126 switch (dc->is_jmp) {
1127 case DISAS_NEXT:
1128 gen_goto_tb(dc, 1, dc->pc);
1129 break;
1130 default:
1131 case DISAS_JUMP:
1132 case DISAS_UPDATE:
1133 /* indicate that the hash table must be used
1134 to find the next TB */
1135 tcg_gen_exit_tb(0);
1136 break;
1137 case DISAS_TB_JUMP:
1138 /* nothing more to generate */
1139 break;
1140 }
1141 }
1142
806f352d 1143 gen_tb_end(tb, num_insns);
0a7df5da 1144
4e5e1215
RH		 1145 tb->size = dc->pc - pc_start;
1146 tb->icount = num_insns;
17c0fa3d
MW		 1147
1148#ifdef DEBUG_DISAS
4910e6e4
RH		 1149 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
1150 && qemu_log_in_addr_range(pc_start)) {
1ee73216 1151 qemu_log_lock();
17c0fa3d 1152 qemu_log("\n");
d49190c4 1153 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
fe700adb
RH		 1154 qemu_log("\nisize=%d osize=%d\n",
1155 dc->pc - pc_start, tcg_op_buf_count());
1ee73216 1156 qemu_log_unlock();
17c0fa3d
MW		 1157 }
1158#endif
1159}
1160
878096ee
AF		 1161void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1162 int flags)
17c0fa3d 1163{
878096ee
AF		 1164 LM32CPU *cpu = LM32_CPU(cs);
1165 CPULM32State *env = &cpu->env;
17c0fa3d
MW		 1166 int i;
1167
1168 if (!env || !f) {
1169 return;
1170 }
1171
1172 cpu_fprintf(f, "IN: PC=%x %s\n",
1173 env->pc, lookup_symbol(env->pc));
1174
1175 cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
1176 env->ie,
1177 (env->ie & IE_IE) ? 1 : 0,
1178 (env->ie & IE_EIE) ? 1 : 0,
1179 (env->ie & IE_BIE) ? 1 : 0,
1180 lm32_pic_get_im(env->pic_state),
1181 lm32_pic_get_ip(env->pic_state));
1182 cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
1183 env->eba,
1184 env->deba);
1185
1186 for (i = 0; i < 32; i++) {
1187 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1188 if ((i + 1) % 4 == 0) {
1189 cpu_fprintf(f, "\n");
1190 }
1191 }
1192 cpu_fprintf(f, "\n\n");
1193}
1194
bad729e2
RH		 1195void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb,
1196 target_ulong *data)
17c0fa3d 1197{
bad729e2 1198 env->pc = data[0];
17c0fa3d
MW		 1199}
1200
1201void lm32_translate_init(void)
1202{
1203 int i;
1204
1205 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 1206 tcg_ctx.tcg_env = cpu_env;
17c0fa3d
MW		 1207
1208 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
e1ccc054 1209 cpu_R[i] = tcg_global_mem_new(cpu_env,
6393c08d 1210 offsetof(CPULM32State, regs[i]),
17c0fa3d
MW		 1211 regnames[i]);
1212 }
1213
1214 for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
e1ccc054 1215 cpu_bp[i] = tcg_global_mem_new(cpu_env,
6393c08d 1216 offsetof(CPULM32State, bp[i]),
17c0fa3d
MW		 1217 regnames[32+i]);
1218 }
1219
1220 for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
e1ccc054 1221 cpu_wp[i] = tcg_global_mem_new(cpu_env,
6393c08d 1222 offsetof(CPULM32State, wp[i]),
17c0fa3d
MW		 1223 regnames[36+i]);
1224 }
1225
e1ccc054 1226 cpu_pc = tcg_global_mem_new(cpu_env,
6393c08d 1227 offsetof(CPULM32State, pc),
17c0fa3d 1228 "pc");
e1ccc054 1229 cpu_ie = tcg_global_mem_new(cpu_env,
6393c08d 1230 offsetof(CPULM32State, ie),
17c0fa3d 1231 "ie");
e1ccc054 1232 cpu_icc = tcg_global_mem_new(cpu_env,
6393c08d 1233 offsetof(CPULM32State, icc),
17c0fa3d 1234 "icc");
e1ccc054 1235 cpu_dcc = tcg_global_mem_new(cpu_env,
6393c08d 1236 offsetof(CPULM32State, dcc),
17c0fa3d 1237 "dcc");
e1ccc054 1238 cpu_cc = tcg_global_mem_new(cpu_env,
6393c08d 1239 offsetof(CPULM32State, cc),
17c0fa3d 1240 "cc");
e1ccc054 1241 cpu_cfg = tcg_global_mem_new(cpu_env,
6393c08d 1242 offsetof(CPULM32State, cfg),
17c0fa3d 1243 "cfg");
e1ccc054 1244 cpu_eba = tcg_global_mem_new(cpu_env,
6393c08d 1245 offsetof(CPULM32State, eba),
17c0fa3d 1246 "eba");
e1ccc054 1247 cpu_dc = tcg_global_mem_new(cpu_env,
6393c08d 1248 offsetof(CPULM32State, dc),
17c0fa3d 1249 "dc");
e1ccc054 1250 cpu_deba = tcg_global_mem_new(cpu_env,
6393c08d 1251 offsetof(CPULM32State, deba),
17c0fa3d
MW		 1252 "deba");
1253}
1254
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