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trace: [tcg] Include TCG-tracing header on all targets
[mirror_qemu.git] / target-lm32 / translate.c
CommitLineData
17c0fa3d
MW		 1/*
2 * LatticeMico32 main translation routines.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
17c0fa3d 20#include "cpu.h"
76cad711 21#include "disas/disas.h"
2ef6175a 22#include "exec/helper-proto.h"
17c0fa3d 23#include "tcg-op.h"
17c0fa3d 24
f08b6170 25#include "exec/cpu_ldst.h"
0d09e41a 26#include "hw/lm32/lm32_pic.h"
17c0fa3d 27
2ef6175a 28#include "exec/helper-gen.h"
17c0fa3d 29
a7e30d84
LV		 30#include "trace-tcg.h"
31
32
17c0fa3d
MW		 33#define DISAS_LM32 1
34#if DISAS_LM32
35# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
36#else
37# define LOG_DIS(...) do { } while (0)
38#endif
39
40#define EXTRACT_FIELD(src, start, end) \
41 (((src) >> start) & ((1 << (end - start + 1)) - 1))
42
43#define MEM_INDEX 0
44
45static TCGv_ptr cpu_env;
46static TCGv cpu_R[32];
47static TCGv cpu_pc;
48static TCGv cpu_ie;
49static TCGv cpu_icc;
50static TCGv cpu_dcc;
51static TCGv cpu_cc;
52static TCGv cpu_cfg;
53static TCGv cpu_eba;
54static TCGv cpu_dc;
55static TCGv cpu_deba;
56static TCGv cpu_bp[4];
57static TCGv cpu_wp[4];
58
022c62cb 59#include "exec/gen-icount.h"
17c0fa3d
MW		 60
61enum {
62 OP_FMT_RI,
63 OP_FMT_RR,
64 OP_FMT_CR,
65 OP_FMT_I
66};
67
68/* This is the state at translation time. */
69typedef struct DisasContext {
17c0fa3d
MW		 70 target_ulong pc;
71
72 /* Decoder. */
73 int format;
74 uint32_t ir;
75 uint8_t opcode;
76 uint8_t r0, r1, r2, csr;
77 uint16_t imm5;
78 uint16_t imm16;
79 uint32_t imm26;
80
81 unsigned int delayed_branch;
82 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
83 int is_jmp;
84
17c0fa3d
MW		 85 struct TranslationBlock *tb;
86 int singlestep_enabled;
34f4aa83
MW		 87
88 uint32_t features;
89 uint8_t num_breakpoints;
90 uint8_t num_watchpoints;
17c0fa3d
MW		 91} DisasContext;
92
93static const char *regnames[] = {
94 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
95 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra",
98 "r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0",
99 "wp1", "wp2", "wp3"
100};
101
102static inline int zero_extend(unsigned int val, int width)
103{
104 return val & ((1 << width) - 1);
105}
106
107static inline int sign_extend(unsigned int val, int width)
108{
109 int sval;
110
111 /* LSL. */
112 val <<= 32 - width;
113 sval = val;
114 /* ASR. */
115 sval >>= 32 - width;
116
117 return sval;
118}
119
120static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
121{
122 TCGv_i32 tmp = tcg_const_i32(index);
123
32ac0ca2 124 gen_helper_raise_exception(cpu_env, tmp);
17c0fa3d
MW		 125 tcg_temp_free_i32(tmp);
126}
127
667ff961
MW		 128static inline void t_gen_illegal_insn(DisasContext *dc)
129{
130 tcg_gen_movi_tl(cpu_pc, dc->pc);
131 gen_helper_ill(cpu_env);
132}
133
17c0fa3d
MW		 134static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
135{
136 TranslationBlock *tb;
137
138 tb = dc->tb;
139 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
140 likely(!dc->singlestep_enabled)) {
141 tcg_gen_goto_tb(n);
142 tcg_gen_movi_tl(cpu_pc, dest);
8cfd0495 143 tcg_gen_exit_tb((uintptr_t)tb + n);
17c0fa3d
MW		 144 } else {
145 tcg_gen_movi_tl(cpu_pc, dest);
146 if (dc->singlestep_enabled) {
147 t_gen_raise_exception(dc, EXCP_DEBUG);
148 }
149 tcg_gen_exit_tb(0);
150 }
151}
152
153static void dec_add(DisasContext *dc)
154{
155 if (dc->format == OP_FMT_RI) {
156 if (dc->r0 == R_R0) {
157 if (dc->r1 == R_R0 && dc->imm16 == 0) {
158 LOG_DIS("nop\n");
159 } else {
160 LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16));
161 }
162 } else {
163 LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
164 sign_extend(dc->imm16, 16));
165 }
166 } else {
167 LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
168 }
169
170 if (dc->format == OP_FMT_RI) {
171 tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
172 sign_extend(dc->imm16, 16));
173 } else {
174 tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
175 }
176}
177
178static void dec_and(DisasContext *dc)
179{
180 if (dc->format == OP_FMT_RI) {
181 LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
182 zero_extend(dc->imm16, 16));
183 } else {
184 LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
185 }
186
187 if (dc->format == OP_FMT_RI) {
188 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
189 zero_extend(dc->imm16, 16));
190 } else {
191 if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
192 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
32ac0ca2 193 gen_helper_hlt(cpu_env);
17c0fa3d
MW		 194 } else {
195 tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
196 }
197 }
198}
199
200static void dec_andhi(DisasContext *dc)
201{
202 LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
203
204 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
205}
206
207static void dec_b(DisasContext *dc)
208{
209 if (dc->r0 == R_RA) {
210 LOG_DIS("ret\n");
211 } else if (dc->r0 == R_EA) {
212 LOG_DIS("eret\n");
213 } else if (dc->r0 == R_BA) {
214 LOG_DIS("bret\n");
215 } else {
216 LOG_DIS("b r%d\n", dc->r0);
217 }
218
219 /* restore IE.IE in case of an eret */
220 if (dc->r0 == R_EA) {
221 TCGv t0 = tcg_temp_new();
222 int l1 = gen_new_label();
223 tcg_gen_andi_tl(t0, cpu_ie, IE_EIE);
224 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
225 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1);
226 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
227 gen_set_label(l1);
228 tcg_temp_free(t0);
229 } else if (dc->r0 == R_BA) {
230 TCGv t0 = tcg_temp_new();
231 int l1 = gen_new_label();
232 tcg_gen_andi_tl(t0, cpu_ie, IE_BIE);
233 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
234 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1);
235 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
236 gen_set_label(l1);
237 tcg_temp_free(t0);
238 }
239 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
240
241 dc->is_jmp = DISAS_JUMP;
242}
243
244static void dec_bi(DisasContext *dc)
245{
246 LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26));
247
248 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
249
250 dc->is_jmp = DISAS_TB_JUMP;
251}
252
253static inline void gen_cond_branch(DisasContext *dc, int cond)
254{
255 int l1;
256
257 l1 = gen_new_label();
258 tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1);
259 gen_goto_tb(dc, 0, dc->pc + 4);
260 gen_set_label(l1);
261 gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16)));
262 dc->is_jmp = DISAS_TB_JUMP;
263}
264
265static void dec_be(DisasContext *dc)
266{
267 LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
268 sign_extend(dc->imm16, 16) * 4);
269
270 gen_cond_branch(dc, TCG_COND_EQ);
271}
272
273static void dec_bg(DisasContext *dc)
274{
275 LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
276 sign_extend(dc->imm16, 16 * 4));
277
278 gen_cond_branch(dc, TCG_COND_GT);
279}
280
281static void dec_bge(DisasContext *dc)
282{
283 LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
284 sign_extend(dc->imm16, 16) * 4);
285
286 gen_cond_branch(dc, TCG_COND_GE);
287}
288
289static void dec_bgeu(DisasContext *dc)
290{
291 LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
292 sign_extend(dc->imm16, 16) * 4);
293
294 gen_cond_branch(dc, TCG_COND_GEU);
295}
296
297static void dec_bgu(DisasContext *dc)
298{
299 LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
300 sign_extend(dc->imm16, 16) * 4);
301
302 gen_cond_branch(dc, TCG_COND_GTU);
303}
304
305static void dec_bne(DisasContext *dc)
306{
307 LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
308 sign_extend(dc->imm16, 16) * 4);
309
310 gen_cond_branch(dc, TCG_COND_NE);
311}
312
313static void dec_call(DisasContext *dc)
314{
315 LOG_DIS("call r%d\n", dc->r0);
316
317 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
318 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
319
320 dc->is_jmp = DISAS_JUMP;
321}
322
323static void dec_calli(DisasContext *dc)
324{
325 LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4);
326
327 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
328 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
329
330 dc->is_jmp = DISAS_TB_JUMP;
331}
332
333static inline void gen_compare(DisasContext *dc, int cond)
334{
335 int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
336 int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
337 int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1;
df5eb7d2 338 int i;
17c0fa3d
MW		 339
340 if (dc->format == OP_FMT_RI) {
df5eb7d2
MW		 341 switch (cond) {
342 case TCG_COND_GEU:
343 case TCG_COND_GTU:
344 i = zero_extend(dc->imm16, 16);
345 break;
346 default:
347 i = sign_extend(dc->imm16, 16);
348 break;
349 }
350
351 tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY], i);
17c0fa3d
MW		 352 } else {
353 tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]);
354 }
355}
356
357static void dec_cmpe(DisasContext *dc)
358{
359 if (dc->format == OP_FMT_RI) {
360 LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
361 sign_extend(dc->imm16, 16));
362 } else {
363 LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
364 }
365
366 gen_compare(dc, TCG_COND_EQ);
367}
368
369static void dec_cmpg(DisasContext *dc)
370{
371 if (dc->format == OP_FMT_RI) {
372 LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
373 sign_extend(dc->imm16, 16));
374 } else {
375 LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
376 }
377
378 gen_compare(dc, TCG_COND_GT);
379}
380
381static void dec_cmpge(DisasContext *dc)
382{
383 if (dc->format == OP_FMT_RI) {
384 LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
385 sign_extend(dc->imm16, 16));
386 } else {
387 LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
388 }
389
390 gen_compare(dc, TCG_COND_GE);
391}
392
393static void dec_cmpgeu(DisasContext *dc)
394{
395 if (dc->format == OP_FMT_RI) {
396 LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
df5eb7d2 397 zero_extend(dc->imm16, 16));
17c0fa3d
MW		 398 } else {
399 LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
400 }
401
402 gen_compare(dc, TCG_COND_GEU);
403}
404
405static void dec_cmpgu(DisasContext *dc)
406{
407 if (dc->format == OP_FMT_RI) {
408 LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
df5eb7d2 409 zero_extend(dc->imm16, 16));
17c0fa3d
MW		 410 } else {
411 LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
412 }
413
414 gen_compare(dc, TCG_COND_GTU);
415}
416
417static void dec_cmpne(DisasContext *dc)
418{
419 if (dc->format == OP_FMT_RI) {
420 LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
421 sign_extend(dc->imm16, 16));
422 } else {
423 LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
424 }
425
426 gen_compare(dc, TCG_COND_NE);
427}
428
429static void dec_divu(DisasContext *dc)
430{
431 int l1;
432
433 LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
434
34f4aa83 435 if (!(dc->features & LM32_FEATURE_DIVIDE)) {
3604a76f 436 qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
667ff961 437 t_gen_illegal_insn(dc);
3604a76f 438 return;
17c0fa3d
MW		 439 }
440
441 l1 = gen_new_label();
442 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
443 tcg_gen_movi_tl(cpu_pc, dc->pc);
444 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
445 gen_set_label(l1);
446 tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
447}
448
449static void dec_lb(DisasContext *dc)
450{
451 TCGv t0;
452
453 LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
454
455 t0 = tcg_temp_new();
456 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
457 tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX);
458 tcg_temp_free(t0);
459}
460
461static void dec_lbu(DisasContext *dc)
462{
463 TCGv t0;
464
465 LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
466
467 t0 = tcg_temp_new();
468 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
469 tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX);
470 tcg_temp_free(t0);
471}
472
473static void dec_lh(DisasContext *dc)
474{
475 TCGv t0;
476
477 LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
478
479 t0 = tcg_temp_new();
480 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
481 tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX);
482 tcg_temp_free(t0);
483}
484
485static void dec_lhu(DisasContext *dc)
486{
487 TCGv t0;
488
489 LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
490
491 t0 = tcg_temp_new();
492 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
493 tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX);
494 tcg_temp_free(t0);
495}
496
497static void dec_lw(DisasContext *dc)
498{
499 TCGv t0;
500
501 LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16));
502
503 t0 = tcg_temp_new();
504 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
505 tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX);
506 tcg_temp_free(t0);
507}
508
509static void dec_modu(DisasContext *dc)
510{
511 int l1;
512
513 LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
514
34f4aa83 515 if (!(dc->features & LM32_FEATURE_DIVIDE)) {
3604a76f 516 qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
667ff961 517 t_gen_illegal_insn(dc);
3604a76f 518 return;
17c0fa3d
MW		 519 }
520
521 l1 = gen_new_label();
522 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
523 tcg_gen_movi_tl(cpu_pc, dc->pc);
524 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
525 gen_set_label(l1);
526 tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
527}
528
529static void dec_mul(DisasContext *dc)
530{
531 if (dc->format == OP_FMT_RI) {
532 LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
533 sign_extend(dc->imm16, 16));
534 } else {
535 LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
536 }
537
34f4aa83 538 if (!(dc->features & LM32_FEATURE_MULTIPLY)) {
3604a76f
MW		 539 qemu_log_mask(LOG_GUEST_ERROR,
540 "hardware multiplier is not available\n");
667ff961 541 t_gen_illegal_insn(dc);
3604a76f 542 return;
17c0fa3d
MW		 543 }
544
545 if (dc->format == OP_FMT_RI) {
546 tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0],
547 sign_extend(dc->imm16, 16));
548 } else {
549 tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
550 }
551}
552
553static void dec_nor(DisasContext *dc)
554{
555 if (dc->format == OP_FMT_RI) {
556 LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
557 zero_extend(dc->imm16, 16));
558 } else {
559 LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
560 }
561
562 if (dc->format == OP_FMT_RI) {
563 TCGv t0 = tcg_temp_new();
564 tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
565 tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0);
566 tcg_temp_free(t0);
567 } else {
568 tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
569 }
570}
571
572static void dec_or(DisasContext *dc)
573{
574 if (dc->format == OP_FMT_RI) {
575 LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
576 zero_extend(dc->imm16, 16));
577 } else {
578 if (dc->r1 == R_R0) {
579 LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
580 } else {
581 LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
582 }
583 }
584
585 if (dc->format == OP_FMT_RI) {
586 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
587 zero_extend(dc->imm16, 16));
588 } else {
589 tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
590 }
591}
592
593static void dec_orhi(DisasContext *dc)
594{
595 if (dc->r0 == R_R0) {
596 LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
597 } else {
598 LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
599 }
600
601 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
602}
603
fcda9863 604static void dec_scall(DisasContext *dc)
17c0fa3d 605{
667ff961
MW		 606 switch (dc->imm5) {
607 case 2:
17c0fa3d 608 LOG_DIS("break\n");
17c0fa3d
MW		 609 tcg_gen_movi_tl(cpu_pc, dc->pc);
610 t_gen_raise_exception(dc, EXCP_BREAKPOINT);
667ff961
MW		 611 break;
612 case 7:
613 LOG_DIS("scall\n");
614 tcg_gen_movi_tl(cpu_pc, dc->pc);
615 t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
616 break;
617 default:
618 qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode @0x%x", dc->pc);
619 t_gen_illegal_insn(dc);
620 break;
17c0fa3d
MW		 621 }
622}
623
624static void dec_rcsr(DisasContext *dc)
625{
626 LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
627
628 switch (dc->csr) {
629 case CSR_IE:
630 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
631 break;
632 case CSR_IM:
32ac0ca2 633 gen_helper_rcsr_im(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 634 break;
635 case CSR_IP:
32ac0ca2 636 gen_helper_rcsr_ip(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 637 break;
638 case CSR_CC:
639 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
640 break;
641 case CSR_CFG:
642 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg);
643 break;
644 case CSR_EBA:
645 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba);
646 break;
647 case CSR_DC:
648 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc);
649 break;
650 case CSR_DEBA:
651 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
652 break;
653 case CSR_JTX:
32ac0ca2 654 gen_helper_rcsr_jtx(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 655 break;
656 case CSR_JRX:
32ac0ca2 657 gen_helper_rcsr_jrx(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 658 break;
659 case CSR_ICC:
660 case CSR_DCC:
661 case CSR_BP0:
662 case CSR_BP1:
663 case CSR_BP2:
664 case CSR_BP3:
665 case CSR_WP0:
666 case CSR_WP1:
667 case CSR_WP2:
668 case CSR_WP3:
3604a76f 669 qemu_log_mask(LOG_GUEST_ERROR, "invalid read access csr=%x\n", dc->csr);
17c0fa3d
MW		 670 break;
671 default:
3604a76f 672 qemu_log_mask(LOG_GUEST_ERROR, "read_csr: unknown csr=%x\n", dc->csr);
17c0fa3d
MW		 673 break;
674 }
675}
676
677static void dec_sb(DisasContext *dc)
678{
679 TCGv t0;
680
681 LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
682
683 t0 = tcg_temp_new();
684 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
685 tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX);
686 tcg_temp_free(t0);
687}
688
689static void dec_sextb(DisasContext *dc)
690{
691 LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
692
34f4aa83 693 if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
3604a76f
MW		 694 qemu_log_mask(LOG_GUEST_ERROR,
695 "hardware sign extender is not available\n");
667ff961 696 t_gen_illegal_insn(dc);
3604a76f 697 return;
17c0fa3d
MW		 698 }
699
700 tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
701}
702
703static void dec_sexth(DisasContext *dc)
704{
705 LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
706
34f4aa83 707 if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
3604a76f
MW		 708 qemu_log_mask(LOG_GUEST_ERROR,
709 "hardware sign extender is not available\n");
667ff961 710 t_gen_illegal_insn(dc);
3604a76f 711 return;
17c0fa3d
MW		 712 }
713
714 tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
715}
716
717static void dec_sh(DisasContext *dc)
718{
719 TCGv t0;
720
721 LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
722
723 t0 = tcg_temp_new();
724 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
725 tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX);
726 tcg_temp_free(t0);
727}
728
729static void dec_sl(DisasContext *dc)
730{
731 if (dc->format == OP_FMT_RI) {
732 LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
733 } else {
734 LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
735 }
736
34f4aa83 737 if (!(dc->features & LM32_FEATURE_SHIFT)) {
3604a76f 738 qemu_log_mask(LOG_GUEST_ERROR, "hardware shifter is not available\n");
667ff961 739 t_gen_illegal_insn(dc);
3604a76f 740 return;
17c0fa3d
MW		 741 }
742
743 if (dc->format == OP_FMT_RI) {
744 tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
745 } else {
746 TCGv t0 = tcg_temp_new();
747 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
748 tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
749 tcg_temp_free(t0);
750 }
751}
752
753static void dec_sr(DisasContext *dc)
754{
755 if (dc->format == OP_FMT_RI) {
756 LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
757 } else {
758 LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
759 }
760
667ff961
MW		 761 /* The real CPU (w/o hardware shifter) only supports right shift by exactly
762 * one bit */
17c0fa3d 763 if (dc->format == OP_FMT_RI) {
667ff961
MW		 764 if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
765 qemu_log_mask(LOG_GUEST_ERROR,
766 "hardware shifter is not available\n");
767 t_gen_illegal_insn(dc);
768 return;
769 }
17c0fa3d
MW		 770 tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
771 } else {
667ff961
MW		 772 int l1 = gen_new_label();
773 int l2 = gen_new_label();
774 TCGv t0 = tcg_temp_local_new();
17c0fa3d 775 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
667ff961
MW		 776
777 if (!(dc->features & LM32_FEATURE_SHIFT)) {
778 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
779 t_gen_illegal_insn(dc);
780 tcg_gen_br(l2);
781 }
782
783 gen_set_label(l1);
17c0fa3d 784 tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
667ff961
MW		 785 gen_set_label(l2);
786
17c0fa3d
MW		 787 tcg_temp_free(t0);
788 }
789}
790
791static void dec_sru(DisasContext *dc)
792{
793 if (dc->format == OP_FMT_RI) {
794 LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
795 } else {
796 LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
797 }
798
17c0fa3d 799 if (dc->format == OP_FMT_RI) {
667ff961
MW		 800 if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
801 qemu_log_mask(LOG_GUEST_ERROR,
802 "hardware shifter is not available\n");
803 t_gen_illegal_insn(dc);
804 return;
805 }
17c0fa3d
MW		 806 tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
807 } else {
667ff961
MW		 808 int l1 = gen_new_label();
809 int l2 = gen_new_label();
810 TCGv t0 = tcg_temp_local_new();
17c0fa3d 811 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
667ff961
MW		 812
813 if (!(dc->features & LM32_FEATURE_SHIFT)) {
814 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
815 t_gen_illegal_insn(dc);
816 tcg_gen_br(l2);
817 }
818
819 gen_set_label(l1);
17c0fa3d 820 tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
667ff961
MW		 821 gen_set_label(l2);
822
17c0fa3d
MW		 823 tcg_temp_free(t0);
824 }
825}
826
827static void dec_sub(DisasContext *dc)
828{
829 LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
830
831 tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
832}
833
834static void dec_sw(DisasContext *dc)
835{
836 TCGv t0;
837
838 LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1);
839
840 t0 = tcg_temp_new();
841 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
842 tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX);
843 tcg_temp_free(t0);
844}
845
846static void dec_user(DisasContext *dc)
847{
848 LOG_DIS("user");
849
3604a76f 850 qemu_log_mask(LOG_GUEST_ERROR, "user instruction undefined\n");
667ff961 851 t_gen_illegal_insn(dc);
17c0fa3d
MW		 852}
853
854static void dec_wcsr(DisasContext *dc)
855{
856 int no;
857
858 LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
859
860 switch (dc->csr) {
861 case CSR_IE:
862 tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]);
863 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
864 dc->is_jmp = DISAS_UPDATE;
865 break;
866 case CSR_IM:
867 /* mark as an io operation because it could cause an interrupt */
868 if (use_icount) {
869 gen_io_start();
870 }
32ac0ca2 871 gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 872 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
873 if (use_icount) {
874 gen_io_end();
875 }
876 dc->is_jmp = DISAS_UPDATE;
877 break;
878 case CSR_IP:
879 /* mark as an io operation because it could cause an interrupt */
880 if (use_icount) {
881 gen_io_start();
882 }
32ac0ca2 883 gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 884 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
885 if (use_icount) {
886 gen_io_end();
887 }
888 dc->is_jmp = DISAS_UPDATE;
889 break;
890 case CSR_ICC:
891 /* TODO */
892 break;
893 case CSR_DCC:
894 /* TODO */
895 break;
896 case CSR_EBA:
897 tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]);
898 break;
899 case CSR_DEBA:
900 tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
901 break;
902 case CSR_JTX:
32ac0ca2 903 gen_helper_wcsr_jtx(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 904 break;
905 case CSR_JRX:
32ac0ca2 906 gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 907 break;
908 case CSR_DC:
3dd3a2b9 909 gen_helper_wcsr_dc(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 910 break;
911 case CSR_BP0:
912 case CSR_BP1:
913 case CSR_BP2:
914 case CSR_BP3:
915 no = dc->csr - CSR_BP0;
34f4aa83 916 if (dc->num_breakpoints <= no) {
3604a76f
MW		 917 qemu_log_mask(LOG_GUEST_ERROR,
918 "breakpoint #%i is not available\n", no);
667ff961 919 t_gen_illegal_insn(dc);
3604a76f 920 break;
17c0fa3d 921 }
3dd3a2b9 922 gen_helper_wcsr_bp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
17c0fa3d
MW		 923 break;
924 case CSR_WP0:
925 case CSR_WP1:
926 case CSR_WP2:
927 case CSR_WP3:
928 no = dc->csr - CSR_WP0;
34f4aa83 929 if (dc->num_watchpoints <= no) {
3604a76f
MW		 930 qemu_log_mask(LOG_GUEST_ERROR,
931 "watchpoint #%i is not available\n", no);
667ff961 932 t_gen_illegal_insn(dc);
3604a76f 933 break;
17c0fa3d 934 }
3dd3a2b9 935 gen_helper_wcsr_wp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
17c0fa3d
MW		 936 break;
937 case CSR_CC:
938 case CSR_CFG:
3604a76f
MW		 939 qemu_log_mask(LOG_GUEST_ERROR, "invalid write access csr=%x\n",
940 dc->csr);
17c0fa3d
MW		 941 break;
942 default:
3604a76f
MW		 943 qemu_log_mask(LOG_GUEST_ERROR, "write_csr: unknown csr=%x\n",
944 dc->csr);
17c0fa3d
MW		 945 break;
946 }
947}
948
949static void dec_xnor(DisasContext *dc)
950{
951 if (dc->format == OP_FMT_RI) {
952 LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
953 zero_extend(dc->imm16, 16));
954 } else {
955 if (dc->r1 == R_R0) {
956 LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
957 } else {
958 LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
959 }
960 }
961
962 if (dc->format == OP_FMT_RI) {
963 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
964 zero_extend(dc->imm16, 16));
965 tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]);
966 } else {
967 tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
968 }
969}
970
971static void dec_xor(DisasContext *dc)
972{
973 if (dc->format == OP_FMT_RI) {
974 LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
975 zero_extend(dc->imm16, 16));
976 } else {
977 LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
978 }
979
980 if (dc->format == OP_FMT_RI) {
981 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
982 zero_extend(dc->imm16, 16));
983 } else {
984 tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
985 }
986}
987
a5086f95
MW		 988static void dec_ill(DisasContext *dc)
989{
3604a76f 990 qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode 0x%02x\n", dc->opcode);
667ff961 991 t_gen_illegal_insn(dc);
a5086f95 992}
17c0fa3d 993
a5086f95 994typedef void (*DecoderInfo)(DisasContext *dc);
17c0fa3d 995static const DecoderInfo decinfo[] = {
a5086f95
MW		 996 dec_sru, dec_nor, dec_mul, dec_sh, dec_lb, dec_sr, dec_xor, dec_lh,
997 dec_and, dec_xnor, dec_lw, dec_lhu, dec_sb, dec_add, dec_or, dec_sl,
998 dec_lbu, dec_be, dec_bg, dec_bge, dec_bgeu, dec_bgu, dec_sw, dec_bne,
999 dec_andhi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_orhi,
1000 dec_cmpne,
1001 dec_sru, dec_nor, dec_mul, dec_divu, dec_rcsr, dec_sr, dec_xor, dec_ill,
1002 dec_and, dec_xnor, dec_ill, dec_scall, dec_sextb, dec_add, dec_or, dec_sl,
1003 dec_b, dec_modu, dec_sub, dec_user, dec_wcsr, dec_ill, dec_call, dec_sexth,
1004 dec_bi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_calli,
1005 dec_cmpne
17c0fa3d
MW		 1006};
1007
32ac0ca2 1008static inline void decode(DisasContext *dc, uint32_t ir)
17c0fa3d 1009{
fdefe51c 1010 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
17c0fa3d
MW		 1011 tcg_gen_debug_insn_start(dc->pc);
1012 }
1013
32ac0ca2 1014 dc->ir = ir;
17c0fa3d
MW		 1015 LOG_DIS("%8.8x\t", dc->ir);
1016
17c0fa3d
MW		 1017 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1018
1019 dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
1020 dc->imm16 = EXTRACT_FIELD(ir, 0, 15);
1021 dc->imm26 = EXTRACT_FIELD(ir, 0, 25);
1022
1023 dc->csr = EXTRACT_FIELD(ir, 21, 25);
1024 dc->r0 = EXTRACT_FIELD(ir, 21, 25);
1025 dc->r1 = EXTRACT_FIELD(ir, 16, 20);
1026 dc->r2 = EXTRACT_FIELD(ir, 11, 15);
1027
1028 /* bit 31 seems to indicate insn type. */
1029 if (ir & (1 << 31)) {
1030 dc->format = OP_FMT_RR;
1031 } else {
1032 dc->format = OP_FMT_RI;
1033 }
1034
a5086f95
MW		 1035 assert(ARRAY_SIZE(decinfo) == 64);
1036 assert(dc->opcode < 64);
17c0fa3d 1037
a5086f95 1038 decinfo[dc->opcode](dc);
17c0fa3d
MW		 1039}
1040
6393c08d 1041static void check_breakpoint(CPULM32State *env, DisasContext *dc)
17c0fa3d 1042{
f0c3c505 1043 CPUState *cs = CPU(lm32_env_get_cpu(env));
17c0fa3d
MW		 1044 CPUBreakpoint *bp;
1045
f0c3c505
AF		 1046 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
1047 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
17c0fa3d
MW		 1048 if (bp->pc == dc->pc) {
1049 tcg_gen_movi_tl(cpu_pc, dc->pc);
1050 t_gen_raise_exception(dc, EXCP_DEBUG);
1051 dc->is_jmp = DISAS_UPDATE;
1052 }
1053 }
1054 }
1055}
1056
1057/* generate intermediate code for basic block 'tb'. */
28014bca 1058static inline
cd0db97e
AF		 1059void gen_intermediate_code_internal(LM32CPU *cpu,
1060 TranslationBlock *tb, bool search_pc)
17c0fa3d 1061{
ed2803da 1062 CPUState *cs = CPU(cpu);
cd0db97e 1063 CPULM32State *env = &cpu->env;
17c0fa3d
MW		 1064 struct DisasContext ctx, *dc = &ctx;
1065 uint16_t *gen_opc_end;
1066 uint32_t pc_start;
1067 int j, lj;
1068 uint32_t next_page_start;
1069 int num_insns;
1070 int max_insns;
1071
17c0fa3d 1072 pc_start = tb->pc;
34f4aa83
MW		 1073 dc->features = cpu->features;
1074 dc->num_breakpoints = cpu->num_breakpoints;
1075 dc->num_watchpoints = cpu->num_watchpoints;
17c0fa3d
MW		 1076 dc->tb = tb;
1077
92414b31 1078 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
17c0fa3d
MW		 1079
1080 dc->is_jmp = DISAS_NEXT;
1081 dc->pc = pc_start;
ed2803da 1082 dc->singlestep_enabled = cs->singlestep_enabled;
17c0fa3d
MW		 1083
1084 if (pc_start & 3) {
3604a76f
MW		 1085 qemu_log_mask(LOG_GUEST_ERROR,
1086 "unaligned PC=%x. Ignoring lowest bits.\n", pc_start);
1087 pc_start &= ~3;
17c0fa3d
MW		 1088 }
1089
17c0fa3d
MW		 1090 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1091 lj = -1;
1092 num_insns = 0;
1093 max_insns = tb->cflags & CF_COUNT_MASK;
1094 if (max_insns == 0) {
1095 max_insns = CF_COUNT_MASK;
1096 }
1097
806f352d 1098 gen_tb_start();
17c0fa3d
MW		 1099 do {
1100 check_breakpoint(env, dc);
1101
1102 if (search_pc) {
92414b31 1103 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
17c0fa3d
MW		 1104 if (lj < j) {
1105 lj++;
1106 while (lj < j) {
ab1103de 1107 tcg_ctx.gen_opc_instr_start[lj++] = 0;
17c0fa3d
MW		 1108 }
1109 }
25983cad 1110 tcg_ctx.gen_opc_pc[lj] = dc->pc;
ab1103de 1111 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 1112 tcg_ctx.gen_opc_icount[lj] = num_insns;
17c0fa3d
MW		 1113 }
1114
1115 /* Pretty disas. */
1116 LOG_DIS("%8.8x:\t", dc->pc);
1117
1118 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
1119 gen_io_start();
1120 }
1121
32ac0ca2 1122 decode(dc, cpu_ldl_code(env, dc->pc));
17c0fa3d
MW		 1123 dc->pc += 4;
1124 num_insns++;
1125
1126 } while (!dc->is_jmp
efd7f486 1127 && tcg_ctx.gen_opc_ptr < gen_opc_end
ed2803da 1128 && !cs->singlestep_enabled
17c0fa3d
MW		 1129 && !singlestep
1130 && (dc->pc < next_page_start)
1131 && num_insns < max_insns);
1132
1133 if (tb->cflags & CF_LAST_IO) {
1134 gen_io_end();
1135 }
1136
ed2803da 1137 if (unlikely(cs->singlestep_enabled)) {
17c0fa3d
MW		 1138 if (dc->is_jmp == DISAS_NEXT) {
1139 tcg_gen_movi_tl(cpu_pc, dc->pc);
1140 }
1141 t_gen_raise_exception(dc, EXCP_DEBUG);
1142 } else {
1143 switch (dc->is_jmp) {
1144 case DISAS_NEXT:
1145 gen_goto_tb(dc, 1, dc->pc);
1146 break;
1147 default:
1148 case DISAS_JUMP:
1149 case DISAS_UPDATE:
1150 /* indicate that the hash table must be used
1151 to find the next TB */
1152 tcg_gen_exit_tb(0);
1153 break;
1154 case DISAS_TB_JUMP:
1155 /* nothing more to generate */
1156 break;
1157 }
1158 }
1159
806f352d 1160 gen_tb_end(tb, num_insns);
efd7f486 1161 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
17c0fa3d 1162 if (search_pc) {
92414b31 1163 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
17c0fa3d
MW		 1164 lj++;
1165 while (lj <= j) {
ab1103de 1166 tcg_ctx.gen_opc_instr_start[lj++] = 0;
17c0fa3d
MW		 1167 }
1168 } else {
1169 tb->size = dc->pc - pc_start;
1170 tb->icount = num_insns;
1171 }
1172
1173#ifdef DEBUG_DISAS
1174 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1175 qemu_log("\n");
f4359b9f 1176 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
dfa5294f 1177 qemu_log("\nisize=%d osize=%td\n",
92414b31
EV		 1178 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1179 tcg_ctx.gen_opc_buf);
17c0fa3d
MW		 1180 }
1181#endif
1182}
1183
6393c08d 1184void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
17c0fa3d 1185{
cd0db97e 1186 gen_intermediate_code_internal(lm32_env_get_cpu(env), tb, false);
17c0fa3d
MW		 1187}
1188
6393c08d 1189void gen_intermediate_code_pc(CPULM32State *env, struct TranslationBlock *tb)
17c0fa3d 1190{
cd0db97e 1191 gen_intermediate_code_internal(lm32_env_get_cpu(env), tb, true);
17c0fa3d
MW		 1192}
1193
878096ee
AF		 1194void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1195 int flags)
17c0fa3d 1196{
878096ee
AF		 1197 LM32CPU *cpu = LM32_CPU(cs);
1198 CPULM32State *env = &cpu->env;
17c0fa3d
MW		 1199 int i;
1200
1201 if (!env || !f) {
1202 return;
1203 }
1204
1205 cpu_fprintf(f, "IN: PC=%x %s\n",
1206 env->pc, lookup_symbol(env->pc));
1207
1208 cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
1209 env->ie,
1210 (env->ie & IE_IE) ? 1 : 0,
1211 (env->ie & IE_EIE) ? 1 : 0,
1212 (env->ie & IE_BIE) ? 1 : 0,
1213 lm32_pic_get_im(env->pic_state),
1214 lm32_pic_get_ip(env->pic_state));
1215 cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
1216 env->eba,
1217 env->deba);
1218
1219 for (i = 0; i < 32; i++) {
1220 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1221 if ((i + 1) % 4 == 0) {
1222 cpu_fprintf(f, "\n");
1223 }
1224 }
1225 cpu_fprintf(f, "\n\n");
1226}
1227
6393c08d 1228void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos)
17c0fa3d 1229{
25983cad 1230 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
17c0fa3d
MW		 1231}
1232
1233void lm32_translate_init(void)
1234{
1235 int i;
1236
1237 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1238
1239 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1240 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
6393c08d 1241 offsetof(CPULM32State, regs[i]),
17c0fa3d
MW		 1242 regnames[i]);
1243 }
1244
1245 for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
1246 cpu_bp[i] = tcg_global_mem_new(TCG_AREG0,
6393c08d 1247 offsetof(CPULM32State, bp[i]),
17c0fa3d
MW		 1248 regnames[32+i]);
1249 }
1250
1251 for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
1252 cpu_wp[i] = tcg_global_mem_new(TCG_AREG0,
6393c08d 1253 offsetof(CPULM32State, wp[i]),
17c0fa3d
MW		 1254 regnames[36+i]);
1255 }
1256
1257 cpu_pc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1258 offsetof(CPULM32State, pc),
17c0fa3d
MW		 1259 "pc");
1260 cpu_ie = tcg_global_mem_new(TCG_AREG0,
6393c08d 1261 offsetof(CPULM32State, ie),
17c0fa3d
MW		 1262 "ie");
1263 cpu_icc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1264 offsetof(CPULM32State, icc),
17c0fa3d
MW		 1265 "icc");
1266 cpu_dcc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1267 offsetof(CPULM32State, dcc),
17c0fa3d
MW		 1268 "dcc");
1269 cpu_cc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1270 offsetof(CPULM32State, cc),
17c0fa3d
MW		 1271 "cc");
1272 cpu_cfg = tcg_global_mem_new(TCG_AREG0,
6393c08d 1273 offsetof(CPULM32State, cfg),
17c0fa3d
MW		 1274 "cfg");
1275 cpu_eba = tcg_global_mem_new(TCG_AREG0,
6393c08d 1276 offsetof(CPULM32State, eba),
17c0fa3d
MW		 1277 "eba");
1278 cpu_dc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1279 offsetof(CPULM32State, dc),
17c0fa3d
MW		 1280 "dc");
1281 cpu_deba = tcg_global_mem_new(TCG_AREG0,
6393c08d 1282 offsetof(CPULM32State, deba),
17c0fa3d
MW		 1283 "deba");
1284}
1285
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