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e6e5906b PB |
1 | /* |
2 | * m68k virtual CPU header | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
07f5a258 MA |
20 | |
21 | #ifndef M68K_CPU_H | |
22 | #define M68K_CPU_H | |
e6e5906b PB |
23 | |
24 | #define TARGET_LONG_BITS 32 | |
25 | ||
9349b4f9 | 26 | #define CPUArchState struct CPUM68KState |
c2764719 | 27 | |
9a78eead | 28 | #include "qemu-common.h" |
022c62cb | 29 | #include "exec/cpu-defs.h" |
a836b8fa | 30 | #include "cpu-qom.h" |
6b4c305c | 31 | #include "fpu/softfloat.h" |
e6e5906b | 32 | |
7ef25cdd LV |
33 | #define OS_BYTE 0 |
34 | #define OS_WORD 1 | |
35 | #define OS_LONG 2 | |
36 | #define OS_SINGLE 3 | |
37 | #define OS_DOUBLE 4 | |
38 | #define OS_EXTENDED 5 | |
39 | #define OS_PACKED 6 | |
40 | ||
e6e5906b PB |
41 | #define MAX_QREGS 32 |
42 | ||
e6e5906b PB |
43 | #define EXCP_ACCESS 2 /* Access (MMU) error. */ |
44 | #define EXCP_ADDRESS 3 /* Address error. */ | |
45 | #define EXCP_ILLEGAL 4 /* Illegal instruction. */ | |
46 | #define EXCP_DIV0 5 /* Divide by zero */ | |
47 | #define EXCP_PRIVILEGE 8 /* Privilege violation. */ | |
48 | #define EXCP_TRACE 9 | |
49 | #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ | |
50 | #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ | |
51 | #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ | |
52 | #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ | |
53 | #define EXCP_FORMAT 14 /* RTE format error. */ | |
54 | #define EXCP_UNINITIALIZED 15 | |
55 | #define EXCP_TRAP0 32 /* User trap #0. */ | |
56 | #define EXCP_TRAP15 47 /* User trap #15. */ | |
57 | #define EXCP_UNSUPPORTED 61 | |
58 | #define EXCP_ICE 13 | |
59 | ||
0633879f | 60 | #define EXCP_RTE 0x100 |
a87295e8 | 61 | #define EXCP_HALT_INSN 0x101 |
0633879f | 62 | |
6ebbf390 | 63 | #define NB_MMU_MODES 2 |
20a8856e | 64 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
6ebbf390 | 65 | |
e6e5906b PB |
66 | typedef struct CPUM68KState { |
67 | uint32_t dregs[8]; | |
68 | uint32_t aregs[8]; | |
69 | uint32_t pc; | |
70 | uint32_t sr; | |
71 | ||
20dcee94 PB |
72 | /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ |
73 | int current_sp; | |
74 | uint32_t sp[2]; | |
75 | ||
e6e5906b PB |
76 | /* Condition flags. */ |
77 | uint32_t cc_op; | |
620c6cf6 RH |
78 | uint32_t cc_x; /* always 0/1 */ |
79 | uint32_t cc_n; /* in bit 31 (i.e. negative) */ | |
80 | uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ | |
81 | uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ | |
82 | uint32_t cc_z; /* == 0 or unused */ | |
e6e5906b PB |
83 | |
84 | float64 fregs[8]; | |
85 | float64 fp_result; | |
86 | uint32_t fpcr; | |
87 | uint32_t fpsr; | |
88 | float_status fp_status; | |
89 | ||
acf930aa PB |
90 | uint64_t mactmp; |
91 | /* EMAC Hardware deals with 48-bit values composed of one 32-bit and | |
92 | two 8-bit parts. We store a single 64-bit value and | |
93 | rearrange/extend this when changing modes. */ | |
94 | uint64_t macc[4]; | |
95 | uint32_t macsr; | |
96 | uint32_t mac_mask; | |
97 | ||
e6e5906b PB |
98 | /* Temporary storage for DIV helpers. */ |
99 | uint32_t div1; | |
100 | uint32_t div2; | |
3b46e624 | 101 | |
e6e5906b PB |
102 | /* MMU status. */ |
103 | struct { | |
104 | uint32_t ar; | |
105 | } mmu; | |
0633879f PB |
106 | |
107 | /* Control registers. */ | |
108 | uint32_t vbr; | |
109 | uint32_t mbar; | |
110 | uint32_t rambar0; | |
20dcee94 | 111 | uint32_t cacr; |
0633879f | 112 | |
0633879f PB |
113 | int pending_vector; |
114 | int pending_level; | |
e6e5906b PB |
115 | |
116 | uint32_t qregs[MAX_QREGS]; | |
117 | ||
118 | CPU_COMMON | |
aaed909a | 119 | |
f0c3c505 | 120 | /* Fields from here on are preserved across CPU reset. */ |
aaed909a | 121 | uint32_t features; |
e6e5906b PB |
122 | } CPUM68KState; |
123 | ||
a836b8fa PB |
124 | /** |
125 | * M68kCPU: | |
126 | * @env: #CPUM68KState | |
127 | * | |
128 | * A Motorola 68k CPU. | |
129 | */ | |
130 | struct M68kCPU { | |
131 | /*< private >*/ | |
132 | CPUState parent_obj; | |
133 | /*< public >*/ | |
134 | ||
135 | CPUM68KState env; | |
136 | }; | |
137 | ||
138 | static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) | |
139 | { | |
140 | return container_of(env, M68kCPU, env); | |
141 | } | |
142 | ||
143 | #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) | |
144 | ||
145 | #define ENV_OFFSET offsetof(M68kCPU, env) | |
146 | ||
147 | void m68k_cpu_do_interrupt(CPUState *cpu); | |
148 | bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
149 | void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
150 | int flags); | |
151 | hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
152 | int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
153 | int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
154 | ||
e1f3808e | 155 | void m68k_tcg_init(void); |
6d1bbc62 | 156 | void m68k_cpu_init_gdb(M68kCPU *cpu); |
c7937d9f | 157 | M68kCPU *cpu_m68k_init(const char *cpu_model); |
e6e5906b PB |
158 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
159 | signal handlers to inform the virtual CPU of exceptions. non zero | |
160 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 161 | int cpu_m68k_signal_handler(int host_signum, void *pinfo, |
e6e5906b | 162 | void *puc); |
99c51448 RH |
163 | uint32_t cpu_m68k_get_ccr(CPUM68KState *env); |
164 | void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); | |
e6e5906b | 165 | |
c3ce5a23 PB |
166 | |
167 | /* Instead of computing the condition codes after each m68k instruction, | |
168 | * QEMU just stores one operand (called CC_SRC), the result | |
169 | * (called CC_DEST) and the type of operation (called CC_OP). When the | |
170 | * condition codes are needed, the condition codes can be calculated | |
171 | * using this information. Condition codes are not generated if they | |
172 | * are only needed for conditional branches. | |
173 | */ | |
9fdb533f | 174 | typedef enum { |
620c6cf6 RH |
175 | /* Translator only -- use env->cc_op. */ |
176 | CC_OP_DYNAMIC = -1, | |
177 | ||
178 | /* Each flag bit computed into cc_[xcnvz]. */ | |
179 | CC_OP_FLAGS, | |
180 | ||
181 | /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ | |
db3d7945 LV |
182 | CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, |
183 | CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, | |
620c6cf6 RH |
184 | |
185 | /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ | |
db3d7945 | 186 | CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, |
620c6cf6 RH |
187 | |
188 | /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ | |
189 | CC_OP_LOGIC, | |
190 | ||
191 | CC_OP_NB | |
9fdb533f | 192 | } CCOp; |
e6e5906b PB |
193 | |
194 | #define CCF_C 0x01 | |
195 | #define CCF_V 0x02 | |
196 | #define CCF_Z 0x04 | |
197 | #define CCF_N 0x08 | |
0633879f PB |
198 | #define CCF_X 0x10 |
199 | ||
200 | #define SR_I_SHIFT 8 | |
201 | #define SR_I 0x0700 | |
202 | #define SR_M 0x1000 | |
203 | #define SR_S 0x2000 | |
204 | #define SR_T 0x8000 | |
e6e5906b | 205 | |
20dcee94 PB |
206 | #define M68K_SSP 0 |
207 | #define M68K_USP 1 | |
208 | ||
209 | /* CACR fields are implementation defined, but some bits are common. */ | |
210 | #define M68K_CACR_EUSP 0x10 | |
211 | ||
acf930aa PB |
212 | #define MACSR_PAV0 0x100 |
213 | #define MACSR_OMC 0x080 | |
214 | #define MACSR_SU 0x040 | |
215 | #define MACSR_FI 0x020 | |
216 | #define MACSR_RT 0x010 | |
217 | #define MACSR_N 0x008 | |
218 | #define MACSR_Z 0x004 | |
219 | #define MACSR_V 0x002 | |
220 | #define MACSR_EV 0x001 | |
221 | ||
cb3fb38e | 222 | void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); |
20dcee94 | 223 | void m68k_switch_sp(CPUM68KState *env); |
e6e5906b PB |
224 | |
225 | #define M68K_FPCR_PREC (1 << 6) | |
226 | ||
a87295e8 PB |
227 | void do_m68k_semihosting(CPUM68KState *env, int nr); |
228 | ||
d315c888 PB |
229 | /* There are 4 ColdFire core ISA revisions: A, A+, B and C. |
230 | Each feature covers the subset of instructions common to the | |
231 | ISA revisions mentioned. */ | |
232 | ||
0402f767 | 233 | enum m68k_features { |
f076803b | 234 | M68K_FEATURE_M68000, |
0402f767 | 235 | M68K_FEATURE_CF_ISA_A, |
d315c888 PB |
236 | M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ |
237 | M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ | |
238 | M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ | |
0402f767 PB |
239 | M68K_FEATURE_CF_FPU, |
240 | M68K_FEATURE_CF_MAC, | |
241 | M68K_FEATURE_CF_EMAC, | |
d315c888 PB |
242 | M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ |
243 | M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ | |
e6dbd3b3 | 244 | M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ |
f076803b LV |
245 | M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ |
246 | M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ | |
247 | M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ | |
248 | M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ | |
249 | M68K_FEATURE_BCCL, /* Long conditional branches. */ | |
250 | M68K_FEATURE_BITFIELD, /* Bit field insns. */ | |
251 | M68K_FEATURE_FPU, | |
252 | M68K_FEATURE_CAS, | |
253 | M68K_FEATURE_BKPT, | |
0402f767 PB |
254 | }; |
255 | ||
256 | static inline int m68k_feature(CPUM68KState *env, int feature) | |
257 | { | |
258 | return (env->features & (1u << feature)) != 0; | |
259 | } | |
260 | ||
9a78eead | 261 | void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
009a4356 | 262 | |
0402f767 PB |
263 | void register_m68k_insns (CPUM68KState *env); |
264 | ||
e6e5906b | 265 | #ifdef CONFIG_USER_ONLY |
2b04e85a LV |
266 | /* Coldfire Linux uses 8k pages |
267 | * and m68k linux uses 4k pages | |
268 | * use the smaller one | |
269 | */ | |
270 | #define TARGET_PAGE_BITS 12 | |
e6e5906b | 271 | #else |
5fafdf24 | 272 | /* Smallest TLB entry size is 1k. */ |
e6e5906b PB |
273 | #define TARGET_PAGE_BITS 10 |
274 | #endif | |
9467d44c | 275 | |
52705890 RH |
276 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
277 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
278 | ||
2994fd96 | 279 | #define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model)) |
c7937d9f | 280 | |
9467d44c | 281 | #define cpu_signal_handler cpu_m68k_signal_handler |
009a4356 | 282 | #define cpu_list m68k_cpu_list |
9467d44c | 283 | |
6ebbf390 JM |
284 | /* MMU modes definitions */ |
285 | #define MMU_MODE0_SUFFIX _kernel | |
286 | #define MMU_MODE1_SUFFIX _user | |
287 | #define MMU_USER_IDX 1 | |
97ed5ccd | 288 | static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) |
6ebbf390 JM |
289 | { |
290 | return (env->sr & SR_S) == 0 ? 1 : 0; | |
291 | } | |
292 | ||
7510454e | 293 | int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, |
97b348e7 | 294 | int mmu_idx); |
aaedd1f9 | 295 | |
022c62cb | 296 | #include "exec/cpu-all.h" |
622ed360 | 297 | |
2b3e3cfe | 298 | static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, |
89fee74a | 299 | target_ulong *cs_base, uint32_t *flags) |
6b917547 AL |
300 | { |
301 | *pc = env->pc; | |
302 | *cs_base = 0; | |
303 | *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */ | |
304 | | (env->sr & SR_S) /* Bit 13 */ | |
305 | | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ | |
306 | } | |
307 | ||
e6e5906b | 308 | #endif |