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Commit | Line | Data |
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e6e5906b PB |
1 | /* |
2 | * m68k translation | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
e6e5906b | 20 | |
e6e5906b | 21 | #include "cpu.h" |
76cad711 | 22 | #include "disas/disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
1de7afc9 | 24 | #include "qemu/log.h" |
f08b6170 | 25 | #include "exec/cpu_ldst.h" |
e1f3808e | 26 | |
2ef6175a RH |
27 | #include "exec/helper-proto.h" |
28 | #include "exec/helper-gen.h" | |
e6e5906b | 29 | |
a7e30d84 LV |
30 | #include "trace-tcg.h" |
31 | ||
32 | ||
0633879f PB |
33 | //#define DEBUG_DISPATCH 1 |
34 | ||
815a6742 | 35 | /* Fake floating point. */ |
815a6742 | 36 | #define tcg_gen_mov_f64 tcg_gen_mov_i64 |
815a6742 | 37 | #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 |
815a6742 | 38 | #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 |
815a6742 | 39 | |
e1f3808e | 40 | #define DEFO32(name, offset) static TCGv QREG_##name; |
a7812ae4 PB |
41 | #define DEFO64(name, offset) static TCGv_i64 QREG_##name; |
42 | #define DEFF64(name, offset) static TCGv_i64 QREG_##name; | |
e1f3808e PB |
43 | #include "qregs.def" |
44 | #undef DEFO32 | |
45 | #undef DEFO64 | |
46 | #undef DEFF64 | |
47 | ||
259186a7 | 48 | static TCGv_i32 cpu_halted; |
27103424 | 49 | static TCGv_i32 cpu_exception_index; |
259186a7 | 50 | |
a7812ae4 | 51 | static TCGv_ptr cpu_env; |
e1f3808e PB |
52 | |
53 | static char cpu_reg_names[3*8*3 + 5*4]; | |
54 | static TCGv cpu_dregs[8]; | |
55 | static TCGv cpu_aregs[8]; | |
a7812ae4 PB |
56 | static TCGv_i64 cpu_fregs[8]; |
57 | static TCGv_i64 cpu_macc[4]; | |
e1f3808e PB |
58 | |
59 | #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7] | |
60 | #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7] | |
61 | #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7] | |
62 | #define MACREG(acc) cpu_macc[acc] | |
63 | #define QREG_SP cpu_aregs[7] | |
64 | ||
65 | static TCGv NULL_QREG; | |
a7812ae4 | 66 | #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) |
e1f3808e PB |
67 | /* Used to distinguish stores from bad addressing modes. */ |
68 | static TCGv store_dummy; | |
69 | ||
022c62cb | 70 | #include "exec/gen-icount.h" |
2e70f6ef | 71 | |
e1f3808e PB |
72 | void m68k_tcg_init(void) |
73 | { | |
74 | char *p; | |
75 | int i; | |
76 | ||
2b3e3cfe AF |
77 | #define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUM68KState, offset), #name); |
78 | #define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUM68KState, offset), #name); | |
e1f3808e PB |
79 | #define DEFF64(name, offset) DEFO64(name, offset) |
80 | #include "qregs.def" | |
81 | #undef DEFO32 | |
82 | #undef DEFO64 | |
83 | #undef DEFF64 | |
84 | ||
259186a7 AF |
85 | cpu_halted = tcg_global_mem_new_i32(TCG_AREG0, |
86 | -offsetof(M68kCPU, env) + | |
87 | offsetof(CPUState, halted), "HALTED"); | |
27103424 AF |
88 | cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0, |
89 | -offsetof(M68kCPU, env) + | |
90 | offsetof(CPUState, exception_index), | |
91 | "EXCEPTION"); | |
259186a7 | 92 | |
a7812ae4 | 93 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
e1f3808e PB |
94 | |
95 | p = cpu_reg_names; | |
96 | for (i = 0; i < 8; i++) { | |
97 | sprintf(p, "D%d", i); | |
a7812ae4 | 98 | cpu_dregs[i] = tcg_global_mem_new(TCG_AREG0, |
e1f3808e PB |
99 | offsetof(CPUM68KState, dregs[i]), p); |
100 | p += 3; | |
101 | sprintf(p, "A%d", i); | |
a7812ae4 | 102 | cpu_aregs[i] = tcg_global_mem_new(TCG_AREG0, |
e1f3808e PB |
103 | offsetof(CPUM68KState, aregs[i]), p); |
104 | p += 3; | |
105 | sprintf(p, "F%d", i); | |
a7812ae4 | 106 | cpu_fregs[i] = tcg_global_mem_new_i64(TCG_AREG0, |
e1f3808e PB |
107 | offsetof(CPUM68KState, fregs[i]), p); |
108 | p += 3; | |
109 | } | |
110 | for (i = 0; i < 4; i++) { | |
111 | sprintf(p, "ACC%d", i); | |
a7812ae4 | 112 | cpu_macc[i] = tcg_global_mem_new_i64(TCG_AREG0, |
e1f3808e PB |
113 | offsetof(CPUM68KState, macc[i]), p); |
114 | p += 5; | |
115 | } | |
116 | ||
a7812ae4 PB |
117 | NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL"); |
118 | store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL"); | |
e1f3808e PB |
119 | } |
120 | ||
e6e5906b PB |
121 | /* internal defines */ |
122 | typedef struct DisasContext { | |
e6dbd3b3 | 123 | CPUM68KState *env; |
510ff0b7 | 124 | target_ulong insn_pc; /* Start of the current instruction. */ |
e6e5906b PB |
125 | target_ulong pc; |
126 | int is_jmp; | |
127 | int cc_op; | |
0633879f | 128 | int user; |
e6e5906b PB |
129 | uint32_t fpcr; |
130 | struct TranslationBlock *tb; | |
131 | int singlestep_enabled; | |
a7812ae4 PB |
132 | TCGv_i64 mactmp; |
133 | int done_mac; | |
e6e5906b PB |
134 | } DisasContext; |
135 | ||
136 | #define DISAS_JUMP_NEXT 4 | |
137 | ||
0633879f PB |
138 | #if defined(CONFIG_USER_ONLY) |
139 | #define IS_USER(s) 1 | |
140 | #else | |
141 | #define IS_USER(s) s->user | |
142 | #endif | |
143 | ||
e6e5906b PB |
144 | /* XXX: move that elsewhere */ |
145 | /* ??? Fix exceptions. */ | |
146 | static void *gen_throws_exception; | |
147 | #define gen_last_qop NULL | |
148 | ||
e6e5906b PB |
149 | #define OS_BYTE 0 |
150 | #define OS_WORD 1 | |
151 | #define OS_LONG 2 | |
152 | #define OS_SINGLE 4 | |
153 | #define OS_DOUBLE 5 | |
154 | ||
d4d79bb1 | 155 | typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); |
e6e5906b | 156 | |
0633879f | 157 | #ifdef DEBUG_DISPATCH |
d4d79bb1 BS |
158 | #define DISAS_INSN(name) \ |
159 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
160 | uint16_t insn); \ | |
161 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
162 | uint16_t insn) \ | |
163 | { \ | |
164 | qemu_log("Dispatch " #name "\n"); \ | |
165 | real_disas_##name(s, env, insn); \ | |
166 | } \ | |
167 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
168 | uint16_t insn) | |
0633879f | 169 | #else |
d4d79bb1 BS |
170 | #define DISAS_INSN(name) \ |
171 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
172 | uint16_t insn) | |
0633879f | 173 | #endif |
e6e5906b PB |
174 | |
175 | /* Generate a load from the specified address. Narrow values are | |
176 | sign extended to full register width. */ | |
e1f3808e | 177 | static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) |
e6e5906b | 178 | { |
e1f3808e PB |
179 | TCGv tmp; |
180 | int index = IS_USER(s); | |
a7812ae4 | 181 | tmp = tcg_temp_new_i32(); |
e6e5906b PB |
182 | switch(opsize) { |
183 | case OS_BYTE: | |
e6e5906b | 184 | if (sign) |
e1f3808e | 185 | tcg_gen_qemu_ld8s(tmp, addr, index); |
e6e5906b | 186 | else |
e1f3808e | 187 | tcg_gen_qemu_ld8u(tmp, addr, index); |
e6e5906b PB |
188 | break; |
189 | case OS_WORD: | |
e6e5906b | 190 | if (sign) |
e1f3808e | 191 | tcg_gen_qemu_ld16s(tmp, addr, index); |
e6e5906b | 192 | else |
e1f3808e | 193 | tcg_gen_qemu_ld16u(tmp, addr, index); |
e6e5906b PB |
194 | break; |
195 | case OS_LONG: | |
e6e5906b | 196 | case OS_SINGLE: |
a7812ae4 | 197 | tcg_gen_qemu_ld32u(tmp, addr, index); |
e6e5906b PB |
198 | break; |
199 | default: | |
7372c2b9 | 200 | g_assert_not_reached(); |
e6e5906b PB |
201 | } |
202 | gen_throws_exception = gen_last_qop; | |
203 | return tmp; | |
204 | } | |
205 | ||
a7812ae4 PB |
206 | static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) |
207 | { | |
208 | TCGv_i64 tmp; | |
209 | int index = IS_USER(s); | |
a7812ae4 PB |
210 | tmp = tcg_temp_new_i64(); |
211 | tcg_gen_qemu_ldf64(tmp, addr, index); | |
212 | gen_throws_exception = gen_last_qop; | |
213 | return tmp; | |
214 | } | |
215 | ||
e6e5906b | 216 | /* Generate a store. */ |
e1f3808e | 217 | static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) |
e6e5906b | 218 | { |
e1f3808e | 219 | int index = IS_USER(s); |
e6e5906b PB |
220 | switch(opsize) { |
221 | case OS_BYTE: | |
e1f3808e | 222 | tcg_gen_qemu_st8(val, addr, index); |
e6e5906b PB |
223 | break; |
224 | case OS_WORD: | |
e1f3808e | 225 | tcg_gen_qemu_st16(val, addr, index); |
e6e5906b PB |
226 | break; |
227 | case OS_LONG: | |
e6e5906b | 228 | case OS_SINGLE: |
a7812ae4 | 229 | tcg_gen_qemu_st32(val, addr, index); |
e6e5906b PB |
230 | break; |
231 | default: | |
7372c2b9 | 232 | g_assert_not_reached(); |
e6e5906b PB |
233 | } |
234 | gen_throws_exception = gen_last_qop; | |
235 | } | |
236 | ||
a7812ae4 PB |
237 | static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) |
238 | { | |
239 | int index = IS_USER(s); | |
a7812ae4 PB |
240 | tcg_gen_qemu_stf64(val, addr, index); |
241 | gen_throws_exception = gen_last_qop; | |
242 | } | |
243 | ||
e1f3808e PB |
244 | typedef enum { |
245 | EA_STORE, | |
246 | EA_LOADU, | |
247 | EA_LOADS | |
248 | } ea_what; | |
249 | ||
e6e5906b PB |
250 | /* Generate an unsigned load if VAL is 0 a signed load if val is -1, |
251 | otherwise generate a store. */ | |
e1f3808e PB |
252 | static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, |
253 | ea_what what) | |
e6e5906b | 254 | { |
e1f3808e | 255 | if (what == EA_STORE) { |
0633879f | 256 | gen_store(s, opsize, addr, val); |
e1f3808e | 257 | return store_dummy; |
e6e5906b | 258 | } else { |
e1f3808e | 259 | return gen_load(s, opsize, addr, what == EA_LOADS); |
e6e5906b PB |
260 | } |
261 | } | |
262 | ||
e6dbd3b3 | 263 | /* Read a 32-bit immediate constant. */ |
d4d79bb1 | 264 | static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) |
e6dbd3b3 PB |
265 | { |
266 | uint32_t im; | |
d4d79bb1 | 267 | im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16; |
e6dbd3b3 | 268 | s->pc += 2; |
d4d79bb1 | 269 | im |= cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
270 | s->pc += 2; |
271 | return im; | |
272 | } | |
273 | ||
274 | /* Calculate and address index. */ | |
e1f3808e | 275 | static TCGv gen_addr_index(uint16_t ext, TCGv tmp) |
e6dbd3b3 | 276 | { |
e1f3808e | 277 | TCGv add; |
e6dbd3b3 PB |
278 | int scale; |
279 | ||
280 | add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); | |
281 | if ((ext & 0x800) == 0) { | |
e1f3808e | 282 | tcg_gen_ext16s_i32(tmp, add); |
e6dbd3b3 PB |
283 | add = tmp; |
284 | } | |
285 | scale = (ext >> 9) & 3; | |
286 | if (scale != 0) { | |
e1f3808e | 287 | tcg_gen_shli_i32(tmp, add, scale); |
e6dbd3b3 PB |
288 | add = tmp; |
289 | } | |
290 | return add; | |
291 | } | |
292 | ||
e1f3808e PB |
293 | /* Handle a base + index + displacement effective addresss. |
294 | A NULL_QREG base means pc-relative. */ | |
a4356126 | 295 | static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) |
e6e5906b | 296 | { |
e6e5906b PB |
297 | uint32_t offset; |
298 | uint16_t ext; | |
e1f3808e PB |
299 | TCGv add; |
300 | TCGv tmp; | |
e6dbd3b3 | 301 | uint32_t bd, od; |
e6e5906b PB |
302 | |
303 | offset = s->pc; | |
d4d79bb1 | 304 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 305 | s->pc += 2; |
e6dbd3b3 PB |
306 | |
307 | if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) | |
e1f3808e | 308 | return NULL_QREG; |
e6dbd3b3 PB |
309 | |
310 | if (ext & 0x100) { | |
311 | /* full extension word format */ | |
312 | if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) | |
e1f3808e | 313 | return NULL_QREG; |
e6dbd3b3 PB |
314 | |
315 | if ((ext & 0x30) > 0x10) { | |
316 | /* base displacement */ | |
317 | if ((ext & 0x30) == 0x20) { | |
d4d79bb1 | 318 | bd = (int16_t)cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
319 | s->pc += 2; |
320 | } else { | |
d4d79bb1 | 321 | bd = read_im32(env, s); |
e6dbd3b3 PB |
322 | } |
323 | } else { | |
324 | bd = 0; | |
325 | } | |
a7812ae4 | 326 | tmp = tcg_temp_new(); |
e6dbd3b3 PB |
327 | if ((ext & 0x44) == 0) { |
328 | /* pre-index */ | |
329 | add = gen_addr_index(ext, tmp); | |
330 | } else { | |
e1f3808e | 331 | add = NULL_QREG; |
e6dbd3b3 PB |
332 | } |
333 | if ((ext & 0x80) == 0) { | |
334 | /* base not suppressed */ | |
e1f3808e | 335 | if (IS_NULL_QREG(base)) { |
351326a6 | 336 | base = tcg_const_i32(offset + bd); |
e6dbd3b3 PB |
337 | bd = 0; |
338 | } | |
e1f3808e PB |
339 | if (!IS_NULL_QREG(add)) { |
340 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 PB |
341 | add = tmp; |
342 | } else { | |
343 | add = base; | |
344 | } | |
345 | } | |
e1f3808e | 346 | if (!IS_NULL_QREG(add)) { |
e6dbd3b3 | 347 | if (bd != 0) { |
e1f3808e | 348 | tcg_gen_addi_i32(tmp, add, bd); |
e6dbd3b3 PB |
349 | add = tmp; |
350 | } | |
351 | } else { | |
351326a6 | 352 | add = tcg_const_i32(bd); |
e6dbd3b3 PB |
353 | } |
354 | if ((ext & 3) != 0) { | |
355 | /* memory indirect */ | |
356 | base = gen_load(s, OS_LONG, add, 0); | |
357 | if ((ext & 0x44) == 4) { | |
358 | add = gen_addr_index(ext, tmp); | |
e1f3808e | 359 | tcg_gen_add_i32(tmp, add, base); |
e6dbd3b3 PB |
360 | add = tmp; |
361 | } else { | |
362 | add = base; | |
363 | } | |
364 | if ((ext & 3) > 1) { | |
365 | /* outer displacement */ | |
366 | if ((ext & 3) == 2) { | |
d4d79bb1 | 367 | od = (int16_t)cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
368 | s->pc += 2; |
369 | } else { | |
d4d79bb1 | 370 | od = read_im32(env, s); |
e6dbd3b3 PB |
371 | } |
372 | } else { | |
373 | od = 0; | |
374 | } | |
375 | if (od != 0) { | |
e1f3808e | 376 | tcg_gen_addi_i32(tmp, add, od); |
e6dbd3b3 PB |
377 | add = tmp; |
378 | } | |
379 | } | |
e6e5906b | 380 | } else { |
e6dbd3b3 | 381 | /* brief extension word format */ |
a7812ae4 | 382 | tmp = tcg_temp_new(); |
e6dbd3b3 | 383 | add = gen_addr_index(ext, tmp); |
e1f3808e PB |
384 | if (!IS_NULL_QREG(base)) { |
385 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 | 386 | if ((int8_t)ext) |
e1f3808e | 387 | tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); |
e6dbd3b3 | 388 | } else { |
e1f3808e | 389 | tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); |
e6dbd3b3 PB |
390 | } |
391 | add = tmp; | |
e6e5906b | 392 | } |
e6dbd3b3 | 393 | return add; |
e6e5906b PB |
394 | } |
395 | ||
e6e5906b PB |
396 | /* Update the CPU env CC_OP state. */ |
397 | static inline void gen_flush_cc_op(DisasContext *s) | |
398 | { | |
399 | if (s->cc_op != CC_OP_DYNAMIC) | |
e1f3808e | 400 | tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); |
e6e5906b PB |
401 | } |
402 | ||
403 | /* Evaluate all the CC flags. */ | |
404 | static inline void gen_flush_flags(DisasContext *s) | |
405 | { | |
406 | if (s->cc_op == CC_OP_FLAGS) | |
407 | return; | |
0cf5c677 | 408 | gen_flush_cc_op(s); |
e1f3808e | 409 | gen_helper_flush_flags(cpu_env, QREG_CC_OP); |
e6e5906b PB |
410 | s->cc_op = CC_OP_FLAGS; |
411 | } | |
412 | ||
e1f3808e PB |
413 | static void gen_logic_cc(DisasContext *s, TCGv val) |
414 | { | |
415 | tcg_gen_mov_i32(QREG_CC_DEST, val); | |
416 | s->cc_op = CC_OP_LOGIC; | |
417 | } | |
418 | ||
419 | static void gen_update_cc_add(TCGv dest, TCGv src) | |
420 | { | |
421 | tcg_gen_mov_i32(QREG_CC_DEST, dest); | |
422 | tcg_gen_mov_i32(QREG_CC_SRC, src); | |
423 | } | |
424 | ||
e6e5906b PB |
425 | static inline int opsize_bytes(int opsize) |
426 | { | |
427 | switch (opsize) { | |
428 | case OS_BYTE: return 1; | |
429 | case OS_WORD: return 2; | |
430 | case OS_LONG: return 4; | |
431 | case OS_SINGLE: return 4; | |
432 | case OS_DOUBLE: return 8; | |
433 | default: | |
7372c2b9 | 434 | g_assert_not_reached(); |
e6e5906b PB |
435 | } |
436 | } | |
437 | ||
438 | /* Assign value to a register. If the width is less than the register width | |
439 | only the low part of the register is set. */ | |
e1f3808e | 440 | static void gen_partset_reg(int opsize, TCGv reg, TCGv val) |
e6e5906b | 441 | { |
e1f3808e | 442 | TCGv tmp; |
e6e5906b PB |
443 | switch (opsize) { |
444 | case OS_BYTE: | |
e1f3808e | 445 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
a7812ae4 | 446 | tmp = tcg_temp_new(); |
e1f3808e PB |
447 | tcg_gen_ext8u_i32(tmp, val); |
448 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
449 | break; |
450 | case OS_WORD: | |
e1f3808e | 451 | tcg_gen_andi_i32(reg, reg, 0xffff0000); |
a7812ae4 | 452 | tmp = tcg_temp_new(); |
e1f3808e PB |
453 | tcg_gen_ext16u_i32(tmp, val); |
454 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
455 | break; |
456 | case OS_LONG: | |
e6e5906b | 457 | case OS_SINGLE: |
a7812ae4 | 458 | tcg_gen_mov_i32(reg, val); |
e6e5906b PB |
459 | break; |
460 | default: | |
7372c2b9 | 461 | g_assert_not_reached(); |
e6e5906b PB |
462 | } |
463 | } | |
464 | ||
465 | /* Sign or zero extend a value. */ | |
e1f3808e | 466 | static inline TCGv gen_extend(TCGv val, int opsize, int sign) |
e6e5906b | 467 | { |
e1f3808e | 468 | TCGv tmp; |
e6e5906b PB |
469 | |
470 | switch (opsize) { | |
471 | case OS_BYTE: | |
a7812ae4 | 472 | tmp = tcg_temp_new(); |
e6e5906b | 473 | if (sign) |
e1f3808e | 474 | tcg_gen_ext8s_i32(tmp, val); |
e6e5906b | 475 | else |
e1f3808e | 476 | tcg_gen_ext8u_i32(tmp, val); |
e6e5906b PB |
477 | break; |
478 | case OS_WORD: | |
a7812ae4 | 479 | tmp = tcg_temp_new(); |
e6e5906b | 480 | if (sign) |
e1f3808e | 481 | tcg_gen_ext16s_i32(tmp, val); |
e6e5906b | 482 | else |
e1f3808e | 483 | tcg_gen_ext16u_i32(tmp, val); |
e6e5906b PB |
484 | break; |
485 | case OS_LONG: | |
e6e5906b | 486 | case OS_SINGLE: |
a7812ae4 | 487 | tmp = val; |
e6e5906b PB |
488 | break; |
489 | default: | |
7372c2b9 | 490 | g_assert_not_reached(); |
e6e5906b PB |
491 | } |
492 | return tmp; | |
493 | } | |
494 | ||
495 | /* Generate code for an "effective address". Does not adjust the base | |
1addc7c5 | 496 | register for autoincrement addressing modes. */ |
d4d79bb1 BS |
497 | static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
498 | int opsize) | |
e6e5906b | 499 | { |
e1f3808e PB |
500 | TCGv reg; |
501 | TCGv tmp; | |
e6e5906b PB |
502 | uint16_t ext; |
503 | uint32_t offset; | |
504 | ||
e6e5906b PB |
505 | switch ((insn >> 3) & 7) { |
506 | case 0: /* Data register direct. */ | |
507 | case 1: /* Address register direct. */ | |
e1f3808e | 508 | return NULL_QREG; |
e6e5906b PB |
509 | case 2: /* Indirect register */ |
510 | case 3: /* Indirect postincrement. */ | |
e1f3808e | 511 | return AREG(insn, 0); |
e6e5906b | 512 | case 4: /* Indirect predecrememnt. */ |
e1f3808e | 513 | reg = AREG(insn, 0); |
a7812ae4 | 514 | tmp = tcg_temp_new(); |
e1f3808e | 515 | tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); |
e6e5906b PB |
516 | return tmp; |
517 | case 5: /* Indirect displacement. */ | |
e1f3808e | 518 | reg = AREG(insn, 0); |
a7812ae4 | 519 | tmp = tcg_temp_new(); |
d4d79bb1 | 520 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 521 | s->pc += 2; |
e1f3808e | 522 | tcg_gen_addi_i32(tmp, reg, (int16_t)ext); |
e6e5906b PB |
523 | return tmp; |
524 | case 6: /* Indirect index + displacement. */ | |
e1f3808e | 525 | reg = AREG(insn, 0); |
a4356126 | 526 | return gen_lea_indexed(env, s, reg); |
e6e5906b | 527 | case 7: /* Other */ |
e1f3808e | 528 | switch (insn & 7) { |
e6e5906b | 529 | case 0: /* Absolute short. */ |
d4d79bb1 | 530 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b | 531 | s->pc += 2; |
351326a6 | 532 | return tcg_const_i32(offset); |
e6e5906b | 533 | case 1: /* Absolute long. */ |
d4d79bb1 | 534 | offset = read_im32(env, s); |
351326a6 | 535 | return tcg_const_i32(offset); |
e6e5906b | 536 | case 2: /* pc displacement */ |
e6e5906b | 537 | offset = s->pc; |
d4d79bb1 | 538 | offset += cpu_ldsw_code(env, s->pc); |
e6e5906b | 539 | s->pc += 2; |
351326a6 | 540 | return tcg_const_i32(offset); |
e6e5906b | 541 | case 3: /* pc index+displacement. */ |
a4356126 | 542 | return gen_lea_indexed(env, s, NULL_QREG); |
e6e5906b PB |
543 | case 4: /* Immediate. */ |
544 | default: | |
e1f3808e | 545 | return NULL_QREG; |
e6e5906b PB |
546 | } |
547 | } | |
548 | /* Should never happen. */ | |
e1f3808e | 549 | return NULL_QREG; |
e6e5906b PB |
550 | } |
551 | ||
552 | /* Helper function for gen_ea. Reuse the computed address between the | |
553 | for read/write operands. */ | |
d4d79bb1 BS |
554 | static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s, |
555 | uint16_t insn, int opsize, TCGv val, | |
556 | TCGv *addrp, ea_what what) | |
e6e5906b | 557 | { |
e1f3808e | 558 | TCGv tmp; |
e6e5906b | 559 | |
e1f3808e | 560 | if (addrp && what == EA_STORE) { |
e6e5906b PB |
561 | tmp = *addrp; |
562 | } else { | |
d4d79bb1 | 563 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
564 | if (IS_NULL_QREG(tmp)) |
565 | return tmp; | |
e6e5906b PB |
566 | if (addrp) |
567 | *addrp = tmp; | |
568 | } | |
e1f3808e | 569 | return gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
570 | } |
571 | ||
f38f7a84 | 572 | /* Generate code to load/store a value from/into an EA. If VAL > 0 this is |
e6e5906b PB |
573 | a write otherwise it is a read (0 == sign extend, -1 == zero extend). |
574 | ADDRP is non-null for readwrite operands. */ | |
d4d79bb1 BS |
575 | static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
576 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
e6e5906b | 577 | { |
e1f3808e PB |
578 | TCGv reg; |
579 | TCGv result; | |
e6e5906b PB |
580 | uint32_t offset; |
581 | ||
e6e5906b PB |
582 | switch ((insn >> 3) & 7) { |
583 | case 0: /* Data register direct. */ | |
e1f3808e PB |
584 | reg = DREG(insn, 0); |
585 | if (what == EA_STORE) { | |
e6e5906b | 586 | gen_partset_reg(opsize, reg, val); |
e1f3808e | 587 | return store_dummy; |
e6e5906b | 588 | } else { |
e1f3808e | 589 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
590 | } |
591 | case 1: /* Address register direct. */ | |
e1f3808e PB |
592 | reg = AREG(insn, 0); |
593 | if (what == EA_STORE) { | |
594 | tcg_gen_mov_i32(reg, val); | |
595 | return store_dummy; | |
e6e5906b | 596 | } else { |
e1f3808e | 597 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
598 | } |
599 | case 2: /* Indirect register */ | |
e1f3808e PB |
600 | reg = AREG(insn, 0); |
601 | return gen_ldst(s, opsize, reg, val, what); | |
e6e5906b | 602 | case 3: /* Indirect postincrement. */ |
e1f3808e PB |
603 | reg = AREG(insn, 0); |
604 | result = gen_ldst(s, opsize, reg, val, what); | |
e6e5906b PB |
605 | /* ??? This is not exception safe. The instruction may still |
606 | fault after this point. */ | |
e1f3808e PB |
607 | if (what == EA_STORE || !addrp) |
608 | tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize)); | |
e6e5906b PB |
609 | return result; |
610 | case 4: /* Indirect predecrememnt. */ | |
611 | { | |
e1f3808e PB |
612 | TCGv tmp; |
613 | if (addrp && what == EA_STORE) { | |
e6e5906b PB |
614 | tmp = *addrp; |
615 | } else { | |
d4d79bb1 | 616 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
617 | if (IS_NULL_QREG(tmp)) |
618 | return tmp; | |
e6e5906b PB |
619 | if (addrp) |
620 | *addrp = tmp; | |
621 | } | |
e1f3808e | 622 | result = gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
623 | /* ??? This is not exception safe. The instruction may still |
624 | fault after this point. */ | |
e1f3808e PB |
625 | if (what == EA_STORE || !addrp) { |
626 | reg = AREG(insn, 0); | |
627 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
628 | } |
629 | } | |
630 | return result; | |
631 | case 5: /* Indirect displacement. */ | |
632 | case 6: /* Indirect index + displacement. */ | |
d4d79bb1 | 633 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b | 634 | case 7: /* Other */ |
e1f3808e | 635 | switch (insn & 7) { |
e6e5906b PB |
636 | case 0: /* Absolute short. */ |
637 | case 1: /* Absolute long. */ | |
638 | case 2: /* pc displacement */ | |
639 | case 3: /* pc index+displacement. */ | |
d4d79bb1 | 640 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b PB |
641 | case 4: /* Immediate. */ |
642 | /* Sign extend values for consistency. */ | |
643 | switch (opsize) { | |
644 | case OS_BYTE: | |
31871141 | 645 | if (what == EA_LOADS) { |
d4d79bb1 | 646 | offset = cpu_ldsb_code(env, s->pc + 1); |
31871141 | 647 | } else { |
d4d79bb1 | 648 | offset = cpu_ldub_code(env, s->pc + 1); |
31871141 | 649 | } |
e6e5906b PB |
650 | s->pc += 2; |
651 | break; | |
652 | case OS_WORD: | |
31871141 | 653 | if (what == EA_LOADS) { |
d4d79bb1 | 654 | offset = cpu_ldsw_code(env, s->pc); |
31871141 | 655 | } else { |
d4d79bb1 | 656 | offset = cpu_lduw_code(env, s->pc); |
31871141 | 657 | } |
e6e5906b PB |
658 | s->pc += 2; |
659 | break; | |
660 | case OS_LONG: | |
d4d79bb1 | 661 | offset = read_im32(env, s); |
e6e5906b PB |
662 | break; |
663 | default: | |
7372c2b9 | 664 | g_assert_not_reached(); |
e6e5906b | 665 | } |
e1f3808e | 666 | return tcg_const_i32(offset); |
e6e5906b | 667 | default: |
e1f3808e | 668 | return NULL_QREG; |
e6e5906b PB |
669 | } |
670 | } | |
671 | /* Should never happen. */ | |
e1f3808e | 672 | return NULL_QREG; |
e6e5906b PB |
673 | } |
674 | ||
e1f3808e | 675 | /* This generates a conditional branch, clobbering all temporaries. */ |
42a268c2 | 676 | static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) |
e6e5906b | 677 | { |
e1f3808e | 678 | TCGv tmp; |
e6e5906b | 679 | |
e1f3808e PB |
680 | /* TODO: Optimize compare/branch pairs rather than always flushing |
681 | flag state to CC_OP_FLAGS. */ | |
e6e5906b PB |
682 | gen_flush_flags(s); |
683 | switch (cond) { | |
684 | case 0: /* T */ | |
e1f3808e | 685 | tcg_gen_br(l1); |
e6e5906b PB |
686 | break; |
687 | case 1: /* F */ | |
688 | break; | |
689 | case 2: /* HI (!C && !Z) */ | |
a7812ae4 | 690 | tmp = tcg_temp_new(); |
e1f3808e PB |
691 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
692 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
693 | break; |
694 | case 3: /* LS (C || Z) */ | |
a7812ae4 | 695 | tmp = tcg_temp_new(); |
e1f3808e PB |
696 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
697 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
698 | break; |
699 | case 4: /* CC (!C) */ | |
a7812ae4 | 700 | tmp = tcg_temp_new(); |
e1f3808e PB |
701 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
702 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
703 | break; |
704 | case 5: /* CS (C) */ | |
a7812ae4 | 705 | tmp = tcg_temp_new(); |
e1f3808e PB |
706 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
707 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
708 | break; |
709 | case 6: /* NE (!Z) */ | |
a7812ae4 | 710 | tmp = tcg_temp_new(); |
e1f3808e PB |
711 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
712 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
713 | break; |
714 | case 7: /* EQ (Z) */ | |
a7812ae4 | 715 | tmp = tcg_temp_new(); |
e1f3808e PB |
716 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
717 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
718 | break; |
719 | case 8: /* VC (!V) */ | |
a7812ae4 | 720 | tmp = tcg_temp_new(); |
e1f3808e PB |
721 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
722 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
723 | break; |
724 | case 9: /* VS (V) */ | |
a7812ae4 | 725 | tmp = tcg_temp_new(); |
e1f3808e PB |
726 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
727 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
728 | break; |
729 | case 10: /* PL (!N) */ | |
a7812ae4 | 730 | tmp = tcg_temp_new(); |
e1f3808e PB |
731 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
732 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
733 | break; |
734 | case 11: /* MI (N) */ | |
a7812ae4 | 735 | tmp = tcg_temp_new(); |
e1f3808e PB |
736 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
737 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
738 | break; |
739 | case 12: /* GE (!(N ^ V)) */ | |
a7812ae4 | 740 | tmp = tcg_temp_new(); |
e1f3808e PB |
741 | assert(CCF_V == (CCF_N >> 2)); |
742 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
743 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
744 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
745 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
746 | break; |
747 | case 13: /* LT (N ^ V) */ | |
a7812ae4 | 748 | tmp = tcg_temp_new(); |
e1f3808e PB |
749 | assert(CCF_V == (CCF_N >> 2)); |
750 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
751 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
752 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
753 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
754 | break; |
755 | case 14: /* GT (!(Z || (N ^ V))) */ | |
a7812ae4 | 756 | tmp = tcg_temp_new(); |
e1f3808e PB |
757 | assert(CCF_V == (CCF_N >> 2)); |
758 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
759 | tcg_gen_shri_i32(tmp, tmp, 2); | |
760 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
761 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
762 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
763 | break; |
764 | case 15: /* LE (Z || (N ^ V)) */ | |
a7812ae4 | 765 | tmp = tcg_temp_new(); |
e1f3808e PB |
766 | assert(CCF_V == (CCF_N >> 2)); |
767 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
768 | tcg_gen_shri_i32(tmp, tmp, 2); | |
769 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
770 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
771 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
772 | break; |
773 | default: | |
774 | /* Should ever happen. */ | |
775 | abort(); | |
776 | } | |
777 | } | |
778 | ||
779 | DISAS_INSN(scc) | |
780 | { | |
42a268c2 | 781 | TCGLabel *l1; |
e6e5906b | 782 | int cond; |
e1f3808e | 783 | TCGv reg; |
e6e5906b PB |
784 | |
785 | l1 = gen_new_label(); | |
786 | cond = (insn >> 8) & 0xf; | |
787 | reg = DREG(insn, 0); | |
e1f3808e PB |
788 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
789 | /* This is safe because we modify the reg directly, with no other values | |
790 | live. */ | |
e6e5906b | 791 | gen_jmpcc(s, cond ^ 1, l1); |
e1f3808e | 792 | tcg_gen_ori_i32(reg, reg, 0xff); |
e6e5906b PB |
793 | gen_set_label(l1); |
794 | } | |
795 | ||
0633879f PB |
796 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
797 | static void gen_lookup_tb(DisasContext *s) | |
798 | { | |
799 | gen_flush_cc_op(s); | |
e1f3808e | 800 | tcg_gen_movi_i32(QREG_PC, s->pc); |
0633879f PB |
801 | s->is_jmp = DISAS_UPDATE; |
802 | } | |
803 | ||
e1f3808e PB |
804 | /* Generate a jump to an immediate address. */ |
805 | static void gen_jmp_im(DisasContext *s, uint32_t dest) | |
806 | { | |
807 | gen_flush_cc_op(s); | |
808 | tcg_gen_movi_i32(QREG_PC, dest); | |
809 | s->is_jmp = DISAS_JUMP; | |
810 | } | |
811 | ||
812 | /* Generate a jump to the address in qreg DEST. */ | |
813 | static void gen_jmp(DisasContext *s, TCGv dest) | |
e6e5906b PB |
814 | { |
815 | gen_flush_cc_op(s); | |
e1f3808e | 816 | tcg_gen_mov_i32(QREG_PC, dest); |
e6e5906b PB |
817 | s->is_jmp = DISAS_JUMP; |
818 | } | |
819 | ||
820 | static void gen_exception(DisasContext *s, uint32_t where, int nr) | |
821 | { | |
822 | gen_flush_cc_op(s); | |
e1f3808e | 823 | gen_jmp_im(s, where); |
31871141 | 824 | gen_helper_raise_exception(cpu_env, tcg_const_i32(nr)); |
e6e5906b PB |
825 | } |
826 | ||
510ff0b7 PB |
827 | static inline void gen_addr_fault(DisasContext *s) |
828 | { | |
829 | gen_exception(s, s->insn_pc, EXCP_ADDRESS); | |
830 | } | |
831 | ||
d4d79bb1 BS |
832 | #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ |
833 | result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ | |
834 | op_sign ? EA_LOADS : EA_LOADU); \ | |
835 | if (IS_NULL_QREG(result)) { \ | |
836 | gen_addr_fault(s); \ | |
837 | return; \ | |
838 | } \ | |
510ff0b7 PB |
839 | } while (0) |
840 | ||
d4d79bb1 BS |
841 | #define DEST_EA(env, insn, opsize, val, addrp) do { \ |
842 | TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ | |
843 | if (IS_NULL_QREG(ea_result)) { \ | |
844 | gen_addr_fault(s); \ | |
845 | return; \ | |
846 | } \ | |
510ff0b7 PB |
847 | } while (0) |
848 | ||
e6e5906b PB |
849 | /* Generate a jump to an immediate address. */ |
850 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | |
851 | { | |
852 | TranslationBlock *tb; | |
853 | ||
854 | tb = s->tb; | |
551bd27f | 855 | if (unlikely(s->singlestep_enabled)) { |
e6e5906b PB |
856 | gen_exception(s, dest, EXCP_DEBUG); |
857 | } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || | |
858 | (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { | |
57fec1fe | 859 | tcg_gen_goto_tb(n); |
e1f3808e | 860 | tcg_gen_movi_i32(QREG_PC, dest); |
8cfd0495 | 861 | tcg_gen_exit_tb((uintptr_t)tb + n); |
e6e5906b | 862 | } else { |
e1f3808e | 863 | gen_jmp_im(s, dest); |
57fec1fe | 864 | tcg_gen_exit_tb(0); |
e6e5906b PB |
865 | } |
866 | s->is_jmp = DISAS_TB_JUMP; | |
867 | } | |
868 | ||
869 | DISAS_INSN(undef_mac) | |
870 | { | |
871 | gen_exception(s, s->pc - 2, EXCP_LINEA); | |
872 | } | |
873 | ||
874 | DISAS_INSN(undef_fpu) | |
875 | { | |
876 | gen_exception(s, s->pc - 2, EXCP_LINEF); | |
877 | } | |
878 | ||
879 | DISAS_INSN(undef) | |
880 | { | |
a47dddd7 AF |
881 | M68kCPU *cpu = m68k_env_get_cpu(env); |
882 | ||
e6e5906b | 883 | gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); |
a47dddd7 | 884 | cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); |
e6e5906b PB |
885 | } |
886 | ||
887 | DISAS_INSN(mulw) | |
888 | { | |
e1f3808e PB |
889 | TCGv reg; |
890 | TCGv tmp; | |
891 | TCGv src; | |
e6e5906b PB |
892 | int sign; |
893 | ||
894 | sign = (insn & 0x100) != 0; | |
895 | reg = DREG(insn, 9); | |
a7812ae4 | 896 | tmp = tcg_temp_new(); |
e6e5906b | 897 | if (sign) |
e1f3808e | 898 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 899 | else |
e1f3808e | 900 | tcg_gen_ext16u_i32(tmp, reg); |
d4d79bb1 | 901 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e PB |
902 | tcg_gen_mul_i32(tmp, tmp, src); |
903 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
904 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
905 | gen_logic_cc(s, tmp); | |
906 | } | |
907 | ||
908 | DISAS_INSN(divw) | |
909 | { | |
e1f3808e PB |
910 | TCGv reg; |
911 | TCGv tmp; | |
912 | TCGv src; | |
e6e5906b PB |
913 | int sign; |
914 | ||
915 | sign = (insn & 0x100) != 0; | |
916 | reg = DREG(insn, 9); | |
917 | if (sign) { | |
e1f3808e | 918 | tcg_gen_ext16s_i32(QREG_DIV1, reg); |
e6e5906b | 919 | } else { |
e1f3808e | 920 | tcg_gen_ext16u_i32(QREG_DIV1, reg); |
e6e5906b | 921 | } |
d4d79bb1 | 922 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e | 923 | tcg_gen_mov_i32(QREG_DIV2, src); |
e6e5906b | 924 | if (sign) { |
e1f3808e | 925 | gen_helper_divs(cpu_env, tcg_const_i32(1)); |
e6e5906b | 926 | } else { |
e1f3808e | 927 | gen_helper_divu(cpu_env, tcg_const_i32(1)); |
e6e5906b PB |
928 | } |
929 | ||
a7812ae4 PB |
930 | tmp = tcg_temp_new(); |
931 | src = tcg_temp_new(); | |
e1f3808e PB |
932 | tcg_gen_ext16u_i32(tmp, QREG_DIV1); |
933 | tcg_gen_shli_i32(src, QREG_DIV2, 16); | |
934 | tcg_gen_or_i32(reg, tmp, src); | |
e6e5906b PB |
935 | s->cc_op = CC_OP_FLAGS; |
936 | } | |
937 | ||
938 | DISAS_INSN(divl) | |
939 | { | |
e1f3808e PB |
940 | TCGv num; |
941 | TCGv den; | |
942 | TCGv reg; | |
e6e5906b PB |
943 | uint16_t ext; |
944 | ||
d4d79bb1 | 945 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
946 | s->pc += 2; |
947 | if (ext & 0x87f8) { | |
948 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
949 | return; | |
950 | } | |
951 | num = DREG(ext, 12); | |
952 | reg = DREG(ext, 0); | |
e1f3808e | 953 | tcg_gen_mov_i32(QREG_DIV1, num); |
d4d79bb1 | 954 | SRC_EA(env, den, OS_LONG, 0, NULL); |
e1f3808e | 955 | tcg_gen_mov_i32(QREG_DIV2, den); |
e6e5906b | 956 | if (ext & 0x0800) { |
e1f3808e | 957 | gen_helper_divs(cpu_env, tcg_const_i32(0)); |
e6e5906b | 958 | } else { |
e1f3808e | 959 | gen_helper_divu(cpu_env, tcg_const_i32(0)); |
e6e5906b | 960 | } |
e1f3808e | 961 | if ((ext & 7) == ((ext >> 12) & 7)) { |
e6e5906b | 962 | /* div */ |
e1f3808e | 963 | tcg_gen_mov_i32 (reg, QREG_DIV1); |
e6e5906b PB |
964 | } else { |
965 | /* rem */ | |
e1f3808e | 966 | tcg_gen_mov_i32 (reg, QREG_DIV2); |
e6e5906b | 967 | } |
e6e5906b PB |
968 | s->cc_op = CC_OP_FLAGS; |
969 | } | |
970 | ||
971 | DISAS_INSN(addsub) | |
972 | { | |
e1f3808e PB |
973 | TCGv reg; |
974 | TCGv dest; | |
975 | TCGv src; | |
976 | TCGv tmp; | |
977 | TCGv addr; | |
e6e5906b PB |
978 | int add; |
979 | ||
980 | add = (insn & 0x4000) != 0; | |
981 | reg = DREG(insn, 9); | |
a7812ae4 | 982 | dest = tcg_temp_new(); |
e6e5906b | 983 | if (insn & 0x100) { |
d4d79bb1 | 984 | SRC_EA(env, tmp, OS_LONG, 0, &addr); |
e6e5906b PB |
985 | src = reg; |
986 | } else { | |
987 | tmp = reg; | |
d4d79bb1 | 988 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b PB |
989 | } |
990 | if (add) { | |
e1f3808e PB |
991 | tcg_gen_add_i32(dest, tmp, src); |
992 | gen_helper_xflag_lt(QREG_CC_X, dest, src); | |
e6e5906b PB |
993 | s->cc_op = CC_OP_ADD; |
994 | } else { | |
e1f3808e PB |
995 | gen_helper_xflag_lt(QREG_CC_X, tmp, src); |
996 | tcg_gen_sub_i32(dest, tmp, src); | |
e6e5906b PB |
997 | s->cc_op = CC_OP_SUB; |
998 | } | |
e1f3808e | 999 | gen_update_cc_add(dest, src); |
e6e5906b | 1000 | if (insn & 0x100) { |
d4d79bb1 | 1001 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1002 | } else { |
e1f3808e | 1003 | tcg_gen_mov_i32(reg, dest); |
e6e5906b PB |
1004 | } |
1005 | } | |
1006 | ||
1007 | ||
1008 | /* Reverse the order of the bits in REG. */ | |
1009 | DISAS_INSN(bitrev) | |
1010 | { | |
e1f3808e | 1011 | TCGv reg; |
e6e5906b | 1012 | reg = DREG(insn, 0); |
e1f3808e | 1013 | gen_helper_bitrev(reg, reg); |
e6e5906b PB |
1014 | } |
1015 | ||
1016 | DISAS_INSN(bitop_reg) | |
1017 | { | |
1018 | int opsize; | |
1019 | int op; | |
e1f3808e PB |
1020 | TCGv src1; |
1021 | TCGv src2; | |
1022 | TCGv tmp; | |
1023 | TCGv addr; | |
1024 | TCGv dest; | |
e6e5906b PB |
1025 | |
1026 | if ((insn & 0x38) != 0) | |
1027 | opsize = OS_BYTE; | |
1028 | else | |
1029 | opsize = OS_LONG; | |
1030 | op = (insn >> 6) & 3; | |
d4d79bb1 | 1031 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1032 | src2 = DREG(insn, 9); |
a7812ae4 | 1033 | dest = tcg_temp_new(); |
e6e5906b PB |
1034 | |
1035 | gen_flush_flags(s); | |
a7812ae4 | 1036 | tmp = tcg_temp_new(); |
e6e5906b | 1037 | if (opsize == OS_BYTE) |
e1f3808e | 1038 | tcg_gen_andi_i32(tmp, src2, 7); |
e6e5906b | 1039 | else |
e1f3808e | 1040 | tcg_gen_andi_i32(tmp, src2, 31); |
e6e5906b | 1041 | src2 = tmp; |
a7812ae4 | 1042 | tmp = tcg_temp_new(); |
e1f3808e PB |
1043 | tcg_gen_shr_i32(tmp, src1, src2); |
1044 | tcg_gen_andi_i32(tmp, tmp, 1); | |
1045 | tcg_gen_shli_i32(tmp, tmp, 2); | |
1046 | /* Clear CCF_Z if bit set. */ | |
1047 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1048 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1049 | ||
1050 | tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2); | |
e6e5906b PB |
1051 | switch (op) { |
1052 | case 1: /* bchg */ | |
e1f3808e | 1053 | tcg_gen_xor_i32(dest, src1, tmp); |
e6e5906b PB |
1054 | break; |
1055 | case 2: /* bclr */ | |
e1f3808e PB |
1056 | tcg_gen_not_i32(tmp, tmp); |
1057 | tcg_gen_and_i32(dest, src1, tmp); | |
e6e5906b PB |
1058 | break; |
1059 | case 3: /* bset */ | |
e1f3808e | 1060 | tcg_gen_or_i32(dest, src1, tmp); |
e6e5906b PB |
1061 | break; |
1062 | default: /* btst */ | |
1063 | break; | |
1064 | } | |
1065 | if (op) | |
d4d79bb1 | 1066 | DEST_EA(env, insn, opsize, dest, &addr); |
e6e5906b PB |
1067 | } |
1068 | ||
1069 | DISAS_INSN(sats) | |
1070 | { | |
e1f3808e | 1071 | TCGv reg; |
e6e5906b | 1072 | reg = DREG(insn, 0); |
e6e5906b | 1073 | gen_flush_flags(s); |
e1f3808e PB |
1074 | gen_helper_sats(reg, reg, QREG_CC_DEST); |
1075 | gen_logic_cc(s, reg); | |
e6e5906b PB |
1076 | } |
1077 | ||
e1f3808e | 1078 | static void gen_push(DisasContext *s, TCGv val) |
e6e5906b | 1079 | { |
e1f3808e | 1080 | TCGv tmp; |
e6e5906b | 1081 | |
a7812ae4 | 1082 | tmp = tcg_temp_new(); |
e1f3808e | 1083 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1084 | gen_store(s, OS_LONG, tmp, val); |
e1f3808e | 1085 | tcg_gen_mov_i32(QREG_SP, tmp); |
e6e5906b PB |
1086 | } |
1087 | ||
1088 | DISAS_INSN(movem) | |
1089 | { | |
e1f3808e | 1090 | TCGv addr; |
e6e5906b PB |
1091 | int i; |
1092 | uint16_t mask; | |
e1f3808e PB |
1093 | TCGv reg; |
1094 | TCGv tmp; | |
e6e5906b PB |
1095 | int is_load; |
1096 | ||
d4d79bb1 | 1097 | mask = cpu_lduw_code(env, s->pc); |
e6e5906b | 1098 | s->pc += 2; |
d4d79bb1 | 1099 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1100 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1101 | gen_addr_fault(s); |
1102 | return; | |
1103 | } | |
a7812ae4 | 1104 | addr = tcg_temp_new(); |
e1f3808e | 1105 | tcg_gen_mov_i32(addr, tmp); |
e6e5906b PB |
1106 | is_load = ((insn & 0x0400) != 0); |
1107 | for (i = 0; i < 16; i++, mask >>= 1) { | |
1108 | if (mask & 1) { | |
1109 | if (i < 8) | |
1110 | reg = DREG(i, 0); | |
1111 | else | |
1112 | reg = AREG(i, 0); | |
1113 | if (is_load) { | |
0633879f | 1114 | tmp = gen_load(s, OS_LONG, addr, 0); |
e1f3808e | 1115 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b | 1116 | } else { |
0633879f | 1117 | gen_store(s, OS_LONG, addr, reg); |
e6e5906b PB |
1118 | } |
1119 | if (mask != 1) | |
e1f3808e | 1120 | tcg_gen_addi_i32(addr, addr, 4); |
e6e5906b PB |
1121 | } |
1122 | } | |
1123 | } | |
1124 | ||
1125 | DISAS_INSN(bitop_im) | |
1126 | { | |
1127 | int opsize; | |
1128 | int op; | |
e1f3808e | 1129 | TCGv src1; |
e6e5906b PB |
1130 | uint32_t mask; |
1131 | int bitnum; | |
e1f3808e PB |
1132 | TCGv tmp; |
1133 | TCGv addr; | |
e6e5906b PB |
1134 | |
1135 | if ((insn & 0x38) != 0) | |
1136 | opsize = OS_BYTE; | |
1137 | else | |
1138 | opsize = OS_LONG; | |
1139 | op = (insn >> 6) & 3; | |
1140 | ||
d4d79bb1 | 1141 | bitnum = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
1142 | s->pc += 2; |
1143 | if (bitnum & 0xff00) { | |
d4d79bb1 | 1144 | disas_undef(env, s, insn); |
e6e5906b PB |
1145 | return; |
1146 | } | |
1147 | ||
d4d79bb1 | 1148 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b PB |
1149 | |
1150 | gen_flush_flags(s); | |
e6e5906b PB |
1151 | if (opsize == OS_BYTE) |
1152 | bitnum &= 7; | |
1153 | else | |
1154 | bitnum &= 31; | |
1155 | mask = 1 << bitnum; | |
1156 | ||
a7812ae4 | 1157 | tmp = tcg_temp_new(); |
e1f3808e PB |
1158 | assert (CCF_Z == (1 << 2)); |
1159 | if (bitnum > 2) | |
1160 | tcg_gen_shri_i32(tmp, src1, bitnum - 2); | |
1161 | else if (bitnum < 2) | |
1162 | tcg_gen_shli_i32(tmp, src1, 2 - bitnum); | |
e6e5906b | 1163 | else |
e1f3808e PB |
1164 | tcg_gen_mov_i32(tmp, src1); |
1165 | tcg_gen_andi_i32(tmp, tmp, CCF_Z); | |
1166 | /* Clear CCF_Z if bit set. */ | |
1167 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1168 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1169 | if (op) { | |
1170 | switch (op) { | |
1171 | case 1: /* bchg */ | |
1172 | tcg_gen_xori_i32(tmp, src1, mask); | |
1173 | break; | |
1174 | case 2: /* bclr */ | |
1175 | tcg_gen_andi_i32(tmp, src1, ~mask); | |
1176 | break; | |
1177 | case 3: /* bset */ | |
1178 | tcg_gen_ori_i32(tmp, src1, mask); | |
1179 | break; | |
1180 | default: /* btst */ | |
1181 | break; | |
1182 | } | |
d4d79bb1 | 1183 | DEST_EA(env, insn, opsize, tmp, &addr); |
e6e5906b | 1184 | } |
e6e5906b PB |
1185 | } |
1186 | ||
1187 | DISAS_INSN(arith_im) | |
1188 | { | |
1189 | int op; | |
e1f3808e PB |
1190 | uint32_t im; |
1191 | TCGv src1; | |
1192 | TCGv dest; | |
1193 | TCGv addr; | |
e6e5906b PB |
1194 | |
1195 | op = (insn >> 9) & 7; | |
d4d79bb1 BS |
1196 | SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr); |
1197 | im = read_im32(env, s); | |
a7812ae4 | 1198 | dest = tcg_temp_new(); |
e6e5906b PB |
1199 | switch (op) { |
1200 | case 0: /* ori */ | |
e1f3808e | 1201 | tcg_gen_ori_i32(dest, src1, im); |
e6e5906b PB |
1202 | gen_logic_cc(s, dest); |
1203 | break; | |
1204 | case 1: /* andi */ | |
e1f3808e | 1205 | tcg_gen_andi_i32(dest, src1, im); |
e6e5906b PB |
1206 | gen_logic_cc(s, dest); |
1207 | break; | |
1208 | case 2: /* subi */ | |
e1f3808e | 1209 | tcg_gen_mov_i32(dest, src1); |
351326a6 | 1210 | gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); |
e1f3808e | 1211 | tcg_gen_subi_i32(dest, dest, im); |
351326a6 | 1212 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1213 | s->cc_op = CC_OP_SUB; |
1214 | break; | |
1215 | case 3: /* addi */ | |
e1f3808e PB |
1216 | tcg_gen_mov_i32(dest, src1); |
1217 | tcg_gen_addi_i32(dest, dest, im); | |
351326a6 LV |
1218 | gen_update_cc_add(dest, tcg_const_i32(im)); |
1219 | gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); | |
e6e5906b PB |
1220 | s->cc_op = CC_OP_ADD; |
1221 | break; | |
1222 | case 5: /* eori */ | |
e1f3808e | 1223 | tcg_gen_xori_i32(dest, src1, im); |
e6e5906b PB |
1224 | gen_logic_cc(s, dest); |
1225 | break; | |
1226 | case 6: /* cmpi */ | |
e1f3808e PB |
1227 | tcg_gen_mov_i32(dest, src1); |
1228 | tcg_gen_subi_i32(dest, dest, im); | |
351326a6 | 1229 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1230 | s->cc_op = CC_OP_SUB; |
1231 | break; | |
1232 | default: | |
1233 | abort(); | |
1234 | } | |
1235 | if (op != 6) { | |
d4d79bb1 | 1236 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1237 | } |
1238 | } | |
1239 | ||
1240 | DISAS_INSN(byterev) | |
1241 | { | |
e1f3808e | 1242 | TCGv reg; |
e6e5906b PB |
1243 | |
1244 | reg = DREG(insn, 0); | |
66896cb8 | 1245 | tcg_gen_bswap32_i32(reg, reg); |
e6e5906b PB |
1246 | } |
1247 | ||
1248 | DISAS_INSN(move) | |
1249 | { | |
e1f3808e PB |
1250 | TCGv src; |
1251 | TCGv dest; | |
e6e5906b PB |
1252 | int op; |
1253 | int opsize; | |
1254 | ||
1255 | switch (insn >> 12) { | |
1256 | case 1: /* move.b */ | |
1257 | opsize = OS_BYTE; | |
1258 | break; | |
1259 | case 2: /* move.l */ | |
1260 | opsize = OS_LONG; | |
1261 | break; | |
1262 | case 3: /* move.w */ | |
1263 | opsize = OS_WORD; | |
1264 | break; | |
1265 | default: | |
1266 | abort(); | |
1267 | } | |
d4d79bb1 | 1268 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b PB |
1269 | op = (insn >> 6) & 7; |
1270 | if (op == 1) { | |
1271 | /* movea */ | |
1272 | /* The value will already have been sign extended. */ | |
1273 | dest = AREG(insn, 9); | |
e1f3808e | 1274 | tcg_gen_mov_i32(dest, src); |
e6e5906b PB |
1275 | } else { |
1276 | /* normal move */ | |
1277 | uint16_t dest_ea; | |
1278 | dest_ea = ((insn >> 9) & 7) | (op << 3); | |
d4d79bb1 | 1279 | DEST_EA(env, dest_ea, opsize, src, NULL); |
e6e5906b PB |
1280 | /* This will be correct because loads sign extend. */ |
1281 | gen_logic_cc(s, src); | |
1282 | } | |
1283 | } | |
1284 | ||
1285 | DISAS_INSN(negx) | |
1286 | { | |
e1f3808e | 1287 | TCGv reg; |
e6e5906b PB |
1288 | |
1289 | gen_flush_flags(s); | |
1290 | reg = DREG(insn, 0); | |
e1f3808e | 1291 | gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg); |
e6e5906b PB |
1292 | } |
1293 | ||
1294 | DISAS_INSN(lea) | |
1295 | { | |
e1f3808e PB |
1296 | TCGv reg; |
1297 | TCGv tmp; | |
e6e5906b PB |
1298 | |
1299 | reg = AREG(insn, 9); | |
d4d79bb1 | 1300 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1301 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1302 | gen_addr_fault(s); |
1303 | return; | |
1304 | } | |
e1f3808e | 1305 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1306 | } |
1307 | ||
1308 | DISAS_INSN(clr) | |
1309 | { | |
1310 | int opsize; | |
1311 | ||
1312 | switch ((insn >> 6) & 3) { | |
1313 | case 0: /* clr.b */ | |
1314 | opsize = OS_BYTE; | |
1315 | break; | |
1316 | case 1: /* clr.w */ | |
1317 | opsize = OS_WORD; | |
1318 | break; | |
1319 | case 2: /* clr.l */ | |
1320 | opsize = OS_LONG; | |
1321 | break; | |
1322 | default: | |
1323 | abort(); | |
1324 | } | |
d4d79bb1 | 1325 | DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL); |
351326a6 | 1326 | gen_logic_cc(s, tcg_const_i32(0)); |
e6e5906b PB |
1327 | } |
1328 | ||
e1f3808e | 1329 | static TCGv gen_get_ccr(DisasContext *s) |
e6e5906b | 1330 | { |
e1f3808e | 1331 | TCGv dest; |
e6e5906b PB |
1332 | |
1333 | gen_flush_flags(s); | |
a7812ae4 | 1334 | dest = tcg_temp_new(); |
e1f3808e PB |
1335 | tcg_gen_shli_i32(dest, QREG_CC_X, 4); |
1336 | tcg_gen_or_i32(dest, dest, QREG_CC_DEST); | |
0633879f PB |
1337 | return dest; |
1338 | } | |
1339 | ||
1340 | DISAS_INSN(move_from_ccr) | |
1341 | { | |
e1f3808e PB |
1342 | TCGv reg; |
1343 | TCGv ccr; | |
0633879f PB |
1344 | |
1345 | ccr = gen_get_ccr(s); | |
e6e5906b | 1346 | reg = DREG(insn, 0); |
0633879f | 1347 | gen_partset_reg(OS_WORD, reg, ccr); |
e6e5906b PB |
1348 | } |
1349 | ||
1350 | DISAS_INSN(neg) | |
1351 | { | |
e1f3808e PB |
1352 | TCGv reg; |
1353 | TCGv src1; | |
e6e5906b PB |
1354 | |
1355 | reg = DREG(insn, 0); | |
a7812ae4 | 1356 | src1 = tcg_temp_new(); |
e1f3808e PB |
1357 | tcg_gen_mov_i32(src1, reg); |
1358 | tcg_gen_neg_i32(reg, src1); | |
e6e5906b | 1359 | s->cc_op = CC_OP_SUB; |
e1f3808e PB |
1360 | gen_update_cc_add(reg, src1); |
1361 | gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1); | |
e6e5906b PB |
1362 | s->cc_op = CC_OP_SUB; |
1363 | } | |
1364 | ||
0633879f PB |
1365 | static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) |
1366 | { | |
e1f3808e PB |
1367 | tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf); |
1368 | tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4); | |
0633879f | 1369 | if (!ccr_only) { |
e1f3808e | 1370 | gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00)); |
0633879f PB |
1371 | } |
1372 | } | |
1373 | ||
d4d79bb1 BS |
1374 | static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, |
1375 | int ccr_only) | |
e6e5906b | 1376 | { |
e1f3808e PB |
1377 | TCGv tmp; |
1378 | TCGv reg; | |
e6e5906b PB |
1379 | |
1380 | s->cc_op = CC_OP_FLAGS; | |
1381 | if ((insn & 0x38) == 0) | |
1382 | { | |
a7812ae4 | 1383 | tmp = tcg_temp_new(); |
e6e5906b | 1384 | reg = DREG(insn, 0); |
e1f3808e PB |
1385 | tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf); |
1386 | tcg_gen_shri_i32(tmp, reg, 4); | |
1387 | tcg_gen_andi_i32(QREG_CC_X, tmp, 1); | |
0633879f | 1388 | if (!ccr_only) { |
e1f3808e | 1389 | gen_helper_set_sr(cpu_env, reg); |
0633879f | 1390 | } |
e6e5906b | 1391 | } |
0633879f | 1392 | else if ((insn & 0x3f) == 0x3c) |
e6e5906b | 1393 | { |
0633879f | 1394 | uint16_t val; |
d4d79bb1 | 1395 | val = cpu_lduw_code(env, s->pc); |
e6e5906b | 1396 | s->pc += 2; |
0633879f | 1397 | gen_set_sr_im(s, val, ccr_only); |
e6e5906b PB |
1398 | } |
1399 | else | |
d4d79bb1 | 1400 | disas_undef(env, s, insn); |
e6e5906b PB |
1401 | } |
1402 | ||
0633879f PB |
1403 | DISAS_INSN(move_to_ccr) |
1404 | { | |
d4d79bb1 | 1405 | gen_set_sr(env, s, insn, 1); |
0633879f PB |
1406 | } |
1407 | ||
e6e5906b PB |
1408 | DISAS_INSN(not) |
1409 | { | |
e1f3808e | 1410 | TCGv reg; |
e6e5906b PB |
1411 | |
1412 | reg = DREG(insn, 0); | |
e1f3808e | 1413 | tcg_gen_not_i32(reg, reg); |
e6e5906b PB |
1414 | gen_logic_cc(s, reg); |
1415 | } | |
1416 | ||
1417 | DISAS_INSN(swap) | |
1418 | { | |
e1f3808e PB |
1419 | TCGv src1; |
1420 | TCGv src2; | |
1421 | TCGv reg; | |
e6e5906b | 1422 | |
a7812ae4 PB |
1423 | src1 = tcg_temp_new(); |
1424 | src2 = tcg_temp_new(); | |
e6e5906b | 1425 | reg = DREG(insn, 0); |
e1f3808e PB |
1426 | tcg_gen_shli_i32(src1, reg, 16); |
1427 | tcg_gen_shri_i32(src2, reg, 16); | |
1428 | tcg_gen_or_i32(reg, src1, src2); | |
1429 | gen_logic_cc(s, reg); | |
e6e5906b PB |
1430 | } |
1431 | ||
1432 | DISAS_INSN(pea) | |
1433 | { | |
e1f3808e | 1434 | TCGv tmp; |
e6e5906b | 1435 | |
d4d79bb1 | 1436 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1437 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1438 | gen_addr_fault(s); |
1439 | return; | |
1440 | } | |
0633879f | 1441 | gen_push(s, tmp); |
e6e5906b PB |
1442 | } |
1443 | ||
1444 | DISAS_INSN(ext) | |
1445 | { | |
e6e5906b | 1446 | int op; |
e1f3808e PB |
1447 | TCGv reg; |
1448 | TCGv tmp; | |
e6e5906b PB |
1449 | |
1450 | reg = DREG(insn, 0); | |
1451 | op = (insn >> 6) & 7; | |
a7812ae4 | 1452 | tmp = tcg_temp_new(); |
e6e5906b | 1453 | if (op == 3) |
e1f3808e | 1454 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1455 | else |
e1f3808e | 1456 | tcg_gen_ext8s_i32(tmp, reg); |
e6e5906b PB |
1457 | if (op == 2) |
1458 | gen_partset_reg(OS_WORD, reg, tmp); | |
1459 | else | |
e1f3808e | 1460 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1461 | gen_logic_cc(s, tmp); |
1462 | } | |
1463 | ||
1464 | DISAS_INSN(tst) | |
1465 | { | |
1466 | int opsize; | |
e1f3808e | 1467 | TCGv tmp; |
e6e5906b PB |
1468 | |
1469 | switch ((insn >> 6) & 3) { | |
1470 | case 0: /* tst.b */ | |
1471 | opsize = OS_BYTE; | |
1472 | break; | |
1473 | case 1: /* tst.w */ | |
1474 | opsize = OS_WORD; | |
1475 | break; | |
1476 | case 2: /* tst.l */ | |
1477 | opsize = OS_LONG; | |
1478 | break; | |
1479 | default: | |
1480 | abort(); | |
1481 | } | |
d4d79bb1 | 1482 | SRC_EA(env, tmp, opsize, 1, NULL); |
e6e5906b PB |
1483 | gen_logic_cc(s, tmp); |
1484 | } | |
1485 | ||
1486 | DISAS_INSN(pulse) | |
1487 | { | |
1488 | /* Implemented as a NOP. */ | |
1489 | } | |
1490 | ||
1491 | DISAS_INSN(illegal) | |
1492 | { | |
1493 | gen_exception(s, s->pc - 2, EXCP_ILLEGAL); | |
1494 | } | |
1495 | ||
1496 | /* ??? This should be atomic. */ | |
1497 | DISAS_INSN(tas) | |
1498 | { | |
e1f3808e PB |
1499 | TCGv dest; |
1500 | TCGv src1; | |
1501 | TCGv addr; | |
e6e5906b | 1502 | |
a7812ae4 | 1503 | dest = tcg_temp_new(); |
d4d79bb1 | 1504 | SRC_EA(env, src1, OS_BYTE, 1, &addr); |
e6e5906b | 1505 | gen_logic_cc(s, src1); |
e1f3808e | 1506 | tcg_gen_ori_i32(dest, src1, 0x80); |
d4d79bb1 | 1507 | DEST_EA(env, insn, OS_BYTE, dest, &addr); |
e6e5906b PB |
1508 | } |
1509 | ||
1510 | DISAS_INSN(mull) | |
1511 | { | |
1512 | uint16_t ext; | |
e1f3808e PB |
1513 | TCGv reg; |
1514 | TCGv src1; | |
1515 | TCGv dest; | |
e6e5906b PB |
1516 | |
1517 | /* The upper 32 bits of the product are discarded, so | |
1518 | muls.l and mulu.l are functionally equivalent. */ | |
d4d79bb1 | 1519 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
1520 | s->pc += 2; |
1521 | if (ext & 0x87ff) { | |
1522 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
1523 | return; | |
1524 | } | |
1525 | reg = DREG(ext, 12); | |
d4d79bb1 | 1526 | SRC_EA(env, src1, OS_LONG, 0, NULL); |
a7812ae4 | 1527 | dest = tcg_temp_new(); |
e1f3808e PB |
1528 | tcg_gen_mul_i32(dest, src1, reg); |
1529 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1530 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
1531 | gen_logic_cc(s, dest); | |
1532 | } | |
1533 | ||
1534 | DISAS_INSN(link) | |
1535 | { | |
1536 | int16_t offset; | |
e1f3808e PB |
1537 | TCGv reg; |
1538 | TCGv tmp; | |
e6e5906b | 1539 | |
d4d79bb1 | 1540 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1541 | s->pc += 2; |
1542 | reg = AREG(insn, 0); | |
a7812ae4 | 1543 | tmp = tcg_temp_new(); |
e1f3808e | 1544 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1545 | gen_store(s, OS_LONG, tmp, reg); |
e1f3808e PB |
1546 | if ((insn & 7) != 7) |
1547 | tcg_gen_mov_i32(reg, tmp); | |
1548 | tcg_gen_addi_i32(QREG_SP, tmp, offset); | |
e6e5906b PB |
1549 | } |
1550 | ||
1551 | DISAS_INSN(unlk) | |
1552 | { | |
e1f3808e PB |
1553 | TCGv src; |
1554 | TCGv reg; | |
1555 | TCGv tmp; | |
e6e5906b | 1556 | |
a7812ae4 | 1557 | src = tcg_temp_new(); |
e6e5906b | 1558 | reg = AREG(insn, 0); |
e1f3808e | 1559 | tcg_gen_mov_i32(src, reg); |
0633879f | 1560 | tmp = gen_load(s, OS_LONG, src, 0); |
e1f3808e PB |
1561 | tcg_gen_mov_i32(reg, tmp); |
1562 | tcg_gen_addi_i32(QREG_SP, src, 4); | |
e6e5906b PB |
1563 | } |
1564 | ||
1565 | DISAS_INSN(nop) | |
1566 | { | |
1567 | } | |
1568 | ||
1569 | DISAS_INSN(rts) | |
1570 | { | |
e1f3808e | 1571 | TCGv tmp; |
e6e5906b | 1572 | |
0633879f | 1573 | tmp = gen_load(s, OS_LONG, QREG_SP, 0); |
e1f3808e | 1574 | tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); |
e6e5906b PB |
1575 | gen_jmp(s, tmp); |
1576 | } | |
1577 | ||
1578 | DISAS_INSN(jump) | |
1579 | { | |
e1f3808e | 1580 | TCGv tmp; |
e6e5906b PB |
1581 | |
1582 | /* Load the target address first to ensure correct exception | |
1583 | behavior. */ | |
d4d79bb1 | 1584 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1585 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1586 | gen_addr_fault(s); |
1587 | return; | |
1588 | } | |
e6e5906b PB |
1589 | if ((insn & 0x40) == 0) { |
1590 | /* jsr */ | |
351326a6 | 1591 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1592 | } |
1593 | gen_jmp(s, tmp); | |
1594 | } | |
1595 | ||
1596 | DISAS_INSN(addsubq) | |
1597 | { | |
e1f3808e PB |
1598 | TCGv src1; |
1599 | TCGv src2; | |
1600 | TCGv dest; | |
e6e5906b | 1601 | int val; |
e1f3808e | 1602 | TCGv addr; |
e6e5906b | 1603 | |
d4d79bb1 | 1604 | SRC_EA(env, src1, OS_LONG, 0, &addr); |
e6e5906b PB |
1605 | val = (insn >> 9) & 7; |
1606 | if (val == 0) | |
1607 | val = 8; | |
a7812ae4 | 1608 | dest = tcg_temp_new(); |
e1f3808e | 1609 | tcg_gen_mov_i32(dest, src1); |
e6e5906b PB |
1610 | if ((insn & 0x38) == 0x08) { |
1611 | /* Don't update condition codes if the destination is an | |
1612 | address register. */ | |
1613 | if (insn & 0x0100) { | |
e1f3808e | 1614 | tcg_gen_subi_i32(dest, dest, val); |
e6e5906b | 1615 | } else { |
e1f3808e | 1616 | tcg_gen_addi_i32(dest, dest, val); |
e6e5906b PB |
1617 | } |
1618 | } else { | |
351326a6 | 1619 | src2 = tcg_const_i32(val); |
e6e5906b | 1620 | if (insn & 0x0100) { |
e1f3808e PB |
1621 | gen_helper_xflag_lt(QREG_CC_X, dest, src2); |
1622 | tcg_gen_subi_i32(dest, dest, val); | |
e6e5906b PB |
1623 | s->cc_op = CC_OP_SUB; |
1624 | } else { | |
e1f3808e PB |
1625 | tcg_gen_addi_i32(dest, dest, val); |
1626 | gen_helper_xflag_lt(QREG_CC_X, dest, src2); | |
e6e5906b PB |
1627 | s->cc_op = CC_OP_ADD; |
1628 | } | |
e1f3808e | 1629 | gen_update_cc_add(dest, src2); |
e6e5906b | 1630 | } |
d4d79bb1 | 1631 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1632 | } |
1633 | ||
1634 | DISAS_INSN(tpf) | |
1635 | { | |
1636 | switch (insn & 7) { | |
1637 | case 2: /* One extension word. */ | |
1638 | s->pc += 2; | |
1639 | break; | |
1640 | case 3: /* Two extension words. */ | |
1641 | s->pc += 4; | |
1642 | break; | |
1643 | case 4: /* No extension words. */ | |
1644 | break; | |
1645 | default: | |
d4d79bb1 | 1646 | disas_undef(env, s, insn); |
e6e5906b PB |
1647 | } |
1648 | } | |
1649 | ||
1650 | DISAS_INSN(branch) | |
1651 | { | |
1652 | int32_t offset; | |
1653 | uint32_t base; | |
1654 | int op; | |
42a268c2 | 1655 | TCGLabel *l1; |
3b46e624 | 1656 | |
e6e5906b PB |
1657 | base = s->pc; |
1658 | op = (insn >> 8) & 0xf; | |
1659 | offset = (int8_t)insn; | |
1660 | if (offset == 0) { | |
d4d79bb1 | 1661 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1662 | s->pc += 2; |
1663 | } else if (offset == -1) { | |
d4d79bb1 | 1664 | offset = read_im32(env, s); |
e6e5906b PB |
1665 | } |
1666 | if (op == 1) { | |
1667 | /* bsr */ | |
351326a6 | 1668 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1669 | } |
1670 | gen_flush_cc_op(s); | |
1671 | if (op > 1) { | |
1672 | /* Bcc */ | |
1673 | l1 = gen_new_label(); | |
1674 | gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); | |
1675 | gen_jmp_tb(s, 1, base + offset); | |
1676 | gen_set_label(l1); | |
1677 | gen_jmp_tb(s, 0, s->pc); | |
1678 | } else { | |
1679 | /* Unconditional branch. */ | |
1680 | gen_jmp_tb(s, 0, base + offset); | |
1681 | } | |
1682 | } | |
1683 | ||
1684 | DISAS_INSN(moveq) | |
1685 | { | |
e1f3808e | 1686 | uint32_t val; |
e6e5906b | 1687 | |
e1f3808e PB |
1688 | val = (int8_t)insn; |
1689 | tcg_gen_movi_i32(DREG(insn, 9), val); | |
1690 | gen_logic_cc(s, tcg_const_i32(val)); | |
e6e5906b PB |
1691 | } |
1692 | ||
1693 | DISAS_INSN(mvzs) | |
1694 | { | |
1695 | int opsize; | |
e1f3808e PB |
1696 | TCGv src; |
1697 | TCGv reg; | |
e6e5906b PB |
1698 | |
1699 | if (insn & 0x40) | |
1700 | opsize = OS_WORD; | |
1701 | else | |
1702 | opsize = OS_BYTE; | |
d4d79bb1 | 1703 | SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); |
e6e5906b | 1704 | reg = DREG(insn, 9); |
e1f3808e | 1705 | tcg_gen_mov_i32(reg, src); |
e6e5906b PB |
1706 | gen_logic_cc(s, src); |
1707 | } | |
1708 | ||
1709 | DISAS_INSN(or) | |
1710 | { | |
e1f3808e PB |
1711 | TCGv reg; |
1712 | TCGv dest; | |
1713 | TCGv src; | |
1714 | TCGv addr; | |
e6e5906b PB |
1715 | |
1716 | reg = DREG(insn, 9); | |
a7812ae4 | 1717 | dest = tcg_temp_new(); |
e6e5906b | 1718 | if (insn & 0x100) { |
d4d79bb1 | 1719 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1720 | tcg_gen_or_i32(dest, src, reg); |
d4d79bb1 | 1721 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1722 | } else { |
d4d79bb1 | 1723 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1724 | tcg_gen_or_i32(dest, src, reg); |
1725 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1726 | } |
1727 | gen_logic_cc(s, dest); | |
1728 | } | |
1729 | ||
1730 | DISAS_INSN(suba) | |
1731 | { | |
e1f3808e PB |
1732 | TCGv src; |
1733 | TCGv reg; | |
e6e5906b | 1734 | |
d4d79bb1 | 1735 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1736 | reg = AREG(insn, 9); |
e1f3808e | 1737 | tcg_gen_sub_i32(reg, reg, src); |
e6e5906b PB |
1738 | } |
1739 | ||
1740 | DISAS_INSN(subx) | |
1741 | { | |
e1f3808e PB |
1742 | TCGv reg; |
1743 | TCGv src; | |
e6e5906b PB |
1744 | |
1745 | gen_flush_flags(s); | |
1746 | reg = DREG(insn, 9); | |
1747 | src = DREG(insn, 0); | |
e1f3808e | 1748 | gen_helper_subx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1749 | } |
1750 | ||
1751 | DISAS_INSN(mov3q) | |
1752 | { | |
e1f3808e | 1753 | TCGv src; |
e6e5906b PB |
1754 | int val; |
1755 | ||
1756 | val = (insn >> 9) & 7; | |
1757 | if (val == 0) | |
1758 | val = -1; | |
351326a6 | 1759 | src = tcg_const_i32(val); |
e6e5906b | 1760 | gen_logic_cc(s, src); |
d4d79bb1 | 1761 | DEST_EA(env, insn, OS_LONG, src, NULL); |
e6e5906b PB |
1762 | } |
1763 | ||
1764 | DISAS_INSN(cmp) | |
1765 | { | |
1766 | int op; | |
e1f3808e PB |
1767 | TCGv src; |
1768 | TCGv reg; | |
1769 | TCGv dest; | |
e6e5906b PB |
1770 | int opsize; |
1771 | ||
1772 | op = (insn >> 6) & 3; | |
1773 | switch (op) { | |
1774 | case 0: /* cmp.b */ | |
1775 | opsize = OS_BYTE; | |
1776 | s->cc_op = CC_OP_CMPB; | |
1777 | break; | |
1778 | case 1: /* cmp.w */ | |
1779 | opsize = OS_WORD; | |
1780 | s->cc_op = CC_OP_CMPW; | |
1781 | break; | |
1782 | case 2: /* cmp.l */ | |
1783 | opsize = OS_LONG; | |
1784 | s->cc_op = CC_OP_SUB; | |
1785 | break; | |
1786 | default: | |
1787 | abort(); | |
1788 | } | |
d4d79bb1 | 1789 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1790 | reg = DREG(insn, 9); |
a7812ae4 | 1791 | dest = tcg_temp_new(); |
e1f3808e PB |
1792 | tcg_gen_sub_i32(dest, reg, src); |
1793 | gen_update_cc_add(dest, src); | |
e6e5906b PB |
1794 | } |
1795 | ||
1796 | DISAS_INSN(cmpa) | |
1797 | { | |
1798 | int opsize; | |
e1f3808e PB |
1799 | TCGv src; |
1800 | TCGv reg; | |
1801 | TCGv dest; | |
e6e5906b PB |
1802 | |
1803 | if (insn & 0x100) { | |
1804 | opsize = OS_LONG; | |
1805 | } else { | |
1806 | opsize = OS_WORD; | |
1807 | } | |
d4d79bb1 | 1808 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1809 | reg = AREG(insn, 9); |
a7812ae4 | 1810 | dest = tcg_temp_new(); |
e1f3808e PB |
1811 | tcg_gen_sub_i32(dest, reg, src); |
1812 | gen_update_cc_add(dest, src); | |
e6e5906b PB |
1813 | s->cc_op = CC_OP_SUB; |
1814 | } | |
1815 | ||
1816 | DISAS_INSN(eor) | |
1817 | { | |
e1f3808e PB |
1818 | TCGv src; |
1819 | TCGv reg; | |
1820 | TCGv dest; | |
1821 | TCGv addr; | |
e6e5906b | 1822 | |
d4d79bb1 | 1823 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e6e5906b | 1824 | reg = DREG(insn, 9); |
a7812ae4 | 1825 | dest = tcg_temp_new(); |
e1f3808e | 1826 | tcg_gen_xor_i32(dest, src, reg); |
e6e5906b | 1827 | gen_logic_cc(s, dest); |
d4d79bb1 | 1828 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1829 | } |
1830 | ||
1831 | DISAS_INSN(and) | |
1832 | { | |
e1f3808e PB |
1833 | TCGv src; |
1834 | TCGv reg; | |
1835 | TCGv dest; | |
1836 | TCGv addr; | |
e6e5906b PB |
1837 | |
1838 | reg = DREG(insn, 9); | |
a7812ae4 | 1839 | dest = tcg_temp_new(); |
e6e5906b | 1840 | if (insn & 0x100) { |
d4d79bb1 | 1841 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1842 | tcg_gen_and_i32(dest, src, reg); |
d4d79bb1 | 1843 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1844 | } else { |
d4d79bb1 | 1845 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1846 | tcg_gen_and_i32(dest, src, reg); |
1847 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1848 | } |
1849 | gen_logic_cc(s, dest); | |
1850 | } | |
1851 | ||
1852 | DISAS_INSN(adda) | |
1853 | { | |
e1f3808e PB |
1854 | TCGv src; |
1855 | TCGv reg; | |
e6e5906b | 1856 | |
d4d79bb1 | 1857 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1858 | reg = AREG(insn, 9); |
e1f3808e | 1859 | tcg_gen_add_i32(reg, reg, src); |
e6e5906b PB |
1860 | } |
1861 | ||
1862 | DISAS_INSN(addx) | |
1863 | { | |
e1f3808e PB |
1864 | TCGv reg; |
1865 | TCGv src; | |
e6e5906b PB |
1866 | |
1867 | gen_flush_flags(s); | |
1868 | reg = DREG(insn, 9); | |
1869 | src = DREG(insn, 0); | |
e1f3808e | 1870 | gen_helper_addx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1871 | s->cc_op = CC_OP_FLAGS; |
1872 | } | |
1873 | ||
e1f3808e | 1874 | /* TODO: This could be implemented without helper functions. */ |
e6e5906b PB |
1875 | DISAS_INSN(shift_im) |
1876 | { | |
e1f3808e | 1877 | TCGv reg; |
e6e5906b | 1878 | int tmp; |
e1f3808e | 1879 | TCGv shift; |
e6e5906b PB |
1880 | |
1881 | reg = DREG(insn, 0); | |
1882 | tmp = (insn >> 9) & 7; | |
1883 | if (tmp == 0) | |
e1f3808e | 1884 | tmp = 8; |
351326a6 | 1885 | shift = tcg_const_i32(tmp); |
e1f3808e | 1886 | /* No need to flush flags becuse we know we will set C flag. */ |
e6e5906b | 1887 | if (insn & 0x100) { |
e1f3808e | 1888 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1889 | } else { |
1890 | if (insn & 8) { | |
e1f3808e | 1891 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1892 | } else { |
e1f3808e | 1893 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1894 | } |
1895 | } | |
e1f3808e | 1896 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1897 | } |
1898 | ||
1899 | DISAS_INSN(shift_reg) | |
1900 | { | |
e1f3808e PB |
1901 | TCGv reg; |
1902 | TCGv shift; | |
e6e5906b PB |
1903 | |
1904 | reg = DREG(insn, 0); | |
e1f3808e PB |
1905 | shift = DREG(insn, 9); |
1906 | /* Shift by zero leaves C flag unmodified. */ | |
1907 | gen_flush_flags(s); | |
e6e5906b | 1908 | if (insn & 0x100) { |
e1f3808e | 1909 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1910 | } else { |
1911 | if (insn & 8) { | |
e1f3808e | 1912 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1913 | } else { |
e1f3808e | 1914 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1915 | } |
1916 | } | |
e1f3808e | 1917 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1918 | } |
1919 | ||
1920 | DISAS_INSN(ff1) | |
1921 | { | |
e1f3808e | 1922 | TCGv reg; |
821f7e76 PB |
1923 | reg = DREG(insn, 0); |
1924 | gen_logic_cc(s, reg); | |
e1f3808e | 1925 | gen_helper_ff1(reg, reg); |
e6e5906b PB |
1926 | } |
1927 | ||
e1f3808e | 1928 | static TCGv gen_get_sr(DisasContext *s) |
0633879f | 1929 | { |
e1f3808e PB |
1930 | TCGv ccr; |
1931 | TCGv sr; | |
0633879f PB |
1932 | |
1933 | ccr = gen_get_ccr(s); | |
a7812ae4 | 1934 | sr = tcg_temp_new(); |
e1f3808e PB |
1935 | tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); |
1936 | tcg_gen_or_i32(sr, sr, ccr); | |
0633879f PB |
1937 | return sr; |
1938 | } | |
1939 | ||
e6e5906b PB |
1940 | DISAS_INSN(strldsr) |
1941 | { | |
1942 | uint16_t ext; | |
1943 | uint32_t addr; | |
1944 | ||
1945 | addr = s->pc - 2; | |
d4d79bb1 | 1946 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 1947 | s->pc += 2; |
0633879f | 1948 | if (ext != 0x46FC) { |
e6e5906b | 1949 | gen_exception(s, addr, EXCP_UNSUPPORTED); |
0633879f PB |
1950 | return; |
1951 | } | |
d4d79bb1 | 1952 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
1953 | s->pc += 2; |
1954 | if (IS_USER(s) || (ext & SR_S) == 0) { | |
e6e5906b | 1955 | gen_exception(s, addr, EXCP_PRIVILEGE); |
0633879f PB |
1956 | return; |
1957 | } | |
1958 | gen_push(s, gen_get_sr(s)); | |
1959 | gen_set_sr_im(s, ext, 0); | |
e6e5906b PB |
1960 | } |
1961 | ||
1962 | DISAS_INSN(move_from_sr) | |
1963 | { | |
e1f3808e PB |
1964 | TCGv reg; |
1965 | TCGv sr; | |
0633879f PB |
1966 | |
1967 | if (IS_USER(s)) { | |
1968 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1969 | return; | |
1970 | } | |
1971 | sr = gen_get_sr(s); | |
1972 | reg = DREG(insn, 0); | |
1973 | gen_partset_reg(OS_WORD, reg, sr); | |
e6e5906b PB |
1974 | } |
1975 | ||
1976 | DISAS_INSN(move_to_sr) | |
1977 | { | |
0633879f PB |
1978 | if (IS_USER(s)) { |
1979 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1980 | return; | |
1981 | } | |
d4d79bb1 | 1982 | gen_set_sr(env, s, insn, 0); |
0633879f | 1983 | gen_lookup_tb(s); |
e6e5906b PB |
1984 | } |
1985 | ||
1986 | DISAS_INSN(move_from_usp) | |
1987 | { | |
0633879f PB |
1988 | if (IS_USER(s)) { |
1989 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1990 | return; | |
1991 | } | |
2a8327e8 GU |
1992 | tcg_gen_ld_i32(AREG(insn, 0), cpu_env, |
1993 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
1994 | } |
1995 | ||
1996 | DISAS_INSN(move_to_usp) | |
1997 | { | |
0633879f PB |
1998 | if (IS_USER(s)) { |
1999 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2000 | return; | |
2001 | } | |
2a8327e8 GU |
2002 | tcg_gen_st_i32(AREG(insn, 0), cpu_env, |
2003 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2004 | } |
2005 | ||
2006 | DISAS_INSN(halt) | |
2007 | { | |
e1f3808e | 2008 | gen_exception(s, s->pc, EXCP_HALT_INSN); |
e6e5906b PB |
2009 | } |
2010 | ||
2011 | DISAS_INSN(stop) | |
2012 | { | |
0633879f PB |
2013 | uint16_t ext; |
2014 | ||
2015 | if (IS_USER(s)) { | |
2016 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2017 | return; | |
2018 | } | |
2019 | ||
d4d79bb1 | 2020 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
2021 | s->pc += 2; |
2022 | ||
2023 | gen_set_sr_im(s, ext, 0); | |
259186a7 | 2024 | tcg_gen_movi_i32(cpu_halted, 1); |
e1f3808e | 2025 | gen_exception(s, s->pc, EXCP_HLT); |
e6e5906b PB |
2026 | } |
2027 | ||
2028 | DISAS_INSN(rte) | |
2029 | { | |
0633879f PB |
2030 | if (IS_USER(s)) { |
2031 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2032 | return; | |
2033 | } | |
2034 | gen_exception(s, s->pc - 2, EXCP_RTE); | |
e6e5906b PB |
2035 | } |
2036 | ||
2037 | DISAS_INSN(movec) | |
2038 | { | |
0633879f | 2039 | uint16_t ext; |
e1f3808e | 2040 | TCGv reg; |
0633879f PB |
2041 | |
2042 | if (IS_USER(s)) { | |
2043 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2044 | return; | |
2045 | } | |
2046 | ||
d4d79bb1 | 2047 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
2048 | s->pc += 2; |
2049 | ||
2050 | if (ext & 0x8000) { | |
2051 | reg = AREG(ext, 12); | |
2052 | } else { | |
2053 | reg = DREG(ext, 12); | |
2054 | } | |
e1f3808e | 2055 | gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); |
0633879f | 2056 | gen_lookup_tb(s); |
e6e5906b PB |
2057 | } |
2058 | ||
2059 | DISAS_INSN(intouch) | |
2060 | { | |
0633879f PB |
2061 | if (IS_USER(s)) { |
2062 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2063 | return; | |
2064 | } | |
2065 | /* ICache fetch. Implement as no-op. */ | |
e6e5906b PB |
2066 | } |
2067 | ||
2068 | DISAS_INSN(cpushl) | |
2069 | { | |
0633879f PB |
2070 | if (IS_USER(s)) { |
2071 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2072 | return; | |
2073 | } | |
2074 | /* Cache push/invalidate. Implement as no-op. */ | |
e6e5906b PB |
2075 | } |
2076 | ||
2077 | DISAS_INSN(wddata) | |
2078 | { | |
2079 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2080 | } | |
2081 | ||
2082 | DISAS_INSN(wdebug) | |
2083 | { | |
a47dddd7 AF |
2084 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2085 | ||
0633879f PB |
2086 | if (IS_USER(s)) { |
2087 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2088 | return; | |
2089 | } | |
2090 | /* TODO: Implement wdebug. */ | |
a47dddd7 | 2091 | cpu_abort(CPU(cpu), "WDEBUG not implemented"); |
e6e5906b PB |
2092 | } |
2093 | ||
2094 | DISAS_INSN(trap) | |
2095 | { | |
2096 | gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); | |
2097 | } | |
2098 | ||
2099 | /* ??? FP exceptions are not implemented. Most exceptions are deferred until | |
2100 | immediately before the next FP instruction is executed. */ | |
2101 | DISAS_INSN(fpu) | |
2102 | { | |
2103 | uint16_t ext; | |
a7812ae4 | 2104 | int32_t offset; |
e6e5906b | 2105 | int opmode; |
a7812ae4 PB |
2106 | TCGv_i64 src; |
2107 | TCGv_i64 dest; | |
2108 | TCGv_i64 res; | |
2109 | TCGv tmp32; | |
e6e5906b | 2110 | int round; |
a7812ae4 | 2111 | int set_dest; |
e6e5906b PB |
2112 | int opsize; |
2113 | ||
d4d79bb1 | 2114 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2115 | s->pc += 2; |
2116 | opmode = ext & 0x7f; | |
2117 | switch ((ext >> 13) & 7) { | |
2118 | case 0: case 2: | |
2119 | break; | |
2120 | case 1: | |
2121 | goto undef; | |
2122 | case 3: /* fmove out */ | |
2123 | src = FREG(ext, 7); | |
a7812ae4 | 2124 | tmp32 = tcg_temp_new_i32(); |
e6e5906b PB |
2125 | /* fmove */ |
2126 | /* ??? TODO: Proper behavior on overflow. */ | |
2127 | switch ((ext >> 10) & 7) { | |
2128 | case 0: | |
2129 | opsize = OS_LONG; | |
a7812ae4 | 2130 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2131 | break; |
2132 | case 1: | |
2133 | opsize = OS_SINGLE; | |
a7812ae4 | 2134 | gen_helper_f64_to_f32(tmp32, cpu_env, src); |
e6e5906b PB |
2135 | break; |
2136 | case 4: | |
2137 | opsize = OS_WORD; | |
a7812ae4 | 2138 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b | 2139 | break; |
a7812ae4 PB |
2140 | case 5: /* OS_DOUBLE */ |
2141 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2142 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2143 | case 2: |
2144 | case 3: | |
243ee8f7 | 2145 | break; |
a7812ae4 PB |
2146 | case 4: |
2147 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2148 | break; | |
2149 | case 5: | |
d4d79bb1 | 2150 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2151 | s->pc += 2; |
2152 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2153 | break; | |
2154 | default: | |
2155 | goto undef; | |
2156 | } | |
2157 | gen_store64(s, tmp32, src); | |
c59b97aa | 2158 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2159 | case 3: |
2160 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2161 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2162 | break; | |
2163 | case 4: | |
2164 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2165 | break; | |
2166 | } | |
2167 | tcg_temp_free_i32(tmp32); | |
2168 | return; | |
e6e5906b PB |
2169 | case 6: |
2170 | opsize = OS_BYTE; | |
a7812ae4 | 2171 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2172 | break; |
2173 | default: | |
2174 | goto undef; | |
2175 | } | |
d4d79bb1 | 2176 | DEST_EA(env, insn, opsize, tmp32, NULL); |
a7812ae4 | 2177 | tcg_temp_free_i32(tmp32); |
e6e5906b PB |
2178 | return; |
2179 | case 4: /* fmove to control register. */ | |
2180 | switch ((ext >> 10) & 7) { | |
2181 | case 4: /* FPCR */ | |
2182 | /* Not implemented. Ignore writes. */ | |
2183 | break; | |
2184 | case 1: /* FPIAR */ | |
2185 | case 2: /* FPSR */ | |
2186 | default: | |
2187 | cpu_abort(NULL, "Unimplemented: fmove to control %d", | |
2188 | (ext >> 10) & 7); | |
2189 | } | |
2190 | break; | |
2191 | case 5: /* fmove from control register. */ | |
2192 | switch ((ext >> 10) & 7) { | |
2193 | case 4: /* FPCR */ | |
2194 | /* Not implemented. Always return zero. */ | |
351326a6 | 2195 | tmp32 = tcg_const_i32(0); |
e6e5906b PB |
2196 | break; |
2197 | case 1: /* FPIAR */ | |
2198 | case 2: /* FPSR */ | |
2199 | default: | |
2200 | cpu_abort(NULL, "Unimplemented: fmove from control %d", | |
2201 | (ext >> 10) & 7); | |
2202 | goto undef; | |
2203 | } | |
d4d79bb1 | 2204 | DEST_EA(env, insn, OS_LONG, tmp32, NULL); |
e6e5906b | 2205 | break; |
5fafdf24 | 2206 | case 6: /* fmovem */ |
e6e5906b PB |
2207 | case 7: |
2208 | { | |
e1f3808e PB |
2209 | TCGv addr; |
2210 | uint16_t mask; | |
2211 | int i; | |
2212 | if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) | |
2213 | goto undef; | |
d4d79bb1 | 2214 | tmp32 = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2215 | if (IS_NULL_QREG(tmp32)) { |
e1f3808e PB |
2216 | gen_addr_fault(s); |
2217 | return; | |
2218 | } | |
a7812ae4 PB |
2219 | addr = tcg_temp_new_i32(); |
2220 | tcg_gen_mov_i32(addr, tmp32); | |
e1f3808e PB |
2221 | mask = 0x80; |
2222 | for (i = 0; i < 8; i++) { | |
2223 | if (ext & mask) { | |
e1f3808e PB |
2224 | dest = FREG(i, 0); |
2225 | if (ext & (1 << 13)) { | |
2226 | /* store */ | |
2227 | tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); | |
2228 | } else { | |
2229 | /* load */ | |
2230 | tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); | |
2231 | } | |
2232 | if (ext & (mask - 1)) | |
2233 | tcg_gen_addi_i32(addr, addr, 8); | |
e6e5906b | 2234 | } |
e1f3808e | 2235 | mask >>= 1; |
e6e5906b | 2236 | } |
18307f26 | 2237 | tcg_temp_free_i32(addr); |
e6e5906b PB |
2238 | } |
2239 | return; | |
2240 | } | |
2241 | if (ext & (1 << 14)) { | |
e6e5906b PB |
2242 | /* Source effective address. */ |
2243 | switch ((ext >> 10) & 7) { | |
2244 | case 0: opsize = OS_LONG; break; | |
2245 | case 1: opsize = OS_SINGLE; break; | |
2246 | case 4: opsize = OS_WORD; break; | |
2247 | case 5: opsize = OS_DOUBLE; break; | |
2248 | case 6: opsize = OS_BYTE; break; | |
2249 | default: | |
2250 | goto undef; | |
2251 | } | |
e6e5906b | 2252 | if (opsize == OS_DOUBLE) { |
a7812ae4 PB |
2253 | tmp32 = tcg_temp_new_i32(); |
2254 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2255 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2256 | case 2: |
2257 | case 3: | |
243ee8f7 | 2258 | break; |
a7812ae4 PB |
2259 | case 4: |
2260 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2261 | break; | |
2262 | case 5: | |
d4d79bb1 | 2263 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2264 | s->pc += 2; |
2265 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2266 | break; | |
2267 | case 7: | |
d4d79bb1 | 2268 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2269 | offset += s->pc - 2; |
2270 | s->pc += 2; | |
2271 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2272 | break; | |
2273 | default: | |
2274 | goto undef; | |
2275 | } | |
2276 | src = gen_load64(s, tmp32); | |
c59b97aa | 2277 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2278 | case 3: |
2279 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2280 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2281 | break; | |
2282 | case 4: | |
2283 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2284 | break; | |
2285 | } | |
2286 | tcg_temp_free_i32(tmp32); | |
e6e5906b | 2287 | } else { |
d4d79bb1 | 2288 | SRC_EA(env, tmp32, opsize, 1, NULL); |
a7812ae4 | 2289 | src = tcg_temp_new_i64(); |
e6e5906b PB |
2290 | switch (opsize) { |
2291 | case OS_LONG: | |
2292 | case OS_WORD: | |
2293 | case OS_BYTE: | |
a7812ae4 | 2294 | gen_helper_i32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2295 | break; |
2296 | case OS_SINGLE: | |
a7812ae4 | 2297 | gen_helper_f32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2298 | break; |
2299 | } | |
2300 | } | |
2301 | } else { | |
2302 | /* Source register. */ | |
2303 | src = FREG(ext, 10); | |
2304 | } | |
2305 | dest = FREG(ext, 7); | |
a7812ae4 | 2306 | res = tcg_temp_new_i64(); |
e6e5906b | 2307 | if (opmode != 0x3a) |
e1f3808e | 2308 | tcg_gen_mov_f64(res, dest); |
e6e5906b | 2309 | round = 1; |
a7812ae4 | 2310 | set_dest = 1; |
e6e5906b PB |
2311 | switch (opmode) { |
2312 | case 0: case 0x40: case 0x44: /* fmove */ | |
e1f3808e | 2313 | tcg_gen_mov_f64(res, src); |
e6e5906b PB |
2314 | break; |
2315 | case 1: /* fint */ | |
e1f3808e | 2316 | gen_helper_iround_f64(res, cpu_env, src); |
e6e5906b PB |
2317 | round = 0; |
2318 | break; | |
2319 | case 3: /* fintrz */ | |
e1f3808e | 2320 | gen_helper_itrunc_f64(res, cpu_env, src); |
e6e5906b PB |
2321 | round = 0; |
2322 | break; | |
2323 | case 4: case 0x41: case 0x45: /* fsqrt */ | |
e1f3808e | 2324 | gen_helper_sqrt_f64(res, cpu_env, src); |
e6e5906b PB |
2325 | break; |
2326 | case 0x18: case 0x58: case 0x5c: /* fabs */ | |
e1f3808e | 2327 | gen_helper_abs_f64(res, src); |
e6e5906b PB |
2328 | break; |
2329 | case 0x1a: case 0x5a: case 0x5e: /* fneg */ | |
e1f3808e | 2330 | gen_helper_chs_f64(res, src); |
e6e5906b PB |
2331 | break; |
2332 | case 0x20: case 0x60: case 0x64: /* fdiv */ | |
e1f3808e | 2333 | gen_helper_div_f64(res, cpu_env, res, src); |
e6e5906b PB |
2334 | break; |
2335 | case 0x22: case 0x62: case 0x66: /* fadd */ | |
e1f3808e | 2336 | gen_helper_add_f64(res, cpu_env, res, src); |
e6e5906b PB |
2337 | break; |
2338 | case 0x23: case 0x63: case 0x67: /* fmul */ | |
e1f3808e | 2339 | gen_helper_mul_f64(res, cpu_env, res, src); |
e6e5906b PB |
2340 | break; |
2341 | case 0x28: case 0x68: case 0x6c: /* fsub */ | |
e1f3808e | 2342 | gen_helper_sub_f64(res, cpu_env, res, src); |
e6e5906b PB |
2343 | break; |
2344 | case 0x38: /* fcmp */ | |
e1f3808e | 2345 | gen_helper_sub_cmp_f64(res, cpu_env, res, src); |
a7812ae4 | 2346 | set_dest = 0; |
e6e5906b PB |
2347 | round = 0; |
2348 | break; | |
2349 | case 0x3a: /* ftst */ | |
e1f3808e | 2350 | tcg_gen_mov_f64(res, src); |
a7812ae4 | 2351 | set_dest = 0; |
e6e5906b PB |
2352 | round = 0; |
2353 | break; | |
2354 | default: | |
2355 | goto undef; | |
2356 | } | |
a7812ae4 PB |
2357 | if (ext & (1 << 14)) { |
2358 | tcg_temp_free_i64(src); | |
2359 | } | |
e6e5906b PB |
2360 | if (round) { |
2361 | if (opmode & 0x40) { | |
2362 | if ((opmode & 0x4) != 0) | |
2363 | round = 0; | |
2364 | } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { | |
2365 | round = 0; | |
2366 | } | |
2367 | } | |
2368 | if (round) { | |
a7812ae4 | 2369 | TCGv tmp = tcg_temp_new_i32(); |
e1f3808e PB |
2370 | gen_helper_f64_to_f32(tmp, cpu_env, res); |
2371 | gen_helper_f32_to_f64(res, cpu_env, tmp); | |
a7812ae4 | 2372 | tcg_temp_free_i32(tmp); |
5fafdf24 | 2373 | } |
e1f3808e | 2374 | tcg_gen_mov_f64(QREG_FP_RESULT, res); |
a7812ae4 | 2375 | if (set_dest) { |
e1f3808e | 2376 | tcg_gen_mov_f64(dest, res); |
e6e5906b | 2377 | } |
a7812ae4 | 2378 | tcg_temp_free_i64(res); |
e6e5906b PB |
2379 | return; |
2380 | undef: | |
a7812ae4 | 2381 | /* FIXME: Is this right for offset addressing modes? */ |
e6e5906b | 2382 | s->pc -= 2; |
d4d79bb1 | 2383 | disas_undef_fpu(env, s, insn); |
e6e5906b PB |
2384 | } |
2385 | ||
2386 | DISAS_INSN(fbcc) | |
2387 | { | |
2388 | uint32_t offset; | |
2389 | uint32_t addr; | |
e1f3808e | 2390 | TCGv flag; |
42a268c2 | 2391 | TCGLabel *l1; |
e6e5906b PB |
2392 | |
2393 | addr = s->pc; | |
d4d79bb1 | 2394 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
2395 | s->pc += 2; |
2396 | if (insn & (1 << 6)) { | |
d4d79bb1 | 2397 | offset = (offset << 16) | cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2398 | s->pc += 2; |
2399 | } | |
2400 | ||
2401 | l1 = gen_new_label(); | |
2402 | /* TODO: Raise BSUN exception. */ | |
a7812ae4 | 2403 | flag = tcg_temp_new(); |
e1f3808e | 2404 | gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); |
e6e5906b PB |
2405 | /* Jump to l1 if condition is true. */ |
2406 | switch (insn & 0xf) { | |
2407 | case 0: /* f */ | |
2408 | break; | |
2409 | case 1: /* eq (=0) */ | |
e1f3808e | 2410 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2411 | break; |
2412 | case 2: /* ogt (=1) */ | |
e1f3808e | 2413 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2414 | break; |
2415 | case 3: /* oge (=0 or =1) */ | |
e1f3808e | 2416 | tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2417 | break; |
2418 | case 4: /* olt (=-1) */ | |
e1f3808e | 2419 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2420 | break; |
2421 | case 5: /* ole (=-1 or =0) */ | |
e1f3808e | 2422 | tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2423 | break; |
2424 | case 6: /* ogl (=-1 or =1) */ | |
e1f3808e PB |
2425 | tcg_gen_andi_i32(flag, flag, 1); |
2426 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2427 | break; |
2428 | case 7: /* or (=2) */ | |
e1f3808e | 2429 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2430 | break; |
2431 | case 8: /* un (<2) */ | |
e1f3808e | 2432 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2433 | break; |
2434 | case 9: /* ueq (=0 or =2) */ | |
e1f3808e PB |
2435 | tcg_gen_andi_i32(flag, flag, 1); |
2436 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2437 | break; |
2438 | case 10: /* ugt (>0) */ | |
e1f3808e | 2439 | tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2440 | break; |
2441 | case 11: /* uge (>=0) */ | |
e1f3808e | 2442 | tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2443 | break; |
2444 | case 12: /* ult (=-1 or =2) */ | |
e1f3808e | 2445 | tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2446 | break; |
2447 | case 13: /* ule (!=1) */ | |
e1f3808e | 2448 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2449 | break; |
2450 | case 14: /* ne (!=0) */ | |
e1f3808e | 2451 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2452 | break; |
2453 | case 15: /* t */ | |
e1f3808e | 2454 | tcg_gen_br(l1); |
e6e5906b PB |
2455 | break; |
2456 | } | |
2457 | gen_jmp_tb(s, 0, s->pc); | |
2458 | gen_set_label(l1); | |
2459 | gen_jmp_tb(s, 1, addr + offset); | |
2460 | } | |
2461 | ||
0633879f PB |
2462 | DISAS_INSN(frestore) |
2463 | { | |
a47dddd7 AF |
2464 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2465 | ||
0633879f | 2466 | /* TODO: Implement frestore. */ |
a47dddd7 | 2467 | cpu_abort(CPU(cpu), "FRESTORE not implemented"); |
0633879f PB |
2468 | } |
2469 | ||
2470 | DISAS_INSN(fsave) | |
2471 | { | |
a47dddd7 AF |
2472 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2473 | ||
0633879f | 2474 | /* TODO: Implement fsave. */ |
a47dddd7 | 2475 | cpu_abort(CPU(cpu), "FSAVE not implemented"); |
0633879f PB |
2476 | } |
2477 | ||
e1f3808e | 2478 | static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) |
acf930aa | 2479 | { |
a7812ae4 | 2480 | TCGv tmp = tcg_temp_new(); |
acf930aa PB |
2481 | if (s->env->macsr & MACSR_FI) { |
2482 | if (upper) | |
e1f3808e | 2483 | tcg_gen_andi_i32(tmp, val, 0xffff0000); |
acf930aa | 2484 | else |
e1f3808e | 2485 | tcg_gen_shli_i32(tmp, val, 16); |
acf930aa PB |
2486 | } else if (s->env->macsr & MACSR_SU) { |
2487 | if (upper) | |
e1f3808e | 2488 | tcg_gen_sari_i32(tmp, val, 16); |
acf930aa | 2489 | else |
e1f3808e | 2490 | tcg_gen_ext16s_i32(tmp, val); |
acf930aa PB |
2491 | } else { |
2492 | if (upper) | |
e1f3808e | 2493 | tcg_gen_shri_i32(tmp, val, 16); |
acf930aa | 2494 | else |
e1f3808e | 2495 | tcg_gen_ext16u_i32(tmp, val); |
acf930aa PB |
2496 | } |
2497 | return tmp; | |
2498 | } | |
2499 | ||
e1f3808e PB |
2500 | static void gen_mac_clear_flags(void) |
2501 | { | |
2502 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, | |
2503 | ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); | |
2504 | } | |
2505 | ||
acf930aa PB |
2506 | DISAS_INSN(mac) |
2507 | { | |
e1f3808e PB |
2508 | TCGv rx; |
2509 | TCGv ry; | |
acf930aa PB |
2510 | uint16_t ext; |
2511 | int acc; | |
e1f3808e PB |
2512 | TCGv tmp; |
2513 | TCGv addr; | |
2514 | TCGv loadval; | |
acf930aa | 2515 | int dual; |
e1f3808e PB |
2516 | TCGv saved_flags; |
2517 | ||
a7812ae4 PB |
2518 | if (!s->done_mac) { |
2519 | s->mactmp = tcg_temp_new_i64(); | |
2520 | s->done_mac = 1; | |
2521 | } | |
acf930aa | 2522 | |
d4d79bb1 | 2523 | ext = cpu_lduw_code(env, s->pc); |
acf930aa PB |
2524 | s->pc += 2; |
2525 | ||
2526 | acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); | |
2527 | dual = ((insn & 0x30) != 0 && (ext & 3) != 0); | |
d315c888 | 2528 | if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { |
d4d79bb1 | 2529 | disas_undef(env, s, insn); |
d315c888 PB |
2530 | return; |
2531 | } | |
acf930aa PB |
2532 | if (insn & 0x30) { |
2533 | /* MAC with load. */ | |
d4d79bb1 | 2534 | tmp = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2535 | addr = tcg_temp_new(); |
e1f3808e | 2536 | tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); |
acf930aa PB |
2537 | /* Load the value now to ensure correct exception behavior. |
2538 | Perform writeback after reading the MAC inputs. */ | |
2539 | loadval = gen_load(s, OS_LONG, addr, 0); | |
2540 | ||
2541 | acc ^= 1; | |
2542 | rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); | |
2543 | ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); | |
2544 | } else { | |
e1f3808e | 2545 | loadval = addr = NULL_QREG; |
acf930aa PB |
2546 | rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
2547 | ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
2548 | } | |
2549 | ||
e1f3808e PB |
2550 | gen_mac_clear_flags(); |
2551 | #if 0 | |
acf930aa | 2552 | l1 = -1; |
e1f3808e | 2553 | /* Disabled because conditional branches clobber temporary vars. */ |
acf930aa PB |
2554 | if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { |
2555 | /* Skip the multiply if we know we will ignore it. */ | |
2556 | l1 = gen_new_label(); | |
a7812ae4 | 2557 | tmp = tcg_temp_new(); |
e1f3808e | 2558 | tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); |
acf930aa PB |
2559 | gen_op_jmp_nz32(tmp, l1); |
2560 | } | |
e1f3808e | 2561 | #endif |
acf930aa PB |
2562 | |
2563 | if ((ext & 0x0800) == 0) { | |
2564 | /* Word. */ | |
2565 | rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); | |
2566 | ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); | |
2567 | } | |
2568 | if (s->env->macsr & MACSR_FI) { | |
e1f3808e | 2569 | gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2570 | } else { |
2571 | if (s->env->macsr & MACSR_SU) | |
e1f3808e | 2572 | gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); |
acf930aa | 2573 | else |
e1f3808e | 2574 | gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2575 | switch ((ext >> 9) & 3) { |
2576 | case 1: | |
e1f3808e | 2577 | tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2578 | break; |
2579 | case 3: | |
e1f3808e | 2580 | tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2581 | break; |
2582 | } | |
2583 | } | |
2584 | ||
2585 | if (dual) { | |
2586 | /* Save the overflow flag from the multiply. */ | |
a7812ae4 | 2587 | saved_flags = tcg_temp_new(); |
e1f3808e PB |
2588 | tcg_gen_mov_i32(saved_flags, QREG_MACSR); |
2589 | } else { | |
2590 | saved_flags = NULL_QREG; | |
acf930aa PB |
2591 | } |
2592 | ||
e1f3808e PB |
2593 | #if 0 |
2594 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2595 | if ((s->env->macsr & MACSR_OMC) != 0 && dual) { |
2596 | /* Skip the accumulate if the value is already saturated. */ | |
2597 | l1 = gen_new_label(); | |
a7812ae4 | 2598 | tmp = tcg_temp_new(); |
351326a6 | 2599 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2600 | gen_op_jmp_nz32(tmp, l1); |
2601 | } | |
e1f3808e | 2602 | #endif |
acf930aa PB |
2603 | |
2604 | if (insn & 0x100) | |
e1f3808e | 2605 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2606 | else |
e1f3808e | 2607 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa PB |
2608 | |
2609 | if (s->env->macsr & MACSR_FI) | |
e1f3808e | 2610 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2611 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2612 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2613 | else |
e1f3808e | 2614 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2615 | |
e1f3808e PB |
2616 | #if 0 |
2617 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2618 | if (l1 != -1) |
2619 | gen_set_label(l1); | |
e1f3808e | 2620 | #endif |
acf930aa PB |
2621 | |
2622 | if (dual) { | |
2623 | /* Dual accumulate variant. */ | |
2624 | acc = (ext >> 2) & 3; | |
2625 | /* Restore the overflow flag from the multiplier. */ | |
e1f3808e PB |
2626 | tcg_gen_mov_i32(QREG_MACSR, saved_flags); |
2627 | #if 0 | |
2628 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2629 | if ((s->env->macsr & MACSR_OMC) != 0) { |
2630 | /* Skip the accumulate if the value is already saturated. */ | |
2631 | l1 = gen_new_label(); | |
a7812ae4 | 2632 | tmp = tcg_temp_new(); |
351326a6 | 2633 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2634 | gen_op_jmp_nz32(tmp, l1); |
2635 | } | |
e1f3808e | 2636 | #endif |
acf930aa | 2637 | if (ext & 2) |
e1f3808e | 2638 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2639 | else |
e1f3808e | 2640 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2641 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2642 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2643 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2644 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2645 | else |
e1f3808e PB |
2646 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
2647 | #if 0 | |
2648 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2649 | if (l1 != -1) |
2650 | gen_set_label(l1); | |
e1f3808e | 2651 | #endif |
acf930aa | 2652 | } |
e1f3808e | 2653 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); |
acf930aa PB |
2654 | |
2655 | if (insn & 0x30) { | |
e1f3808e | 2656 | TCGv rw; |
acf930aa | 2657 | rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
e1f3808e | 2658 | tcg_gen_mov_i32(rw, loadval); |
acf930aa PB |
2659 | /* FIXME: Should address writeback happen with the masked or |
2660 | unmasked value? */ | |
2661 | switch ((insn >> 3) & 7) { | |
2662 | case 3: /* Post-increment. */ | |
e1f3808e | 2663 | tcg_gen_addi_i32(AREG(insn, 0), addr, 4); |
acf930aa PB |
2664 | break; |
2665 | case 4: /* Pre-decrement. */ | |
e1f3808e | 2666 | tcg_gen_mov_i32(AREG(insn, 0), addr); |
acf930aa PB |
2667 | } |
2668 | } | |
2669 | } | |
2670 | ||
2671 | DISAS_INSN(from_mac) | |
2672 | { | |
e1f3808e | 2673 | TCGv rx; |
a7812ae4 | 2674 | TCGv_i64 acc; |
e1f3808e | 2675 | int accnum; |
acf930aa PB |
2676 | |
2677 | rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e PB |
2678 | accnum = (insn >> 9) & 3; |
2679 | acc = MACREG(accnum); | |
acf930aa | 2680 | if (s->env->macsr & MACSR_FI) { |
a7812ae4 | 2681 | gen_helper_get_macf(rx, cpu_env, acc); |
acf930aa | 2682 | } else if ((s->env->macsr & MACSR_OMC) == 0) { |
ecc7b3aa | 2683 | tcg_gen_extrl_i64_i32(rx, acc); |
acf930aa | 2684 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2685 | gen_helper_get_macs(rx, acc); |
acf930aa | 2686 | } else { |
e1f3808e PB |
2687 | gen_helper_get_macu(rx, acc); |
2688 | } | |
2689 | if (insn & 0x40) { | |
2690 | tcg_gen_movi_i64(acc, 0); | |
2691 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
acf930aa | 2692 | } |
acf930aa PB |
2693 | } |
2694 | ||
2695 | DISAS_INSN(move_mac) | |
2696 | { | |
e1f3808e | 2697 | /* FIXME: This can be done without a helper. */ |
acf930aa | 2698 | int src; |
e1f3808e | 2699 | TCGv dest; |
acf930aa | 2700 | src = insn & 3; |
e1f3808e PB |
2701 | dest = tcg_const_i32((insn >> 9) & 3); |
2702 | gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); | |
2703 | gen_mac_clear_flags(); | |
2704 | gen_helper_mac_set_flags(cpu_env, dest); | |
acf930aa PB |
2705 | } |
2706 | ||
2707 | DISAS_INSN(from_macsr) | |
2708 | { | |
e1f3808e | 2709 | TCGv reg; |
acf930aa PB |
2710 | |
2711 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e | 2712 | tcg_gen_mov_i32(reg, QREG_MACSR); |
acf930aa PB |
2713 | } |
2714 | ||
2715 | DISAS_INSN(from_mask) | |
2716 | { | |
e1f3808e | 2717 | TCGv reg; |
acf930aa | 2718 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2719 | tcg_gen_mov_i32(reg, QREG_MAC_MASK); |
acf930aa PB |
2720 | } |
2721 | ||
2722 | DISAS_INSN(from_mext) | |
2723 | { | |
e1f3808e PB |
2724 | TCGv reg; |
2725 | TCGv acc; | |
acf930aa | 2726 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2727 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2728 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2729 | gen_helper_get_mac_extf(reg, cpu_env, acc); |
acf930aa | 2730 | else |
e1f3808e | 2731 | gen_helper_get_mac_exti(reg, cpu_env, acc); |
acf930aa PB |
2732 | } |
2733 | ||
2734 | DISAS_INSN(macsr_to_ccr) | |
2735 | { | |
e1f3808e PB |
2736 | tcg_gen_movi_i32(QREG_CC_X, 0); |
2737 | tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf); | |
acf930aa PB |
2738 | s->cc_op = CC_OP_FLAGS; |
2739 | } | |
2740 | ||
2741 | DISAS_INSN(to_mac) | |
2742 | { | |
a7812ae4 | 2743 | TCGv_i64 acc; |
e1f3808e PB |
2744 | TCGv val; |
2745 | int accnum; | |
2746 | accnum = (insn >> 9) & 3; | |
2747 | acc = MACREG(accnum); | |
d4d79bb1 | 2748 | SRC_EA(env, val, OS_LONG, 0, NULL); |
acf930aa | 2749 | if (s->env->macsr & MACSR_FI) { |
e1f3808e PB |
2750 | tcg_gen_ext_i32_i64(acc, val); |
2751 | tcg_gen_shli_i64(acc, acc, 8); | |
acf930aa | 2752 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2753 | tcg_gen_ext_i32_i64(acc, val); |
acf930aa | 2754 | } else { |
e1f3808e | 2755 | tcg_gen_extu_i32_i64(acc, val); |
acf930aa | 2756 | } |
e1f3808e PB |
2757 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); |
2758 | gen_mac_clear_flags(); | |
2759 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); | |
acf930aa PB |
2760 | } |
2761 | ||
2762 | DISAS_INSN(to_macsr) | |
2763 | { | |
e1f3808e | 2764 | TCGv val; |
d4d79bb1 | 2765 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2766 | gen_helper_set_macsr(cpu_env, val); |
acf930aa PB |
2767 | gen_lookup_tb(s); |
2768 | } | |
2769 | ||
2770 | DISAS_INSN(to_mask) | |
2771 | { | |
e1f3808e | 2772 | TCGv val; |
d4d79bb1 | 2773 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2774 | tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); |
acf930aa PB |
2775 | } |
2776 | ||
2777 | DISAS_INSN(to_mext) | |
2778 | { | |
e1f3808e PB |
2779 | TCGv val; |
2780 | TCGv acc; | |
d4d79bb1 | 2781 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2782 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2783 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2784 | gen_helper_set_mac_extf(cpu_env, val, acc); |
acf930aa | 2785 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2786 | gen_helper_set_mac_exts(cpu_env, val, acc); |
acf930aa | 2787 | else |
e1f3808e | 2788 | gen_helper_set_mac_extu(cpu_env, val, acc); |
acf930aa PB |
2789 | } |
2790 | ||
e6e5906b PB |
2791 | static disas_proc opcode_table[65536]; |
2792 | ||
2793 | static void | |
2794 | register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) | |
2795 | { | |
2796 | int i; | |
2797 | int from; | |
2798 | int to; | |
2799 | ||
2800 | /* Sanity check. All set bits must be included in the mask. */ | |
5fc4adf6 PB |
2801 | if (opcode & ~mask) { |
2802 | fprintf(stderr, | |
2803 | "qemu internal error: bogus opcode definition %04x/%04x\n", | |
2804 | opcode, mask); | |
e6e5906b | 2805 | abort(); |
5fc4adf6 | 2806 | } |
e6e5906b PB |
2807 | /* This could probably be cleverer. For now just optimize the case where |
2808 | the top bits are known. */ | |
2809 | /* Find the first zero bit in the mask. */ | |
2810 | i = 0x8000; | |
2811 | while ((i & mask) != 0) | |
2812 | i >>= 1; | |
2813 | /* Iterate over all combinations of this and lower bits. */ | |
2814 | if (i == 0) | |
2815 | i = 1; | |
2816 | else | |
2817 | i <<= 1; | |
2818 | from = opcode & ~(i - 1); | |
2819 | to = from + i; | |
0633879f | 2820 | for (i = from; i < to; i++) { |
e6e5906b PB |
2821 | if ((i & mask) == opcode) |
2822 | opcode_table[i] = proc; | |
0633879f | 2823 | } |
e6e5906b PB |
2824 | } |
2825 | ||
2826 | /* Register m68k opcode handlers. Order is important. | |
2827 | Later insn override earlier ones. */ | |
0402f767 | 2828 | void register_m68k_insns (CPUM68KState *env) |
e6e5906b | 2829 | { |
d315c888 | 2830 | #define INSN(name, opcode, mask, feature) do { \ |
0402f767 | 2831 | if (m68k_feature(env, M68K_FEATURE_##feature)) \ |
d315c888 PB |
2832 | register_opcode(disas_##name, 0x##opcode, 0x##mask); \ |
2833 | } while(0) | |
0402f767 PB |
2834 | INSN(undef, 0000, 0000, CF_ISA_A); |
2835 | INSN(arith_im, 0080, fff8, CF_ISA_A); | |
d315c888 | 2836 | INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); |
0402f767 PB |
2837 | INSN(bitop_reg, 0100, f1c0, CF_ISA_A); |
2838 | INSN(bitop_reg, 0140, f1c0, CF_ISA_A); | |
2839 | INSN(bitop_reg, 0180, f1c0, CF_ISA_A); | |
2840 | INSN(bitop_reg, 01c0, f1c0, CF_ISA_A); | |
2841 | INSN(arith_im, 0280, fff8, CF_ISA_A); | |
d315c888 | 2842 | INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); |
0402f767 | 2843 | INSN(arith_im, 0480, fff8, CF_ISA_A); |
d315c888 | 2844 | INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); |
0402f767 PB |
2845 | INSN(arith_im, 0680, fff8, CF_ISA_A); |
2846 | INSN(bitop_im, 0800, ffc0, CF_ISA_A); | |
2847 | INSN(bitop_im, 0840, ffc0, CF_ISA_A); | |
2848 | INSN(bitop_im, 0880, ffc0, CF_ISA_A); | |
2849 | INSN(bitop_im, 08c0, ffc0, CF_ISA_A); | |
2850 | INSN(arith_im, 0a80, fff8, CF_ISA_A); | |
2851 | INSN(arith_im, 0c00, ff38, CF_ISA_A); | |
2852 | INSN(move, 1000, f000, CF_ISA_A); | |
2853 | INSN(move, 2000, f000, CF_ISA_A); | |
2854 | INSN(move, 3000, f000, CF_ISA_A); | |
d315c888 | 2855 | INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); |
0402f767 PB |
2856 | INSN(negx, 4080, fff8, CF_ISA_A); |
2857 | INSN(move_from_sr, 40c0, fff8, CF_ISA_A); | |
2858 | INSN(lea, 41c0, f1c0, CF_ISA_A); | |
2859 | INSN(clr, 4200, ff00, CF_ISA_A); | |
2860 | INSN(undef, 42c0, ffc0, CF_ISA_A); | |
2861 | INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); | |
2862 | INSN(neg, 4480, fff8, CF_ISA_A); | |
2863 | INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A); | |
2864 | INSN(not, 4680, fff8, CF_ISA_A); | |
2865 | INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); | |
2866 | INSN(pea, 4840, ffc0, CF_ISA_A); | |
2867 | INSN(swap, 4840, fff8, CF_ISA_A); | |
2868 | INSN(movem, 48c0, fbc0, CF_ISA_A); | |
2869 | INSN(ext, 4880, fff8, CF_ISA_A); | |
2870 | INSN(ext, 48c0, fff8, CF_ISA_A); | |
2871 | INSN(ext, 49c0, fff8, CF_ISA_A); | |
2872 | INSN(tst, 4a00, ff00, CF_ISA_A); | |
2873 | INSN(tas, 4ac0, ffc0, CF_ISA_B); | |
2874 | INSN(halt, 4ac8, ffff, CF_ISA_A); | |
2875 | INSN(pulse, 4acc, ffff, CF_ISA_A); | |
2876 | INSN(illegal, 4afc, ffff, CF_ISA_A); | |
2877 | INSN(mull, 4c00, ffc0, CF_ISA_A); | |
2878 | INSN(divl, 4c40, ffc0, CF_ISA_A); | |
2879 | INSN(sats, 4c80, fff8, CF_ISA_B); | |
2880 | INSN(trap, 4e40, fff0, CF_ISA_A); | |
2881 | INSN(link, 4e50, fff8, CF_ISA_A); | |
2882 | INSN(unlk, 4e58, fff8, CF_ISA_A); | |
20dcee94 PB |
2883 | INSN(move_to_usp, 4e60, fff8, USP); |
2884 | INSN(move_from_usp, 4e68, fff8, USP); | |
0402f767 PB |
2885 | INSN(nop, 4e71, ffff, CF_ISA_A); |
2886 | INSN(stop, 4e72, ffff, CF_ISA_A); | |
2887 | INSN(rte, 4e73, ffff, CF_ISA_A); | |
2888 | INSN(rts, 4e75, ffff, CF_ISA_A); | |
2889 | INSN(movec, 4e7b, ffff, CF_ISA_A); | |
2890 | INSN(jump, 4e80, ffc0, CF_ISA_A); | |
2891 | INSN(jump, 4ec0, ffc0, CF_ISA_A); | |
2892 | INSN(addsubq, 5180, f1c0, CF_ISA_A); | |
2893 | INSN(scc, 50c0, f0f8, CF_ISA_A); | |
2894 | INSN(addsubq, 5080, f1c0, CF_ISA_A); | |
2895 | INSN(tpf, 51f8, fff8, CF_ISA_A); | |
d315c888 PB |
2896 | |
2897 | /* Branch instructions. */ | |
0402f767 | 2898 | INSN(branch, 6000, f000, CF_ISA_A); |
d315c888 PB |
2899 | /* Disable long branch instructions, then add back the ones we want. */ |
2900 | INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */ | |
2901 | INSN(branch, 60ff, f0ff, CF_ISA_B); | |
2902 | INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ | |
2903 | INSN(branch, 60ff, ffff, BRAL); | |
2904 | ||
0402f767 PB |
2905 | INSN(moveq, 7000, f100, CF_ISA_A); |
2906 | INSN(mvzs, 7100, f100, CF_ISA_B); | |
2907 | INSN(or, 8000, f000, CF_ISA_A); | |
2908 | INSN(divw, 80c0, f0c0, CF_ISA_A); | |
2909 | INSN(addsub, 9000, f000, CF_ISA_A); | |
2910 | INSN(subx, 9180, f1f8, CF_ISA_A); | |
2911 | INSN(suba, 91c0, f1c0, CF_ISA_A); | |
acf930aa | 2912 | |
0402f767 | 2913 | INSN(undef_mac, a000, f000, CF_ISA_A); |
acf930aa PB |
2914 | INSN(mac, a000, f100, CF_EMAC); |
2915 | INSN(from_mac, a180, f9b0, CF_EMAC); | |
2916 | INSN(move_mac, a110, f9fc, CF_EMAC); | |
2917 | INSN(from_macsr,a980, f9f0, CF_EMAC); | |
2918 | INSN(from_mask, ad80, fff0, CF_EMAC); | |
2919 | INSN(from_mext, ab80, fbf0, CF_EMAC); | |
2920 | INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); | |
2921 | INSN(to_mac, a100, f9c0, CF_EMAC); | |
2922 | INSN(to_macsr, a900, ffc0, CF_EMAC); | |
2923 | INSN(to_mext, ab00, fbc0, CF_EMAC); | |
2924 | INSN(to_mask, ad00, ffc0, CF_EMAC); | |
2925 | ||
0402f767 PB |
2926 | INSN(mov3q, a140, f1c0, CF_ISA_B); |
2927 | INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ | |
2928 | INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ | |
2929 | INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ | |
2930 | INSN(cmp, b080, f1c0, CF_ISA_A); | |
2931 | INSN(cmpa, b1c0, f1c0, CF_ISA_A); | |
2932 | INSN(eor, b180, f1c0, CF_ISA_A); | |
2933 | INSN(and, c000, f000, CF_ISA_A); | |
2934 | INSN(mulw, c0c0, f0c0, CF_ISA_A); | |
2935 | INSN(addsub, d000, f000, CF_ISA_A); | |
2936 | INSN(addx, d180, f1f8, CF_ISA_A); | |
2937 | INSN(adda, d1c0, f1c0, CF_ISA_A); | |
2938 | INSN(shift_im, e080, f0f0, CF_ISA_A); | |
2939 | INSN(shift_reg, e0a0, f0f0, CF_ISA_A); | |
2940 | INSN(undef_fpu, f000, f000, CF_ISA_A); | |
e6e5906b PB |
2941 | INSN(fpu, f200, ffc0, CF_FPU); |
2942 | INSN(fbcc, f280, ffc0, CF_FPU); | |
0633879f PB |
2943 | INSN(frestore, f340, ffc0, CF_FPU); |
2944 | INSN(fsave, f340, ffc0, CF_FPU); | |
0402f767 PB |
2945 | INSN(intouch, f340, ffc0, CF_ISA_A); |
2946 | INSN(cpushl, f428, ff38, CF_ISA_A); | |
2947 | INSN(wddata, fb00, ff00, CF_ISA_A); | |
2948 | INSN(wdebug, fbc0, ffc0, CF_ISA_A); | |
e6e5906b PB |
2949 | #undef INSN |
2950 | } | |
2951 | ||
2952 | /* ??? Some of this implementation is not exception safe. We should always | |
2953 | write back the result to memory before setting the condition codes. */ | |
2b3e3cfe | 2954 | static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) |
e6e5906b PB |
2955 | { |
2956 | uint16_t insn; | |
2957 | ||
fa547e61 RH |
2958 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
2959 | tcg_gen_debug_insn_start(s->pc); | |
2960 | } | |
2961 | ||
d4d79bb1 | 2962 | insn = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2963 | s->pc += 2; |
2964 | ||
d4d79bb1 | 2965 | opcode_table[insn](env, s, insn); |
e6e5906b PB |
2966 | } |
2967 | ||
e6e5906b | 2968 | /* generate intermediate code for basic block 'tb'. */ |
2cfc5f17 | 2969 | static inline void |
c296b15b AF |
2970 | gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, |
2971 | bool search_pc) | |
e6e5906b | 2972 | { |
ed2803da | 2973 | CPUState *cs = CPU(cpu); |
c296b15b | 2974 | CPUM68KState *env = &cpu->env; |
e6e5906b | 2975 | DisasContext dc1, *dc = &dc1; |
a1d1bb31 | 2976 | CPUBreakpoint *bp; |
e6e5906b PB |
2977 | int j, lj; |
2978 | target_ulong pc_start; | |
2979 | int pc_offset; | |
2e70f6ef PB |
2980 | int num_insns; |
2981 | int max_insns; | |
e6e5906b PB |
2982 | |
2983 | /* generate intermediate code */ | |
2984 | pc_start = tb->pc; | |
3b46e624 | 2985 | |
e6e5906b PB |
2986 | dc->tb = tb; |
2987 | ||
e6dbd3b3 | 2988 | dc->env = env; |
e6e5906b PB |
2989 | dc->is_jmp = DISAS_NEXT; |
2990 | dc->pc = pc_start; | |
2991 | dc->cc_op = CC_OP_DYNAMIC; | |
ed2803da | 2992 | dc->singlestep_enabled = cs->singlestep_enabled; |
e6e5906b | 2993 | dc->fpcr = env->fpcr; |
0633879f | 2994 | dc->user = (env->sr & SR_S) == 0; |
a7812ae4 | 2995 | dc->done_mac = 0; |
e6e5906b | 2996 | lj = -1; |
2e70f6ef PB |
2997 | num_insns = 0; |
2998 | max_insns = tb->cflags & CF_COUNT_MASK; | |
2999 | if (max_insns == 0) | |
3000 | max_insns = CF_COUNT_MASK; | |
3001 | ||
cd42d5b2 | 3002 | gen_tb_start(tb); |
e6e5906b | 3003 | do { |
e6e5906b PB |
3004 | pc_offset = dc->pc - pc_start; |
3005 | gen_throws_exception = NULL; | |
f0c3c505 AF |
3006 | if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |
3007 | QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { | |
a1d1bb31 | 3008 | if (bp->pc == dc->pc) { |
e6e5906b PB |
3009 | gen_exception(dc, dc->pc, EXCP_DEBUG); |
3010 | dc->is_jmp = DISAS_JUMP; | |
3011 | break; | |
3012 | } | |
3013 | } | |
3014 | if (dc->is_jmp) | |
3015 | break; | |
3016 | } | |
3017 | if (search_pc) { | |
fe700adb | 3018 | j = tcg_op_buf_count(); |
e6e5906b PB |
3019 | if (lj < j) { |
3020 | lj++; | |
3021 | while (lj < j) | |
ab1103de | 3022 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
e6e5906b | 3023 | } |
25983cad | 3024 | tcg_ctx.gen_opc_pc[lj] = dc->pc; |
ab1103de | 3025 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 3026 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
e6e5906b | 3027 | } |
2e70f6ef PB |
3028 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
3029 | gen_io_start(); | |
510ff0b7 | 3030 | dc->insn_pc = dc->pc; |
e6e5906b | 3031 | disas_m68k_insn(env, dc); |
2e70f6ef | 3032 | num_insns++; |
fe700adb | 3033 | } while (!dc->is_jmp && !tcg_op_buf_full() && |
ed2803da | 3034 | !cs->singlestep_enabled && |
1b530a6d | 3035 | !singlestep && |
2e70f6ef PB |
3036 | (pc_offset) < (TARGET_PAGE_SIZE - 32) && |
3037 | num_insns < max_insns); | |
e6e5906b | 3038 | |
2e70f6ef PB |
3039 | if (tb->cflags & CF_LAST_IO) |
3040 | gen_io_end(); | |
ed2803da | 3041 | if (unlikely(cs->singlestep_enabled)) { |
e6e5906b PB |
3042 | /* Make sure the pc is updated, and raise a debug exception. */ |
3043 | if (!dc->is_jmp) { | |
3044 | gen_flush_cc_op(dc); | |
e1f3808e | 3045 | tcg_gen_movi_i32(QREG_PC, dc->pc); |
e6e5906b | 3046 | } |
31871141 | 3047 | gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); |
e6e5906b PB |
3048 | } else { |
3049 | switch(dc->is_jmp) { | |
3050 | case DISAS_NEXT: | |
3051 | gen_flush_cc_op(dc); | |
3052 | gen_jmp_tb(dc, 0, dc->pc); | |
3053 | break; | |
3054 | default: | |
3055 | case DISAS_JUMP: | |
3056 | case DISAS_UPDATE: | |
3057 | gen_flush_cc_op(dc); | |
3058 | /* indicate that the hash table must be used to find the next TB */ | |
57fec1fe | 3059 | tcg_gen_exit_tb(0); |
e6e5906b PB |
3060 | break; |
3061 | case DISAS_TB_JUMP: | |
3062 | /* nothing more to generate */ | |
3063 | break; | |
3064 | } | |
3065 | } | |
806f352d | 3066 | gen_tb_end(tb, num_insns); |
e6e5906b PB |
3067 | |
3068 | #ifdef DEBUG_DISAS | |
8fec2b8c | 3069 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
93fcfe39 AL |
3070 | qemu_log("----------------\n"); |
3071 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 3072 | log_target_disas(cs, pc_start, dc->pc - pc_start, 0); |
93fcfe39 | 3073 | qemu_log("\n"); |
e6e5906b PB |
3074 | } |
3075 | #endif | |
3076 | if (search_pc) { | |
fe700adb | 3077 | j = tcg_op_buf_count(); |
e6e5906b PB |
3078 | lj++; |
3079 | while (lj <= j) | |
ab1103de | 3080 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
e6e5906b PB |
3081 | } else { |
3082 | tb->size = dc->pc - pc_start; | |
2e70f6ef | 3083 | tb->icount = num_insns; |
e6e5906b PB |
3084 | } |
3085 | ||
3086 | //optimize_flags(); | |
3087 | //expand_target_qops(); | |
e6e5906b PB |
3088 | } |
3089 | ||
2b3e3cfe | 3090 | void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 3091 | { |
c296b15b | 3092 | gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, false); |
e6e5906b PB |
3093 | } |
3094 | ||
2b3e3cfe | 3095 | void gen_intermediate_code_pc(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 3096 | { |
c296b15b | 3097 | gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, true); |
e6e5906b PB |
3098 | } |
3099 | ||
878096ee AF |
3100 | void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
3101 | int flags) | |
e6e5906b | 3102 | { |
878096ee AF |
3103 | M68kCPU *cpu = M68K_CPU(cs); |
3104 | CPUM68KState *env = &cpu->env; | |
e6e5906b PB |
3105 | int i; |
3106 | uint16_t sr; | |
3107 | CPU_DoubleU u; | |
3108 | for (i = 0; i < 8; i++) | |
3109 | { | |
3110 | u.d = env->fregs[i]; | |
3111 | cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", | |
3112 | i, env->dregs[i], i, env->aregs[i], | |
8fc7cc58 | 3113 | i, u.l.upper, u.l.lower, *(double *)&u.d); |
e6e5906b PB |
3114 | } |
3115 | cpu_fprintf (f, "PC = %08x ", env->pc); | |
3116 | sr = env->sr; | |
3117 | cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-', | |
3118 | (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', | |
3119 | (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); | |
8fc7cc58 | 3120 | cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); |
e6e5906b PB |
3121 | } |
3122 | ||
2b3e3cfe | 3123 | void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 3124 | { |
25983cad | 3125 | env->pc = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 3126 | } |