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Commit | Line | Data |
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e6e5906b PB |
1 | /* |
2 | * m68k translation | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
e6e5906b | 20 | |
d8416665 | 21 | #include "qemu/osdep.h" |
e6e5906b | 22 | #include "cpu.h" |
76cad711 | 23 | #include "disas/disas.h" |
57fec1fe | 24 | #include "tcg-op.h" |
1de7afc9 | 25 | #include "qemu/log.h" |
f08b6170 | 26 | #include "exec/cpu_ldst.h" |
e1f3808e | 27 | |
2ef6175a RH |
28 | #include "exec/helper-proto.h" |
29 | #include "exec/helper-gen.h" | |
e6e5906b | 30 | |
a7e30d84 | 31 | #include "trace-tcg.h" |
508127e2 | 32 | #include "exec/log.h" |
a7e30d84 LV |
33 | |
34 | ||
0633879f PB |
35 | //#define DEBUG_DISPATCH 1 |
36 | ||
815a6742 | 37 | /* Fake floating point. */ |
815a6742 | 38 | #define tcg_gen_mov_f64 tcg_gen_mov_i64 |
815a6742 | 39 | #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 |
815a6742 | 40 | #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 |
815a6742 | 41 | |
e1f3808e | 42 | #define DEFO32(name, offset) static TCGv QREG_##name; |
a7812ae4 PB |
43 | #define DEFO64(name, offset) static TCGv_i64 QREG_##name; |
44 | #define DEFF64(name, offset) static TCGv_i64 QREG_##name; | |
e1f3808e PB |
45 | #include "qregs.def" |
46 | #undef DEFO32 | |
47 | #undef DEFO64 | |
48 | #undef DEFF64 | |
49 | ||
259186a7 | 50 | static TCGv_i32 cpu_halted; |
27103424 | 51 | static TCGv_i32 cpu_exception_index; |
259186a7 | 52 | |
1bcea73e | 53 | static TCGv_env cpu_env; |
e1f3808e PB |
54 | |
55 | static char cpu_reg_names[3*8*3 + 5*4]; | |
56 | static TCGv cpu_dregs[8]; | |
57 | static TCGv cpu_aregs[8]; | |
a7812ae4 PB |
58 | static TCGv_i64 cpu_fregs[8]; |
59 | static TCGv_i64 cpu_macc[4]; | |
e1f3808e PB |
60 | |
61 | #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7] | |
62 | #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7] | |
63 | #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7] | |
64 | #define MACREG(acc) cpu_macc[acc] | |
65 | #define QREG_SP cpu_aregs[7] | |
66 | ||
67 | static TCGv NULL_QREG; | |
a7812ae4 | 68 | #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) |
e1f3808e PB |
69 | /* Used to distinguish stores from bad addressing modes. */ |
70 | static TCGv store_dummy; | |
71 | ||
022c62cb | 72 | #include "exec/gen-icount.h" |
2e70f6ef | 73 | |
e1f3808e PB |
74 | void m68k_tcg_init(void) |
75 | { | |
76 | char *p; | |
77 | int i; | |
78 | ||
e1ccc054 RH |
79 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
80 | ||
81 | #define DEFO32(name, offset) \ | |
82 | QREG_##name = tcg_global_mem_new_i32(cpu_env, \ | |
83 | offsetof(CPUM68KState, offset), #name); | |
84 | #define DEFO64(name, offset) \ | |
85 | QREG_##name = tcg_global_mem_new_i64(cpu_env, \ | |
86 | offsetof(CPUM68KState, offset), #name); | |
87 | #define DEFF64(name, offset) DEFO64(name, offset) | |
e1f3808e PB |
88 | #include "qregs.def" |
89 | #undef DEFO32 | |
90 | #undef DEFO64 | |
91 | #undef DEFF64 | |
92 | ||
e1ccc054 | 93 | cpu_halted = tcg_global_mem_new_i32(cpu_env, |
259186a7 AF |
94 | -offsetof(M68kCPU, env) + |
95 | offsetof(CPUState, halted), "HALTED"); | |
e1ccc054 | 96 | cpu_exception_index = tcg_global_mem_new_i32(cpu_env, |
27103424 AF |
97 | -offsetof(M68kCPU, env) + |
98 | offsetof(CPUState, exception_index), | |
99 | "EXCEPTION"); | |
259186a7 | 100 | |
e1f3808e PB |
101 | p = cpu_reg_names; |
102 | for (i = 0; i < 8; i++) { | |
103 | sprintf(p, "D%d", i); | |
e1ccc054 | 104 | cpu_dregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
105 | offsetof(CPUM68KState, dregs[i]), p); |
106 | p += 3; | |
107 | sprintf(p, "A%d", i); | |
e1ccc054 | 108 | cpu_aregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
109 | offsetof(CPUM68KState, aregs[i]), p); |
110 | p += 3; | |
111 | sprintf(p, "F%d", i); | |
e1ccc054 | 112 | cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
113 | offsetof(CPUM68KState, fregs[i]), p); |
114 | p += 3; | |
115 | } | |
116 | for (i = 0; i < 4; i++) { | |
117 | sprintf(p, "ACC%d", i); | |
e1ccc054 | 118 | cpu_macc[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
119 | offsetof(CPUM68KState, macc[i]), p); |
120 | p += 5; | |
121 | } | |
122 | ||
e1ccc054 RH |
123 | NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL"); |
124 | store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL"); | |
e1f3808e PB |
125 | } |
126 | ||
e6e5906b PB |
127 | /* internal defines */ |
128 | typedef struct DisasContext { | |
e6dbd3b3 | 129 | CPUM68KState *env; |
510ff0b7 | 130 | target_ulong insn_pc; /* Start of the current instruction. */ |
e6e5906b PB |
131 | target_ulong pc; |
132 | int is_jmp; | |
133 | int cc_op; | |
0633879f | 134 | int user; |
e6e5906b PB |
135 | uint32_t fpcr; |
136 | struct TranslationBlock *tb; | |
137 | int singlestep_enabled; | |
a7812ae4 PB |
138 | TCGv_i64 mactmp; |
139 | int done_mac; | |
e6e5906b PB |
140 | } DisasContext; |
141 | ||
142 | #define DISAS_JUMP_NEXT 4 | |
143 | ||
0633879f PB |
144 | #if defined(CONFIG_USER_ONLY) |
145 | #define IS_USER(s) 1 | |
146 | #else | |
147 | #define IS_USER(s) s->user | |
148 | #endif | |
149 | ||
e6e5906b PB |
150 | /* XXX: move that elsewhere */ |
151 | /* ??? Fix exceptions. */ | |
152 | static void *gen_throws_exception; | |
153 | #define gen_last_qop NULL | |
154 | ||
e6e5906b PB |
155 | #define OS_BYTE 0 |
156 | #define OS_WORD 1 | |
157 | #define OS_LONG 2 | |
158 | #define OS_SINGLE 4 | |
159 | #define OS_DOUBLE 5 | |
160 | ||
d4d79bb1 | 161 | typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); |
e6e5906b | 162 | |
0633879f | 163 | #ifdef DEBUG_DISPATCH |
d4d79bb1 BS |
164 | #define DISAS_INSN(name) \ |
165 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
166 | uint16_t insn); \ | |
167 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
168 | uint16_t insn) \ | |
169 | { \ | |
170 | qemu_log("Dispatch " #name "\n"); \ | |
171 | real_disas_##name(s, env, insn); \ | |
172 | } \ | |
173 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
174 | uint16_t insn) | |
0633879f | 175 | #else |
d4d79bb1 BS |
176 | #define DISAS_INSN(name) \ |
177 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
178 | uint16_t insn) | |
0633879f | 179 | #endif |
e6e5906b PB |
180 | |
181 | /* Generate a load from the specified address. Narrow values are | |
182 | sign extended to full register width. */ | |
e1f3808e | 183 | static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) |
e6e5906b | 184 | { |
e1f3808e PB |
185 | TCGv tmp; |
186 | int index = IS_USER(s); | |
a7812ae4 | 187 | tmp = tcg_temp_new_i32(); |
e6e5906b PB |
188 | switch(opsize) { |
189 | case OS_BYTE: | |
e6e5906b | 190 | if (sign) |
e1f3808e | 191 | tcg_gen_qemu_ld8s(tmp, addr, index); |
e6e5906b | 192 | else |
e1f3808e | 193 | tcg_gen_qemu_ld8u(tmp, addr, index); |
e6e5906b PB |
194 | break; |
195 | case OS_WORD: | |
e6e5906b | 196 | if (sign) |
e1f3808e | 197 | tcg_gen_qemu_ld16s(tmp, addr, index); |
e6e5906b | 198 | else |
e1f3808e | 199 | tcg_gen_qemu_ld16u(tmp, addr, index); |
e6e5906b PB |
200 | break; |
201 | case OS_LONG: | |
e6e5906b | 202 | case OS_SINGLE: |
a7812ae4 | 203 | tcg_gen_qemu_ld32u(tmp, addr, index); |
e6e5906b PB |
204 | break; |
205 | default: | |
7372c2b9 | 206 | g_assert_not_reached(); |
e6e5906b PB |
207 | } |
208 | gen_throws_exception = gen_last_qop; | |
209 | return tmp; | |
210 | } | |
211 | ||
a7812ae4 PB |
212 | static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) |
213 | { | |
214 | TCGv_i64 tmp; | |
215 | int index = IS_USER(s); | |
a7812ae4 PB |
216 | tmp = tcg_temp_new_i64(); |
217 | tcg_gen_qemu_ldf64(tmp, addr, index); | |
218 | gen_throws_exception = gen_last_qop; | |
219 | return tmp; | |
220 | } | |
221 | ||
e6e5906b | 222 | /* Generate a store. */ |
e1f3808e | 223 | static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) |
e6e5906b | 224 | { |
e1f3808e | 225 | int index = IS_USER(s); |
e6e5906b PB |
226 | switch(opsize) { |
227 | case OS_BYTE: | |
e1f3808e | 228 | tcg_gen_qemu_st8(val, addr, index); |
e6e5906b PB |
229 | break; |
230 | case OS_WORD: | |
e1f3808e | 231 | tcg_gen_qemu_st16(val, addr, index); |
e6e5906b PB |
232 | break; |
233 | case OS_LONG: | |
e6e5906b | 234 | case OS_SINGLE: |
a7812ae4 | 235 | tcg_gen_qemu_st32(val, addr, index); |
e6e5906b PB |
236 | break; |
237 | default: | |
7372c2b9 | 238 | g_assert_not_reached(); |
e6e5906b PB |
239 | } |
240 | gen_throws_exception = gen_last_qop; | |
241 | } | |
242 | ||
a7812ae4 PB |
243 | static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) |
244 | { | |
245 | int index = IS_USER(s); | |
a7812ae4 PB |
246 | tcg_gen_qemu_stf64(val, addr, index); |
247 | gen_throws_exception = gen_last_qop; | |
248 | } | |
249 | ||
e1f3808e PB |
250 | typedef enum { |
251 | EA_STORE, | |
252 | EA_LOADU, | |
253 | EA_LOADS | |
254 | } ea_what; | |
255 | ||
e6e5906b PB |
256 | /* Generate an unsigned load if VAL is 0 a signed load if val is -1, |
257 | otherwise generate a store. */ | |
e1f3808e PB |
258 | static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, |
259 | ea_what what) | |
e6e5906b | 260 | { |
e1f3808e | 261 | if (what == EA_STORE) { |
0633879f | 262 | gen_store(s, opsize, addr, val); |
e1f3808e | 263 | return store_dummy; |
e6e5906b | 264 | } else { |
e1f3808e | 265 | return gen_load(s, opsize, addr, what == EA_LOADS); |
e6e5906b PB |
266 | } |
267 | } | |
268 | ||
e6dbd3b3 | 269 | /* Read a 32-bit immediate constant. */ |
d4d79bb1 | 270 | static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) |
e6dbd3b3 PB |
271 | { |
272 | uint32_t im; | |
d4d79bb1 | 273 | im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16; |
e6dbd3b3 | 274 | s->pc += 2; |
d4d79bb1 | 275 | im |= cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
276 | s->pc += 2; |
277 | return im; | |
278 | } | |
279 | ||
280 | /* Calculate and address index. */ | |
e1f3808e | 281 | static TCGv gen_addr_index(uint16_t ext, TCGv tmp) |
e6dbd3b3 | 282 | { |
e1f3808e | 283 | TCGv add; |
e6dbd3b3 PB |
284 | int scale; |
285 | ||
286 | add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); | |
287 | if ((ext & 0x800) == 0) { | |
e1f3808e | 288 | tcg_gen_ext16s_i32(tmp, add); |
e6dbd3b3 PB |
289 | add = tmp; |
290 | } | |
291 | scale = (ext >> 9) & 3; | |
292 | if (scale != 0) { | |
e1f3808e | 293 | tcg_gen_shli_i32(tmp, add, scale); |
e6dbd3b3 PB |
294 | add = tmp; |
295 | } | |
296 | return add; | |
297 | } | |
298 | ||
e1f3808e PB |
299 | /* Handle a base + index + displacement effective addresss. |
300 | A NULL_QREG base means pc-relative. */ | |
a4356126 | 301 | static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) |
e6e5906b | 302 | { |
e6e5906b PB |
303 | uint32_t offset; |
304 | uint16_t ext; | |
e1f3808e PB |
305 | TCGv add; |
306 | TCGv tmp; | |
e6dbd3b3 | 307 | uint32_t bd, od; |
e6e5906b PB |
308 | |
309 | offset = s->pc; | |
d4d79bb1 | 310 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 311 | s->pc += 2; |
e6dbd3b3 PB |
312 | |
313 | if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) | |
e1f3808e | 314 | return NULL_QREG; |
e6dbd3b3 PB |
315 | |
316 | if (ext & 0x100) { | |
317 | /* full extension word format */ | |
318 | if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) | |
e1f3808e | 319 | return NULL_QREG; |
e6dbd3b3 PB |
320 | |
321 | if ((ext & 0x30) > 0x10) { | |
322 | /* base displacement */ | |
323 | if ((ext & 0x30) == 0x20) { | |
d4d79bb1 | 324 | bd = (int16_t)cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
325 | s->pc += 2; |
326 | } else { | |
d4d79bb1 | 327 | bd = read_im32(env, s); |
e6dbd3b3 PB |
328 | } |
329 | } else { | |
330 | bd = 0; | |
331 | } | |
a7812ae4 | 332 | tmp = tcg_temp_new(); |
e6dbd3b3 PB |
333 | if ((ext & 0x44) == 0) { |
334 | /* pre-index */ | |
335 | add = gen_addr_index(ext, tmp); | |
336 | } else { | |
e1f3808e | 337 | add = NULL_QREG; |
e6dbd3b3 PB |
338 | } |
339 | if ((ext & 0x80) == 0) { | |
340 | /* base not suppressed */ | |
e1f3808e | 341 | if (IS_NULL_QREG(base)) { |
351326a6 | 342 | base = tcg_const_i32(offset + bd); |
e6dbd3b3 PB |
343 | bd = 0; |
344 | } | |
e1f3808e PB |
345 | if (!IS_NULL_QREG(add)) { |
346 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 PB |
347 | add = tmp; |
348 | } else { | |
349 | add = base; | |
350 | } | |
351 | } | |
e1f3808e | 352 | if (!IS_NULL_QREG(add)) { |
e6dbd3b3 | 353 | if (bd != 0) { |
e1f3808e | 354 | tcg_gen_addi_i32(tmp, add, bd); |
e6dbd3b3 PB |
355 | add = tmp; |
356 | } | |
357 | } else { | |
351326a6 | 358 | add = tcg_const_i32(bd); |
e6dbd3b3 PB |
359 | } |
360 | if ((ext & 3) != 0) { | |
361 | /* memory indirect */ | |
362 | base = gen_load(s, OS_LONG, add, 0); | |
363 | if ((ext & 0x44) == 4) { | |
364 | add = gen_addr_index(ext, tmp); | |
e1f3808e | 365 | tcg_gen_add_i32(tmp, add, base); |
e6dbd3b3 PB |
366 | add = tmp; |
367 | } else { | |
368 | add = base; | |
369 | } | |
370 | if ((ext & 3) > 1) { | |
371 | /* outer displacement */ | |
372 | if ((ext & 3) == 2) { | |
d4d79bb1 | 373 | od = (int16_t)cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
374 | s->pc += 2; |
375 | } else { | |
d4d79bb1 | 376 | od = read_im32(env, s); |
e6dbd3b3 PB |
377 | } |
378 | } else { | |
379 | od = 0; | |
380 | } | |
381 | if (od != 0) { | |
e1f3808e | 382 | tcg_gen_addi_i32(tmp, add, od); |
e6dbd3b3 PB |
383 | add = tmp; |
384 | } | |
385 | } | |
e6e5906b | 386 | } else { |
e6dbd3b3 | 387 | /* brief extension word format */ |
a7812ae4 | 388 | tmp = tcg_temp_new(); |
e6dbd3b3 | 389 | add = gen_addr_index(ext, tmp); |
e1f3808e PB |
390 | if (!IS_NULL_QREG(base)) { |
391 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 | 392 | if ((int8_t)ext) |
e1f3808e | 393 | tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); |
e6dbd3b3 | 394 | } else { |
e1f3808e | 395 | tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); |
e6dbd3b3 PB |
396 | } |
397 | add = tmp; | |
e6e5906b | 398 | } |
e6dbd3b3 | 399 | return add; |
e6e5906b PB |
400 | } |
401 | ||
e6e5906b PB |
402 | /* Update the CPU env CC_OP state. */ |
403 | static inline void gen_flush_cc_op(DisasContext *s) | |
404 | { | |
405 | if (s->cc_op != CC_OP_DYNAMIC) | |
e1f3808e | 406 | tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); |
e6e5906b PB |
407 | } |
408 | ||
409 | /* Evaluate all the CC flags. */ | |
410 | static inline void gen_flush_flags(DisasContext *s) | |
411 | { | |
412 | if (s->cc_op == CC_OP_FLAGS) | |
413 | return; | |
0cf5c677 | 414 | gen_flush_cc_op(s); |
e1f3808e | 415 | gen_helper_flush_flags(cpu_env, QREG_CC_OP); |
e6e5906b PB |
416 | s->cc_op = CC_OP_FLAGS; |
417 | } | |
418 | ||
e1f3808e PB |
419 | static void gen_logic_cc(DisasContext *s, TCGv val) |
420 | { | |
421 | tcg_gen_mov_i32(QREG_CC_DEST, val); | |
422 | s->cc_op = CC_OP_LOGIC; | |
423 | } | |
424 | ||
425 | static void gen_update_cc_add(TCGv dest, TCGv src) | |
426 | { | |
427 | tcg_gen_mov_i32(QREG_CC_DEST, dest); | |
428 | tcg_gen_mov_i32(QREG_CC_SRC, src); | |
429 | } | |
430 | ||
e6e5906b PB |
431 | static inline int opsize_bytes(int opsize) |
432 | { | |
433 | switch (opsize) { | |
434 | case OS_BYTE: return 1; | |
435 | case OS_WORD: return 2; | |
436 | case OS_LONG: return 4; | |
437 | case OS_SINGLE: return 4; | |
438 | case OS_DOUBLE: return 8; | |
439 | default: | |
7372c2b9 | 440 | g_assert_not_reached(); |
e6e5906b PB |
441 | } |
442 | } | |
443 | ||
444 | /* Assign value to a register. If the width is less than the register width | |
445 | only the low part of the register is set. */ | |
e1f3808e | 446 | static void gen_partset_reg(int opsize, TCGv reg, TCGv val) |
e6e5906b | 447 | { |
e1f3808e | 448 | TCGv tmp; |
e6e5906b PB |
449 | switch (opsize) { |
450 | case OS_BYTE: | |
e1f3808e | 451 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
a7812ae4 | 452 | tmp = tcg_temp_new(); |
e1f3808e PB |
453 | tcg_gen_ext8u_i32(tmp, val); |
454 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
455 | break; |
456 | case OS_WORD: | |
e1f3808e | 457 | tcg_gen_andi_i32(reg, reg, 0xffff0000); |
a7812ae4 | 458 | tmp = tcg_temp_new(); |
e1f3808e PB |
459 | tcg_gen_ext16u_i32(tmp, val); |
460 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
461 | break; |
462 | case OS_LONG: | |
e6e5906b | 463 | case OS_SINGLE: |
a7812ae4 | 464 | tcg_gen_mov_i32(reg, val); |
e6e5906b PB |
465 | break; |
466 | default: | |
7372c2b9 | 467 | g_assert_not_reached(); |
e6e5906b PB |
468 | } |
469 | } | |
470 | ||
471 | /* Sign or zero extend a value. */ | |
e1f3808e | 472 | static inline TCGv gen_extend(TCGv val, int opsize, int sign) |
e6e5906b | 473 | { |
e1f3808e | 474 | TCGv tmp; |
e6e5906b PB |
475 | |
476 | switch (opsize) { | |
477 | case OS_BYTE: | |
a7812ae4 | 478 | tmp = tcg_temp_new(); |
e6e5906b | 479 | if (sign) |
e1f3808e | 480 | tcg_gen_ext8s_i32(tmp, val); |
e6e5906b | 481 | else |
e1f3808e | 482 | tcg_gen_ext8u_i32(tmp, val); |
e6e5906b PB |
483 | break; |
484 | case OS_WORD: | |
a7812ae4 | 485 | tmp = tcg_temp_new(); |
e6e5906b | 486 | if (sign) |
e1f3808e | 487 | tcg_gen_ext16s_i32(tmp, val); |
e6e5906b | 488 | else |
e1f3808e | 489 | tcg_gen_ext16u_i32(tmp, val); |
e6e5906b PB |
490 | break; |
491 | case OS_LONG: | |
e6e5906b | 492 | case OS_SINGLE: |
a7812ae4 | 493 | tmp = val; |
e6e5906b PB |
494 | break; |
495 | default: | |
7372c2b9 | 496 | g_assert_not_reached(); |
e6e5906b PB |
497 | } |
498 | return tmp; | |
499 | } | |
500 | ||
501 | /* Generate code for an "effective address". Does not adjust the base | |
1addc7c5 | 502 | register for autoincrement addressing modes. */ |
d4d79bb1 BS |
503 | static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
504 | int opsize) | |
e6e5906b | 505 | { |
e1f3808e PB |
506 | TCGv reg; |
507 | TCGv tmp; | |
e6e5906b PB |
508 | uint16_t ext; |
509 | uint32_t offset; | |
510 | ||
e6e5906b PB |
511 | switch ((insn >> 3) & 7) { |
512 | case 0: /* Data register direct. */ | |
513 | case 1: /* Address register direct. */ | |
e1f3808e | 514 | return NULL_QREG; |
e6e5906b PB |
515 | case 2: /* Indirect register */ |
516 | case 3: /* Indirect postincrement. */ | |
e1f3808e | 517 | return AREG(insn, 0); |
e6e5906b | 518 | case 4: /* Indirect predecrememnt. */ |
e1f3808e | 519 | reg = AREG(insn, 0); |
a7812ae4 | 520 | tmp = tcg_temp_new(); |
e1f3808e | 521 | tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); |
e6e5906b PB |
522 | return tmp; |
523 | case 5: /* Indirect displacement. */ | |
e1f3808e | 524 | reg = AREG(insn, 0); |
a7812ae4 | 525 | tmp = tcg_temp_new(); |
d4d79bb1 | 526 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 527 | s->pc += 2; |
e1f3808e | 528 | tcg_gen_addi_i32(tmp, reg, (int16_t)ext); |
e6e5906b PB |
529 | return tmp; |
530 | case 6: /* Indirect index + displacement. */ | |
e1f3808e | 531 | reg = AREG(insn, 0); |
a4356126 | 532 | return gen_lea_indexed(env, s, reg); |
e6e5906b | 533 | case 7: /* Other */ |
e1f3808e | 534 | switch (insn & 7) { |
e6e5906b | 535 | case 0: /* Absolute short. */ |
d4d79bb1 | 536 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b | 537 | s->pc += 2; |
351326a6 | 538 | return tcg_const_i32(offset); |
e6e5906b | 539 | case 1: /* Absolute long. */ |
d4d79bb1 | 540 | offset = read_im32(env, s); |
351326a6 | 541 | return tcg_const_i32(offset); |
e6e5906b | 542 | case 2: /* pc displacement */ |
e6e5906b | 543 | offset = s->pc; |
d4d79bb1 | 544 | offset += cpu_ldsw_code(env, s->pc); |
e6e5906b | 545 | s->pc += 2; |
351326a6 | 546 | return tcg_const_i32(offset); |
e6e5906b | 547 | case 3: /* pc index+displacement. */ |
a4356126 | 548 | return gen_lea_indexed(env, s, NULL_QREG); |
e6e5906b PB |
549 | case 4: /* Immediate. */ |
550 | default: | |
e1f3808e | 551 | return NULL_QREG; |
e6e5906b PB |
552 | } |
553 | } | |
554 | /* Should never happen. */ | |
e1f3808e | 555 | return NULL_QREG; |
e6e5906b PB |
556 | } |
557 | ||
558 | /* Helper function for gen_ea. Reuse the computed address between the | |
559 | for read/write operands. */ | |
d4d79bb1 BS |
560 | static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s, |
561 | uint16_t insn, int opsize, TCGv val, | |
562 | TCGv *addrp, ea_what what) | |
e6e5906b | 563 | { |
e1f3808e | 564 | TCGv tmp; |
e6e5906b | 565 | |
e1f3808e | 566 | if (addrp && what == EA_STORE) { |
e6e5906b PB |
567 | tmp = *addrp; |
568 | } else { | |
d4d79bb1 | 569 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
570 | if (IS_NULL_QREG(tmp)) |
571 | return tmp; | |
e6e5906b PB |
572 | if (addrp) |
573 | *addrp = tmp; | |
574 | } | |
e1f3808e | 575 | return gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
576 | } |
577 | ||
f38f7a84 | 578 | /* Generate code to load/store a value from/into an EA. If VAL > 0 this is |
e6e5906b PB |
579 | a write otherwise it is a read (0 == sign extend, -1 == zero extend). |
580 | ADDRP is non-null for readwrite operands. */ | |
d4d79bb1 BS |
581 | static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
582 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
e6e5906b | 583 | { |
e1f3808e PB |
584 | TCGv reg; |
585 | TCGv result; | |
e6e5906b PB |
586 | uint32_t offset; |
587 | ||
e6e5906b PB |
588 | switch ((insn >> 3) & 7) { |
589 | case 0: /* Data register direct. */ | |
e1f3808e PB |
590 | reg = DREG(insn, 0); |
591 | if (what == EA_STORE) { | |
e6e5906b | 592 | gen_partset_reg(opsize, reg, val); |
e1f3808e | 593 | return store_dummy; |
e6e5906b | 594 | } else { |
e1f3808e | 595 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
596 | } |
597 | case 1: /* Address register direct. */ | |
e1f3808e PB |
598 | reg = AREG(insn, 0); |
599 | if (what == EA_STORE) { | |
600 | tcg_gen_mov_i32(reg, val); | |
601 | return store_dummy; | |
e6e5906b | 602 | } else { |
e1f3808e | 603 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
604 | } |
605 | case 2: /* Indirect register */ | |
e1f3808e PB |
606 | reg = AREG(insn, 0); |
607 | return gen_ldst(s, opsize, reg, val, what); | |
e6e5906b | 608 | case 3: /* Indirect postincrement. */ |
e1f3808e PB |
609 | reg = AREG(insn, 0); |
610 | result = gen_ldst(s, opsize, reg, val, what); | |
e6e5906b PB |
611 | /* ??? This is not exception safe. The instruction may still |
612 | fault after this point. */ | |
e1f3808e PB |
613 | if (what == EA_STORE || !addrp) |
614 | tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize)); | |
e6e5906b PB |
615 | return result; |
616 | case 4: /* Indirect predecrememnt. */ | |
617 | { | |
e1f3808e PB |
618 | TCGv tmp; |
619 | if (addrp && what == EA_STORE) { | |
e6e5906b PB |
620 | tmp = *addrp; |
621 | } else { | |
d4d79bb1 | 622 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
623 | if (IS_NULL_QREG(tmp)) |
624 | return tmp; | |
e6e5906b PB |
625 | if (addrp) |
626 | *addrp = tmp; | |
627 | } | |
e1f3808e | 628 | result = gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
629 | /* ??? This is not exception safe. The instruction may still |
630 | fault after this point. */ | |
e1f3808e PB |
631 | if (what == EA_STORE || !addrp) { |
632 | reg = AREG(insn, 0); | |
633 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
634 | } |
635 | } | |
636 | return result; | |
637 | case 5: /* Indirect displacement. */ | |
638 | case 6: /* Indirect index + displacement. */ | |
d4d79bb1 | 639 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b | 640 | case 7: /* Other */ |
e1f3808e | 641 | switch (insn & 7) { |
e6e5906b PB |
642 | case 0: /* Absolute short. */ |
643 | case 1: /* Absolute long. */ | |
644 | case 2: /* pc displacement */ | |
645 | case 3: /* pc index+displacement. */ | |
d4d79bb1 | 646 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b PB |
647 | case 4: /* Immediate. */ |
648 | /* Sign extend values for consistency. */ | |
649 | switch (opsize) { | |
650 | case OS_BYTE: | |
31871141 | 651 | if (what == EA_LOADS) { |
d4d79bb1 | 652 | offset = cpu_ldsb_code(env, s->pc + 1); |
31871141 | 653 | } else { |
d4d79bb1 | 654 | offset = cpu_ldub_code(env, s->pc + 1); |
31871141 | 655 | } |
e6e5906b PB |
656 | s->pc += 2; |
657 | break; | |
658 | case OS_WORD: | |
31871141 | 659 | if (what == EA_LOADS) { |
d4d79bb1 | 660 | offset = cpu_ldsw_code(env, s->pc); |
31871141 | 661 | } else { |
d4d79bb1 | 662 | offset = cpu_lduw_code(env, s->pc); |
31871141 | 663 | } |
e6e5906b PB |
664 | s->pc += 2; |
665 | break; | |
666 | case OS_LONG: | |
d4d79bb1 | 667 | offset = read_im32(env, s); |
e6e5906b PB |
668 | break; |
669 | default: | |
7372c2b9 | 670 | g_assert_not_reached(); |
e6e5906b | 671 | } |
e1f3808e | 672 | return tcg_const_i32(offset); |
e6e5906b | 673 | default: |
e1f3808e | 674 | return NULL_QREG; |
e6e5906b PB |
675 | } |
676 | } | |
677 | /* Should never happen. */ | |
e1f3808e | 678 | return NULL_QREG; |
e6e5906b PB |
679 | } |
680 | ||
e1f3808e | 681 | /* This generates a conditional branch, clobbering all temporaries. */ |
42a268c2 | 682 | static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) |
e6e5906b | 683 | { |
e1f3808e | 684 | TCGv tmp; |
e6e5906b | 685 | |
e1f3808e PB |
686 | /* TODO: Optimize compare/branch pairs rather than always flushing |
687 | flag state to CC_OP_FLAGS. */ | |
e6e5906b PB |
688 | gen_flush_flags(s); |
689 | switch (cond) { | |
690 | case 0: /* T */ | |
e1f3808e | 691 | tcg_gen_br(l1); |
e6e5906b PB |
692 | break; |
693 | case 1: /* F */ | |
694 | break; | |
695 | case 2: /* HI (!C && !Z) */ | |
a7812ae4 | 696 | tmp = tcg_temp_new(); |
e1f3808e PB |
697 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
698 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
699 | break; |
700 | case 3: /* LS (C || Z) */ | |
a7812ae4 | 701 | tmp = tcg_temp_new(); |
e1f3808e PB |
702 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
703 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
704 | break; |
705 | case 4: /* CC (!C) */ | |
a7812ae4 | 706 | tmp = tcg_temp_new(); |
e1f3808e PB |
707 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
708 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
709 | break; |
710 | case 5: /* CS (C) */ | |
a7812ae4 | 711 | tmp = tcg_temp_new(); |
e1f3808e PB |
712 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
713 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
714 | break; |
715 | case 6: /* NE (!Z) */ | |
a7812ae4 | 716 | tmp = tcg_temp_new(); |
e1f3808e PB |
717 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
718 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
719 | break; |
720 | case 7: /* EQ (Z) */ | |
a7812ae4 | 721 | tmp = tcg_temp_new(); |
e1f3808e PB |
722 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
723 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
724 | break; |
725 | case 8: /* VC (!V) */ | |
a7812ae4 | 726 | tmp = tcg_temp_new(); |
e1f3808e PB |
727 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
728 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
729 | break; |
730 | case 9: /* VS (V) */ | |
a7812ae4 | 731 | tmp = tcg_temp_new(); |
e1f3808e PB |
732 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
733 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
734 | break; |
735 | case 10: /* PL (!N) */ | |
a7812ae4 | 736 | tmp = tcg_temp_new(); |
e1f3808e PB |
737 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
738 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
739 | break; |
740 | case 11: /* MI (N) */ | |
a7812ae4 | 741 | tmp = tcg_temp_new(); |
e1f3808e PB |
742 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
743 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
744 | break; |
745 | case 12: /* GE (!(N ^ V)) */ | |
a7812ae4 | 746 | tmp = tcg_temp_new(); |
e1f3808e PB |
747 | assert(CCF_V == (CCF_N >> 2)); |
748 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
749 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
750 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
751 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
752 | break; |
753 | case 13: /* LT (N ^ V) */ | |
a7812ae4 | 754 | tmp = tcg_temp_new(); |
e1f3808e PB |
755 | assert(CCF_V == (CCF_N >> 2)); |
756 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
757 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
758 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
759 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
760 | break; |
761 | case 14: /* GT (!(Z || (N ^ V))) */ | |
a7812ae4 | 762 | tmp = tcg_temp_new(); |
e1f3808e PB |
763 | assert(CCF_V == (CCF_N >> 2)); |
764 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
765 | tcg_gen_shri_i32(tmp, tmp, 2); | |
766 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
767 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
768 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
769 | break; |
770 | case 15: /* LE (Z || (N ^ V)) */ | |
a7812ae4 | 771 | tmp = tcg_temp_new(); |
e1f3808e PB |
772 | assert(CCF_V == (CCF_N >> 2)); |
773 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
774 | tcg_gen_shri_i32(tmp, tmp, 2); | |
775 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
776 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
777 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
778 | break; |
779 | default: | |
780 | /* Should ever happen. */ | |
781 | abort(); | |
782 | } | |
783 | } | |
784 | ||
785 | DISAS_INSN(scc) | |
786 | { | |
42a268c2 | 787 | TCGLabel *l1; |
e6e5906b | 788 | int cond; |
e1f3808e | 789 | TCGv reg; |
e6e5906b PB |
790 | |
791 | l1 = gen_new_label(); | |
792 | cond = (insn >> 8) & 0xf; | |
793 | reg = DREG(insn, 0); | |
e1f3808e PB |
794 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
795 | /* This is safe because we modify the reg directly, with no other values | |
796 | live. */ | |
e6e5906b | 797 | gen_jmpcc(s, cond ^ 1, l1); |
e1f3808e | 798 | tcg_gen_ori_i32(reg, reg, 0xff); |
e6e5906b PB |
799 | gen_set_label(l1); |
800 | } | |
801 | ||
0633879f PB |
802 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
803 | static void gen_lookup_tb(DisasContext *s) | |
804 | { | |
805 | gen_flush_cc_op(s); | |
e1f3808e | 806 | tcg_gen_movi_i32(QREG_PC, s->pc); |
0633879f PB |
807 | s->is_jmp = DISAS_UPDATE; |
808 | } | |
809 | ||
e1f3808e PB |
810 | /* Generate a jump to an immediate address. */ |
811 | static void gen_jmp_im(DisasContext *s, uint32_t dest) | |
812 | { | |
813 | gen_flush_cc_op(s); | |
814 | tcg_gen_movi_i32(QREG_PC, dest); | |
815 | s->is_jmp = DISAS_JUMP; | |
816 | } | |
817 | ||
818 | /* Generate a jump to the address in qreg DEST. */ | |
819 | static void gen_jmp(DisasContext *s, TCGv dest) | |
e6e5906b PB |
820 | { |
821 | gen_flush_cc_op(s); | |
e1f3808e | 822 | tcg_gen_mov_i32(QREG_PC, dest); |
e6e5906b PB |
823 | s->is_jmp = DISAS_JUMP; |
824 | } | |
825 | ||
826 | static void gen_exception(DisasContext *s, uint32_t where, int nr) | |
827 | { | |
828 | gen_flush_cc_op(s); | |
e1f3808e | 829 | gen_jmp_im(s, where); |
31871141 | 830 | gen_helper_raise_exception(cpu_env, tcg_const_i32(nr)); |
e6e5906b PB |
831 | } |
832 | ||
510ff0b7 PB |
833 | static inline void gen_addr_fault(DisasContext *s) |
834 | { | |
835 | gen_exception(s, s->insn_pc, EXCP_ADDRESS); | |
836 | } | |
837 | ||
d4d79bb1 BS |
838 | #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ |
839 | result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ | |
840 | op_sign ? EA_LOADS : EA_LOADU); \ | |
841 | if (IS_NULL_QREG(result)) { \ | |
842 | gen_addr_fault(s); \ | |
843 | return; \ | |
844 | } \ | |
510ff0b7 PB |
845 | } while (0) |
846 | ||
d4d79bb1 BS |
847 | #define DEST_EA(env, insn, opsize, val, addrp) do { \ |
848 | TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ | |
849 | if (IS_NULL_QREG(ea_result)) { \ | |
850 | gen_addr_fault(s); \ | |
851 | return; \ | |
852 | } \ | |
510ff0b7 PB |
853 | } while (0) |
854 | ||
e6e5906b PB |
855 | /* Generate a jump to an immediate address. */ |
856 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | |
857 | { | |
858 | TranslationBlock *tb; | |
859 | ||
860 | tb = s->tb; | |
551bd27f | 861 | if (unlikely(s->singlestep_enabled)) { |
e6e5906b PB |
862 | gen_exception(s, dest, EXCP_DEBUG); |
863 | } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || | |
5b053a4a | 864 | (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { |
57fec1fe | 865 | tcg_gen_goto_tb(n); |
e1f3808e | 866 | tcg_gen_movi_i32(QREG_PC, dest); |
8cfd0495 | 867 | tcg_gen_exit_tb((uintptr_t)tb + n); |
e6e5906b | 868 | } else { |
e1f3808e | 869 | gen_jmp_im(s, dest); |
57fec1fe | 870 | tcg_gen_exit_tb(0); |
e6e5906b PB |
871 | } |
872 | s->is_jmp = DISAS_TB_JUMP; | |
873 | } | |
874 | ||
875 | DISAS_INSN(undef_mac) | |
876 | { | |
877 | gen_exception(s, s->pc - 2, EXCP_LINEA); | |
878 | } | |
879 | ||
880 | DISAS_INSN(undef_fpu) | |
881 | { | |
882 | gen_exception(s, s->pc - 2, EXCP_LINEF); | |
883 | } | |
884 | ||
885 | DISAS_INSN(undef) | |
886 | { | |
a47dddd7 AF |
887 | M68kCPU *cpu = m68k_env_get_cpu(env); |
888 | ||
e6e5906b | 889 | gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); |
a47dddd7 | 890 | cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); |
e6e5906b PB |
891 | } |
892 | ||
893 | DISAS_INSN(mulw) | |
894 | { | |
e1f3808e PB |
895 | TCGv reg; |
896 | TCGv tmp; | |
897 | TCGv src; | |
e6e5906b PB |
898 | int sign; |
899 | ||
900 | sign = (insn & 0x100) != 0; | |
901 | reg = DREG(insn, 9); | |
a7812ae4 | 902 | tmp = tcg_temp_new(); |
e6e5906b | 903 | if (sign) |
e1f3808e | 904 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 905 | else |
e1f3808e | 906 | tcg_gen_ext16u_i32(tmp, reg); |
d4d79bb1 | 907 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e PB |
908 | tcg_gen_mul_i32(tmp, tmp, src); |
909 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
910 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
911 | gen_logic_cc(s, tmp); | |
912 | } | |
913 | ||
914 | DISAS_INSN(divw) | |
915 | { | |
e1f3808e PB |
916 | TCGv reg; |
917 | TCGv tmp; | |
918 | TCGv src; | |
e6e5906b PB |
919 | int sign; |
920 | ||
921 | sign = (insn & 0x100) != 0; | |
922 | reg = DREG(insn, 9); | |
923 | if (sign) { | |
e1f3808e | 924 | tcg_gen_ext16s_i32(QREG_DIV1, reg); |
e6e5906b | 925 | } else { |
e1f3808e | 926 | tcg_gen_ext16u_i32(QREG_DIV1, reg); |
e6e5906b | 927 | } |
d4d79bb1 | 928 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e | 929 | tcg_gen_mov_i32(QREG_DIV2, src); |
e6e5906b | 930 | if (sign) { |
e1f3808e | 931 | gen_helper_divs(cpu_env, tcg_const_i32(1)); |
e6e5906b | 932 | } else { |
e1f3808e | 933 | gen_helper_divu(cpu_env, tcg_const_i32(1)); |
e6e5906b PB |
934 | } |
935 | ||
a7812ae4 PB |
936 | tmp = tcg_temp_new(); |
937 | src = tcg_temp_new(); | |
e1f3808e PB |
938 | tcg_gen_ext16u_i32(tmp, QREG_DIV1); |
939 | tcg_gen_shli_i32(src, QREG_DIV2, 16); | |
940 | tcg_gen_or_i32(reg, tmp, src); | |
e6e5906b PB |
941 | s->cc_op = CC_OP_FLAGS; |
942 | } | |
943 | ||
944 | DISAS_INSN(divl) | |
945 | { | |
e1f3808e PB |
946 | TCGv num; |
947 | TCGv den; | |
948 | TCGv reg; | |
e6e5906b PB |
949 | uint16_t ext; |
950 | ||
d4d79bb1 | 951 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
952 | s->pc += 2; |
953 | if (ext & 0x87f8) { | |
954 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
955 | return; | |
956 | } | |
957 | num = DREG(ext, 12); | |
958 | reg = DREG(ext, 0); | |
e1f3808e | 959 | tcg_gen_mov_i32(QREG_DIV1, num); |
d4d79bb1 | 960 | SRC_EA(env, den, OS_LONG, 0, NULL); |
e1f3808e | 961 | tcg_gen_mov_i32(QREG_DIV2, den); |
e6e5906b | 962 | if (ext & 0x0800) { |
e1f3808e | 963 | gen_helper_divs(cpu_env, tcg_const_i32(0)); |
e6e5906b | 964 | } else { |
e1f3808e | 965 | gen_helper_divu(cpu_env, tcg_const_i32(0)); |
e6e5906b | 966 | } |
e1f3808e | 967 | if ((ext & 7) == ((ext >> 12) & 7)) { |
e6e5906b | 968 | /* div */ |
e1f3808e | 969 | tcg_gen_mov_i32 (reg, QREG_DIV1); |
e6e5906b PB |
970 | } else { |
971 | /* rem */ | |
e1f3808e | 972 | tcg_gen_mov_i32 (reg, QREG_DIV2); |
e6e5906b | 973 | } |
e6e5906b PB |
974 | s->cc_op = CC_OP_FLAGS; |
975 | } | |
976 | ||
977 | DISAS_INSN(addsub) | |
978 | { | |
e1f3808e PB |
979 | TCGv reg; |
980 | TCGv dest; | |
981 | TCGv src; | |
982 | TCGv tmp; | |
983 | TCGv addr; | |
e6e5906b PB |
984 | int add; |
985 | ||
986 | add = (insn & 0x4000) != 0; | |
987 | reg = DREG(insn, 9); | |
a7812ae4 | 988 | dest = tcg_temp_new(); |
e6e5906b | 989 | if (insn & 0x100) { |
d4d79bb1 | 990 | SRC_EA(env, tmp, OS_LONG, 0, &addr); |
e6e5906b PB |
991 | src = reg; |
992 | } else { | |
993 | tmp = reg; | |
d4d79bb1 | 994 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b PB |
995 | } |
996 | if (add) { | |
e1f3808e PB |
997 | tcg_gen_add_i32(dest, tmp, src); |
998 | gen_helper_xflag_lt(QREG_CC_X, dest, src); | |
e6e5906b PB |
999 | s->cc_op = CC_OP_ADD; |
1000 | } else { | |
e1f3808e PB |
1001 | gen_helper_xflag_lt(QREG_CC_X, tmp, src); |
1002 | tcg_gen_sub_i32(dest, tmp, src); | |
e6e5906b PB |
1003 | s->cc_op = CC_OP_SUB; |
1004 | } | |
e1f3808e | 1005 | gen_update_cc_add(dest, src); |
e6e5906b | 1006 | if (insn & 0x100) { |
d4d79bb1 | 1007 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1008 | } else { |
e1f3808e | 1009 | tcg_gen_mov_i32(reg, dest); |
e6e5906b PB |
1010 | } |
1011 | } | |
1012 | ||
1013 | ||
1014 | /* Reverse the order of the bits in REG. */ | |
1015 | DISAS_INSN(bitrev) | |
1016 | { | |
e1f3808e | 1017 | TCGv reg; |
e6e5906b | 1018 | reg = DREG(insn, 0); |
e1f3808e | 1019 | gen_helper_bitrev(reg, reg); |
e6e5906b PB |
1020 | } |
1021 | ||
1022 | DISAS_INSN(bitop_reg) | |
1023 | { | |
1024 | int opsize; | |
1025 | int op; | |
e1f3808e PB |
1026 | TCGv src1; |
1027 | TCGv src2; | |
1028 | TCGv tmp; | |
1029 | TCGv addr; | |
1030 | TCGv dest; | |
e6e5906b PB |
1031 | |
1032 | if ((insn & 0x38) != 0) | |
1033 | opsize = OS_BYTE; | |
1034 | else | |
1035 | opsize = OS_LONG; | |
1036 | op = (insn >> 6) & 3; | |
d4d79bb1 | 1037 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1038 | src2 = DREG(insn, 9); |
a7812ae4 | 1039 | dest = tcg_temp_new(); |
e6e5906b PB |
1040 | |
1041 | gen_flush_flags(s); | |
a7812ae4 | 1042 | tmp = tcg_temp_new(); |
e6e5906b | 1043 | if (opsize == OS_BYTE) |
e1f3808e | 1044 | tcg_gen_andi_i32(tmp, src2, 7); |
e6e5906b | 1045 | else |
e1f3808e | 1046 | tcg_gen_andi_i32(tmp, src2, 31); |
e6e5906b | 1047 | src2 = tmp; |
a7812ae4 | 1048 | tmp = tcg_temp_new(); |
e1f3808e PB |
1049 | tcg_gen_shr_i32(tmp, src1, src2); |
1050 | tcg_gen_andi_i32(tmp, tmp, 1); | |
1051 | tcg_gen_shli_i32(tmp, tmp, 2); | |
1052 | /* Clear CCF_Z if bit set. */ | |
1053 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1054 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1055 | ||
1056 | tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2); | |
e6e5906b PB |
1057 | switch (op) { |
1058 | case 1: /* bchg */ | |
e1f3808e | 1059 | tcg_gen_xor_i32(dest, src1, tmp); |
e6e5906b PB |
1060 | break; |
1061 | case 2: /* bclr */ | |
e1f3808e PB |
1062 | tcg_gen_not_i32(tmp, tmp); |
1063 | tcg_gen_and_i32(dest, src1, tmp); | |
e6e5906b PB |
1064 | break; |
1065 | case 3: /* bset */ | |
e1f3808e | 1066 | tcg_gen_or_i32(dest, src1, tmp); |
e6e5906b PB |
1067 | break; |
1068 | default: /* btst */ | |
1069 | break; | |
1070 | } | |
1071 | if (op) | |
d4d79bb1 | 1072 | DEST_EA(env, insn, opsize, dest, &addr); |
e6e5906b PB |
1073 | } |
1074 | ||
1075 | DISAS_INSN(sats) | |
1076 | { | |
e1f3808e | 1077 | TCGv reg; |
e6e5906b | 1078 | reg = DREG(insn, 0); |
e6e5906b | 1079 | gen_flush_flags(s); |
e1f3808e PB |
1080 | gen_helper_sats(reg, reg, QREG_CC_DEST); |
1081 | gen_logic_cc(s, reg); | |
e6e5906b PB |
1082 | } |
1083 | ||
e1f3808e | 1084 | static void gen_push(DisasContext *s, TCGv val) |
e6e5906b | 1085 | { |
e1f3808e | 1086 | TCGv tmp; |
e6e5906b | 1087 | |
a7812ae4 | 1088 | tmp = tcg_temp_new(); |
e1f3808e | 1089 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1090 | gen_store(s, OS_LONG, tmp, val); |
e1f3808e | 1091 | tcg_gen_mov_i32(QREG_SP, tmp); |
e6e5906b PB |
1092 | } |
1093 | ||
1094 | DISAS_INSN(movem) | |
1095 | { | |
e1f3808e | 1096 | TCGv addr; |
e6e5906b PB |
1097 | int i; |
1098 | uint16_t mask; | |
e1f3808e PB |
1099 | TCGv reg; |
1100 | TCGv tmp; | |
e6e5906b PB |
1101 | int is_load; |
1102 | ||
d4d79bb1 | 1103 | mask = cpu_lduw_code(env, s->pc); |
e6e5906b | 1104 | s->pc += 2; |
d4d79bb1 | 1105 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1106 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1107 | gen_addr_fault(s); |
1108 | return; | |
1109 | } | |
a7812ae4 | 1110 | addr = tcg_temp_new(); |
e1f3808e | 1111 | tcg_gen_mov_i32(addr, tmp); |
e6e5906b PB |
1112 | is_load = ((insn & 0x0400) != 0); |
1113 | for (i = 0; i < 16; i++, mask >>= 1) { | |
1114 | if (mask & 1) { | |
1115 | if (i < 8) | |
1116 | reg = DREG(i, 0); | |
1117 | else | |
1118 | reg = AREG(i, 0); | |
1119 | if (is_load) { | |
0633879f | 1120 | tmp = gen_load(s, OS_LONG, addr, 0); |
e1f3808e | 1121 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b | 1122 | } else { |
0633879f | 1123 | gen_store(s, OS_LONG, addr, reg); |
e6e5906b PB |
1124 | } |
1125 | if (mask != 1) | |
e1f3808e | 1126 | tcg_gen_addi_i32(addr, addr, 4); |
e6e5906b PB |
1127 | } |
1128 | } | |
1129 | } | |
1130 | ||
1131 | DISAS_INSN(bitop_im) | |
1132 | { | |
1133 | int opsize; | |
1134 | int op; | |
e1f3808e | 1135 | TCGv src1; |
e6e5906b PB |
1136 | uint32_t mask; |
1137 | int bitnum; | |
e1f3808e PB |
1138 | TCGv tmp; |
1139 | TCGv addr; | |
e6e5906b PB |
1140 | |
1141 | if ((insn & 0x38) != 0) | |
1142 | opsize = OS_BYTE; | |
1143 | else | |
1144 | opsize = OS_LONG; | |
1145 | op = (insn >> 6) & 3; | |
1146 | ||
d4d79bb1 | 1147 | bitnum = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
1148 | s->pc += 2; |
1149 | if (bitnum & 0xff00) { | |
d4d79bb1 | 1150 | disas_undef(env, s, insn); |
e6e5906b PB |
1151 | return; |
1152 | } | |
1153 | ||
d4d79bb1 | 1154 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b PB |
1155 | |
1156 | gen_flush_flags(s); | |
e6e5906b PB |
1157 | if (opsize == OS_BYTE) |
1158 | bitnum &= 7; | |
1159 | else | |
1160 | bitnum &= 31; | |
1161 | mask = 1 << bitnum; | |
1162 | ||
a7812ae4 | 1163 | tmp = tcg_temp_new(); |
e1f3808e PB |
1164 | assert (CCF_Z == (1 << 2)); |
1165 | if (bitnum > 2) | |
1166 | tcg_gen_shri_i32(tmp, src1, bitnum - 2); | |
1167 | else if (bitnum < 2) | |
1168 | tcg_gen_shli_i32(tmp, src1, 2 - bitnum); | |
e6e5906b | 1169 | else |
e1f3808e PB |
1170 | tcg_gen_mov_i32(tmp, src1); |
1171 | tcg_gen_andi_i32(tmp, tmp, CCF_Z); | |
1172 | /* Clear CCF_Z if bit set. */ | |
1173 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1174 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1175 | if (op) { | |
1176 | switch (op) { | |
1177 | case 1: /* bchg */ | |
1178 | tcg_gen_xori_i32(tmp, src1, mask); | |
1179 | break; | |
1180 | case 2: /* bclr */ | |
1181 | tcg_gen_andi_i32(tmp, src1, ~mask); | |
1182 | break; | |
1183 | case 3: /* bset */ | |
1184 | tcg_gen_ori_i32(tmp, src1, mask); | |
1185 | break; | |
1186 | default: /* btst */ | |
1187 | break; | |
1188 | } | |
d4d79bb1 | 1189 | DEST_EA(env, insn, opsize, tmp, &addr); |
e6e5906b | 1190 | } |
e6e5906b PB |
1191 | } |
1192 | ||
1193 | DISAS_INSN(arith_im) | |
1194 | { | |
1195 | int op; | |
e1f3808e PB |
1196 | uint32_t im; |
1197 | TCGv src1; | |
1198 | TCGv dest; | |
1199 | TCGv addr; | |
e6e5906b PB |
1200 | |
1201 | op = (insn >> 9) & 7; | |
d4d79bb1 BS |
1202 | SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr); |
1203 | im = read_im32(env, s); | |
a7812ae4 | 1204 | dest = tcg_temp_new(); |
e6e5906b PB |
1205 | switch (op) { |
1206 | case 0: /* ori */ | |
e1f3808e | 1207 | tcg_gen_ori_i32(dest, src1, im); |
e6e5906b PB |
1208 | gen_logic_cc(s, dest); |
1209 | break; | |
1210 | case 1: /* andi */ | |
e1f3808e | 1211 | tcg_gen_andi_i32(dest, src1, im); |
e6e5906b PB |
1212 | gen_logic_cc(s, dest); |
1213 | break; | |
1214 | case 2: /* subi */ | |
e1f3808e | 1215 | tcg_gen_mov_i32(dest, src1); |
351326a6 | 1216 | gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); |
e1f3808e | 1217 | tcg_gen_subi_i32(dest, dest, im); |
351326a6 | 1218 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1219 | s->cc_op = CC_OP_SUB; |
1220 | break; | |
1221 | case 3: /* addi */ | |
e1f3808e PB |
1222 | tcg_gen_mov_i32(dest, src1); |
1223 | tcg_gen_addi_i32(dest, dest, im); | |
351326a6 LV |
1224 | gen_update_cc_add(dest, tcg_const_i32(im)); |
1225 | gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); | |
e6e5906b PB |
1226 | s->cc_op = CC_OP_ADD; |
1227 | break; | |
1228 | case 5: /* eori */ | |
e1f3808e | 1229 | tcg_gen_xori_i32(dest, src1, im); |
e6e5906b PB |
1230 | gen_logic_cc(s, dest); |
1231 | break; | |
1232 | case 6: /* cmpi */ | |
e1f3808e PB |
1233 | tcg_gen_mov_i32(dest, src1); |
1234 | tcg_gen_subi_i32(dest, dest, im); | |
351326a6 | 1235 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1236 | s->cc_op = CC_OP_SUB; |
1237 | break; | |
1238 | default: | |
1239 | abort(); | |
1240 | } | |
1241 | if (op != 6) { | |
d4d79bb1 | 1242 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1243 | } |
1244 | } | |
1245 | ||
1246 | DISAS_INSN(byterev) | |
1247 | { | |
e1f3808e | 1248 | TCGv reg; |
e6e5906b PB |
1249 | |
1250 | reg = DREG(insn, 0); | |
66896cb8 | 1251 | tcg_gen_bswap32_i32(reg, reg); |
e6e5906b PB |
1252 | } |
1253 | ||
1254 | DISAS_INSN(move) | |
1255 | { | |
e1f3808e PB |
1256 | TCGv src; |
1257 | TCGv dest; | |
e6e5906b PB |
1258 | int op; |
1259 | int opsize; | |
1260 | ||
1261 | switch (insn >> 12) { | |
1262 | case 1: /* move.b */ | |
1263 | opsize = OS_BYTE; | |
1264 | break; | |
1265 | case 2: /* move.l */ | |
1266 | opsize = OS_LONG; | |
1267 | break; | |
1268 | case 3: /* move.w */ | |
1269 | opsize = OS_WORD; | |
1270 | break; | |
1271 | default: | |
1272 | abort(); | |
1273 | } | |
d4d79bb1 | 1274 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b PB |
1275 | op = (insn >> 6) & 7; |
1276 | if (op == 1) { | |
1277 | /* movea */ | |
1278 | /* The value will already have been sign extended. */ | |
1279 | dest = AREG(insn, 9); | |
e1f3808e | 1280 | tcg_gen_mov_i32(dest, src); |
e6e5906b PB |
1281 | } else { |
1282 | /* normal move */ | |
1283 | uint16_t dest_ea; | |
1284 | dest_ea = ((insn >> 9) & 7) | (op << 3); | |
d4d79bb1 | 1285 | DEST_EA(env, dest_ea, opsize, src, NULL); |
e6e5906b PB |
1286 | /* This will be correct because loads sign extend. */ |
1287 | gen_logic_cc(s, src); | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | DISAS_INSN(negx) | |
1292 | { | |
e1f3808e | 1293 | TCGv reg; |
e6e5906b PB |
1294 | |
1295 | gen_flush_flags(s); | |
1296 | reg = DREG(insn, 0); | |
e1f3808e | 1297 | gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg); |
e6e5906b PB |
1298 | } |
1299 | ||
1300 | DISAS_INSN(lea) | |
1301 | { | |
e1f3808e PB |
1302 | TCGv reg; |
1303 | TCGv tmp; | |
e6e5906b PB |
1304 | |
1305 | reg = AREG(insn, 9); | |
d4d79bb1 | 1306 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1307 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1308 | gen_addr_fault(s); |
1309 | return; | |
1310 | } | |
e1f3808e | 1311 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1312 | } |
1313 | ||
1314 | DISAS_INSN(clr) | |
1315 | { | |
1316 | int opsize; | |
1317 | ||
1318 | switch ((insn >> 6) & 3) { | |
1319 | case 0: /* clr.b */ | |
1320 | opsize = OS_BYTE; | |
1321 | break; | |
1322 | case 1: /* clr.w */ | |
1323 | opsize = OS_WORD; | |
1324 | break; | |
1325 | case 2: /* clr.l */ | |
1326 | opsize = OS_LONG; | |
1327 | break; | |
1328 | default: | |
1329 | abort(); | |
1330 | } | |
d4d79bb1 | 1331 | DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL); |
351326a6 | 1332 | gen_logic_cc(s, tcg_const_i32(0)); |
e6e5906b PB |
1333 | } |
1334 | ||
e1f3808e | 1335 | static TCGv gen_get_ccr(DisasContext *s) |
e6e5906b | 1336 | { |
e1f3808e | 1337 | TCGv dest; |
e6e5906b PB |
1338 | |
1339 | gen_flush_flags(s); | |
a7812ae4 | 1340 | dest = tcg_temp_new(); |
e1f3808e PB |
1341 | tcg_gen_shli_i32(dest, QREG_CC_X, 4); |
1342 | tcg_gen_or_i32(dest, dest, QREG_CC_DEST); | |
0633879f PB |
1343 | return dest; |
1344 | } | |
1345 | ||
1346 | DISAS_INSN(move_from_ccr) | |
1347 | { | |
e1f3808e PB |
1348 | TCGv reg; |
1349 | TCGv ccr; | |
0633879f PB |
1350 | |
1351 | ccr = gen_get_ccr(s); | |
e6e5906b | 1352 | reg = DREG(insn, 0); |
0633879f | 1353 | gen_partset_reg(OS_WORD, reg, ccr); |
e6e5906b PB |
1354 | } |
1355 | ||
1356 | DISAS_INSN(neg) | |
1357 | { | |
e1f3808e PB |
1358 | TCGv reg; |
1359 | TCGv src1; | |
e6e5906b PB |
1360 | |
1361 | reg = DREG(insn, 0); | |
a7812ae4 | 1362 | src1 = tcg_temp_new(); |
e1f3808e PB |
1363 | tcg_gen_mov_i32(src1, reg); |
1364 | tcg_gen_neg_i32(reg, src1); | |
e6e5906b | 1365 | s->cc_op = CC_OP_SUB; |
e1f3808e PB |
1366 | gen_update_cc_add(reg, src1); |
1367 | gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1); | |
e6e5906b PB |
1368 | s->cc_op = CC_OP_SUB; |
1369 | } | |
1370 | ||
0633879f PB |
1371 | static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) |
1372 | { | |
e1f3808e PB |
1373 | tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf); |
1374 | tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4); | |
0633879f | 1375 | if (!ccr_only) { |
e1f3808e | 1376 | gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00)); |
0633879f PB |
1377 | } |
1378 | } | |
1379 | ||
d4d79bb1 BS |
1380 | static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, |
1381 | int ccr_only) | |
e6e5906b | 1382 | { |
e1f3808e PB |
1383 | TCGv tmp; |
1384 | TCGv reg; | |
e6e5906b PB |
1385 | |
1386 | s->cc_op = CC_OP_FLAGS; | |
1387 | if ((insn & 0x38) == 0) | |
1388 | { | |
a7812ae4 | 1389 | tmp = tcg_temp_new(); |
e6e5906b | 1390 | reg = DREG(insn, 0); |
e1f3808e PB |
1391 | tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf); |
1392 | tcg_gen_shri_i32(tmp, reg, 4); | |
1393 | tcg_gen_andi_i32(QREG_CC_X, tmp, 1); | |
0633879f | 1394 | if (!ccr_only) { |
e1f3808e | 1395 | gen_helper_set_sr(cpu_env, reg); |
0633879f | 1396 | } |
e6e5906b | 1397 | } |
0633879f | 1398 | else if ((insn & 0x3f) == 0x3c) |
e6e5906b | 1399 | { |
0633879f | 1400 | uint16_t val; |
d4d79bb1 | 1401 | val = cpu_lduw_code(env, s->pc); |
e6e5906b | 1402 | s->pc += 2; |
0633879f | 1403 | gen_set_sr_im(s, val, ccr_only); |
e6e5906b PB |
1404 | } |
1405 | else | |
d4d79bb1 | 1406 | disas_undef(env, s, insn); |
e6e5906b PB |
1407 | } |
1408 | ||
0633879f PB |
1409 | DISAS_INSN(move_to_ccr) |
1410 | { | |
d4d79bb1 | 1411 | gen_set_sr(env, s, insn, 1); |
0633879f PB |
1412 | } |
1413 | ||
e6e5906b PB |
1414 | DISAS_INSN(not) |
1415 | { | |
e1f3808e | 1416 | TCGv reg; |
e6e5906b PB |
1417 | |
1418 | reg = DREG(insn, 0); | |
e1f3808e | 1419 | tcg_gen_not_i32(reg, reg); |
e6e5906b PB |
1420 | gen_logic_cc(s, reg); |
1421 | } | |
1422 | ||
1423 | DISAS_INSN(swap) | |
1424 | { | |
e1f3808e PB |
1425 | TCGv src1; |
1426 | TCGv src2; | |
1427 | TCGv reg; | |
e6e5906b | 1428 | |
a7812ae4 PB |
1429 | src1 = tcg_temp_new(); |
1430 | src2 = tcg_temp_new(); | |
e6e5906b | 1431 | reg = DREG(insn, 0); |
e1f3808e PB |
1432 | tcg_gen_shli_i32(src1, reg, 16); |
1433 | tcg_gen_shri_i32(src2, reg, 16); | |
1434 | tcg_gen_or_i32(reg, src1, src2); | |
1435 | gen_logic_cc(s, reg); | |
e6e5906b PB |
1436 | } |
1437 | ||
1438 | DISAS_INSN(pea) | |
1439 | { | |
e1f3808e | 1440 | TCGv tmp; |
e6e5906b | 1441 | |
d4d79bb1 | 1442 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1443 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1444 | gen_addr_fault(s); |
1445 | return; | |
1446 | } | |
0633879f | 1447 | gen_push(s, tmp); |
e6e5906b PB |
1448 | } |
1449 | ||
1450 | DISAS_INSN(ext) | |
1451 | { | |
e6e5906b | 1452 | int op; |
e1f3808e PB |
1453 | TCGv reg; |
1454 | TCGv tmp; | |
e6e5906b PB |
1455 | |
1456 | reg = DREG(insn, 0); | |
1457 | op = (insn >> 6) & 7; | |
a7812ae4 | 1458 | tmp = tcg_temp_new(); |
e6e5906b | 1459 | if (op == 3) |
e1f3808e | 1460 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1461 | else |
e1f3808e | 1462 | tcg_gen_ext8s_i32(tmp, reg); |
e6e5906b PB |
1463 | if (op == 2) |
1464 | gen_partset_reg(OS_WORD, reg, tmp); | |
1465 | else | |
e1f3808e | 1466 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1467 | gen_logic_cc(s, tmp); |
1468 | } | |
1469 | ||
1470 | DISAS_INSN(tst) | |
1471 | { | |
1472 | int opsize; | |
e1f3808e | 1473 | TCGv tmp; |
e6e5906b PB |
1474 | |
1475 | switch ((insn >> 6) & 3) { | |
1476 | case 0: /* tst.b */ | |
1477 | opsize = OS_BYTE; | |
1478 | break; | |
1479 | case 1: /* tst.w */ | |
1480 | opsize = OS_WORD; | |
1481 | break; | |
1482 | case 2: /* tst.l */ | |
1483 | opsize = OS_LONG; | |
1484 | break; | |
1485 | default: | |
1486 | abort(); | |
1487 | } | |
d4d79bb1 | 1488 | SRC_EA(env, tmp, opsize, 1, NULL); |
e6e5906b PB |
1489 | gen_logic_cc(s, tmp); |
1490 | } | |
1491 | ||
1492 | DISAS_INSN(pulse) | |
1493 | { | |
1494 | /* Implemented as a NOP. */ | |
1495 | } | |
1496 | ||
1497 | DISAS_INSN(illegal) | |
1498 | { | |
1499 | gen_exception(s, s->pc - 2, EXCP_ILLEGAL); | |
1500 | } | |
1501 | ||
1502 | /* ??? This should be atomic. */ | |
1503 | DISAS_INSN(tas) | |
1504 | { | |
e1f3808e PB |
1505 | TCGv dest; |
1506 | TCGv src1; | |
1507 | TCGv addr; | |
e6e5906b | 1508 | |
a7812ae4 | 1509 | dest = tcg_temp_new(); |
d4d79bb1 | 1510 | SRC_EA(env, src1, OS_BYTE, 1, &addr); |
e6e5906b | 1511 | gen_logic_cc(s, src1); |
e1f3808e | 1512 | tcg_gen_ori_i32(dest, src1, 0x80); |
d4d79bb1 | 1513 | DEST_EA(env, insn, OS_BYTE, dest, &addr); |
e6e5906b PB |
1514 | } |
1515 | ||
1516 | DISAS_INSN(mull) | |
1517 | { | |
1518 | uint16_t ext; | |
e1f3808e PB |
1519 | TCGv reg; |
1520 | TCGv src1; | |
1521 | TCGv dest; | |
e6e5906b PB |
1522 | |
1523 | /* The upper 32 bits of the product are discarded, so | |
1524 | muls.l and mulu.l are functionally equivalent. */ | |
d4d79bb1 | 1525 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
1526 | s->pc += 2; |
1527 | if (ext & 0x87ff) { | |
1528 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
1529 | return; | |
1530 | } | |
1531 | reg = DREG(ext, 12); | |
d4d79bb1 | 1532 | SRC_EA(env, src1, OS_LONG, 0, NULL); |
a7812ae4 | 1533 | dest = tcg_temp_new(); |
e1f3808e PB |
1534 | tcg_gen_mul_i32(dest, src1, reg); |
1535 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1536 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
1537 | gen_logic_cc(s, dest); | |
1538 | } | |
1539 | ||
1540 | DISAS_INSN(link) | |
1541 | { | |
1542 | int16_t offset; | |
e1f3808e PB |
1543 | TCGv reg; |
1544 | TCGv tmp; | |
e6e5906b | 1545 | |
d4d79bb1 | 1546 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1547 | s->pc += 2; |
1548 | reg = AREG(insn, 0); | |
a7812ae4 | 1549 | tmp = tcg_temp_new(); |
e1f3808e | 1550 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1551 | gen_store(s, OS_LONG, tmp, reg); |
e1f3808e PB |
1552 | if ((insn & 7) != 7) |
1553 | tcg_gen_mov_i32(reg, tmp); | |
1554 | tcg_gen_addi_i32(QREG_SP, tmp, offset); | |
e6e5906b PB |
1555 | } |
1556 | ||
1557 | DISAS_INSN(unlk) | |
1558 | { | |
e1f3808e PB |
1559 | TCGv src; |
1560 | TCGv reg; | |
1561 | TCGv tmp; | |
e6e5906b | 1562 | |
a7812ae4 | 1563 | src = tcg_temp_new(); |
e6e5906b | 1564 | reg = AREG(insn, 0); |
e1f3808e | 1565 | tcg_gen_mov_i32(src, reg); |
0633879f | 1566 | tmp = gen_load(s, OS_LONG, src, 0); |
e1f3808e PB |
1567 | tcg_gen_mov_i32(reg, tmp); |
1568 | tcg_gen_addi_i32(QREG_SP, src, 4); | |
e6e5906b PB |
1569 | } |
1570 | ||
1571 | DISAS_INSN(nop) | |
1572 | { | |
1573 | } | |
1574 | ||
1575 | DISAS_INSN(rts) | |
1576 | { | |
e1f3808e | 1577 | TCGv tmp; |
e6e5906b | 1578 | |
0633879f | 1579 | tmp = gen_load(s, OS_LONG, QREG_SP, 0); |
e1f3808e | 1580 | tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); |
e6e5906b PB |
1581 | gen_jmp(s, tmp); |
1582 | } | |
1583 | ||
1584 | DISAS_INSN(jump) | |
1585 | { | |
e1f3808e | 1586 | TCGv tmp; |
e6e5906b PB |
1587 | |
1588 | /* Load the target address first to ensure correct exception | |
1589 | behavior. */ | |
d4d79bb1 | 1590 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1591 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1592 | gen_addr_fault(s); |
1593 | return; | |
1594 | } | |
e6e5906b PB |
1595 | if ((insn & 0x40) == 0) { |
1596 | /* jsr */ | |
351326a6 | 1597 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1598 | } |
1599 | gen_jmp(s, tmp); | |
1600 | } | |
1601 | ||
1602 | DISAS_INSN(addsubq) | |
1603 | { | |
e1f3808e PB |
1604 | TCGv src1; |
1605 | TCGv src2; | |
1606 | TCGv dest; | |
e6e5906b | 1607 | int val; |
e1f3808e | 1608 | TCGv addr; |
e6e5906b | 1609 | |
d4d79bb1 | 1610 | SRC_EA(env, src1, OS_LONG, 0, &addr); |
e6e5906b PB |
1611 | val = (insn >> 9) & 7; |
1612 | if (val == 0) | |
1613 | val = 8; | |
a7812ae4 | 1614 | dest = tcg_temp_new(); |
e1f3808e | 1615 | tcg_gen_mov_i32(dest, src1); |
e6e5906b PB |
1616 | if ((insn & 0x38) == 0x08) { |
1617 | /* Don't update condition codes if the destination is an | |
1618 | address register. */ | |
1619 | if (insn & 0x0100) { | |
e1f3808e | 1620 | tcg_gen_subi_i32(dest, dest, val); |
e6e5906b | 1621 | } else { |
e1f3808e | 1622 | tcg_gen_addi_i32(dest, dest, val); |
e6e5906b PB |
1623 | } |
1624 | } else { | |
351326a6 | 1625 | src2 = tcg_const_i32(val); |
e6e5906b | 1626 | if (insn & 0x0100) { |
e1f3808e PB |
1627 | gen_helper_xflag_lt(QREG_CC_X, dest, src2); |
1628 | tcg_gen_subi_i32(dest, dest, val); | |
e6e5906b PB |
1629 | s->cc_op = CC_OP_SUB; |
1630 | } else { | |
e1f3808e PB |
1631 | tcg_gen_addi_i32(dest, dest, val); |
1632 | gen_helper_xflag_lt(QREG_CC_X, dest, src2); | |
e6e5906b PB |
1633 | s->cc_op = CC_OP_ADD; |
1634 | } | |
e1f3808e | 1635 | gen_update_cc_add(dest, src2); |
e6e5906b | 1636 | } |
d4d79bb1 | 1637 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1638 | } |
1639 | ||
1640 | DISAS_INSN(tpf) | |
1641 | { | |
1642 | switch (insn & 7) { | |
1643 | case 2: /* One extension word. */ | |
1644 | s->pc += 2; | |
1645 | break; | |
1646 | case 3: /* Two extension words. */ | |
1647 | s->pc += 4; | |
1648 | break; | |
1649 | case 4: /* No extension words. */ | |
1650 | break; | |
1651 | default: | |
d4d79bb1 | 1652 | disas_undef(env, s, insn); |
e6e5906b PB |
1653 | } |
1654 | } | |
1655 | ||
1656 | DISAS_INSN(branch) | |
1657 | { | |
1658 | int32_t offset; | |
1659 | uint32_t base; | |
1660 | int op; | |
42a268c2 | 1661 | TCGLabel *l1; |
3b46e624 | 1662 | |
e6e5906b PB |
1663 | base = s->pc; |
1664 | op = (insn >> 8) & 0xf; | |
1665 | offset = (int8_t)insn; | |
1666 | if (offset == 0) { | |
d4d79bb1 | 1667 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1668 | s->pc += 2; |
1669 | } else if (offset == -1) { | |
d4d79bb1 | 1670 | offset = read_im32(env, s); |
e6e5906b PB |
1671 | } |
1672 | if (op == 1) { | |
1673 | /* bsr */ | |
351326a6 | 1674 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1675 | } |
1676 | gen_flush_cc_op(s); | |
1677 | if (op > 1) { | |
1678 | /* Bcc */ | |
1679 | l1 = gen_new_label(); | |
1680 | gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); | |
1681 | gen_jmp_tb(s, 1, base + offset); | |
1682 | gen_set_label(l1); | |
1683 | gen_jmp_tb(s, 0, s->pc); | |
1684 | } else { | |
1685 | /* Unconditional branch. */ | |
1686 | gen_jmp_tb(s, 0, base + offset); | |
1687 | } | |
1688 | } | |
1689 | ||
1690 | DISAS_INSN(moveq) | |
1691 | { | |
e1f3808e | 1692 | uint32_t val; |
e6e5906b | 1693 | |
e1f3808e PB |
1694 | val = (int8_t)insn; |
1695 | tcg_gen_movi_i32(DREG(insn, 9), val); | |
1696 | gen_logic_cc(s, tcg_const_i32(val)); | |
e6e5906b PB |
1697 | } |
1698 | ||
1699 | DISAS_INSN(mvzs) | |
1700 | { | |
1701 | int opsize; | |
e1f3808e PB |
1702 | TCGv src; |
1703 | TCGv reg; | |
e6e5906b PB |
1704 | |
1705 | if (insn & 0x40) | |
1706 | opsize = OS_WORD; | |
1707 | else | |
1708 | opsize = OS_BYTE; | |
d4d79bb1 | 1709 | SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); |
e6e5906b | 1710 | reg = DREG(insn, 9); |
e1f3808e | 1711 | tcg_gen_mov_i32(reg, src); |
e6e5906b PB |
1712 | gen_logic_cc(s, src); |
1713 | } | |
1714 | ||
1715 | DISAS_INSN(or) | |
1716 | { | |
e1f3808e PB |
1717 | TCGv reg; |
1718 | TCGv dest; | |
1719 | TCGv src; | |
1720 | TCGv addr; | |
e6e5906b PB |
1721 | |
1722 | reg = DREG(insn, 9); | |
a7812ae4 | 1723 | dest = tcg_temp_new(); |
e6e5906b | 1724 | if (insn & 0x100) { |
d4d79bb1 | 1725 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1726 | tcg_gen_or_i32(dest, src, reg); |
d4d79bb1 | 1727 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1728 | } else { |
d4d79bb1 | 1729 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1730 | tcg_gen_or_i32(dest, src, reg); |
1731 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1732 | } |
1733 | gen_logic_cc(s, dest); | |
1734 | } | |
1735 | ||
1736 | DISAS_INSN(suba) | |
1737 | { | |
e1f3808e PB |
1738 | TCGv src; |
1739 | TCGv reg; | |
e6e5906b | 1740 | |
d4d79bb1 | 1741 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1742 | reg = AREG(insn, 9); |
e1f3808e | 1743 | tcg_gen_sub_i32(reg, reg, src); |
e6e5906b PB |
1744 | } |
1745 | ||
1746 | DISAS_INSN(subx) | |
1747 | { | |
e1f3808e PB |
1748 | TCGv reg; |
1749 | TCGv src; | |
e6e5906b PB |
1750 | |
1751 | gen_flush_flags(s); | |
1752 | reg = DREG(insn, 9); | |
1753 | src = DREG(insn, 0); | |
e1f3808e | 1754 | gen_helper_subx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1755 | } |
1756 | ||
1757 | DISAS_INSN(mov3q) | |
1758 | { | |
e1f3808e | 1759 | TCGv src; |
e6e5906b PB |
1760 | int val; |
1761 | ||
1762 | val = (insn >> 9) & 7; | |
1763 | if (val == 0) | |
1764 | val = -1; | |
351326a6 | 1765 | src = tcg_const_i32(val); |
e6e5906b | 1766 | gen_logic_cc(s, src); |
d4d79bb1 | 1767 | DEST_EA(env, insn, OS_LONG, src, NULL); |
e6e5906b PB |
1768 | } |
1769 | ||
1770 | DISAS_INSN(cmp) | |
1771 | { | |
1772 | int op; | |
e1f3808e PB |
1773 | TCGv src; |
1774 | TCGv reg; | |
1775 | TCGv dest; | |
e6e5906b PB |
1776 | int opsize; |
1777 | ||
1778 | op = (insn >> 6) & 3; | |
1779 | switch (op) { | |
1780 | case 0: /* cmp.b */ | |
1781 | opsize = OS_BYTE; | |
1782 | s->cc_op = CC_OP_CMPB; | |
1783 | break; | |
1784 | case 1: /* cmp.w */ | |
1785 | opsize = OS_WORD; | |
1786 | s->cc_op = CC_OP_CMPW; | |
1787 | break; | |
1788 | case 2: /* cmp.l */ | |
1789 | opsize = OS_LONG; | |
1790 | s->cc_op = CC_OP_SUB; | |
1791 | break; | |
1792 | default: | |
1793 | abort(); | |
1794 | } | |
d4d79bb1 | 1795 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1796 | reg = DREG(insn, 9); |
a7812ae4 | 1797 | dest = tcg_temp_new(); |
e1f3808e PB |
1798 | tcg_gen_sub_i32(dest, reg, src); |
1799 | gen_update_cc_add(dest, src); | |
e6e5906b PB |
1800 | } |
1801 | ||
1802 | DISAS_INSN(cmpa) | |
1803 | { | |
1804 | int opsize; | |
e1f3808e PB |
1805 | TCGv src; |
1806 | TCGv reg; | |
1807 | TCGv dest; | |
e6e5906b PB |
1808 | |
1809 | if (insn & 0x100) { | |
1810 | opsize = OS_LONG; | |
1811 | } else { | |
1812 | opsize = OS_WORD; | |
1813 | } | |
d4d79bb1 | 1814 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1815 | reg = AREG(insn, 9); |
a7812ae4 | 1816 | dest = tcg_temp_new(); |
e1f3808e PB |
1817 | tcg_gen_sub_i32(dest, reg, src); |
1818 | gen_update_cc_add(dest, src); | |
e6e5906b PB |
1819 | s->cc_op = CC_OP_SUB; |
1820 | } | |
1821 | ||
1822 | DISAS_INSN(eor) | |
1823 | { | |
e1f3808e PB |
1824 | TCGv src; |
1825 | TCGv reg; | |
1826 | TCGv dest; | |
1827 | TCGv addr; | |
e6e5906b | 1828 | |
d4d79bb1 | 1829 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e6e5906b | 1830 | reg = DREG(insn, 9); |
a7812ae4 | 1831 | dest = tcg_temp_new(); |
e1f3808e | 1832 | tcg_gen_xor_i32(dest, src, reg); |
e6e5906b | 1833 | gen_logic_cc(s, dest); |
d4d79bb1 | 1834 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1835 | } |
1836 | ||
1837 | DISAS_INSN(and) | |
1838 | { | |
e1f3808e PB |
1839 | TCGv src; |
1840 | TCGv reg; | |
1841 | TCGv dest; | |
1842 | TCGv addr; | |
e6e5906b PB |
1843 | |
1844 | reg = DREG(insn, 9); | |
a7812ae4 | 1845 | dest = tcg_temp_new(); |
e6e5906b | 1846 | if (insn & 0x100) { |
d4d79bb1 | 1847 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1848 | tcg_gen_and_i32(dest, src, reg); |
d4d79bb1 | 1849 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1850 | } else { |
d4d79bb1 | 1851 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1852 | tcg_gen_and_i32(dest, src, reg); |
1853 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1854 | } |
1855 | gen_logic_cc(s, dest); | |
1856 | } | |
1857 | ||
1858 | DISAS_INSN(adda) | |
1859 | { | |
e1f3808e PB |
1860 | TCGv src; |
1861 | TCGv reg; | |
e6e5906b | 1862 | |
d4d79bb1 | 1863 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1864 | reg = AREG(insn, 9); |
e1f3808e | 1865 | tcg_gen_add_i32(reg, reg, src); |
e6e5906b PB |
1866 | } |
1867 | ||
1868 | DISAS_INSN(addx) | |
1869 | { | |
e1f3808e PB |
1870 | TCGv reg; |
1871 | TCGv src; | |
e6e5906b PB |
1872 | |
1873 | gen_flush_flags(s); | |
1874 | reg = DREG(insn, 9); | |
1875 | src = DREG(insn, 0); | |
e1f3808e | 1876 | gen_helper_addx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1877 | s->cc_op = CC_OP_FLAGS; |
1878 | } | |
1879 | ||
e1f3808e | 1880 | /* TODO: This could be implemented without helper functions. */ |
e6e5906b PB |
1881 | DISAS_INSN(shift_im) |
1882 | { | |
e1f3808e | 1883 | TCGv reg; |
e6e5906b | 1884 | int tmp; |
e1f3808e | 1885 | TCGv shift; |
e6e5906b PB |
1886 | |
1887 | reg = DREG(insn, 0); | |
1888 | tmp = (insn >> 9) & 7; | |
1889 | if (tmp == 0) | |
e1f3808e | 1890 | tmp = 8; |
351326a6 | 1891 | shift = tcg_const_i32(tmp); |
e1f3808e | 1892 | /* No need to flush flags becuse we know we will set C flag. */ |
e6e5906b | 1893 | if (insn & 0x100) { |
e1f3808e | 1894 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1895 | } else { |
1896 | if (insn & 8) { | |
e1f3808e | 1897 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1898 | } else { |
e1f3808e | 1899 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1900 | } |
1901 | } | |
e1f3808e | 1902 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1903 | } |
1904 | ||
1905 | DISAS_INSN(shift_reg) | |
1906 | { | |
e1f3808e PB |
1907 | TCGv reg; |
1908 | TCGv shift; | |
e6e5906b PB |
1909 | |
1910 | reg = DREG(insn, 0); | |
e1f3808e PB |
1911 | shift = DREG(insn, 9); |
1912 | /* Shift by zero leaves C flag unmodified. */ | |
1913 | gen_flush_flags(s); | |
e6e5906b | 1914 | if (insn & 0x100) { |
e1f3808e | 1915 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1916 | } else { |
1917 | if (insn & 8) { | |
e1f3808e | 1918 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1919 | } else { |
e1f3808e | 1920 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1921 | } |
1922 | } | |
e1f3808e | 1923 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1924 | } |
1925 | ||
1926 | DISAS_INSN(ff1) | |
1927 | { | |
e1f3808e | 1928 | TCGv reg; |
821f7e76 PB |
1929 | reg = DREG(insn, 0); |
1930 | gen_logic_cc(s, reg); | |
e1f3808e | 1931 | gen_helper_ff1(reg, reg); |
e6e5906b PB |
1932 | } |
1933 | ||
e1f3808e | 1934 | static TCGv gen_get_sr(DisasContext *s) |
0633879f | 1935 | { |
e1f3808e PB |
1936 | TCGv ccr; |
1937 | TCGv sr; | |
0633879f PB |
1938 | |
1939 | ccr = gen_get_ccr(s); | |
a7812ae4 | 1940 | sr = tcg_temp_new(); |
e1f3808e PB |
1941 | tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); |
1942 | tcg_gen_or_i32(sr, sr, ccr); | |
0633879f PB |
1943 | return sr; |
1944 | } | |
1945 | ||
e6e5906b PB |
1946 | DISAS_INSN(strldsr) |
1947 | { | |
1948 | uint16_t ext; | |
1949 | uint32_t addr; | |
1950 | ||
1951 | addr = s->pc - 2; | |
d4d79bb1 | 1952 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 1953 | s->pc += 2; |
0633879f | 1954 | if (ext != 0x46FC) { |
e6e5906b | 1955 | gen_exception(s, addr, EXCP_UNSUPPORTED); |
0633879f PB |
1956 | return; |
1957 | } | |
d4d79bb1 | 1958 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
1959 | s->pc += 2; |
1960 | if (IS_USER(s) || (ext & SR_S) == 0) { | |
e6e5906b | 1961 | gen_exception(s, addr, EXCP_PRIVILEGE); |
0633879f PB |
1962 | return; |
1963 | } | |
1964 | gen_push(s, gen_get_sr(s)); | |
1965 | gen_set_sr_im(s, ext, 0); | |
e6e5906b PB |
1966 | } |
1967 | ||
1968 | DISAS_INSN(move_from_sr) | |
1969 | { | |
e1f3808e PB |
1970 | TCGv reg; |
1971 | TCGv sr; | |
0633879f PB |
1972 | |
1973 | if (IS_USER(s)) { | |
1974 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1975 | return; | |
1976 | } | |
1977 | sr = gen_get_sr(s); | |
1978 | reg = DREG(insn, 0); | |
1979 | gen_partset_reg(OS_WORD, reg, sr); | |
e6e5906b PB |
1980 | } |
1981 | ||
1982 | DISAS_INSN(move_to_sr) | |
1983 | { | |
0633879f PB |
1984 | if (IS_USER(s)) { |
1985 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1986 | return; | |
1987 | } | |
d4d79bb1 | 1988 | gen_set_sr(env, s, insn, 0); |
0633879f | 1989 | gen_lookup_tb(s); |
e6e5906b PB |
1990 | } |
1991 | ||
1992 | DISAS_INSN(move_from_usp) | |
1993 | { | |
0633879f PB |
1994 | if (IS_USER(s)) { |
1995 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1996 | return; | |
1997 | } | |
2a8327e8 GU |
1998 | tcg_gen_ld_i32(AREG(insn, 0), cpu_env, |
1999 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2000 | } |
2001 | ||
2002 | DISAS_INSN(move_to_usp) | |
2003 | { | |
0633879f PB |
2004 | if (IS_USER(s)) { |
2005 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2006 | return; | |
2007 | } | |
2a8327e8 GU |
2008 | tcg_gen_st_i32(AREG(insn, 0), cpu_env, |
2009 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2010 | } |
2011 | ||
2012 | DISAS_INSN(halt) | |
2013 | { | |
e1f3808e | 2014 | gen_exception(s, s->pc, EXCP_HALT_INSN); |
e6e5906b PB |
2015 | } |
2016 | ||
2017 | DISAS_INSN(stop) | |
2018 | { | |
0633879f PB |
2019 | uint16_t ext; |
2020 | ||
2021 | if (IS_USER(s)) { | |
2022 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2023 | return; | |
2024 | } | |
2025 | ||
d4d79bb1 | 2026 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
2027 | s->pc += 2; |
2028 | ||
2029 | gen_set_sr_im(s, ext, 0); | |
259186a7 | 2030 | tcg_gen_movi_i32(cpu_halted, 1); |
e1f3808e | 2031 | gen_exception(s, s->pc, EXCP_HLT); |
e6e5906b PB |
2032 | } |
2033 | ||
2034 | DISAS_INSN(rte) | |
2035 | { | |
0633879f PB |
2036 | if (IS_USER(s)) { |
2037 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2038 | return; | |
2039 | } | |
2040 | gen_exception(s, s->pc - 2, EXCP_RTE); | |
e6e5906b PB |
2041 | } |
2042 | ||
2043 | DISAS_INSN(movec) | |
2044 | { | |
0633879f | 2045 | uint16_t ext; |
e1f3808e | 2046 | TCGv reg; |
0633879f PB |
2047 | |
2048 | if (IS_USER(s)) { | |
2049 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2050 | return; | |
2051 | } | |
2052 | ||
d4d79bb1 | 2053 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
2054 | s->pc += 2; |
2055 | ||
2056 | if (ext & 0x8000) { | |
2057 | reg = AREG(ext, 12); | |
2058 | } else { | |
2059 | reg = DREG(ext, 12); | |
2060 | } | |
e1f3808e | 2061 | gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); |
0633879f | 2062 | gen_lookup_tb(s); |
e6e5906b PB |
2063 | } |
2064 | ||
2065 | DISAS_INSN(intouch) | |
2066 | { | |
0633879f PB |
2067 | if (IS_USER(s)) { |
2068 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2069 | return; | |
2070 | } | |
2071 | /* ICache fetch. Implement as no-op. */ | |
e6e5906b PB |
2072 | } |
2073 | ||
2074 | DISAS_INSN(cpushl) | |
2075 | { | |
0633879f PB |
2076 | if (IS_USER(s)) { |
2077 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2078 | return; | |
2079 | } | |
2080 | /* Cache push/invalidate. Implement as no-op. */ | |
e6e5906b PB |
2081 | } |
2082 | ||
2083 | DISAS_INSN(wddata) | |
2084 | { | |
2085 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2086 | } | |
2087 | ||
2088 | DISAS_INSN(wdebug) | |
2089 | { | |
a47dddd7 AF |
2090 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2091 | ||
0633879f PB |
2092 | if (IS_USER(s)) { |
2093 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2094 | return; | |
2095 | } | |
2096 | /* TODO: Implement wdebug. */ | |
a47dddd7 | 2097 | cpu_abort(CPU(cpu), "WDEBUG not implemented"); |
e6e5906b PB |
2098 | } |
2099 | ||
2100 | DISAS_INSN(trap) | |
2101 | { | |
2102 | gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); | |
2103 | } | |
2104 | ||
2105 | /* ??? FP exceptions are not implemented. Most exceptions are deferred until | |
2106 | immediately before the next FP instruction is executed. */ | |
2107 | DISAS_INSN(fpu) | |
2108 | { | |
2109 | uint16_t ext; | |
a7812ae4 | 2110 | int32_t offset; |
e6e5906b | 2111 | int opmode; |
a7812ae4 PB |
2112 | TCGv_i64 src; |
2113 | TCGv_i64 dest; | |
2114 | TCGv_i64 res; | |
2115 | TCGv tmp32; | |
e6e5906b | 2116 | int round; |
a7812ae4 | 2117 | int set_dest; |
e6e5906b PB |
2118 | int opsize; |
2119 | ||
d4d79bb1 | 2120 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2121 | s->pc += 2; |
2122 | opmode = ext & 0x7f; | |
2123 | switch ((ext >> 13) & 7) { | |
2124 | case 0: case 2: | |
2125 | break; | |
2126 | case 1: | |
2127 | goto undef; | |
2128 | case 3: /* fmove out */ | |
2129 | src = FREG(ext, 7); | |
a7812ae4 | 2130 | tmp32 = tcg_temp_new_i32(); |
e6e5906b PB |
2131 | /* fmove */ |
2132 | /* ??? TODO: Proper behavior on overflow. */ | |
2133 | switch ((ext >> 10) & 7) { | |
2134 | case 0: | |
2135 | opsize = OS_LONG; | |
a7812ae4 | 2136 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2137 | break; |
2138 | case 1: | |
2139 | opsize = OS_SINGLE; | |
a7812ae4 | 2140 | gen_helper_f64_to_f32(tmp32, cpu_env, src); |
e6e5906b PB |
2141 | break; |
2142 | case 4: | |
2143 | opsize = OS_WORD; | |
a7812ae4 | 2144 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b | 2145 | break; |
a7812ae4 PB |
2146 | case 5: /* OS_DOUBLE */ |
2147 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2148 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2149 | case 2: |
2150 | case 3: | |
243ee8f7 | 2151 | break; |
a7812ae4 PB |
2152 | case 4: |
2153 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2154 | break; | |
2155 | case 5: | |
d4d79bb1 | 2156 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2157 | s->pc += 2; |
2158 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2159 | break; | |
2160 | default: | |
2161 | goto undef; | |
2162 | } | |
2163 | gen_store64(s, tmp32, src); | |
c59b97aa | 2164 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2165 | case 3: |
2166 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2167 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2168 | break; | |
2169 | case 4: | |
2170 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2171 | break; | |
2172 | } | |
2173 | tcg_temp_free_i32(tmp32); | |
2174 | return; | |
e6e5906b PB |
2175 | case 6: |
2176 | opsize = OS_BYTE; | |
a7812ae4 | 2177 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2178 | break; |
2179 | default: | |
2180 | goto undef; | |
2181 | } | |
d4d79bb1 | 2182 | DEST_EA(env, insn, opsize, tmp32, NULL); |
a7812ae4 | 2183 | tcg_temp_free_i32(tmp32); |
e6e5906b PB |
2184 | return; |
2185 | case 4: /* fmove to control register. */ | |
2186 | switch ((ext >> 10) & 7) { | |
2187 | case 4: /* FPCR */ | |
2188 | /* Not implemented. Ignore writes. */ | |
2189 | break; | |
2190 | case 1: /* FPIAR */ | |
2191 | case 2: /* FPSR */ | |
2192 | default: | |
2193 | cpu_abort(NULL, "Unimplemented: fmove to control %d", | |
2194 | (ext >> 10) & 7); | |
2195 | } | |
2196 | break; | |
2197 | case 5: /* fmove from control register. */ | |
2198 | switch ((ext >> 10) & 7) { | |
2199 | case 4: /* FPCR */ | |
2200 | /* Not implemented. Always return zero. */ | |
351326a6 | 2201 | tmp32 = tcg_const_i32(0); |
e6e5906b PB |
2202 | break; |
2203 | case 1: /* FPIAR */ | |
2204 | case 2: /* FPSR */ | |
2205 | default: | |
2206 | cpu_abort(NULL, "Unimplemented: fmove from control %d", | |
2207 | (ext >> 10) & 7); | |
2208 | goto undef; | |
2209 | } | |
d4d79bb1 | 2210 | DEST_EA(env, insn, OS_LONG, tmp32, NULL); |
e6e5906b | 2211 | break; |
5fafdf24 | 2212 | case 6: /* fmovem */ |
e6e5906b PB |
2213 | case 7: |
2214 | { | |
e1f3808e PB |
2215 | TCGv addr; |
2216 | uint16_t mask; | |
2217 | int i; | |
2218 | if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) | |
2219 | goto undef; | |
d4d79bb1 | 2220 | tmp32 = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2221 | if (IS_NULL_QREG(tmp32)) { |
e1f3808e PB |
2222 | gen_addr_fault(s); |
2223 | return; | |
2224 | } | |
a7812ae4 PB |
2225 | addr = tcg_temp_new_i32(); |
2226 | tcg_gen_mov_i32(addr, tmp32); | |
e1f3808e PB |
2227 | mask = 0x80; |
2228 | for (i = 0; i < 8; i++) { | |
2229 | if (ext & mask) { | |
e1f3808e PB |
2230 | dest = FREG(i, 0); |
2231 | if (ext & (1 << 13)) { | |
2232 | /* store */ | |
2233 | tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); | |
2234 | } else { | |
2235 | /* load */ | |
2236 | tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); | |
2237 | } | |
2238 | if (ext & (mask - 1)) | |
2239 | tcg_gen_addi_i32(addr, addr, 8); | |
e6e5906b | 2240 | } |
e1f3808e | 2241 | mask >>= 1; |
e6e5906b | 2242 | } |
18307f26 | 2243 | tcg_temp_free_i32(addr); |
e6e5906b PB |
2244 | } |
2245 | return; | |
2246 | } | |
2247 | if (ext & (1 << 14)) { | |
e6e5906b PB |
2248 | /* Source effective address. */ |
2249 | switch ((ext >> 10) & 7) { | |
2250 | case 0: opsize = OS_LONG; break; | |
2251 | case 1: opsize = OS_SINGLE; break; | |
2252 | case 4: opsize = OS_WORD; break; | |
2253 | case 5: opsize = OS_DOUBLE; break; | |
2254 | case 6: opsize = OS_BYTE; break; | |
2255 | default: | |
2256 | goto undef; | |
2257 | } | |
e6e5906b | 2258 | if (opsize == OS_DOUBLE) { |
a7812ae4 PB |
2259 | tmp32 = tcg_temp_new_i32(); |
2260 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2261 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2262 | case 2: |
2263 | case 3: | |
243ee8f7 | 2264 | break; |
a7812ae4 PB |
2265 | case 4: |
2266 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2267 | break; | |
2268 | case 5: | |
d4d79bb1 | 2269 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2270 | s->pc += 2; |
2271 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2272 | break; | |
2273 | case 7: | |
d4d79bb1 | 2274 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2275 | offset += s->pc - 2; |
2276 | s->pc += 2; | |
2277 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2278 | break; | |
2279 | default: | |
2280 | goto undef; | |
2281 | } | |
2282 | src = gen_load64(s, tmp32); | |
c59b97aa | 2283 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2284 | case 3: |
2285 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2286 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2287 | break; | |
2288 | case 4: | |
2289 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2290 | break; | |
2291 | } | |
2292 | tcg_temp_free_i32(tmp32); | |
e6e5906b | 2293 | } else { |
d4d79bb1 | 2294 | SRC_EA(env, tmp32, opsize, 1, NULL); |
a7812ae4 | 2295 | src = tcg_temp_new_i64(); |
e6e5906b PB |
2296 | switch (opsize) { |
2297 | case OS_LONG: | |
2298 | case OS_WORD: | |
2299 | case OS_BYTE: | |
a7812ae4 | 2300 | gen_helper_i32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2301 | break; |
2302 | case OS_SINGLE: | |
a7812ae4 | 2303 | gen_helper_f32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2304 | break; |
2305 | } | |
2306 | } | |
2307 | } else { | |
2308 | /* Source register. */ | |
2309 | src = FREG(ext, 10); | |
2310 | } | |
2311 | dest = FREG(ext, 7); | |
a7812ae4 | 2312 | res = tcg_temp_new_i64(); |
e6e5906b | 2313 | if (opmode != 0x3a) |
e1f3808e | 2314 | tcg_gen_mov_f64(res, dest); |
e6e5906b | 2315 | round = 1; |
a7812ae4 | 2316 | set_dest = 1; |
e6e5906b PB |
2317 | switch (opmode) { |
2318 | case 0: case 0x40: case 0x44: /* fmove */ | |
e1f3808e | 2319 | tcg_gen_mov_f64(res, src); |
e6e5906b PB |
2320 | break; |
2321 | case 1: /* fint */ | |
e1f3808e | 2322 | gen_helper_iround_f64(res, cpu_env, src); |
e6e5906b PB |
2323 | round = 0; |
2324 | break; | |
2325 | case 3: /* fintrz */ | |
e1f3808e | 2326 | gen_helper_itrunc_f64(res, cpu_env, src); |
e6e5906b PB |
2327 | round = 0; |
2328 | break; | |
2329 | case 4: case 0x41: case 0x45: /* fsqrt */ | |
e1f3808e | 2330 | gen_helper_sqrt_f64(res, cpu_env, src); |
e6e5906b PB |
2331 | break; |
2332 | case 0x18: case 0x58: case 0x5c: /* fabs */ | |
e1f3808e | 2333 | gen_helper_abs_f64(res, src); |
e6e5906b PB |
2334 | break; |
2335 | case 0x1a: case 0x5a: case 0x5e: /* fneg */ | |
e1f3808e | 2336 | gen_helper_chs_f64(res, src); |
e6e5906b PB |
2337 | break; |
2338 | case 0x20: case 0x60: case 0x64: /* fdiv */ | |
e1f3808e | 2339 | gen_helper_div_f64(res, cpu_env, res, src); |
e6e5906b PB |
2340 | break; |
2341 | case 0x22: case 0x62: case 0x66: /* fadd */ | |
e1f3808e | 2342 | gen_helper_add_f64(res, cpu_env, res, src); |
e6e5906b PB |
2343 | break; |
2344 | case 0x23: case 0x63: case 0x67: /* fmul */ | |
e1f3808e | 2345 | gen_helper_mul_f64(res, cpu_env, res, src); |
e6e5906b PB |
2346 | break; |
2347 | case 0x28: case 0x68: case 0x6c: /* fsub */ | |
e1f3808e | 2348 | gen_helper_sub_f64(res, cpu_env, res, src); |
e6e5906b PB |
2349 | break; |
2350 | case 0x38: /* fcmp */ | |
e1f3808e | 2351 | gen_helper_sub_cmp_f64(res, cpu_env, res, src); |
a7812ae4 | 2352 | set_dest = 0; |
e6e5906b PB |
2353 | round = 0; |
2354 | break; | |
2355 | case 0x3a: /* ftst */ | |
e1f3808e | 2356 | tcg_gen_mov_f64(res, src); |
a7812ae4 | 2357 | set_dest = 0; |
e6e5906b PB |
2358 | round = 0; |
2359 | break; | |
2360 | default: | |
2361 | goto undef; | |
2362 | } | |
a7812ae4 PB |
2363 | if (ext & (1 << 14)) { |
2364 | tcg_temp_free_i64(src); | |
2365 | } | |
e6e5906b PB |
2366 | if (round) { |
2367 | if (opmode & 0x40) { | |
2368 | if ((opmode & 0x4) != 0) | |
2369 | round = 0; | |
2370 | } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { | |
2371 | round = 0; | |
2372 | } | |
2373 | } | |
2374 | if (round) { | |
a7812ae4 | 2375 | TCGv tmp = tcg_temp_new_i32(); |
e1f3808e PB |
2376 | gen_helper_f64_to_f32(tmp, cpu_env, res); |
2377 | gen_helper_f32_to_f64(res, cpu_env, tmp); | |
a7812ae4 | 2378 | tcg_temp_free_i32(tmp); |
5fafdf24 | 2379 | } |
e1f3808e | 2380 | tcg_gen_mov_f64(QREG_FP_RESULT, res); |
a7812ae4 | 2381 | if (set_dest) { |
e1f3808e | 2382 | tcg_gen_mov_f64(dest, res); |
e6e5906b | 2383 | } |
a7812ae4 | 2384 | tcg_temp_free_i64(res); |
e6e5906b PB |
2385 | return; |
2386 | undef: | |
a7812ae4 | 2387 | /* FIXME: Is this right for offset addressing modes? */ |
e6e5906b | 2388 | s->pc -= 2; |
d4d79bb1 | 2389 | disas_undef_fpu(env, s, insn); |
e6e5906b PB |
2390 | } |
2391 | ||
2392 | DISAS_INSN(fbcc) | |
2393 | { | |
2394 | uint32_t offset; | |
2395 | uint32_t addr; | |
e1f3808e | 2396 | TCGv flag; |
42a268c2 | 2397 | TCGLabel *l1; |
e6e5906b PB |
2398 | |
2399 | addr = s->pc; | |
d4d79bb1 | 2400 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
2401 | s->pc += 2; |
2402 | if (insn & (1 << 6)) { | |
d4d79bb1 | 2403 | offset = (offset << 16) | cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2404 | s->pc += 2; |
2405 | } | |
2406 | ||
2407 | l1 = gen_new_label(); | |
2408 | /* TODO: Raise BSUN exception. */ | |
a7812ae4 | 2409 | flag = tcg_temp_new(); |
e1f3808e | 2410 | gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); |
e6e5906b PB |
2411 | /* Jump to l1 if condition is true. */ |
2412 | switch (insn & 0xf) { | |
2413 | case 0: /* f */ | |
2414 | break; | |
2415 | case 1: /* eq (=0) */ | |
e1f3808e | 2416 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2417 | break; |
2418 | case 2: /* ogt (=1) */ | |
e1f3808e | 2419 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2420 | break; |
2421 | case 3: /* oge (=0 or =1) */ | |
e1f3808e | 2422 | tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2423 | break; |
2424 | case 4: /* olt (=-1) */ | |
e1f3808e | 2425 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2426 | break; |
2427 | case 5: /* ole (=-1 or =0) */ | |
e1f3808e | 2428 | tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2429 | break; |
2430 | case 6: /* ogl (=-1 or =1) */ | |
e1f3808e PB |
2431 | tcg_gen_andi_i32(flag, flag, 1); |
2432 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2433 | break; |
2434 | case 7: /* or (=2) */ | |
e1f3808e | 2435 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2436 | break; |
2437 | case 8: /* un (<2) */ | |
e1f3808e | 2438 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2439 | break; |
2440 | case 9: /* ueq (=0 or =2) */ | |
e1f3808e PB |
2441 | tcg_gen_andi_i32(flag, flag, 1); |
2442 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2443 | break; |
2444 | case 10: /* ugt (>0) */ | |
e1f3808e | 2445 | tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2446 | break; |
2447 | case 11: /* uge (>=0) */ | |
e1f3808e | 2448 | tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2449 | break; |
2450 | case 12: /* ult (=-1 or =2) */ | |
e1f3808e | 2451 | tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2452 | break; |
2453 | case 13: /* ule (!=1) */ | |
e1f3808e | 2454 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2455 | break; |
2456 | case 14: /* ne (!=0) */ | |
e1f3808e | 2457 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2458 | break; |
2459 | case 15: /* t */ | |
e1f3808e | 2460 | tcg_gen_br(l1); |
e6e5906b PB |
2461 | break; |
2462 | } | |
2463 | gen_jmp_tb(s, 0, s->pc); | |
2464 | gen_set_label(l1); | |
2465 | gen_jmp_tb(s, 1, addr + offset); | |
2466 | } | |
2467 | ||
0633879f PB |
2468 | DISAS_INSN(frestore) |
2469 | { | |
a47dddd7 AF |
2470 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2471 | ||
0633879f | 2472 | /* TODO: Implement frestore. */ |
a47dddd7 | 2473 | cpu_abort(CPU(cpu), "FRESTORE not implemented"); |
0633879f PB |
2474 | } |
2475 | ||
2476 | DISAS_INSN(fsave) | |
2477 | { | |
a47dddd7 AF |
2478 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2479 | ||
0633879f | 2480 | /* TODO: Implement fsave. */ |
a47dddd7 | 2481 | cpu_abort(CPU(cpu), "FSAVE not implemented"); |
0633879f PB |
2482 | } |
2483 | ||
e1f3808e | 2484 | static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) |
acf930aa | 2485 | { |
a7812ae4 | 2486 | TCGv tmp = tcg_temp_new(); |
acf930aa PB |
2487 | if (s->env->macsr & MACSR_FI) { |
2488 | if (upper) | |
e1f3808e | 2489 | tcg_gen_andi_i32(tmp, val, 0xffff0000); |
acf930aa | 2490 | else |
e1f3808e | 2491 | tcg_gen_shli_i32(tmp, val, 16); |
acf930aa PB |
2492 | } else if (s->env->macsr & MACSR_SU) { |
2493 | if (upper) | |
e1f3808e | 2494 | tcg_gen_sari_i32(tmp, val, 16); |
acf930aa | 2495 | else |
e1f3808e | 2496 | tcg_gen_ext16s_i32(tmp, val); |
acf930aa PB |
2497 | } else { |
2498 | if (upper) | |
e1f3808e | 2499 | tcg_gen_shri_i32(tmp, val, 16); |
acf930aa | 2500 | else |
e1f3808e | 2501 | tcg_gen_ext16u_i32(tmp, val); |
acf930aa PB |
2502 | } |
2503 | return tmp; | |
2504 | } | |
2505 | ||
e1f3808e PB |
2506 | static void gen_mac_clear_flags(void) |
2507 | { | |
2508 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, | |
2509 | ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); | |
2510 | } | |
2511 | ||
acf930aa PB |
2512 | DISAS_INSN(mac) |
2513 | { | |
e1f3808e PB |
2514 | TCGv rx; |
2515 | TCGv ry; | |
acf930aa PB |
2516 | uint16_t ext; |
2517 | int acc; | |
e1f3808e PB |
2518 | TCGv tmp; |
2519 | TCGv addr; | |
2520 | TCGv loadval; | |
acf930aa | 2521 | int dual; |
e1f3808e PB |
2522 | TCGv saved_flags; |
2523 | ||
a7812ae4 PB |
2524 | if (!s->done_mac) { |
2525 | s->mactmp = tcg_temp_new_i64(); | |
2526 | s->done_mac = 1; | |
2527 | } | |
acf930aa | 2528 | |
d4d79bb1 | 2529 | ext = cpu_lduw_code(env, s->pc); |
acf930aa PB |
2530 | s->pc += 2; |
2531 | ||
2532 | acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); | |
2533 | dual = ((insn & 0x30) != 0 && (ext & 3) != 0); | |
d315c888 | 2534 | if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { |
d4d79bb1 | 2535 | disas_undef(env, s, insn); |
d315c888 PB |
2536 | return; |
2537 | } | |
acf930aa PB |
2538 | if (insn & 0x30) { |
2539 | /* MAC with load. */ | |
d4d79bb1 | 2540 | tmp = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2541 | addr = tcg_temp_new(); |
e1f3808e | 2542 | tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); |
acf930aa PB |
2543 | /* Load the value now to ensure correct exception behavior. |
2544 | Perform writeback after reading the MAC inputs. */ | |
2545 | loadval = gen_load(s, OS_LONG, addr, 0); | |
2546 | ||
2547 | acc ^= 1; | |
2548 | rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); | |
2549 | ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); | |
2550 | } else { | |
e1f3808e | 2551 | loadval = addr = NULL_QREG; |
acf930aa PB |
2552 | rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
2553 | ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
2554 | } | |
2555 | ||
e1f3808e PB |
2556 | gen_mac_clear_flags(); |
2557 | #if 0 | |
acf930aa | 2558 | l1 = -1; |
e1f3808e | 2559 | /* Disabled because conditional branches clobber temporary vars. */ |
acf930aa PB |
2560 | if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { |
2561 | /* Skip the multiply if we know we will ignore it. */ | |
2562 | l1 = gen_new_label(); | |
a7812ae4 | 2563 | tmp = tcg_temp_new(); |
e1f3808e | 2564 | tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); |
acf930aa PB |
2565 | gen_op_jmp_nz32(tmp, l1); |
2566 | } | |
e1f3808e | 2567 | #endif |
acf930aa PB |
2568 | |
2569 | if ((ext & 0x0800) == 0) { | |
2570 | /* Word. */ | |
2571 | rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); | |
2572 | ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); | |
2573 | } | |
2574 | if (s->env->macsr & MACSR_FI) { | |
e1f3808e | 2575 | gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2576 | } else { |
2577 | if (s->env->macsr & MACSR_SU) | |
e1f3808e | 2578 | gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); |
acf930aa | 2579 | else |
e1f3808e | 2580 | gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2581 | switch ((ext >> 9) & 3) { |
2582 | case 1: | |
e1f3808e | 2583 | tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2584 | break; |
2585 | case 3: | |
e1f3808e | 2586 | tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2587 | break; |
2588 | } | |
2589 | } | |
2590 | ||
2591 | if (dual) { | |
2592 | /* Save the overflow flag from the multiply. */ | |
a7812ae4 | 2593 | saved_flags = tcg_temp_new(); |
e1f3808e PB |
2594 | tcg_gen_mov_i32(saved_flags, QREG_MACSR); |
2595 | } else { | |
2596 | saved_flags = NULL_QREG; | |
acf930aa PB |
2597 | } |
2598 | ||
e1f3808e PB |
2599 | #if 0 |
2600 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2601 | if ((s->env->macsr & MACSR_OMC) != 0 && dual) { |
2602 | /* Skip the accumulate if the value is already saturated. */ | |
2603 | l1 = gen_new_label(); | |
a7812ae4 | 2604 | tmp = tcg_temp_new(); |
351326a6 | 2605 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2606 | gen_op_jmp_nz32(tmp, l1); |
2607 | } | |
e1f3808e | 2608 | #endif |
acf930aa PB |
2609 | |
2610 | if (insn & 0x100) | |
e1f3808e | 2611 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2612 | else |
e1f3808e | 2613 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa PB |
2614 | |
2615 | if (s->env->macsr & MACSR_FI) | |
e1f3808e | 2616 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2617 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2618 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2619 | else |
e1f3808e | 2620 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2621 | |
e1f3808e PB |
2622 | #if 0 |
2623 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2624 | if (l1 != -1) |
2625 | gen_set_label(l1); | |
e1f3808e | 2626 | #endif |
acf930aa PB |
2627 | |
2628 | if (dual) { | |
2629 | /* Dual accumulate variant. */ | |
2630 | acc = (ext >> 2) & 3; | |
2631 | /* Restore the overflow flag from the multiplier. */ | |
e1f3808e PB |
2632 | tcg_gen_mov_i32(QREG_MACSR, saved_flags); |
2633 | #if 0 | |
2634 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2635 | if ((s->env->macsr & MACSR_OMC) != 0) { |
2636 | /* Skip the accumulate if the value is already saturated. */ | |
2637 | l1 = gen_new_label(); | |
a7812ae4 | 2638 | tmp = tcg_temp_new(); |
351326a6 | 2639 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2640 | gen_op_jmp_nz32(tmp, l1); |
2641 | } | |
e1f3808e | 2642 | #endif |
acf930aa | 2643 | if (ext & 2) |
e1f3808e | 2644 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2645 | else |
e1f3808e | 2646 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2647 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2648 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2649 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2650 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2651 | else |
e1f3808e PB |
2652 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
2653 | #if 0 | |
2654 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2655 | if (l1 != -1) |
2656 | gen_set_label(l1); | |
e1f3808e | 2657 | #endif |
acf930aa | 2658 | } |
e1f3808e | 2659 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); |
acf930aa PB |
2660 | |
2661 | if (insn & 0x30) { | |
e1f3808e | 2662 | TCGv rw; |
acf930aa | 2663 | rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
e1f3808e | 2664 | tcg_gen_mov_i32(rw, loadval); |
acf930aa PB |
2665 | /* FIXME: Should address writeback happen with the masked or |
2666 | unmasked value? */ | |
2667 | switch ((insn >> 3) & 7) { | |
2668 | case 3: /* Post-increment. */ | |
e1f3808e | 2669 | tcg_gen_addi_i32(AREG(insn, 0), addr, 4); |
acf930aa PB |
2670 | break; |
2671 | case 4: /* Pre-decrement. */ | |
e1f3808e | 2672 | tcg_gen_mov_i32(AREG(insn, 0), addr); |
acf930aa PB |
2673 | } |
2674 | } | |
2675 | } | |
2676 | ||
2677 | DISAS_INSN(from_mac) | |
2678 | { | |
e1f3808e | 2679 | TCGv rx; |
a7812ae4 | 2680 | TCGv_i64 acc; |
e1f3808e | 2681 | int accnum; |
acf930aa PB |
2682 | |
2683 | rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e PB |
2684 | accnum = (insn >> 9) & 3; |
2685 | acc = MACREG(accnum); | |
acf930aa | 2686 | if (s->env->macsr & MACSR_FI) { |
a7812ae4 | 2687 | gen_helper_get_macf(rx, cpu_env, acc); |
acf930aa | 2688 | } else if ((s->env->macsr & MACSR_OMC) == 0) { |
ecc7b3aa | 2689 | tcg_gen_extrl_i64_i32(rx, acc); |
acf930aa | 2690 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2691 | gen_helper_get_macs(rx, acc); |
acf930aa | 2692 | } else { |
e1f3808e PB |
2693 | gen_helper_get_macu(rx, acc); |
2694 | } | |
2695 | if (insn & 0x40) { | |
2696 | tcg_gen_movi_i64(acc, 0); | |
2697 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
acf930aa | 2698 | } |
acf930aa PB |
2699 | } |
2700 | ||
2701 | DISAS_INSN(move_mac) | |
2702 | { | |
e1f3808e | 2703 | /* FIXME: This can be done without a helper. */ |
acf930aa | 2704 | int src; |
e1f3808e | 2705 | TCGv dest; |
acf930aa | 2706 | src = insn & 3; |
e1f3808e PB |
2707 | dest = tcg_const_i32((insn >> 9) & 3); |
2708 | gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); | |
2709 | gen_mac_clear_flags(); | |
2710 | gen_helper_mac_set_flags(cpu_env, dest); | |
acf930aa PB |
2711 | } |
2712 | ||
2713 | DISAS_INSN(from_macsr) | |
2714 | { | |
e1f3808e | 2715 | TCGv reg; |
acf930aa PB |
2716 | |
2717 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e | 2718 | tcg_gen_mov_i32(reg, QREG_MACSR); |
acf930aa PB |
2719 | } |
2720 | ||
2721 | DISAS_INSN(from_mask) | |
2722 | { | |
e1f3808e | 2723 | TCGv reg; |
acf930aa | 2724 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2725 | tcg_gen_mov_i32(reg, QREG_MAC_MASK); |
acf930aa PB |
2726 | } |
2727 | ||
2728 | DISAS_INSN(from_mext) | |
2729 | { | |
e1f3808e PB |
2730 | TCGv reg; |
2731 | TCGv acc; | |
acf930aa | 2732 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2733 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2734 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2735 | gen_helper_get_mac_extf(reg, cpu_env, acc); |
acf930aa | 2736 | else |
e1f3808e | 2737 | gen_helper_get_mac_exti(reg, cpu_env, acc); |
acf930aa PB |
2738 | } |
2739 | ||
2740 | DISAS_INSN(macsr_to_ccr) | |
2741 | { | |
e1f3808e PB |
2742 | tcg_gen_movi_i32(QREG_CC_X, 0); |
2743 | tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf); | |
acf930aa PB |
2744 | s->cc_op = CC_OP_FLAGS; |
2745 | } | |
2746 | ||
2747 | DISAS_INSN(to_mac) | |
2748 | { | |
a7812ae4 | 2749 | TCGv_i64 acc; |
e1f3808e PB |
2750 | TCGv val; |
2751 | int accnum; | |
2752 | accnum = (insn >> 9) & 3; | |
2753 | acc = MACREG(accnum); | |
d4d79bb1 | 2754 | SRC_EA(env, val, OS_LONG, 0, NULL); |
acf930aa | 2755 | if (s->env->macsr & MACSR_FI) { |
e1f3808e PB |
2756 | tcg_gen_ext_i32_i64(acc, val); |
2757 | tcg_gen_shli_i64(acc, acc, 8); | |
acf930aa | 2758 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2759 | tcg_gen_ext_i32_i64(acc, val); |
acf930aa | 2760 | } else { |
e1f3808e | 2761 | tcg_gen_extu_i32_i64(acc, val); |
acf930aa | 2762 | } |
e1f3808e PB |
2763 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); |
2764 | gen_mac_clear_flags(); | |
2765 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); | |
acf930aa PB |
2766 | } |
2767 | ||
2768 | DISAS_INSN(to_macsr) | |
2769 | { | |
e1f3808e | 2770 | TCGv val; |
d4d79bb1 | 2771 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2772 | gen_helper_set_macsr(cpu_env, val); |
acf930aa PB |
2773 | gen_lookup_tb(s); |
2774 | } | |
2775 | ||
2776 | DISAS_INSN(to_mask) | |
2777 | { | |
e1f3808e | 2778 | TCGv val; |
d4d79bb1 | 2779 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2780 | tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); |
acf930aa PB |
2781 | } |
2782 | ||
2783 | DISAS_INSN(to_mext) | |
2784 | { | |
e1f3808e PB |
2785 | TCGv val; |
2786 | TCGv acc; | |
d4d79bb1 | 2787 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2788 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2789 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2790 | gen_helper_set_mac_extf(cpu_env, val, acc); |
acf930aa | 2791 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2792 | gen_helper_set_mac_exts(cpu_env, val, acc); |
acf930aa | 2793 | else |
e1f3808e | 2794 | gen_helper_set_mac_extu(cpu_env, val, acc); |
acf930aa PB |
2795 | } |
2796 | ||
e6e5906b PB |
2797 | static disas_proc opcode_table[65536]; |
2798 | ||
2799 | static void | |
2800 | register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) | |
2801 | { | |
2802 | int i; | |
2803 | int from; | |
2804 | int to; | |
2805 | ||
2806 | /* Sanity check. All set bits must be included in the mask. */ | |
5fc4adf6 PB |
2807 | if (opcode & ~mask) { |
2808 | fprintf(stderr, | |
2809 | "qemu internal error: bogus opcode definition %04x/%04x\n", | |
2810 | opcode, mask); | |
e6e5906b | 2811 | abort(); |
5fc4adf6 | 2812 | } |
e6e5906b PB |
2813 | /* This could probably be cleverer. For now just optimize the case where |
2814 | the top bits are known. */ | |
2815 | /* Find the first zero bit in the mask. */ | |
2816 | i = 0x8000; | |
2817 | while ((i & mask) != 0) | |
2818 | i >>= 1; | |
2819 | /* Iterate over all combinations of this and lower bits. */ | |
2820 | if (i == 0) | |
2821 | i = 1; | |
2822 | else | |
2823 | i <<= 1; | |
2824 | from = opcode & ~(i - 1); | |
2825 | to = from + i; | |
0633879f | 2826 | for (i = from; i < to; i++) { |
e6e5906b PB |
2827 | if ((i & mask) == opcode) |
2828 | opcode_table[i] = proc; | |
0633879f | 2829 | } |
e6e5906b PB |
2830 | } |
2831 | ||
2832 | /* Register m68k opcode handlers. Order is important. | |
2833 | Later insn override earlier ones. */ | |
0402f767 | 2834 | void register_m68k_insns (CPUM68KState *env) |
e6e5906b | 2835 | { |
d315c888 | 2836 | #define INSN(name, opcode, mask, feature) do { \ |
0402f767 | 2837 | if (m68k_feature(env, M68K_FEATURE_##feature)) \ |
d315c888 PB |
2838 | register_opcode(disas_##name, 0x##opcode, 0x##mask); \ |
2839 | } while(0) | |
0402f767 PB |
2840 | INSN(undef, 0000, 0000, CF_ISA_A); |
2841 | INSN(arith_im, 0080, fff8, CF_ISA_A); | |
d315c888 | 2842 | INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); |
0402f767 PB |
2843 | INSN(bitop_reg, 0100, f1c0, CF_ISA_A); |
2844 | INSN(bitop_reg, 0140, f1c0, CF_ISA_A); | |
2845 | INSN(bitop_reg, 0180, f1c0, CF_ISA_A); | |
2846 | INSN(bitop_reg, 01c0, f1c0, CF_ISA_A); | |
2847 | INSN(arith_im, 0280, fff8, CF_ISA_A); | |
d315c888 | 2848 | INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); |
0402f767 | 2849 | INSN(arith_im, 0480, fff8, CF_ISA_A); |
d315c888 | 2850 | INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); |
0402f767 PB |
2851 | INSN(arith_im, 0680, fff8, CF_ISA_A); |
2852 | INSN(bitop_im, 0800, ffc0, CF_ISA_A); | |
2853 | INSN(bitop_im, 0840, ffc0, CF_ISA_A); | |
2854 | INSN(bitop_im, 0880, ffc0, CF_ISA_A); | |
2855 | INSN(bitop_im, 08c0, ffc0, CF_ISA_A); | |
2856 | INSN(arith_im, 0a80, fff8, CF_ISA_A); | |
2857 | INSN(arith_im, 0c00, ff38, CF_ISA_A); | |
2858 | INSN(move, 1000, f000, CF_ISA_A); | |
2859 | INSN(move, 2000, f000, CF_ISA_A); | |
2860 | INSN(move, 3000, f000, CF_ISA_A); | |
d315c888 | 2861 | INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); |
0402f767 PB |
2862 | INSN(negx, 4080, fff8, CF_ISA_A); |
2863 | INSN(move_from_sr, 40c0, fff8, CF_ISA_A); | |
2864 | INSN(lea, 41c0, f1c0, CF_ISA_A); | |
2865 | INSN(clr, 4200, ff00, CF_ISA_A); | |
2866 | INSN(undef, 42c0, ffc0, CF_ISA_A); | |
2867 | INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); | |
2868 | INSN(neg, 4480, fff8, CF_ISA_A); | |
2869 | INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A); | |
2870 | INSN(not, 4680, fff8, CF_ISA_A); | |
2871 | INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); | |
2872 | INSN(pea, 4840, ffc0, CF_ISA_A); | |
2873 | INSN(swap, 4840, fff8, CF_ISA_A); | |
2874 | INSN(movem, 48c0, fbc0, CF_ISA_A); | |
2875 | INSN(ext, 4880, fff8, CF_ISA_A); | |
2876 | INSN(ext, 48c0, fff8, CF_ISA_A); | |
2877 | INSN(ext, 49c0, fff8, CF_ISA_A); | |
2878 | INSN(tst, 4a00, ff00, CF_ISA_A); | |
2879 | INSN(tas, 4ac0, ffc0, CF_ISA_B); | |
2880 | INSN(halt, 4ac8, ffff, CF_ISA_A); | |
2881 | INSN(pulse, 4acc, ffff, CF_ISA_A); | |
2882 | INSN(illegal, 4afc, ffff, CF_ISA_A); | |
2883 | INSN(mull, 4c00, ffc0, CF_ISA_A); | |
2884 | INSN(divl, 4c40, ffc0, CF_ISA_A); | |
2885 | INSN(sats, 4c80, fff8, CF_ISA_B); | |
2886 | INSN(trap, 4e40, fff0, CF_ISA_A); | |
2887 | INSN(link, 4e50, fff8, CF_ISA_A); | |
2888 | INSN(unlk, 4e58, fff8, CF_ISA_A); | |
20dcee94 PB |
2889 | INSN(move_to_usp, 4e60, fff8, USP); |
2890 | INSN(move_from_usp, 4e68, fff8, USP); | |
0402f767 PB |
2891 | INSN(nop, 4e71, ffff, CF_ISA_A); |
2892 | INSN(stop, 4e72, ffff, CF_ISA_A); | |
2893 | INSN(rte, 4e73, ffff, CF_ISA_A); | |
2894 | INSN(rts, 4e75, ffff, CF_ISA_A); | |
2895 | INSN(movec, 4e7b, ffff, CF_ISA_A); | |
2896 | INSN(jump, 4e80, ffc0, CF_ISA_A); | |
2897 | INSN(jump, 4ec0, ffc0, CF_ISA_A); | |
2898 | INSN(addsubq, 5180, f1c0, CF_ISA_A); | |
2899 | INSN(scc, 50c0, f0f8, CF_ISA_A); | |
2900 | INSN(addsubq, 5080, f1c0, CF_ISA_A); | |
2901 | INSN(tpf, 51f8, fff8, CF_ISA_A); | |
d315c888 PB |
2902 | |
2903 | /* Branch instructions. */ | |
0402f767 | 2904 | INSN(branch, 6000, f000, CF_ISA_A); |
d315c888 PB |
2905 | /* Disable long branch instructions, then add back the ones we want. */ |
2906 | INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */ | |
2907 | INSN(branch, 60ff, f0ff, CF_ISA_B); | |
2908 | INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ | |
2909 | INSN(branch, 60ff, ffff, BRAL); | |
2910 | ||
0402f767 PB |
2911 | INSN(moveq, 7000, f100, CF_ISA_A); |
2912 | INSN(mvzs, 7100, f100, CF_ISA_B); | |
2913 | INSN(or, 8000, f000, CF_ISA_A); | |
2914 | INSN(divw, 80c0, f0c0, CF_ISA_A); | |
2915 | INSN(addsub, 9000, f000, CF_ISA_A); | |
2916 | INSN(subx, 9180, f1f8, CF_ISA_A); | |
2917 | INSN(suba, 91c0, f1c0, CF_ISA_A); | |
acf930aa | 2918 | |
0402f767 | 2919 | INSN(undef_mac, a000, f000, CF_ISA_A); |
acf930aa PB |
2920 | INSN(mac, a000, f100, CF_EMAC); |
2921 | INSN(from_mac, a180, f9b0, CF_EMAC); | |
2922 | INSN(move_mac, a110, f9fc, CF_EMAC); | |
2923 | INSN(from_macsr,a980, f9f0, CF_EMAC); | |
2924 | INSN(from_mask, ad80, fff0, CF_EMAC); | |
2925 | INSN(from_mext, ab80, fbf0, CF_EMAC); | |
2926 | INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); | |
2927 | INSN(to_mac, a100, f9c0, CF_EMAC); | |
2928 | INSN(to_macsr, a900, ffc0, CF_EMAC); | |
2929 | INSN(to_mext, ab00, fbc0, CF_EMAC); | |
2930 | INSN(to_mask, ad00, ffc0, CF_EMAC); | |
2931 | ||
0402f767 PB |
2932 | INSN(mov3q, a140, f1c0, CF_ISA_B); |
2933 | INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ | |
2934 | INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ | |
2935 | INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ | |
2936 | INSN(cmp, b080, f1c0, CF_ISA_A); | |
2937 | INSN(cmpa, b1c0, f1c0, CF_ISA_A); | |
2938 | INSN(eor, b180, f1c0, CF_ISA_A); | |
2939 | INSN(and, c000, f000, CF_ISA_A); | |
2940 | INSN(mulw, c0c0, f0c0, CF_ISA_A); | |
2941 | INSN(addsub, d000, f000, CF_ISA_A); | |
2942 | INSN(addx, d180, f1f8, CF_ISA_A); | |
2943 | INSN(adda, d1c0, f1c0, CF_ISA_A); | |
2944 | INSN(shift_im, e080, f0f0, CF_ISA_A); | |
2945 | INSN(shift_reg, e0a0, f0f0, CF_ISA_A); | |
2946 | INSN(undef_fpu, f000, f000, CF_ISA_A); | |
e6e5906b PB |
2947 | INSN(fpu, f200, ffc0, CF_FPU); |
2948 | INSN(fbcc, f280, ffc0, CF_FPU); | |
0633879f PB |
2949 | INSN(frestore, f340, ffc0, CF_FPU); |
2950 | INSN(fsave, f340, ffc0, CF_FPU); | |
0402f767 PB |
2951 | INSN(intouch, f340, ffc0, CF_ISA_A); |
2952 | INSN(cpushl, f428, ff38, CF_ISA_A); | |
2953 | INSN(wddata, fb00, ff00, CF_ISA_A); | |
2954 | INSN(wdebug, fbc0, ffc0, CF_ISA_A); | |
e6e5906b PB |
2955 | #undef INSN |
2956 | } | |
2957 | ||
2958 | /* ??? Some of this implementation is not exception safe. We should always | |
2959 | write back the result to memory before setting the condition codes. */ | |
2b3e3cfe | 2960 | static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) |
e6e5906b PB |
2961 | { |
2962 | uint16_t insn; | |
2963 | ||
d4d79bb1 | 2964 | insn = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2965 | s->pc += 2; |
2966 | ||
d4d79bb1 | 2967 | opcode_table[insn](env, s, insn); |
e6e5906b PB |
2968 | } |
2969 | ||
e6e5906b | 2970 | /* generate intermediate code for basic block 'tb'. */ |
4e5e1215 | 2971 | void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 2972 | { |
4e5e1215 | 2973 | M68kCPU *cpu = m68k_env_get_cpu(env); |
ed2803da | 2974 | CPUState *cs = CPU(cpu); |
e6e5906b | 2975 | DisasContext dc1, *dc = &dc1; |
e6e5906b PB |
2976 | target_ulong pc_start; |
2977 | int pc_offset; | |
2e70f6ef PB |
2978 | int num_insns; |
2979 | int max_insns; | |
e6e5906b PB |
2980 | |
2981 | /* generate intermediate code */ | |
2982 | pc_start = tb->pc; | |
3b46e624 | 2983 | |
e6e5906b PB |
2984 | dc->tb = tb; |
2985 | ||
e6dbd3b3 | 2986 | dc->env = env; |
e6e5906b PB |
2987 | dc->is_jmp = DISAS_NEXT; |
2988 | dc->pc = pc_start; | |
2989 | dc->cc_op = CC_OP_DYNAMIC; | |
ed2803da | 2990 | dc->singlestep_enabled = cs->singlestep_enabled; |
e6e5906b | 2991 | dc->fpcr = env->fpcr; |
0633879f | 2992 | dc->user = (env->sr & SR_S) == 0; |
a7812ae4 | 2993 | dc->done_mac = 0; |
2e70f6ef PB |
2994 | num_insns = 0; |
2995 | max_insns = tb->cflags & CF_COUNT_MASK; | |
190ce7fb | 2996 | if (max_insns == 0) { |
2e70f6ef | 2997 | max_insns = CF_COUNT_MASK; |
190ce7fb RH |
2998 | } |
2999 | if (max_insns > TCG_MAX_INSNS) { | |
3000 | max_insns = TCG_MAX_INSNS; | |
3001 | } | |
2e70f6ef | 3002 | |
cd42d5b2 | 3003 | gen_tb_start(tb); |
e6e5906b | 3004 | do { |
e6e5906b PB |
3005 | pc_offset = dc->pc - pc_start; |
3006 | gen_throws_exception = NULL; | |
667b8e29 | 3007 | tcg_gen_insn_start(dc->pc); |
959082fc | 3008 | num_insns++; |
667b8e29 | 3009 | |
b933066a RH |
3010 | if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { |
3011 | gen_exception(dc, dc->pc, EXCP_DEBUG); | |
3012 | dc->is_jmp = DISAS_JUMP; | |
522a0d4e RH |
3013 | /* The address covered by the breakpoint must be included in |
3014 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
3015 | properly cleared -- thus we increment the PC here so that | |
3016 | the logic setting tb->size below does the right thing. */ | |
3017 | dc->pc += 2; | |
b933066a RH |
3018 | break; |
3019 | } | |
3020 | ||
959082fc | 3021 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
2e70f6ef | 3022 | gen_io_start(); |
667b8e29 RH |
3023 | } |
3024 | ||
510ff0b7 | 3025 | dc->insn_pc = dc->pc; |
e6e5906b | 3026 | disas_m68k_insn(env, dc); |
fe700adb | 3027 | } while (!dc->is_jmp && !tcg_op_buf_full() && |
ed2803da | 3028 | !cs->singlestep_enabled && |
1b530a6d | 3029 | !singlestep && |
2e70f6ef PB |
3030 | (pc_offset) < (TARGET_PAGE_SIZE - 32) && |
3031 | num_insns < max_insns); | |
e6e5906b | 3032 | |
2e70f6ef PB |
3033 | if (tb->cflags & CF_LAST_IO) |
3034 | gen_io_end(); | |
ed2803da | 3035 | if (unlikely(cs->singlestep_enabled)) { |
e6e5906b PB |
3036 | /* Make sure the pc is updated, and raise a debug exception. */ |
3037 | if (!dc->is_jmp) { | |
3038 | gen_flush_cc_op(dc); | |
e1f3808e | 3039 | tcg_gen_movi_i32(QREG_PC, dc->pc); |
e6e5906b | 3040 | } |
31871141 | 3041 | gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); |
e6e5906b PB |
3042 | } else { |
3043 | switch(dc->is_jmp) { | |
3044 | case DISAS_NEXT: | |
3045 | gen_flush_cc_op(dc); | |
3046 | gen_jmp_tb(dc, 0, dc->pc); | |
3047 | break; | |
3048 | default: | |
3049 | case DISAS_JUMP: | |
3050 | case DISAS_UPDATE: | |
3051 | gen_flush_cc_op(dc); | |
3052 | /* indicate that the hash table must be used to find the next TB */ | |
57fec1fe | 3053 | tcg_gen_exit_tb(0); |
e6e5906b PB |
3054 | break; |
3055 | case DISAS_TB_JUMP: | |
3056 | /* nothing more to generate */ | |
3057 | break; | |
3058 | } | |
3059 | } | |
806f352d | 3060 | gen_tb_end(tb, num_insns); |
e6e5906b PB |
3061 | |
3062 | #ifdef DEBUG_DISAS | |
8fec2b8c | 3063 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
93fcfe39 AL |
3064 | qemu_log("----------------\n"); |
3065 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 3066 | log_target_disas(cs, pc_start, dc->pc - pc_start, 0); |
93fcfe39 | 3067 | qemu_log("\n"); |
e6e5906b PB |
3068 | } |
3069 | #endif | |
4e5e1215 RH |
3070 | tb->size = dc->pc - pc_start; |
3071 | tb->icount = num_insns; | |
e6e5906b PB |
3072 | } |
3073 | ||
878096ee AF |
3074 | void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
3075 | int flags) | |
e6e5906b | 3076 | { |
878096ee AF |
3077 | M68kCPU *cpu = M68K_CPU(cs); |
3078 | CPUM68KState *env = &cpu->env; | |
e6e5906b PB |
3079 | int i; |
3080 | uint16_t sr; | |
3081 | CPU_DoubleU u; | |
3082 | for (i = 0; i < 8; i++) | |
3083 | { | |
3084 | u.d = env->fregs[i]; | |
3085 | cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", | |
3086 | i, env->dregs[i], i, env->aregs[i], | |
8fc7cc58 | 3087 | i, u.l.upper, u.l.lower, *(double *)&u.d); |
e6e5906b PB |
3088 | } |
3089 | cpu_fprintf (f, "PC = %08x ", env->pc); | |
3090 | sr = env->sr; | |
3091 | cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-', | |
3092 | (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', | |
3093 | (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); | |
8fc7cc58 | 3094 | cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); |
e6e5906b PB |
3095 | } |
3096 | ||
bad729e2 RH |
3097 | void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, |
3098 | target_ulong *data) | |
d2856f1a | 3099 | { |
bad729e2 | 3100 | env->pc = data[0]; |
d2856f1a | 3101 | } |