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Commit | Line | Data |
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e6e5906b PB |
1 | /* |
2 | * m68k translation | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
e6e5906b | 20 | |
d8416665 | 21 | #include "qemu/osdep.h" |
e6e5906b | 22 | #include "cpu.h" |
76cad711 | 23 | #include "disas/disas.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
57fec1fe | 25 | #include "tcg-op.h" |
1de7afc9 | 26 | #include "qemu/log.h" |
f08b6170 | 27 | #include "exec/cpu_ldst.h" |
e1f3808e | 28 | |
2ef6175a RH |
29 | #include "exec/helper-proto.h" |
30 | #include "exec/helper-gen.h" | |
e6e5906b | 31 | |
a7e30d84 | 32 | #include "trace-tcg.h" |
508127e2 | 33 | #include "exec/log.h" |
a7e30d84 LV |
34 | |
35 | ||
0633879f PB |
36 | //#define DEBUG_DISPATCH 1 |
37 | ||
815a6742 | 38 | /* Fake floating point. */ |
815a6742 | 39 | #define tcg_gen_mov_f64 tcg_gen_mov_i64 |
815a6742 | 40 | #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 |
815a6742 | 41 | #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 |
815a6742 | 42 | |
e1f3808e | 43 | #define DEFO32(name, offset) static TCGv QREG_##name; |
a7812ae4 PB |
44 | #define DEFO64(name, offset) static TCGv_i64 QREG_##name; |
45 | #define DEFF64(name, offset) static TCGv_i64 QREG_##name; | |
e1f3808e PB |
46 | #include "qregs.def" |
47 | #undef DEFO32 | |
48 | #undef DEFO64 | |
49 | #undef DEFF64 | |
50 | ||
259186a7 | 51 | static TCGv_i32 cpu_halted; |
27103424 | 52 | static TCGv_i32 cpu_exception_index; |
259186a7 | 53 | |
1bcea73e | 54 | static TCGv_env cpu_env; |
e1f3808e PB |
55 | |
56 | static char cpu_reg_names[3*8*3 + 5*4]; | |
57 | static TCGv cpu_dregs[8]; | |
58 | static TCGv cpu_aregs[8]; | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fregs[8]; |
60 | static TCGv_i64 cpu_macc[4]; | |
e1f3808e PB |
61 | |
62 | #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7] | |
63 | #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7] | |
64 | #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7] | |
65 | #define MACREG(acc) cpu_macc[acc] | |
66 | #define QREG_SP cpu_aregs[7] | |
67 | ||
68 | static TCGv NULL_QREG; | |
a7812ae4 | 69 | #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) |
e1f3808e PB |
70 | /* Used to distinguish stores from bad addressing modes. */ |
71 | static TCGv store_dummy; | |
72 | ||
022c62cb | 73 | #include "exec/gen-icount.h" |
2e70f6ef | 74 | |
e1f3808e PB |
75 | void m68k_tcg_init(void) |
76 | { | |
77 | char *p; | |
78 | int i; | |
79 | ||
e1ccc054 RH |
80 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
81 | ||
82 | #define DEFO32(name, offset) \ | |
83 | QREG_##name = tcg_global_mem_new_i32(cpu_env, \ | |
84 | offsetof(CPUM68KState, offset), #name); | |
85 | #define DEFO64(name, offset) \ | |
86 | QREG_##name = tcg_global_mem_new_i64(cpu_env, \ | |
87 | offsetof(CPUM68KState, offset), #name); | |
88 | #define DEFF64(name, offset) DEFO64(name, offset) | |
e1f3808e PB |
89 | #include "qregs.def" |
90 | #undef DEFO32 | |
91 | #undef DEFO64 | |
92 | #undef DEFF64 | |
93 | ||
e1ccc054 | 94 | cpu_halted = tcg_global_mem_new_i32(cpu_env, |
259186a7 AF |
95 | -offsetof(M68kCPU, env) + |
96 | offsetof(CPUState, halted), "HALTED"); | |
e1ccc054 | 97 | cpu_exception_index = tcg_global_mem_new_i32(cpu_env, |
27103424 AF |
98 | -offsetof(M68kCPU, env) + |
99 | offsetof(CPUState, exception_index), | |
100 | "EXCEPTION"); | |
259186a7 | 101 | |
e1f3808e PB |
102 | p = cpu_reg_names; |
103 | for (i = 0; i < 8; i++) { | |
104 | sprintf(p, "D%d", i); | |
e1ccc054 | 105 | cpu_dregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
106 | offsetof(CPUM68KState, dregs[i]), p); |
107 | p += 3; | |
108 | sprintf(p, "A%d", i); | |
e1ccc054 | 109 | cpu_aregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
110 | offsetof(CPUM68KState, aregs[i]), p); |
111 | p += 3; | |
112 | sprintf(p, "F%d", i); | |
e1ccc054 | 113 | cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
114 | offsetof(CPUM68KState, fregs[i]), p); |
115 | p += 3; | |
116 | } | |
117 | for (i = 0; i < 4; i++) { | |
118 | sprintf(p, "ACC%d", i); | |
e1ccc054 | 119 | cpu_macc[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
120 | offsetof(CPUM68KState, macc[i]), p); |
121 | p += 5; | |
122 | } | |
123 | ||
e1ccc054 RH |
124 | NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL"); |
125 | store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL"); | |
e1f3808e PB |
126 | } |
127 | ||
e6e5906b PB |
128 | /* internal defines */ |
129 | typedef struct DisasContext { | |
e6dbd3b3 | 130 | CPUM68KState *env; |
510ff0b7 | 131 | target_ulong insn_pc; /* Start of the current instruction. */ |
e6e5906b PB |
132 | target_ulong pc; |
133 | int is_jmp; | |
134 | int cc_op; | |
0633879f | 135 | int user; |
e6e5906b PB |
136 | uint32_t fpcr; |
137 | struct TranslationBlock *tb; | |
138 | int singlestep_enabled; | |
a7812ae4 PB |
139 | TCGv_i64 mactmp; |
140 | int done_mac; | |
e6e5906b PB |
141 | } DisasContext; |
142 | ||
143 | #define DISAS_JUMP_NEXT 4 | |
144 | ||
0633879f PB |
145 | #if defined(CONFIG_USER_ONLY) |
146 | #define IS_USER(s) 1 | |
147 | #else | |
148 | #define IS_USER(s) s->user | |
149 | #endif | |
150 | ||
e6e5906b PB |
151 | /* XXX: move that elsewhere */ |
152 | /* ??? Fix exceptions. */ | |
153 | static void *gen_throws_exception; | |
154 | #define gen_last_qop NULL | |
155 | ||
e6e5906b PB |
156 | #define OS_BYTE 0 |
157 | #define OS_WORD 1 | |
158 | #define OS_LONG 2 | |
159 | #define OS_SINGLE 4 | |
160 | #define OS_DOUBLE 5 | |
161 | ||
d4d79bb1 | 162 | typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); |
e6e5906b | 163 | |
0633879f | 164 | #ifdef DEBUG_DISPATCH |
d4d79bb1 BS |
165 | #define DISAS_INSN(name) \ |
166 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
167 | uint16_t insn); \ | |
168 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
169 | uint16_t insn) \ | |
170 | { \ | |
171 | qemu_log("Dispatch " #name "\n"); \ | |
172 | real_disas_##name(s, env, insn); \ | |
173 | } \ | |
174 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
175 | uint16_t insn) | |
0633879f | 176 | #else |
d4d79bb1 BS |
177 | #define DISAS_INSN(name) \ |
178 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
179 | uint16_t insn) | |
0633879f | 180 | #endif |
e6e5906b PB |
181 | |
182 | /* Generate a load from the specified address. Narrow values are | |
183 | sign extended to full register width. */ | |
e1f3808e | 184 | static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) |
e6e5906b | 185 | { |
e1f3808e PB |
186 | TCGv tmp; |
187 | int index = IS_USER(s); | |
a7812ae4 | 188 | tmp = tcg_temp_new_i32(); |
e6e5906b PB |
189 | switch(opsize) { |
190 | case OS_BYTE: | |
e6e5906b | 191 | if (sign) |
e1f3808e | 192 | tcg_gen_qemu_ld8s(tmp, addr, index); |
e6e5906b | 193 | else |
e1f3808e | 194 | tcg_gen_qemu_ld8u(tmp, addr, index); |
e6e5906b PB |
195 | break; |
196 | case OS_WORD: | |
e6e5906b | 197 | if (sign) |
e1f3808e | 198 | tcg_gen_qemu_ld16s(tmp, addr, index); |
e6e5906b | 199 | else |
e1f3808e | 200 | tcg_gen_qemu_ld16u(tmp, addr, index); |
e6e5906b PB |
201 | break; |
202 | case OS_LONG: | |
e6e5906b | 203 | case OS_SINGLE: |
a7812ae4 | 204 | tcg_gen_qemu_ld32u(tmp, addr, index); |
e6e5906b PB |
205 | break; |
206 | default: | |
7372c2b9 | 207 | g_assert_not_reached(); |
e6e5906b PB |
208 | } |
209 | gen_throws_exception = gen_last_qop; | |
210 | return tmp; | |
211 | } | |
212 | ||
a7812ae4 PB |
213 | static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) |
214 | { | |
215 | TCGv_i64 tmp; | |
216 | int index = IS_USER(s); | |
a7812ae4 PB |
217 | tmp = tcg_temp_new_i64(); |
218 | tcg_gen_qemu_ldf64(tmp, addr, index); | |
219 | gen_throws_exception = gen_last_qop; | |
220 | return tmp; | |
221 | } | |
222 | ||
e6e5906b | 223 | /* Generate a store. */ |
e1f3808e | 224 | static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) |
e6e5906b | 225 | { |
e1f3808e | 226 | int index = IS_USER(s); |
e6e5906b PB |
227 | switch(opsize) { |
228 | case OS_BYTE: | |
e1f3808e | 229 | tcg_gen_qemu_st8(val, addr, index); |
e6e5906b PB |
230 | break; |
231 | case OS_WORD: | |
e1f3808e | 232 | tcg_gen_qemu_st16(val, addr, index); |
e6e5906b PB |
233 | break; |
234 | case OS_LONG: | |
e6e5906b | 235 | case OS_SINGLE: |
a7812ae4 | 236 | tcg_gen_qemu_st32(val, addr, index); |
e6e5906b PB |
237 | break; |
238 | default: | |
7372c2b9 | 239 | g_assert_not_reached(); |
e6e5906b PB |
240 | } |
241 | gen_throws_exception = gen_last_qop; | |
242 | } | |
243 | ||
a7812ae4 PB |
244 | static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) |
245 | { | |
246 | int index = IS_USER(s); | |
a7812ae4 PB |
247 | tcg_gen_qemu_stf64(val, addr, index); |
248 | gen_throws_exception = gen_last_qop; | |
249 | } | |
250 | ||
e1f3808e PB |
251 | typedef enum { |
252 | EA_STORE, | |
253 | EA_LOADU, | |
254 | EA_LOADS | |
255 | } ea_what; | |
256 | ||
e6e5906b PB |
257 | /* Generate an unsigned load if VAL is 0 a signed load if val is -1, |
258 | otherwise generate a store. */ | |
e1f3808e PB |
259 | static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, |
260 | ea_what what) | |
e6e5906b | 261 | { |
e1f3808e | 262 | if (what == EA_STORE) { |
0633879f | 263 | gen_store(s, opsize, addr, val); |
e1f3808e | 264 | return store_dummy; |
e6e5906b | 265 | } else { |
e1f3808e | 266 | return gen_load(s, opsize, addr, what == EA_LOADS); |
e6e5906b PB |
267 | } |
268 | } | |
269 | ||
e6dbd3b3 | 270 | /* Read a 32-bit immediate constant. */ |
d4d79bb1 | 271 | static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) |
e6dbd3b3 PB |
272 | { |
273 | uint32_t im; | |
d4d79bb1 | 274 | im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16; |
e6dbd3b3 | 275 | s->pc += 2; |
d4d79bb1 | 276 | im |= cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
277 | s->pc += 2; |
278 | return im; | |
279 | } | |
280 | ||
281 | /* Calculate and address index. */ | |
e1f3808e | 282 | static TCGv gen_addr_index(uint16_t ext, TCGv tmp) |
e6dbd3b3 | 283 | { |
e1f3808e | 284 | TCGv add; |
e6dbd3b3 PB |
285 | int scale; |
286 | ||
287 | add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); | |
288 | if ((ext & 0x800) == 0) { | |
e1f3808e | 289 | tcg_gen_ext16s_i32(tmp, add); |
e6dbd3b3 PB |
290 | add = tmp; |
291 | } | |
292 | scale = (ext >> 9) & 3; | |
293 | if (scale != 0) { | |
e1f3808e | 294 | tcg_gen_shli_i32(tmp, add, scale); |
e6dbd3b3 PB |
295 | add = tmp; |
296 | } | |
297 | return add; | |
298 | } | |
299 | ||
e1f3808e PB |
300 | /* Handle a base + index + displacement effective addresss. |
301 | A NULL_QREG base means pc-relative. */ | |
a4356126 | 302 | static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) |
e6e5906b | 303 | { |
e6e5906b PB |
304 | uint32_t offset; |
305 | uint16_t ext; | |
e1f3808e PB |
306 | TCGv add; |
307 | TCGv tmp; | |
e6dbd3b3 | 308 | uint32_t bd, od; |
e6e5906b PB |
309 | |
310 | offset = s->pc; | |
d4d79bb1 | 311 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 312 | s->pc += 2; |
e6dbd3b3 PB |
313 | |
314 | if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) | |
e1f3808e | 315 | return NULL_QREG; |
e6dbd3b3 PB |
316 | |
317 | if (ext & 0x100) { | |
318 | /* full extension word format */ | |
319 | if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) | |
e1f3808e | 320 | return NULL_QREG; |
e6dbd3b3 PB |
321 | |
322 | if ((ext & 0x30) > 0x10) { | |
323 | /* base displacement */ | |
324 | if ((ext & 0x30) == 0x20) { | |
d4d79bb1 | 325 | bd = (int16_t)cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
326 | s->pc += 2; |
327 | } else { | |
d4d79bb1 | 328 | bd = read_im32(env, s); |
e6dbd3b3 PB |
329 | } |
330 | } else { | |
331 | bd = 0; | |
332 | } | |
a7812ae4 | 333 | tmp = tcg_temp_new(); |
e6dbd3b3 PB |
334 | if ((ext & 0x44) == 0) { |
335 | /* pre-index */ | |
336 | add = gen_addr_index(ext, tmp); | |
337 | } else { | |
e1f3808e | 338 | add = NULL_QREG; |
e6dbd3b3 PB |
339 | } |
340 | if ((ext & 0x80) == 0) { | |
341 | /* base not suppressed */ | |
e1f3808e | 342 | if (IS_NULL_QREG(base)) { |
351326a6 | 343 | base = tcg_const_i32(offset + bd); |
e6dbd3b3 PB |
344 | bd = 0; |
345 | } | |
e1f3808e PB |
346 | if (!IS_NULL_QREG(add)) { |
347 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 PB |
348 | add = tmp; |
349 | } else { | |
350 | add = base; | |
351 | } | |
352 | } | |
e1f3808e | 353 | if (!IS_NULL_QREG(add)) { |
e6dbd3b3 | 354 | if (bd != 0) { |
e1f3808e | 355 | tcg_gen_addi_i32(tmp, add, bd); |
e6dbd3b3 PB |
356 | add = tmp; |
357 | } | |
358 | } else { | |
351326a6 | 359 | add = tcg_const_i32(bd); |
e6dbd3b3 PB |
360 | } |
361 | if ((ext & 3) != 0) { | |
362 | /* memory indirect */ | |
363 | base = gen_load(s, OS_LONG, add, 0); | |
364 | if ((ext & 0x44) == 4) { | |
365 | add = gen_addr_index(ext, tmp); | |
e1f3808e | 366 | tcg_gen_add_i32(tmp, add, base); |
e6dbd3b3 PB |
367 | add = tmp; |
368 | } else { | |
369 | add = base; | |
370 | } | |
371 | if ((ext & 3) > 1) { | |
372 | /* outer displacement */ | |
373 | if ((ext & 3) == 2) { | |
d4d79bb1 | 374 | od = (int16_t)cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
375 | s->pc += 2; |
376 | } else { | |
d4d79bb1 | 377 | od = read_im32(env, s); |
e6dbd3b3 PB |
378 | } |
379 | } else { | |
380 | od = 0; | |
381 | } | |
382 | if (od != 0) { | |
e1f3808e | 383 | tcg_gen_addi_i32(tmp, add, od); |
e6dbd3b3 PB |
384 | add = tmp; |
385 | } | |
386 | } | |
e6e5906b | 387 | } else { |
e6dbd3b3 | 388 | /* brief extension word format */ |
a7812ae4 | 389 | tmp = tcg_temp_new(); |
e6dbd3b3 | 390 | add = gen_addr_index(ext, tmp); |
e1f3808e PB |
391 | if (!IS_NULL_QREG(base)) { |
392 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 | 393 | if ((int8_t)ext) |
e1f3808e | 394 | tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); |
e6dbd3b3 | 395 | } else { |
e1f3808e | 396 | tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); |
e6dbd3b3 PB |
397 | } |
398 | add = tmp; | |
e6e5906b | 399 | } |
e6dbd3b3 | 400 | return add; |
e6e5906b PB |
401 | } |
402 | ||
e6e5906b PB |
403 | /* Update the CPU env CC_OP state. */ |
404 | static inline void gen_flush_cc_op(DisasContext *s) | |
405 | { | |
406 | if (s->cc_op != CC_OP_DYNAMIC) | |
e1f3808e | 407 | tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); |
e6e5906b PB |
408 | } |
409 | ||
410 | /* Evaluate all the CC flags. */ | |
411 | static inline void gen_flush_flags(DisasContext *s) | |
412 | { | |
413 | if (s->cc_op == CC_OP_FLAGS) | |
414 | return; | |
0cf5c677 | 415 | gen_flush_cc_op(s); |
e1f3808e | 416 | gen_helper_flush_flags(cpu_env, QREG_CC_OP); |
e6e5906b PB |
417 | s->cc_op = CC_OP_FLAGS; |
418 | } | |
419 | ||
e1f3808e PB |
420 | static void gen_logic_cc(DisasContext *s, TCGv val) |
421 | { | |
422 | tcg_gen_mov_i32(QREG_CC_DEST, val); | |
423 | s->cc_op = CC_OP_LOGIC; | |
424 | } | |
425 | ||
426 | static void gen_update_cc_add(TCGv dest, TCGv src) | |
427 | { | |
428 | tcg_gen_mov_i32(QREG_CC_DEST, dest); | |
429 | tcg_gen_mov_i32(QREG_CC_SRC, src); | |
430 | } | |
431 | ||
e6e5906b PB |
432 | static inline int opsize_bytes(int opsize) |
433 | { | |
434 | switch (opsize) { | |
435 | case OS_BYTE: return 1; | |
436 | case OS_WORD: return 2; | |
437 | case OS_LONG: return 4; | |
438 | case OS_SINGLE: return 4; | |
439 | case OS_DOUBLE: return 8; | |
440 | default: | |
7372c2b9 | 441 | g_assert_not_reached(); |
e6e5906b PB |
442 | } |
443 | } | |
444 | ||
445 | /* Assign value to a register. If the width is less than the register width | |
446 | only the low part of the register is set. */ | |
e1f3808e | 447 | static void gen_partset_reg(int opsize, TCGv reg, TCGv val) |
e6e5906b | 448 | { |
e1f3808e | 449 | TCGv tmp; |
e6e5906b PB |
450 | switch (opsize) { |
451 | case OS_BYTE: | |
e1f3808e | 452 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
a7812ae4 | 453 | tmp = tcg_temp_new(); |
e1f3808e PB |
454 | tcg_gen_ext8u_i32(tmp, val); |
455 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
456 | break; |
457 | case OS_WORD: | |
e1f3808e | 458 | tcg_gen_andi_i32(reg, reg, 0xffff0000); |
a7812ae4 | 459 | tmp = tcg_temp_new(); |
e1f3808e PB |
460 | tcg_gen_ext16u_i32(tmp, val); |
461 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
462 | break; |
463 | case OS_LONG: | |
e6e5906b | 464 | case OS_SINGLE: |
a7812ae4 | 465 | tcg_gen_mov_i32(reg, val); |
e6e5906b PB |
466 | break; |
467 | default: | |
7372c2b9 | 468 | g_assert_not_reached(); |
e6e5906b PB |
469 | } |
470 | } | |
471 | ||
472 | /* Sign or zero extend a value. */ | |
e1f3808e | 473 | static inline TCGv gen_extend(TCGv val, int opsize, int sign) |
e6e5906b | 474 | { |
e1f3808e | 475 | TCGv tmp; |
e6e5906b PB |
476 | |
477 | switch (opsize) { | |
478 | case OS_BYTE: | |
a7812ae4 | 479 | tmp = tcg_temp_new(); |
e6e5906b | 480 | if (sign) |
e1f3808e | 481 | tcg_gen_ext8s_i32(tmp, val); |
e6e5906b | 482 | else |
e1f3808e | 483 | tcg_gen_ext8u_i32(tmp, val); |
e6e5906b PB |
484 | break; |
485 | case OS_WORD: | |
a7812ae4 | 486 | tmp = tcg_temp_new(); |
e6e5906b | 487 | if (sign) |
e1f3808e | 488 | tcg_gen_ext16s_i32(tmp, val); |
e6e5906b | 489 | else |
e1f3808e | 490 | tcg_gen_ext16u_i32(tmp, val); |
e6e5906b PB |
491 | break; |
492 | case OS_LONG: | |
e6e5906b | 493 | case OS_SINGLE: |
a7812ae4 | 494 | tmp = val; |
e6e5906b PB |
495 | break; |
496 | default: | |
7372c2b9 | 497 | g_assert_not_reached(); |
e6e5906b PB |
498 | } |
499 | return tmp; | |
500 | } | |
501 | ||
502 | /* Generate code for an "effective address". Does not adjust the base | |
1addc7c5 | 503 | register for autoincrement addressing modes. */ |
d4d79bb1 BS |
504 | static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
505 | int opsize) | |
e6e5906b | 506 | { |
e1f3808e PB |
507 | TCGv reg; |
508 | TCGv tmp; | |
e6e5906b PB |
509 | uint16_t ext; |
510 | uint32_t offset; | |
511 | ||
e6e5906b PB |
512 | switch ((insn >> 3) & 7) { |
513 | case 0: /* Data register direct. */ | |
514 | case 1: /* Address register direct. */ | |
e1f3808e | 515 | return NULL_QREG; |
e6e5906b PB |
516 | case 2: /* Indirect register */ |
517 | case 3: /* Indirect postincrement. */ | |
e1f3808e | 518 | return AREG(insn, 0); |
e6e5906b | 519 | case 4: /* Indirect predecrememnt. */ |
e1f3808e | 520 | reg = AREG(insn, 0); |
a7812ae4 | 521 | tmp = tcg_temp_new(); |
e1f3808e | 522 | tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); |
e6e5906b PB |
523 | return tmp; |
524 | case 5: /* Indirect displacement. */ | |
e1f3808e | 525 | reg = AREG(insn, 0); |
a7812ae4 | 526 | tmp = tcg_temp_new(); |
d4d79bb1 | 527 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 528 | s->pc += 2; |
e1f3808e | 529 | tcg_gen_addi_i32(tmp, reg, (int16_t)ext); |
e6e5906b PB |
530 | return tmp; |
531 | case 6: /* Indirect index + displacement. */ | |
e1f3808e | 532 | reg = AREG(insn, 0); |
a4356126 | 533 | return gen_lea_indexed(env, s, reg); |
e6e5906b | 534 | case 7: /* Other */ |
e1f3808e | 535 | switch (insn & 7) { |
e6e5906b | 536 | case 0: /* Absolute short. */ |
d4d79bb1 | 537 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b | 538 | s->pc += 2; |
351326a6 | 539 | return tcg_const_i32(offset); |
e6e5906b | 540 | case 1: /* Absolute long. */ |
d4d79bb1 | 541 | offset = read_im32(env, s); |
351326a6 | 542 | return tcg_const_i32(offset); |
e6e5906b | 543 | case 2: /* pc displacement */ |
e6e5906b | 544 | offset = s->pc; |
d4d79bb1 | 545 | offset += cpu_ldsw_code(env, s->pc); |
e6e5906b | 546 | s->pc += 2; |
351326a6 | 547 | return tcg_const_i32(offset); |
e6e5906b | 548 | case 3: /* pc index+displacement. */ |
a4356126 | 549 | return gen_lea_indexed(env, s, NULL_QREG); |
e6e5906b PB |
550 | case 4: /* Immediate. */ |
551 | default: | |
e1f3808e | 552 | return NULL_QREG; |
e6e5906b PB |
553 | } |
554 | } | |
555 | /* Should never happen. */ | |
e1f3808e | 556 | return NULL_QREG; |
e6e5906b PB |
557 | } |
558 | ||
559 | /* Helper function for gen_ea. Reuse the computed address between the | |
560 | for read/write operands. */ | |
d4d79bb1 BS |
561 | static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s, |
562 | uint16_t insn, int opsize, TCGv val, | |
563 | TCGv *addrp, ea_what what) | |
e6e5906b | 564 | { |
e1f3808e | 565 | TCGv tmp; |
e6e5906b | 566 | |
e1f3808e | 567 | if (addrp && what == EA_STORE) { |
e6e5906b PB |
568 | tmp = *addrp; |
569 | } else { | |
d4d79bb1 | 570 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
571 | if (IS_NULL_QREG(tmp)) |
572 | return tmp; | |
e6e5906b PB |
573 | if (addrp) |
574 | *addrp = tmp; | |
575 | } | |
e1f3808e | 576 | return gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
577 | } |
578 | ||
f38f7a84 | 579 | /* Generate code to load/store a value from/into an EA. If VAL > 0 this is |
e6e5906b PB |
580 | a write otherwise it is a read (0 == sign extend, -1 == zero extend). |
581 | ADDRP is non-null for readwrite operands. */ | |
d4d79bb1 BS |
582 | static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
583 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
e6e5906b | 584 | { |
e1f3808e PB |
585 | TCGv reg; |
586 | TCGv result; | |
e6e5906b PB |
587 | uint32_t offset; |
588 | ||
e6e5906b PB |
589 | switch ((insn >> 3) & 7) { |
590 | case 0: /* Data register direct. */ | |
e1f3808e PB |
591 | reg = DREG(insn, 0); |
592 | if (what == EA_STORE) { | |
e6e5906b | 593 | gen_partset_reg(opsize, reg, val); |
e1f3808e | 594 | return store_dummy; |
e6e5906b | 595 | } else { |
e1f3808e | 596 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
597 | } |
598 | case 1: /* Address register direct. */ | |
e1f3808e PB |
599 | reg = AREG(insn, 0); |
600 | if (what == EA_STORE) { | |
601 | tcg_gen_mov_i32(reg, val); | |
602 | return store_dummy; | |
e6e5906b | 603 | } else { |
e1f3808e | 604 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
605 | } |
606 | case 2: /* Indirect register */ | |
e1f3808e PB |
607 | reg = AREG(insn, 0); |
608 | return gen_ldst(s, opsize, reg, val, what); | |
e6e5906b | 609 | case 3: /* Indirect postincrement. */ |
e1f3808e PB |
610 | reg = AREG(insn, 0); |
611 | result = gen_ldst(s, opsize, reg, val, what); | |
e6e5906b PB |
612 | /* ??? This is not exception safe. The instruction may still |
613 | fault after this point. */ | |
e1f3808e PB |
614 | if (what == EA_STORE || !addrp) |
615 | tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize)); | |
e6e5906b PB |
616 | return result; |
617 | case 4: /* Indirect predecrememnt. */ | |
618 | { | |
e1f3808e PB |
619 | TCGv tmp; |
620 | if (addrp && what == EA_STORE) { | |
e6e5906b PB |
621 | tmp = *addrp; |
622 | } else { | |
d4d79bb1 | 623 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
624 | if (IS_NULL_QREG(tmp)) |
625 | return tmp; | |
e6e5906b PB |
626 | if (addrp) |
627 | *addrp = tmp; | |
628 | } | |
e1f3808e | 629 | result = gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
630 | /* ??? This is not exception safe. The instruction may still |
631 | fault after this point. */ | |
e1f3808e PB |
632 | if (what == EA_STORE || !addrp) { |
633 | reg = AREG(insn, 0); | |
634 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
635 | } |
636 | } | |
637 | return result; | |
638 | case 5: /* Indirect displacement. */ | |
639 | case 6: /* Indirect index + displacement. */ | |
d4d79bb1 | 640 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b | 641 | case 7: /* Other */ |
e1f3808e | 642 | switch (insn & 7) { |
e6e5906b PB |
643 | case 0: /* Absolute short. */ |
644 | case 1: /* Absolute long. */ | |
645 | case 2: /* pc displacement */ | |
646 | case 3: /* pc index+displacement. */ | |
d4d79bb1 | 647 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b PB |
648 | case 4: /* Immediate. */ |
649 | /* Sign extend values for consistency. */ | |
650 | switch (opsize) { | |
651 | case OS_BYTE: | |
31871141 | 652 | if (what == EA_LOADS) { |
d4d79bb1 | 653 | offset = cpu_ldsb_code(env, s->pc + 1); |
31871141 | 654 | } else { |
d4d79bb1 | 655 | offset = cpu_ldub_code(env, s->pc + 1); |
31871141 | 656 | } |
e6e5906b PB |
657 | s->pc += 2; |
658 | break; | |
659 | case OS_WORD: | |
31871141 | 660 | if (what == EA_LOADS) { |
d4d79bb1 | 661 | offset = cpu_ldsw_code(env, s->pc); |
31871141 | 662 | } else { |
d4d79bb1 | 663 | offset = cpu_lduw_code(env, s->pc); |
31871141 | 664 | } |
e6e5906b PB |
665 | s->pc += 2; |
666 | break; | |
667 | case OS_LONG: | |
d4d79bb1 | 668 | offset = read_im32(env, s); |
e6e5906b PB |
669 | break; |
670 | default: | |
7372c2b9 | 671 | g_assert_not_reached(); |
e6e5906b | 672 | } |
e1f3808e | 673 | return tcg_const_i32(offset); |
e6e5906b | 674 | default: |
e1f3808e | 675 | return NULL_QREG; |
e6e5906b PB |
676 | } |
677 | } | |
678 | /* Should never happen. */ | |
e1f3808e | 679 | return NULL_QREG; |
e6e5906b PB |
680 | } |
681 | ||
e1f3808e | 682 | /* This generates a conditional branch, clobbering all temporaries. */ |
42a268c2 | 683 | static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) |
e6e5906b | 684 | { |
e1f3808e | 685 | TCGv tmp; |
e6e5906b | 686 | |
e1f3808e PB |
687 | /* TODO: Optimize compare/branch pairs rather than always flushing |
688 | flag state to CC_OP_FLAGS. */ | |
e6e5906b PB |
689 | gen_flush_flags(s); |
690 | switch (cond) { | |
691 | case 0: /* T */ | |
e1f3808e | 692 | tcg_gen_br(l1); |
e6e5906b PB |
693 | break; |
694 | case 1: /* F */ | |
695 | break; | |
696 | case 2: /* HI (!C && !Z) */ | |
a7812ae4 | 697 | tmp = tcg_temp_new(); |
e1f3808e PB |
698 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
699 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
700 | break; |
701 | case 3: /* LS (C || Z) */ | |
a7812ae4 | 702 | tmp = tcg_temp_new(); |
e1f3808e PB |
703 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
704 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
705 | break; |
706 | case 4: /* CC (!C) */ | |
a7812ae4 | 707 | tmp = tcg_temp_new(); |
e1f3808e PB |
708 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
709 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
710 | break; |
711 | case 5: /* CS (C) */ | |
a7812ae4 | 712 | tmp = tcg_temp_new(); |
e1f3808e PB |
713 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
714 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
715 | break; |
716 | case 6: /* NE (!Z) */ | |
a7812ae4 | 717 | tmp = tcg_temp_new(); |
e1f3808e PB |
718 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
719 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
720 | break; |
721 | case 7: /* EQ (Z) */ | |
a7812ae4 | 722 | tmp = tcg_temp_new(); |
e1f3808e PB |
723 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
724 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
725 | break; |
726 | case 8: /* VC (!V) */ | |
a7812ae4 | 727 | tmp = tcg_temp_new(); |
e1f3808e PB |
728 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
729 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
730 | break; |
731 | case 9: /* VS (V) */ | |
a7812ae4 | 732 | tmp = tcg_temp_new(); |
e1f3808e PB |
733 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
734 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
735 | break; |
736 | case 10: /* PL (!N) */ | |
a7812ae4 | 737 | tmp = tcg_temp_new(); |
e1f3808e PB |
738 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
739 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
740 | break; |
741 | case 11: /* MI (N) */ | |
a7812ae4 | 742 | tmp = tcg_temp_new(); |
e1f3808e PB |
743 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
744 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
745 | break; |
746 | case 12: /* GE (!(N ^ V)) */ | |
a7812ae4 | 747 | tmp = tcg_temp_new(); |
e1f3808e PB |
748 | assert(CCF_V == (CCF_N >> 2)); |
749 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
750 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
751 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
752 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
753 | break; |
754 | case 13: /* LT (N ^ V) */ | |
a7812ae4 | 755 | tmp = tcg_temp_new(); |
e1f3808e PB |
756 | assert(CCF_V == (CCF_N >> 2)); |
757 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
758 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
759 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
760 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
761 | break; |
762 | case 14: /* GT (!(Z || (N ^ V))) */ | |
a7812ae4 | 763 | tmp = tcg_temp_new(); |
e1f3808e PB |
764 | assert(CCF_V == (CCF_N >> 2)); |
765 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
766 | tcg_gen_shri_i32(tmp, tmp, 2); | |
767 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
768 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
769 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
770 | break; |
771 | case 15: /* LE (Z || (N ^ V)) */ | |
a7812ae4 | 772 | tmp = tcg_temp_new(); |
e1f3808e PB |
773 | assert(CCF_V == (CCF_N >> 2)); |
774 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
775 | tcg_gen_shri_i32(tmp, tmp, 2); | |
776 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
777 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
778 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
779 | break; |
780 | default: | |
781 | /* Should ever happen. */ | |
782 | abort(); | |
783 | } | |
784 | } | |
785 | ||
786 | DISAS_INSN(scc) | |
787 | { | |
42a268c2 | 788 | TCGLabel *l1; |
e6e5906b | 789 | int cond; |
e1f3808e | 790 | TCGv reg; |
e6e5906b PB |
791 | |
792 | l1 = gen_new_label(); | |
793 | cond = (insn >> 8) & 0xf; | |
794 | reg = DREG(insn, 0); | |
e1f3808e PB |
795 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
796 | /* This is safe because we modify the reg directly, with no other values | |
797 | live. */ | |
e6e5906b | 798 | gen_jmpcc(s, cond ^ 1, l1); |
e1f3808e | 799 | tcg_gen_ori_i32(reg, reg, 0xff); |
e6e5906b PB |
800 | gen_set_label(l1); |
801 | } | |
802 | ||
0633879f PB |
803 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
804 | static void gen_lookup_tb(DisasContext *s) | |
805 | { | |
806 | gen_flush_cc_op(s); | |
e1f3808e | 807 | tcg_gen_movi_i32(QREG_PC, s->pc); |
0633879f PB |
808 | s->is_jmp = DISAS_UPDATE; |
809 | } | |
810 | ||
e1f3808e PB |
811 | /* Generate a jump to an immediate address. */ |
812 | static void gen_jmp_im(DisasContext *s, uint32_t dest) | |
813 | { | |
814 | gen_flush_cc_op(s); | |
815 | tcg_gen_movi_i32(QREG_PC, dest); | |
816 | s->is_jmp = DISAS_JUMP; | |
817 | } | |
818 | ||
819 | /* Generate a jump to the address in qreg DEST. */ | |
820 | static void gen_jmp(DisasContext *s, TCGv dest) | |
e6e5906b PB |
821 | { |
822 | gen_flush_cc_op(s); | |
e1f3808e | 823 | tcg_gen_mov_i32(QREG_PC, dest); |
e6e5906b PB |
824 | s->is_jmp = DISAS_JUMP; |
825 | } | |
826 | ||
827 | static void gen_exception(DisasContext *s, uint32_t where, int nr) | |
828 | { | |
829 | gen_flush_cc_op(s); | |
e1f3808e | 830 | gen_jmp_im(s, where); |
31871141 | 831 | gen_helper_raise_exception(cpu_env, tcg_const_i32(nr)); |
e6e5906b PB |
832 | } |
833 | ||
510ff0b7 PB |
834 | static inline void gen_addr_fault(DisasContext *s) |
835 | { | |
836 | gen_exception(s, s->insn_pc, EXCP_ADDRESS); | |
837 | } | |
838 | ||
d4d79bb1 BS |
839 | #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ |
840 | result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ | |
841 | op_sign ? EA_LOADS : EA_LOADU); \ | |
842 | if (IS_NULL_QREG(result)) { \ | |
843 | gen_addr_fault(s); \ | |
844 | return; \ | |
845 | } \ | |
510ff0b7 PB |
846 | } while (0) |
847 | ||
d4d79bb1 BS |
848 | #define DEST_EA(env, insn, opsize, val, addrp) do { \ |
849 | TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ | |
850 | if (IS_NULL_QREG(ea_result)) { \ | |
851 | gen_addr_fault(s); \ | |
852 | return; \ | |
853 | } \ | |
510ff0b7 PB |
854 | } while (0) |
855 | ||
90aa39a1 SF |
856 | static inline bool use_goto_tb(DisasContext *s, uint32_t dest) |
857 | { | |
858 | #ifndef CONFIG_USER_ONLY | |
859 | return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || | |
860 | (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
861 | #else | |
862 | return true; | |
863 | #endif | |
864 | } | |
865 | ||
e6e5906b PB |
866 | /* Generate a jump to an immediate address. */ |
867 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | |
868 | { | |
551bd27f | 869 | if (unlikely(s->singlestep_enabled)) { |
e6e5906b | 870 | gen_exception(s, dest, EXCP_DEBUG); |
90aa39a1 | 871 | } else if (use_goto_tb(s, dest)) { |
57fec1fe | 872 | tcg_gen_goto_tb(n); |
e1f3808e | 873 | tcg_gen_movi_i32(QREG_PC, dest); |
90aa39a1 | 874 | tcg_gen_exit_tb((uintptr_t)s->tb + n); |
e6e5906b | 875 | } else { |
e1f3808e | 876 | gen_jmp_im(s, dest); |
57fec1fe | 877 | tcg_gen_exit_tb(0); |
e6e5906b PB |
878 | } |
879 | s->is_jmp = DISAS_TB_JUMP; | |
880 | } | |
881 | ||
882 | DISAS_INSN(undef_mac) | |
883 | { | |
884 | gen_exception(s, s->pc - 2, EXCP_LINEA); | |
885 | } | |
886 | ||
887 | DISAS_INSN(undef_fpu) | |
888 | { | |
889 | gen_exception(s, s->pc - 2, EXCP_LINEF); | |
890 | } | |
891 | ||
892 | DISAS_INSN(undef) | |
893 | { | |
a47dddd7 AF |
894 | M68kCPU *cpu = m68k_env_get_cpu(env); |
895 | ||
e6e5906b | 896 | gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); |
a47dddd7 | 897 | cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); |
e6e5906b PB |
898 | } |
899 | ||
900 | DISAS_INSN(mulw) | |
901 | { | |
e1f3808e PB |
902 | TCGv reg; |
903 | TCGv tmp; | |
904 | TCGv src; | |
e6e5906b PB |
905 | int sign; |
906 | ||
907 | sign = (insn & 0x100) != 0; | |
908 | reg = DREG(insn, 9); | |
a7812ae4 | 909 | tmp = tcg_temp_new(); |
e6e5906b | 910 | if (sign) |
e1f3808e | 911 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 912 | else |
e1f3808e | 913 | tcg_gen_ext16u_i32(tmp, reg); |
d4d79bb1 | 914 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e PB |
915 | tcg_gen_mul_i32(tmp, tmp, src); |
916 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
917 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
918 | gen_logic_cc(s, tmp); | |
919 | } | |
920 | ||
921 | DISAS_INSN(divw) | |
922 | { | |
e1f3808e PB |
923 | TCGv reg; |
924 | TCGv tmp; | |
925 | TCGv src; | |
e6e5906b PB |
926 | int sign; |
927 | ||
928 | sign = (insn & 0x100) != 0; | |
929 | reg = DREG(insn, 9); | |
930 | if (sign) { | |
e1f3808e | 931 | tcg_gen_ext16s_i32(QREG_DIV1, reg); |
e6e5906b | 932 | } else { |
e1f3808e | 933 | tcg_gen_ext16u_i32(QREG_DIV1, reg); |
e6e5906b | 934 | } |
d4d79bb1 | 935 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e | 936 | tcg_gen_mov_i32(QREG_DIV2, src); |
e6e5906b | 937 | if (sign) { |
e1f3808e | 938 | gen_helper_divs(cpu_env, tcg_const_i32(1)); |
e6e5906b | 939 | } else { |
e1f3808e | 940 | gen_helper_divu(cpu_env, tcg_const_i32(1)); |
e6e5906b PB |
941 | } |
942 | ||
a7812ae4 PB |
943 | tmp = tcg_temp_new(); |
944 | src = tcg_temp_new(); | |
e1f3808e PB |
945 | tcg_gen_ext16u_i32(tmp, QREG_DIV1); |
946 | tcg_gen_shli_i32(src, QREG_DIV2, 16); | |
947 | tcg_gen_or_i32(reg, tmp, src); | |
e6e5906b PB |
948 | s->cc_op = CC_OP_FLAGS; |
949 | } | |
950 | ||
951 | DISAS_INSN(divl) | |
952 | { | |
e1f3808e PB |
953 | TCGv num; |
954 | TCGv den; | |
955 | TCGv reg; | |
e6e5906b PB |
956 | uint16_t ext; |
957 | ||
d4d79bb1 | 958 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
959 | s->pc += 2; |
960 | if (ext & 0x87f8) { | |
961 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
962 | return; | |
963 | } | |
964 | num = DREG(ext, 12); | |
965 | reg = DREG(ext, 0); | |
e1f3808e | 966 | tcg_gen_mov_i32(QREG_DIV1, num); |
d4d79bb1 | 967 | SRC_EA(env, den, OS_LONG, 0, NULL); |
e1f3808e | 968 | tcg_gen_mov_i32(QREG_DIV2, den); |
e6e5906b | 969 | if (ext & 0x0800) { |
e1f3808e | 970 | gen_helper_divs(cpu_env, tcg_const_i32(0)); |
e6e5906b | 971 | } else { |
e1f3808e | 972 | gen_helper_divu(cpu_env, tcg_const_i32(0)); |
e6e5906b | 973 | } |
e1f3808e | 974 | if ((ext & 7) == ((ext >> 12) & 7)) { |
e6e5906b | 975 | /* div */ |
e1f3808e | 976 | tcg_gen_mov_i32 (reg, QREG_DIV1); |
e6e5906b PB |
977 | } else { |
978 | /* rem */ | |
e1f3808e | 979 | tcg_gen_mov_i32 (reg, QREG_DIV2); |
e6e5906b | 980 | } |
e6e5906b PB |
981 | s->cc_op = CC_OP_FLAGS; |
982 | } | |
983 | ||
984 | DISAS_INSN(addsub) | |
985 | { | |
e1f3808e PB |
986 | TCGv reg; |
987 | TCGv dest; | |
988 | TCGv src; | |
989 | TCGv tmp; | |
990 | TCGv addr; | |
e6e5906b PB |
991 | int add; |
992 | ||
993 | add = (insn & 0x4000) != 0; | |
994 | reg = DREG(insn, 9); | |
a7812ae4 | 995 | dest = tcg_temp_new(); |
e6e5906b | 996 | if (insn & 0x100) { |
d4d79bb1 | 997 | SRC_EA(env, tmp, OS_LONG, 0, &addr); |
e6e5906b PB |
998 | src = reg; |
999 | } else { | |
1000 | tmp = reg; | |
d4d79bb1 | 1001 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b PB |
1002 | } |
1003 | if (add) { | |
e1f3808e PB |
1004 | tcg_gen_add_i32(dest, tmp, src); |
1005 | gen_helper_xflag_lt(QREG_CC_X, dest, src); | |
e6e5906b PB |
1006 | s->cc_op = CC_OP_ADD; |
1007 | } else { | |
e1f3808e PB |
1008 | gen_helper_xflag_lt(QREG_CC_X, tmp, src); |
1009 | tcg_gen_sub_i32(dest, tmp, src); | |
e6e5906b PB |
1010 | s->cc_op = CC_OP_SUB; |
1011 | } | |
e1f3808e | 1012 | gen_update_cc_add(dest, src); |
e6e5906b | 1013 | if (insn & 0x100) { |
d4d79bb1 | 1014 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1015 | } else { |
e1f3808e | 1016 | tcg_gen_mov_i32(reg, dest); |
e6e5906b PB |
1017 | } |
1018 | } | |
1019 | ||
1020 | ||
1021 | /* Reverse the order of the bits in REG. */ | |
1022 | DISAS_INSN(bitrev) | |
1023 | { | |
e1f3808e | 1024 | TCGv reg; |
e6e5906b | 1025 | reg = DREG(insn, 0); |
e1f3808e | 1026 | gen_helper_bitrev(reg, reg); |
e6e5906b PB |
1027 | } |
1028 | ||
1029 | DISAS_INSN(bitop_reg) | |
1030 | { | |
1031 | int opsize; | |
1032 | int op; | |
e1f3808e PB |
1033 | TCGv src1; |
1034 | TCGv src2; | |
1035 | TCGv tmp; | |
1036 | TCGv addr; | |
1037 | TCGv dest; | |
e6e5906b PB |
1038 | |
1039 | if ((insn & 0x38) != 0) | |
1040 | opsize = OS_BYTE; | |
1041 | else | |
1042 | opsize = OS_LONG; | |
1043 | op = (insn >> 6) & 3; | |
d4d79bb1 | 1044 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1045 | src2 = DREG(insn, 9); |
a7812ae4 | 1046 | dest = tcg_temp_new(); |
e6e5906b PB |
1047 | |
1048 | gen_flush_flags(s); | |
a7812ae4 | 1049 | tmp = tcg_temp_new(); |
e6e5906b | 1050 | if (opsize == OS_BYTE) |
e1f3808e | 1051 | tcg_gen_andi_i32(tmp, src2, 7); |
e6e5906b | 1052 | else |
e1f3808e | 1053 | tcg_gen_andi_i32(tmp, src2, 31); |
e6e5906b | 1054 | src2 = tmp; |
a7812ae4 | 1055 | tmp = tcg_temp_new(); |
e1f3808e PB |
1056 | tcg_gen_shr_i32(tmp, src1, src2); |
1057 | tcg_gen_andi_i32(tmp, tmp, 1); | |
1058 | tcg_gen_shli_i32(tmp, tmp, 2); | |
1059 | /* Clear CCF_Z if bit set. */ | |
1060 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1061 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1062 | ||
1063 | tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2); | |
e6e5906b PB |
1064 | switch (op) { |
1065 | case 1: /* bchg */ | |
e1f3808e | 1066 | tcg_gen_xor_i32(dest, src1, tmp); |
e6e5906b PB |
1067 | break; |
1068 | case 2: /* bclr */ | |
e1f3808e PB |
1069 | tcg_gen_not_i32(tmp, tmp); |
1070 | tcg_gen_and_i32(dest, src1, tmp); | |
e6e5906b PB |
1071 | break; |
1072 | case 3: /* bset */ | |
e1f3808e | 1073 | tcg_gen_or_i32(dest, src1, tmp); |
e6e5906b PB |
1074 | break; |
1075 | default: /* btst */ | |
1076 | break; | |
1077 | } | |
1078 | if (op) | |
d4d79bb1 | 1079 | DEST_EA(env, insn, opsize, dest, &addr); |
e6e5906b PB |
1080 | } |
1081 | ||
1082 | DISAS_INSN(sats) | |
1083 | { | |
e1f3808e | 1084 | TCGv reg; |
e6e5906b | 1085 | reg = DREG(insn, 0); |
e6e5906b | 1086 | gen_flush_flags(s); |
e1f3808e PB |
1087 | gen_helper_sats(reg, reg, QREG_CC_DEST); |
1088 | gen_logic_cc(s, reg); | |
e6e5906b PB |
1089 | } |
1090 | ||
e1f3808e | 1091 | static void gen_push(DisasContext *s, TCGv val) |
e6e5906b | 1092 | { |
e1f3808e | 1093 | TCGv tmp; |
e6e5906b | 1094 | |
a7812ae4 | 1095 | tmp = tcg_temp_new(); |
e1f3808e | 1096 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1097 | gen_store(s, OS_LONG, tmp, val); |
e1f3808e | 1098 | tcg_gen_mov_i32(QREG_SP, tmp); |
e6e5906b PB |
1099 | } |
1100 | ||
1101 | DISAS_INSN(movem) | |
1102 | { | |
e1f3808e | 1103 | TCGv addr; |
e6e5906b PB |
1104 | int i; |
1105 | uint16_t mask; | |
e1f3808e PB |
1106 | TCGv reg; |
1107 | TCGv tmp; | |
e6e5906b PB |
1108 | int is_load; |
1109 | ||
d4d79bb1 | 1110 | mask = cpu_lduw_code(env, s->pc); |
e6e5906b | 1111 | s->pc += 2; |
d4d79bb1 | 1112 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1113 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1114 | gen_addr_fault(s); |
1115 | return; | |
1116 | } | |
a7812ae4 | 1117 | addr = tcg_temp_new(); |
e1f3808e | 1118 | tcg_gen_mov_i32(addr, tmp); |
e6e5906b PB |
1119 | is_load = ((insn & 0x0400) != 0); |
1120 | for (i = 0; i < 16; i++, mask >>= 1) { | |
1121 | if (mask & 1) { | |
1122 | if (i < 8) | |
1123 | reg = DREG(i, 0); | |
1124 | else | |
1125 | reg = AREG(i, 0); | |
1126 | if (is_load) { | |
0633879f | 1127 | tmp = gen_load(s, OS_LONG, addr, 0); |
e1f3808e | 1128 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b | 1129 | } else { |
0633879f | 1130 | gen_store(s, OS_LONG, addr, reg); |
e6e5906b PB |
1131 | } |
1132 | if (mask != 1) | |
e1f3808e | 1133 | tcg_gen_addi_i32(addr, addr, 4); |
e6e5906b PB |
1134 | } |
1135 | } | |
1136 | } | |
1137 | ||
1138 | DISAS_INSN(bitop_im) | |
1139 | { | |
1140 | int opsize; | |
1141 | int op; | |
e1f3808e | 1142 | TCGv src1; |
e6e5906b PB |
1143 | uint32_t mask; |
1144 | int bitnum; | |
e1f3808e PB |
1145 | TCGv tmp; |
1146 | TCGv addr; | |
e6e5906b PB |
1147 | |
1148 | if ((insn & 0x38) != 0) | |
1149 | opsize = OS_BYTE; | |
1150 | else | |
1151 | opsize = OS_LONG; | |
1152 | op = (insn >> 6) & 3; | |
1153 | ||
d4d79bb1 | 1154 | bitnum = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
1155 | s->pc += 2; |
1156 | if (bitnum & 0xff00) { | |
d4d79bb1 | 1157 | disas_undef(env, s, insn); |
e6e5906b PB |
1158 | return; |
1159 | } | |
1160 | ||
d4d79bb1 | 1161 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b PB |
1162 | |
1163 | gen_flush_flags(s); | |
e6e5906b PB |
1164 | if (opsize == OS_BYTE) |
1165 | bitnum &= 7; | |
1166 | else | |
1167 | bitnum &= 31; | |
1168 | mask = 1 << bitnum; | |
1169 | ||
a7812ae4 | 1170 | tmp = tcg_temp_new(); |
e1f3808e PB |
1171 | assert (CCF_Z == (1 << 2)); |
1172 | if (bitnum > 2) | |
1173 | tcg_gen_shri_i32(tmp, src1, bitnum - 2); | |
1174 | else if (bitnum < 2) | |
1175 | tcg_gen_shli_i32(tmp, src1, 2 - bitnum); | |
e6e5906b | 1176 | else |
e1f3808e PB |
1177 | tcg_gen_mov_i32(tmp, src1); |
1178 | tcg_gen_andi_i32(tmp, tmp, CCF_Z); | |
1179 | /* Clear CCF_Z if bit set. */ | |
1180 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1181 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1182 | if (op) { | |
1183 | switch (op) { | |
1184 | case 1: /* bchg */ | |
1185 | tcg_gen_xori_i32(tmp, src1, mask); | |
1186 | break; | |
1187 | case 2: /* bclr */ | |
1188 | tcg_gen_andi_i32(tmp, src1, ~mask); | |
1189 | break; | |
1190 | case 3: /* bset */ | |
1191 | tcg_gen_ori_i32(tmp, src1, mask); | |
1192 | break; | |
1193 | default: /* btst */ | |
1194 | break; | |
1195 | } | |
d4d79bb1 | 1196 | DEST_EA(env, insn, opsize, tmp, &addr); |
e6e5906b | 1197 | } |
e6e5906b PB |
1198 | } |
1199 | ||
1200 | DISAS_INSN(arith_im) | |
1201 | { | |
1202 | int op; | |
e1f3808e PB |
1203 | uint32_t im; |
1204 | TCGv src1; | |
1205 | TCGv dest; | |
1206 | TCGv addr; | |
e6e5906b PB |
1207 | |
1208 | op = (insn >> 9) & 7; | |
d4d79bb1 BS |
1209 | SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr); |
1210 | im = read_im32(env, s); | |
a7812ae4 | 1211 | dest = tcg_temp_new(); |
e6e5906b PB |
1212 | switch (op) { |
1213 | case 0: /* ori */ | |
e1f3808e | 1214 | tcg_gen_ori_i32(dest, src1, im); |
e6e5906b PB |
1215 | gen_logic_cc(s, dest); |
1216 | break; | |
1217 | case 1: /* andi */ | |
e1f3808e | 1218 | tcg_gen_andi_i32(dest, src1, im); |
e6e5906b PB |
1219 | gen_logic_cc(s, dest); |
1220 | break; | |
1221 | case 2: /* subi */ | |
e1f3808e | 1222 | tcg_gen_mov_i32(dest, src1); |
351326a6 | 1223 | gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); |
e1f3808e | 1224 | tcg_gen_subi_i32(dest, dest, im); |
351326a6 | 1225 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1226 | s->cc_op = CC_OP_SUB; |
1227 | break; | |
1228 | case 3: /* addi */ | |
e1f3808e PB |
1229 | tcg_gen_mov_i32(dest, src1); |
1230 | tcg_gen_addi_i32(dest, dest, im); | |
351326a6 LV |
1231 | gen_update_cc_add(dest, tcg_const_i32(im)); |
1232 | gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); | |
e6e5906b PB |
1233 | s->cc_op = CC_OP_ADD; |
1234 | break; | |
1235 | case 5: /* eori */ | |
e1f3808e | 1236 | tcg_gen_xori_i32(dest, src1, im); |
e6e5906b PB |
1237 | gen_logic_cc(s, dest); |
1238 | break; | |
1239 | case 6: /* cmpi */ | |
e1f3808e PB |
1240 | tcg_gen_mov_i32(dest, src1); |
1241 | tcg_gen_subi_i32(dest, dest, im); | |
351326a6 | 1242 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1243 | s->cc_op = CC_OP_SUB; |
1244 | break; | |
1245 | default: | |
1246 | abort(); | |
1247 | } | |
1248 | if (op != 6) { | |
d4d79bb1 | 1249 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1250 | } |
1251 | } | |
1252 | ||
1253 | DISAS_INSN(byterev) | |
1254 | { | |
e1f3808e | 1255 | TCGv reg; |
e6e5906b PB |
1256 | |
1257 | reg = DREG(insn, 0); | |
66896cb8 | 1258 | tcg_gen_bswap32_i32(reg, reg); |
e6e5906b PB |
1259 | } |
1260 | ||
1261 | DISAS_INSN(move) | |
1262 | { | |
e1f3808e PB |
1263 | TCGv src; |
1264 | TCGv dest; | |
e6e5906b PB |
1265 | int op; |
1266 | int opsize; | |
1267 | ||
1268 | switch (insn >> 12) { | |
1269 | case 1: /* move.b */ | |
1270 | opsize = OS_BYTE; | |
1271 | break; | |
1272 | case 2: /* move.l */ | |
1273 | opsize = OS_LONG; | |
1274 | break; | |
1275 | case 3: /* move.w */ | |
1276 | opsize = OS_WORD; | |
1277 | break; | |
1278 | default: | |
1279 | abort(); | |
1280 | } | |
d4d79bb1 | 1281 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b PB |
1282 | op = (insn >> 6) & 7; |
1283 | if (op == 1) { | |
1284 | /* movea */ | |
1285 | /* The value will already have been sign extended. */ | |
1286 | dest = AREG(insn, 9); | |
e1f3808e | 1287 | tcg_gen_mov_i32(dest, src); |
e6e5906b PB |
1288 | } else { |
1289 | /* normal move */ | |
1290 | uint16_t dest_ea; | |
1291 | dest_ea = ((insn >> 9) & 7) | (op << 3); | |
d4d79bb1 | 1292 | DEST_EA(env, dest_ea, opsize, src, NULL); |
e6e5906b PB |
1293 | /* This will be correct because loads sign extend. */ |
1294 | gen_logic_cc(s, src); | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | DISAS_INSN(negx) | |
1299 | { | |
e1f3808e | 1300 | TCGv reg; |
e6e5906b PB |
1301 | |
1302 | gen_flush_flags(s); | |
1303 | reg = DREG(insn, 0); | |
e1f3808e | 1304 | gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg); |
e6e5906b PB |
1305 | } |
1306 | ||
1307 | DISAS_INSN(lea) | |
1308 | { | |
e1f3808e PB |
1309 | TCGv reg; |
1310 | TCGv tmp; | |
e6e5906b PB |
1311 | |
1312 | reg = AREG(insn, 9); | |
d4d79bb1 | 1313 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1314 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1315 | gen_addr_fault(s); |
1316 | return; | |
1317 | } | |
e1f3808e | 1318 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1319 | } |
1320 | ||
1321 | DISAS_INSN(clr) | |
1322 | { | |
1323 | int opsize; | |
1324 | ||
1325 | switch ((insn >> 6) & 3) { | |
1326 | case 0: /* clr.b */ | |
1327 | opsize = OS_BYTE; | |
1328 | break; | |
1329 | case 1: /* clr.w */ | |
1330 | opsize = OS_WORD; | |
1331 | break; | |
1332 | case 2: /* clr.l */ | |
1333 | opsize = OS_LONG; | |
1334 | break; | |
1335 | default: | |
1336 | abort(); | |
1337 | } | |
d4d79bb1 | 1338 | DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL); |
351326a6 | 1339 | gen_logic_cc(s, tcg_const_i32(0)); |
e6e5906b PB |
1340 | } |
1341 | ||
e1f3808e | 1342 | static TCGv gen_get_ccr(DisasContext *s) |
e6e5906b | 1343 | { |
e1f3808e | 1344 | TCGv dest; |
e6e5906b PB |
1345 | |
1346 | gen_flush_flags(s); | |
a7812ae4 | 1347 | dest = tcg_temp_new(); |
e1f3808e PB |
1348 | tcg_gen_shli_i32(dest, QREG_CC_X, 4); |
1349 | tcg_gen_or_i32(dest, dest, QREG_CC_DEST); | |
0633879f PB |
1350 | return dest; |
1351 | } | |
1352 | ||
1353 | DISAS_INSN(move_from_ccr) | |
1354 | { | |
e1f3808e PB |
1355 | TCGv reg; |
1356 | TCGv ccr; | |
0633879f PB |
1357 | |
1358 | ccr = gen_get_ccr(s); | |
e6e5906b | 1359 | reg = DREG(insn, 0); |
0633879f | 1360 | gen_partset_reg(OS_WORD, reg, ccr); |
e6e5906b PB |
1361 | } |
1362 | ||
1363 | DISAS_INSN(neg) | |
1364 | { | |
e1f3808e PB |
1365 | TCGv reg; |
1366 | TCGv src1; | |
e6e5906b PB |
1367 | |
1368 | reg = DREG(insn, 0); | |
a7812ae4 | 1369 | src1 = tcg_temp_new(); |
e1f3808e PB |
1370 | tcg_gen_mov_i32(src1, reg); |
1371 | tcg_gen_neg_i32(reg, src1); | |
e6e5906b | 1372 | s->cc_op = CC_OP_SUB; |
e1f3808e PB |
1373 | gen_update_cc_add(reg, src1); |
1374 | gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1); | |
e6e5906b PB |
1375 | s->cc_op = CC_OP_SUB; |
1376 | } | |
1377 | ||
0633879f PB |
1378 | static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) |
1379 | { | |
e1f3808e PB |
1380 | tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf); |
1381 | tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4); | |
0633879f | 1382 | if (!ccr_only) { |
e1f3808e | 1383 | gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00)); |
0633879f PB |
1384 | } |
1385 | } | |
1386 | ||
d4d79bb1 BS |
1387 | static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, |
1388 | int ccr_only) | |
e6e5906b | 1389 | { |
e1f3808e PB |
1390 | TCGv tmp; |
1391 | TCGv reg; | |
e6e5906b PB |
1392 | |
1393 | s->cc_op = CC_OP_FLAGS; | |
1394 | if ((insn & 0x38) == 0) | |
1395 | { | |
a7812ae4 | 1396 | tmp = tcg_temp_new(); |
e6e5906b | 1397 | reg = DREG(insn, 0); |
e1f3808e PB |
1398 | tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf); |
1399 | tcg_gen_shri_i32(tmp, reg, 4); | |
1400 | tcg_gen_andi_i32(QREG_CC_X, tmp, 1); | |
0633879f | 1401 | if (!ccr_only) { |
e1f3808e | 1402 | gen_helper_set_sr(cpu_env, reg); |
0633879f | 1403 | } |
e6e5906b | 1404 | } |
0633879f | 1405 | else if ((insn & 0x3f) == 0x3c) |
e6e5906b | 1406 | { |
0633879f | 1407 | uint16_t val; |
d4d79bb1 | 1408 | val = cpu_lduw_code(env, s->pc); |
e6e5906b | 1409 | s->pc += 2; |
0633879f | 1410 | gen_set_sr_im(s, val, ccr_only); |
e6e5906b PB |
1411 | } |
1412 | else | |
d4d79bb1 | 1413 | disas_undef(env, s, insn); |
e6e5906b PB |
1414 | } |
1415 | ||
0633879f PB |
1416 | DISAS_INSN(move_to_ccr) |
1417 | { | |
d4d79bb1 | 1418 | gen_set_sr(env, s, insn, 1); |
0633879f PB |
1419 | } |
1420 | ||
e6e5906b PB |
1421 | DISAS_INSN(not) |
1422 | { | |
e1f3808e | 1423 | TCGv reg; |
e6e5906b PB |
1424 | |
1425 | reg = DREG(insn, 0); | |
e1f3808e | 1426 | tcg_gen_not_i32(reg, reg); |
e6e5906b PB |
1427 | gen_logic_cc(s, reg); |
1428 | } | |
1429 | ||
1430 | DISAS_INSN(swap) | |
1431 | { | |
e1f3808e PB |
1432 | TCGv src1; |
1433 | TCGv src2; | |
1434 | TCGv reg; | |
e6e5906b | 1435 | |
a7812ae4 PB |
1436 | src1 = tcg_temp_new(); |
1437 | src2 = tcg_temp_new(); | |
e6e5906b | 1438 | reg = DREG(insn, 0); |
e1f3808e PB |
1439 | tcg_gen_shli_i32(src1, reg, 16); |
1440 | tcg_gen_shri_i32(src2, reg, 16); | |
1441 | tcg_gen_or_i32(reg, src1, src2); | |
1442 | gen_logic_cc(s, reg); | |
e6e5906b PB |
1443 | } |
1444 | ||
1445 | DISAS_INSN(pea) | |
1446 | { | |
e1f3808e | 1447 | TCGv tmp; |
e6e5906b | 1448 | |
d4d79bb1 | 1449 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1450 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1451 | gen_addr_fault(s); |
1452 | return; | |
1453 | } | |
0633879f | 1454 | gen_push(s, tmp); |
e6e5906b PB |
1455 | } |
1456 | ||
1457 | DISAS_INSN(ext) | |
1458 | { | |
e6e5906b | 1459 | int op; |
e1f3808e PB |
1460 | TCGv reg; |
1461 | TCGv tmp; | |
e6e5906b PB |
1462 | |
1463 | reg = DREG(insn, 0); | |
1464 | op = (insn >> 6) & 7; | |
a7812ae4 | 1465 | tmp = tcg_temp_new(); |
e6e5906b | 1466 | if (op == 3) |
e1f3808e | 1467 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1468 | else |
e1f3808e | 1469 | tcg_gen_ext8s_i32(tmp, reg); |
e6e5906b PB |
1470 | if (op == 2) |
1471 | gen_partset_reg(OS_WORD, reg, tmp); | |
1472 | else | |
e1f3808e | 1473 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1474 | gen_logic_cc(s, tmp); |
1475 | } | |
1476 | ||
1477 | DISAS_INSN(tst) | |
1478 | { | |
1479 | int opsize; | |
e1f3808e | 1480 | TCGv tmp; |
e6e5906b PB |
1481 | |
1482 | switch ((insn >> 6) & 3) { | |
1483 | case 0: /* tst.b */ | |
1484 | opsize = OS_BYTE; | |
1485 | break; | |
1486 | case 1: /* tst.w */ | |
1487 | opsize = OS_WORD; | |
1488 | break; | |
1489 | case 2: /* tst.l */ | |
1490 | opsize = OS_LONG; | |
1491 | break; | |
1492 | default: | |
1493 | abort(); | |
1494 | } | |
d4d79bb1 | 1495 | SRC_EA(env, tmp, opsize, 1, NULL); |
e6e5906b PB |
1496 | gen_logic_cc(s, tmp); |
1497 | } | |
1498 | ||
1499 | DISAS_INSN(pulse) | |
1500 | { | |
1501 | /* Implemented as a NOP. */ | |
1502 | } | |
1503 | ||
1504 | DISAS_INSN(illegal) | |
1505 | { | |
1506 | gen_exception(s, s->pc - 2, EXCP_ILLEGAL); | |
1507 | } | |
1508 | ||
1509 | /* ??? This should be atomic. */ | |
1510 | DISAS_INSN(tas) | |
1511 | { | |
e1f3808e PB |
1512 | TCGv dest; |
1513 | TCGv src1; | |
1514 | TCGv addr; | |
e6e5906b | 1515 | |
a7812ae4 | 1516 | dest = tcg_temp_new(); |
d4d79bb1 | 1517 | SRC_EA(env, src1, OS_BYTE, 1, &addr); |
e6e5906b | 1518 | gen_logic_cc(s, src1); |
e1f3808e | 1519 | tcg_gen_ori_i32(dest, src1, 0x80); |
d4d79bb1 | 1520 | DEST_EA(env, insn, OS_BYTE, dest, &addr); |
e6e5906b PB |
1521 | } |
1522 | ||
1523 | DISAS_INSN(mull) | |
1524 | { | |
1525 | uint16_t ext; | |
e1f3808e PB |
1526 | TCGv reg; |
1527 | TCGv src1; | |
1528 | TCGv dest; | |
e6e5906b PB |
1529 | |
1530 | /* The upper 32 bits of the product are discarded, so | |
1531 | muls.l and mulu.l are functionally equivalent. */ | |
d4d79bb1 | 1532 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
1533 | s->pc += 2; |
1534 | if (ext & 0x87ff) { | |
1535 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
1536 | return; | |
1537 | } | |
1538 | reg = DREG(ext, 12); | |
d4d79bb1 | 1539 | SRC_EA(env, src1, OS_LONG, 0, NULL); |
a7812ae4 | 1540 | dest = tcg_temp_new(); |
e1f3808e PB |
1541 | tcg_gen_mul_i32(dest, src1, reg); |
1542 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1543 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
1544 | gen_logic_cc(s, dest); | |
1545 | } | |
1546 | ||
1547 | DISAS_INSN(link) | |
1548 | { | |
1549 | int16_t offset; | |
e1f3808e PB |
1550 | TCGv reg; |
1551 | TCGv tmp; | |
e6e5906b | 1552 | |
d4d79bb1 | 1553 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1554 | s->pc += 2; |
1555 | reg = AREG(insn, 0); | |
a7812ae4 | 1556 | tmp = tcg_temp_new(); |
e1f3808e | 1557 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1558 | gen_store(s, OS_LONG, tmp, reg); |
e1f3808e PB |
1559 | if ((insn & 7) != 7) |
1560 | tcg_gen_mov_i32(reg, tmp); | |
1561 | tcg_gen_addi_i32(QREG_SP, tmp, offset); | |
e6e5906b PB |
1562 | } |
1563 | ||
1564 | DISAS_INSN(unlk) | |
1565 | { | |
e1f3808e PB |
1566 | TCGv src; |
1567 | TCGv reg; | |
1568 | TCGv tmp; | |
e6e5906b | 1569 | |
a7812ae4 | 1570 | src = tcg_temp_new(); |
e6e5906b | 1571 | reg = AREG(insn, 0); |
e1f3808e | 1572 | tcg_gen_mov_i32(src, reg); |
0633879f | 1573 | tmp = gen_load(s, OS_LONG, src, 0); |
e1f3808e PB |
1574 | tcg_gen_mov_i32(reg, tmp); |
1575 | tcg_gen_addi_i32(QREG_SP, src, 4); | |
e6e5906b PB |
1576 | } |
1577 | ||
1578 | DISAS_INSN(nop) | |
1579 | { | |
1580 | } | |
1581 | ||
1582 | DISAS_INSN(rts) | |
1583 | { | |
e1f3808e | 1584 | TCGv tmp; |
e6e5906b | 1585 | |
0633879f | 1586 | tmp = gen_load(s, OS_LONG, QREG_SP, 0); |
e1f3808e | 1587 | tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); |
e6e5906b PB |
1588 | gen_jmp(s, tmp); |
1589 | } | |
1590 | ||
1591 | DISAS_INSN(jump) | |
1592 | { | |
e1f3808e | 1593 | TCGv tmp; |
e6e5906b PB |
1594 | |
1595 | /* Load the target address first to ensure correct exception | |
1596 | behavior. */ | |
d4d79bb1 | 1597 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1598 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1599 | gen_addr_fault(s); |
1600 | return; | |
1601 | } | |
e6e5906b PB |
1602 | if ((insn & 0x40) == 0) { |
1603 | /* jsr */ | |
351326a6 | 1604 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1605 | } |
1606 | gen_jmp(s, tmp); | |
1607 | } | |
1608 | ||
1609 | DISAS_INSN(addsubq) | |
1610 | { | |
e1f3808e PB |
1611 | TCGv src1; |
1612 | TCGv src2; | |
1613 | TCGv dest; | |
e6e5906b | 1614 | int val; |
e1f3808e | 1615 | TCGv addr; |
e6e5906b | 1616 | |
d4d79bb1 | 1617 | SRC_EA(env, src1, OS_LONG, 0, &addr); |
e6e5906b PB |
1618 | val = (insn >> 9) & 7; |
1619 | if (val == 0) | |
1620 | val = 8; | |
a7812ae4 | 1621 | dest = tcg_temp_new(); |
e1f3808e | 1622 | tcg_gen_mov_i32(dest, src1); |
e6e5906b PB |
1623 | if ((insn & 0x38) == 0x08) { |
1624 | /* Don't update condition codes if the destination is an | |
1625 | address register. */ | |
1626 | if (insn & 0x0100) { | |
e1f3808e | 1627 | tcg_gen_subi_i32(dest, dest, val); |
e6e5906b | 1628 | } else { |
e1f3808e | 1629 | tcg_gen_addi_i32(dest, dest, val); |
e6e5906b PB |
1630 | } |
1631 | } else { | |
351326a6 | 1632 | src2 = tcg_const_i32(val); |
e6e5906b | 1633 | if (insn & 0x0100) { |
e1f3808e PB |
1634 | gen_helper_xflag_lt(QREG_CC_X, dest, src2); |
1635 | tcg_gen_subi_i32(dest, dest, val); | |
e6e5906b PB |
1636 | s->cc_op = CC_OP_SUB; |
1637 | } else { | |
e1f3808e PB |
1638 | tcg_gen_addi_i32(dest, dest, val); |
1639 | gen_helper_xflag_lt(QREG_CC_X, dest, src2); | |
e6e5906b PB |
1640 | s->cc_op = CC_OP_ADD; |
1641 | } | |
e1f3808e | 1642 | gen_update_cc_add(dest, src2); |
e6e5906b | 1643 | } |
d4d79bb1 | 1644 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1645 | } |
1646 | ||
1647 | DISAS_INSN(tpf) | |
1648 | { | |
1649 | switch (insn & 7) { | |
1650 | case 2: /* One extension word. */ | |
1651 | s->pc += 2; | |
1652 | break; | |
1653 | case 3: /* Two extension words. */ | |
1654 | s->pc += 4; | |
1655 | break; | |
1656 | case 4: /* No extension words. */ | |
1657 | break; | |
1658 | default: | |
d4d79bb1 | 1659 | disas_undef(env, s, insn); |
e6e5906b PB |
1660 | } |
1661 | } | |
1662 | ||
1663 | DISAS_INSN(branch) | |
1664 | { | |
1665 | int32_t offset; | |
1666 | uint32_t base; | |
1667 | int op; | |
42a268c2 | 1668 | TCGLabel *l1; |
3b46e624 | 1669 | |
e6e5906b PB |
1670 | base = s->pc; |
1671 | op = (insn >> 8) & 0xf; | |
1672 | offset = (int8_t)insn; | |
1673 | if (offset == 0) { | |
d4d79bb1 | 1674 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1675 | s->pc += 2; |
1676 | } else if (offset == -1) { | |
d4d79bb1 | 1677 | offset = read_im32(env, s); |
e6e5906b PB |
1678 | } |
1679 | if (op == 1) { | |
1680 | /* bsr */ | |
351326a6 | 1681 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1682 | } |
1683 | gen_flush_cc_op(s); | |
1684 | if (op > 1) { | |
1685 | /* Bcc */ | |
1686 | l1 = gen_new_label(); | |
1687 | gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); | |
1688 | gen_jmp_tb(s, 1, base + offset); | |
1689 | gen_set_label(l1); | |
1690 | gen_jmp_tb(s, 0, s->pc); | |
1691 | } else { | |
1692 | /* Unconditional branch. */ | |
1693 | gen_jmp_tb(s, 0, base + offset); | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | DISAS_INSN(moveq) | |
1698 | { | |
e1f3808e | 1699 | uint32_t val; |
e6e5906b | 1700 | |
e1f3808e PB |
1701 | val = (int8_t)insn; |
1702 | tcg_gen_movi_i32(DREG(insn, 9), val); | |
1703 | gen_logic_cc(s, tcg_const_i32(val)); | |
e6e5906b PB |
1704 | } |
1705 | ||
1706 | DISAS_INSN(mvzs) | |
1707 | { | |
1708 | int opsize; | |
e1f3808e PB |
1709 | TCGv src; |
1710 | TCGv reg; | |
e6e5906b PB |
1711 | |
1712 | if (insn & 0x40) | |
1713 | opsize = OS_WORD; | |
1714 | else | |
1715 | opsize = OS_BYTE; | |
d4d79bb1 | 1716 | SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); |
e6e5906b | 1717 | reg = DREG(insn, 9); |
e1f3808e | 1718 | tcg_gen_mov_i32(reg, src); |
e6e5906b PB |
1719 | gen_logic_cc(s, src); |
1720 | } | |
1721 | ||
1722 | DISAS_INSN(or) | |
1723 | { | |
e1f3808e PB |
1724 | TCGv reg; |
1725 | TCGv dest; | |
1726 | TCGv src; | |
1727 | TCGv addr; | |
e6e5906b PB |
1728 | |
1729 | reg = DREG(insn, 9); | |
a7812ae4 | 1730 | dest = tcg_temp_new(); |
e6e5906b | 1731 | if (insn & 0x100) { |
d4d79bb1 | 1732 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1733 | tcg_gen_or_i32(dest, src, reg); |
d4d79bb1 | 1734 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1735 | } else { |
d4d79bb1 | 1736 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1737 | tcg_gen_or_i32(dest, src, reg); |
1738 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1739 | } |
1740 | gen_logic_cc(s, dest); | |
1741 | } | |
1742 | ||
1743 | DISAS_INSN(suba) | |
1744 | { | |
e1f3808e PB |
1745 | TCGv src; |
1746 | TCGv reg; | |
e6e5906b | 1747 | |
d4d79bb1 | 1748 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1749 | reg = AREG(insn, 9); |
e1f3808e | 1750 | tcg_gen_sub_i32(reg, reg, src); |
e6e5906b PB |
1751 | } |
1752 | ||
1753 | DISAS_INSN(subx) | |
1754 | { | |
e1f3808e PB |
1755 | TCGv reg; |
1756 | TCGv src; | |
e6e5906b PB |
1757 | |
1758 | gen_flush_flags(s); | |
1759 | reg = DREG(insn, 9); | |
1760 | src = DREG(insn, 0); | |
e1f3808e | 1761 | gen_helper_subx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1762 | } |
1763 | ||
1764 | DISAS_INSN(mov3q) | |
1765 | { | |
e1f3808e | 1766 | TCGv src; |
e6e5906b PB |
1767 | int val; |
1768 | ||
1769 | val = (insn >> 9) & 7; | |
1770 | if (val == 0) | |
1771 | val = -1; | |
351326a6 | 1772 | src = tcg_const_i32(val); |
e6e5906b | 1773 | gen_logic_cc(s, src); |
d4d79bb1 | 1774 | DEST_EA(env, insn, OS_LONG, src, NULL); |
e6e5906b PB |
1775 | } |
1776 | ||
1777 | DISAS_INSN(cmp) | |
1778 | { | |
1779 | int op; | |
e1f3808e PB |
1780 | TCGv src; |
1781 | TCGv reg; | |
1782 | TCGv dest; | |
e6e5906b PB |
1783 | int opsize; |
1784 | ||
1785 | op = (insn >> 6) & 3; | |
1786 | switch (op) { | |
1787 | case 0: /* cmp.b */ | |
1788 | opsize = OS_BYTE; | |
1789 | s->cc_op = CC_OP_CMPB; | |
1790 | break; | |
1791 | case 1: /* cmp.w */ | |
1792 | opsize = OS_WORD; | |
1793 | s->cc_op = CC_OP_CMPW; | |
1794 | break; | |
1795 | case 2: /* cmp.l */ | |
1796 | opsize = OS_LONG; | |
1797 | s->cc_op = CC_OP_SUB; | |
1798 | break; | |
1799 | default: | |
1800 | abort(); | |
1801 | } | |
d4d79bb1 | 1802 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1803 | reg = DREG(insn, 9); |
a7812ae4 | 1804 | dest = tcg_temp_new(); |
e1f3808e PB |
1805 | tcg_gen_sub_i32(dest, reg, src); |
1806 | gen_update_cc_add(dest, src); | |
e6e5906b PB |
1807 | } |
1808 | ||
1809 | DISAS_INSN(cmpa) | |
1810 | { | |
1811 | int opsize; | |
e1f3808e PB |
1812 | TCGv src; |
1813 | TCGv reg; | |
1814 | TCGv dest; | |
e6e5906b PB |
1815 | |
1816 | if (insn & 0x100) { | |
1817 | opsize = OS_LONG; | |
1818 | } else { | |
1819 | opsize = OS_WORD; | |
1820 | } | |
d4d79bb1 | 1821 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1822 | reg = AREG(insn, 9); |
a7812ae4 | 1823 | dest = tcg_temp_new(); |
e1f3808e PB |
1824 | tcg_gen_sub_i32(dest, reg, src); |
1825 | gen_update_cc_add(dest, src); | |
e6e5906b PB |
1826 | s->cc_op = CC_OP_SUB; |
1827 | } | |
1828 | ||
1829 | DISAS_INSN(eor) | |
1830 | { | |
e1f3808e PB |
1831 | TCGv src; |
1832 | TCGv reg; | |
1833 | TCGv dest; | |
1834 | TCGv addr; | |
e6e5906b | 1835 | |
d4d79bb1 | 1836 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e6e5906b | 1837 | reg = DREG(insn, 9); |
a7812ae4 | 1838 | dest = tcg_temp_new(); |
e1f3808e | 1839 | tcg_gen_xor_i32(dest, src, reg); |
e6e5906b | 1840 | gen_logic_cc(s, dest); |
d4d79bb1 | 1841 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1842 | } |
1843 | ||
1844 | DISAS_INSN(and) | |
1845 | { | |
e1f3808e PB |
1846 | TCGv src; |
1847 | TCGv reg; | |
1848 | TCGv dest; | |
1849 | TCGv addr; | |
e6e5906b PB |
1850 | |
1851 | reg = DREG(insn, 9); | |
a7812ae4 | 1852 | dest = tcg_temp_new(); |
e6e5906b | 1853 | if (insn & 0x100) { |
d4d79bb1 | 1854 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1855 | tcg_gen_and_i32(dest, src, reg); |
d4d79bb1 | 1856 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1857 | } else { |
d4d79bb1 | 1858 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1859 | tcg_gen_and_i32(dest, src, reg); |
1860 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1861 | } |
1862 | gen_logic_cc(s, dest); | |
1863 | } | |
1864 | ||
1865 | DISAS_INSN(adda) | |
1866 | { | |
e1f3808e PB |
1867 | TCGv src; |
1868 | TCGv reg; | |
e6e5906b | 1869 | |
d4d79bb1 | 1870 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1871 | reg = AREG(insn, 9); |
e1f3808e | 1872 | tcg_gen_add_i32(reg, reg, src); |
e6e5906b PB |
1873 | } |
1874 | ||
1875 | DISAS_INSN(addx) | |
1876 | { | |
e1f3808e PB |
1877 | TCGv reg; |
1878 | TCGv src; | |
e6e5906b PB |
1879 | |
1880 | gen_flush_flags(s); | |
1881 | reg = DREG(insn, 9); | |
1882 | src = DREG(insn, 0); | |
e1f3808e | 1883 | gen_helper_addx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1884 | s->cc_op = CC_OP_FLAGS; |
1885 | } | |
1886 | ||
e1f3808e | 1887 | /* TODO: This could be implemented without helper functions. */ |
e6e5906b PB |
1888 | DISAS_INSN(shift_im) |
1889 | { | |
e1f3808e | 1890 | TCGv reg; |
e6e5906b | 1891 | int tmp; |
e1f3808e | 1892 | TCGv shift; |
e6e5906b PB |
1893 | |
1894 | reg = DREG(insn, 0); | |
1895 | tmp = (insn >> 9) & 7; | |
1896 | if (tmp == 0) | |
e1f3808e | 1897 | tmp = 8; |
351326a6 | 1898 | shift = tcg_const_i32(tmp); |
e1f3808e | 1899 | /* No need to flush flags becuse we know we will set C flag. */ |
e6e5906b | 1900 | if (insn & 0x100) { |
e1f3808e | 1901 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1902 | } else { |
1903 | if (insn & 8) { | |
e1f3808e | 1904 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1905 | } else { |
e1f3808e | 1906 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1907 | } |
1908 | } | |
e1f3808e | 1909 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1910 | } |
1911 | ||
1912 | DISAS_INSN(shift_reg) | |
1913 | { | |
e1f3808e PB |
1914 | TCGv reg; |
1915 | TCGv shift; | |
e6e5906b PB |
1916 | |
1917 | reg = DREG(insn, 0); | |
e1f3808e PB |
1918 | shift = DREG(insn, 9); |
1919 | /* Shift by zero leaves C flag unmodified. */ | |
1920 | gen_flush_flags(s); | |
e6e5906b | 1921 | if (insn & 0x100) { |
e1f3808e | 1922 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1923 | } else { |
1924 | if (insn & 8) { | |
e1f3808e | 1925 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1926 | } else { |
e1f3808e | 1927 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1928 | } |
1929 | } | |
e1f3808e | 1930 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1931 | } |
1932 | ||
1933 | DISAS_INSN(ff1) | |
1934 | { | |
e1f3808e | 1935 | TCGv reg; |
821f7e76 PB |
1936 | reg = DREG(insn, 0); |
1937 | gen_logic_cc(s, reg); | |
e1f3808e | 1938 | gen_helper_ff1(reg, reg); |
e6e5906b PB |
1939 | } |
1940 | ||
e1f3808e | 1941 | static TCGv gen_get_sr(DisasContext *s) |
0633879f | 1942 | { |
e1f3808e PB |
1943 | TCGv ccr; |
1944 | TCGv sr; | |
0633879f PB |
1945 | |
1946 | ccr = gen_get_ccr(s); | |
a7812ae4 | 1947 | sr = tcg_temp_new(); |
e1f3808e PB |
1948 | tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); |
1949 | tcg_gen_or_i32(sr, sr, ccr); | |
0633879f PB |
1950 | return sr; |
1951 | } | |
1952 | ||
e6e5906b PB |
1953 | DISAS_INSN(strldsr) |
1954 | { | |
1955 | uint16_t ext; | |
1956 | uint32_t addr; | |
1957 | ||
1958 | addr = s->pc - 2; | |
d4d79bb1 | 1959 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 1960 | s->pc += 2; |
0633879f | 1961 | if (ext != 0x46FC) { |
e6e5906b | 1962 | gen_exception(s, addr, EXCP_UNSUPPORTED); |
0633879f PB |
1963 | return; |
1964 | } | |
d4d79bb1 | 1965 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
1966 | s->pc += 2; |
1967 | if (IS_USER(s) || (ext & SR_S) == 0) { | |
e6e5906b | 1968 | gen_exception(s, addr, EXCP_PRIVILEGE); |
0633879f PB |
1969 | return; |
1970 | } | |
1971 | gen_push(s, gen_get_sr(s)); | |
1972 | gen_set_sr_im(s, ext, 0); | |
e6e5906b PB |
1973 | } |
1974 | ||
1975 | DISAS_INSN(move_from_sr) | |
1976 | { | |
e1f3808e PB |
1977 | TCGv reg; |
1978 | TCGv sr; | |
0633879f PB |
1979 | |
1980 | if (IS_USER(s)) { | |
1981 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1982 | return; | |
1983 | } | |
1984 | sr = gen_get_sr(s); | |
1985 | reg = DREG(insn, 0); | |
1986 | gen_partset_reg(OS_WORD, reg, sr); | |
e6e5906b PB |
1987 | } |
1988 | ||
1989 | DISAS_INSN(move_to_sr) | |
1990 | { | |
0633879f PB |
1991 | if (IS_USER(s)) { |
1992 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1993 | return; | |
1994 | } | |
d4d79bb1 | 1995 | gen_set_sr(env, s, insn, 0); |
0633879f | 1996 | gen_lookup_tb(s); |
e6e5906b PB |
1997 | } |
1998 | ||
1999 | DISAS_INSN(move_from_usp) | |
2000 | { | |
0633879f PB |
2001 | if (IS_USER(s)) { |
2002 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2003 | return; | |
2004 | } | |
2a8327e8 GU |
2005 | tcg_gen_ld_i32(AREG(insn, 0), cpu_env, |
2006 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2007 | } |
2008 | ||
2009 | DISAS_INSN(move_to_usp) | |
2010 | { | |
0633879f PB |
2011 | if (IS_USER(s)) { |
2012 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2013 | return; | |
2014 | } | |
2a8327e8 GU |
2015 | tcg_gen_st_i32(AREG(insn, 0), cpu_env, |
2016 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2017 | } |
2018 | ||
2019 | DISAS_INSN(halt) | |
2020 | { | |
e1f3808e | 2021 | gen_exception(s, s->pc, EXCP_HALT_INSN); |
e6e5906b PB |
2022 | } |
2023 | ||
2024 | DISAS_INSN(stop) | |
2025 | { | |
0633879f PB |
2026 | uint16_t ext; |
2027 | ||
2028 | if (IS_USER(s)) { | |
2029 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2030 | return; | |
2031 | } | |
2032 | ||
d4d79bb1 | 2033 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
2034 | s->pc += 2; |
2035 | ||
2036 | gen_set_sr_im(s, ext, 0); | |
259186a7 | 2037 | tcg_gen_movi_i32(cpu_halted, 1); |
e1f3808e | 2038 | gen_exception(s, s->pc, EXCP_HLT); |
e6e5906b PB |
2039 | } |
2040 | ||
2041 | DISAS_INSN(rte) | |
2042 | { | |
0633879f PB |
2043 | if (IS_USER(s)) { |
2044 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2045 | return; | |
2046 | } | |
2047 | gen_exception(s, s->pc - 2, EXCP_RTE); | |
e6e5906b PB |
2048 | } |
2049 | ||
2050 | DISAS_INSN(movec) | |
2051 | { | |
0633879f | 2052 | uint16_t ext; |
e1f3808e | 2053 | TCGv reg; |
0633879f PB |
2054 | |
2055 | if (IS_USER(s)) { | |
2056 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2057 | return; | |
2058 | } | |
2059 | ||
d4d79bb1 | 2060 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
2061 | s->pc += 2; |
2062 | ||
2063 | if (ext & 0x8000) { | |
2064 | reg = AREG(ext, 12); | |
2065 | } else { | |
2066 | reg = DREG(ext, 12); | |
2067 | } | |
e1f3808e | 2068 | gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); |
0633879f | 2069 | gen_lookup_tb(s); |
e6e5906b PB |
2070 | } |
2071 | ||
2072 | DISAS_INSN(intouch) | |
2073 | { | |
0633879f PB |
2074 | if (IS_USER(s)) { |
2075 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2076 | return; | |
2077 | } | |
2078 | /* ICache fetch. Implement as no-op. */ | |
e6e5906b PB |
2079 | } |
2080 | ||
2081 | DISAS_INSN(cpushl) | |
2082 | { | |
0633879f PB |
2083 | if (IS_USER(s)) { |
2084 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2085 | return; | |
2086 | } | |
2087 | /* Cache push/invalidate. Implement as no-op. */ | |
e6e5906b PB |
2088 | } |
2089 | ||
2090 | DISAS_INSN(wddata) | |
2091 | { | |
2092 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2093 | } | |
2094 | ||
2095 | DISAS_INSN(wdebug) | |
2096 | { | |
a47dddd7 AF |
2097 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2098 | ||
0633879f PB |
2099 | if (IS_USER(s)) { |
2100 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2101 | return; | |
2102 | } | |
2103 | /* TODO: Implement wdebug. */ | |
a47dddd7 | 2104 | cpu_abort(CPU(cpu), "WDEBUG not implemented"); |
e6e5906b PB |
2105 | } |
2106 | ||
2107 | DISAS_INSN(trap) | |
2108 | { | |
2109 | gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); | |
2110 | } | |
2111 | ||
2112 | /* ??? FP exceptions are not implemented. Most exceptions are deferred until | |
2113 | immediately before the next FP instruction is executed. */ | |
2114 | DISAS_INSN(fpu) | |
2115 | { | |
2116 | uint16_t ext; | |
a7812ae4 | 2117 | int32_t offset; |
e6e5906b | 2118 | int opmode; |
a7812ae4 PB |
2119 | TCGv_i64 src; |
2120 | TCGv_i64 dest; | |
2121 | TCGv_i64 res; | |
2122 | TCGv tmp32; | |
e6e5906b | 2123 | int round; |
a7812ae4 | 2124 | int set_dest; |
e6e5906b PB |
2125 | int opsize; |
2126 | ||
d4d79bb1 | 2127 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2128 | s->pc += 2; |
2129 | opmode = ext & 0x7f; | |
2130 | switch ((ext >> 13) & 7) { | |
2131 | case 0: case 2: | |
2132 | break; | |
2133 | case 1: | |
2134 | goto undef; | |
2135 | case 3: /* fmove out */ | |
2136 | src = FREG(ext, 7); | |
a7812ae4 | 2137 | tmp32 = tcg_temp_new_i32(); |
e6e5906b PB |
2138 | /* fmove */ |
2139 | /* ??? TODO: Proper behavior on overflow. */ | |
2140 | switch ((ext >> 10) & 7) { | |
2141 | case 0: | |
2142 | opsize = OS_LONG; | |
a7812ae4 | 2143 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2144 | break; |
2145 | case 1: | |
2146 | opsize = OS_SINGLE; | |
a7812ae4 | 2147 | gen_helper_f64_to_f32(tmp32, cpu_env, src); |
e6e5906b PB |
2148 | break; |
2149 | case 4: | |
2150 | opsize = OS_WORD; | |
a7812ae4 | 2151 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b | 2152 | break; |
a7812ae4 PB |
2153 | case 5: /* OS_DOUBLE */ |
2154 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2155 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2156 | case 2: |
2157 | case 3: | |
243ee8f7 | 2158 | break; |
a7812ae4 PB |
2159 | case 4: |
2160 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2161 | break; | |
2162 | case 5: | |
d4d79bb1 | 2163 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2164 | s->pc += 2; |
2165 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2166 | break; | |
2167 | default: | |
2168 | goto undef; | |
2169 | } | |
2170 | gen_store64(s, tmp32, src); | |
c59b97aa | 2171 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2172 | case 3: |
2173 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2174 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2175 | break; | |
2176 | case 4: | |
2177 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2178 | break; | |
2179 | } | |
2180 | tcg_temp_free_i32(tmp32); | |
2181 | return; | |
e6e5906b PB |
2182 | case 6: |
2183 | opsize = OS_BYTE; | |
a7812ae4 | 2184 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2185 | break; |
2186 | default: | |
2187 | goto undef; | |
2188 | } | |
d4d79bb1 | 2189 | DEST_EA(env, insn, opsize, tmp32, NULL); |
a7812ae4 | 2190 | tcg_temp_free_i32(tmp32); |
e6e5906b PB |
2191 | return; |
2192 | case 4: /* fmove to control register. */ | |
2193 | switch ((ext >> 10) & 7) { | |
2194 | case 4: /* FPCR */ | |
2195 | /* Not implemented. Ignore writes. */ | |
2196 | break; | |
2197 | case 1: /* FPIAR */ | |
2198 | case 2: /* FPSR */ | |
2199 | default: | |
2200 | cpu_abort(NULL, "Unimplemented: fmove to control %d", | |
2201 | (ext >> 10) & 7); | |
2202 | } | |
2203 | break; | |
2204 | case 5: /* fmove from control register. */ | |
2205 | switch ((ext >> 10) & 7) { | |
2206 | case 4: /* FPCR */ | |
2207 | /* Not implemented. Always return zero. */ | |
351326a6 | 2208 | tmp32 = tcg_const_i32(0); |
e6e5906b PB |
2209 | break; |
2210 | case 1: /* FPIAR */ | |
2211 | case 2: /* FPSR */ | |
2212 | default: | |
2213 | cpu_abort(NULL, "Unimplemented: fmove from control %d", | |
2214 | (ext >> 10) & 7); | |
2215 | goto undef; | |
2216 | } | |
d4d79bb1 | 2217 | DEST_EA(env, insn, OS_LONG, tmp32, NULL); |
e6e5906b | 2218 | break; |
5fafdf24 | 2219 | case 6: /* fmovem */ |
e6e5906b PB |
2220 | case 7: |
2221 | { | |
e1f3808e PB |
2222 | TCGv addr; |
2223 | uint16_t mask; | |
2224 | int i; | |
2225 | if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) | |
2226 | goto undef; | |
d4d79bb1 | 2227 | tmp32 = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2228 | if (IS_NULL_QREG(tmp32)) { |
e1f3808e PB |
2229 | gen_addr_fault(s); |
2230 | return; | |
2231 | } | |
a7812ae4 PB |
2232 | addr = tcg_temp_new_i32(); |
2233 | tcg_gen_mov_i32(addr, tmp32); | |
e1f3808e PB |
2234 | mask = 0x80; |
2235 | for (i = 0; i < 8; i++) { | |
2236 | if (ext & mask) { | |
e1f3808e PB |
2237 | dest = FREG(i, 0); |
2238 | if (ext & (1 << 13)) { | |
2239 | /* store */ | |
2240 | tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); | |
2241 | } else { | |
2242 | /* load */ | |
2243 | tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); | |
2244 | } | |
2245 | if (ext & (mask - 1)) | |
2246 | tcg_gen_addi_i32(addr, addr, 8); | |
e6e5906b | 2247 | } |
e1f3808e | 2248 | mask >>= 1; |
e6e5906b | 2249 | } |
18307f26 | 2250 | tcg_temp_free_i32(addr); |
e6e5906b PB |
2251 | } |
2252 | return; | |
2253 | } | |
2254 | if (ext & (1 << 14)) { | |
e6e5906b PB |
2255 | /* Source effective address. */ |
2256 | switch ((ext >> 10) & 7) { | |
2257 | case 0: opsize = OS_LONG; break; | |
2258 | case 1: opsize = OS_SINGLE; break; | |
2259 | case 4: opsize = OS_WORD; break; | |
2260 | case 5: opsize = OS_DOUBLE; break; | |
2261 | case 6: opsize = OS_BYTE; break; | |
2262 | default: | |
2263 | goto undef; | |
2264 | } | |
e6e5906b | 2265 | if (opsize == OS_DOUBLE) { |
a7812ae4 PB |
2266 | tmp32 = tcg_temp_new_i32(); |
2267 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2268 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2269 | case 2: |
2270 | case 3: | |
243ee8f7 | 2271 | break; |
a7812ae4 PB |
2272 | case 4: |
2273 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2274 | break; | |
2275 | case 5: | |
d4d79bb1 | 2276 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2277 | s->pc += 2; |
2278 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2279 | break; | |
2280 | case 7: | |
d4d79bb1 | 2281 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2282 | offset += s->pc - 2; |
2283 | s->pc += 2; | |
2284 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2285 | break; | |
2286 | default: | |
2287 | goto undef; | |
2288 | } | |
2289 | src = gen_load64(s, tmp32); | |
c59b97aa | 2290 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2291 | case 3: |
2292 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2293 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2294 | break; | |
2295 | case 4: | |
2296 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2297 | break; | |
2298 | } | |
2299 | tcg_temp_free_i32(tmp32); | |
e6e5906b | 2300 | } else { |
d4d79bb1 | 2301 | SRC_EA(env, tmp32, opsize, 1, NULL); |
a7812ae4 | 2302 | src = tcg_temp_new_i64(); |
e6e5906b PB |
2303 | switch (opsize) { |
2304 | case OS_LONG: | |
2305 | case OS_WORD: | |
2306 | case OS_BYTE: | |
a7812ae4 | 2307 | gen_helper_i32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2308 | break; |
2309 | case OS_SINGLE: | |
a7812ae4 | 2310 | gen_helper_f32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2311 | break; |
2312 | } | |
2313 | } | |
2314 | } else { | |
2315 | /* Source register. */ | |
2316 | src = FREG(ext, 10); | |
2317 | } | |
2318 | dest = FREG(ext, 7); | |
a7812ae4 | 2319 | res = tcg_temp_new_i64(); |
e6e5906b | 2320 | if (opmode != 0x3a) |
e1f3808e | 2321 | tcg_gen_mov_f64(res, dest); |
e6e5906b | 2322 | round = 1; |
a7812ae4 | 2323 | set_dest = 1; |
e6e5906b PB |
2324 | switch (opmode) { |
2325 | case 0: case 0x40: case 0x44: /* fmove */ | |
e1f3808e | 2326 | tcg_gen_mov_f64(res, src); |
e6e5906b PB |
2327 | break; |
2328 | case 1: /* fint */ | |
e1f3808e | 2329 | gen_helper_iround_f64(res, cpu_env, src); |
e6e5906b PB |
2330 | round = 0; |
2331 | break; | |
2332 | case 3: /* fintrz */ | |
e1f3808e | 2333 | gen_helper_itrunc_f64(res, cpu_env, src); |
e6e5906b PB |
2334 | round = 0; |
2335 | break; | |
2336 | case 4: case 0x41: case 0x45: /* fsqrt */ | |
e1f3808e | 2337 | gen_helper_sqrt_f64(res, cpu_env, src); |
e6e5906b PB |
2338 | break; |
2339 | case 0x18: case 0x58: case 0x5c: /* fabs */ | |
e1f3808e | 2340 | gen_helper_abs_f64(res, src); |
e6e5906b PB |
2341 | break; |
2342 | case 0x1a: case 0x5a: case 0x5e: /* fneg */ | |
e1f3808e | 2343 | gen_helper_chs_f64(res, src); |
e6e5906b PB |
2344 | break; |
2345 | case 0x20: case 0x60: case 0x64: /* fdiv */ | |
e1f3808e | 2346 | gen_helper_div_f64(res, cpu_env, res, src); |
e6e5906b PB |
2347 | break; |
2348 | case 0x22: case 0x62: case 0x66: /* fadd */ | |
e1f3808e | 2349 | gen_helper_add_f64(res, cpu_env, res, src); |
e6e5906b PB |
2350 | break; |
2351 | case 0x23: case 0x63: case 0x67: /* fmul */ | |
e1f3808e | 2352 | gen_helper_mul_f64(res, cpu_env, res, src); |
e6e5906b PB |
2353 | break; |
2354 | case 0x28: case 0x68: case 0x6c: /* fsub */ | |
e1f3808e | 2355 | gen_helper_sub_f64(res, cpu_env, res, src); |
e6e5906b PB |
2356 | break; |
2357 | case 0x38: /* fcmp */ | |
e1f3808e | 2358 | gen_helper_sub_cmp_f64(res, cpu_env, res, src); |
a7812ae4 | 2359 | set_dest = 0; |
e6e5906b PB |
2360 | round = 0; |
2361 | break; | |
2362 | case 0x3a: /* ftst */ | |
e1f3808e | 2363 | tcg_gen_mov_f64(res, src); |
a7812ae4 | 2364 | set_dest = 0; |
e6e5906b PB |
2365 | round = 0; |
2366 | break; | |
2367 | default: | |
2368 | goto undef; | |
2369 | } | |
a7812ae4 PB |
2370 | if (ext & (1 << 14)) { |
2371 | tcg_temp_free_i64(src); | |
2372 | } | |
e6e5906b PB |
2373 | if (round) { |
2374 | if (opmode & 0x40) { | |
2375 | if ((opmode & 0x4) != 0) | |
2376 | round = 0; | |
2377 | } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { | |
2378 | round = 0; | |
2379 | } | |
2380 | } | |
2381 | if (round) { | |
a7812ae4 | 2382 | TCGv tmp = tcg_temp_new_i32(); |
e1f3808e PB |
2383 | gen_helper_f64_to_f32(tmp, cpu_env, res); |
2384 | gen_helper_f32_to_f64(res, cpu_env, tmp); | |
a7812ae4 | 2385 | tcg_temp_free_i32(tmp); |
5fafdf24 | 2386 | } |
e1f3808e | 2387 | tcg_gen_mov_f64(QREG_FP_RESULT, res); |
a7812ae4 | 2388 | if (set_dest) { |
e1f3808e | 2389 | tcg_gen_mov_f64(dest, res); |
e6e5906b | 2390 | } |
a7812ae4 | 2391 | tcg_temp_free_i64(res); |
e6e5906b PB |
2392 | return; |
2393 | undef: | |
a7812ae4 | 2394 | /* FIXME: Is this right for offset addressing modes? */ |
e6e5906b | 2395 | s->pc -= 2; |
d4d79bb1 | 2396 | disas_undef_fpu(env, s, insn); |
e6e5906b PB |
2397 | } |
2398 | ||
2399 | DISAS_INSN(fbcc) | |
2400 | { | |
2401 | uint32_t offset; | |
2402 | uint32_t addr; | |
e1f3808e | 2403 | TCGv flag; |
42a268c2 | 2404 | TCGLabel *l1; |
e6e5906b PB |
2405 | |
2406 | addr = s->pc; | |
d4d79bb1 | 2407 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
2408 | s->pc += 2; |
2409 | if (insn & (1 << 6)) { | |
d4d79bb1 | 2410 | offset = (offset << 16) | cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2411 | s->pc += 2; |
2412 | } | |
2413 | ||
2414 | l1 = gen_new_label(); | |
2415 | /* TODO: Raise BSUN exception. */ | |
a7812ae4 | 2416 | flag = tcg_temp_new(); |
e1f3808e | 2417 | gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); |
e6e5906b PB |
2418 | /* Jump to l1 if condition is true. */ |
2419 | switch (insn & 0xf) { | |
2420 | case 0: /* f */ | |
2421 | break; | |
2422 | case 1: /* eq (=0) */ | |
e1f3808e | 2423 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2424 | break; |
2425 | case 2: /* ogt (=1) */ | |
e1f3808e | 2426 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2427 | break; |
2428 | case 3: /* oge (=0 or =1) */ | |
e1f3808e | 2429 | tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2430 | break; |
2431 | case 4: /* olt (=-1) */ | |
e1f3808e | 2432 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2433 | break; |
2434 | case 5: /* ole (=-1 or =0) */ | |
e1f3808e | 2435 | tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2436 | break; |
2437 | case 6: /* ogl (=-1 or =1) */ | |
e1f3808e PB |
2438 | tcg_gen_andi_i32(flag, flag, 1); |
2439 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2440 | break; |
2441 | case 7: /* or (=2) */ | |
e1f3808e | 2442 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2443 | break; |
2444 | case 8: /* un (<2) */ | |
e1f3808e | 2445 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2446 | break; |
2447 | case 9: /* ueq (=0 or =2) */ | |
e1f3808e PB |
2448 | tcg_gen_andi_i32(flag, flag, 1); |
2449 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2450 | break; |
2451 | case 10: /* ugt (>0) */ | |
e1f3808e | 2452 | tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2453 | break; |
2454 | case 11: /* uge (>=0) */ | |
e1f3808e | 2455 | tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2456 | break; |
2457 | case 12: /* ult (=-1 or =2) */ | |
e1f3808e | 2458 | tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2459 | break; |
2460 | case 13: /* ule (!=1) */ | |
e1f3808e | 2461 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2462 | break; |
2463 | case 14: /* ne (!=0) */ | |
e1f3808e | 2464 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2465 | break; |
2466 | case 15: /* t */ | |
e1f3808e | 2467 | tcg_gen_br(l1); |
e6e5906b PB |
2468 | break; |
2469 | } | |
2470 | gen_jmp_tb(s, 0, s->pc); | |
2471 | gen_set_label(l1); | |
2472 | gen_jmp_tb(s, 1, addr + offset); | |
2473 | } | |
2474 | ||
0633879f PB |
2475 | DISAS_INSN(frestore) |
2476 | { | |
a47dddd7 AF |
2477 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2478 | ||
0633879f | 2479 | /* TODO: Implement frestore. */ |
a47dddd7 | 2480 | cpu_abort(CPU(cpu), "FRESTORE not implemented"); |
0633879f PB |
2481 | } |
2482 | ||
2483 | DISAS_INSN(fsave) | |
2484 | { | |
a47dddd7 AF |
2485 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2486 | ||
0633879f | 2487 | /* TODO: Implement fsave. */ |
a47dddd7 | 2488 | cpu_abort(CPU(cpu), "FSAVE not implemented"); |
0633879f PB |
2489 | } |
2490 | ||
e1f3808e | 2491 | static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) |
acf930aa | 2492 | { |
a7812ae4 | 2493 | TCGv tmp = tcg_temp_new(); |
acf930aa PB |
2494 | if (s->env->macsr & MACSR_FI) { |
2495 | if (upper) | |
e1f3808e | 2496 | tcg_gen_andi_i32(tmp, val, 0xffff0000); |
acf930aa | 2497 | else |
e1f3808e | 2498 | tcg_gen_shli_i32(tmp, val, 16); |
acf930aa PB |
2499 | } else if (s->env->macsr & MACSR_SU) { |
2500 | if (upper) | |
e1f3808e | 2501 | tcg_gen_sari_i32(tmp, val, 16); |
acf930aa | 2502 | else |
e1f3808e | 2503 | tcg_gen_ext16s_i32(tmp, val); |
acf930aa PB |
2504 | } else { |
2505 | if (upper) | |
e1f3808e | 2506 | tcg_gen_shri_i32(tmp, val, 16); |
acf930aa | 2507 | else |
e1f3808e | 2508 | tcg_gen_ext16u_i32(tmp, val); |
acf930aa PB |
2509 | } |
2510 | return tmp; | |
2511 | } | |
2512 | ||
e1f3808e PB |
2513 | static void gen_mac_clear_flags(void) |
2514 | { | |
2515 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, | |
2516 | ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); | |
2517 | } | |
2518 | ||
acf930aa PB |
2519 | DISAS_INSN(mac) |
2520 | { | |
e1f3808e PB |
2521 | TCGv rx; |
2522 | TCGv ry; | |
acf930aa PB |
2523 | uint16_t ext; |
2524 | int acc; | |
e1f3808e PB |
2525 | TCGv tmp; |
2526 | TCGv addr; | |
2527 | TCGv loadval; | |
acf930aa | 2528 | int dual; |
e1f3808e PB |
2529 | TCGv saved_flags; |
2530 | ||
a7812ae4 PB |
2531 | if (!s->done_mac) { |
2532 | s->mactmp = tcg_temp_new_i64(); | |
2533 | s->done_mac = 1; | |
2534 | } | |
acf930aa | 2535 | |
d4d79bb1 | 2536 | ext = cpu_lduw_code(env, s->pc); |
acf930aa PB |
2537 | s->pc += 2; |
2538 | ||
2539 | acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); | |
2540 | dual = ((insn & 0x30) != 0 && (ext & 3) != 0); | |
d315c888 | 2541 | if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { |
d4d79bb1 | 2542 | disas_undef(env, s, insn); |
d315c888 PB |
2543 | return; |
2544 | } | |
acf930aa PB |
2545 | if (insn & 0x30) { |
2546 | /* MAC with load. */ | |
d4d79bb1 | 2547 | tmp = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2548 | addr = tcg_temp_new(); |
e1f3808e | 2549 | tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); |
acf930aa PB |
2550 | /* Load the value now to ensure correct exception behavior. |
2551 | Perform writeback after reading the MAC inputs. */ | |
2552 | loadval = gen_load(s, OS_LONG, addr, 0); | |
2553 | ||
2554 | acc ^= 1; | |
2555 | rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); | |
2556 | ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); | |
2557 | } else { | |
e1f3808e | 2558 | loadval = addr = NULL_QREG; |
acf930aa PB |
2559 | rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
2560 | ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
2561 | } | |
2562 | ||
e1f3808e PB |
2563 | gen_mac_clear_flags(); |
2564 | #if 0 | |
acf930aa | 2565 | l1 = -1; |
e1f3808e | 2566 | /* Disabled because conditional branches clobber temporary vars. */ |
acf930aa PB |
2567 | if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { |
2568 | /* Skip the multiply if we know we will ignore it. */ | |
2569 | l1 = gen_new_label(); | |
a7812ae4 | 2570 | tmp = tcg_temp_new(); |
e1f3808e | 2571 | tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); |
acf930aa PB |
2572 | gen_op_jmp_nz32(tmp, l1); |
2573 | } | |
e1f3808e | 2574 | #endif |
acf930aa PB |
2575 | |
2576 | if ((ext & 0x0800) == 0) { | |
2577 | /* Word. */ | |
2578 | rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); | |
2579 | ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); | |
2580 | } | |
2581 | if (s->env->macsr & MACSR_FI) { | |
e1f3808e | 2582 | gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2583 | } else { |
2584 | if (s->env->macsr & MACSR_SU) | |
e1f3808e | 2585 | gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); |
acf930aa | 2586 | else |
e1f3808e | 2587 | gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2588 | switch ((ext >> 9) & 3) { |
2589 | case 1: | |
e1f3808e | 2590 | tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2591 | break; |
2592 | case 3: | |
e1f3808e | 2593 | tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2594 | break; |
2595 | } | |
2596 | } | |
2597 | ||
2598 | if (dual) { | |
2599 | /* Save the overflow flag from the multiply. */ | |
a7812ae4 | 2600 | saved_flags = tcg_temp_new(); |
e1f3808e PB |
2601 | tcg_gen_mov_i32(saved_flags, QREG_MACSR); |
2602 | } else { | |
2603 | saved_flags = NULL_QREG; | |
acf930aa PB |
2604 | } |
2605 | ||
e1f3808e PB |
2606 | #if 0 |
2607 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2608 | if ((s->env->macsr & MACSR_OMC) != 0 && dual) { |
2609 | /* Skip the accumulate if the value is already saturated. */ | |
2610 | l1 = gen_new_label(); | |
a7812ae4 | 2611 | tmp = tcg_temp_new(); |
351326a6 | 2612 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2613 | gen_op_jmp_nz32(tmp, l1); |
2614 | } | |
e1f3808e | 2615 | #endif |
acf930aa PB |
2616 | |
2617 | if (insn & 0x100) | |
e1f3808e | 2618 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2619 | else |
e1f3808e | 2620 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa PB |
2621 | |
2622 | if (s->env->macsr & MACSR_FI) | |
e1f3808e | 2623 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2624 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2625 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2626 | else |
e1f3808e | 2627 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2628 | |
e1f3808e PB |
2629 | #if 0 |
2630 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2631 | if (l1 != -1) |
2632 | gen_set_label(l1); | |
e1f3808e | 2633 | #endif |
acf930aa PB |
2634 | |
2635 | if (dual) { | |
2636 | /* Dual accumulate variant. */ | |
2637 | acc = (ext >> 2) & 3; | |
2638 | /* Restore the overflow flag from the multiplier. */ | |
e1f3808e PB |
2639 | tcg_gen_mov_i32(QREG_MACSR, saved_flags); |
2640 | #if 0 | |
2641 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2642 | if ((s->env->macsr & MACSR_OMC) != 0) { |
2643 | /* Skip the accumulate if the value is already saturated. */ | |
2644 | l1 = gen_new_label(); | |
a7812ae4 | 2645 | tmp = tcg_temp_new(); |
351326a6 | 2646 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2647 | gen_op_jmp_nz32(tmp, l1); |
2648 | } | |
e1f3808e | 2649 | #endif |
acf930aa | 2650 | if (ext & 2) |
e1f3808e | 2651 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2652 | else |
e1f3808e | 2653 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2654 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2655 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2656 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2657 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2658 | else |
e1f3808e PB |
2659 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
2660 | #if 0 | |
2661 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2662 | if (l1 != -1) |
2663 | gen_set_label(l1); | |
e1f3808e | 2664 | #endif |
acf930aa | 2665 | } |
e1f3808e | 2666 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); |
acf930aa PB |
2667 | |
2668 | if (insn & 0x30) { | |
e1f3808e | 2669 | TCGv rw; |
acf930aa | 2670 | rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
e1f3808e | 2671 | tcg_gen_mov_i32(rw, loadval); |
acf930aa PB |
2672 | /* FIXME: Should address writeback happen with the masked or |
2673 | unmasked value? */ | |
2674 | switch ((insn >> 3) & 7) { | |
2675 | case 3: /* Post-increment. */ | |
e1f3808e | 2676 | tcg_gen_addi_i32(AREG(insn, 0), addr, 4); |
acf930aa PB |
2677 | break; |
2678 | case 4: /* Pre-decrement. */ | |
e1f3808e | 2679 | tcg_gen_mov_i32(AREG(insn, 0), addr); |
acf930aa PB |
2680 | } |
2681 | } | |
2682 | } | |
2683 | ||
2684 | DISAS_INSN(from_mac) | |
2685 | { | |
e1f3808e | 2686 | TCGv rx; |
a7812ae4 | 2687 | TCGv_i64 acc; |
e1f3808e | 2688 | int accnum; |
acf930aa PB |
2689 | |
2690 | rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e PB |
2691 | accnum = (insn >> 9) & 3; |
2692 | acc = MACREG(accnum); | |
acf930aa | 2693 | if (s->env->macsr & MACSR_FI) { |
a7812ae4 | 2694 | gen_helper_get_macf(rx, cpu_env, acc); |
acf930aa | 2695 | } else if ((s->env->macsr & MACSR_OMC) == 0) { |
ecc7b3aa | 2696 | tcg_gen_extrl_i64_i32(rx, acc); |
acf930aa | 2697 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2698 | gen_helper_get_macs(rx, acc); |
acf930aa | 2699 | } else { |
e1f3808e PB |
2700 | gen_helper_get_macu(rx, acc); |
2701 | } | |
2702 | if (insn & 0x40) { | |
2703 | tcg_gen_movi_i64(acc, 0); | |
2704 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
acf930aa | 2705 | } |
acf930aa PB |
2706 | } |
2707 | ||
2708 | DISAS_INSN(move_mac) | |
2709 | { | |
e1f3808e | 2710 | /* FIXME: This can be done without a helper. */ |
acf930aa | 2711 | int src; |
e1f3808e | 2712 | TCGv dest; |
acf930aa | 2713 | src = insn & 3; |
e1f3808e PB |
2714 | dest = tcg_const_i32((insn >> 9) & 3); |
2715 | gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); | |
2716 | gen_mac_clear_flags(); | |
2717 | gen_helper_mac_set_flags(cpu_env, dest); | |
acf930aa PB |
2718 | } |
2719 | ||
2720 | DISAS_INSN(from_macsr) | |
2721 | { | |
e1f3808e | 2722 | TCGv reg; |
acf930aa PB |
2723 | |
2724 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e | 2725 | tcg_gen_mov_i32(reg, QREG_MACSR); |
acf930aa PB |
2726 | } |
2727 | ||
2728 | DISAS_INSN(from_mask) | |
2729 | { | |
e1f3808e | 2730 | TCGv reg; |
acf930aa | 2731 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2732 | tcg_gen_mov_i32(reg, QREG_MAC_MASK); |
acf930aa PB |
2733 | } |
2734 | ||
2735 | DISAS_INSN(from_mext) | |
2736 | { | |
e1f3808e PB |
2737 | TCGv reg; |
2738 | TCGv acc; | |
acf930aa | 2739 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2740 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2741 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2742 | gen_helper_get_mac_extf(reg, cpu_env, acc); |
acf930aa | 2743 | else |
e1f3808e | 2744 | gen_helper_get_mac_exti(reg, cpu_env, acc); |
acf930aa PB |
2745 | } |
2746 | ||
2747 | DISAS_INSN(macsr_to_ccr) | |
2748 | { | |
e1f3808e PB |
2749 | tcg_gen_movi_i32(QREG_CC_X, 0); |
2750 | tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf); | |
acf930aa PB |
2751 | s->cc_op = CC_OP_FLAGS; |
2752 | } | |
2753 | ||
2754 | DISAS_INSN(to_mac) | |
2755 | { | |
a7812ae4 | 2756 | TCGv_i64 acc; |
e1f3808e PB |
2757 | TCGv val; |
2758 | int accnum; | |
2759 | accnum = (insn >> 9) & 3; | |
2760 | acc = MACREG(accnum); | |
d4d79bb1 | 2761 | SRC_EA(env, val, OS_LONG, 0, NULL); |
acf930aa | 2762 | if (s->env->macsr & MACSR_FI) { |
e1f3808e PB |
2763 | tcg_gen_ext_i32_i64(acc, val); |
2764 | tcg_gen_shli_i64(acc, acc, 8); | |
acf930aa | 2765 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2766 | tcg_gen_ext_i32_i64(acc, val); |
acf930aa | 2767 | } else { |
e1f3808e | 2768 | tcg_gen_extu_i32_i64(acc, val); |
acf930aa | 2769 | } |
e1f3808e PB |
2770 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); |
2771 | gen_mac_clear_flags(); | |
2772 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); | |
acf930aa PB |
2773 | } |
2774 | ||
2775 | DISAS_INSN(to_macsr) | |
2776 | { | |
e1f3808e | 2777 | TCGv val; |
d4d79bb1 | 2778 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2779 | gen_helper_set_macsr(cpu_env, val); |
acf930aa PB |
2780 | gen_lookup_tb(s); |
2781 | } | |
2782 | ||
2783 | DISAS_INSN(to_mask) | |
2784 | { | |
e1f3808e | 2785 | TCGv val; |
d4d79bb1 | 2786 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2787 | tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); |
acf930aa PB |
2788 | } |
2789 | ||
2790 | DISAS_INSN(to_mext) | |
2791 | { | |
e1f3808e PB |
2792 | TCGv val; |
2793 | TCGv acc; | |
d4d79bb1 | 2794 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2795 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2796 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2797 | gen_helper_set_mac_extf(cpu_env, val, acc); |
acf930aa | 2798 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2799 | gen_helper_set_mac_exts(cpu_env, val, acc); |
acf930aa | 2800 | else |
e1f3808e | 2801 | gen_helper_set_mac_extu(cpu_env, val, acc); |
acf930aa PB |
2802 | } |
2803 | ||
e6e5906b PB |
2804 | static disas_proc opcode_table[65536]; |
2805 | ||
2806 | static void | |
2807 | register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) | |
2808 | { | |
2809 | int i; | |
2810 | int from; | |
2811 | int to; | |
2812 | ||
2813 | /* Sanity check. All set bits must be included in the mask. */ | |
5fc4adf6 PB |
2814 | if (opcode & ~mask) { |
2815 | fprintf(stderr, | |
2816 | "qemu internal error: bogus opcode definition %04x/%04x\n", | |
2817 | opcode, mask); | |
e6e5906b | 2818 | abort(); |
5fc4adf6 | 2819 | } |
e6e5906b PB |
2820 | /* This could probably be cleverer. For now just optimize the case where |
2821 | the top bits are known. */ | |
2822 | /* Find the first zero bit in the mask. */ | |
2823 | i = 0x8000; | |
2824 | while ((i & mask) != 0) | |
2825 | i >>= 1; | |
2826 | /* Iterate over all combinations of this and lower bits. */ | |
2827 | if (i == 0) | |
2828 | i = 1; | |
2829 | else | |
2830 | i <<= 1; | |
2831 | from = opcode & ~(i - 1); | |
2832 | to = from + i; | |
0633879f | 2833 | for (i = from; i < to; i++) { |
e6e5906b PB |
2834 | if ((i & mask) == opcode) |
2835 | opcode_table[i] = proc; | |
0633879f | 2836 | } |
e6e5906b PB |
2837 | } |
2838 | ||
2839 | /* Register m68k opcode handlers. Order is important. | |
2840 | Later insn override earlier ones. */ | |
0402f767 | 2841 | void register_m68k_insns (CPUM68KState *env) |
e6e5906b | 2842 | { |
d315c888 | 2843 | #define INSN(name, opcode, mask, feature) do { \ |
0402f767 | 2844 | if (m68k_feature(env, M68K_FEATURE_##feature)) \ |
d315c888 PB |
2845 | register_opcode(disas_##name, 0x##opcode, 0x##mask); \ |
2846 | } while(0) | |
0402f767 PB |
2847 | INSN(undef, 0000, 0000, CF_ISA_A); |
2848 | INSN(arith_im, 0080, fff8, CF_ISA_A); | |
d315c888 | 2849 | INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); |
0402f767 PB |
2850 | INSN(bitop_reg, 0100, f1c0, CF_ISA_A); |
2851 | INSN(bitop_reg, 0140, f1c0, CF_ISA_A); | |
2852 | INSN(bitop_reg, 0180, f1c0, CF_ISA_A); | |
2853 | INSN(bitop_reg, 01c0, f1c0, CF_ISA_A); | |
2854 | INSN(arith_im, 0280, fff8, CF_ISA_A); | |
d315c888 | 2855 | INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); |
0402f767 | 2856 | INSN(arith_im, 0480, fff8, CF_ISA_A); |
d315c888 | 2857 | INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); |
0402f767 PB |
2858 | INSN(arith_im, 0680, fff8, CF_ISA_A); |
2859 | INSN(bitop_im, 0800, ffc0, CF_ISA_A); | |
2860 | INSN(bitop_im, 0840, ffc0, CF_ISA_A); | |
2861 | INSN(bitop_im, 0880, ffc0, CF_ISA_A); | |
2862 | INSN(bitop_im, 08c0, ffc0, CF_ISA_A); | |
2863 | INSN(arith_im, 0a80, fff8, CF_ISA_A); | |
2864 | INSN(arith_im, 0c00, ff38, CF_ISA_A); | |
2865 | INSN(move, 1000, f000, CF_ISA_A); | |
2866 | INSN(move, 2000, f000, CF_ISA_A); | |
2867 | INSN(move, 3000, f000, CF_ISA_A); | |
d315c888 | 2868 | INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); |
0402f767 PB |
2869 | INSN(negx, 4080, fff8, CF_ISA_A); |
2870 | INSN(move_from_sr, 40c0, fff8, CF_ISA_A); | |
2871 | INSN(lea, 41c0, f1c0, CF_ISA_A); | |
2872 | INSN(clr, 4200, ff00, CF_ISA_A); | |
2873 | INSN(undef, 42c0, ffc0, CF_ISA_A); | |
2874 | INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); | |
2875 | INSN(neg, 4480, fff8, CF_ISA_A); | |
2876 | INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A); | |
2877 | INSN(not, 4680, fff8, CF_ISA_A); | |
2878 | INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); | |
2879 | INSN(pea, 4840, ffc0, CF_ISA_A); | |
2880 | INSN(swap, 4840, fff8, CF_ISA_A); | |
2881 | INSN(movem, 48c0, fbc0, CF_ISA_A); | |
2882 | INSN(ext, 4880, fff8, CF_ISA_A); | |
2883 | INSN(ext, 48c0, fff8, CF_ISA_A); | |
2884 | INSN(ext, 49c0, fff8, CF_ISA_A); | |
2885 | INSN(tst, 4a00, ff00, CF_ISA_A); | |
2886 | INSN(tas, 4ac0, ffc0, CF_ISA_B); | |
2887 | INSN(halt, 4ac8, ffff, CF_ISA_A); | |
2888 | INSN(pulse, 4acc, ffff, CF_ISA_A); | |
2889 | INSN(illegal, 4afc, ffff, CF_ISA_A); | |
2890 | INSN(mull, 4c00, ffc0, CF_ISA_A); | |
2891 | INSN(divl, 4c40, ffc0, CF_ISA_A); | |
2892 | INSN(sats, 4c80, fff8, CF_ISA_B); | |
2893 | INSN(trap, 4e40, fff0, CF_ISA_A); | |
2894 | INSN(link, 4e50, fff8, CF_ISA_A); | |
2895 | INSN(unlk, 4e58, fff8, CF_ISA_A); | |
20dcee94 PB |
2896 | INSN(move_to_usp, 4e60, fff8, USP); |
2897 | INSN(move_from_usp, 4e68, fff8, USP); | |
0402f767 PB |
2898 | INSN(nop, 4e71, ffff, CF_ISA_A); |
2899 | INSN(stop, 4e72, ffff, CF_ISA_A); | |
2900 | INSN(rte, 4e73, ffff, CF_ISA_A); | |
2901 | INSN(rts, 4e75, ffff, CF_ISA_A); | |
2902 | INSN(movec, 4e7b, ffff, CF_ISA_A); | |
2903 | INSN(jump, 4e80, ffc0, CF_ISA_A); | |
2904 | INSN(jump, 4ec0, ffc0, CF_ISA_A); | |
2905 | INSN(addsubq, 5180, f1c0, CF_ISA_A); | |
2906 | INSN(scc, 50c0, f0f8, CF_ISA_A); | |
2907 | INSN(addsubq, 5080, f1c0, CF_ISA_A); | |
2908 | INSN(tpf, 51f8, fff8, CF_ISA_A); | |
d315c888 PB |
2909 | |
2910 | /* Branch instructions. */ | |
0402f767 | 2911 | INSN(branch, 6000, f000, CF_ISA_A); |
d315c888 PB |
2912 | /* Disable long branch instructions, then add back the ones we want. */ |
2913 | INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */ | |
2914 | INSN(branch, 60ff, f0ff, CF_ISA_B); | |
2915 | INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ | |
2916 | INSN(branch, 60ff, ffff, BRAL); | |
2917 | ||
0402f767 PB |
2918 | INSN(moveq, 7000, f100, CF_ISA_A); |
2919 | INSN(mvzs, 7100, f100, CF_ISA_B); | |
2920 | INSN(or, 8000, f000, CF_ISA_A); | |
2921 | INSN(divw, 80c0, f0c0, CF_ISA_A); | |
2922 | INSN(addsub, 9000, f000, CF_ISA_A); | |
2923 | INSN(subx, 9180, f1f8, CF_ISA_A); | |
2924 | INSN(suba, 91c0, f1c0, CF_ISA_A); | |
acf930aa | 2925 | |
0402f767 | 2926 | INSN(undef_mac, a000, f000, CF_ISA_A); |
acf930aa PB |
2927 | INSN(mac, a000, f100, CF_EMAC); |
2928 | INSN(from_mac, a180, f9b0, CF_EMAC); | |
2929 | INSN(move_mac, a110, f9fc, CF_EMAC); | |
2930 | INSN(from_macsr,a980, f9f0, CF_EMAC); | |
2931 | INSN(from_mask, ad80, fff0, CF_EMAC); | |
2932 | INSN(from_mext, ab80, fbf0, CF_EMAC); | |
2933 | INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); | |
2934 | INSN(to_mac, a100, f9c0, CF_EMAC); | |
2935 | INSN(to_macsr, a900, ffc0, CF_EMAC); | |
2936 | INSN(to_mext, ab00, fbc0, CF_EMAC); | |
2937 | INSN(to_mask, ad00, ffc0, CF_EMAC); | |
2938 | ||
0402f767 PB |
2939 | INSN(mov3q, a140, f1c0, CF_ISA_B); |
2940 | INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ | |
2941 | INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ | |
2942 | INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ | |
2943 | INSN(cmp, b080, f1c0, CF_ISA_A); | |
2944 | INSN(cmpa, b1c0, f1c0, CF_ISA_A); | |
2945 | INSN(eor, b180, f1c0, CF_ISA_A); | |
2946 | INSN(and, c000, f000, CF_ISA_A); | |
2947 | INSN(mulw, c0c0, f0c0, CF_ISA_A); | |
2948 | INSN(addsub, d000, f000, CF_ISA_A); | |
2949 | INSN(addx, d180, f1f8, CF_ISA_A); | |
2950 | INSN(adda, d1c0, f1c0, CF_ISA_A); | |
2951 | INSN(shift_im, e080, f0f0, CF_ISA_A); | |
2952 | INSN(shift_reg, e0a0, f0f0, CF_ISA_A); | |
2953 | INSN(undef_fpu, f000, f000, CF_ISA_A); | |
e6e5906b PB |
2954 | INSN(fpu, f200, ffc0, CF_FPU); |
2955 | INSN(fbcc, f280, ffc0, CF_FPU); | |
0633879f PB |
2956 | INSN(frestore, f340, ffc0, CF_FPU); |
2957 | INSN(fsave, f340, ffc0, CF_FPU); | |
0402f767 PB |
2958 | INSN(intouch, f340, ffc0, CF_ISA_A); |
2959 | INSN(cpushl, f428, ff38, CF_ISA_A); | |
2960 | INSN(wddata, fb00, ff00, CF_ISA_A); | |
2961 | INSN(wdebug, fbc0, ffc0, CF_ISA_A); | |
e6e5906b PB |
2962 | #undef INSN |
2963 | } | |
2964 | ||
2965 | /* ??? Some of this implementation is not exception safe. We should always | |
2966 | write back the result to memory before setting the condition codes. */ | |
2b3e3cfe | 2967 | static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) |
e6e5906b PB |
2968 | { |
2969 | uint16_t insn; | |
2970 | ||
d4d79bb1 | 2971 | insn = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2972 | s->pc += 2; |
2973 | ||
d4d79bb1 | 2974 | opcode_table[insn](env, s, insn); |
e6e5906b PB |
2975 | } |
2976 | ||
e6e5906b | 2977 | /* generate intermediate code for basic block 'tb'. */ |
4e5e1215 | 2978 | void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 2979 | { |
4e5e1215 | 2980 | M68kCPU *cpu = m68k_env_get_cpu(env); |
ed2803da | 2981 | CPUState *cs = CPU(cpu); |
e6e5906b | 2982 | DisasContext dc1, *dc = &dc1; |
e6e5906b PB |
2983 | target_ulong pc_start; |
2984 | int pc_offset; | |
2e70f6ef PB |
2985 | int num_insns; |
2986 | int max_insns; | |
e6e5906b PB |
2987 | |
2988 | /* generate intermediate code */ | |
2989 | pc_start = tb->pc; | |
3b46e624 | 2990 | |
e6e5906b PB |
2991 | dc->tb = tb; |
2992 | ||
e6dbd3b3 | 2993 | dc->env = env; |
e6e5906b PB |
2994 | dc->is_jmp = DISAS_NEXT; |
2995 | dc->pc = pc_start; | |
2996 | dc->cc_op = CC_OP_DYNAMIC; | |
ed2803da | 2997 | dc->singlestep_enabled = cs->singlestep_enabled; |
e6e5906b | 2998 | dc->fpcr = env->fpcr; |
0633879f | 2999 | dc->user = (env->sr & SR_S) == 0; |
a7812ae4 | 3000 | dc->done_mac = 0; |
2e70f6ef PB |
3001 | num_insns = 0; |
3002 | max_insns = tb->cflags & CF_COUNT_MASK; | |
190ce7fb | 3003 | if (max_insns == 0) { |
2e70f6ef | 3004 | max_insns = CF_COUNT_MASK; |
190ce7fb RH |
3005 | } |
3006 | if (max_insns > TCG_MAX_INSNS) { | |
3007 | max_insns = TCG_MAX_INSNS; | |
3008 | } | |
2e70f6ef | 3009 | |
cd42d5b2 | 3010 | gen_tb_start(tb); |
e6e5906b | 3011 | do { |
e6e5906b PB |
3012 | pc_offset = dc->pc - pc_start; |
3013 | gen_throws_exception = NULL; | |
667b8e29 | 3014 | tcg_gen_insn_start(dc->pc); |
959082fc | 3015 | num_insns++; |
667b8e29 | 3016 | |
b933066a RH |
3017 | if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { |
3018 | gen_exception(dc, dc->pc, EXCP_DEBUG); | |
3019 | dc->is_jmp = DISAS_JUMP; | |
522a0d4e RH |
3020 | /* The address covered by the breakpoint must be included in |
3021 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
3022 | properly cleared -- thus we increment the PC here so that | |
3023 | the logic setting tb->size below does the right thing. */ | |
3024 | dc->pc += 2; | |
b933066a RH |
3025 | break; |
3026 | } | |
3027 | ||
959082fc | 3028 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
2e70f6ef | 3029 | gen_io_start(); |
667b8e29 RH |
3030 | } |
3031 | ||
510ff0b7 | 3032 | dc->insn_pc = dc->pc; |
e6e5906b | 3033 | disas_m68k_insn(env, dc); |
fe700adb | 3034 | } while (!dc->is_jmp && !tcg_op_buf_full() && |
ed2803da | 3035 | !cs->singlestep_enabled && |
1b530a6d | 3036 | !singlestep && |
2e70f6ef PB |
3037 | (pc_offset) < (TARGET_PAGE_SIZE - 32) && |
3038 | num_insns < max_insns); | |
e6e5906b | 3039 | |
2e70f6ef PB |
3040 | if (tb->cflags & CF_LAST_IO) |
3041 | gen_io_end(); | |
ed2803da | 3042 | if (unlikely(cs->singlestep_enabled)) { |
e6e5906b PB |
3043 | /* Make sure the pc is updated, and raise a debug exception. */ |
3044 | if (!dc->is_jmp) { | |
3045 | gen_flush_cc_op(dc); | |
e1f3808e | 3046 | tcg_gen_movi_i32(QREG_PC, dc->pc); |
e6e5906b | 3047 | } |
31871141 | 3048 | gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); |
e6e5906b PB |
3049 | } else { |
3050 | switch(dc->is_jmp) { | |
3051 | case DISAS_NEXT: | |
3052 | gen_flush_cc_op(dc); | |
3053 | gen_jmp_tb(dc, 0, dc->pc); | |
3054 | break; | |
3055 | default: | |
3056 | case DISAS_JUMP: | |
3057 | case DISAS_UPDATE: | |
3058 | gen_flush_cc_op(dc); | |
3059 | /* indicate that the hash table must be used to find the next TB */ | |
57fec1fe | 3060 | tcg_gen_exit_tb(0); |
e6e5906b PB |
3061 | break; |
3062 | case DISAS_TB_JUMP: | |
3063 | /* nothing more to generate */ | |
3064 | break; | |
3065 | } | |
3066 | } | |
806f352d | 3067 | gen_tb_end(tb, num_insns); |
e6e5906b PB |
3068 | |
3069 | #ifdef DEBUG_DISAS | |
4910e6e4 RH |
3070 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
3071 | && qemu_log_in_addr_range(pc_start)) { | |
93fcfe39 AL |
3072 | qemu_log("----------------\n"); |
3073 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 3074 | log_target_disas(cs, pc_start, dc->pc - pc_start, 0); |
93fcfe39 | 3075 | qemu_log("\n"); |
e6e5906b PB |
3076 | } |
3077 | #endif | |
4e5e1215 RH |
3078 | tb->size = dc->pc - pc_start; |
3079 | tb->icount = num_insns; | |
e6e5906b PB |
3080 | } |
3081 | ||
878096ee AF |
3082 | void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
3083 | int flags) | |
e6e5906b | 3084 | { |
878096ee AF |
3085 | M68kCPU *cpu = M68K_CPU(cs); |
3086 | CPUM68KState *env = &cpu->env; | |
e6e5906b PB |
3087 | int i; |
3088 | uint16_t sr; | |
3089 | CPU_DoubleU u; | |
3090 | for (i = 0; i < 8; i++) | |
3091 | { | |
3092 | u.d = env->fregs[i]; | |
3093 | cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", | |
3094 | i, env->dregs[i], i, env->aregs[i], | |
8fc7cc58 | 3095 | i, u.l.upper, u.l.lower, *(double *)&u.d); |
e6e5906b PB |
3096 | } |
3097 | cpu_fprintf (f, "PC = %08x ", env->pc); | |
3098 | sr = env->sr; | |
3099 | cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-', | |
3100 | (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', | |
3101 | (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); | |
8fc7cc58 | 3102 | cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); |
e6e5906b PB |
3103 | } |
3104 | ||
bad729e2 RH |
3105 | void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, |
3106 | target_ulong *data) | |
d2856f1a | 3107 | { |
bad729e2 | 3108 | env->pc = data[0]; |
d2856f1a | 3109 | } |