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Commit | Line | Data |
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e6e5906b PB |
1 | /* |
2 | * m68k translation | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
e6e5906b | 20 | |
d8416665 | 21 | #include "qemu/osdep.h" |
e6e5906b | 22 | #include "cpu.h" |
76cad711 | 23 | #include "disas/disas.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
57fec1fe | 25 | #include "tcg-op.h" |
1de7afc9 | 26 | #include "qemu/log.h" |
f08b6170 | 27 | #include "exec/cpu_ldst.h" |
e1f3808e | 28 | |
2ef6175a RH |
29 | #include "exec/helper-proto.h" |
30 | #include "exec/helper-gen.h" | |
e6e5906b | 31 | |
a7e30d84 | 32 | #include "trace-tcg.h" |
508127e2 | 33 | #include "exec/log.h" |
a7e30d84 LV |
34 | |
35 | ||
0633879f PB |
36 | //#define DEBUG_DISPATCH 1 |
37 | ||
815a6742 | 38 | /* Fake floating point. */ |
815a6742 | 39 | #define tcg_gen_mov_f64 tcg_gen_mov_i64 |
815a6742 | 40 | #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 |
815a6742 | 41 | #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 |
815a6742 | 42 | |
e1f3808e | 43 | #define DEFO32(name, offset) static TCGv QREG_##name; |
a7812ae4 PB |
44 | #define DEFO64(name, offset) static TCGv_i64 QREG_##name; |
45 | #define DEFF64(name, offset) static TCGv_i64 QREG_##name; | |
e1f3808e PB |
46 | #include "qregs.def" |
47 | #undef DEFO32 | |
48 | #undef DEFO64 | |
49 | #undef DEFF64 | |
50 | ||
259186a7 | 51 | static TCGv_i32 cpu_halted; |
27103424 | 52 | static TCGv_i32 cpu_exception_index; |
259186a7 | 53 | |
1bcea73e | 54 | static TCGv_env cpu_env; |
e1f3808e PB |
55 | |
56 | static char cpu_reg_names[3*8*3 + 5*4]; | |
57 | static TCGv cpu_dregs[8]; | |
58 | static TCGv cpu_aregs[8]; | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fregs[8]; |
60 | static TCGv_i64 cpu_macc[4]; | |
e1f3808e | 61 | |
bcc098b0 LV |
62 | #define REG(insn, pos) (((insn) >> (pos)) & 7) |
63 | #define DREG(insn, pos) cpu_dregs[REG(insn, pos)] | |
64 | #define AREG(insn, pos) cpu_aregs[REG(insn, pos)] | |
65 | #define FREG(insn, pos) cpu_fregs[REG(insn, pos)] | |
e1f3808e PB |
66 | #define MACREG(acc) cpu_macc[acc] |
67 | #define QREG_SP cpu_aregs[7] | |
68 | ||
69 | static TCGv NULL_QREG; | |
a7812ae4 | 70 | #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) |
e1f3808e PB |
71 | /* Used to distinguish stores from bad addressing modes. */ |
72 | static TCGv store_dummy; | |
73 | ||
022c62cb | 74 | #include "exec/gen-icount.h" |
2e70f6ef | 75 | |
e1f3808e PB |
76 | void m68k_tcg_init(void) |
77 | { | |
78 | char *p; | |
79 | int i; | |
80 | ||
e1ccc054 | 81 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7c255043 | 82 | tcg_ctx.tcg_env = cpu_env; |
e1ccc054 RH |
83 | |
84 | #define DEFO32(name, offset) \ | |
85 | QREG_##name = tcg_global_mem_new_i32(cpu_env, \ | |
86 | offsetof(CPUM68KState, offset), #name); | |
87 | #define DEFO64(name, offset) \ | |
88 | QREG_##name = tcg_global_mem_new_i64(cpu_env, \ | |
89 | offsetof(CPUM68KState, offset), #name); | |
90 | #define DEFF64(name, offset) DEFO64(name, offset) | |
e1f3808e PB |
91 | #include "qregs.def" |
92 | #undef DEFO32 | |
93 | #undef DEFO64 | |
94 | #undef DEFF64 | |
95 | ||
e1ccc054 | 96 | cpu_halted = tcg_global_mem_new_i32(cpu_env, |
259186a7 AF |
97 | -offsetof(M68kCPU, env) + |
98 | offsetof(CPUState, halted), "HALTED"); | |
e1ccc054 | 99 | cpu_exception_index = tcg_global_mem_new_i32(cpu_env, |
27103424 AF |
100 | -offsetof(M68kCPU, env) + |
101 | offsetof(CPUState, exception_index), | |
102 | "EXCEPTION"); | |
259186a7 | 103 | |
e1f3808e PB |
104 | p = cpu_reg_names; |
105 | for (i = 0; i < 8; i++) { | |
106 | sprintf(p, "D%d", i); | |
e1ccc054 | 107 | cpu_dregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
108 | offsetof(CPUM68KState, dregs[i]), p); |
109 | p += 3; | |
110 | sprintf(p, "A%d", i); | |
e1ccc054 | 111 | cpu_aregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
112 | offsetof(CPUM68KState, aregs[i]), p); |
113 | p += 3; | |
114 | sprintf(p, "F%d", i); | |
e1ccc054 | 115 | cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
116 | offsetof(CPUM68KState, fregs[i]), p); |
117 | p += 3; | |
118 | } | |
119 | for (i = 0; i < 4; i++) { | |
120 | sprintf(p, "ACC%d", i); | |
e1ccc054 | 121 | cpu_macc[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
122 | offsetof(CPUM68KState, macc[i]), p); |
123 | p += 5; | |
124 | } | |
125 | ||
e1ccc054 RH |
126 | NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL"); |
127 | store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL"); | |
e1f3808e PB |
128 | } |
129 | ||
e6e5906b PB |
130 | /* internal defines */ |
131 | typedef struct DisasContext { | |
e6dbd3b3 | 132 | CPUM68KState *env; |
510ff0b7 | 133 | target_ulong insn_pc; /* Start of the current instruction. */ |
e6e5906b PB |
134 | target_ulong pc; |
135 | int is_jmp; | |
9fdb533f | 136 | CCOp cc_op; /* Current CC operation */ |
620c6cf6 | 137 | int cc_op_synced; |
0633879f | 138 | int user; |
e6e5906b PB |
139 | uint32_t fpcr; |
140 | struct TranslationBlock *tb; | |
141 | int singlestep_enabled; | |
a7812ae4 PB |
142 | TCGv_i64 mactmp; |
143 | int done_mac; | |
e6e5906b PB |
144 | } DisasContext; |
145 | ||
146 | #define DISAS_JUMP_NEXT 4 | |
147 | ||
0633879f PB |
148 | #if defined(CONFIG_USER_ONLY) |
149 | #define IS_USER(s) 1 | |
150 | #else | |
151 | #define IS_USER(s) s->user | |
152 | #endif | |
153 | ||
e6e5906b PB |
154 | /* XXX: move that elsewhere */ |
155 | /* ??? Fix exceptions. */ | |
156 | static void *gen_throws_exception; | |
157 | #define gen_last_qop NULL | |
158 | ||
d4d79bb1 | 159 | typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); |
e6e5906b | 160 | |
0633879f | 161 | #ifdef DEBUG_DISPATCH |
d4d79bb1 BS |
162 | #define DISAS_INSN(name) \ |
163 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
164 | uint16_t insn); \ | |
165 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
166 | uint16_t insn) \ | |
167 | { \ | |
168 | qemu_log("Dispatch " #name "\n"); \ | |
a1ff1930 | 169 | real_disas_##name(env, s, insn); \ |
d4d79bb1 BS |
170 | } \ |
171 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
172 | uint16_t insn) | |
0633879f | 173 | #else |
d4d79bb1 BS |
174 | #define DISAS_INSN(name) \ |
175 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
176 | uint16_t insn) | |
0633879f | 177 | #endif |
e6e5906b | 178 | |
9fdb533f | 179 | static const uint8_t cc_op_live[CC_OP_NB] = { |
620c6cf6 RH |
180 | [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X, |
181 | [CC_OP_ADD] = CCF_X | CCF_N | CCF_V, | |
182 | [CC_OP_SUB] = CCF_X | CCF_N | CCF_V, | |
183 | [CC_OP_CMP] = CCF_X | CCF_N | CCF_V, | |
184 | [CC_OP_LOGIC] = CCF_X | CCF_N | |
9fdb533f LV |
185 | }; |
186 | ||
187 | static void set_cc_op(DisasContext *s, CCOp op) | |
188 | { | |
620c6cf6 | 189 | CCOp old_op = s->cc_op; |
9fdb533f LV |
190 | int dead; |
191 | ||
620c6cf6 | 192 | if (old_op == op) { |
9fdb533f LV |
193 | return; |
194 | } | |
620c6cf6 RH |
195 | s->cc_op = op; |
196 | s->cc_op_synced = 0; | |
9fdb533f | 197 | |
620c6cf6 RH |
198 | /* Discard CC computation that will no longer be used. |
199 | Note that X and N are never dead. */ | |
200 | dead = cc_op_live[old_op] & ~cc_op_live[op]; | |
201 | if (dead & CCF_C) { | |
202 | tcg_gen_discard_i32(QREG_CC_C); | |
9fdb533f | 203 | } |
620c6cf6 RH |
204 | if (dead & CCF_Z) { |
205 | tcg_gen_discard_i32(QREG_CC_Z); | |
9fdb533f | 206 | } |
620c6cf6 RH |
207 | if (dead & CCF_V) { |
208 | tcg_gen_discard_i32(QREG_CC_V); | |
9fdb533f | 209 | } |
9fdb533f LV |
210 | } |
211 | ||
212 | /* Update the CPU env CC_OP state. */ | |
620c6cf6 | 213 | static void update_cc_op(DisasContext *s) |
9fdb533f | 214 | { |
620c6cf6 RH |
215 | if (!s->cc_op_synced) { |
216 | s->cc_op_synced = 1; | |
9fdb533f LV |
217 | tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); |
218 | } | |
219 | } | |
220 | ||
e6e5906b PB |
221 | /* Generate a load from the specified address. Narrow values are |
222 | sign extended to full register width. */ | |
e1f3808e | 223 | static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) |
e6e5906b | 224 | { |
e1f3808e PB |
225 | TCGv tmp; |
226 | int index = IS_USER(s); | |
a7812ae4 | 227 | tmp = tcg_temp_new_i32(); |
e6e5906b PB |
228 | switch(opsize) { |
229 | case OS_BYTE: | |
e6e5906b | 230 | if (sign) |
e1f3808e | 231 | tcg_gen_qemu_ld8s(tmp, addr, index); |
e6e5906b | 232 | else |
e1f3808e | 233 | tcg_gen_qemu_ld8u(tmp, addr, index); |
e6e5906b PB |
234 | break; |
235 | case OS_WORD: | |
e6e5906b | 236 | if (sign) |
e1f3808e | 237 | tcg_gen_qemu_ld16s(tmp, addr, index); |
e6e5906b | 238 | else |
e1f3808e | 239 | tcg_gen_qemu_ld16u(tmp, addr, index); |
e6e5906b PB |
240 | break; |
241 | case OS_LONG: | |
e6e5906b | 242 | case OS_SINGLE: |
a7812ae4 | 243 | tcg_gen_qemu_ld32u(tmp, addr, index); |
e6e5906b PB |
244 | break; |
245 | default: | |
7372c2b9 | 246 | g_assert_not_reached(); |
e6e5906b PB |
247 | } |
248 | gen_throws_exception = gen_last_qop; | |
249 | return tmp; | |
250 | } | |
251 | ||
a7812ae4 PB |
252 | static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) |
253 | { | |
254 | TCGv_i64 tmp; | |
255 | int index = IS_USER(s); | |
a7812ae4 PB |
256 | tmp = tcg_temp_new_i64(); |
257 | tcg_gen_qemu_ldf64(tmp, addr, index); | |
258 | gen_throws_exception = gen_last_qop; | |
259 | return tmp; | |
260 | } | |
261 | ||
e6e5906b | 262 | /* Generate a store. */ |
e1f3808e | 263 | static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) |
e6e5906b | 264 | { |
e1f3808e | 265 | int index = IS_USER(s); |
e6e5906b PB |
266 | switch(opsize) { |
267 | case OS_BYTE: | |
e1f3808e | 268 | tcg_gen_qemu_st8(val, addr, index); |
e6e5906b PB |
269 | break; |
270 | case OS_WORD: | |
e1f3808e | 271 | tcg_gen_qemu_st16(val, addr, index); |
e6e5906b PB |
272 | break; |
273 | case OS_LONG: | |
e6e5906b | 274 | case OS_SINGLE: |
a7812ae4 | 275 | tcg_gen_qemu_st32(val, addr, index); |
e6e5906b PB |
276 | break; |
277 | default: | |
7372c2b9 | 278 | g_assert_not_reached(); |
e6e5906b PB |
279 | } |
280 | gen_throws_exception = gen_last_qop; | |
281 | } | |
282 | ||
a7812ae4 PB |
283 | static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) |
284 | { | |
285 | int index = IS_USER(s); | |
a7812ae4 PB |
286 | tcg_gen_qemu_stf64(val, addr, index); |
287 | gen_throws_exception = gen_last_qop; | |
288 | } | |
289 | ||
e1f3808e PB |
290 | typedef enum { |
291 | EA_STORE, | |
292 | EA_LOADU, | |
293 | EA_LOADS | |
294 | } ea_what; | |
295 | ||
e6e5906b PB |
296 | /* Generate an unsigned load if VAL is 0 a signed load if val is -1, |
297 | otherwise generate a store. */ | |
e1f3808e PB |
298 | static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, |
299 | ea_what what) | |
e6e5906b | 300 | { |
e1f3808e | 301 | if (what == EA_STORE) { |
0633879f | 302 | gen_store(s, opsize, addr, val); |
e1f3808e | 303 | return store_dummy; |
e6e5906b | 304 | } else { |
e1f3808e | 305 | return gen_load(s, opsize, addr, what == EA_LOADS); |
e6e5906b PB |
306 | } |
307 | } | |
308 | ||
28b68cd7 LV |
309 | /* Read a 16-bit immediate constant */ |
310 | static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) | |
311 | { | |
312 | uint16_t im; | |
313 | im = cpu_lduw_code(env, s->pc); | |
314 | s->pc += 2; | |
315 | return im; | |
316 | } | |
317 | ||
318 | /* Read an 8-bit immediate constant */ | |
319 | static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s) | |
320 | { | |
321 | return read_im16(env, s); | |
322 | } | |
323 | ||
e6dbd3b3 | 324 | /* Read a 32-bit immediate constant. */ |
d4d79bb1 | 325 | static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) |
e6dbd3b3 PB |
326 | { |
327 | uint32_t im; | |
28b68cd7 LV |
328 | im = read_im16(env, s) << 16; |
329 | im |= 0xffff & read_im16(env, s); | |
e6dbd3b3 PB |
330 | return im; |
331 | } | |
332 | ||
333 | /* Calculate and address index. */ | |
e1f3808e | 334 | static TCGv gen_addr_index(uint16_t ext, TCGv tmp) |
e6dbd3b3 | 335 | { |
e1f3808e | 336 | TCGv add; |
e6dbd3b3 PB |
337 | int scale; |
338 | ||
339 | add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); | |
340 | if ((ext & 0x800) == 0) { | |
e1f3808e | 341 | tcg_gen_ext16s_i32(tmp, add); |
e6dbd3b3 PB |
342 | add = tmp; |
343 | } | |
344 | scale = (ext >> 9) & 3; | |
345 | if (scale != 0) { | |
e1f3808e | 346 | tcg_gen_shli_i32(tmp, add, scale); |
e6dbd3b3 PB |
347 | add = tmp; |
348 | } | |
349 | return add; | |
350 | } | |
351 | ||
e1f3808e PB |
352 | /* Handle a base + index + displacement effective addresss. |
353 | A NULL_QREG base means pc-relative. */ | |
a4356126 | 354 | static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) |
e6e5906b | 355 | { |
e6e5906b PB |
356 | uint32_t offset; |
357 | uint16_t ext; | |
e1f3808e PB |
358 | TCGv add; |
359 | TCGv tmp; | |
e6dbd3b3 | 360 | uint32_t bd, od; |
e6e5906b PB |
361 | |
362 | offset = s->pc; | |
28b68cd7 | 363 | ext = read_im16(env, s); |
e6dbd3b3 PB |
364 | |
365 | if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) | |
e1f3808e | 366 | return NULL_QREG; |
e6dbd3b3 | 367 | |
d8633620 LV |
368 | if (m68k_feature(s->env, M68K_FEATURE_M68000) && |
369 | !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) { | |
370 | ext &= ~(3 << 9); | |
371 | } | |
372 | ||
e6dbd3b3 PB |
373 | if (ext & 0x100) { |
374 | /* full extension word format */ | |
375 | if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) | |
e1f3808e | 376 | return NULL_QREG; |
e6dbd3b3 PB |
377 | |
378 | if ((ext & 0x30) > 0x10) { | |
379 | /* base displacement */ | |
380 | if ((ext & 0x30) == 0x20) { | |
28b68cd7 | 381 | bd = (int16_t)read_im16(env, s); |
e6dbd3b3 | 382 | } else { |
d4d79bb1 | 383 | bd = read_im32(env, s); |
e6dbd3b3 PB |
384 | } |
385 | } else { | |
386 | bd = 0; | |
387 | } | |
a7812ae4 | 388 | tmp = tcg_temp_new(); |
e6dbd3b3 PB |
389 | if ((ext & 0x44) == 0) { |
390 | /* pre-index */ | |
391 | add = gen_addr_index(ext, tmp); | |
392 | } else { | |
e1f3808e | 393 | add = NULL_QREG; |
e6dbd3b3 PB |
394 | } |
395 | if ((ext & 0x80) == 0) { | |
396 | /* base not suppressed */ | |
e1f3808e | 397 | if (IS_NULL_QREG(base)) { |
351326a6 | 398 | base = tcg_const_i32(offset + bd); |
e6dbd3b3 PB |
399 | bd = 0; |
400 | } | |
e1f3808e PB |
401 | if (!IS_NULL_QREG(add)) { |
402 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 PB |
403 | add = tmp; |
404 | } else { | |
405 | add = base; | |
406 | } | |
407 | } | |
e1f3808e | 408 | if (!IS_NULL_QREG(add)) { |
e6dbd3b3 | 409 | if (bd != 0) { |
e1f3808e | 410 | tcg_gen_addi_i32(tmp, add, bd); |
e6dbd3b3 PB |
411 | add = tmp; |
412 | } | |
413 | } else { | |
351326a6 | 414 | add = tcg_const_i32(bd); |
e6dbd3b3 PB |
415 | } |
416 | if ((ext & 3) != 0) { | |
417 | /* memory indirect */ | |
418 | base = gen_load(s, OS_LONG, add, 0); | |
419 | if ((ext & 0x44) == 4) { | |
420 | add = gen_addr_index(ext, tmp); | |
e1f3808e | 421 | tcg_gen_add_i32(tmp, add, base); |
e6dbd3b3 PB |
422 | add = tmp; |
423 | } else { | |
424 | add = base; | |
425 | } | |
426 | if ((ext & 3) > 1) { | |
427 | /* outer displacement */ | |
428 | if ((ext & 3) == 2) { | |
28b68cd7 | 429 | od = (int16_t)read_im16(env, s); |
e6dbd3b3 | 430 | } else { |
d4d79bb1 | 431 | od = read_im32(env, s); |
e6dbd3b3 PB |
432 | } |
433 | } else { | |
434 | od = 0; | |
435 | } | |
436 | if (od != 0) { | |
e1f3808e | 437 | tcg_gen_addi_i32(tmp, add, od); |
e6dbd3b3 PB |
438 | add = tmp; |
439 | } | |
440 | } | |
e6e5906b | 441 | } else { |
e6dbd3b3 | 442 | /* brief extension word format */ |
a7812ae4 | 443 | tmp = tcg_temp_new(); |
e6dbd3b3 | 444 | add = gen_addr_index(ext, tmp); |
e1f3808e PB |
445 | if (!IS_NULL_QREG(base)) { |
446 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 | 447 | if ((int8_t)ext) |
e1f3808e | 448 | tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); |
e6dbd3b3 | 449 | } else { |
e1f3808e | 450 | tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); |
e6dbd3b3 PB |
451 | } |
452 | add = tmp; | |
e6e5906b | 453 | } |
e6dbd3b3 | 454 | return add; |
e6e5906b PB |
455 | } |
456 | ||
e6e5906b | 457 | /* Evaluate all the CC flags. */ |
9fdb533f | 458 | |
620c6cf6 | 459 | static void gen_flush_flags(DisasContext *s) |
e6e5906b | 460 | { |
620c6cf6 RH |
461 | TCGv tmp; |
462 | ||
463 | switch (s->cc_op) { | |
464 | case CC_OP_FLAGS: | |
e6e5906b | 465 | return; |
620c6cf6 RH |
466 | case CC_OP_DYNAMIC: |
467 | gen_helper_flush_flags(cpu_env, QREG_CC_OP); | |
468 | break; | |
469 | default: | |
470 | tmp = tcg_const_i32(s->cc_op); | |
471 | gen_helper_flush_flags(cpu_env, tmp); | |
472 | tcg_temp_free(tmp); | |
473 | break; | |
474 | } | |
475 | ||
476 | /* Note that flush_flags also assigned to env->cc_op. */ | |
477 | s->cc_op = CC_OP_FLAGS; | |
478 | s->cc_op_synced = 1; | |
479 | } | |
480 | ||
481 | /* Sign or zero extend a value. */ | |
482 | ||
483 | static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign) | |
484 | { | |
485 | switch (opsize) { | |
486 | case OS_BYTE: | |
487 | if (sign) { | |
488 | tcg_gen_ext8s_i32(res, val); | |
489 | } else { | |
490 | tcg_gen_ext8u_i32(res, val); | |
491 | } | |
492 | break; | |
493 | case OS_WORD: | |
494 | if (sign) { | |
495 | tcg_gen_ext16s_i32(res, val); | |
496 | } else { | |
497 | tcg_gen_ext16u_i32(res, val); | |
498 | } | |
499 | break; | |
500 | case OS_LONG: | |
501 | tcg_gen_mov_i32(res, val); | |
502 | break; | |
503 | default: | |
504 | g_assert_not_reached(); | |
9fdb533f | 505 | } |
e6e5906b PB |
506 | } |
507 | ||
620c6cf6 RH |
508 | static TCGv gen_extend(TCGv val, int opsize, int sign) |
509 | { | |
510 | TCGv tmp; | |
511 | ||
512 | if (opsize == OS_LONG) { | |
513 | tmp = val; | |
514 | } else { | |
515 | tmp = tcg_temp_new(); | |
516 | gen_ext(tmp, val, opsize, sign); | |
517 | } | |
518 | ||
519 | return tmp; | |
520 | } | |
5dbb6784 LV |
521 | |
522 | static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) | |
e1f3808e | 523 | { |
620c6cf6 RH |
524 | gen_ext(QREG_CC_N, val, opsize, 1); |
525 | set_cc_op(s, CC_OP_LOGIC); | |
e1f3808e PB |
526 | } |
527 | ||
528 | static void gen_update_cc_add(TCGv dest, TCGv src) | |
529 | { | |
620c6cf6 RH |
530 | tcg_gen_mov_i32(QREG_CC_N, dest); |
531 | tcg_gen_mov_i32(QREG_CC_V, src); | |
e1f3808e PB |
532 | } |
533 | ||
e6e5906b PB |
534 | static inline int opsize_bytes(int opsize) |
535 | { | |
536 | switch (opsize) { | |
537 | case OS_BYTE: return 1; | |
538 | case OS_WORD: return 2; | |
539 | case OS_LONG: return 4; | |
540 | case OS_SINGLE: return 4; | |
541 | case OS_DOUBLE: return 8; | |
7ef25cdd LV |
542 | case OS_EXTENDED: return 12; |
543 | case OS_PACKED: return 12; | |
544 | default: | |
545 | g_assert_not_reached(); | |
546 | } | |
547 | } | |
548 | ||
549 | static inline int insn_opsize(int insn) | |
550 | { | |
551 | switch ((insn >> 6) & 3) { | |
552 | case 0: return OS_BYTE; | |
553 | case 1: return OS_WORD; | |
554 | case 2: return OS_LONG; | |
e6e5906b | 555 | default: |
7372c2b9 | 556 | g_assert_not_reached(); |
e6e5906b PB |
557 | } |
558 | } | |
559 | ||
560 | /* Assign value to a register. If the width is less than the register width | |
561 | only the low part of the register is set. */ | |
e1f3808e | 562 | static void gen_partset_reg(int opsize, TCGv reg, TCGv val) |
e6e5906b | 563 | { |
e1f3808e | 564 | TCGv tmp; |
e6e5906b PB |
565 | switch (opsize) { |
566 | case OS_BYTE: | |
e1f3808e | 567 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
a7812ae4 | 568 | tmp = tcg_temp_new(); |
e1f3808e PB |
569 | tcg_gen_ext8u_i32(tmp, val); |
570 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
571 | break; |
572 | case OS_WORD: | |
e1f3808e | 573 | tcg_gen_andi_i32(reg, reg, 0xffff0000); |
a7812ae4 | 574 | tmp = tcg_temp_new(); |
e1f3808e PB |
575 | tcg_gen_ext16u_i32(tmp, val); |
576 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
577 | break; |
578 | case OS_LONG: | |
e6e5906b | 579 | case OS_SINGLE: |
a7812ae4 | 580 | tcg_gen_mov_i32(reg, val); |
e6e5906b PB |
581 | break; |
582 | default: | |
7372c2b9 | 583 | g_assert_not_reached(); |
e6e5906b PB |
584 | } |
585 | } | |
586 | ||
e6e5906b | 587 | /* Generate code for an "effective address". Does not adjust the base |
1addc7c5 | 588 | register for autoincrement addressing modes. */ |
d4d79bb1 BS |
589 | static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
590 | int opsize) | |
e6e5906b | 591 | { |
e1f3808e PB |
592 | TCGv reg; |
593 | TCGv tmp; | |
e6e5906b PB |
594 | uint16_t ext; |
595 | uint32_t offset; | |
596 | ||
e6e5906b PB |
597 | switch ((insn >> 3) & 7) { |
598 | case 0: /* Data register direct. */ | |
599 | case 1: /* Address register direct. */ | |
e1f3808e | 600 | return NULL_QREG; |
e6e5906b PB |
601 | case 2: /* Indirect register */ |
602 | case 3: /* Indirect postincrement. */ | |
e1f3808e | 603 | return AREG(insn, 0); |
e6e5906b | 604 | case 4: /* Indirect predecrememnt. */ |
e1f3808e | 605 | reg = AREG(insn, 0); |
a7812ae4 | 606 | tmp = tcg_temp_new(); |
e1f3808e | 607 | tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); |
e6e5906b PB |
608 | return tmp; |
609 | case 5: /* Indirect displacement. */ | |
e1f3808e | 610 | reg = AREG(insn, 0); |
a7812ae4 | 611 | tmp = tcg_temp_new(); |
28b68cd7 | 612 | ext = read_im16(env, s); |
e1f3808e | 613 | tcg_gen_addi_i32(tmp, reg, (int16_t)ext); |
e6e5906b PB |
614 | return tmp; |
615 | case 6: /* Indirect index + displacement. */ | |
e1f3808e | 616 | reg = AREG(insn, 0); |
a4356126 | 617 | return gen_lea_indexed(env, s, reg); |
e6e5906b | 618 | case 7: /* Other */ |
e1f3808e | 619 | switch (insn & 7) { |
e6e5906b | 620 | case 0: /* Absolute short. */ |
28b68cd7 | 621 | offset = (int16_t)read_im16(env, s); |
351326a6 | 622 | return tcg_const_i32(offset); |
e6e5906b | 623 | case 1: /* Absolute long. */ |
d4d79bb1 | 624 | offset = read_im32(env, s); |
351326a6 | 625 | return tcg_const_i32(offset); |
e6e5906b | 626 | case 2: /* pc displacement */ |
e6e5906b | 627 | offset = s->pc; |
28b68cd7 | 628 | offset += (int16_t)read_im16(env, s); |
351326a6 | 629 | return tcg_const_i32(offset); |
e6e5906b | 630 | case 3: /* pc index+displacement. */ |
a4356126 | 631 | return gen_lea_indexed(env, s, NULL_QREG); |
e6e5906b PB |
632 | case 4: /* Immediate. */ |
633 | default: | |
e1f3808e | 634 | return NULL_QREG; |
e6e5906b PB |
635 | } |
636 | } | |
637 | /* Should never happen. */ | |
e1f3808e | 638 | return NULL_QREG; |
e6e5906b PB |
639 | } |
640 | ||
641 | /* Helper function for gen_ea. Reuse the computed address between the | |
642 | for read/write operands. */ | |
d4d79bb1 BS |
643 | static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s, |
644 | uint16_t insn, int opsize, TCGv val, | |
645 | TCGv *addrp, ea_what what) | |
e6e5906b | 646 | { |
e1f3808e | 647 | TCGv tmp; |
e6e5906b | 648 | |
e1f3808e | 649 | if (addrp && what == EA_STORE) { |
e6e5906b PB |
650 | tmp = *addrp; |
651 | } else { | |
d4d79bb1 | 652 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
653 | if (IS_NULL_QREG(tmp)) |
654 | return tmp; | |
e6e5906b PB |
655 | if (addrp) |
656 | *addrp = tmp; | |
657 | } | |
e1f3808e | 658 | return gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
659 | } |
660 | ||
f38f7a84 | 661 | /* Generate code to load/store a value from/into an EA. If VAL > 0 this is |
e6e5906b PB |
662 | a write otherwise it is a read (0 == sign extend, -1 == zero extend). |
663 | ADDRP is non-null for readwrite operands. */ | |
d4d79bb1 BS |
664 | static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
665 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
e6e5906b | 666 | { |
e1f3808e PB |
667 | TCGv reg; |
668 | TCGv result; | |
e6e5906b PB |
669 | uint32_t offset; |
670 | ||
e6e5906b PB |
671 | switch ((insn >> 3) & 7) { |
672 | case 0: /* Data register direct. */ | |
e1f3808e PB |
673 | reg = DREG(insn, 0); |
674 | if (what == EA_STORE) { | |
e6e5906b | 675 | gen_partset_reg(opsize, reg, val); |
e1f3808e | 676 | return store_dummy; |
e6e5906b | 677 | } else { |
e1f3808e | 678 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
679 | } |
680 | case 1: /* Address register direct. */ | |
e1f3808e PB |
681 | reg = AREG(insn, 0); |
682 | if (what == EA_STORE) { | |
683 | tcg_gen_mov_i32(reg, val); | |
684 | return store_dummy; | |
e6e5906b | 685 | } else { |
e1f3808e | 686 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
687 | } |
688 | case 2: /* Indirect register */ | |
e1f3808e PB |
689 | reg = AREG(insn, 0); |
690 | return gen_ldst(s, opsize, reg, val, what); | |
e6e5906b | 691 | case 3: /* Indirect postincrement. */ |
e1f3808e PB |
692 | reg = AREG(insn, 0); |
693 | result = gen_ldst(s, opsize, reg, val, what); | |
e6e5906b PB |
694 | /* ??? This is not exception safe. The instruction may still |
695 | fault after this point. */ | |
e1f3808e PB |
696 | if (what == EA_STORE || !addrp) |
697 | tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize)); | |
e6e5906b PB |
698 | return result; |
699 | case 4: /* Indirect predecrememnt. */ | |
700 | { | |
e1f3808e PB |
701 | TCGv tmp; |
702 | if (addrp && what == EA_STORE) { | |
e6e5906b PB |
703 | tmp = *addrp; |
704 | } else { | |
d4d79bb1 | 705 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
706 | if (IS_NULL_QREG(tmp)) |
707 | return tmp; | |
e6e5906b PB |
708 | if (addrp) |
709 | *addrp = tmp; | |
710 | } | |
e1f3808e | 711 | result = gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
712 | /* ??? This is not exception safe. The instruction may still |
713 | fault after this point. */ | |
e1f3808e PB |
714 | if (what == EA_STORE || !addrp) { |
715 | reg = AREG(insn, 0); | |
716 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
717 | } |
718 | } | |
719 | return result; | |
720 | case 5: /* Indirect displacement. */ | |
721 | case 6: /* Indirect index + displacement. */ | |
d4d79bb1 | 722 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b | 723 | case 7: /* Other */ |
e1f3808e | 724 | switch (insn & 7) { |
e6e5906b PB |
725 | case 0: /* Absolute short. */ |
726 | case 1: /* Absolute long. */ | |
727 | case 2: /* pc displacement */ | |
728 | case 3: /* pc index+displacement. */ | |
d4d79bb1 | 729 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b PB |
730 | case 4: /* Immediate. */ |
731 | /* Sign extend values for consistency. */ | |
732 | switch (opsize) { | |
733 | case OS_BYTE: | |
31871141 | 734 | if (what == EA_LOADS) { |
28b68cd7 | 735 | offset = (int8_t)read_im8(env, s); |
31871141 | 736 | } else { |
28b68cd7 | 737 | offset = read_im8(env, s); |
31871141 | 738 | } |
e6e5906b PB |
739 | break; |
740 | case OS_WORD: | |
31871141 | 741 | if (what == EA_LOADS) { |
28b68cd7 | 742 | offset = (int16_t)read_im16(env, s); |
31871141 | 743 | } else { |
28b68cd7 | 744 | offset = read_im16(env, s); |
31871141 | 745 | } |
e6e5906b PB |
746 | break; |
747 | case OS_LONG: | |
d4d79bb1 | 748 | offset = read_im32(env, s); |
e6e5906b PB |
749 | break; |
750 | default: | |
7372c2b9 | 751 | g_assert_not_reached(); |
e6e5906b | 752 | } |
e1f3808e | 753 | return tcg_const_i32(offset); |
e6e5906b | 754 | default: |
e1f3808e | 755 | return NULL_QREG; |
e6e5906b PB |
756 | } |
757 | } | |
758 | /* Should never happen. */ | |
e1f3808e | 759 | return NULL_QREG; |
e6e5906b PB |
760 | } |
761 | ||
6a432295 RH |
762 | typedef struct { |
763 | TCGCond tcond; | |
764 | bool g1; | |
765 | bool g2; | |
766 | TCGv v1; | |
767 | TCGv v2; | |
768 | } DisasCompare; | |
769 | ||
770 | static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond) | |
e6e5906b | 771 | { |
620c6cf6 RH |
772 | TCGv tmp, tmp2; |
773 | TCGCond tcond; | |
9d896621 | 774 | CCOp op = s->cc_op; |
e6e5906b | 775 | |
9d896621 RH |
776 | /* The CC_OP_CMP form can handle most normal comparisons directly. */ |
777 | if (op == CC_OP_CMP) { | |
778 | c->g1 = c->g2 = 1; | |
779 | c->v1 = QREG_CC_N; | |
780 | c->v2 = QREG_CC_V; | |
781 | switch (cond) { | |
782 | case 2: /* HI */ | |
783 | case 3: /* LS */ | |
784 | tcond = TCG_COND_LEU; | |
785 | goto done; | |
786 | case 4: /* CC */ | |
787 | case 5: /* CS */ | |
788 | tcond = TCG_COND_LTU; | |
789 | goto done; | |
790 | case 6: /* NE */ | |
791 | case 7: /* EQ */ | |
792 | tcond = TCG_COND_EQ; | |
793 | goto done; | |
794 | case 10: /* PL */ | |
795 | case 11: /* MI */ | |
796 | c->g1 = c->g2 = 0; | |
797 | c->v2 = tcg_const_i32(0); | |
798 | c->v1 = tmp = tcg_temp_new(); | |
799 | tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V); | |
800 | /* fallthru */ | |
801 | case 12: /* GE */ | |
802 | case 13: /* LT */ | |
803 | tcond = TCG_COND_LT; | |
804 | goto done; | |
805 | case 14: /* GT */ | |
806 | case 15: /* LE */ | |
807 | tcond = TCG_COND_LE; | |
808 | goto done; | |
809 | } | |
810 | } | |
6a432295 RH |
811 | |
812 | c->g1 = 1; | |
813 | c->g2 = 0; | |
814 | c->v2 = tcg_const_i32(0); | |
815 | ||
e6e5906b PB |
816 | switch (cond) { |
817 | case 0: /* T */ | |
e6e5906b | 818 | case 1: /* F */ |
6a432295 RH |
819 | c->v1 = c->v2; |
820 | tcond = TCG_COND_NEVER; | |
9d896621 RH |
821 | goto done; |
822 | case 14: /* GT (!(Z || (N ^ V))) */ | |
823 | case 15: /* LE (Z || (N ^ V)) */ | |
824 | /* Logic operations clear V, which simplifies LE to (Z || N), | |
825 | and since Z and N are co-located, this becomes a normal | |
826 | comparison vs N. */ | |
827 | if (op == CC_OP_LOGIC) { | |
828 | c->v1 = QREG_CC_N; | |
829 | tcond = TCG_COND_LE; | |
830 | goto done; | |
831 | } | |
6a432295 | 832 | break; |
9d896621 RH |
833 | case 12: /* GE (!(N ^ V)) */ |
834 | case 13: /* LT (N ^ V) */ | |
835 | /* Logic operations clear V, which simplifies this to N. */ | |
836 | if (op != CC_OP_LOGIC) { | |
837 | break; | |
838 | } | |
839 | /* fallthru */ | |
840 | case 10: /* PL (!N) */ | |
841 | case 11: /* MI (N) */ | |
842 | /* Several cases represent N normally. */ | |
843 | if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) { | |
844 | c->v1 = QREG_CC_N; | |
845 | tcond = TCG_COND_LT; | |
846 | goto done; | |
847 | } | |
848 | break; | |
849 | case 6: /* NE (!Z) */ | |
850 | case 7: /* EQ (Z) */ | |
851 | /* Some cases fold Z into N. */ | |
852 | if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) { | |
853 | tcond = TCG_COND_EQ; | |
854 | c->v1 = QREG_CC_N; | |
855 | goto done; | |
856 | } | |
857 | break; | |
858 | case 4: /* CC (!C) */ | |
859 | case 5: /* CS (C) */ | |
860 | /* Some cases fold C into X. */ | |
861 | if (op == CC_OP_ADD || op == CC_OP_SUB) { | |
862 | tcond = TCG_COND_NE; | |
863 | c->v1 = QREG_CC_X; | |
864 | goto done; | |
865 | } | |
866 | /* fallthru */ | |
867 | case 8: /* VC (!V) */ | |
868 | case 9: /* VS (V) */ | |
869 | /* Logic operations clear V and C. */ | |
870 | if (op == CC_OP_LOGIC) { | |
871 | tcond = TCG_COND_NEVER; | |
872 | c->v1 = c->v2; | |
873 | goto done; | |
874 | } | |
875 | break; | |
876 | } | |
877 | ||
878 | /* Otherwise, flush flag state to CC_OP_FLAGS. */ | |
879 | gen_flush_flags(s); | |
880 | ||
881 | switch (cond) { | |
882 | case 0: /* T */ | |
883 | case 1: /* F */ | |
884 | default: | |
885 | /* Invalid, or handled above. */ | |
886 | abort(); | |
620c6cf6 | 887 | case 2: /* HI (!C && !Z) -> !(C || Z)*/ |
e6e5906b | 888 | case 3: /* LS (C || Z) */ |
6a432295 RH |
889 | c->v1 = tmp = tcg_temp_new(); |
890 | c->g1 = 0; | |
891 | tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); | |
620c6cf6 | 892 | tcg_gen_or_i32(tmp, tmp, QREG_CC_C); |
6a432295 | 893 | tcond = TCG_COND_NE; |
e6e5906b PB |
894 | break; |
895 | case 4: /* CC (!C) */ | |
e6e5906b | 896 | case 5: /* CS (C) */ |
6a432295 RH |
897 | c->v1 = QREG_CC_C; |
898 | tcond = TCG_COND_NE; | |
e6e5906b PB |
899 | break; |
900 | case 6: /* NE (!Z) */ | |
e6e5906b | 901 | case 7: /* EQ (Z) */ |
6a432295 RH |
902 | c->v1 = QREG_CC_Z; |
903 | tcond = TCG_COND_EQ; | |
e6e5906b PB |
904 | break; |
905 | case 8: /* VC (!V) */ | |
e6e5906b | 906 | case 9: /* VS (V) */ |
6a432295 RH |
907 | c->v1 = QREG_CC_V; |
908 | tcond = TCG_COND_LT; | |
e6e5906b PB |
909 | break; |
910 | case 10: /* PL (!N) */ | |
e6e5906b | 911 | case 11: /* MI (N) */ |
6a432295 RH |
912 | c->v1 = QREG_CC_N; |
913 | tcond = TCG_COND_LT; | |
e6e5906b PB |
914 | break; |
915 | case 12: /* GE (!(N ^ V)) */ | |
e6e5906b | 916 | case 13: /* LT (N ^ V) */ |
6a432295 RH |
917 | c->v1 = tmp = tcg_temp_new(); |
918 | c->g1 = 0; | |
620c6cf6 | 919 | tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V); |
6a432295 | 920 | tcond = TCG_COND_LT; |
e6e5906b PB |
921 | break; |
922 | case 14: /* GT (!(Z || (N ^ V))) */ | |
e6e5906b | 923 | case 15: /* LE (Z || (N ^ V)) */ |
6a432295 RH |
924 | c->v1 = tmp = tcg_temp_new(); |
925 | c->g1 = 0; | |
926 | tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); | |
620c6cf6 RH |
927 | tcg_gen_neg_i32(tmp, tmp); |
928 | tmp2 = tcg_temp_new(); | |
929 | tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); | |
930 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
6a432295 RH |
931 | tcg_temp_free(tmp2); |
932 | tcond = TCG_COND_LT; | |
e6e5906b | 933 | break; |
e6e5906b | 934 | } |
9d896621 RH |
935 | |
936 | done: | |
6a432295 RH |
937 | if ((cond & 1) == 0) { |
938 | tcond = tcg_invert_cond(tcond); | |
939 | } | |
940 | c->tcond = tcond; | |
941 | } | |
942 | ||
943 | static void free_cond(DisasCompare *c) | |
944 | { | |
945 | if (!c->g1) { | |
946 | tcg_temp_free(c->v1); | |
947 | } | |
948 | if (!c->g2) { | |
949 | tcg_temp_free(c->v2); | |
950 | } | |
951 | } | |
952 | ||
953 | static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) | |
954 | { | |
955 | DisasCompare c; | |
956 | ||
957 | gen_cc_cond(&c, s, cond); | |
958 | update_cc_op(s); | |
959 | tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); | |
960 | free_cond(&c); | |
e6e5906b PB |
961 | } |
962 | ||
963 | DISAS_INSN(scc) | |
964 | { | |
b459e3ec | 965 | DisasCompare c; |
e6e5906b | 966 | int cond; |
b459e3ec | 967 | TCGv reg, tmp; |
e6e5906b | 968 | |
e6e5906b | 969 | cond = (insn >> 8) & 0xf; |
b459e3ec RH |
970 | gen_cc_cond(&c, s, cond); |
971 | ||
972 | tmp = tcg_temp_new(); | |
973 | tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); | |
974 | free_cond(&c); | |
975 | ||
e6e5906b | 976 | reg = DREG(insn, 0); |
b459e3ec RH |
977 | tcg_gen_neg_i32(tmp, tmp); |
978 | tcg_gen_deposit_i32(reg, reg, tmp, 0, 8); | |
979 | tcg_temp_free(tmp); | |
e6e5906b PB |
980 | } |
981 | ||
0633879f PB |
982 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
983 | static void gen_lookup_tb(DisasContext *s) | |
984 | { | |
9fdb533f | 985 | update_cc_op(s); |
e1f3808e | 986 | tcg_gen_movi_i32(QREG_PC, s->pc); |
0633879f PB |
987 | s->is_jmp = DISAS_UPDATE; |
988 | } | |
989 | ||
e1f3808e PB |
990 | /* Generate a jump to an immediate address. */ |
991 | static void gen_jmp_im(DisasContext *s, uint32_t dest) | |
992 | { | |
9fdb533f | 993 | update_cc_op(s); |
e1f3808e PB |
994 | tcg_gen_movi_i32(QREG_PC, dest); |
995 | s->is_jmp = DISAS_JUMP; | |
996 | } | |
997 | ||
998 | /* Generate a jump to the address in qreg DEST. */ | |
999 | static void gen_jmp(DisasContext *s, TCGv dest) | |
e6e5906b | 1000 | { |
9fdb533f | 1001 | update_cc_op(s); |
e1f3808e | 1002 | tcg_gen_mov_i32(QREG_PC, dest); |
e6e5906b PB |
1003 | s->is_jmp = DISAS_JUMP; |
1004 | } | |
1005 | ||
1006 | static void gen_exception(DisasContext *s, uint32_t where, int nr) | |
1007 | { | |
9fdb533f | 1008 | update_cc_op(s); |
e1f3808e | 1009 | gen_jmp_im(s, where); |
31871141 | 1010 | gen_helper_raise_exception(cpu_env, tcg_const_i32(nr)); |
e6e5906b PB |
1011 | } |
1012 | ||
510ff0b7 PB |
1013 | static inline void gen_addr_fault(DisasContext *s) |
1014 | { | |
1015 | gen_exception(s, s->insn_pc, EXCP_ADDRESS); | |
1016 | } | |
1017 | ||
d4d79bb1 BS |
1018 | #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ |
1019 | result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ | |
1020 | op_sign ? EA_LOADS : EA_LOADU); \ | |
1021 | if (IS_NULL_QREG(result)) { \ | |
1022 | gen_addr_fault(s); \ | |
1023 | return; \ | |
1024 | } \ | |
510ff0b7 PB |
1025 | } while (0) |
1026 | ||
d4d79bb1 BS |
1027 | #define DEST_EA(env, insn, opsize, val, addrp) do { \ |
1028 | TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ | |
1029 | if (IS_NULL_QREG(ea_result)) { \ | |
1030 | gen_addr_fault(s); \ | |
1031 | return; \ | |
1032 | } \ | |
510ff0b7 PB |
1033 | } while (0) |
1034 | ||
90aa39a1 SF |
1035 | static inline bool use_goto_tb(DisasContext *s, uint32_t dest) |
1036 | { | |
1037 | #ifndef CONFIG_USER_ONLY | |
1038 | return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || | |
1039 | (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
1040 | #else | |
1041 | return true; | |
1042 | #endif | |
1043 | } | |
1044 | ||
e6e5906b PB |
1045 | /* Generate a jump to an immediate address. */ |
1046 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | |
1047 | { | |
551bd27f | 1048 | if (unlikely(s->singlestep_enabled)) { |
e6e5906b | 1049 | gen_exception(s, dest, EXCP_DEBUG); |
90aa39a1 | 1050 | } else if (use_goto_tb(s, dest)) { |
57fec1fe | 1051 | tcg_gen_goto_tb(n); |
e1f3808e | 1052 | tcg_gen_movi_i32(QREG_PC, dest); |
90aa39a1 | 1053 | tcg_gen_exit_tb((uintptr_t)s->tb + n); |
e6e5906b | 1054 | } else { |
e1f3808e | 1055 | gen_jmp_im(s, dest); |
57fec1fe | 1056 | tcg_gen_exit_tb(0); |
e6e5906b PB |
1057 | } |
1058 | s->is_jmp = DISAS_TB_JUMP; | |
1059 | } | |
1060 | ||
1061 | DISAS_INSN(undef_mac) | |
1062 | { | |
1063 | gen_exception(s, s->pc - 2, EXCP_LINEA); | |
1064 | } | |
1065 | ||
1066 | DISAS_INSN(undef_fpu) | |
1067 | { | |
1068 | gen_exception(s, s->pc - 2, EXCP_LINEF); | |
1069 | } | |
1070 | ||
1071 | DISAS_INSN(undef) | |
1072 | { | |
a47dddd7 AF |
1073 | M68kCPU *cpu = m68k_env_get_cpu(env); |
1074 | ||
e6e5906b | 1075 | gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); |
a47dddd7 | 1076 | cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); |
e6e5906b PB |
1077 | } |
1078 | ||
1079 | DISAS_INSN(mulw) | |
1080 | { | |
e1f3808e PB |
1081 | TCGv reg; |
1082 | TCGv tmp; | |
1083 | TCGv src; | |
e6e5906b PB |
1084 | int sign; |
1085 | ||
1086 | sign = (insn & 0x100) != 0; | |
1087 | reg = DREG(insn, 9); | |
a7812ae4 | 1088 | tmp = tcg_temp_new(); |
e6e5906b | 1089 | if (sign) |
e1f3808e | 1090 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1091 | else |
e1f3808e | 1092 | tcg_gen_ext16u_i32(tmp, reg); |
d4d79bb1 | 1093 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e PB |
1094 | tcg_gen_mul_i32(tmp, tmp, src); |
1095 | tcg_gen_mov_i32(reg, tmp); | |
5dbb6784 | 1096 | gen_logic_cc(s, tmp, OS_WORD); |
e6e5906b PB |
1097 | } |
1098 | ||
1099 | DISAS_INSN(divw) | |
1100 | { | |
e1f3808e PB |
1101 | TCGv reg; |
1102 | TCGv tmp; | |
1103 | TCGv src; | |
e6e5906b PB |
1104 | int sign; |
1105 | ||
1106 | sign = (insn & 0x100) != 0; | |
1107 | reg = DREG(insn, 9); | |
1108 | if (sign) { | |
e1f3808e | 1109 | tcg_gen_ext16s_i32(QREG_DIV1, reg); |
e6e5906b | 1110 | } else { |
e1f3808e | 1111 | tcg_gen_ext16u_i32(QREG_DIV1, reg); |
e6e5906b | 1112 | } |
d4d79bb1 | 1113 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e | 1114 | tcg_gen_mov_i32(QREG_DIV2, src); |
e6e5906b | 1115 | if (sign) { |
e1f3808e | 1116 | gen_helper_divs(cpu_env, tcg_const_i32(1)); |
e6e5906b | 1117 | } else { |
e1f3808e | 1118 | gen_helper_divu(cpu_env, tcg_const_i32(1)); |
e6e5906b PB |
1119 | } |
1120 | ||
a7812ae4 PB |
1121 | tmp = tcg_temp_new(); |
1122 | src = tcg_temp_new(); | |
e1f3808e PB |
1123 | tcg_gen_ext16u_i32(tmp, QREG_DIV1); |
1124 | tcg_gen_shli_i32(src, QREG_DIV2, 16); | |
1125 | tcg_gen_or_i32(reg, tmp, src); | |
620c6cf6 | 1126 | |
9fdb533f | 1127 | set_cc_op(s, CC_OP_FLAGS); |
e6e5906b PB |
1128 | } |
1129 | ||
1130 | DISAS_INSN(divl) | |
1131 | { | |
e1f3808e PB |
1132 | TCGv num; |
1133 | TCGv den; | |
1134 | TCGv reg; | |
e6e5906b PB |
1135 | uint16_t ext; |
1136 | ||
28b68cd7 | 1137 | ext = read_im16(env, s); |
e6e5906b PB |
1138 | if (ext & 0x87f8) { |
1139 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
1140 | return; | |
1141 | } | |
1142 | num = DREG(ext, 12); | |
1143 | reg = DREG(ext, 0); | |
e1f3808e | 1144 | tcg_gen_mov_i32(QREG_DIV1, num); |
d4d79bb1 | 1145 | SRC_EA(env, den, OS_LONG, 0, NULL); |
e1f3808e | 1146 | tcg_gen_mov_i32(QREG_DIV2, den); |
e6e5906b | 1147 | if (ext & 0x0800) { |
e1f3808e | 1148 | gen_helper_divs(cpu_env, tcg_const_i32(0)); |
e6e5906b | 1149 | } else { |
e1f3808e | 1150 | gen_helper_divu(cpu_env, tcg_const_i32(0)); |
e6e5906b | 1151 | } |
e1f3808e | 1152 | if ((ext & 7) == ((ext >> 12) & 7)) { |
e6e5906b | 1153 | /* div */ |
e1f3808e | 1154 | tcg_gen_mov_i32 (reg, QREG_DIV1); |
e6e5906b PB |
1155 | } else { |
1156 | /* rem */ | |
e1f3808e | 1157 | tcg_gen_mov_i32 (reg, QREG_DIV2); |
e6e5906b | 1158 | } |
9fdb533f | 1159 | set_cc_op(s, CC_OP_FLAGS); |
e6e5906b PB |
1160 | } |
1161 | ||
1162 | DISAS_INSN(addsub) | |
1163 | { | |
e1f3808e PB |
1164 | TCGv reg; |
1165 | TCGv dest; | |
1166 | TCGv src; | |
1167 | TCGv tmp; | |
1168 | TCGv addr; | |
e6e5906b PB |
1169 | int add; |
1170 | ||
1171 | add = (insn & 0x4000) != 0; | |
1172 | reg = DREG(insn, 9); | |
a7812ae4 | 1173 | dest = tcg_temp_new(); |
e6e5906b | 1174 | if (insn & 0x100) { |
d4d79bb1 | 1175 | SRC_EA(env, tmp, OS_LONG, 0, &addr); |
e6e5906b PB |
1176 | src = reg; |
1177 | } else { | |
1178 | tmp = reg; | |
d4d79bb1 | 1179 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b PB |
1180 | } |
1181 | if (add) { | |
e1f3808e | 1182 | tcg_gen_add_i32(dest, tmp, src); |
f9083519 | 1183 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); |
9fdb533f | 1184 | set_cc_op(s, CC_OP_ADD); |
e6e5906b | 1185 | } else { |
f9083519 | 1186 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); |
e1f3808e | 1187 | tcg_gen_sub_i32(dest, tmp, src); |
9fdb533f | 1188 | set_cc_op(s, CC_OP_SUB); |
e6e5906b | 1189 | } |
e1f3808e | 1190 | gen_update_cc_add(dest, src); |
e6e5906b | 1191 | if (insn & 0x100) { |
d4d79bb1 | 1192 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1193 | } else { |
e1f3808e | 1194 | tcg_gen_mov_i32(reg, dest); |
e6e5906b PB |
1195 | } |
1196 | } | |
1197 | ||
1198 | ||
1199 | /* Reverse the order of the bits in REG. */ | |
1200 | DISAS_INSN(bitrev) | |
1201 | { | |
e1f3808e | 1202 | TCGv reg; |
e6e5906b | 1203 | reg = DREG(insn, 0); |
e1f3808e | 1204 | gen_helper_bitrev(reg, reg); |
e6e5906b PB |
1205 | } |
1206 | ||
1207 | DISAS_INSN(bitop_reg) | |
1208 | { | |
1209 | int opsize; | |
1210 | int op; | |
e1f3808e PB |
1211 | TCGv src1; |
1212 | TCGv src2; | |
1213 | TCGv tmp; | |
1214 | TCGv addr; | |
1215 | TCGv dest; | |
e6e5906b PB |
1216 | |
1217 | if ((insn & 0x38) != 0) | |
1218 | opsize = OS_BYTE; | |
1219 | else | |
1220 | opsize = OS_LONG; | |
1221 | op = (insn >> 6) & 3; | |
620c6cf6 RH |
1222 | |
1223 | gen_flush_flags(s); | |
1224 | ||
d4d79bb1 | 1225 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1226 | src2 = DREG(insn, 9); |
a7812ae4 | 1227 | dest = tcg_temp_new(); |
e6e5906b | 1228 | |
a7812ae4 | 1229 | tmp = tcg_temp_new(); |
e6e5906b | 1230 | if (opsize == OS_BYTE) |
e1f3808e | 1231 | tcg_gen_andi_i32(tmp, src2, 7); |
e6e5906b | 1232 | else |
e1f3808e | 1233 | tcg_gen_andi_i32(tmp, src2, 31); |
620c6cf6 RH |
1234 | |
1235 | src2 = tcg_const_i32(1); | |
1236 | tcg_gen_shl_i32(src2, src2, tmp); | |
1237 | tcg_temp_free(tmp); | |
1238 | ||
1239 | tcg_gen_and_i32(QREG_CC_Z, src1, src2); | |
1240 | ||
e6e5906b PB |
1241 | switch (op) { |
1242 | case 1: /* bchg */ | |
620c6cf6 | 1243 | tcg_gen_xor_i32(dest, src1, src2); |
e6e5906b PB |
1244 | break; |
1245 | case 2: /* bclr */ | |
620c6cf6 | 1246 | tcg_gen_andc_i32(dest, src1, src2); |
e6e5906b PB |
1247 | break; |
1248 | case 3: /* bset */ | |
620c6cf6 | 1249 | tcg_gen_or_i32(dest, src1, src2); |
e6e5906b PB |
1250 | break; |
1251 | default: /* btst */ | |
1252 | break; | |
1253 | } | |
620c6cf6 RH |
1254 | tcg_temp_free(src2); |
1255 | if (op) { | |
d4d79bb1 | 1256 | DEST_EA(env, insn, opsize, dest, &addr); |
620c6cf6 RH |
1257 | } |
1258 | tcg_temp_free(dest); | |
e6e5906b PB |
1259 | } |
1260 | ||
1261 | DISAS_INSN(sats) | |
1262 | { | |
e1f3808e | 1263 | TCGv reg; |
e6e5906b | 1264 | reg = DREG(insn, 0); |
e6e5906b | 1265 | gen_flush_flags(s); |
620c6cf6 | 1266 | gen_helper_sats(reg, reg, QREG_CC_V); |
5dbb6784 | 1267 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1268 | } |
1269 | ||
e1f3808e | 1270 | static void gen_push(DisasContext *s, TCGv val) |
e6e5906b | 1271 | { |
e1f3808e | 1272 | TCGv tmp; |
e6e5906b | 1273 | |
a7812ae4 | 1274 | tmp = tcg_temp_new(); |
e1f3808e | 1275 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1276 | gen_store(s, OS_LONG, tmp, val); |
e1f3808e | 1277 | tcg_gen_mov_i32(QREG_SP, tmp); |
e6e5906b PB |
1278 | } |
1279 | ||
1280 | DISAS_INSN(movem) | |
1281 | { | |
e1f3808e | 1282 | TCGv addr; |
e6e5906b PB |
1283 | int i; |
1284 | uint16_t mask; | |
e1f3808e PB |
1285 | TCGv reg; |
1286 | TCGv tmp; | |
e6e5906b PB |
1287 | int is_load; |
1288 | ||
28b68cd7 | 1289 | mask = read_im16(env, s); |
d4d79bb1 | 1290 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1291 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1292 | gen_addr_fault(s); |
1293 | return; | |
1294 | } | |
a7812ae4 | 1295 | addr = tcg_temp_new(); |
e1f3808e | 1296 | tcg_gen_mov_i32(addr, tmp); |
e6e5906b PB |
1297 | is_load = ((insn & 0x0400) != 0); |
1298 | for (i = 0; i < 16; i++, mask >>= 1) { | |
1299 | if (mask & 1) { | |
1300 | if (i < 8) | |
1301 | reg = DREG(i, 0); | |
1302 | else | |
1303 | reg = AREG(i, 0); | |
1304 | if (is_load) { | |
0633879f | 1305 | tmp = gen_load(s, OS_LONG, addr, 0); |
e1f3808e | 1306 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b | 1307 | } else { |
0633879f | 1308 | gen_store(s, OS_LONG, addr, reg); |
e6e5906b PB |
1309 | } |
1310 | if (mask != 1) | |
e1f3808e | 1311 | tcg_gen_addi_i32(addr, addr, 4); |
e6e5906b PB |
1312 | } |
1313 | } | |
1314 | } | |
1315 | ||
1316 | DISAS_INSN(bitop_im) | |
1317 | { | |
1318 | int opsize; | |
1319 | int op; | |
e1f3808e | 1320 | TCGv src1; |
e6e5906b PB |
1321 | uint32_t mask; |
1322 | int bitnum; | |
e1f3808e PB |
1323 | TCGv tmp; |
1324 | TCGv addr; | |
e6e5906b PB |
1325 | |
1326 | if ((insn & 0x38) != 0) | |
1327 | opsize = OS_BYTE; | |
1328 | else | |
1329 | opsize = OS_LONG; | |
1330 | op = (insn >> 6) & 3; | |
1331 | ||
28b68cd7 | 1332 | bitnum = read_im16(env, s); |
e6e5906b | 1333 | if (bitnum & 0xff00) { |
d4d79bb1 | 1334 | disas_undef(env, s, insn); |
e6e5906b PB |
1335 | return; |
1336 | } | |
1337 | ||
620c6cf6 RH |
1338 | gen_flush_flags(s); |
1339 | ||
d4d79bb1 | 1340 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1341 | |
e6e5906b PB |
1342 | if (opsize == OS_BYTE) |
1343 | bitnum &= 7; | |
1344 | else | |
1345 | bitnum &= 31; | |
1346 | mask = 1 << bitnum; | |
1347 | ||
620c6cf6 RH |
1348 | tcg_gen_andi_i32(QREG_CC_Z, src1, mask); |
1349 | ||
e1f3808e | 1350 | if (op) { |
620c6cf6 | 1351 | tmp = tcg_temp_new(); |
e1f3808e PB |
1352 | switch (op) { |
1353 | case 1: /* bchg */ | |
1354 | tcg_gen_xori_i32(tmp, src1, mask); | |
1355 | break; | |
1356 | case 2: /* bclr */ | |
1357 | tcg_gen_andi_i32(tmp, src1, ~mask); | |
1358 | break; | |
1359 | case 3: /* bset */ | |
1360 | tcg_gen_ori_i32(tmp, src1, mask); | |
1361 | break; | |
1362 | default: /* btst */ | |
1363 | break; | |
1364 | } | |
d4d79bb1 | 1365 | DEST_EA(env, insn, opsize, tmp, &addr); |
620c6cf6 | 1366 | tcg_temp_free(tmp); |
e6e5906b | 1367 | } |
e6e5906b | 1368 | } |
620c6cf6 | 1369 | |
e6e5906b PB |
1370 | DISAS_INSN(arith_im) |
1371 | { | |
1372 | int op; | |
e1f3808e PB |
1373 | uint32_t im; |
1374 | TCGv src1; | |
1375 | TCGv dest; | |
1376 | TCGv addr; | |
e6e5906b PB |
1377 | |
1378 | op = (insn >> 9) & 7; | |
d4d79bb1 BS |
1379 | SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr); |
1380 | im = read_im32(env, s); | |
a7812ae4 | 1381 | dest = tcg_temp_new(); |
e6e5906b PB |
1382 | switch (op) { |
1383 | case 0: /* ori */ | |
e1f3808e | 1384 | tcg_gen_ori_i32(dest, src1, im); |
5dbb6784 | 1385 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1386 | break; |
1387 | case 1: /* andi */ | |
e1f3808e | 1388 | tcg_gen_andi_i32(dest, src1, im); |
5dbb6784 | 1389 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1390 | break; |
1391 | case 2: /* subi */ | |
e1f3808e | 1392 | tcg_gen_mov_i32(dest, src1); |
620c6cf6 | 1393 | tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im); |
e1f3808e | 1394 | tcg_gen_subi_i32(dest, dest, im); |
351326a6 | 1395 | gen_update_cc_add(dest, tcg_const_i32(im)); |
9fdb533f | 1396 | set_cc_op(s, CC_OP_SUB); |
e6e5906b PB |
1397 | break; |
1398 | case 3: /* addi */ | |
e1f3808e PB |
1399 | tcg_gen_mov_i32(dest, src1); |
1400 | tcg_gen_addi_i32(dest, dest, im); | |
351326a6 | 1401 | gen_update_cc_add(dest, tcg_const_i32(im)); |
620c6cf6 | 1402 | tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im); |
9fdb533f | 1403 | set_cc_op(s, CC_OP_ADD); |
e6e5906b PB |
1404 | break; |
1405 | case 5: /* eori */ | |
e1f3808e | 1406 | tcg_gen_xori_i32(dest, src1, im); |
5dbb6784 | 1407 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1408 | break; |
1409 | case 6: /* cmpi */ | |
620c6cf6 RH |
1410 | gen_update_cc_add(src1, tcg_const_i32(im)); |
1411 | set_cc_op(s, CC_OP_CMP); | |
e6e5906b PB |
1412 | break; |
1413 | default: | |
1414 | abort(); | |
1415 | } | |
1416 | if (op != 6) { | |
d4d79bb1 | 1417 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1418 | } |
1419 | } | |
1420 | ||
1421 | DISAS_INSN(byterev) | |
1422 | { | |
e1f3808e | 1423 | TCGv reg; |
e6e5906b PB |
1424 | |
1425 | reg = DREG(insn, 0); | |
66896cb8 | 1426 | tcg_gen_bswap32_i32(reg, reg); |
e6e5906b PB |
1427 | } |
1428 | ||
1429 | DISAS_INSN(move) | |
1430 | { | |
e1f3808e PB |
1431 | TCGv src; |
1432 | TCGv dest; | |
e6e5906b PB |
1433 | int op; |
1434 | int opsize; | |
1435 | ||
1436 | switch (insn >> 12) { | |
1437 | case 1: /* move.b */ | |
1438 | opsize = OS_BYTE; | |
1439 | break; | |
1440 | case 2: /* move.l */ | |
1441 | opsize = OS_LONG; | |
1442 | break; | |
1443 | case 3: /* move.w */ | |
1444 | opsize = OS_WORD; | |
1445 | break; | |
1446 | default: | |
1447 | abort(); | |
1448 | } | |
d4d79bb1 | 1449 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b PB |
1450 | op = (insn >> 6) & 7; |
1451 | if (op == 1) { | |
1452 | /* movea */ | |
1453 | /* The value will already have been sign extended. */ | |
1454 | dest = AREG(insn, 9); | |
e1f3808e | 1455 | tcg_gen_mov_i32(dest, src); |
e6e5906b PB |
1456 | } else { |
1457 | /* normal move */ | |
1458 | uint16_t dest_ea; | |
1459 | dest_ea = ((insn >> 9) & 7) | (op << 3); | |
d4d79bb1 | 1460 | DEST_EA(env, dest_ea, opsize, src, NULL); |
e6e5906b | 1461 | /* This will be correct because loads sign extend. */ |
5dbb6784 | 1462 | gen_logic_cc(s, src, opsize); |
e6e5906b PB |
1463 | } |
1464 | } | |
1465 | ||
1466 | DISAS_INSN(negx) | |
1467 | { | |
e1f3808e | 1468 | TCGv reg; |
e6e5906b PB |
1469 | |
1470 | gen_flush_flags(s); | |
1471 | reg = DREG(insn, 0); | |
e1f3808e | 1472 | gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg); |
e6e5906b PB |
1473 | } |
1474 | ||
1475 | DISAS_INSN(lea) | |
1476 | { | |
e1f3808e PB |
1477 | TCGv reg; |
1478 | TCGv tmp; | |
e6e5906b PB |
1479 | |
1480 | reg = AREG(insn, 9); | |
d4d79bb1 | 1481 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1482 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1483 | gen_addr_fault(s); |
1484 | return; | |
1485 | } | |
e1f3808e | 1486 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1487 | } |
1488 | ||
1489 | DISAS_INSN(clr) | |
1490 | { | |
1491 | int opsize; | |
1492 | ||
7ef25cdd | 1493 | opsize = insn_opsize(insn); |
d4d79bb1 | 1494 | DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL); |
5dbb6784 | 1495 | gen_logic_cc(s, tcg_const_i32(0), opsize); |
e6e5906b PB |
1496 | } |
1497 | ||
e1f3808e | 1498 | static TCGv gen_get_ccr(DisasContext *s) |
e6e5906b | 1499 | { |
e1f3808e | 1500 | TCGv dest; |
e6e5906b PB |
1501 | |
1502 | gen_flush_flags(s); | |
620c6cf6 | 1503 | update_cc_op(s); |
a7812ae4 | 1504 | dest = tcg_temp_new(); |
620c6cf6 | 1505 | gen_helper_get_ccr(dest, cpu_env); |
0633879f PB |
1506 | return dest; |
1507 | } | |
1508 | ||
1509 | DISAS_INSN(move_from_ccr) | |
1510 | { | |
e1f3808e | 1511 | TCGv ccr; |
0633879f PB |
1512 | |
1513 | ccr = gen_get_ccr(s); | |
7c0eb318 | 1514 | DEST_EA(env, insn, OS_WORD, ccr, NULL); |
e6e5906b PB |
1515 | } |
1516 | ||
1517 | DISAS_INSN(neg) | |
1518 | { | |
e1f3808e PB |
1519 | TCGv reg; |
1520 | TCGv src1; | |
e6e5906b PB |
1521 | |
1522 | reg = DREG(insn, 0); | |
a7812ae4 | 1523 | src1 = tcg_temp_new(); |
e1f3808e PB |
1524 | tcg_gen_mov_i32(src1, reg); |
1525 | tcg_gen_neg_i32(reg, src1); | |
e1f3808e | 1526 | gen_update_cc_add(reg, src1); |
620c6cf6 | 1527 | tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, src1, 0); |
9fdb533f | 1528 | set_cc_op(s, CC_OP_SUB); |
e6e5906b PB |
1529 | } |
1530 | ||
0633879f PB |
1531 | static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) |
1532 | { | |
620c6cf6 RH |
1533 | if (ccr_only) { |
1534 | tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0); | |
1535 | tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0); | |
1536 | tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1); | |
1537 | tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0); | |
1538 | tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0); | |
1539 | } else { | |
1540 | gen_helper_set_sr(cpu_env, tcg_const_i32(val)); | |
0633879f | 1541 | } |
9fdb533f | 1542 | set_cc_op(s, CC_OP_FLAGS); |
0633879f PB |
1543 | } |
1544 | ||
620c6cf6 RH |
1545 | static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, |
1546 | int ccr_only) | |
e6e5906b | 1547 | { |
620c6cf6 RH |
1548 | if ((insn & 0x38) == 0) { |
1549 | if (ccr_only) { | |
1550 | gen_helper_set_ccr(cpu_env, DREG(insn, 0)); | |
1551 | } else { | |
1552 | gen_helper_set_sr(cpu_env, DREG(insn, 0)); | |
1553 | } | |
1554 | set_cc_op(s, CC_OP_FLAGS); | |
1555 | } else if ((insn & 0x3f) == 0x3c) { | |
1556 | uint16_t val; | |
1557 | val = read_im16(env, s); | |
1558 | gen_set_sr_im(s, val, ccr_only); | |
1559 | } else { | |
1560 | disas_undef(env, s, insn); | |
7c0eb318 LV |
1561 | } |
1562 | } | |
e6e5906b | 1563 | |
7c0eb318 | 1564 | |
0633879f PB |
1565 | DISAS_INSN(move_to_ccr) |
1566 | { | |
620c6cf6 | 1567 | gen_set_sr(env, s, insn, 1); |
0633879f PB |
1568 | } |
1569 | ||
e6e5906b PB |
1570 | DISAS_INSN(not) |
1571 | { | |
e1f3808e | 1572 | TCGv reg; |
e6e5906b PB |
1573 | |
1574 | reg = DREG(insn, 0); | |
e1f3808e | 1575 | tcg_gen_not_i32(reg, reg); |
5dbb6784 | 1576 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1577 | } |
1578 | ||
1579 | DISAS_INSN(swap) | |
1580 | { | |
e1f3808e PB |
1581 | TCGv src1; |
1582 | TCGv src2; | |
1583 | TCGv reg; | |
e6e5906b | 1584 | |
a7812ae4 PB |
1585 | src1 = tcg_temp_new(); |
1586 | src2 = tcg_temp_new(); | |
e6e5906b | 1587 | reg = DREG(insn, 0); |
e1f3808e PB |
1588 | tcg_gen_shli_i32(src1, reg, 16); |
1589 | tcg_gen_shri_i32(src2, reg, 16); | |
1590 | tcg_gen_or_i32(reg, src1, src2); | |
5dbb6784 | 1591 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1592 | } |
1593 | ||
1594 | DISAS_INSN(pea) | |
1595 | { | |
e1f3808e | 1596 | TCGv tmp; |
e6e5906b | 1597 | |
d4d79bb1 | 1598 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1599 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1600 | gen_addr_fault(s); |
1601 | return; | |
1602 | } | |
0633879f | 1603 | gen_push(s, tmp); |
e6e5906b PB |
1604 | } |
1605 | ||
1606 | DISAS_INSN(ext) | |
1607 | { | |
e6e5906b | 1608 | int op; |
e1f3808e PB |
1609 | TCGv reg; |
1610 | TCGv tmp; | |
e6e5906b PB |
1611 | |
1612 | reg = DREG(insn, 0); | |
1613 | op = (insn >> 6) & 7; | |
a7812ae4 | 1614 | tmp = tcg_temp_new(); |
e6e5906b | 1615 | if (op == 3) |
e1f3808e | 1616 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1617 | else |
e1f3808e | 1618 | tcg_gen_ext8s_i32(tmp, reg); |
e6e5906b PB |
1619 | if (op == 2) |
1620 | gen_partset_reg(OS_WORD, reg, tmp); | |
1621 | else | |
e1f3808e | 1622 | tcg_gen_mov_i32(reg, tmp); |
5dbb6784 | 1623 | gen_logic_cc(s, tmp, OS_LONG); |
e6e5906b PB |
1624 | } |
1625 | ||
1626 | DISAS_INSN(tst) | |
1627 | { | |
1628 | int opsize; | |
e1f3808e | 1629 | TCGv tmp; |
e6e5906b | 1630 | |
7ef25cdd | 1631 | opsize = insn_opsize(insn); |
d4d79bb1 | 1632 | SRC_EA(env, tmp, opsize, 1, NULL); |
5dbb6784 | 1633 | gen_logic_cc(s, tmp, opsize); |
e6e5906b PB |
1634 | } |
1635 | ||
1636 | DISAS_INSN(pulse) | |
1637 | { | |
1638 | /* Implemented as a NOP. */ | |
1639 | } | |
1640 | ||
1641 | DISAS_INSN(illegal) | |
1642 | { | |
1643 | gen_exception(s, s->pc - 2, EXCP_ILLEGAL); | |
1644 | } | |
1645 | ||
1646 | /* ??? This should be atomic. */ | |
1647 | DISAS_INSN(tas) | |
1648 | { | |
e1f3808e PB |
1649 | TCGv dest; |
1650 | TCGv src1; | |
1651 | TCGv addr; | |
e6e5906b | 1652 | |
a7812ae4 | 1653 | dest = tcg_temp_new(); |
d4d79bb1 | 1654 | SRC_EA(env, src1, OS_BYTE, 1, &addr); |
5dbb6784 | 1655 | gen_logic_cc(s, src1, OS_BYTE); |
e1f3808e | 1656 | tcg_gen_ori_i32(dest, src1, 0x80); |
d4d79bb1 | 1657 | DEST_EA(env, insn, OS_BYTE, dest, &addr); |
e6e5906b PB |
1658 | } |
1659 | ||
1660 | DISAS_INSN(mull) | |
1661 | { | |
1662 | uint16_t ext; | |
e1f3808e PB |
1663 | TCGv reg; |
1664 | TCGv src1; | |
1665 | TCGv dest; | |
e6e5906b PB |
1666 | |
1667 | /* The upper 32 bits of the product are discarded, so | |
1668 | muls.l and mulu.l are functionally equivalent. */ | |
28b68cd7 | 1669 | ext = read_im16(env, s); |
e6e5906b PB |
1670 | if (ext & 0x87ff) { |
1671 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
1672 | return; | |
1673 | } | |
1674 | reg = DREG(ext, 12); | |
d4d79bb1 | 1675 | SRC_EA(env, src1, OS_LONG, 0, NULL); |
a7812ae4 | 1676 | dest = tcg_temp_new(); |
e1f3808e PB |
1677 | tcg_gen_mul_i32(dest, src1, reg); |
1678 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b | 1679 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
5dbb6784 | 1680 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1681 | } |
1682 | ||
1683 | DISAS_INSN(link) | |
1684 | { | |
1685 | int16_t offset; | |
e1f3808e PB |
1686 | TCGv reg; |
1687 | TCGv tmp; | |
e6e5906b | 1688 | |
d4d79bb1 | 1689 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1690 | s->pc += 2; |
1691 | reg = AREG(insn, 0); | |
a7812ae4 | 1692 | tmp = tcg_temp_new(); |
e1f3808e | 1693 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1694 | gen_store(s, OS_LONG, tmp, reg); |
e1f3808e PB |
1695 | if ((insn & 7) != 7) |
1696 | tcg_gen_mov_i32(reg, tmp); | |
1697 | tcg_gen_addi_i32(QREG_SP, tmp, offset); | |
e6e5906b PB |
1698 | } |
1699 | ||
1700 | DISAS_INSN(unlk) | |
1701 | { | |
e1f3808e PB |
1702 | TCGv src; |
1703 | TCGv reg; | |
1704 | TCGv tmp; | |
e6e5906b | 1705 | |
a7812ae4 | 1706 | src = tcg_temp_new(); |
e6e5906b | 1707 | reg = AREG(insn, 0); |
e1f3808e | 1708 | tcg_gen_mov_i32(src, reg); |
0633879f | 1709 | tmp = gen_load(s, OS_LONG, src, 0); |
e1f3808e PB |
1710 | tcg_gen_mov_i32(reg, tmp); |
1711 | tcg_gen_addi_i32(QREG_SP, src, 4); | |
e6e5906b PB |
1712 | } |
1713 | ||
1714 | DISAS_INSN(nop) | |
1715 | { | |
1716 | } | |
1717 | ||
1718 | DISAS_INSN(rts) | |
1719 | { | |
e1f3808e | 1720 | TCGv tmp; |
e6e5906b | 1721 | |
0633879f | 1722 | tmp = gen_load(s, OS_LONG, QREG_SP, 0); |
e1f3808e | 1723 | tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); |
e6e5906b PB |
1724 | gen_jmp(s, tmp); |
1725 | } | |
1726 | ||
1727 | DISAS_INSN(jump) | |
1728 | { | |
e1f3808e | 1729 | TCGv tmp; |
e6e5906b PB |
1730 | |
1731 | /* Load the target address first to ensure correct exception | |
1732 | behavior. */ | |
d4d79bb1 | 1733 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1734 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1735 | gen_addr_fault(s); |
1736 | return; | |
1737 | } | |
e6e5906b PB |
1738 | if ((insn & 0x40) == 0) { |
1739 | /* jsr */ | |
351326a6 | 1740 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1741 | } |
1742 | gen_jmp(s, tmp); | |
1743 | } | |
1744 | ||
1745 | DISAS_INSN(addsubq) | |
1746 | { | |
e1f3808e PB |
1747 | TCGv src1; |
1748 | TCGv src2; | |
1749 | TCGv dest; | |
e6e5906b | 1750 | int val; |
e1f3808e | 1751 | TCGv addr; |
e6e5906b | 1752 | |
d4d79bb1 | 1753 | SRC_EA(env, src1, OS_LONG, 0, &addr); |
e6e5906b PB |
1754 | val = (insn >> 9) & 7; |
1755 | if (val == 0) | |
1756 | val = 8; | |
a7812ae4 | 1757 | dest = tcg_temp_new(); |
e1f3808e | 1758 | tcg_gen_mov_i32(dest, src1); |
e6e5906b PB |
1759 | if ((insn & 0x38) == 0x08) { |
1760 | /* Don't update condition codes if the destination is an | |
1761 | address register. */ | |
1762 | if (insn & 0x0100) { | |
e1f3808e | 1763 | tcg_gen_subi_i32(dest, dest, val); |
e6e5906b | 1764 | } else { |
e1f3808e | 1765 | tcg_gen_addi_i32(dest, dest, val); |
e6e5906b PB |
1766 | } |
1767 | } else { | |
351326a6 | 1768 | src2 = tcg_const_i32(val); |
e6e5906b | 1769 | if (insn & 0x0100) { |
f9083519 | 1770 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); |
620c6cf6 | 1771 | tcg_gen_sub_i32(dest, dest, src2); |
9fdb533f | 1772 | set_cc_op(s, CC_OP_SUB); |
e6e5906b | 1773 | } else { |
620c6cf6 | 1774 | tcg_gen_add_i32(dest, dest, src2); |
f9083519 | 1775 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); |
9fdb533f | 1776 | set_cc_op(s, CC_OP_ADD); |
e6e5906b | 1777 | } |
e1f3808e | 1778 | gen_update_cc_add(dest, src2); |
e6e5906b | 1779 | } |
d4d79bb1 | 1780 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1781 | } |
1782 | ||
1783 | DISAS_INSN(tpf) | |
1784 | { | |
1785 | switch (insn & 7) { | |
1786 | case 2: /* One extension word. */ | |
1787 | s->pc += 2; | |
1788 | break; | |
1789 | case 3: /* Two extension words. */ | |
1790 | s->pc += 4; | |
1791 | break; | |
1792 | case 4: /* No extension words. */ | |
1793 | break; | |
1794 | default: | |
d4d79bb1 | 1795 | disas_undef(env, s, insn); |
e6e5906b PB |
1796 | } |
1797 | } | |
1798 | ||
1799 | DISAS_INSN(branch) | |
1800 | { | |
1801 | int32_t offset; | |
1802 | uint32_t base; | |
1803 | int op; | |
42a268c2 | 1804 | TCGLabel *l1; |
3b46e624 | 1805 | |
e6e5906b PB |
1806 | base = s->pc; |
1807 | op = (insn >> 8) & 0xf; | |
1808 | offset = (int8_t)insn; | |
1809 | if (offset == 0) { | |
28b68cd7 | 1810 | offset = (int16_t)read_im16(env, s); |
e6e5906b | 1811 | } else if (offset == -1) { |
d4d79bb1 | 1812 | offset = read_im32(env, s); |
e6e5906b PB |
1813 | } |
1814 | if (op == 1) { | |
1815 | /* bsr */ | |
351326a6 | 1816 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b | 1817 | } |
e6e5906b PB |
1818 | if (op > 1) { |
1819 | /* Bcc */ | |
1820 | l1 = gen_new_label(); | |
1821 | gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); | |
1822 | gen_jmp_tb(s, 1, base + offset); | |
1823 | gen_set_label(l1); | |
1824 | gen_jmp_tb(s, 0, s->pc); | |
1825 | } else { | |
1826 | /* Unconditional branch. */ | |
1827 | gen_jmp_tb(s, 0, base + offset); | |
1828 | } | |
1829 | } | |
1830 | ||
1831 | DISAS_INSN(moveq) | |
1832 | { | |
e1f3808e | 1833 | uint32_t val; |
e6e5906b | 1834 | |
e1f3808e PB |
1835 | val = (int8_t)insn; |
1836 | tcg_gen_movi_i32(DREG(insn, 9), val); | |
5dbb6784 | 1837 | gen_logic_cc(s, tcg_const_i32(val), OS_LONG); |
e6e5906b PB |
1838 | } |
1839 | ||
1840 | DISAS_INSN(mvzs) | |
1841 | { | |
1842 | int opsize; | |
e1f3808e PB |
1843 | TCGv src; |
1844 | TCGv reg; | |
e6e5906b PB |
1845 | |
1846 | if (insn & 0x40) | |
1847 | opsize = OS_WORD; | |
1848 | else | |
1849 | opsize = OS_BYTE; | |
d4d79bb1 | 1850 | SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); |
e6e5906b | 1851 | reg = DREG(insn, 9); |
e1f3808e | 1852 | tcg_gen_mov_i32(reg, src); |
5dbb6784 | 1853 | gen_logic_cc(s, src, opsize); |
e6e5906b PB |
1854 | } |
1855 | ||
1856 | DISAS_INSN(or) | |
1857 | { | |
e1f3808e PB |
1858 | TCGv reg; |
1859 | TCGv dest; | |
1860 | TCGv src; | |
1861 | TCGv addr; | |
e6e5906b PB |
1862 | |
1863 | reg = DREG(insn, 9); | |
a7812ae4 | 1864 | dest = tcg_temp_new(); |
e6e5906b | 1865 | if (insn & 0x100) { |
d4d79bb1 | 1866 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1867 | tcg_gen_or_i32(dest, src, reg); |
d4d79bb1 | 1868 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1869 | } else { |
d4d79bb1 | 1870 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1871 | tcg_gen_or_i32(dest, src, reg); |
1872 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b | 1873 | } |
5dbb6784 | 1874 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1875 | } |
1876 | ||
1877 | DISAS_INSN(suba) | |
1878 | { | |
e1f3808e PB |
1879 | TCGv src; |
1880 | TCGv reg; | |
e6e5906b | 1881 | |
d4d79bb1 | 1882 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1883 | reg = AREG(insn, 9); |
e1f3808e | 1884 | tcg_gen_sub_i32(reg, reg, src); |
e6e5906b PB |
1885 | } |
1886 | ||
1887 | DISAS_INSN(subx) | |
1888 | { | |
e1f3808e PB |
1889 | TCGv reg; |
1890 | TCGv src; | |
e6e5906b PB |
1891 | |
1892 | gen_flush_flags(s); | |
1893 | reg = DREG(insn, 9); | |
1894 | src = DREG(insn, 0); | |
e1f3808e | 1895 | gen_helper_subx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1896 | } |
1897 | ||
1898 | DISAS_INSN(mov3q) | |
1899 | { | |
e1f3808e | 1900 | TCGv src; |
e6e5906b PB |
1901 | int val; |
1902 | ||
1903 | val = (insn >> 9) & 7; | |
1904 | if (val == 0) | |
1905 | val = -1; | |
351326a6 | 1906 | src = tcg_const_i32(val); |
5dbb6784 | 1907 | gen_logic_cc(s, src, OS_LONG); |
d4d79bb1 | 1908 | DEST_EA(env, insn, OS_LONG, src, NULL); |
e6e5906b PB |
1909 | } |
1910 | ||
1911 | DISAS_INSN(cmp) | |
1912 | { | |
e1f3808e PB |
1913 | TCGv src; |
1914 | TCGv reg; | |
e6e5906b PB |
1915 | int opsize; |
1916 | ||
5dbb6784 LV |
1917 | opsize = insn_opsize(insn); |
1918 | SRC_EA(env, src, opsize, -1, NULL); | |
e6e5906b | 1919 | reg = DREG(insn, 9); |
620c6cf6 RH |
1920 | gen_update_cc_add(reg, src); |
1921 | set_cc_op(s, CC_OP_CMP); | |
e6e5906b PB |
1922 | } |
1923 | ||
1924 | DISAS_INSN(cmpa) | |
1925 | { | |
1926 | int opsize; | |
e1f3808e PB |
1927 | TCGv src; |
1928 | TCGv reg; | |
e6e5906b PB |
1929 | |
1930 | if (insn & 0x100) { | |
1931 | opsize = OS_LONG; | |
1932 | } else { | |
1933 | opsize = OS_WORD; | |
1934 | } | |
d4d79bb1 | 1935 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1936 | reg = AREG(insn, 9); |
620c6cf6 RH |
1937 | gen_update_cc_add(reg, src); |
1938 | set_cc_op(s, CC_OP_CMP); | |
e6e5906b PB |
1939 | } |
1940 | ||
1941 | DISAS_INSN(eor) | |
1942 | { | |
e1f3808e PB |
1943 | TCGv src; |
1944 | TCGv reg; | |
1945 | TCGv dest; | |
1946 | TCGv addr; | |
e6e5906b | 1947 | |
d4d79bb1 | 1948 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e6e5906b | 1949 | reg = DREG(insn, 9); |
a7812ae4 | 1950 | dest = tcg_temp_new(); |
e1f3808e | 1951 | tcg_gen_xor_i32(dest, src, reg); |
5dbb6784 | 1952 | gen_logic_cc(s, dest, OS_LONG); |
d4d79bb1 | 1953 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1954 | } |
1955 | ||
1956 | DISAS_INSN(and) | |
1957 | { | |
e1f3808e PB |
1958 | TCGv src; |
1959 | TCGv reg; | |
1960 | TCGv dest; | |
1961 | TCGv addr; | |
e6e5906b PB |
1962 | |
1963 | reg = DREG(insn, 9); | |
a7812ae4 | 1964 | dest = tcg_temp_new(); |
e6e5906b | 1965 | if (insn & 0x100) { |
d4d79bb1 | 1966 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1967 | tcg_gen_and_i32(dest, src, reg); |
d4d79bb1 | 1968 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1969 | } else { |
d4d79bb1 | 1970 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1971 | tcg_gen_and_i32(dest, src, reg); |
1972 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b | 1973 | } |
5dbb6784 | 1974 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1975 | } |
1976 | ||
1977 | DISAS_INSN(adda) | |
1978 | { | |
e1f3808e PB |
1979 | TCGv src; |
1980 | TCGv reg; | |
e6e5906b | 1981 | |
d4d79bb1 | 1982 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1983 | reg = AREG(insn, 9); |
e1f3808e | 1984 | tcg_gen_add_i32(reg, reg, src); |
e6e5906b PB |
1985 | } |
1986 | ||
1987 | DISAS_INSN(addx) | |
1988 | { | |
e1f3808e PB |
1989 | TCGv reg; |
1990 | TCGv src; | |
e6e5906b PB |
1991 | |
1992 | gen_flush_flags(s); | |
1993 | reg = DREG(insn, 9); | |
1994 | src = DREG(insn, 0); | |
e1f3808e | 1995 | gen_helper_addx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1996 | } |
1997 | ||
e1f3808e | 1998 | /* TODO: This could be implemented without helper functions. */ |
e6e5906b PB |
1999 | DISAS_INSN(shift_im) |
2000 | { | |
e1f3808e | 2001 | TCGv reg; |
e6e5906b | 2002 | int tmp; |
e1f3808e | 2003 | TCGv shift; |
e6e5906b | 2004 | |
620c6cf6 RH |
2005 | set_cc_op(s, CC_OP_FLAGS); |
2006 | ||
e6e5906b PB |
2007 | reg = DREG(insn, 0); |
2008 | tmp = (insn >> 9) & 7; | |
2009 | if (tmp == 0) | |
e1f3808e | 2010 | tmp = 8; |
351326a6 | 2011 | shift = tcg_const_i32(tmp); |
e1f3808e | 2012 | /* No need to flush flags becuse we know we will set C flag. */ |
e6e5906b | 2013 | if (insn & 0x100) { |
e1f3808e | 2014 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
2015 | } else { |
2016 | if (insn & 8) { | |
e1f3808e | 2017 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 2018 | } else { |
e1f3808e | 2019 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
2020 | } |
2021 | } | |
2022 | } | |
2023 | ||
2024 | DISAS_INSN(shift_reg) | |
2025 | { | |
e1f3808e PB |
2026 | TCGv reg; |
2027 | TCGv shift; | |
e6e5906b PB |
2028 | |
2029 | reg = DREG(insn, 0); | |
e1f3808e | 2030 | shift = DREG(insn, 9); |
e6e5906b | 2031 | if (insn & 0x100) { |
e1f3808e | 2032 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
2033 | } else { |
2034 | if (insn & 8) { | |
e1f3808e | 2035 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 2036 | } else { |
e1f3808e | 2037 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
2038 | } |
2039 | } | |
620c6cf6 | 2040 | set_cc_op(s, CC_OP_FLAGS); |
e6e5906b PB |
2041 | } |
2042 | ||
2043 | DISAS_INSN(ff1) | |
2044 | { | |
e1f3808e | 2045 | TCGv reg; |
821f7e76 | 2046 | reg = DREG(insn, 0); |
5dbb6784 | 2047 | gen_logic_cc(s, reg, OS_LONG); |
e1f3808e | 2048 | gen_helper_ff1(reg, reg); |
e6e5906b PB |
2049 | } |
2050 | ||
e1f3808e | 2051 | static TCGv gen_get_sr(DisasContext *s) |
0633879f | 2052 | { |
e1f3808e PB |
2053 | TCGv ccr; |
2054 | TCGv sr; | |
0633879f PB |
2055 | |
2056 | ccr = gen_get_ccr(s); | |
a7812ae4 | 2057 | sr = tcg_temp_new(); |
e1f3808e PB |
2058 | tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); |
2059 | tcg_gen_or_i32(sr, sr, ccr); | |
0633879f PB |
2060 | return sr; |
2061 | } | |
2062 | ||
e6e5906b PB |
2063 | DISAS_INSN(strldsr) |
2064 | { | |
2065 | uint16_t ext; | |
2066 | uint32_t addr; | |
2067 | ||
2068 | addr = s->pc - 2; | |
28b68cd7 | 2069 | ext = read_im16(env, s); |
0633879f | 2070 | if (ext != 0x46FC) { |
e6e5906b | 2071 | gen_exception(s, addr, EXCP_UNSUPPORTED); |
0633879f PB |
2072 | return; |
2073 | } | |
28b68cd7 | 2074 | ext = read_im16(env, s); |
0633879f | 2075 | if (IS_USER(s) || (ext & SR_S) == 0) { |
e6e5906b | 2076 | gen_exception(s, addr, EXCP_PRIVILEGE); |
0633879f PB |
2077 | return; |
2078 | } | |
2079 | gen_push(s, gen_get_sr(s)); | |
2080 | gen_set_sr_im(s, ext, 0); | |
e6e5906b PB |
2081 | } |
2082 | ||
2083 | DISAS_INSN(move_from_sr) | |
2084 | { | |
e1f3808e | 2085 | TCGv sr; |
0633879f | 2086 | |
7c0eb318 | 2087 | if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) { |
0633879f PB |
2088 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); |
2089 | return; | |
2090 | } | |
2091 | sr = gen_get_sr(s); | |
7c0eb318 | 2092 | DEST_EA(env, insn, OS_WORD, sr, NULL); |
e6e5906b PB |
2093 | } |
2094 | ||
2095 | DISAS_INSN(move_to_sr) | |
2096 | { | |
0633879f PB |
2097 | if (IS_USER(s)) { |
2098 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2099 | return; | |
2100 | } | |
620c6cf6 | 2101 | gen_set_sr(env, s, insn, 0); |
0633879f | 2102 | gen_lookup_tb(s); |
e6e5906b PB |
2103 | } |
2104 | ||
2105 | DISAS_INSN(move_from_usp) | |
2106 | { | |
0633879f PB |
2107 | if (IS_USER(s)) { |
2108 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2109 | return; | |
2110 | } | |
2a8327e8 GU |
2111 | tcg_gen_ld_i32(AREG(insn, 0), cpu_env, |
2112 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2113 | } |
2114 | ||
2115 | DISAS_INSN(move_to_usp) | |
2116 | { | |
0633879f PB |
2117 | if (IS_USER(s)) { |
2118 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2119 | return; | |
2120 | } | |
2a8327e8 GU |
2121 | tcg_gen_st_i32(AREG(insn, 0), cpu_env, |
2122 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2123 | } |
2124 | ||
2125 | DISAS_INSN(halt) | |
2126 | { | |
e1f3808e | 2127 | gen_exception(s, s->pc, EXCP_HALT_INSN); |
e6e5906b PB |
2128 | } |
2129 | ||
2130 | DISAS_INSN(stop) | |
2131 | { | |
0633879f PB |
2132 | uint16_t ext; |
2133 | ||
2134 | if (IS_USER(s)) { | |
2135 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2136 | return; | |
2137 | } | |
2138 | ||
28b68cd7 | 2139 | ext = read_im16(env, s); |
0633879f PB |
2140 | |
2141 | gen_set_sr_im(s, ext, 0); | |
259186a7 | 2142 | tcg_gen_movi_i32(cpu_halted, 1); |
e1f3808e | 2143 | gen_exception(s, s->pc, EXCP_HLT); |
e6e5906b PB |
2144 | } |
2145 | ||
2146 | DISAS_INSN(rte) | |
2147 | { | |
0633879f PB |
2148 | if (IS_USER(s)) { |
2149 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2150 | return; | |
2151 | } | |
2152 | gen_exception(s, s->pc - 2, EXCP_RTE); | |
e6e5906b PB |
2153 | } |
2154 | ||
2155 | DISAS_INSN(movec) | |
2156 | { | |
0633879f | 2157 | uint16_t ext; |
e1f3808e | 2158 | TCGv reg; |
0633879f PB |
2159 | |
2160 | if (IS_USER(s)) { | |
2161 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2162 | return; | |
2163 | } | |
2164 | ||
28b68cd7 | 2165 | ext = read_im16(env, s); |
0633879f PB |
2166 | |
2167 | if (ext & 0x8000) { | |
2168 | reg = AREG(ext, 12); | |
2169 | } else { | |
2170 | reg = DREG(ext, 12); | |
2171 | } | |
e1f3808e | 2172 | gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); |
0633879f | 2173 | gen_lookup_tb(s); |
e6e5906b PB |
2174 | } |
2175 | ||
2176 | DISAS_INSN(intouch) | |
2177 | { | |
0633879f PB |
2178 | if (IS_USER(s)) { |
2179 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2180 | return; | |
2181 | } | |
2182 | /* ICache fetch. Implement as no-op. */ | |
e6e5906b PB |
2183 | } |
2184 | ||
2185 | DISAS_INSN(cpushl) | |
2186 | { | |
0633879f PB |
2187 | if (IS_USER(s)) { |
2188 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2189 | return; | |
2190 | } | |
2191 | /* Cache push/invalidate. Implement as no-op. */ | |
e6e5906b PB |
2192 | } |
2193 | ||
2194 | DISAS_INSN(wddata) | |
2195 | { | |
2196 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2197 | } | |
2198 | ||
2199 | DISAS_INSN(wdebug) | |
2200 | { | |
a47dddd7 AF |
2201 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2202 | ||
0633879f PB |
2203 | if (IS_USER(s)) { |
2204 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2205 | return; | |
2206 | } | |
2207 | /* TODO: Implement wdebug. */ | |
a47dddd7 | 2208 | cpu_abort(CPU(cpu), "WDEBUG not implemented"); |
e6e5906b PB |
2209 | } |
2210 | ||
2211 | DISAS_INSN(trap) | |
2212 | { | |
2213 | gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); | |
2214 | } | |
2215 | ||
2216 | /* ??? FP exceptions are not implemented. Most exceptions are deferred until | |
2217 | immediately before the next FP instruction is executed. */ | |
2218 | DISAS_INSN(fpu) | |
2219 | { | |
2220 | uint16_t ext; | |
a7812ae4 | 2221 | int32_t offset; |
e6e5906b | 2222 | int opmode; |
a7812ae4 PB |
2223 | TCGv_i64 src; |
2224 | TCGv_i64 dest; | |
2225 | TCGv_i64 res; | |
2226 | TCGv tmp32; | |
e6e5906b | 2227 | int round; |
a7812ae4 | 2228 | int set_dest; |
e6e5906b PB |
2229 | int opsize; |
2230 | ||
28b68cd7 | 2231 | ext = read_im16(env, s); |
e6e5906b PB |
2232 | opmode = ext & 0x7f; |
2233 | switch ((ext >> 13) & 7) { | |
2234 | case 0: case 2: | |
2235 | break; | |
2236 | case 1: | |
2237 | goto undef; | |
2238 | case 3: /* fmove out */ | |
2239 | src = FREG(ext, 7); | |
a7812ae4 | 2240 | tmp32 = tcg_temp_new_i32(); |
e6e5906b PB |
2241 | /* fmove */ |
2242 | /* ??? TODO: Proper behavior on overflow. */ | |
2243 | switch ((ext >> 10) & 7) { | |
2244 | case 0: | |
2245 | opsize = OS_LONG; | |
a7812ae4 | 2246 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2247 | break; |
2248 | case 1: | |
2249 | opsize = OS_SINGLE; | |
a7812ae4 | 2250 | gen_helper_f64_to_f32(tmp32, cpu_env, src); |
e6e5906b PB |
2251 | break; |
2252 | case 4: | |
2253 | opsize = OS_WORD; | |
a7812ae4 | 2254 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b | 2255 | break; |
a7812ae4 PB |
2256 | case 5: /* OS_DOUBLE */ |
2257 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2258 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2259 | case 2: |
2260 | case 3: | |
243ee8f7 | 2261 | break; |
a7812ae4 PB |
2262 | case 4: |
2263 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2264 | break; | |
2265 | case 5: | |
d4d79bb1 | 2266 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2267 | s->pc += 2; |
2268 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2269 | break; | |
2270 | default: | |
2271 | goto undef; | |
2272 | } | |
2273 | gen_store64(s, tmp32, src); | |
c59b97aa | 2274 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2275 | case 3: |
2276 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2277 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2278 | break; | |
2279 | case 4: | |
2280 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2281 | break; | |
2282 | } | |
2283 | tcg_temp_free_i32(tmp32); | |
2284 | return; | |
e6e5906b PB |
2285 | case 6: |
2286 | opsize = OS_BYTE; | |
a7812ae4 | 2287 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2288 | break; |
2289 | default: | |
2290 | goto undef; | |
2291 | } | |
d4d79bb1 | 2292 | DEST_EA(env, insn, opsize, tmp32, NULL); |
a7812ae4 | 2293 | tcg_temp_free_i32(tmp32); |
e6e5906b PB |
2294 | return; |
2295 | case 4: /* fmove to control register. */ | |
2296 | switch ((ext >> 10) & 7) { | |
2297 | case 4: /* FPCR */ | |
2298 | /* Not implemented. Ignore writes. */ | |
2299 | break; | |
2300 | case 1: /* FPIAR */ | |
2301 | case 2: /* FPSR */ | |
2302 | default: | |
2303 | cpu_abort(NULL, "Unimplemented: fmove to control %d", | |
2304 | (ext >> 10) & 7); | |
2305 | } | |
2306 | break; | |
2307 | case 5: /* fmove from control register. */ | |
2308 | switch ((ext >> 10) & 7) { | |
2309 | case 4: /* FPCR */ | |
2310 | /* Not implemented. Always return zero. */ | |
351326a6 | 2311 | tmp32 = tcg_const_i32(0); |
e6e5906b PB |
2312 | break; |
2313 | case 1: /* FPIAR */ | |
2314 | case 2: /* FPSR */ | |
2315 | default: | |
2316 | cpu_abort(NULL, "Unimplemented: fmove from control %d", | |
2317 | (ext >> 10) & 7); | |
2318 | goto undef; | |
2319 | } | |
d4d79bb1 | 2320 | DEST_EA(env, insn, OS_LONG, tmp32, NULL); |
e6e5906b | 2321 | break; |
5fafdf24 | 2322 | case 6: /* fmovem */ |
e6e5906b PB |
2323 | case 7: |
2324 | { | |
e1f3808e PB |
2325 | TCGv addr; |
2326 | uint16_t mask; | |
2327 | int i; | |
2328 | if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) | |
2329 | goto undef; | |
d4d79bb1 | 2330 | tmp32 = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2331 | if (IS_NULL_QREG(tmp32)) { |
e1f3808e PB |
2332 | gen_addr_fault(s); |
2333 | return; | |
2334 | } | |
a7812ae4 PB |
2335 | addr = tcg_temp_new_i32(); |
2336 | tcg_gen_mov_i32(addr, tmp32); | |
e1f3808e PB |
2337 | mask = 0x80; |
2338 | for (i = 0; i < 8; i++) { | |
2339 | if (ext & mask) { | |
e1f3808e PB |
2340 | dest = FREG(i, 0); |
2341 | if (ext & (1 << 13)) { | |
2342 | /* store */ | |
2343 | tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); | |
2344 | } else { | |
2345 | /* load */ | |
2346 | tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); | |
2347 | } | |
2348 | if (ext & (mask - 1)) | |
2349 | tcg_gen_addi_i32(addr, addr, 8); | |
e6e5906b | 2350 | } |
e1f3808e | 2351 | mask >>= 1; |
e6e5906b | 2352 | } |
18307f26 | 2353 | tcg_temp_free_i32(addr); |
e6e5906b PB |
2354 | } |
2355 | return; | |
2356 | } | |
2357 | if (ext & (1 << 14)) { | |
e6e5906b PB |
2358 | /* Source effective address. */ |
2359 | switch ((ext >> 10) & 7) { | |
2360 | case 0: opsize = OS_LONG; break; | |
2361 | case 1: opsize = OS_SINGLE; break; | |
2362 | case 4: opsize = OS_WORD; break; | |
2363 | case 5: opsize = OS_DOUBLE; break; | |
2364 | case 6: opsize = OS_BYTE; break; | |
2365 | default: | |
2366 | goto undef; | |
2367 | } | |
e6e5906b | 2368 | if (opsize == OS_DOUBLE) { |
a7812ae4 PB |
2369 | tmp32 = tcg_temp_new_i32(); |
2370 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2371 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2372 | case 2: |
2373 | case 3: | |
243ee8f7 | 2374 | break; |
a7812ae4 PB |
2375 | case 4: |
2376 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2377 | break; | |
2378 | case 5: | |
d4d79bb1 | 2379 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2380 | s->pc += 2; |
2381 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2382 | break; | |
2383 | case 7: | |
d4d79bb1 | 2384 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2385 | offset += s->pc - 2; |
2386 | s->pc += 2; | |
2387 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2388 | break; | |
2389 | default: | |
2390 | goto undef; | |
2391 | } | |
2392 | src = gen_load64(s, tmp32); | |
c59b97aa | 2393 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2394 | case 3: |
2395 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2396 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2397 | break; | |
2398 | case 4: | |
2399 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2400 | break; | |
2401 | } | |
2402 | tcg_temp_free_i32(tmp32); | |
e6e5906b | 2403 | } else { |
d4d79bb1 | 2404 | SRC_EA(env, tmp32, opsize, 1, NULL); |
a7812ae4 | 2405 | src = tcg_temp_new_i64(); |
e6e5906b PB |
2406 | switch (opsize) { |
2407 | case OS_LONG: | |
2408 | case OS_WORD: | |
2409 | case OS_BYTE: | |
a7812ae4 | 2410 | gen_helper_i32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2411 | break; |
2412 | case OS_SINGLE: | |
a7812ae4 | 2413 | gen_helper_f32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2414 | break; |
2415 | } | |
2416 | } | |
2417 | } else { | |
2418 | /* Source register. */ | |
2419 | src = FREG(ext, 10); | |
2420 | } | |
2421 | dest = FREG(ext, 7); | |
a7812ae4 | 2422 | res = tcg_temp_new_i64(); |
e6e5906b | 2423 | if (opmode != 0x3a) |
e1f3808e | 2424 | tcg_gen_mov_f64(res, dest); |
e6e5906b | 2425 | round = 1; |
a7812ae4 | 2426 | set_dest = 1; |
e6e5906b PB |
2427 | switch (opmode) { |
2428 | case 0: case 0x40: case 0x44: /* fmove */ | |
e1f3808e | 2429 | tcg_gen_mov_f64(res, src); |
e6e5906b PB |
2430 | break; |
2431 | case 1: /* fint */ | |
e1f3808e | 2432 | gen_helper_iround_f64(res, cpu_env, src); |
e6e5906b PB |
2433 | round = 0; |
2434 | break; | |
2435 | case 3: /* fintrz */ | |
e1f3808e | 2436 | gen_helper_itrunc_f64(res, cpu_env, src); |
e6e5906b PB |
2437 | round = 0; |
2438 | break; | |
2439 | case 4: case 0x41: case 0x45: /* fsqrt */ | |
e1f3808e | 2440 | gen_helper_sqrt_f64(res, cpu_env, src); |
e6e5906b PB |
2441 | break; |
2442 | case 0x18: case 0x58: case 0x5c: /* fabs */ | |
e1f3808e | 2443 | gen_helper_abs_f64(res, src); |
e6e5906b PB |
2444 | break; |
2445 | case 0x1a: case 0x5a: case 0x5e: /* fneg */ | |
e1f3808e | 2446 | gen_helper_chs_f64(res, src); |
e6e5906b PB |
2447 | break; |
2448 | case 0x20: case 0x60: case 0x64: /* fdiv */ | |
e1f3808e | 2449 | gen_helper_div_f64(res, cpu_env, res, src); |
e6e5906b PB |
2450 | break; |
2451 | case 0x22: case 0x62: case 0x66: /* fadd */ | |
e1f3808e | 2452 | gen_helper_add_f64(res, cpu_env, res, src); |
e6e5906b PB |
2453 | break; |
2454 | case 0x23: case 0x63: case 0x67: /* fmul */ | |
e1f3808e | 2455 | gen_helper_mul_f64(res, cpu_env, res, src); |
e6e5906b PB |
2456 | break; |
2457 | case 0x28: case 0x68: case 0x6c: /* fsub */ | |
e1f3808e | 2458 | gen_helper_sub_f64(res, cpu_env, res, src); |
e6e5906b PB |
2459 | break; |
2460 | case 0x38: /* fcmp */ | |
e1f3808e | 2461 | gen_helper_sub_cmp_f64(res, cpu_env, res, src); |
a7812ae4 | 2462 | set_dest = 0; |
e6e5906b PB |
2463 | round = 0; |
2464 | break; | |
2465 | case 0x3a: /* ftst */ | |
e1f3808e | 2466 | tcg_gen_mov_f64(res, src); |
a7812ae4 | 2467 | set_dest = 0; |
e6e5906b PB |
2468 | round = 0; |
2469 | break; | |
2470 | default: | |
2471 | goto undef; | |
2472 | } | |
a7812ae4 PB |
2473 | if (ext & (1 << 14)) { |
2474 | tcg_temp_free_i64(src); | |
2475 | } | |
e6e5906b PB |
2476 | if (round) { |
2477 | if (opmode & 0x40) { | |
2478 | if ((opmode & 0x4) != 0) | |
2479 | round = 0; | |
2480 | } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { | |
2481 | round = 0; | |
2482 | } | |
2483 | } | |
2484 | if (round) { | |
a7812ae4 | 2485 | TCGv tmp = tcg_temp_new_i32(); |
e1f3808e PB |
2486 | gen_helper_f64_to_f32(tmp, cpu_env, res); |
2487 | gen_helper_f32_to_f64(res, cpu_env, tmp); | |
a7812ae4 | 2488 | tcg_temp_free_i32(tmp); |
5fafdf24 | 2489 | } |
e1f3808e | 2490 | tcg_gen_mov_f64(QREG_FP_RESULT, res); |
a7812ae4 | 2491 | if (set_dest) { |
e1f3808e | 2492 | tcg_gen_mov_f64(dest, res); |
e6e5906b | 2493 | } |
a7812ae4 | 2494 | tcg_temp_free_i64(res); |
e6e5906b PB |
2495 | return; |
2496 | undef: | |
a7812ae4 | 2497 | /* FIXME: Is this right for offset addressing modes? */ |
e6e5906b | 2498 | s->pc -= 2; |
d4d79bb1 | 2499 | disas_undef_fpu(env, s, insn); |
e6e5906b PB |
2500 | } |
2501 | ||
2502 | DISAS_INSN(fbcc) | |
2503 | { | |
2504 | uint32_t offset; | |
2505 | uint32_t addr; | |
e1f3808e | 2506 | TCGv flag; |
42a268c2 | 2507 | TCGLabel *l1; |
e6e5906b PB |
2508 | |
2509 | addr = s->pc; | |
d4d79bb1 | 2510 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
2511 | s->pc += 2; |
2512 | if (insn & (1 << 6)) { | |
28b68cd7 | 2513 | offset = (offset << 16) | read_im16(env, s); |
e6e5906b PB |
2514 | } |
2515 | ||
2516 | l1 = gen_new_label(); | |
2517 | /* TODO: Raise BSUN exception. */ | |
a7812ae4 | 2518 | flag = tcg_temp_new(); |
e1f3808e | 2519 | gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); |
e6e5906b PB |
2520 | /* Jump to l1 if condition is true. */ |
2521 | switch (insn & 0xf) { | |
2522 | case 0: /* f */ | |
2523 | break; | |
2524 | case 1: /* eq (=0) */ | |
e1f3808e | 2525 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2526 | break; |
2527 | case 2: /* ogt (=1) */ | |
e1f3808e | 2528 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2529 | break; |
2530 | case 3: /* oge (=0 or =1) */ | |
e1f3808e | 2531 | tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2532 | break; |
2533 | case 4: /* olt (=-1) */ | |
e1f3808e | 2534 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2535 | break; |
2536 | case 5: /* ole (=-1 or =0) */ | |
e1f3808e | 2537 | tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2538 | break; |
2539 | case 6: /* ogl (=-1 or =1) */ | |
e1f3808e PB |
2540 | tcg_gen_andi_i32(flag, flag, 1); |
2541 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2542 | break; |
2543 | case 7: /* or (=2) */ | |
e1f3808e | 2544 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2545 | break; |
2546 | case 8: /* un (<2) */ | |
e1f3808e | 2547 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2548 | break; |
2549 | case 9: /* ueq (=0 or =2) */ | |
e1f3808e PB |
2550 | tcg_gen_andi_i32(flag, flag, 1); |
2551 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2552 | break; |
2553 | case 10: /* ugt (>0) */ | |
e1f3808e | 2554 | tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2555 | break; |
2556 | case 11: /* uge (>=0) */ | |
e1f3808e | 2557 | tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2558 | break; |
2559 | case 12: /* ult (=-1 or =2) */ | |
e1f3808e | 2560 | tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2561 | break; |
2562 | case 13: /* ule (!=1) */ | |
e1f3808e | 2563 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2564 | break; |
2565 | case 14: /* ne (!=0) */ | |
e1f3808e | 2566 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2567 | break; |
2568 | case 15: /* t */ | |
e1f3808e | 2569 | tcg_gen_br(l1); |
e6e5906b PB |
2570 | break; |
2571 | } | |
2572 | gen_jmp_tb(s, 0, s->pc); | |
2573 | gen_set_label(l1); | |
2574 | gen_jmp_tb(s, 1, addr + offset); | |
2575 | } | |
2576 | ||
0633879f PB |
2577 | DISAS_INSN(frestore) |
2578 | { | |
a47dddd7 AF |
2579 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2580 | ||
0633879f | 2581 | /* TODO: Implement frestore. */ |
a47dddd7 | 2582 | cpu_abort(CPU(cpu), "FRESTORE not implemented"); |
0633879f PB |
2583 | } |
2584 | ||
2585 | DISAS_INSN(fsave) | |
2586 | { | |
a47dddd7 AF |
2587 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2588 | ||
0633879f | 2589 | /* TODO: Implement fsave. */ |
a47dddd7 | 2590 | cpu_abort(CPU(cpu), "FSAVE not implemented"); |
0633879f PB |
2591 | } |
2592 | ||
e1f3808e | 2593 | static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) |
acf930aa | 2594 | { |
a7812ae4 | 2595 | TCGv tmp = tcg_temp_new(); |
acf930aa PB |
2596 | if (s->env->macsr & MACSR_FI) { |
2597 | if (upper) | |
e1f3808e | 2598 | tcg_gen_andi_i32(tmp, val, 0xffff0000); |
acf930aa | 2599 | else |
e1f3808e | 2600 | tcg_gen_shli_i32(tmp, val, 16); |
acf930aa PB |
2601 | } else if (s->env->macsr & MACSR_SU) { |
2602 | if (upper) | |
e1f3808e | 2603 | tcg_gen_sari_i32(tmp, val, 16); |
acf930aa | 2604 | else |
e1f3808e | 2605 | tcg_gen_ext16s_i32(tmp, val); |
acf930aa PB |
2606 | } else { |
2607 | if (upper) | |
e1f3808e | 2608 | tcg_gen_shri_i32(tmp, val, 16); |
acf930aa | 2609 | else |
e1f3808e | 2610 | tcg_gen_ext16u_i32(tmp, val); |
acf930aa PB |
2611 | } |
2612 | return tmp; | |
2613 | } | |
2614 | ||
e1f3808e PB |
2615 | static void gen_mac_clear_flags(void) |
2616 | { | |
2617 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, | |
2618 | ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); | |
2619 | } | |
2620 | ||
acf930aa PB |
2621 | DISAS_INSN(mac) |
2622 | { | |
e1f3808e PB |
2623 | TCGv rx; |
2624 | TCGv ry; | |
acf930aa PB |
2625 | uint16_t ext; |
2626 | int acc; | |
e1f3808e PB |
2627 | TCGv tmp; |
2628 | TCGv addr; | |
2629 | TCGv loadval; | |
acf930aa | 2630 | int dual; |
e1f3808e PB |
2631 | TCGv saved_flags; |
2632 | ||
a7812ae4 PB |
2633 | if (!s->done_mac) { |
2634 | s->mactmp = tcg_temp_new_i64(); | |
2635 | s->done_mac = 1; | |
2636 | } | |
acf930aa | 2637 | |
28b68cd7 | 2638 | ext = read_im16(env, s); |
acf930aa PB |
2639 | |
2640 | acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); | |
2641 | dual = ((insn & 0x30) != 0 && (ext & 3) != 0); | |
d315c888 | 2642 | if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { |
d4d79bb1 | 2643 | disas_undef(env, s, insn); |
d315c888 PB |
2644 | return; |
2645 | } | |
acf930aa PB |
2646 | if (insn & 0x30) { |
2647 | /* MAC with load. */ | |
d4d79bb1 | 2648 | tmp = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2649 | addr = tcg_temp_new(); |
e1f3808e | 2650 | tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); |
acf930aa PB |
2651 | /* Load the value now to ensure correct exception behavior. |
2652 | Perform writeback after reading the MAC inputs. */ | |
2653 | loadval = gen_load(s, OS_LONG, addr, 0); | |
2654 | ||
2655 | acc ^= 1; | |
2656 | rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); | |
2657 | ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); | |
2658 | } else { | |
e1f3808e | 2659 | loadval = addr = NULL_QREG; |
acf930aa PB |
2660 | rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
2661 | ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
2662 | } | |
2663 | ||
e1f3808e PB |
2664 | gen_mac_clear_flags(); |
2665 | #if 0 | |
acf930aa | 2666 | l1 = -1; |
e1f3808e | 2667 | /* Disabled because conditional branches clobber temporary vars. */ |
acf930aa PB |
2668 | if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { |
2669 | /* Skip the multiply if we know we will ignore it. */ | |
2670 | l1 = gen_new_label(); | |
a7812ae4 | 2671 | tmp = tcg_temp_new(); |
e1f3808e | 2672 | tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); |
acf930aa PB |
2673 | gen_op_jmp_nz32(tmp, l1); |
2674 | } | |
e1f3808e | 2675 | #endif |
acf930aa PB |
2676 | |
2677 | if ((ext & 0x0800) == 0) { | |
2678 | /* Word. */ | |
2679 | rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); | |
2680 | ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); | |
2681 | } | |
2682 | if (s->env->macsr & MACSR_FI) { | |
e1f3808e | 2683 | gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2684 | } else { |
2685 | if (s->env->macsr & MACSR_SU) | |
e1f3808e | 2686 | gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); |
acf930aa | 2687 | else |
e1f3808e | 2688 | gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2689 | switch ((ext >> 9) & 3) { |
2690 | case 1: | |
e1f3808e | 2691 | tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2692 | break; |
2693 | case 3: | |
e1f3808e | 2694 | tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2695 | break; |
2696 | } | |
2697 | } | |
2698 | ||
2699 | if (dual) { | |
2700 | /* Save the overflow flag from the multiply. */ | |
a7812ae4 | 2701 | saved_flags = tcg_temp_new(); |
e1f3808e PB |
2702 | tcg_gen_mov_i32(saved_flags, QREG_MACSR); |
2703 | } else { | |
2704 | saved_flags = NULL_QREG; | |
acf930aa PB |
2705 | } |
2706 | ||
e1f3808e PB |
2707 | #if 0 |
2708 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2709 | if ((s->env->macsr & MACSR_OMC) != 0 && dual) { |
2710 | /* Skip the accumulate if the value is already saturated. */ | |
2711 | l1 = gen_new_label(); | |
a7812ae4 | 2712 | tmp = tcg_temp_new(); |
351326a6 | 2713 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2714 | gen_op_jmp_nz32(tmp, l1); |
2715 | } | |
e1f3808e | 2716 | #endif |
acf930aa PB |
2717 | |
2718 | if (insn & 0x100) | |
e1f3808e | 2719 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2720 | else |
e1f3808e | 2721 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa PB |
2722 | |
2723 | if (s->env->macsr & MACSR_FI) | |
e1f3808e | 2724 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2725 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2726 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2727 | else |
e1f3808e | 2728 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2729 | |
e1f3808e PB |
2730 | #if 0 |
2731 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2732 | if (l1 != -1) |
2733 | gen_set_label(l1); | |
e1f3808e | 2734 | #endif |
acf930aa PB |
2735 | |
2736 | if (dual) { | |
2737 | /* Dual accumulate variant. */ | |
2738 | acc = (ext >> 2) & 3; | |
2739 | /* Restore the overflow flag from the multiplier. */ | |
e1f3808e PB |
2740 | tcg_gen_mov_i32(QREG_MACSR, saved_flags); |
2741 | #if 0 | |
2742 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2743 | if ((s->env->macsr & MACSR_OMC) != 0) { |
2744 | /* Skip the accumulate if the value is already saturated. */ | |
2745 | l1 = gen_new_label(); | |
a7812ae4 | 2746 | tmp = tcg_temp_new(); |
351326a6 | 2747 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2748 | gen_op_jmp_nz32(tmp, l1); |
2749 | } | |
e1f3808e | 2750 | #endif |
acf930aa | 2751 | if (ext & 2) |
e1f3808e | 2752 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2753 | else |
e1f3808e | 2754 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2755 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2756 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2757 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2758 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2759 | else |
e1f3808e PB |
2760 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
2761 | #if 0 | |
2762 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2763 | if (l1 != -1) |
2764 | gen_set_label(l1); | |
e1f3808e | 2765 | #endif |
acf930aa | 2766 | } |
e1f3808e | 2767 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); |
acf930aa PB |
2768 | |
2769 | if (insn & 0x30) { | |
e1f3808e | 2770 | TCGv rw; |
acf930aa | 2771 | rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
e1f3808e | 2772 | tcg_gen_mov_i32(rw, loadval); |
acf930aa PB |
2773 | /* FIXME: Should address writeback happen with the masked or |
2774 | unmasked value? */ | |
2775 | switch ((insn >> 3) & 7) { | |
2776 | case 3: /* Post-increment. */ | |
e1f3808e | 2777 | tcg_gen_addi_i32(AREG(insn, 0), addr, 4); |
acf930aa PB |
2778 | break; |
2779 | case 4: /* Pre-decrement. */ | |
e1f3808e | 2780 | tcg_gen_mov_i32(AREG(insn, 0), addr); |
acf930aa PB |
2781 | } |
2782 | } | |
2783 | } | |
2784 | ||
2785 | DISAS_INSN(from_mac) | |
2786 | { | |
e1f3808e | 2787 | TCGv rx; |
a7812ae4 | 2788 | TCGv_i64 acc; |
e1f3808e | 2789 | int accnum; |
acf930aa PB |
2790 | |
2791 | rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e PB |
2792 | accnum = (insn >> 9) & 3; |
2793 | acc = MACREG(accnum); | |
acf930aa | 2794 | if (s->env->macsr & MACSR_FI) { |
a7812ae4 | 2795 | gen_helper_get_macf(rx, cpu_env, acc); |
acf930aa | 2796 | } else if ((s->env->macsr & MACSR_OMC) == 0) { |
ecc7b3aa | 2797 | tcg_gen_extrl_i64_i32(rx, acc); |
acf930aa | 2798 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2799 | gen_helper_get_macs(rx, acc); |
acf930aa | 2800 | } else { |
e1f3808e PB |
2801 | gen_helper_get_macu(rx, acc); |
2802 | } | |
2803 | if (insn & 0x40) { | |
2804 | tcg_gen_movi_i64(acc, 0); | |
2805 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
acf930aa | 2806 | } |
acf930aa PB |
2807 | } |
2808 | ||
2809 | DISAS_INSN(move_mac) | |
2810 | { | |
e1f3808e | 2811 | /* FIXME: This can be done without a helper. */ |
acf930aa | 2812 | int src; |
e1f3808e | 2813 | TCGv dest; |
acf930aa | 2814 | src = insn & 3; |
e1f3808e PB |
2815 | dest = tcg_const_i32((insn >> 9) & 3); |
2816 | gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); | |
2817 | gen_mac_clear_flags(); | |
2818 | gen_helper_mac_set_flags(cpu_env, dest); | |
acf930aa PB |
2819 | } |
2820 | ||
2821 | DISAS_INSN(from_macsr) | |
2822 | { | |
e1f3808e | 2823 | TCGv reg; |
acf930aa PB |
2824 | |
2825 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e | 2826 | tcg_gen_mov_i32(reg, QREG_MACSR); |
acf930aa PB |
2827 | } |
2828 | ||
2829 | DISAS_INSN(from_mask) | |
2830 | { | |
e1f3808e | 2831 | TCGv reg; |
acf930aa | 2832 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2833 | tcg_gen_mov_i32(reg, QREG_MAC_MASK); |
acf930aa PB |
2834 | } |
2835 | ||
2836 | DISAS_INSN(from_mext) | |
2837 | { | |
e1f3808e PB |
2838 | TCGv reg; |
2839 | TCGv acc; | |
acf930aa | 2840 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2841 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2842 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2843 | gen_helper_get_mac_extf(reg, cpu_env, acc); |
acf930aa | 2844 | else |
e1f3808e | 2845 | gen_helper_get_mac_exti(reg, cpu_env, acc); |
acf930aa PB |
2846 | } |
2847 | ||
2848 | DISAS_INSN(macsr_to_ccr) | |
2849 | { | |
620c6cf6 RH |
2850 | TCGv tmp = tcg_temp_new(); |
2851 | tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); | |
2852 | gen_helper_set_sr(cpu_env, tmp); | |
2853 | tcg_temp_free(tmp); | |
9fdb533f | 2854 | set_cc_op(s, CC_OP_FLAGS); |
acf930aa PB |
2855 | } |
2856 | ||
2857 | DISAS_INSN(to_mac) | |
2858 | { | |
a7812ae4 | 2859 | TCGv_i64 acc; |
e1f3808e PB |
2860 | TCGv val; |
2861 | int accnum; | |
2862 | accnum = (insn >> 9) & 3; | |
2863 | acc = MACREG(accnum); | |
d4d79bb1 | 2864 | SRC_EA(env, val, OS_LONG, 0, NULL); |
acf930aa | 2865 | if (s->env->macsr & MACSR_FI) { |
e1f3808e PB |
2866 | tcg_gen_ext_i32_i64(acc, val); |
2867 | tcg_gen_shli_i64(acc, acc, 8); | |
acf930aa | 2868 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2869 | tcg_gen_ext_i32_i64(acc, val); |
acf930aa | 2870 | } else { |
e1f3808e | 2871 | tcg_gen_extu_i32_i64(acc, val); |
acf930aa | 2872 | } |
e1f3808e PB |
2873 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); |
2874 | gen_mac_clear_flags(); | |
2875 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); | |
acf930aa PB |
2876 | } |
2877 | ||
2878 | DISAS_INSN(to_macsr) | |
2879 | { | |
e1f3808e | 2880 | TCGv val; |
d4d79bb1 | 2881 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2882 | gen_helper_set_macsr(cpu_env, val); |
acf930aa PB |
2883 | gen_lookup_tb(s); |
2884 | } | |
2885 | ||
2886 | DISAS_INSN(to_mask) | |
2887 | { | |
e1f3808e | 2888 | TCGv val; |
d4d79bb1 | 2889 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2890 | tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); |
acf930aa PB |
2891 | } |
2892 | ||
2893 | DISAS_INSN(to_mext) | |
2894 | { | |
e1f3808e PB |
2895 | TCGv val; |
2896 | TCGv acc; | |
d4d79bb1 | 2897 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2898 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2899 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2900 | gen_helper_set_mac_extf(cpu_env, val, acc); |
acf930aa | 2901 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2902 | gen_helper_set_mac_exts(cpu_env, val, acc); |
acf930aa | 2903 | else |
e1f3808e | 2904 | gen_helper_set_mac_extu(cpu_env, val, acc); |
acf930aa PB |
2905 | } |
2906 | ||
e6e5906b PB |
2907 | static disas_proc opcode_table[65536]; |
2908 | ||
2909 | static void | |
2910 | register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) | |
2911 | { | |
2912 | int i; | |
2913 | int from; | |
2914 | int to; | |
2915 | ||
2916 | /* Sanity check. All set bits must be included in the mask. */ | |
5fc4adf6 PB |
2917 | if (opcode & ~mask) { |
2918 | fprintf(stderr, | |
2919 | "qemu internal error: bogus opcode definition %04x/%04x\n", | |
2920 | opcode, mask); | |
e6e5906b | 2921 | abort(); |
5fc4adf6 | 2922 | } |
e6e5906b PB |
2923 | /* This could probably be cleverer. For now just optimize the case where |
2924 | the top bits are known. */ | |
2925 | /* Find the first zero bit in the mask. */ | |
2926 | i = 0x8000; | |
2927 | while ((i & mask) != 0) | |
2928 | i >>= 1; | |
2929 | /* Iterate over all combinations of this and lower bits. */ | |
2930 | if (i == 0) | |
2931 | i = 1; | |
2932 | else | |
2933 | i <<= 1; | |
2934 | from = opcode & ~(i - 1); | |
2935 | to = from + i; | |
0633879f | 2936 | for (i = from; i < to; i++) { |
e6e5906b PB |
2937 | if ((i & mask) == opcode) |
2938 | opcode_table[i] = proc; | |
0633879f | 2939 | } |
e6e5906b PB |
2940 | } |
2941 | ||
2942 | /* Register m68k opcode handlers. Order is important. | |
2943 | Later insn override earlier ones. */ | |
0402f767 | 2944 | void register_m68k_insns (CPUM68KState *env) |
e6e5906b | 2945 | { |
b2085257 JPAG |
2946 | /* Build the opcode table only once to avoid |
2947 | multithreading issues. */ | |
2948 | if (opcode_table[0] != NULL) { | |
2949 | return; | |
2950 | } | |
f076803b LV |
2951 | |
2952 | /* use BASE() for instruction available | |
2953 | * for CF_ISA_A and M68000. | |
2954 | */ | |
2955 | #define BASE(name, opcode, mask) \ | |
2956 | register_opcode(disas_##name, 0x##opcode, 0x##mask) | |
d315c888 | 2957 | #define INSN(name, opcode, mask, feature) do { \ |
0402f767 | 2958 | if (m68k_feature(env, M68K_FEATURE_##feature)) \ |
f076803b | 2959 | BASE(name, opcode, mask); \ |
d315c888 | 2960 | } while(0) |
f076803b | 2961 | BASE(undef, 0000, 0000); |
0402f767 | 2962 | INSN(arith_im, 0080, fff8, CF_ISA_A); |
f076803b LV |
2963 | INSN(arith_im, 0000, ff00, M68000); |
2964 | INSN(undef, 00c0, ffc0, M68000); | |
d315c888 | 2965 | INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); |
f076803b LV |
2966 | BASE(bitop_reg, 0100, f1c0); |
2967 | BASE(bitop_reg, 0140, f1c0); | |
2968 | BASE(bitop_reg, 0180, f1c0); | |
2969 | BASE(bitop_reg, 01c0, f1c0); | |
0402f767 | 2970 | INSN(arith_im, 0280, fff8, CF_ISA_A); |
f076803b LV |
2971 | INSN(arith_im, 0200, ff00, M68000); |
2972 | INSN(undef, 02c0, ffc0, M68000); | |
d315c888 | 2973 | INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); |
0402f767 | 2974 | INSN(arith_im, 0480, fff8, CF_ISA_A); |
f076803b LV |
2975 | INSN(arith_im, 0400, ff00, M68000); |
2976 | INSN(undef, 04c0, ffc0, M68000); | |
2977 | INSN(arith_im, 0600, ff00, M68000); | |
2978 | INSN(undef, 06c0, ffc0, M68000); | |
d315c888 | 2979 | INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); |
0402f767 | 2980 | INSN(arith_im, 0680, fff8, CF_ISA_A); |
0402f767 | 2981 | INSN(arith_im, 0c00, ff38, CF_ISA_A); |
f076803b LV |
2982 | INSN(arith_im, 0c00, ff00, M68000); |
2983 | BASE(bitop_im, 0800, ffc0); | |
2984 | BASE(bitop_im, 0840, ffc0); | |
2985 | BASE(bitop_im, 0880, ffc0); | |
2986 | BASE(bitop_im, 08c0, ffc0); | |
2987 | INSN(arith_im, 0a80, fff8, CF_ISA_A); | |
2988 | INSN(arith_im, 0a00, ff00, M68000); | |
2989 | BASE(move, 1000, f000); | |
2990 | BASE(move, 2000, f000); | |
2991 | BASE(move, 3000, f000); | |
d315c888 | 2992 | INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); |
0402f767 PB |
2993 | INSN(negx, 4080, fff8, CF_ISA_A); |
2994 | INSN(move_from_sr, 40c0, fff8, CF_ISA_A); | |
f076803b LV |
2995 | INSN(move_from_sr, 40c0, ffc0, M68000); |
2996 | BASE(lea, 41c0, f1c0); | |
2997 | BASE(clr, 4200, ff00); | |
2998 | BASE(undef, 42c0, ffc0); | |
0402f767 | 2999 | INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); |
7c0eb318 | 3000 | INSN(move_from_ccr, 42c0, ffc0, M68000); |
0402f767 | 3001 | INSN(neg, 4480, fff8, CF_ISA_A); |
f076803b LV |
3002 | INSN(neg, 4400, ff00, M68000); |
3003 | INSN(undef, 44c0, ffc0, M68000); | |
3004 | BASE(move_to_ccr, 44c0, ffc0); | |
0402f767 | 3005 | INSN(not, 4680, fff8, CF_ISA_A); |
f076803b LV |
3006 | INSN(not, 4600, ff00, M68000); |
3007 | INSN(undef, 46c0, ffc0, M68000); | |
0402f767 | 3008 | INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); |
f076803b LV |
3009 | BASE(pea, 4840, ffc0); |
3010 | BASE(swap, 4840, fff8); | |
3011 | BASE(movem, 48c0, fbc0); | |
3012 | BASE(ext, 4880, fff8); | |
3013 | BASE(ext, 48c0, fff8); | |
3014 | BASE(ext, 49c0, fff8); | |
3015 | BASE(tst, 4a00, ff00); | |
0402f767 | 3016 | INSN(tas, 4ac0, ffc0, CF_ISA_B); |
f076803b | 3017 | INSN(tas, 4ac0, ffc0, M68000); |
0402f767 PB |
3018 | INSN(halt, 4ac8, ffff, CF_ISA_A); |
3019 | INSN(pulse, 4acc, ffff, CF_ISA_A); | |
f076803b | 3020 | BASE(illegal, 4afc, ffff); |
0402f767 | 3021 | INSN(mull, 4c00, ffc0, CF_ISA_A); |
f076803b | 3022 | INSN(mull, 4c00, ffc0, LONG_MULDIV); |
0402f767 | 3023 | INSN(divl, 4c40, ffc0, CF_ISA_A); |
f076803b | 3024 | INSN(divl, 4c40, ffc0, LONG_MULDIV); |
0402f767 | 3025 | INSN(sats, 4c80, fff8, CF_ISA_B); |
f076803b LV |
3026 | BASE(trap, 4e40, fff0); |
3027 | BASE(link, 4e50, fff8); | |
3028 | BASE(unlk, 4e58, fff8); | |
20dcee94 PB |
3029 | INSN(move_to_usp, 4e60, fff8, USP); |
3030 | INSN(move_from_usp, 4e68, fff8, USP); | |
f076803b LV |
3031 | BASE(nop, 4e71, ffff); |
3032 | BASE(stop, 4e72, ffff); | |
3033 | BASE(rte, 4e73, ffff); | |
3034 | BASE(rts, 4e75, ffff); | |
0402f767 | 3035 | INSN(movec, 4e7b, ffff, CF_ISA_A); |
f076803b | 3036 | BASE(jump, 4e80, ffc0); |
0402f767 PB |
3037 | INSN(jump, 4ec0, ffc0, CF_ISA_A); |
3038 | INSN(addsubq, 5180, f1c0, CF_ISA_A); | |
f076803b LV |
3039 | INSN(jump, 4ec0, ffc0, M68000); |
3040 | INSN(addsubq, 5000, f080, M68000); | |
3041 | INSN(addsubq, 5080, f0c0, M68000); | |
0402f767 PB |
3042 | INSN(scc, 50c0, f0f8, CF_ISA_A); |
3043 | INSN(addsubq, 5080, f1c0, CF_ISA_A); | |
3044 | INSN(tpf, 51f8, fff8, CF_ISA_A); | |
d315c888 PB |
3045 | |
3046 | /* Branch instructions. */ | |
f076803b | 3047 | BASE(branch, 6000, f000); |
d315c888 | 3048 | /* Disable long branch instructions, then add back the ones we want. */ |
f076803b | 3049 | BASE(undef, 60ff, f0ff); /* All long branches. */ |
d315c888 PB |
3050 | INSN(branch, 60ff, f0ff, CF_ISA_B); |
3051 | INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ | |
3052 | INSN(branch, 60ff, ffff, BRAL); | |
f076803b | 3053 | INSN(branch, 60ff, f0ff, BCCL); |
d315c888 | 3054 | |
f076803b | 3055 | BASE(moveq, 7000, f100); |
0402f767 | 3056 | INSN(mvzs, 7100, f100, CF_ISA_B); |
f076803b LV |
3057 | BASE(or, 8000, f000); |
3058 | BASE(divw, 80c0, f0c0); | |
3059 | BASE(addsub, 9000, f000); | |
0402f767 PB |
3060 | INSN(subx, 9180, f1f8, CF_ISA_A); |
3061 | INSN(suba, 91c0, f1c0, CF_ISA_A); | |
acf930aa | 3062 | |
f076803b | 3063 | BASE(undef_mac, a000, f000); |
acf930aa PB |
3064 | INSN(mac, a000, f100, CF_EMAC); |
3065 | INSN(from_mac, a180, f9b0, CF_EMAC); | |
3066 | INSN(move_mac, a110, f9fc, CF_EMAC); | |
3067 | INSN(from_macsr,a980, f9f0, CF_EMAC); | |
3068 | INSN(from_mask, ad80, fff0, CF_EMAC); | |
3069 | INSN(from_mext, ab80, fbf0, CF_EMAC); | |
3070 | INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); | |
3071 | INSN(to_mac, a100, f9c0, CF_EMAC); | |
3072 | INSN(to_macsr, a900, ffc0, CF_EMAC); | |
3073 | INSN(to_mext, ab00, fbc0, CF_EMAC); | |
3074 | INSN(to_mask, ad00, ffc0, CF_EMAC); | |
3075 | ||
0402f767 PB |
3076 | INSN(mov3q, a140, f1c0, CF_ISA_B); |
3077 | INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ | |
3078 | INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ | |
3079 | INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ | |
3080 | INSN(cmp, b080, f1c0, CF_ISA_A); | |
3081 | INSN(cmpa, b1c0, f1c0, CF_ISA_A); | |
f076803b LV |
3082 | INSN(cmp, b000, f100, M68000); |
3083 | INSN(eor, b100, f100, M68000); | |
3084 | INSN(cmpa, b0c0, f0c0, M68000); | |
0402f767 | 3085 | INSN(eor, b180, f1c0, CF_ISA_A); |
f076803b LV |
3086 | BASE(and, c000, f000); |
3087 | BASE(mulw, c0c0, f0c0); | |
3088 | BASE(addsub, d000, f000); | |
0402f767 PB |
3089 | INSN(addx, d180, f1f8, CF_ISA_A); |
3090 | INSN(adda, d1c0, f1c0, CF_ISA_A); | |
f076803b | 3091 | INSN(adda, d0c0, f0c0, M68000); |
0402f767 PB |
3092 | INSN(shift_im, e080, f0f0, CF_ISA_A); |
3093 | INSN(shift_reg, e0a0, f0f0, CF_ISA_A); | |
3094 | INSN(undef_fpu, f000, f000, CF_ISA_A); | |
e6e5906b PB |
3095 | INSN(fpu, f200, ffc0, CF_FPU); |
3096 | INSN(fbcc, f280, ffc0, CF_FPU); | |
0633879f PB |
3097 | INSN(frestore, f340, ffc0, CF_FPU); |
3098 | INSN(fsave, f340, ffc0, CF_FPU); | |
0402f767 PB |
3099 | INSN(intouch, f340, ffc0, CF_ISA_A); |
3100 | INSN(cpushl, f428, ff38, CF_ISA_A); | |
3101 | INSN(wddata, fb00, ff00, CF_ISA_A); | |
3102 | INSN(wdebug, fbc0, ffc0, CF_ISA_A); | |
e6e5906b PB |
3103 | #undef INSN |
3104 | } | |
3105 | ||
3106 | /* ??? Some of this implementation is not exception safe. We should always | |
3107 | write back the result to memory before setting the condition codes. */ | |
2b3e3cfe | 3108 | static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) |
e6e5906b PB |
3109 | { |
3110 | uint16_t insn; | |
3111 | ||
28b68cd7 | 3112 | insn = read_im16(env, s); |
e6e5906b | 3113 | |
d4d79bb1 | 3114 | opcode_table[insn](env, s, insn); |
e6e5906b PB |
3115 | } |
3116 | ||
e6e5906b | 3117 | /* generate intermediate code for basic block 'tb'. */ |
4e5e1215 | 3118 | void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 3119 | { |
4e5e1215 | 3120 | M68kCPU *cpu = m68k_env_get_cpu(env); |
ed2803da | 3121 | CPUState *cs = CPU(cpu); |
e6e5906b | 3122 | DisasContext dc1, *dc = &dc1; |
e6e5906b PB |
3123 | target_ulong pc_start; |
3124 | int pc_offset; | |
2e70f6ef PB |
3125 | int num_insns; |
3126 | int max_insns; | |
e6e5906b PB |
3127 | |
3128 | /* generate intermediate code */ | |
3129 | pc_start = tb->pc; | |
3b46e624 | 3130 | |
e6e5906b PB |
3131 | dc->tb = tb; |
3132 | ||
e6dbd3b3 | 3133 | dc->env = env; |
e6e5906b PB |
3134 | dc->is_jmp = DISAS_NEXT; |
3135 | dc->pc = pc_start; | |
3136 | dc->cc_op = CC_OP_DYNAMIC; | |
620c6cf6 | 3137 | dc->cc_op_synced = 1; |
ed2803da | 3138 | dc->singlestep_enabled = cs->singlestep_enabled; |
e6e5906b | 3139 | dc->fpcr = env->fpcr; |
0633879f | 3140 | dc->user = (env->sr & SR_S) == 0; |
a7812ae4 | 3141 | dc->done_mac = 0; |
2e70f6ef PB |
3142 | num_insns = 0; |
3143 | max_insns = tb->cflags & CF_COUNT_MASK; | |
190ce7fb | 3144 | if (max_insns == 0) { |
2e70f6ef | 3145 | max_insns = CF_COUNT_MASK; |
190ce7fb RH |
3146 | } |
3147 | if (max_insns > TCG_MAX_INSNS) { | |
3148 | max_insns = TCG_MAX_INSNS; | |
3149 | } | |
2e70f6ef | 3150 | |
cd42d5b2 | 3151 | gen_tb_start(tb); |
e6e5906b | 3152 | do { |
e6e5906b PB |
3153 | pc_offset = dc->pc - pc_start; |
3154 | gen_throws_exception = NULL; | |
20a8856e | 3155 | tcg_gen_insn_start(dc->pc, dc->cc_op); |
959082fc | 3156 | num_insns++; |
667b8e29 | 3157 | |
b933066a RH |
3158 | if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { |
3159 | gen_exception(dc, dc->pc, EXCP_DEBUG); | |
3160 | dc->is_jmp = DISAS_JUMP; | |
522a0d4e RH |
3161 | /* The address covered by the breakpoint must be included in |
3162 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
3163 | properly cleared -- thus we increment the PC here so that | |
3164 | the logic setting tb->size below does the right thing. */ | |
3165 | dc->pc += 2; | |
b933066a RH |
3166 | break; |
3167 | } | |
3168 | ||
959082fc | 3169 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
2e70f6ef | 3170 | gen_io_start(); |
667b8e29 RH |
3171 | } |
3172 | ||
510ff0b7 | 3173 | dc->insn_pc = dc->pc; |
e6e5906b | 3174 | disas_m68k_insn(env, dc); |
fe700adb | 3175 | } while (!dc->is_jmp && !tcg_op_buf_full() && |
ed2803da | 3176 | !cs->singlestep_enabled && |
1b530a6d | 3177 | !singlestep && |
2e70f6ef PB |
3178 | (pc_offset) < (TARGET_PAGE_SIZE - 32) && |
3179 | num_insns < max_insns); | |
e6e5906b | 3180 | |
2e70f6ef PB |
3181 | if (tb->cflags & CF_LAST_IO) |
3182 | gen_io_end(); | |
ed2803da | 3183 | if (unlikely(cs->singlestep_enabled)) { |
e6e5906b PB |
3184 | /* Make sure the pc is updated, and raise a debug exception. */ |
3185 | if (!dc->is_jmp) { | |
9fdb533f | 3186 | update_cc_op(dc); |
e1f3808e | 3187 | tcg_gen_movi_i32(QREG_PC, dc->pc); |
e6e5906b | 3188 | } |
31871141 | 3189 | gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); |
e6e5906b PB |
3190 | } else { |
3191 | switch(dc->is_jmp) { | |
3192 | case DISAS_NEXT: | |
9fdb533f | 3193 | update_cc_op(dc); |
e6e5906b PB |
3194 | gen_jmp_tb(dc, 0, dc->pc); |
3195 | break; | |
3196 | default: | |
3197 | case DISAS_JUMP: | |
3198 | case DISAS_UPDATE: | |
9fdb533f | 3199 | update_cc_op(dc); |
e6e5906b | 3200 | /* indicate that the hash table must be used to find the next TB */ |
57fec1fe | 3201 | tcg_gen_exit_tb(0); |
e6e5906b PB |
3202 | break; |
3203 | case DISAS_TB_JUMP: | |
3204 | /* nothing more to generate */ | |
3205 | break; | |
3206 | } | |
3207 | } | |
806f352d | 3208 | gen_tb_end(tb, num_insns); |
e6e5906b PB |
3209 | |
3210 | #ifdef DEBUG_DISAS | |
4910e6e4 RH |
3211 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
3212 | && qemu_log_in_addr_range(pc_start)) { | |
93fcfe39 AL |
3213 | qemu_log("----------------\n"); |
3214 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 3215 | log_target_disas(cs, pc_start, dc->pc - pc_start, 0); |
93fcfe39 | 3216 | qemu_log("\n"); |
e6e5906b PB |
3217 | } |
3218 | #endif | |
4e5e1215 RH |
3219 | tb->size = dc->pc - pc_start; |
3220 | tb->icount = num_insns; | |
e6e5906b PB |
3221 | } |
3222 | ||
878096ee AF |
3223 | void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
3224 | int flags) | |
e6e5906b | 3225 | { |
878096ee AF |
3226 | M68kCPU *cpu = M68K_CPU(cs); |
3227 | CPUM68KState *env = &cpu->env; | |
e6e5906b PB |
3228 | int i; |
3229 | uint16_t sr; | |
3230 | CPU_DoubleU u; | |
3231 | for (i = 0; i < 8; i++) | |
3232 | { | |
3233 | u.d = env->fregs[i]; | |
8e394cca RH |
3234 | cpu_fprintf(f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", |
3235 | i, env->dregs[i], i, env->aregs[i], | |
3236 | i, u.l.upper, u.l.lower, *(double *)&u.d); | |
e6e5906b PB |
3237 | } |
3238 | cpu_fprintf (f, "PC = %08x ", env->pc); | |
99c51448 | 3239 | sr = env->sr | cpu_m68k_get_ccr(env); |
8e394cca RH |
3240 | cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-', |
3241 | (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', | |
3242 | (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); | |
8fc7cc58 | 3243 | cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); |
e6e5906b PB |
3244 | } |
3245 | ||
bad729e2 RH |
3246 | void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, |
3247 | target_ulong *data) | |
d2856f1a | 3248 | { |
20a8856e | 3249 | int cc_op = data[1]; |
bad729e2 | 3250 | env->pc = data[0]; |
20a8856e LV |
3251 | if (cc_op != CC_OP_DYNAMIC) { |
3252 | env->cc_op = cc_op; | |
3253 | } | |
d2856f1a | 3254 | } |