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Commit | Line | Data |
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e6e5906b PB |
1 | /* |
2 | * m68k translation | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
e6e5906b | 20 | |
d8416665 | 21 | #include "qemu/osdep.h" |
e6e5906b | 22 | #include "cpu.h" |
76cad711 | 23 | #include "disas/disas.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
57fec1fe | 25 | #include "tcg-op.h" |
1de7afc9 | 26 | #include "qemu/log.h" |
f08b6170 | 27 | #include "exec/cpu_ldst.h" |
e1f3808e | 28 | |
2ef6175a RH |
29 | #include "exec/helper-proto.h" |
30 | #include "exec/helper-gen.h" | |
e6e5906b | 31 | |
a7e30d84 | 32 | #include "trace-tcg.h" |
508127e2 | 33 | #include "exec/log.h" |
a7e30d84 LV |
34 | |
35 | ||
0633879f PB |
36 | //#define DEBUG_DISPATCH 1 |
37 | ||
815a6742 | 38 | /* Fake floating point. */ |
815a6742 | 39 | #define tcg_gen_mov_f64 tcg_gen_mov_i64 |
815a6742 | 40 | #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 |
815a6742 | 41 | #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 |
815a6742 | 42 | |
e1f3808e | 43 | #define DEFO32(name, offset) static TCGv QREG_##name; |
a7812ae4 PB |
44 | #define DEFO64(name, offset) static TCGv_i64 QREG_##name; |
45 | #define DEFF64(name, offset) static TCGv_i64 QREG_##name; | |
e1f3808e PB |
46 | #include "qregs.def" |
47 | #undef DEFO32 | |
48 | #undef DEFO64 | |
49 | #undef DEFF64 | |
50 | ||
259186a7 | 51 | static TCGv_i32 cpu_halted; |
27103424 | 52 | static TCGv_i32 cpu_exception_index; |
259186a7 | 53 | |
1bcea73e | 54 | static TCGv_env cpu_env; |
e1f3808e PB |
55 | |
56 | static char cpu_reg_names[3*8*3 + 5*4]; | |
57 | static TCGv cpu_dregs[8]; | |
58 | static TCGv cpu_aregs[8]; | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fregs[8]; |
60 | static TCGv_i64 cpu_macc[4]; | |
e1f3808e | 61 | |
bcc098b0 LV |
62 | #define REG(insn, pos) (((insn) >> (pos)) & 7) |
63 | #define DREG(insn, pos) cpu_dregs[REG(insn, pos)] | |
64 | #define AREG(insn, pos) cpu_aregs[REG(insn, pos)] | |
65 | #define FREG(insn, pos) cpu_fregs[REG(insn, pos)] | |
e1f3808e PB |
66 | #define MACREG(acc) cpu_macc[acc] |
67 | #define QREG_SP cpu_aregs[7] | |
68 | ||
69 | static TCGv NULL_QREG; | |
a7812ae4 | 70 | #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) |
e1f3808e PB |
71 | /* Used to distinguish stores from bad addressing modes. */ |
72 | static TCGv store_dummy; | |
73 | ||
022c62cb | 74 | #include "exec/gen-icount.h" |
2e70f6ef | 75 | |
e1f3808e PB |
76 | void m68k_tcg_init(void) |
77 | { | |
78 | char *p; | |
79 | int i; | |
80 | ||
e1ccc054 | 81 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7c255043 | 82 | tcg_ctx.tcg_env = cpu_env; |
e1ccc054 RH |
83 | |
84 | #define DEFO32(name, offset) \ | |
85 | QREG_##name = tcg_global_mem_new_i32(cpu_env, \ | |
86 | offsetof(CPUM68KState, offset), #name); | |
87 | #define DEFO64(name, offset) \ | |
88 | QREG_##name = tcg_global_mem_new_i64(cpu_env, \ | |
89 | offsetof(CPUM68KState, offset), #name); | |
90 | #define DEFF64(name, offset) DEFO64(name, offset) | |
e1f3808e PB |
91 | #include "qregs.def" |
92 | #undef DEFO32 | |
93 | #undef DEFO64 | |
94 | #undef DEFF64 | |
95 | ||
e1ccc054 | 96 | cpu_halted = tcg_global_mem_new_i32(cpu_env, |
259186a7 AF |
97 | -offsetof(M68kCPU, env) + |
98 | offsetof(CPUState, halted), "HALTED"); | |
e1ccc054 | 99 | cpu_exception_index = tcg_global_mem_new_i32(cpu_env, |
27103424 AF |
100 | -offsetof(M68kCPU, env) + |
101 | offsetof(CPUState, exception_index), | |
102 | "EXCEPTION"); | |
259186a7 | 103 | |
e1f3808e PB |
104 | p = cpu_reg_names; |
105 | for (i = 0; i < 8; i++) { | |
106 | sprintf(p, "D%d", i); | |
e1ccc054 | 107 | cpu_dregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
108 | offsetof(CPUM68KState, dregs[i]), p); |
109 | p += 3; | |
110 | sprintf(p, "A%d", i); | |
e1ccc054 | 111 | cpu_aregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
112 | offsetof(CPUM68KState, aregs[i]), p); |
113 | p += 3; | |
114 | sprintf(p, "F%d", i); | |
e1ccc054 | 115 | cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
116 | offsetof(CPUM68KState, fregs[i]), p); |
117 | p += 3; | |
118 | } | |
119 | for (i = 0; i < 4; i++) { | |
120 | sprintf(p, "ACC%d", i); | |
e1ccc054 | 121 | cpu_macc[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
122 | offsetof(CPUM68KState, macc[i]), p); |
123 | p += 5; | |
124 | } | |
125 | ||
e1ccc054 RH |
126 | NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL"); |
127 | store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL"); | |
e1f3808e PB |
128 | } |
129 | ||
e6e5906b PB |
130 | /* internal defines */ |
131 | typedef struct DisasContext { | |
e6dbd3b3 | 132 | CPUM68KState *env; |
510ff0b7 | 133 | target_ulong insn_pc; /* Start of the current instruction. */ |
e6e5906b PB |
134 | target_ulong pc; |
135 | int is_jmp; | |
9fdb533f | 136 | CCOp cc_op; /* Current CC operation */ |
620c6cf6 | 137 | int cc_op_synced; |
0633879f | 138 | int user; |
e6e5906b PB |
139 | uint32_t fpcr; |
140 | struct TranslationBlock *tb; | |
141 | int singlestep_enabled; | |
a7812ae4 PB |
142 | TCGv_i64 mactmp; |
143 | int done_mac; | |
e6e5906b PB |
144 | } DisasContext; |
145 | ||
146 | #define DISAS_JUMP_NEXT 4 | |
147 | ||
0633879f PB |
148 | #if defined(CONFIG_USER_ONLY) |
149 | #define IS_USER(s) 1 | |
150 | #else | |
151 | #define IS_USER(s) s->user | |
152 | #endif | |
153 | ||
e6e5906b PB |
154 | /* XXX: move that elsewhere */ |
155 | /* ??? Fix exceptions. */ | |
156 | static void *gen_throws_exception; | |
157 | #define gen_last_qop NULL | |
158 | ||
d4d79bb1 | 159 | typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); |
e6e5906b | 160 | |
0633879f | 161 | #ifdef DEBUG_DISPATCH |
d4d79bb1 BS |
162 | #define DISAS_INSN(name) \ |
163 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
164 | uint16_t insn); \ | |
165 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
166 | uint16_t insn) \ | |
167 | { \ | |
168 | qemu_log("Dispatch " #name "\n"); \ | |
a1ff1930 | 169 | real_disas_##name(env, s, insn); \ |
d4d79bb1 BS |
170 | } \ |
171 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
172 | uint16_t insn) | |
0633879f | 173 | #else |
d4d79bb1 BS |
174 | #define DISAS_INSN(name) \ |
175 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
176 | uint16_t insn) | |
0633879f | 177 | #endif |
e6e5906b | 178 | |
9fdb533f | 179 | static const uint8_t cc_op_live[CC_OP_NB] = { |
620c6cf6 RH |
180 | [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X, |
181 | [CC_OP_ADD] = CCF_X | CCF_N | CCF_V, | |
182 | [CC_OP_SUB] = CCF_X | CCF_N | CCF_V, | |
183 | [CC_OP_CMP] = CCF_X | CCF_N | CCF_V, | |
184 | [CC_OP_LOGIC] = CCF_X | CCF_N | |
9fdb533f LV |
185 | }; |
186 | ||
187 | static void set_cc_op(DisasContext *s, CCOp op) | |
188 | { | |
620c6cf6 | 189 | CCOp old_op = s->cc_op; |
9fdb533f LV |
190 | int dead; |
191 | ||
620c6cf6 | 192 | if (old_op == op) { |
9fdb533f LV |
193 | return; |
194 | } | |
620c6cf6 RH |
195 | s->cc_op = op; |
196 | s->cc_op_synced = 0; | |
9fdb533f | 197 | |
620c6cf6 RH |
198 | /* Discard CC computation that will no longer be used. |
199 | Note that X and N are never dead. */ | |
200 | dead = cc_op_live[old_op] & ~cc_op_live[op]; | |
201 | if (dead & CCF_C) { | |
202 | tcg_gen_discard_i32(QREG_CC_C); | |
9fdb533f | 203 | } |
620c6cf6 RH |
204 | if (dead & CCF_Z) { |
205 | tcg_gen_discard_i32(QREG_CC_Z); | |
9fdb533f | 206 | } |
620c6cf6 RH |
207 | if (dead & CCF_V) { |
208 | tcg_gen_discard_i32(QREG_CC_V); | |
9fdb533f | 209 | } |
9fdb533f LV |
210 | } |
211 | ||
212 | /* Update the CPU env CC_OP state. */ | |
620c6cf6 | 213 | static void update_cc_op(DisasContext *s) |
9fdb533f | 214 | { |
620c6cf6 RH |
215 | if (!s->cc_op_synced) { |
216 | s->cc_op_synced = 1; | |
9fdb533f LV |
217 | tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); |
218 | } | |
219 | } | |
220 | ||
e6e5906b PB |
221 | /* Generate a load from the specified address. Narrow values are |
222 | sign extended to full register width. */ | |
e1f3808e | 223 | static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) |
e6e5906b | 224 | { |
e1f3808e PB |
225 | TCGv tmp; |
226 | int index = IS_USER(s); | |
a7812ae4 | 227 | tmp = tcg_temp_new_i32(); |
e6e5906b PB |
228 | switch(opsize) { |
229 | case OS_BYTE: | |
e6e5906b | 230 | if (sign) |
e1f3808e | 231 | tcg_gen_qemu_ld8s(tmp, addr, index); |
e6e5906b | 232 | else |
e1f3808e | 233 | tcg_gen_qemu_ld8u(tmp, addr, index); |
e6e5906b PB |
234 | break; |
235 | case OS_WORD: | |
e6e5906b | 236 | if (sign) |
e1f3808e | 237 | tcg_gen_qemu_ld16s(tmp, addr, index); |
e6e5906b | 238 | else |
e1f3808e | 239 | tcg_gen_qemu_ld16u(tmp, addr, index); |
e6e5906b PB |
240 | break; |
241 | case OS_LONG: | |
e6e5906b | 242 | case OS_SINGLE: |
a7812ae4 | 243 | tcg_gen_qemu_ld32u(tmp, addr, index); |
e6e5906b PB |
244 | break; |
245 | default: | |
7372c2b9 | 246 | g_assert_not_reached(); |
e6e5906b PB |
247 | } |
248 | gen_throws_exception = gen_last_qop; | |
249 | return tmp; | |
250 | } | |
251 | ||
a7812ae4 PB |
252 | static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) |
253 | { | |
254 | TCGv_i64 tmp; | |
255 | int index = IS_USER(s); | |
a7812ae4 PB |
256 | tmp = tcg_temp_new_i64(); |
257 | tcg_gen_qemu_ldf64(tmp, addr, index); | |
258 | gen_throws_exception = gen_last_qop; | |
259 | return tmp; | |
260 | } | |
261 | ||
e6e5906b | 262 | /* Generate a store. */ |
e1f3808e | 263 | static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) |
e6e5906b | 264 | { |
e1f3808e | 265 | int index = IS_USER(s); |
e6e5906b PB |
266 | switch(opsize) { |
267 | case OS_BYTE: | |
e1f3808e | 268 | tcg_gen_qemu_st8(val, addr, index); |
e6e5906b PB |
269 | break; |
270 | case OS_WORD: | |
e1f3808e | 271 | tcg_gen_qemu_st16(val, addr, index); |
e6e5906b PB |
272 | break; |
273 | case OS_LONG: | |
e6e5906b | 274 | case OS_SINGLE: |
a7812ae4 | 275 | tcg_gen_qemu_st32(val, addr, index); |
e6e5906b PB |
276 | break; |
277 | default: | |
7372c2b9 | 278 | g_assert_not_reached(); |
e6e5906b PB |
279 | } |
280 | gen_throws_exception = gen_last_qop; | |
281 | } | |
282 | ||
a7812ae4 PB |
283 | static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) |
284 | { | |
285 | int index = IS_USER(s); | |
a7812ae4 PB |
286 | tcg_gen_qemu_stf64(val, addr, index); |
287 | gen_throws_exception = gen_last_qop; | |
288 | } | |
289 | ||
e1f3808e PB |
290 | typedef enum { |
291 | EA_STORE, | |
292 | EA_LOADU, | |
293 | EA_LOADS | |
294 | } ea_what; | |
295 | ||
e6e5906b PB |
296 | /* Generate an unsigned load if VAL is 0 a signed load if val is -1, |
297 | otherwise generate a store. */ | |
e1f3808e PB |
298 | static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, |
299 | ea_what what) | |
e6e5906b | 300 | { |
e1f3808e | 301 | if (what == EA_STORE) { |
0633879f | 302 | gen_store(s, opsize, addr, val); |
e1f3808e | 303 | return store_dummy; |
e6e5906b | 304 | } else { |
e1f3808e | 305 | return gen_load(s, opsize, addr, what == EA_LOADS); |
e6e5906b PB |
306 | } |
307 | } | |
308 | ||
28b68cd7 LV |
309 | /* Read a 16-bit immediate constant */ |
310 | static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) | |
311 | { | |
312 | uint16_t im; | |
313 | im = cpu_lduw_code(env, s->pc); | |
314 | s->pc += 2; | |
315 | return im; | |
316 | } | |
317 | ||
318 | /* Read an 8-bit immediate constant */ | |
319 | static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s) | |
320 | { | |
321 | return read_im16(env, s); | |
322 | } | |
323 | ||
e6dbd3b3 | 324 | /* Read a 32-bit immediate constant. */ |
d4d79bb1 | 325 | static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) |
e6dbd3b3 PB |
326 | { |
327 | uint32_t im; | |
28b68cd7 LV |
328 | im = read_im16(env, s) << 16; |
329 | im |= 0xffff & read_im16(env, s); | |
e6dbd3b3 PB |
330 | return im; |
331 | } | |
332 | ||
333 | /* Calculate and address index. */ | |
e1f3808e | 334 | static TCGv gen_addr_index(uint16_t ext, TCGv tmp) |
e6dbd3b3 | 335 | { |
e1f3808e | 336 | TCGv add; |
e6dbd3b3 PB |
337 | int scale; |
338 | ||
339 | add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); | |
340 | if ((ext & 0x800) == 0) { | |
e1f3808e | 341 | tcg_gen_ext16s_i32(tmp, add); |
e6dbd3b3 PB |
342 | add = tmp; |
343 | } | |
344 | scale = (ext >> 9) & 3; | |
345 | if (scale != 0) { | |
e1f3808e | 346 | tcg_gen_shli_i32(tmp, add, scale); |
e6dbd3b3 PB |
347 | add = tmp; |
348 | } | |
349 | return add; | |
350 | } | |
351 | ||
e1f3808e PB |
352 | /* Handle a base + index + displacement effective addresss. |
353 | A NULL_QREG base means pc-relative. */ | |
a4356126 | 354 | static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) |
e6e5906b | 355 | { |
e6e5906b PB |
356 | uint32_t offset; |
357 | uint16_t ext; | |
e1f3808e PB |
358 | TCGv add; |
359 | TCGv tmp; | |
e6dbd3b3 | 360 | uint32_t bd, od; |
e6e5906b PB |
361 | |
362 | offset = s->pc; | |
28b68cd7 | 363 | ext = read_im16(env, s); |
e6dbd3b3 PB |
364 | |
365 | if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) | |
e1f3808e | 366 | return NULL_QREG; |
e6dbd3b3 | 367 | |
d8633620 LV |
368 | if (m68k_feature(s->env, M68K_FEATURE_M68000) && |
369 | !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) { | |
370 | ext &= ~(3 << 9); | |
371 | } | |
372 | ||
e6dbd3b3 PB |
373 | if (ext & 0x100) { |
374 | /* full extension word format */ | |
375 | if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) | |
e1f3808e | 376 | return NULL_QREG; |
e6dbd3b3 PB |
377 | |
378 | if ((ext & 0x30) > 0x10) { | |
379 | /* base displacement */ | |
380 | if ((ext & 0x30) == 0x20) { | |
28b68cd7 | 381 | bd = (int16_t)read_im16(env, s); |
e6dbd3b3 | 382 | } else { |
d4d79bb1 | 383 | bd = read_im32(env, s); |
e6dbd3b3 PB |
384 | } |
385 | } else { | |
386 | bd = 0; | |
387 | } | |
a7812ae4 | 388 | tmp = tcg_temp_new(); |
e6dbd3b3 PB |
389 | if ((ext & 0x44) == 0) { |
390 | /* pre-index */ | |
391 | add = gen_addr_index(ext, tmp); | |
392 | } else { | |
e1f3808e | 393 | add = NULL_QREG; |
e6dbd3b3 PB |
394 | } |
395 | if ((ext & 0x80) == 0) { | |
396 | /* base not suppressed */ | |
e1f3808e | 397 | if (IS_NULL_QREG(base)) { |
351326a6 | 398 | base = tcg_const_i32(offset + bd); |
e6dbd3b3 PB |
399 | bd = 0; |
400 | } | |
e1f3808e PB |
401 | if (!IS_NULL_QREG(add)) { |
402 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 PB |
403 | add = tmp; |
404 | } else { | |
405 | add = base; | |
406 | } | |
407 | } | |
e1f3808e | 408 | if (!IS_NULL_QREG(add)) { |
e6dbd3b3 | 409 | if (bd != 0) { |
e1f3808e | 410 | tcg_gen_addi_i32(tmp, add, bd); |
e6dbd3b3 PB |
411 | add = tmp; |
412 | } | |
413 | } else { | |
351326a6 | 414 | add = tcg_const_i32(bd); |
e6dbd3b3 PB |
415 | } |
416 | if ((ext & 3) != 0) { | |
417 | /* memory indirect */ | |
418 | base = gen_load(s, OS_LONG, add, 0); | |
419 | if ((ext & 0x44) == 4) { | |
420 | add = gen_addr_index(ext, tmp); | |
e1f3808e | 421 | tcg_gen_add_i32(tmp, add, base); |
e6dbd3b3 PB |
422 | add = tmp; |
423 | } else { | |
424 | add = base; | |
425 | } | |
426 | if ((ext & 3) > 1) { | |
427 | /* outer displacement */ | |
428 | if ((ext & 3) == 2) { | |
28b68cd7 | 429 | od = (int16_t)read_im16(env, s); |
e6dbd3b3 | 430 | } else { |
d4d79bb1 | 431 | od = read_im32(env, s); |
e6dbd3b3 PB |
432 | } |
433 | } else { | |
434 | od = 0; | |
435 | } | |
436 | if (od != 0) { | |
e1f3808e | 437 | tcg_gen_addi_i32(tmp, add, od); |
e6dbd3b3 PB |
438 | add = tmp; |
439 | } | |
440 | } | |
e6e5906b | 441 | } else { |
e6dbd3b3 | 442 | /* brief extension word format */ |
a7812ae4 | 443 | tmp = tcg_temp_new(); |
e6dbd3b3 | 444 | add = gen_addr_index(ext, tmp); |
e1f3808e PB |
445 | if (!IS_NULL_QREG(base)) { |
446 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 | 447 | if ((int8_t)ext) |
e1f3808e | 448 | tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); |
e6dbd3b3 | 449 | } else { |
e1f3808e | 450 | tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); |
e6dbd3b3 PB |
451 | } |
452 | add = tmp; | |
e6e5906b | 453 | } |
e6dbd3b3 | 454 | return add; |
e6e5906b PB |
455 | } |
456 | ||
e6e5906b | 457 | /* Evaluate all the CC flags. */ |
9fdb533f | 458 | |
620c6cf6 | 459 | static void gen_flush_flags(DisasContext *s) |
e6e5906b | 460 | { |
36f0399d | 461 | TCGv t0, t1; |
620c6cf6 RH |
462 | |
463 | switch (s->cc_op) { | |
464 | case CC_OP_FLAGS: | |
e6e5906b | 465 | return; |
36f0399d RH |
466 | |
467 | case CC_OP_ADD: | |
468 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
469 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
470 | /* Compute signed overflow for addition. */ | |
471 | t0 = tcg_temp_new(); | |
472 | t1 = tcg_temp_new(); | |
473 | tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V); | |
474 | tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V); | |
475 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); | |
476 | tcg_temp_free(t0); | |
477 | tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V); | |
478 | tcg_temp_free(t1); | |
479 | break; | |
480 | ||
481 | case CC_OP_SUB: | |
482 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
483 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
484 | /* Compute signed overflow for subtraction. */ | |
485 | t0 = tcg_temp_new(); | |
486 | t1 = tcg_temp_new(); | |
487 | tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V); | |
488 | tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V); | |
489 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); | |
490 | tcg_temp_free(t0); | |
491 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1); | |
492 | tcg_temp_free(t1); | |
493 | break; | |
494 | ||
495 | case CC_OP_CMP: | |
496 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V); | |
497 | tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V); | |
498 | /* Compute signed overflow for subtraction. */ | |
499 | t0 = tcg_temp_new(); | |
500 | tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N); | |
501 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N); | |
502 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0); | |
503 | tcg_temp_free(t0); | |
504 | tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z); | |
505 | break; | |
506 | ||
507 | case CC_OP_LOGIC: | |
508 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
509 | tcg_gen_movi_i32(QREG_CC_C, 0); | |
510 | tcg_gen_movi_i32(QREG_CC_V, 0); | |
511 | break; | |
512 | ||
620c6cf6 RH |
513 | case CC_OP_DYNAMIC: |
514 | gen_helper_flush_flags(cpu_env, QREG_CC_OP); | |
515 | break; | |
36f0399d | 516 | |
620c6cf6 | 517 | default: |
36f0399d RH |
518 | t0 = tcg_const_i32(s->cc_op); |
519 | gen_helper_flush_flags(cpu_env, t0); | |
520 | tcg_temp_free(t0); | |
620c6cf6 RH |
521 | break; |
522 | } | |
523 | ||
524 | /* Note that flush_flags also assigned to env->cc_op. */ | |
525 | s->cc_op = CC_OP_FLAGS; | |
526 | s->cc_op_synced = 1; | |
527 | } | |
528 | ||
529 | /* Sign or zero extend a value. */ | |
530 | ||
531 | static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign) | |
532 | { | |
533 | switch (opsize) { | |
534 | case OS_BYTE: | |
535 | if (sign) { | |
536 | tcg_gen_ext8s_i32(res, val); | |
537 | } else { | |
538 | tcg_gen_ext8u_i32(res, val); | |
539 | } | |
540 | break; | |
541 | case OS_WORD: | |
542 | if (sign) { | |
543 | tcg_gen_ext16s_i32(res, val); | |
544 | } else { | |
545 | tcg_gen_ext16u_i32(res, val); | |
546 | } | |
547 | break; | |
548 | case OS_LONG: | |
549 | tcg_gen_mov_i32(res, val); | |
550 | break; | |
551 | default: | |
552 | g_assert_not_reached(); | |
9fdb533f | 553 | } |
e6e5906b PB |
554 | } |
555 | ||
620c6cf6 RH |
556 | static TCGv gen_extend(TCGv val, int opsize, int sign) |
557 | { | |
558 | TCGv tmp; | |
559 | ||
560 | if (opsize == OS_LONG) { | |
561 | tmp = val; | |
562 | } else { | |
563 | tmp = tcg_temp_new(); | |
564 | gen_ext(tmp, val, opsize, sign); | |
565 | } | |
566 | ||
567 | return tmp; | |
568 | } | |
5dbb6784 LV |
569 | |
570 | static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) | |
e1f3808e | 571 | { |
620c6cf6 RH |
572 | gen_ext(QREG_CC_N, val, opsize, 1); |
573 | set_cc_op(s, CC_OP_LOGIC); | |
e1f3808e PB |
574 | } |
575 | ||
576 | static void gen_update_cc_add(TCGv dest, TCGv src) | |
577 | { | |
620c6cf6 RH |
578 | tcg_gen_mov_i32(QREG_CC_N, dest); |
579 | tcg_gen_mov_i32(QREG_CC_V, src); | |
e1f3808e PB |
580 | } |
581 | ||
e6e5906b PB |
582 | static inline int opsize_bytes(int opsize) |
583 | { | |
584 | switch (opsize) { | |
585 | case OS_BYTE: return 1; | |
586 | case OS_WORD: return 2; | |
587 | case OS_LONG: return 4; | |
588 | case OS_SINGLE: return 4; | |
589 | case OS_DOUBLE: return 8; | |
7ef25cdd LV |
590 | case OS_EXTENDED: return 12; |
591 | case OS_PACKED: return 12; | |
592 | default: | |
593 | g_assert_not_reached(); | |
594 | } | |
595 | } | |
596 | ||
597 | static inline int insn_opsize(int insn) | |
598 | { | |
599 | switch ((insn >> 6) & 3) { | |
600 | case 0: return OS_BYTE; | |
601 | case 1: return OS_WORD; | |
602 | case 2: return OS_LONG; | |
e6e5906b | 603 | default: |
7372c2b9 | 604 | g_assert_not_reached(); |
e6e5906b PB |
605 | } |
606 | } | |
607 | ||
608 | /* Assign value to a register. If the width is less than the register width | |
609 | only the low part of the register is set. */ | |
e1f3808e | 610 | static void gen_partset_reg(int opsize, TCGv reg, TCGv val) |
e6e5906b | 611 | { |
e1f3808e | 612 | TCGv tmp; |
e6e5906b PB |
613 | switch (opsize) { |
614 | case OS_BYTE: | |
e1f3808e | 615 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
a7812ae4 | 616 | tmp = tcg_temp_new(); |
e1f3808e PB |
617 | tcg_gen_ext8u_i32(tmp, val); |
618 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
619 | break; |
620 | case OS_WORD: | |
e1f3808e | 621 | tcg_gen_andi_i32(reg, reg, 0xffff0000); |
a7812ae4 | 622 | tmp = tcg_temp_new(); |
e1f3808e PB |
623 | tcg_gen_ext16u_i32(tmp, val); |
624 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
625 | break; |
626 | case OS_LONG: | |
e6e5906b | 627 | case OS_SINGLE: |
a7812ae4 | 628 | tcg_gen_mov_i32(reg, val); |
e6e5906b PB |
629 | break; |
630 | default: | |
7372c2b9 | 631 | g_assert_not_reached(); |
e6e5906b PB |
632 | } |
633 | } | |
634 | ||
e6e5906b | 635 | /* Generate code for an "effective address". Does not adjust the base |
1addc7c5 | 636 | register for autoincrement addressing modes. */ |
d4d79bb1 BS |
637 | static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
638 | int opsize) | |
e6e5906b | 639 | { |
e1f3808e PB |
640 | TCGv reg; |
641 | TCGv tmp; | |
e6e5906b PB |
642 | uint16_t ext; |
643 | uint32_t offset; | |
644 | ||
e6e5906b PB |
645 | switch ((insn >> 3) & 7) { |
646 | case 0: /* Data register direct. */ | |
647 | case 1: /* Address register direct. */ | |
e1f3808e | 648 | return NULL_QREG; |
e6e5906b PB |
649 | case 2: /* Indirect register */ |
650 | case 3: /* Indirect postincrement. */ | |
e1f3808e | 651 | return AREG(insn, 0); |
e6e5906b | 652 | case 4: /* Indirect predecrememnt. */ |
e1f3808e | 653 | reg = AREG(insn, 0); |
a7812ae4 | 654 | tmp = tcg_temp_new(); |
e1f3808e | 655 | tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); |
e6e5906b PB |
656 | return tmp; |
657 | case 5: /* Indirect displacement. */ | |
e1f3808e | 658 | reg = AREG(insn, 0); |
a7812ae4 | 659 | tmp = tcg_temp_new(); |
28b68cd7 | 660 | ext = read_im16(env, s); |
e1f3808e | 661 | tcg_gen_addi_i32(tmp, reg, (int16_t)ext); |
e6e5906b PB |
662 | return tmp; |
663 | case 6: /* Indirect index + displacement. */ | |
e1f3808e | 664 | reg = AREG(insn, 0); |
a4356126 | 665 | return gen_lea_indexed(env, s, reg); |
e6e5906b | 666 | case 7: /* Other */ |
e1f3808e | 667 | switch (insn & 7) { |
e6e5906b | 668 | case 0: /* Absolute short. */ |
28b68cd7 | 669 | offset = (int16_t)read_im16(env, s); |
351326a6 | 670 | return tcg_const_i32(offset); |
e6e5906b | 671 | case 1: /* Absolute long. */ |
d4d79bb1 | 672 | offset = read_im32(env, s); |
351326a6 | 673 | return tcg_const_i32(offset); |
e6e5906b | 674 | case 2: /* pc displacement */ |
e6e5906b | 675 | offset = s->pc; |
28b68cd7 | 676 | offset += (int16_t)read_im16(env, s); |
351326a6 | 677 | return tcg_const_i32(offset); |
e6e5906b | 678 | case 3: /* pc index+displacement. */ |
a4356126 | 679 | return gen_lea_indexed(env, s, NULL_QREG); |
e6e5906b PB |
680 | case 4: /* Immediate. */ |
681 | default: | |
e1f3808e | 682 | return NULL_QREG; |
e6e5906b PB |
683 | } |
684 | } | |
685 | /* Should never happen. */ | |
e1f3808e | 686 | return NULL_QREG; |
e6e5906b PB |
687 | } |
688 | ||
689 | /* Helper function for gen_ea. Reuse the computed address between the | |
690 | for read/write operands. */ | |
d4d79bb1 BS |
691 | static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s, |
692 | uint16_t insn, int opsize, TCGv val, | |
693 | TCGv *addrp, ea_what what) | |
e6e5906b | 694 | { |
e1f3808e | 695 | TCGv tmp; |
e6e5906b | 696 | |
e1f3808e | 697 | if (addrp && what == EA_STORE) { |
e6e5906b PB |
698 | tmp = *addrp; |
699 | } else { | |
d4d79bb1 | 700 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
701 | if (IS_NULL_QREG(tmp)) |
702 | return tmp; | |
e6e5906b PB |
703 | if (addrp) |
704 | *addrp = tmp; | |
705 | } | |
e1f3808e | 706 | return gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
707 | } |
708 | ||
f38f7a84 | 709 | /* Generate code to load/store a value from/into an EA. If VAL > 0 this is |
e6e5906b PB |
710 | a write otherwise it is a read (0 == sign extend, -1 == zero extend). |
711 | ADDRP is non-null for readwrite operands. */ | |
d4d79bb1 BS |
712 | static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
713 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
e6e5906b | 714 | { |
e1f3808e PB |
715 | TCGv reg; |
716 | TCGv result; | |
e6e5906b PB |
717 | uint32_t offset; |
718 | ||
e6e5906b PB |
719 | switch ((insn >> 3) & 7) { |
720 | case 0: /* Data register direct. */ | |
e1f3808e PB |
721 | reg = DREG(insn, 0); |
722 | if (what == EA_STORE) { | |
e6e5906b | 723 | gen_partset_reg(opsize, reg, val); |
e1f3808e | 724 | return store_dummy; |
e6e5906b | 725 | } else { |
e1f3808e | 726 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
727 | } |
728 | case 1: /* Address register direct. */ | |
e1f3808e PB |
729 | reg = AREG(insn, 0); |
730 | if (what == EA_STORE) { | |
731 | tcg_gen_mov_i32(reg, val); | |
732 | return store_dummy; | |
e6e5906b | 733 | } else { |
e1f3808e | 734 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
735 | } |
736 | case 2: /* Indirect register */ | |
e1f3808e PB |
737 | reg = AREG(insn, 0); |
738 | return gen_ldst(s, opsize, reg, val, what); | |
e6e5906b | 739 | case 3: /* Indirect postincrement. */ |
e1f3808e PB |
740 | reg = AREG(insn, 0); |
741 | result = gen_ldst(s, opsize, reg, val, what); | |
e6e5906b PB |
742 | /* ??? This is not exception safe. The instruction may still |
743 | fault after this point. */ | |
e1f3808e PB |
744 | if (what == EA_STORE || !addrp) |
745 | tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize)); | |
e6e5906b PB |
746 | return result; |
747 | case 4: /* Indirect predecrememnt. */ | |
748 | { | |
e1f3808e PB |
749 | TCGv tmp; |
750 | if (addrp && what == EA_STORE) { | |
e6e5906b PB |
751 | tmp = *addrp; |
752 | } else { | |
d4d79bb1 | 753 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
754 | if (IS_NULL_QREG(tmp)) |
755 | return tmp; | |
e6e5906b PB |
756 | if (addrp) |
757 | *addrp = tmp; | |
758 | } | |
e1f3808e | 759 | result = gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
760 | /* ??? This is not exception safe. The instruction may still |
761 | fault after this point. */ | |
e1f3808e PB |
762 | if (what == EA_STORE || !addrp) { |
763 | reg = AREG(insn, 0); | |
764 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
765 | } |
766 | } | |
767 | return result; | |
768 | case 5: /* Indirect displacement. */ | |
769 | case 6: /* Indirect index + displacement. */ | |
d4d79bb1 | 770 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b | 771 | case 7: /* Other */ |
e1f3808e | 772 | switch (insn & 7) { |
e6e5906b PB |
773 | case 0: /* Absolute short. */ |
774 | case 1: /* Absolute long. */ | |
775 | case 2: /* pc displacement */ | |
776 | case 3: /* pc index+displacement. */ | |
d4d79bb1 | 777 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b PB |
778 | case 4: /* Immediate. */ |
779 | /* Sign extend values for consistency. */ | |
780 | switch (opsize) { | |
781 | case OS_BYTE: | |
31871141 | 782 | if (what == EA_LOADS) { |
28b68cd7 | 783 | offset = (int8_t)read_im8(env, s); |
31871141 | 784 | } else { |
28b68cd7 | 785 | offset = read_im8(env, s); |
31871141 | 786 | } |
e6e5906b PB |
787 | break; |
788 | case OS_WORD: | |
31871141 | 789 | if (what == EA_LOADS) { |
28b68cd7 | 790 | offset = (int16_t)read_im16(env, s); |
31871141 | 791 | } else { |
28b68cd7 | 792 | offset = read_im16(env, s); |
31871141 | 793 | } |
e6e5906b PB |
794 | break; |
795 | case OS_LONG: | |
d4d79bb1 | 796 | offset = read_im32(env, s); |
e6e5906b PB |
797 | break; |
798 | default: | |
7372c2b9 | 799 | g_assert_not_reached(); |
e6e5906b | 800 | } |
e1f3808e | 801 | return tcg_const_i32(offset); |
e6e5906b | 802 | default: |
e1f3808e | 803 | return NULL_QREG; |
e6e5906b PB |
804 | } |
805 | } | |
806 | /* Should never happen. */ | |
e1f3808e | 807 | return NULL_QREG; |
e6e5906b PB |
808 | } |
809 | ||
6a432295 RH |
810 | typedef struct { |
811 | TCGCond tcond; | |
812 | bool g1; | |
813 | bool g2; | |
814 | TCGv v1; | |
815 | TCGv v2; | |
816 | } DisasCompare; | |
817 | ||
818 | static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond) | |
e6e5906b | 819 | { |
620c6cf6 RH |
820 | TCGv tmp, tmp2; |
821 | TCGCond tcond; | |
9d896621 | 822 | CCOp op = s->cc_op; |
e6e5906b | 823 | |
9d896621 RH |
824 | /* The CC_OP_CMP form can handle most normal comparisons directly. */ |
825 | if (op == CC_OP_CMP) { | |
826 | c->g1 = c->g2 = 1; | |
827 | c->v1 = QREG_CC_N; | |
828 | c->v2 = QREG_CC_V; | |
829 | switch (cond) { | |
830 | case 2: /* HI */ | |
831 | case 3: /* LS */ | |
832 | tcond = TCG_COND_LEU; | |
833 | goto done; | |
834 | case 4: /* CC */ | |
835 | case 5: /* CS */ | |
836 | tcond = TCG_COND_LTU; | |
837 | goto done; | |
838 | case 6: /* NE */ | |
839 | case 7: /* EQ */ | |
840 | tcond = TCG_COND_EQ; | |
841 | goto done; | |
842 | case 10: /* PL */ | |
843 | case 11: /* MI */ | |
844 | c->g1 = c->g2 = 0; | |
845 | c->v2 = tcg_const_i32(0); | |
846 | c->v1 = tmp = tcg_temp_new(); | |
847 | tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V); | |
848 | /* fallthru */ | |
849 | case 12: /* GE */ | |
850 | case 13: /* LT */ | |
851 | tcond = TCG_COND_LT; | |
852 | goto done; | |
853 | case 14: /* GT */ | |
854 | case 15: /* LE */ | |
855 | tcond = TCG_COND_LE; | |
856 | goto done; | |
857 | } | |
858 | } | |
6a432295 RH |
859 | |
860 | c->g1 = 1; | |
861 | c->g2 = 0; | |
862 | c->v2 = tcg_const_i32(0); | |
863 | ||
e6e5906b PB |
864 | switch (cond) { |
865 | case 0: /* T */ | |
e6e5906b | 866 | case 1: /* F */ |
6a432295 RH |
867 | c->v1 = c->v2; |
868 | tcond = TCG_COND_NEVER; | |
9d896621 RH |
869 | goto done; |
870 | case 14: /* GT (!(Z || (N ^ V))) */ | |
871 | case 15: /* LE (Z || (N ^ V)) */ | |
872 | /* Logic operations clear V, which simplifies LE to (Z || N), | |
873 | and since Z and N are co-located, this becomes a normal | |
874 | comparison vs N. */ | |
875 | if (op == CC_OP_LOGIC) { | |
876 | c->v1 = QREG_CC_N; | |
877 | tcond = TCG_COND_LE; | |
878 | goto done; | |
879 | } | |
6a432295 | 880 | break; |
9d896621 RH |
881 | case 12: /* GE (!(N ^ V)) */ |
882 | case 13: /* LT (N ^ V) */ | |
883 | /* Logic operations clear V, which simplifies this to N. */ | |
884 | if (op != CC_OP_LOGIC) { | |
885 | break; | |
886 | } | |
887 | /* fallthru */ | |
888 | case 10: /* PL (!N) */ | |
889 | case 11: /* MI (N) */ | |
890 | /* Several cases represent N normally. */ | |
891 | if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) { | |
892 | c->v1 = QREG_CC_N; | |
893 | tcond = TCG_COND_LT; | |
894 | goto done; | |
895 | } | |
896 | break; | |
897 | case 6: /* NE (!Z) */ | |
898 | case 7: /* EQ (Z) */ | |
899 | /* Some cases fold Z into N. */ | |
900 | if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) { | |
901 | tcond = TCG_COND_EQ; | |
902 | c->v1 = QREG_CC_N; | |
903 | goto done; | |
904 | } | |
905 | break; | |
906 | case 4: /* CC (!C) */ | |
907 | case 5: /* CS (C) */ | |
908 | /* Some cases fold C into X. */ | |
909 | if (op == CC_OP_ADD || op == CC_OP_SUB) { | |
910 | tcond = TCG_COND_NE; | |
911 | c->v1 = QREG_CC_X; | |
912 | goto done; | |
913 | } | |
914 | /* fallthru */ | |
915 | case 8: /* VC (!V) */ | |
916 | case 9: /* VS (V) */ | |
917 | /* Logic operations clear V and C. */ | |
918 | if (op == CC_OP_LOGIC) { | |
919 | tcond = TCG_COND_NEVER; | |
920 | c->v1 = c->v2; | |
921 | goto done; | |
922 | } | |
923 | break; | |
924 | } | |
925 | ||
926 | /* Otherwise, flush flag state to CC_OP_FLAGS. */ | |
927 | gen_flush_flags(s); | |
928 | ||
929 | switch (cond) { | |
930 | case 0: /* T */ | |
931 | case 1: /* F */ | |
932 | default: | |
933 | /* Invalid, or handled above. */ | |
934 | abort(); | |
620c6cf6 | 935 | case 2: /* HI (!C && !Z) -> !(C || Z)*/ |
e6e5906b | 936 | case 3: /* LS (C || Z) */ |
6a432295 RH |
937 | c->v1 = tmp = tcg_temp_new(); |
938 | c->g1 = 0; | |
939 | tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); | |
620c6cf6 | 940 | tcg_gen_or_i32(tmp, tmp, QREG_CC_C); |
6a432295 | 941 | tcond = TCG_COND_NE; |
e6e5906b PB |
942 | break; |
943 | case 4: /* CC (!C) */ | |
e6e5906b | 944 | case 5: /* CS (C) */ |
6a432295 RH |
945 | c->v1 = QREG_CC_C; |
946 | tcond = TCG_COND_NE; | |
e6e5906b PB |
947 | break; |
948 | case 6: /* NE (!Z) */ | |
e6e5906b | 949 | case 7: /* EQ (Z) */ |
6a432295 RH |
950 | c->v1 = QREG_CC_Z; |
951 | tcond = TCG_COND_EQ; | |
e6e5906b PB |
952 | break; |
953 | case 8: /* VC (!V) */ | |
e6e5906b | 954 | case 9: /* VS (V) */ |
6a432295 RH |
955 | c->v1 = QREG_CC_V; |
956 | tcond = TCG_COND_LT; | |
e6e5906b PB |
957 | break; |
958 | case 10: /* PL (!N) */ | |
e6e5906b | 959 | case 11: /* MI (N) */ |
6a432295 RH |
960 | c->v1 = QREG_CC_N; |
961 | tcond = TCG_COND_LT; | |
e6e5906b PB |
962 | break; |
963 | case 12: /* GE (!(N ^ V)) */ | |
e6e5906b | 964 | case 13: /* LT (N ^ V) */ |
6a432295 RH |
965 | c->v1 = tmp = tcg_temp_new(); |
966 | c->g1 = 0; | |
620c6cf6 | 967 | tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V); |
6a432295 | 968 | tcond = TCG_COND_LT; |
e6e5906b PB |
969 | break; |
970 | case 14: /* GT (!(Z || (N ^ V))) */ | |
e6e5906b | 971 | case 15: /* LE (Z || (N ^ V)) */ |
6a432295 RH |
972 | c->v1 = tmp = tcg_temp_new(); |
973 | c->g1 = 0; | |
974 | tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); | |
620c6cf6 RH |
975 | tcg_gen_neg_i32(tmp, tmp); |
976 | tmp2 = tcg_temp_new(); | |
977 | tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); | |
978 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
6a432295 RH |
979 | tcg_temp_free(tmp2); |
980 | tcond = TCG_COND_LT; | |
e6e5906b | 981 | break; |
e6e5906b | 982 | } |
9d896621 RH |
983 | |
984 | done: | |
6a432295 RH |
985 | if ((cond & 1) == 0) { |
986 | tcond = tcg_invert_cond(tcond); | |
987 | } | |
988 | c->tcond = tcond; | |
989 | } | |
990 | ||
991 | static void free_cond(DisasCompare *c) | |
992 | { | |
993 | if (!c->g1) { | |
994 | tcg_temp_free(c->v1); | |
995 | } | |
996 | if (!c->g2) { | |
997 | tcg_temp_free(c->v2); | |
998 | } | |
999 | } | |
1000 | ||
1001 | static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) | |
1002 | { | |
1003 | DisasCompare c; | |
1004 | ||
1005 | gen_cc_cond(&c, s, cond); | |
1006 | update_cc_op(s); | |
1007 | tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); | |
1008 | free_cond(&c); | |
e6e5906b PB |
1009 | } |
1010 | ||
0633879f PB |
1011 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
1012 | static void gen_lookup_tb(DisasContext *s) | |
1013 | { | |
9fdb533f | 1014 | update_cc_op(s); |
e1f3808e | 1015 | tcg_gen_movi_i32(QREG_PC, s->pc); |
0633879f PB |
1016 | s->is_jmp = DISAS_UPDATE; |
1017 | } | |
1018 | ||
e1f3808e PB |
1019 | /* Generate a jump to an immediate address. */ |
1020 | static void gen_jmp_im(DisasContext *s, uint32_t dest) | |
1021 | { | |
9fdb533f | 1022 | update_cc_op(s); |
e1f3808e PB |
1023 | tcg_gen_movi_i32(QREG_PC, dest); |
1024 | s->is_jmp = DISAS_JUMP; | |
1025 | } | |
1026 | ||
1027 | /* Generate a jump to the address in qreg DEST. */ | |
1028 | static void gen_jmp(DisasContext *s, TCGv dest) | |
e6e5906b | 1029 | { |
9fdb533f | 1030 | update_cc_op(s); |
e1f3808e | 1031 | tcg_gen_mov_i32(QREG_PC, dest); |
e6e5906b PB |
1032 | s->is_jmp = DISAS_JUMP; |
1033 | } | |
1034 | ||
1035 | static void gen_exception(DisasContext *s, uint32_t where, int nr) | |
1036 | { | |
9fdb533f | 1037 | update_cc_op(s); |
e1f3808e | 1038 | gen_jmp_im(s, where); |
31871141 | 1039 | gen_helper_raise_exception(cpu_env, tcg_const_i32(nr)); |
e6e5906b PB |
1040 | } |
1041 | ||
510ff0b7 PB |
1042 | static inline void gen_addr_fault(DisasContext *s) |
1043 | { | |
1044 | gen_exception(s, s->insn_pc, EXCP_ADDRESS); | |
1045 | } | |
1046 | ||
d4d79bb1 BS |
1047 | #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ |
1048 | result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ | |
1049 | op_sign ? EA_LOADS : EA_LOADU); \ | |
1050 | if (IS_NULL_QREG(result)) { \ | |
1051 | gen_addr_fault(s); \ | |
1052 | return; \ | |
1053 | } \ | |
510ff0b7 PB |
1054 | } while (0) |
1055 | ||
d4d79bb1 BS |
1056 | #define DEST_EA(env, insn, opsize, val, addrp) do { \ |
1057 | TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ | |
1058 | if (IS_NULL_QREG(ea_result)) { \ | |
1059 | gen_addr_fault(s); \ | |
1060 | return; \ | |
1061 | } \ | |
510ff0b7 PB |
1062 | } while (0) |
1063 | ||
90aa39a1 SF |
1064 | static inline bool use_goto_tb(DisasContext *s, uint32_t dest) |
1065 | { | |
1066 | #ifndef CONFIG_USER_ONLY | |
1067 | return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || | |
1068 | (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
1069 | #else | |
1070 | return true; | |
1071 | #endif | |
1072 | } | |
1073 | ||
e6e5906b PB |
1074 | /* Generate a jump to an immediate address. */ |
1075 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | |
1076 | { | |
551bd27f | 1077 | if (unlikely(s->singlestep_enabled)) { |
e6e5906b | 1078 | gen_exception(s, dest, EXCP_DEBUG); |
90aa39a1 | 1079 | } else if (use_goto_tb(s, dest)) { |
57fec1fe | 1080 | tcg_gen_goto_tb(n); |
e1f3808e | 1081 | tcg_gen_movi_i32(QREG_PC, dest); |
90aa39a1 | 1082 | tcg_gen_exit_tb((uintptr_t)s->tb + n); |
e6e5906b | 1083 | } else { |
e1f3808e | 1084 | gen_jmp_im(s, dest); |
57fec1fe | 1085 | tcg_gen_exit_tb(0); |
e6e5906b PB |
1086 | } |
1087 | s->is_jmp = DISAS_TB_JUMP; | |
1088 | } | |
1089 | ||
d5a3cf33 LV |
1090 | DISAS_INSN(scc) |
1091 | { | |
1092 | DisasCompare c; | |
1093 | int cond; | |
1094 | TCGv tmp; | |
1095 | ||
1096 | cond = (insn >> 8) & 0xf; | |
1097 | gen_cc_cond(&c, s, cond); | |
1098 | ||
1099 | tmp = tcg_temp_new(); | |
1100 | tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); | |
1101 | free_cond(&c); | |
1102 | ||
1103 | tcg_gen_neg_i32(tmp, tmp); | |
1104 | DEST_EA(env, insn, OS_BYTE, tmp, NULL); | |
1105 | tcg_temp_free(tmp); | |
1106 | } | |
1107 | ||
beff27ab LV |
1108 | DISAS_INSN(dbcc) |
1109 | { | |
1110 | TCGLabel *l1; | |
1111 | TCGv reg; | |
1112 | TCGv tmp; | |
1113 | int16_t offset; | |
1114 | uint32_t base; | |
1115 | ||
1116 | reg = DREG(insn, 0); | |
1117 | base = s->pc; | |
1118 | offset = (int16_t)read_im16(env, s); | |
1119 | l1 = gen_new_label(); | |
1120 | gen_jmpcc(s, (insn >> 8) & 0xf, l1); | |
1121 | ||
1122 | tmp = tcg_temp_new(); | |
1123 | tcg_gen_ext16s_i32(tmp, reg); | |
1124 | tcg_gen_addi_i32(tmp, tmp, -1); | |
1125 | gen_partset_reg(OS_WORD, reg, tmp); | |
1126 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1); | |
1127 | gen_jmp_tb(s, 1, base + offset); | |
1128 | gen_set_label(l1); | |
1129 | gen_jmp_tb(s, 0, s->pc); | |
1130 | } | |
1131 | ||
e6e5906b PB |
1132 | DISAS_INSN(undef_mac) |
1133 | { | |
1134 | gen_exception(s, s->pc - 2, EXCP_LINEA); | |
1135 | } | |
1136 | ||
1137 | DISAS_INSN(undef_fpu) | |
1138 | { | |
1139 | gen_exception(s, s->pc - 2, EXCP_LINEF); | |
1140 | } | |
1141 | ||
1142 | DISAS_INSN(undef) | |
1143 | { | |
a47dddd7 AF |
1144 | M68kCPU *cpu = m68k_env_get_cpu(env); |
1145 | ||
e6e5906b | 1146 | gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); |
a47dddd7 | 1147 | cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); |
e6e5906b PB |
1148 | } |
1149 | ||
1150 | DISAS_INSN(mulw) | |
1151 | { | |
e1f3808e PB |
1152 | TCGv reg; |
1153 | TCGv tmp; | |
1154 | TCGv src; | |
e6e5906b PB |
1155 | int sign; |
1156 | ||
1157 | sign = (insn & 0x100) != 0; | |
1158 | reg = DREG(insn, 9); | |
a7812ae4 | 1159 | tmp = tcg_temp_new(); |
e6e5906b | 1160 | if (sign) |
e1f3808e | 1161 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1162 | else |
e1f3808e | 1163 | tcg_gen_ext16u_i32(tmp, reg); |
d4d79bb1 | 1164 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e PB |
1165 | tcg_gen_mul_i32(tmp, tmp, src); |
1166 | tcg_gen_mov_i32(reg, tmp); | |
5dbb6784 | 1167 | gen_logic_cc(s, tmp, OS_WORD); |
e6e5906b PB |
1168 | } |
1169 | ||
1170 | DISAS_INSN(divw) | |
1171 | { | |
e1f3808e PB |
1172 | TCGv reg; |
1173 | TCGv tmp; | |
1174 | TCGv src; | |
e6e5906b PB |
1175 | int sign; |
1176 | ||
1177 | sign = (insn & 0x100) != 0; | |
1178 | reg = DREG(insn, 9); | |
1179 | if (sign) { | |
e1f3808e | 1180 | tcg_gen_ext16s_i32(QREG_DIV1, reg); |
e6e5906b | 1181 | } else { |
e1f3808e | 1182 | tcg_gen_ext16u_i32(QREG_DIV1, reg); |
e6e5906b | 1183 | } |
d4d79bb1 | 1184 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e | 1185 | tcg_gen_mov_i32(QREG_DIV2, src); |
e6e5906b | 1186 | if (sign) { |
e1f3808e | 1187 | gen_helper_divs(cpu_env, tcg_const_i32(1)); |
e6e5906b | 1188 | } else { |
e1f3808e | 1189 | gen_helper_divu(cpu_env, tcg_const_i32(1)); |
e6e5906b PB |
1190 | } |
1191 | ||
a7812ae4 PB |
1192 | tmp = tcg_temp_new(); |
1193 | src = tcg_temp_new(); | |
e1f3808e PB |
1194 | tcg_gen_ext16u_i32(tmp, QREG_DIV1); |
1195 | tcg_gen_shli_i32(src, QREG_DIV2, 16); | |
1196 | tcg_gen_or_i32(reg, tmp, src); | |
620c6cf6 | 1197 | |
9fdb533f | 1198 | set_cc_op(s, CC_OP_FLAGS); |
e6e5906b PB |
1199 | } |
1200 | ||
1201 | DISAS_INSN(divl) | |
1202 | { | |
e1f3808e PB |
1203 | TCGv num; |
1204 | TCGv den; | |
1205 | TCGv reg; | |
e6e5906b PB |
1206 | uint16_t ext; |
1207 | ||
28b68cd7 | 1208 | ext = read_im16(env, s); |
e6e5906b PB |
1209 | if (ext & 0x87f8) { |
1210 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
1211 | return; | |
1212 | } | |
1213 | num = DREG(ext, 12); | |
1214 | reg = DREG(ext, 0); | |
e1f3808e | 1215 | tcg_gen_mov_i32(QREG_DIV1, num); |
d4d79bb1 | 1216 | SRC_EA(env, den, OS_LONG, 0, NULL); |
e1f3808e | 1217 | tcg_gen_mov_i32(QREG_DIV2, den); |
e6e5906b | 1218 | if (ext & 0x0800) { |
e1f3808e | 1219 | gen_helper_divs(cpu_env, tcg_const_i32(0)); |
e6e5906b | 1220 | } else { |
e1f3808e | 1221 | gen_helper_divu(cpu_env, tcg_const_i32(0)); |
e6e5906b | 1222 | } |
e1f3808e | 1223 | if ((ext & 7) == ((ext >> 12) & 7)) { |
e6e5906b | 1224 | /* div */ |
e1f3808e | 1225 | tcg_gen_mov_i32 (reg, QREG_DIV1); |
e6e5906b PB |
1226 | } else { |
1227 | /* rem */ | |
e1f3808e | 1228 | tcg_gen_mov_i32 (reg, QREG_DIV2); |
e6e5906b | 1229 | } |
9fdb533f | 1230 | set_cc_op(s, CC_OP_FLAGS); |
e6e5906b PB |
1231 | } |
1232 | ||
1233 | DISAS_INSN(addsub) | |
1234 | { | |
e1f3808e PB |
1235 | TCGv reg; |
1236 | TCGv dest; | |
1237 | TCGv src; | |
1238 | TCGv tmp; | |
1239 | TCGv addr; | |
e6e5906b PB |
1240 | int add; |
1241 | ||
1242 | add = (insn & 0x4000) != 0; | |
1243 | reg = DREG(insn, 9); | |
a7812ae4 | 1244 | dest = tcg_temp_new(); |
e6e5906b | 1245 | if (insn & 0x100) { |
d4d79bb1 | 1246 | SRC_EA(env, tmp, OS_LONG, 0, &addr); |
e6e5906b PB |
1247 | src = reg; |
1248 | } else { | |
1249 | tmp = reg; | |
d4d79bb1 | 1250 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b PB |
1251 | } |
1252 | if (add) { | |
e1f3808e | 1253 | tcg_gen_add_i32(dest, tmp, src); |
f9083519 | 1254 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); |
9fdb533f | 1255 | set_cc_op(s, CC_OP_ADD); |
e6e5906b | 1256 | } else { |
f9083519 | 1257 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); |
e1f3808e | 1258 | tcg_gen_sub_i32(dest, tmp, src); |
9fdb533f | 1259 | set_cc_op(s, CC_OP_SUB); |
e6e5906b | 1260 | } |
e1f3808e | 1261 | gen_update_cc_add(dest, src); |
e6e5906b | 1262 | if (insn & 0x100) { |
d4d79bb1 | 1263 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1264 | } else { |
e1f3808e | 1265 | tcg_gen_mov_i32(reg, dest); |
e6e5906b PB |
1266 | } |
1267 | } | |
1268 | ||
1269 | ||
1270 | /* Reverse the order of the bits in REG. */ | |
1271 | DISAS_INSN(bitrev) | |
1272 | { | |
e1f3808e | 1273 | TCGv reg; |
e6e5906b | 1274 | reg = DREG(insn, 0); |
e1f3808e | 1275 | gen_helper_bitrev(reg, reg); |
e6e5906b PB |
1276 | } |
1277 | ||
1278 | DISAS_INSN(bitop_reg) | |
1279 | { | |
1280 | int opsize; | |
1281 | int op; | |
e1f3808e PB |
1282 | TCGv src1; |
1283 | TCGv src2; | |
1284 | TCGv tmp; | |
1285 | TCGv addr; | |
1286 | TCGv dest; | |
e6e5906b PB |
1287 | |
1288 | if ((insn & 0x38) != 0) | |
1289 | opsize = OS_BYTE; | |
1290 | else | |
1291 | opsize = OS_LONG; | |
1292 | op = (insn >> 6) & 3; | |
620c6cf6 RH |
1293 | |
1294 | gen_flush_flags(s); | |
1295 | ||
d4d79bb1 | 1296 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1297 | src2 = DREG(insn, 9); |
a7812ae4 | 1298 | dest = tcg_temp_new(); |
e6e5906b | 1299 | |
a7812ae4 | 1300 | tmp = tcg_temp_new(); |
e6e5906b | 1301 | if (opsize == OS_BYTE) |
e1f3808e | 1302 | tcg_gen_andi_i32(tmp, src2, 7); |
e6e5906b | 1303 | else |
e1f3808e | 1304 | tcg_gen_andi_i32(tmp, src2, 31); |
620c6cf6 RH |
1305 | |
1306 | src2 = tcg_const_i32(1); | |
1307 | tcg_gen_shl_i32(src2, src2, tmp); | |
1308 | tcg_temp_free(tmp); | |
1309 | ||
1310 | tcg_gen_and_i32(QREG_CC_Z, src1, src2); | |
1311 | ||
e6e5906b PB |
1312 | switch (op) { |
1313 | case 1: /* bchg */ | |
620c6cf6 | 1314 | tcg_gen_xor_i32(dest, src1, src2); |
e6e5906b PB |
1315 | break; |
1316 | case 2: /* bclr */ | |
620c6cf6 | 1317 | tcg_gen_andc_i32(dest, src1, src2); |
e6e5906b PB |
1318 | break; |
1319 | case 3: /* bset */ | |
620c6cf6 | 1320 | tcg_gen_or_i32(dest, src1, src2); |
e6e5906b PB |
1321 | break; |
1322 | default: /* btst */ | |
1323 | break; | |
1324 | } | |
620c6cf6 RH |
1325 | tcg_temp_free(src2); |
1326 | if (op) { | |
d4d79bb1 | 1327 | DEST_EA(env, insn, opsize, dest, &addr); |
620c6cf6 RH |
1328 | } |
1329 | tcg_temp_free(dest); | |
e6e5906b PB |
1330 | } |
1331 | ||
1332 | DISAS_INSN(sats) | |
1333 | { | |
e1f3808e | 1334 | TCGv reg; |
e6e5906b | 1335 | reg = DREG(insn, 0); |
e6e5906b | 1336 | gen_flush_flags(s); |
620c6cf6 | 1337 | gen_helper_sats(reg, reg, QREG_CC_V); |
5dbb6784 | 1338 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1339 | } |
1340 | ||
e1f3808e | 1341 | static void gen_push(DisasContext *s, TCGv val) |
e6e5906b | 1342 | { |
e1f3808e | 1343 | TCGv tmp; |
e6e5906b | 1344 | |
a7812ae4 | 1345 | tmp = tcg_temp_new(); |
e1f3808e | 1346 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1347 | gen_store(s, OS_LONG, tmp, val); |
e1f3808e | 1348 | tcg_gen_mov_i32(QREG_SP, tmp); |
e6e5906b PB |
1349 | } |
1350 | ||
1351 | DISAS_INSN(movem) | |
1352 | { | |
e1f3808e | 1353 | TCGv addr; |
e6e5906b PB |
1354 | int i; |
1355 | uint16_t mask; | |
e1f3808e PB |
1356 | TCGv reg; |
1357 | TCGv tmp; | |
e6e5906b PB |
1358 | int is_load; |
1359 | ||
28b68cd7 | 1360 | mask = read_im16(env, s); |
d4d79bb1 | 1361 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1362 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1363 | gen_addr_fault(s); |
1364 | return; | |
1365 | } | |
a7812ae4 | 1366 | addr = tcg_temp_new(); |
e1f3808e | 1367 | tcg_gen_mov_i32(addr, tmp); |
e6e5906b PB |
1368 | is_load = ((insn & 0x0400) != 0); |
1369 | for (i = 0; i < 16; i++, mask >>= 1) { | |
1370 | if (mask & 1) { | |
1371 | if (i < 8) | |
1372 | reg = DREG(i, 0); | |
1373 | else | |
1374 | reg = AREG(i, 0); | |
1375 | if (is_load) { | |
0633879f | 1376 | tmp = gen_load(s, OS_LONG, addr, 0); |
e1f3808e | 1377 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b | 1378 | } else { |
0633879f | 1379 | gen_store(s, OS_LONG, addr, reg); |
e6e5906b PB |
1380 | } |
1381 | if (mask != 1) | |
e1f3808e | 1382 | tcg_gen_addi_i32(addr, addr, 4); |
e6e5906b PB |
1383 | } |
1384 | } | |
1385 | } | |
1386 | ||
1387 | DISAS_INSN(bitop_im) | |
1388 | { | |
1389 | int opsize; | |
1390 | int op; | |
e1f3808e | 1391 | TCGv src1; |
e6e5906b PB |
1392 | uint32_t mask; |
1393 | int bitnum; | |
e1f3808e PB |
1394 | TCGv tmp; |
1395 | TCGv addr; | |
e6e5906b PB |
1396 | |
1397 | if ((insn & 0x38) != 0) | |
1398 | opsize = OS_BYTE; | |
1399 | else | |
1400 | opsize = OS_LONG; | |
1401 | op = (insn >> 6) & 3; | |
1402 | ||
28b68cd7 | 1403 | bitnum = read_im16(env, s); |
e6e5906b | 1404 | if (bitnum & 0xff00) { |
d4d79bb1 | 1405 | disas_undef(env, s, insn); |
e6e5906b PB |
1406 | return; |
1407 | } | |
1408 | ||
620c6cf6 RH |
1409 | gen_flush_flags(s); |
1410 | ||
d4d79bb1 | 1411 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1412 | |
e6e5906b PB |
1413 | if (opsize == OS_BYTE) |
1414 | bitnum &= 7; | |
1415 | else | |
1416 | bitnum &= 31; | |
1417 | mask = 1 << bitnum; | |
1418 | ||
620c6cf6 RH |
1419 | tcg_gen_andi_i32(QREG_CC_Z, src1, mask); |
1420 | ||
e1f3808e | 1421 | if (op) { |
620c6cf6 | 1422 | tmp = tcg_temp_new(); |
e1f3808e PB |
1423 | switch (op) { |
1424 | case 1: /* bchg */ | |
1425 | tcg_gen_xori_i32(tmp, src1, mask); | |
1426 | break; | |
1427 | case 2: /* bclr */ | |
1428 | tcg_gen_andi_i32(tmp, src1, ~mask); | |
1429 | break; | |
1430 | case 3: /* bset */ | |
1431 | tcg_gen_ori_i32(tmp, src1, mask); | |
1432 | break; | |
1433 | default: /* btst */ | |
1434 | break; | |
1435 | } | |
d4d79bb1 | 1436 | DEST_EA(env, insn, opsize, tmp, &addr); |
620c6cf6 | 1437 | tcg_temp_free(tmp); |
e6e5906b | 1438 | } |
e6e5906b | 1439 | } |
620c6cf6 | 1440 | |
e6e5906b PB |
1441 | DISAS_INSN(arith_im) |
1442 | { | |
1443 | int op; | |
e1f3808e PB |
1444 | uint32_t im; |
1445 | TCGv src1; | |
1446 | TCGv dest; | |
1447 | TCGv addr; | |
e6e5906b PB |
1448 | |
1449 | op = (insn >> 9) & 7; | |
d4d79bb1 BS |
1450 | SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr); |
1451 | im = read_im32(env, s); | |
a7812ae4 | 1452 | dest = tcg_temp_new(); |
e6e5906b PB |
1453 | switch (op) { |
1454 | case 0: /* ori */ | |
e1f3808e | 1455 | tcg_gen_ori_i32(dest, src1, im); |
5dbb6784 | 1456 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1457 | break; |
1458 | case 1: /* andi */ | |
e1f3808e | 1459 | tcg_gen_andi_i32(dest, src1, im); |
5dbb6784 | 1460 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1461 | break; |
1462 | case 2: /* subi */ | |
e1f3808e | 1463 | tcg_gen_mov_i32(dest, src1); |
620c6cf6 | 1464 | tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im); |
e1f3808e | 1465 | tcg_gen_subi_i32(dest, dest, im); |
351326a6 | 1466 | gen_update_cc_add(dest, tcg_const_i32(im)); |
9fdb533f | 1467 | set_cc_op(s, CC_OP_SUB); |
e6e5906b PB |
1468 | break; |
1469 | case 3: /* addi */ | |
e1f3808e PB |
1470 | tcg_gen_mov_i32(dest, src1); |
1471 | tcg_gen_addi_i32(dest, dest, im); | |
351326a6 | 1472 | gen_update_cc_add(dest, tcg_const_i32(im)); |
620c6cf6 | 1473 | tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im); |
9fdb533f | 1474 | set_cc_op(s, CC_OP_ADD); |
e6e5906b PB |
1475 | break; |
1476 | case 5: /* eori */ | |
e1f3808e | 1477 | tcg_gen_xori_i32(dest, src1, im); |
5dbb6784 | 1478 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1479 | break; |
1480 | case 6: /* cmpi */ | |
620c6cf6 RH |
1481 | gen_update_cc_add(src1, tcg_const_i32(im)); |
1482 | set_cc_op(s, CC_OP_CMP); | |
e6e5906b PB |
1483 | break; |
1484 | default: | |
1485 | abort(); | |
1486 | } | |
1487 | if (op != 6) { | |
d4d79bb1 | 1488 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1489 | } |
1490 | } | |
1491 | ||
1492 | DISAS_INSN(byterev) | |
1493 | { | |
e1f3808e | 1494 | TCGv reg; |
e6e5906b PB |
1495 | |
1496 | reg = DREG(insn, 0); | |
66896cb8 | 1497 | tcg_gen_bswap32_i32(reg, reg); |
e6e5906b PB |
1498 | } |
1499 | ||
1500 | DISAS_INSN(move) | |
1501 | { | |
e1f3808e PB |
1502 | TCGv src; |
1503 | TCGv dest; | |
e6e5906b PB |
1504 | int op; |
1505 | int opsize; | |
1506 | ||
1507 | switch (insn >> 12) { | |
1508 | case 1: /* move.b */ | |
1509 | opsize = OS_BYTE; | |
1510 | break; | |
1511 | case 2: /* move.l */ | |
1512 | opsize = OS_LONG; | |
1513 | break; | |
1514 | case 3: /* move.w */ | |
1515 | opsize = OS_WORD; | |
1516 | break; | |
1517 | default: | |
1518 | abort(); | |
1519 | } | |
d4d79bb1 | 1520 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b PB |
1521 | op = (insn >> 6) & 7; |
1522 | if (op == 1) { | |
1523 | /* movea */ | |
1524 | /* The value will already have been sign extended. */ | |
1525 | dest = AREG(insn, 9); | |
e1f3808e | 1526 | tcg_gen_mov_i32(dest, src); |
e6e5906b PB |
1527 | } else { |
1528 | /* normal move */ | |
1529 | uint16_t dest_ea; | |
1530 | dest_ea = ((insn >> 9) & 7) | (op << 3); | |
d4d79bb1 | 1531 | DEST_EA(env, dest_ea, opsize, src, NULL); |
e6e5906b | 1532 | /* This will be correct because loads sign extend. */ |
5dbb6784 | 1533 | gen_logic_cc(s, src, opsize); |
e6e5906b PB |
1534 | } |
1535 | } | |
1536 | ||
1537 | DISAS_INSN(negx) | |
1538 | { | |
a665a820 RH |
1539 | TCGv z; |
1540 | TCGv src; | |
1541 | TCGv addr; | |
1542 | int opsize; | |
e6e5906b | 1543 | |
a665a820 RH |
1544 | opsize = insn_opsize(insn); |
1545 | SRC_EA(env, src, opsize, 1, &addr); | |
1546 | ||
1547 | gen_flush_flags(s); /* compute old Z */ | |
1548 | ||
1549 | /* Perform substract with borrow. | |
1550 | * (X, N) = -(src + X); | |
1551 | */ | |
1552 | ||
1553 | z = tcg_const_i32(0); | |
1554 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z); | |
1555 | tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X); | |
1556 | tcg_temp_free(z); | |
1557 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
1558 | ||
1559 | tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); | |
1560 | ||
1561 | /* Compute signed-overflow for negation. The normal formula for | |
1562 | * subtraction is (res ^ src) & (src ^ dest), but with dest==0 | |
1563 | * this simplies to res & src. | |
1564 | */ | |
1565 | ||
1566 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src); | |
1567 | ||
1568 | /* Copy the rest of the results into place. */ | |
1569 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ | |
1570 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
1571 | ||
1572 | set_cc_op(s, CC_OP_FLAGS); | |
1573 | ||
1574 | /* result is in QREG_CC_N */ | |
1575 | ||
1576 | DEST_EA(env, insn, opsize, QREG_CC_N, &addr); | |
e6e5906b PB |
1577 | } |
1578 | ||
1579 | DISAS_INSN(lea) | |
1580 | { | |
e1f3808e PB |
1581 | TCGv reg; |
1582 | TCGv tmp; | |
e6e5906b PB |
1583 | |
1584 | reg = AREG(insn, 9); | |
d4d79bb1 | 1585 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1586 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1587 | gen_addr_fault(s); |
1588 | return; | |
1589 | } | |
e1f3808e | 1590 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1591 | } |
1592 | ||
1593 | DISAS_INSN(clr) | |
1594 | { | |
1595 | int opsize; | |
1596 | ||
7ef25cdd | 1597 | opsize = insn_opsize(insn); |
d4d79bb1 | 1598 | DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL); |
5dbb6784 | 1599 | gen_logic_cc(s, tcg_const_i32(0), opsize); |
e6e5906b PB |
1600 | } |
1601 | ||
e1f3808e | 1602 | static TCGv gen_get_ccr(DisasContext *s) |
e6e5906b | 1603 | { |
e1f3808e | 1604 | TCGv dest; |
e6e5906b PB |
1605 | |
1606 | gen_flush_flags(s); | |
620c6cf6 | 1607 | update_cc_op(s); |
a7812ae4 | 1608 | dest = tcg_temp_new(); |
620c6cf6 | 1609 | gen_helper_get_ccr(dest, cpu_env); |
0633879f PB |
1610 | return dest; |
1611 | } | |
1612 | ||
1613 | DISAS_INSN(move_from_ccr) | |
1614 | { | |
e1f3808e | 1615 | TCGv ccr; |
0633879f PB |
1616 | |
1617 | ccr = gen_get_ccr(s); | |
7c0eb318 | 1618 | DEST_EA(env, insn, OS_WORD, ccr, NULL); |
e6e5906b PB |
1619 | } |
1620 | ||
1621 | DISAS_INSN(neg) | |
1622 | { | |
e1f3808e PB |
1623 | TCGv reg; |
1624 | TCGv src1; | |
e6e5906b PB |
1625 | |
1626 | reg = DREG(insn, 0); | |
a7812ae4 | 1627 | src1 = tcg_temp_new(); |
e1f3808e PB |
1628 | tcg_gen_mov_i32(src1, reg); |
1629 | tcg_gen_neg_i32(reg, src1); | |
e1f3808e | 1630 | gen_update_cc_add(reg, src1); |
620c6cf6 | 1631 | tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, src1, 0); |
9fdb533f | 1632 | set_cc_op(s, CC_OP_SUB); |
e6e5906b PB |
1633 | } |
1634 | ||
0633879f PB |
1635 | static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) |
1636 | { | |
620c6cf6 RH |
1637 | if (ccr_only) { |
1638 | tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0); | |
1639 | tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0); | |
1640 | tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1); | |
1641 | tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0); | |
1642 | tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0); | |
1643 | } else { | |
1644 | gen_helper_set_sr(cpu_env, tcg_const_i32(val)); | |
0633879f | 1645 | } |
9fdb533f | 1646 | set_cc_op(s, CC_OP_FLAGS); |
0633879f PB |
1647 | } |
1648 | ||
620c6cf6 RH |
1649 | static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, |
1650 | int ccr_only) | |
e6e5906b | 1651 | { |
620c6cf6 RH |
1652 | if ((insn & 0x38) == 0) { |
1653 | if (ccr_only) { | |
1654 | gen_helper_set_ccr(cpu_env, DREG(insn, 0)); | |
1655 | } else { | |
1656 | gen_helper_set_sr(cpu_env, DREG(insn, 0)); | |
1657 | } | |
1658 | set_cc_op(s, CC_OP_FLAGS); | |
1659 | } else if ((insn & 0x3f) == 0x3c) { | |
1660 | uint16_t val; | |
1661 | val = read_im16(env, s); | |
1662 | gen_set_sr_im(s, val, ccr_only); | |
1663 | } else { | |
1664 | disas_undef(env, s, insn); | |
7c0eb318 LV |
1665 | } |
1666 | } | |
e6e5906b | 1667 | |
7c0eb318 | 1668 | |
0633879f PB |
1669 | DISAS_INSN(move_to_ccr) |
1670 | { | |
620c6cf6 | 1671 | gen_set_sr(env, s, insn, 1); |
0633879f PB |
1672 | } |
1673 | ||
e6e5906b PB |
1674 | DISAS_INSN(not) |
1675 | { | |
e1f3808e | 1676 | TCGv reg; |
e6e5906b PB |
1677 | |
1678 | reg = DREG(insn, 0); | |
e1f3808e | 1679 | tcg_gen_not_i32(reg, reg); |
5dbb6784 | 1680 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1681 | } |
1682 | ||
1683 | DISAS_INSN(swap) | |
1684 | { | |
e1f3808e PB |
1685 | TCGv src1; |
1686 | TCGv src2; | |
1687 | TCGv reg; | |
e6e5906b | 1688 | |
a7812ae4 PB |
1689 | src1 = tcg_temp_new(); |
1690 | src2 = tcg_temp_new(); | |
e6e5906b | 1691 | reg = DREG(insn, 0); |
e1f3808e PB |
1692 | tcg_gen_shli_i32(src1, reg, 16); |
1693 | tcg_gen_shri_i32(src2, reg, 16); | |
1694 | tcg_gen_or_i32(reg, src1, src2); | |
5dbb6784 | 1695 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1696 | } |
1697 | ||
71600eda LV |
1698 | DISAS_INSN(bkpt) |
1699 | { | |
1700 | gen_exception(s, s->pc - 2, EXCP_DEBUG); | |
1701 | } | |
1702 | ||
e6e5906b PB |
1703 | DISAS_INSN(pea) |
1704 | { | |
e1f3808e | 1705 | TCGv tmp; |
e6e5906b | 1706 | |
d4d79bb1 | 1707 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1708 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1709 | gen_addr_fault(s); |
1710 | return; | |
1711 | } | |
0633879f | 1712 | gen_push(s, tmp); |
e6e5906b PB |
1713 | } |
1714 | ||
1715 | DISAS_INSN(ext) | |
1716 | { | |
e6e5906b | 1717 | int op; |
e1f3808e PB |
1718 | TCGv reg; |
1719 | TCGv tmp; | |
e6e5906b PB |
1720 | |
1721 | reg = DREG(insn, 0); | |
1722 | op = (insn >> 6) & 7; | |
a7812ae4 | 1723 | tmp = tcg_temp_new(); |
e6e5906b | 1724 | if (op == 3) |
e1f3808e | 1725 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1726 | else |
e1f3808e | 1727 | tcg_gen_ext8s_i32(tmp, reg); |
e6e5906b PB |
1728 | if (op == 2) |
1729 | gen_partset_reg(OS_WORD, reg, tmp); | |
1730 | else | |
e1f3808e | 1731 | tcg_gen_mov_i32(reg, tmp); |
5dbb6784 | 1732 | gen_logic_cc(s, tmp, OS_LONG); |
e6e5906b PB |
1733 | } |
1734 | ||
1735 | DISAS_INSN(tst) | |
1736 | { | |
1737 | int opsize; | |
e1f3808e | 1738 | TCGv tmp; |
e6e5906b | 1739 | |
7ef25cdd | 1740 | opsize = insn_opsize(insn); |
d4d79bb1 | 1741 | SRC_EA(env, tmp, opsize, 1, NULL); |
5dbb6784 | 1742 | gen_logic_cc(s, tmp, opsize); |
e6e5906b PB |
1743 | } |
1744 | ||
1745 | DISAS_INSN(pulse) | |
1746 | { | |
1747 | /* Implemented as a NOP. */ | |
1748 | } | |
1749 | ||
1750 | DISAS_INSN(illegal) | |
1751 | { | |
1752 | gen_exception(s, s->pc - 2, EXCP_ILLEGAL); | |
1753 | } | |
1754 | ||
1755 | /* ??? This should be atomic. */ | |
1756 | DISAS_INSN(tas) | |
1757 | { | |
e1f3808e PB |
1758 | TCGv dest; |
1759 | TCGv src1; | |
1760 | TCGv addr; | |
e6e5906b | 1761 | |
a7812ae4 | 1762 | dest = tcg_temp_new(); |
d4d79bb1 | 1763 | SRC_EA(env, src1, OS_BYTE, 1, &addr); |
5dbb6784 | 1764 | gen_logic_cc(s, src1, OS_BYTE); |
e1f3808e | 1765 | tcg_gen_ori_i32(dest, src1, 0x80); |
d4d79bb1 | 1766 | DEST_EA(env, insn, OS_BYTE, dest, &addr); |
e6e5906b PB |
1767 | } |
1768 | ||
1769 | DISAS_INSN(mull) | |
1770 | { | |
1771 | uint16_t ext; | |
e1f3808e PB |
1772 | TCGv reg; |
1773 | TCGv src1; | |
1774 | TCGv dest; | |
e6e5906b PB |
1775 | |
1776 | /* The upper 32 bits of the product are discarded, so | |
1777 | muls.l and mulu.l are functionally equivalent. */ | |
28b68cd7 | 1778 | ext = read_im16(env, s); |
e6e5906b PB |
1779 | if (ext & 0x87ff) { |
1780 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
1781 | return; | |
1782 | } | |
1783 | reg = DREG(ext, 12); | |
d4d79bb1 | 1784 | SRC_EA(env, src1, OS_LONG, 0, NULL); |
a7812ae4 | 1785 | dest = tcg_temp_new(); |
e1f3808e PB |
1786 | tcg_gen_mul_i32(dest, src1, reg); |
1787 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b | 1788 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
5dbb6784 | 1789 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1790 | } |
1791 | ||
c630e436 | 1792 | static void gen_link(DisasContext *s, uint16_t insn, int32_t offset) |
e6e5906b | 1793 | { |
e1f3808e PB |
1794 | TCGv reg; |
1795 | TCGv tmp; | |
e6e5906b | 1796 | |
e6e5906b | 1797 | reg = AREG(insn, 0); |
a7812ae4 | 1798 | tmp = tcg_temp_new(); |
e1f3808e | 1799 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1800 | gen_store(s, OS_LONG, tmp, reg); |
c630e436 | 1801 | if ((insn & 7) != 7) { |
e1f3808e | 1802 | tcg_gen_mov_i32(reg, tmp); |
c630e436 | 1803 | } |
e1f3808e | 1804 | tcg_gen_addi_i32(QREG_SP, tmp, offset); |
c630e436 LV |
1805 | tcg_temp_free(tmp); |
1806 | } | |
1807 | ||
1808 | DISAS_INSN(link) | |
1809 | { | |
1810 | int16_t offset; | |
1811 | ||
1812 | offset = read_im16(env, s); | |
1813 | gen_link(s, insn, offset); | |
1814 | } | |
1815 | ||
1816 | DISAS_INSN(linkl) | |
1817 | { | |
1818 | int32_t offset; | |
1819 | ||
1820 | offset = read_im32(env, s); | |
1821 | gen_link(s, insn, offset); | |
e6e5906b PB |
1822 | } |
1823 | ||
1824 | DISAS_INSN(unlk) | |
1825 | { | |
e1f3808e PB |
1826 | TCGv src; |
1827 | TCGv reg; | |
1828 | TCGv tmp; | |
e6e5906b | 1829 | |
a7812ae4 | 1830 | src = tcg_temp_new(); |
e6e5906b | 1831 | reg = AREG(insn, 0); |
e1f3808e | 1832 | tcg_gen_mov_i32(src, reg); |
0633879f | 1833 | tmp = gen_load(s, OS_LONG, src, 0); |
e1f3808e PB |
1834 | tcg_gen_mov_i32(reg, tmp); |
1835 | tcg_gen_addi_i32(QREG_SP, src, 4); | |
e6e5906b PB |
1836 | } |
1837 | ||
1838 | DISAS_INSN(nop) | |
1839 | { | |
1840 | } | |
1841 | ||
1842 | DISAS_INSN(rts) | |
1843 | { | |
e1f3808e | 1844 | TCGv tmp; |
e6e5906b | 1845 | |
0633879f | 1846 | tmp = gen_load(s, OS_LONG, QREG_SP, 0); |
e1f3808e | 1847 | tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); |
e6e5906b PB |
1848 | gen_jmp(s, tmp); |
1849 | } | |
1850 | ||
1851 | DISAS_INSN(jump) | |
1852 | { | |
e1f3808e | 1853 | TCGv tmp; |
e6e5906b PB |
1854 | |
1855 | /* Load the target address first to ensure correct exception | |
1856 | behavior. */ | |
d4d79bb1 | 1857 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1858 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1859 | gen_addr_fault(s); |
1860 | return; | |
1861 | } | |
e6e5906b PB |
1862 | if ((insn & 0x40) == 0) { |
1863 | /* jsr */ | |
351326a6 | 1864 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1865 | } |
1866 | gen_jmp(s, tmp); | |
1867 | } | |
1868 | ||
1869 | DISAS_INSN(addsubq) | |
1870 | { | |
e1f3808e PB |
1871 | TCGv src1; |
1872 | TCGv src2; | |
1873 | TCGv dest; | |
e6e5906b | 1874 | int val; |
e1f3808e | 1875 | TCGv addr; |
e6e5906b | 1876 | |
d4d79bb1 | 1877 | SRC_EA(env, src1, OS_LONG, 0, &addr); |
e6e5906b PB |
1878 | val = (insn >> 9) & 7; |
1879 | if (val == 0) | |
1880 | val = 8; | |
a7812ae4 | 1881 | dest = tcg_temp_new(); |
e1f3808e | 1882 | tcg_gen_mov_i32(dest, src1); |
e6e5906b PB |
1883 | if ((insn & 0x38) == 0x08) { |
1884 | /* Don't update condition codes if the destination is an | |
1885 | address register. */ | |
1886 | if (insn & 0x0100) { | |
e1f3808e | 1887 | tcg_gen_subi_i32(dest, dest, val); |
e6e5906b | 1888 | } else { |
e1f3808e | 1889 | tcg_gen_addi_i32(dest, dest, val); |
e6e5906b PB |
1890 | } |
1891 | } else { | |
351326a6 | 1892 | src2 = tcg_const_i32(val); |
e6e5906b | 1893 | if (insn & 0x0100) { |
f9083519 | 1894 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); |
620c6cf6 | 1895 | tcg_gen_sub_i32(dest, dest, src2); |
9fdb533f | 1896 | set_cc_op(s, CC_OP_SUB); |
e6e5906b | 1897 | } else { |
620c6cf6 | 1898 | tcg_gen_add_i32(dest, dest, src2); |
f9083519 | 1899 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); |
9fdb533f | 1900 | set_cc_op(s, CC_OP_ADD); |
e6e5906b | 1901 | } |
e1f3808e | 1902 | gen_update_cc_add(dest, src2); |
e6e5906b | 1903 | } |
d4d79bb1 | 1904 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1905 | } |
1906 | ||
1907 | DISAS_INSN(tpf) | |
1908 | { | |
1909 | switch (insn & 7) { | |
1910 | case 2: /* One extension word. */ | |
1911 | s->pc += 2; | |
1912 | break; | |
1913 | case 3: /* Two extension words. */ | |
1914 | s->pc += 4; | |
1915 | break; | |
1916 | case 4: /* No extension words. */ | |
1917 | break; | |
1918 | default: | |
d4d79bb1 | 1919 | disas_undef(env, s, insn); |
e6e5906b PB |
1920 | } |
1921 | } | |
1922 | ||
1923 | DISAS_INSN(branch) | |
1924 | { | |
1925 | int32_t offset; | |
1926 | uint32_t base; | |
1927 | int op; | |
42a268c2 | 1928 | TCGLabel *l1; |
3b46e624 | 1929 | |
e6e5906b PB |
1930 | base = s->pc; |
1931 | op = (insn >> 8) & 0xf; | |
1932 | offset = (int8_t)insn; | |
1933 | if (offset == 0) { | |
28b68cd7 | 1934 | offset = (int16_t)read_im16(env, s); |
e6e5906b | 1935 | } else if (offset == -1) { |
d4d79bb1 | 1936 | offset = read_im32(env, s); |
e6e5906b PB |
1937 | } |
1938 | if (op == 1) { | |
1939 | /* bsr */ | |
351326a6 | 1940 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b | 1941 | } |
e6e5906b PB |
1942 | if (op > 1) { |
1943 | /* Bcc */ | |
1944 | l1 = gen_new_label(); | |
1945 | gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); | |
1946 | gen_jmp_tb(s, 1, base + offset); | |
1947 | gen_set_label(l1); | |
1948 | gen_jmp_tb(s, 0, s->pc); | |
1949 | } else { | |
1950 | /* Unconditional branch. */ | |
1951 | gen_jmp_tb(s, 0, base + offset); | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | DISAS_INSN(moveq) | |
1956 | { | |
e1f3808e | 1957 | uint32_t val; |
e6e5906b | 1958 | |
e1f3808e PB |
1959 | val = (int8_t)insn; |
1960 | tcg_gen_movi_i32(DREG(insn, 9), val); | |
5dbb6784 | 1961 | gen_logic_cc(s, tcg_const_i32(val), OS_LONG); |
e6e5906b PB |
1962 | } |
1963 | ||
1964 | DISAS_INSN(mvzs) | |
1965 | { | |
1966 | int opsize; | |
e1f3808e PB |
1967 | TCGv src; |
1968 | TCGv reg; | |
e6e5906b PB |
1969 | |
1970 | if (insn & 0x40) | |
1971 | opsize = OS_WORD; | |
1972 | else | |
1973 | opsize = OS_BYTE; | |
d4d79bb1 | 1974 | SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); |
e6e5906b | 1975 | reg = DREG(insn, 9); |
e1f3808e | 1976 | tcg_gen_mov_i32(reg, src); |
5dbb6784 | 1977 | gen_logic_cc(s, src, opsize); |
e6e5906b PB |
1978 | } |
1979 | ||
1980 | DISAS_INSN(or) | |
1981 | { | |
e1f3808e PB |
1982 | TCGv reg; |
1983 | TCGv dest; | |
1984 | TCGv src; | |
1985 | TCGv addr; | |
e6e5906b PB |
1986 | |
1987 | reg = DREG(insn, 9); | |
a7812ae4 | 1988 | dest = tcg_temp_new(); |
e6e5906b | 1989 | if (insn & 0x100) { |
d4d79bb1 | 1990 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1991 | tcg_gen_or_i32(dest, src, reg); |
d4d79bb1 | 1992 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1993 | } else { |
d4d79bb1 | 1994 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1995 | tcg_gen_or_i32(dest, src, reg); |
1996 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b | 1997 | } |
5dbb6784 | 1998 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1999 | } |
2000 | ||
2001 | DISAS_INSN(suba) | |
2002 | { | |
e1f3808e PB |
2003 | TCGv src; |
2004 | TCGv reg; | |
e6e5906b | 2005 | |
d4d79bb1 | 2006 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 2007 | reg = AREG(insn, 9); |
e1f3808e | 2008 | tcg_gen_sub_i32(reg, reg, src); |
e6e5906b PB |
2009 | } |
2010 | ||
a665a820 | 2011 | static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize) |
e6e5906b | 2012 | { |
a665a820 RH |
2013 | TCGv tmp; |
2014 | ||
2015 | gen_flush_flags(s); /* compute old Z */ | |
2016 | ||
2017 | /* Perform substract with borrow. | |
2018 | * (X, N) = dest - (src + X); | |
2019 | */ | |
2020 | ||
2021 | tmp = tcg_const_i32(0); | |
2022 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp); | |
2023 | tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X); | |
2024 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
2025 | tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); | |
2026 | ||
2027 | /* Compute signed-overflow for substract. */ | |
2028 | ||
2029 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest); | |
2030 | tcg_gen_xor_i32(tmp, dest, src); | |
2031 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp); | |
2032 | tcg_temp_free(tmp); | |
2033 | ||
2034 | /* Copy the rest of the results into place. */ | |
2035 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ | |
2036 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
2037 | ||
2038 | set_cc_op(s, CC_OP_FLAGS); | |
2039 | ||
2040 | /* result is in QREG_CC_N */ | |
2041 | } | |
2042 | ||
2043 | DISAS_INSN(subx_reg) | |
2044 | { | |
2045 | TCGv dest; | |
e1f3808e | 2046 | TCGv src; |
a665a820 | 2047 | int opsize; |
e6e5906b | 2048 | |
a665a820 RH |
2049 | opsize = insn_opsize(insn); |
2050 | ||
2051 | src = gen_extend(DREG(insn, 0), opsize, 1); | |
2052 | dest = gen_extend(DREG(insn, 9), opsize, 1); | |
2053 | ||
2054 | gen_subx(s, src, dest, opsize); | |
2055 | ||
2056 | gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N); | |
2057 | } | |
2058 | ||
2059 | DISAS_INSN(subx_mem) | |
2060 | { | |
2061 | TCGv src; | |
2062 | TCGv addr_src; | |
2063 | TCGv dest; | |
2064 | TCGv addr_dest; | |
2065 | int opsize; | |
2066 | ||
2067 | opsize = insn_opsize(insn); | |
2068 | ||
2069 | addr_src = AREG(insn, 0); | |
2070 | tcg_gen_subi_i32(addr_src, addr_src, opsize); | |
2071 | src = gen_load(s, opsize, addr_src, 1); | |
2072 | ||
2073 | addr_dest = AREG(insn, 9); | |
2074 | tcg_gen_subi_i32(addr_dest, addr_dest, opsize); | |
2075 | dest = gen_load(s, opsize, addr_dest, 1); | |
2076 | ||
2077 | gen_subx(s, src, dest, opsize); | |
2078 | ||
2079 | gen_store(s, opsize, addr_dest, QREG_CC_N); | |
e6e5906b PB |
2080 | } |
2081 | ||
2082 | DISAS_INSN(mov3q) | |
2083 | { | |
e1f3808e | 2084 | TCGv src; |
e6e5906b PB |
2085 | int val; |
2086 | ||
2087 | val = (insn >> 9) & 7; | |
2088 | if (val == 0) | |
2089 | val = -1; | |
351326a6 | 2090 | src = tcg_const_i32(val); |
5dbb6784 | 2091 | gen_logic_cc(s, src, OS_LONG); |
d4d79bb1 | 2092 | DEST_EA(env, insn, OS_LONG, src, NULL); |
e6e5906b PB |
2093 | } |
2094 | ||
2095 | DISAS_INSN(cmp) | |
2096 | { | |
e1f3808e PB |
2097 | TCGv src; |
2098 | TCGv reg; | |
e6e5906b PB |
2099 | int opsize; |
2100 | ||
5dbb6784 LV |
2101 | opsize = insn_opsize(insn); |
2102 | SRC_EA(env, src, opsize, -1, NULL); | |
e6e5906b | 2103 | reg = DREG(insn, 9); |
620c6cf6 RH |
2104 | gen_update_cc_add(reg, src); |
2105 | set_cc_op(s, CC_OP_CMP); | |
e6e5906b PB |
2106 | } |
2107 | ||
2108 | DISAS_INSN(cmpa) | |
2109 | { | |
2110 | int opsize; | |
e1f3808e PB |
2111 | TCGv src; |
2112 | TCGv reg; | |
e6e5906b PB |
2113 | |
2114 | if (insn & 0x100) { | |
2115 | opsize = OS_LONG; | |
2116 | } else { | |
2117 | opsize = OS_WORD; | |
2118 | } | |
d4d79bb1 | 2119 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 2120 | reg = AREG(insn, 9); |
620c6cf6 RH |
2121 | gen_update_cc_add(reg, src); |
2122 | set_cc_op(s, CC_OP_CMP); | |
e6e5906b PB |
2123 | } |
2124 | ||
2125 | DISAS_INSN(eor) | |
2126 | { | |
e1f3808e PB |
2127 | TCGv src; |
2128 | TCGv reg; | |
2129 | TCGv dest; | |
2130 | TCGv addr; | |
e6e5906b | 2131 | |
d4d79bb1 | 2132 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e6e5906b | 2133 | reg = DREG(insn, 9); |
a7812ae4 | 2134 | dest = tcg_temp_new(); |
e1f3808e | 2135 | tcg_gen_xor_i32(dest, src, reg); |
5dbb6784 | 2136 | gen_logic_cc(s, dest, OS_LONG); |
d4d79bb1 | 2137 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
2138 | } |
2139 | ||
29cf437d LV |
2140 | static void do_exg(TCGv reg1, TCGv reg2) |
2141 | { | |
2142 | TCGv temp = tcg_temp_new(); | |
2143 | tcg_gen_mov_i32(temp, reg1); | |
2144 | tcg_gen_mov_i32(reg1, reg2); | |
2145 | tcg_gen_mov_i32(reg2, temp); | |
2146 | tcg_temp_free(temp); | |
2147 | } | |
2148 | ||
2149 | DISAS_INSN(exg_aa) | |
2150 | { | |
2151 | /* exchange Dx and Dy */ | |
2152 | do_exg(DREG(insn, 9), DREG(insn, 0)); | |
2153 | } | |
2154 | ||
2155 | DISAS_INSN(exg_dd) | |
2156 | { | |
2157 | /* exchange Ax and Ay */ | |
2158 | do_exg(AREG(insn, 9), AREG(insn, 0)); | |
2159 | } | |
2160 | ||
2161 | DISAS_INSN(exg_da) | |
2162 | { | |
2163 | /* exchange Dx and Ay */ | |
2164 | do_exg(DREG(insn, 9), AREG(insn, 0)); | |
2165 | } | |
2166 | ||
e6e5906b PB |
2167 | DISAS_INSN(and) |
2168 | { | |
e1f3808e PB |
2169 | TCGv src; |
2170 | TCGv reg; | |
2171 | TCGv dest; | |
2172 | TCGv addr; | |
e6e5906b PB |
2173 | |
2174 | reg = DREG(insn, 9); | |
a7812ae4 | 2175 | dest = tcg_temp_new(); |
e6e5906b | 2176 | if (insn & 0x100) { |
d4d79bb1 | 2177 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 2178 | tcg_gen_and_i32(dest, src, reg); |
d4d79bb1 | 2179 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 2180 | } else { |
d4d79bb1 | 2181 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
2182 | tcg_gen_and_i32(dest, src, reg); |
2183 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b | 2184 | } |
5dbb6784 | 2185 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
2186 | } |
2187 | ||
2188 | DISAS_INSN(adda) | |
2189 | { | |
e1f3808e PB |
2190 | TCGv src; |
2191 | TCGv reg; | |
e6e5906b | 2192 | |
d4d79bb1 | 2193 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 2194 | reg = AREG(insn, 9); |
e1f3808e | 2195 | tcg_gen_add_i32(reg, reg, src); |
e6e5906b PB |
2196 | } |
2197 | ||
a665a820 | 2198 | static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize) |
e6e5906b | 2199 | { |
a665a820 RH |
2200 | TCGv tmp; |
2201 | ||
2202 | gen_flush_flags(s); /* compute old Z */ | |
2203 | ||
2204 | /* Perform addition with carry. | |
2205 | * (X, N) = src + dest + X; | |
2206 | */ | |
2207 | ||
2208 | tmp = tcg_const_i32(0); | |
2209 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp); | |
2210 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp); | |
2211 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
2212 | ||
2213 | /* Compute signed-overflow for addition. */ | |
2214 | ||
2215 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); | |
2216 | tcg_gen_xor_i32(tmp, dest, src); | |
2217 | tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp); | |
2218 | tcg_temp_free(tmp); | |
2219 | ||
2220 | /* Copy the rest of the results into place. */ | |
2221 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ | |
2222 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
2223 | ||
2224 | set_cc_op(s, CC_OP_FLAGS); | |
2225 | ||
2226 | /* result is in QREG_CC_N */ | |
2227 | } | |
2228 | ||
2229 | DISAS_INSN(addx_reg) | |
2230 | { | |
2231 | TCGv dest; | |
e1f3808e | 2232 | TCGv src; |
a665a820 | 2233 | int opsize; |
e6e5906b | 2234 | |
a665a820 RH |
2235 | opsize = insn_opsize(insn); |
2236 | ||
2237 | dest = gen_extend(DREG(insn, 9), opsize, 1); | |
2238 | src = gen_extend(DREG(insn, 0), opsize, 1); | |
2239 | ||
2240 | gen_addx(s, src, dest, opsize); | |
2241 | ||
2242 | gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N); | |
2243 | } | |
2244 | ||
2245 | DISAS_INSN(addx_mem) | |
2246 | { | |
2247 | TCGv src; | |
2248 | TCGv addr_src; | |
2249 | TCGv dest; | |
2250 | TCGv addr_dest; | |
2251 | int opsize; | |
2252 | ||
2253 | opsize = insn_opsize(insn); | |
2254 | ||
2255 | addr_src = AREG(insn, 0); | |
2256 | tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize)); | |
2257 | src = gen_load(s, opsize, addr_src, 1); | |
2258 | ||
2259 | addr_dest = AREG(insn, 9); | |
2260 | tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize)); | |
2261 | dest = gen_load(s, opsize, addr_dest, 1); | |
2262 | ||
2263 | gen_addx(s, src, dest, opsize); | |
2264 | ||
2265 | gen_store(s, opsize, addr_dest, QREG_CC_N); | |
e6e5906b PB |
2266 | } |
2267 | ||
e1f3808e | 2268 | /* TODO: This could be implemented without helper functions. */ |
e6e5906b PB |
2269 | DISAS_INSN(shift_im) |
2270 | { | |
e1f3808e | 2271 | TCGv reg; |
e6e5906b | 2272 | int tmp; |
e1f3808e | 2273 | TCGv shift; |
e6e5906b | 2274 | |
620c6cf6 RH |
2275 | set_cc_op(s, CC_OP_FLAGS); |
2276 | ||
e6e5906b PB |
2277 | reg = DREG(insn, 0); |
2278 | tmp = (insn >> 9) & 7; | |
2279 | if (tmp == 0) | |
e1f3808e | 2280 | tmp = 8; |
351326a6 | 2281 | shift = tcg_const_i32(tmp); |
e1f3808e | 2282 | /* No need to flush flags becuse we know we will set C flag. */ |
e6e5906b | 2283 | if (insn & 0x100) { |
e1f3808e | 2284 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
2285 | } else { |
2286 | if (insn & 8) { | |
e1f3808e | 2287 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 2288 | } else { |
e1f3808e | 2289 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
2290 | } |
2291 | } | |
2292 | } | |
2293 | ||
2294 | DISAS_INSN(shift_reg) | |
2295 | { | |
e1f3808e PB |
2296 | TCGv reg; |
2297 | TCGv shift; | |
e6e5906b PB |
2298 | |
2299 | reg = DREG(insn, 0); | |
e1f3808e | 2300 | shift = DREG(insn, 9); |
e6e5906b | 2301 | if (insn & 0x100) { |
e1f3808e | 2302 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
2303 | } else { |
2304 | if (insn & 8) { | |
e1f3808e | 2305 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 2306 | } else { |
e1f3808e | 2307 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
2308 | } |
2309 | } | |
620c6cf6 | 2310 | set_cc_op(s, CC_OP_FLAGS); |
e6e5906b PB |
2311 | } |
2312 | ||
2313 | DISAS_INSN(ff1) | |
2314 | { | |
e1f3808e | 2315 | TCGv reg; |
821f7e76 | 2316 | reg = DREG(insn, 0); |
5dbb6784 | 2317 | gen_logic_cc(s, reg, OS_LONG); |
e1f3808e | 2318 | gen_helper_ff1(reg, reg); |
e6e5906b PB |
2319 | } |
2320 | ||
e1f3808e | 2321 | static TCGv gen_get_sr(DisasContext *s) |
0633879f | 2322 | { |
e1f3808e PB |
2323 | TCGv ccr; |
2324 | TCGv sr; | |
0633879f PB |
2325 | |
2326 | ccr = gen_get_ccr(s); | |
a7812ae4 | 2327 | sr = tcg_temp_new(); |
e1f3808e PB |
2328 | tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); |
2329 | tcg_gen_or_i32(sr, sr, ccr); | |
0633879f PB |
2330 | return sr; |
2331 | } | |
2332 | ||
e6e5906b PB |
2333 | DISAS_INSN(strldsr) |
2334 | { | |
2335 | uint16_t ext; | |
2336 | uint32_t addr; | |
2337 | ||
2338 | addr = s->pc - 2; | |
28b68cd7 | 2339 | ext = read_im16(env, s); |
0633879f | 2340 | if (ext != 0x46FC) { |
e6e5906b | 2341 | gen_exception(s, addr, EXCP_UNSUPPORTED); |
0633879f PB |
2342 | return; |
2343 | } | |
28b68cd7 | 2344 | ext = read_im16(env, s); |
0633879f | 2345 | if (IS_USER(s) || (ext & SR_S) == 0) { |
e6e5906b | 2346 | gen_exception(s, addr, EXCP_PRIVILEGE); |
0633879f PB |
2347 | return; |
2348 | } | |
2349 | gen_push(s, gen_get_sr(s)); | |
2350 | gen_set_sr_im(s, ext, 0); | |
e6e5906b PB |
2351 | } |
2352 | ||
2353 | DISAS_INSN(move_from_sr) | |
2354 | { | |
e1f3808e | 2355 | TCGv sr; |
0633879f | 2356 | |
7c0eb318 | 2357 | if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) { |
0633879f PB |
2358 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); |
2359 | return; | |
2360 | } | |
2361 | sr = gen_get_sr(s); | |
7c0eb318 | 2362 | DEST_EA(env, insn, OS_WORD, sr, NULL); |
e6e5906b PB |
2363 | } |
2364 | ||
2365 | DISAS_INSN(move_to_sr) | |
2366 | { | |
0633879f PB |
2367 | if (IS_USER(s)) { |
2368 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2369 | return; | |
2370 | } | |
620c6cf6 | 2371 | gen_set_sr(env, s, insn, 0); |
0633879f | 2372 | gen_lookup_tb(s); |
e6e5906b PB |
2373 | } |
2374 | ||
2375 | DISAS_INSN(move_from_usp) | |
2376 | { | |
0633879f PB |
2377 | if (IS_USER(s)) { |
2378 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2379 | return; | |
2380 | } | |
2a8327e8 GU |
2381 | tcg_gen_ld_i32(AREG(insn, 0), cpu_env, |
2382 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2383 | } |
2384 | ||
2385 | DISAS_INSN(move_to_usp) | |
2386 | { | |
0633879f PB |
2387 | if (IS_USER(s)) { |
2388 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2389 | return; | |
2390 | } | |
2a8327e8 GU |
2391 | tcg_gen_st_i32(AREG(insn, 0), cpu_env, |
2392 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2393 | } |
2394 | ||
2395 | DISAS_INSN(halt) | |
2396 | { | |
e1f3808e | 2397 | gen_exception(s, s->pc, EXCP_HALT_INSN); |
e6e5906b PB |
2398 | } |
2399 | ||
2400 | DISAS_INSN(stop) | |
2401 | { | |
0633879f PB |
2402 | uint16_t ext; |
2403 | ||
2404 | if (IS_USER(s)) { | |
2405 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2406 | return; | |
2407 | } | |
2408 | ||
28b68cd7 | 2409 | ext = read_im16(env, s); |
0633879f PB |
2410 | |
2411 | gen_set_sr_im(s, ext, 0); | |
259186a7 | 2412 | tcg_gen_movi_i32(cpu_halted, 1); |
e1f3808e | 2413 | gen_exception(s, s->pc, EXCP_HLT); |
e6e5906b PB |
2414 | } |
2415 | ||
2416 | DISAS_INSN(rte) | |
2417 | { | |
0633879f PB |
2418 | if (IS_USER(s)) { |
2419 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2420 | return; | |
2421 | } | |
2422 | gen_exception(s, s->pc - 2, EXCP_RTE); | |
e6e5906b PB |
2423 | } |
2424 | ||
2425 | DISAS_INSN(movec) | |
2426 | { | |
0633879f | 2427 | uint16_t ext; |
e1f3808e | 2428 | TCGv reg; |
0633879f PB |
2429 | |
2430 | if (IS_USER(s)) { | |
2431 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2432 | return; | |
2433 | } | |
2434 | ||
28b68cd7 | 2435 | ext = read_im16(env, s); |
0633879f PB |
2436 | |
2437 | if (ext & 0x8000) { | |
2438 | reg = AREG(ext, 12); | |
2439 | } else { | |
2440 | reg = DREG(ext, 12); | |
2441 | } | |
e1f3808e | 2442 | gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); |
0633879f | 2443 | gen_lookup_tb(s); |
e6e5906b PB |
2444 | } |
2445 | ||
2446 | DISAS_INSN(intouch) | |
2447 | { | |
0633879f PB |
2448 | if (IS_USER(s)) { |
2449 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2450 | return; | |
2451 | } | |
2452 | /* ICache fetch. Implement as no-op. */ | |
e6e5906b PB |
2453 | } |
2454 | ||
2455 | DISAS_INSN(cpushl) | |
2456 | { | |
0633879f PB |
2457 | if (IS_USER(s)) { |
2458 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2459 | return; | |
2460 | } | |
2461 | /* Cache push/invalidate. Implement as no-op. */ | |
e6e5906b PB |
2462 | } |
2463 | ||
2464 | DISAS_INSN(wddata) | |
2465 | { | |
2466 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2467 | } | |
2468 | ||
2469 | DISAS_INSN(wdebug) | |
2470 | { | |
a47dddd7 AF |
2471 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2472 | ||
0633879f PB |
2473 | if (IS_USER(s)) { |
2474 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2475 | return; | |
2476 | } | |
2477 | /* TODO: Implement wdebug. */ | |
a47dddd7 | 2478 | cpu_abort(CPU(cpu), "WDEBUG not implemented"); |
e6e5906b PB |
2479 | } |
2480 | ||
2481 | DISAS_INSN(trap) | |
2482 | { | |
2483 | gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); | |
2484 | } | |
2485 | ||
2486 | /* ??? FP exceptions are not implemented. Most exceptions are deferred until | |
2487 | immediately before the next FP instruction is executed. */ | |
2488 | DISAS_INSN(fpu) | |
2489 | { | |
2490 | uint16_t ext; | |
a7812ae4 | 2491 | int32_t offset; |
e6e5906b | 2492 | int opmode; |
a7812ae4 PB |
2493 | TCGv_i64 src; |
2494 | TCGv_i64 dest; | |
2495 | TCGv_i64 res; | |
2496 | TCGv tmp32; | |
e6e5906b | 2497 | int round; |
a7812ae4 | 2498 | int set_dest; |
e6e5906b PB |
2499 | int opsize; |
2500 | ||
28b68cd7 | 2501 | ext = read_im16(env, s); |
e6e5906b PB |
2502 | opmode = ext & 0x7f; |
2503 | switch ((ext >> 13) & 7) { | |
2504 | case 0: case 2: | |
2505 | break; | |
2506 | case 1: | |
2507 | goto undef; | |
2508 | case 3: /* fmove out */ | |
2509 | src = FREG(ext, 7); | |
a7812ae4 | 2510 | tmp32 = tcg_temp_new_i32(); |
e6e5906b PB |
2511 | /* fmove */ |
2512 | /* ??? TODO: Proper behavior on overflow. */ | |
2513 | switch ((ext >> 10) & 7) { | |
2514 | case 0: | |
2515 | opsize = OS_LONG; | |
a7812ae4 | 2516 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2517 | break; |
2518 | case 1: | |
2519 | opsize = OS_SINGLE; | |
a7812ae4 | 2520 | gen_helper_f64_to_f32(tmp32, cpu_env, src); |
e6e5906b PB |
2521 | break; |
2522 | case 4: | |
2523 | opsize = OS_WORD; | |
a7812ae4 | 2524 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b | 2525 | break; |
a7812ae4 PB |
2526 | case 5: /* OS_DOUBLE */ |
2527 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2528 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2529 | case 2: |
2530 | case 3: | |
243ee8f7 | 2531 | break; |
a7812ae4 PB |
2532 | case 4: |
2533 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2534 | break; | |
2535 | case 5: | |
d4d79bb1 | 2536 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2537 | s->pc += 2; |
2538 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2539 | break; | |
2540 | default: | |
2541 | goto undef; | |
2542 | } | |
2543 | gen_store64(s, tmp32, src); | |
c59b97aa | 2544 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2545 | case 3: |
2546 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2547 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2548 | break; | |
2549 | case 4: | |
2550 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2551 | break; | |
2552 | } | |
2553 | tcg_temp_free_i32(tmp32); | |
2554 | return; | |
e6e5906b PB |
2555 | case 6: |
2556 | opsize = OS_BYTE; | |
a7812ae4 | 2557 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2558 | break; |
2559 | default: | |
2560 | goto undef; | |
2561 | } | |
d4d79bb1 | 2562 | DEST_EA(env, insn, opsize, tmp32, NULL); |
a7812ae4 | 2563 | tcg_temp_free_i32(tmp32); |
e6e5906b PB |
2564 | return; |
2565 | case 4: /* fmove to control register. */ | |
2566 | switch ((ext >> 10) & 7) { | |
2567 | case 4: /* FPCR */ | |
2568 | /* Not implemented. Ignore writes. */ | |
2569 | break; | |
2570 | case 1: /* FPIAR */ | |
2571 | case 2: /* FPSR */ | |
2572 | default: | |
2573 | cpu_abort(NULL, "Unimplemented: fmove to control %d", | |
2574 | (ext >> 10) & 7); | |
2575 | } | |
2576 | break; | |
2577 | case 5: /* fmove from control register. */ | |
2578 | switch ((ext >> 10) & 7) { | |
2579 | case 4: /* FPCR */ | |
2580 | /* Not implemented. Always return zero. */ | |
351326a6 | 2581 | tmp32 = tcg_const_i32(0); |
e6e5906b PB |
2582 | break; |
2583 | case 1: /* FPIAR */ | |
2584 | case 2: /* FPSR */ | |
2585 | default: | |
2586 | cpu_abort(NULL, "Unimplemented: fmove from control %d", | |
2587 | (ext >> 10) & 7); | |
2588 | goto undef; | |
2589 | } | |
d4d79bb1 | 2590 | DEST_EA(env, insn, OS_LONG, tmp32, NULL); |
e6e5906b | 2591 | break; |
5fafdf24 | 2592 | case 6: /* fmovem */ |
e6e5906b PB |
2593 | case 7: |
2594 | { | |
e1f3808e PB |
2595 | TCGv addr; |
2596 | uint16_t mask; | |
2597 | int i; | |
2598 | if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) | |
2599 | goto undef; | |
d4d79bb1 | 2600 | tmp32 = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2601 | if (IS_NULL_QREG(tmp32)) { |
e1f3808e PB |
2602 | gen_addr_fault(s); |
2603 | return; | |
2604 | } | |
a7812ae4 PB |
2605 | addr = tcg_temp_new_i32(); |
2606 | tcg_gen_mov_i32(addr, tmp32); | |
e1f3808e PB |
2607 | mask = 0x80; |
2608 | for (i = 0; i < 8; i++) { | |
2609 | if (ext & mask) { | |
e1f3808e PB |
2610 | dest = FREG(i, 0); |
2611 | if (ext & (1 << 13)) { | |
2612 | /* store */ | |
2613 | tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); | |
2614 | } else { | |
2615 | /* load */ | |
2616 | tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); | |
2617 | } | |
2618 | if (ext & (mask - 1)) | |
2619 | tcg_gen_addi_i32(addr, addr, 8); | |
e6e5906b | 2620 | } |
e1f3808e | 2621 | mask >>= 1; |
e6e5906b | 2622 | } |
18307f26 | 2623 | tcg_temp_free_i32(addr); |
e6e5906b PB |
2624 | } |
2625 | return; | |
2626 | } | |
2627 | if (ext & (1 << 14)) { | |
e6e5906b PB |
2628 | /* Source effective address. */ |
2629 | switch ((ext >> 10) & 7) { | |
2630 | case 0: opsize = OS_LONG; break; | |
2631 | case 1: opsize = OS_SINGLE; break; | |
2632 | case 4: opsize = OS_WORD; break; | |
2633 | case 5: opsize = OS_DOUBLE; break; | |
2634 | case 6: opsize = OS_BYTE; break; | |
2635 | default: | |
2636 | goto undef; | |
2637 | } | |
e6e5906b | 2638 | if (opsize == OS_DOUBLE) { |
a7812ae4 PB |
2639 | tmp32 = tcg_temp_new_i32(); |
2640 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2641 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2642 | case 2: |
2643 | case 3: | |
243ee8f7 | 2644 | break; |
a7812ae4 PB |
2645 | case 4: |
2646 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2647 | break; | |
2648 | case 5: | |
d4d79bb1 | 2649 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2650 | s->pc += 2; |
2651 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2652 | break; | |
2653 | case 7: | |
d4d79bb1 | 2654 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2655 | offset += s->pc - 2; |
2656 | s->pc += 2; | |
2657 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2658 | break; | |
2659 | default: | |
2660 | goto undef; | |
2661 | } | |
2662 | src = gen_load64(s, tmp32); | |
c59b97aa | 2663 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2664 | case 3: |
2665 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2666 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2667 | break; | |
2668 | case 4: | |
2669 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2670 | break; | |
2671 | } | |
2672 | tcg_temp_free_i32(tmp32); | |
e6e5906b | 2673 | } else { |
d4d79bb1 | 2674 | SRC_EA(env, tmp32, opsize, 1, NULL); |
a7812ae4 | 2675 | src = tcg_temp_new_i64(); |
e6e5906b PB |
2676 | switch (opsize) { |
2677 | case OS_LONG: | |
2678 | case OS_WORD: | |
2679 | case OS_BYTE: | |
a7812ae4 | 2680 | gen_helper_i32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2681 | break; |
2682 | case OS_SINGLE: | |
a7812ae4 | 2683 | gen_helper_f32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2684 | break; |
2685 | } | |
2686 | } | |
2687 | } else { | |
2688 | /* Source register. */ | |
2689 | src = FREG(ext, 10); | |
2690 | } | |
2691 | dest = FREG(ext, 7); | |
a7812ae4 | 2692 | res = tcg_temp_new_i64(); |
e6e5906b | 2693 | if (opmode != 0x3a) |
e1f3808e | 2694 | tcg_gen_mov_f64(res, dest); |
e6e5906b | 2695 | round = 1; |
a7812ae4 | 2696 | set_dest = 1; |
e6e5906b PB |
2697 | switch (opmode) { |
2698 | case 0: case 0x40: case 0x44: /* fmove */ | |
e1f3808e | 2699 | tcg_gen_mov_f64(res, src); |
e6e5906b PB |
2700 | break; |
2701 | case 1: /* fint */ | |
e1f3808e | 2702 | gen_helper_iround_f64(res, cpu_env, src); |
e6e5906b PB |
2703 | round = 0; |
2704 | break; | |
2705 | case 3: /* fintrz */ | |
e1f3808e | 2706 | gen_helper_itrunc_f64(res, cpu_env, src); |
e6e5906b PB |
2707 | round = 0; |
2708 | break; | |
2709 | case 4: case 0x41: case 0x45: /* fsqrt */ | |
e1f3808e | 2710 | gen_helper_sqrt_f64(res, cpu_env, src); |
e6e5906b PB |
2711 | break; |
2712 | case 0x18: case 0x58: case 0x5c: /* fabs */ | |
e1f3808e | 2713 | gen_helper_abs_f64(res, src); |
e6e5906b PB |
2714 | break; |
2715 | case 0x1a: case 0x5a: case 0x5e: /* fneg */ | |
e1f3808e | 2716 | gen_helper_chs_f64(res, src); |
e6e5906b PB |
2717 | break; |
2718 | case 0x20: case 0x60: case 0x64: /* fdiv */ | |
e1f3808e | 2719 | gen_helper_div_f64(res, cpu_env, res, src); |
e6e5906b PB |
2720 | break; |
2721 | case 0x22: case 0x62: case 0x66: /* fadd */ | |
e1f3808e | 2722 | gen_helper_add_f64(res, cpu_env, res, src); |
e6e5906b PB |
2723 | break; |
2724 | case 0x23: case 0x63: case 0x67: /* fmul */ | |
e1f3808e | 2725 | gen_helper_mul_f64(res, cpu_env, res, src); |
e6e5906b PB |
2726 | break; |
2727 | case 0x28: case 0x68: case 0x6c: /* fsub */ | |
e1f3808e | 2728 | gen_helper_sub_f64(res, cpu_env, res, src); |
e6e5906b PB |
2729 | break; |
2730 | case 0x38: /* fcmp */ | |
e1f3808e | 2731 | gen_helper_sub_cmp_f64(res, cpu_env, res, src); |
a7812ae4 | 2732 | set_dest = 0; |
e6e5906b PB |
2733 | round = 0; |
2734 | break; | |
2735 | case 0x3a: /* ftst */ | |
e1f3808e | 2736 | tcg_gen_mov_f64(res, src); |
a7812ae4 | 2737 | set_dest = 0; |
e6e5906b PB |
2738 | round = 0; |
2739 | break; | |
2740 | default: | |
2741 | goto undef; | |
2742 | } | |
a7812ae4 PB |
2743 | if (ext & (1 << 14)) { |
2744 | tcg_temp_free_i64(src); | |
2745 | } | |
e6e5906b PB |
2746 | if (round) { |
2747 | if (opmode & 0x40) { | |
2748 | if ((opmode & 0x4) != 0) | |
2749 | round = 0; | |
2750 | } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { | |
2751 | round = 0; | |
2752 | } | |
2753 | } | |
2754 | if (round) { | |
a7812ae4 | 2755 | TCGv tmp = tcg_temp_new_i32(); |
e1f3808e PB |
2756 | gen_helper_f64_to_f32(tmp, cpu_env, res); |
2757 | gen_helper_f32_to_f64(res, cpu_env, tmp); | |
a7812ae4 | 2758 | tcg_temp_free_i32(tmp); |
5fafdf24 | 2759 | } |
e1f3808e | 2760 | tcg_gen_mov_f64(QREG_FP_RESULT, res); |
a7812ae4 | 2761 | if (set_dest) { |
e1f3808e | 2762 | tcg_gen_mov_f64(dest, res); |
e6e5906b | 2763 | } |
a7812ae4 | 2764 | tcg_temp_free_i64(res); |
e6e5906b PB |
2765 | return; |
2766 | undef: | |
a7812ae4 | 2767 | /* FIXME: Is this right for offset addressing modes? */ |
e6e5906b | 2768 | s->pc -= 2; |
d4d79bb1 | 2769 | disas_undef_fpu(env, s, insn); |
e6e5906b PB |
2770 | } |
2771 | ||
2772 | DISAS_INSN(fbcc) | |
2773 | { | |
2774 | uint32_t offset; | |
2775 | uint32_t addr; | |
e1f3808e | 2776 | TCGv flag; |
42a268c2 | 2777 | TCGLabel *l1; |
e6e5906b PB |
2778 | |
2779 | addr = s->pc; | |
d4d79bb1 | 2780 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
2781 | s->pc += 2; |
2782 | if (insn & (1 << 6)) { | |
28b68cd7 | 2783 | offset = (offset << 16) | read_im16(env, s); |
e6e5906b PB |
2784 | } |
2785 | ||
2786 | l1 = gen_new_label(); | |
2787 | /* TODO: Raise BSUN exception. */ | |
a7812ae4 | 2788 | flag = tcg_temp_new(); |
e1f3808e | 2789 | gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); |
e6e5906b PB |
2790 | /* Jump to l1 if condition is true. */ |
2791 | switch (insn & 0xf) { | |
2792 | case 0: /* f */ | |
2793 | break; | |
2794 | case 1: /* eq (=0) */ | |
e1f3808e | 2795 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2796 | break; |
2797 | case 2: /* ogt (=1) */ | |
e1f3808e | 2798 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2799 | break; |
2800 | case 3: /* oge (=0 or =1) */ | |
e1f3808e | 2801 | tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2802 | break; |
2803 | case 4: /* olt (=-1) */ | |
e1f3808e | 2804 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2805 | break; |
2806 | case 5: /* ole (=-1 or =0) */ | |
e1f3808e | 2807 | tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2808 | break; |
2809 | case 6: /* ogl (=-1 or =1) */ | |
e1f3808e PB |
2810 | tcg_gen_andi_i32(flag, flag, 1); |
2811 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2812 | break; |
2813 | case 7: /* or (=2) */ | |
e1f3808e | 2814 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2815 | break; |
2816 | case 8: /* un (<2) */ | |
e1f3808e | 2817 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2818 | break; |
2819 | case 9: /* ueq (=0 or =2) */ | |
e1f3808e PB |
2820 | tcg_gen_andi_i32(flag, flag, 1); |
2821 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2822 | break; |
2823 | case 10: /* ugt (>0) */ | |
e1f3808e | 2824 | tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2825 | break; |
2826 | case 11: /* uge (>=0) */ | |
e1f3808e | 2827 | tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2828 | break; |
2829 | case 12: /* ult (=-1 or =2) */ | |
e1f3808e | 2830 | tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2831 | break; |
2832 | case 13: /* ule (!=1) */ | |
e1f3808e | 2833 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2834 | break; |
2835 | case 14: /* ne (!=0) */ | |
e1f3808e | 2836 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2837 | break; |
2838 | case 15: /* t */ | |
e1f3808e | 2839 | tcg_gen_br(l1); |
e6e5906b PB |
2840 | break; |
2841 | } | |
2842 | gen_jmp_tb(s, 0, s->pc); | |
2843 | gen_set_label(l1); | |
2844 | gen_jmp_tb(s, 1, addr + offset); | |
2845 | } | |
2846 | ||
0633879f PB |
2847 | DISAS_INSN(frestore) |
2848 | { | |
a47dddd7 AF |
2849 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2850 | ||
0633879f | 2851 | /* TODO: Implement frestore. */ |
a47dddd7 | 2852 | cpu_abort(CPU(cpu), "FRESTORE not implemented"); |
0633879f PB |
2853 | } |
2854 | ||
2855 | DISAS_INSN(fsave) | |
2856 | { | |
a47dddd7 AF |
2857 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2858 | ||
0633879f | 2859 | /* TODO: Implement fsave. */ |
a47dddd7 | 2860 | cpu_abort(CPU(cpu), "FSAVE not implemented"); |
0633879f PB |
2861 | } |
2862 | ||
e1f3808e | 2863 | static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) |
acf930aa | 2864 | { |
a7812ae4 | 2865 | TCGv tmp = tcg_temp_new(); |
acf930aa PB |
2866 | if (s->env->macsr & MACSR_FI) { |
2867 | if (upper) | |
e1f3808e | 2868 | tcg_gen_andi_i32(tmp, val, 0xffff0000); |
acf930aa | 2869 | else |
e1f3808e | 2870 | tcg_gen_shli_i32(tmp, val, 16); |
acf930aa PB |
2871 | } else if (s->env->macsr & MACSR_SU) { |
2872 | if (upper) | |
e1f3808e | 2873 | tcg_gen_sari_i32(tmp, val, 16); |
acf930aa | 2874 | else |
e1f3808e | 2875 | tcg_gen_ext16s_i32(tmp, val); |
acf930aa PB |
2876 | } else { |
2877 | if (upper) | |
e1f3808e | 2878 | tcg_gen_shri_i32(tmp, val, 16); |
acf930aa | 2879 | else |
e1f3808e | 2880 | tcg_gen_ext16u_i32(tmp, val); |
acf930aa PB |
2881 | } |
2882 | return tmp; | |
2883 | } | |
2884 | ||
e1f3808e PB |
2885 | static void gen_mac_clear_flags(void) |
2886 | { | |
2887 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, | |
2888 | ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); | |
2889 | } | |
2890 | ||
acf930aa PB |
2891 | DISAS_INSN(mac) |
2892 | { | |
e1f3808e PB |
2893 | TCGv rx; |
2894 | TCGv ry; | |
acf930aa PB |
2895 | uint16_t ext; |
2896 | int acc; | |
e1f3808e PB |
2897 | TCGv tmp; |
2898 | TCGv addr; | |
2899 | TCGv loadval; | |
acf930aa | 2900 | int dual; |
e1f3808e PB |
2901 | TCGv saved_flags; |
2902 | ||
a7812ae4 PB |
2903 | if (!s->done_mac) { |
2904 | s->mactmp = tcg_temp_new_i64(); | |
2905 | s->done_mac = 1; | |
2906 | } | |
acf930aa | 2907 | |
28b68cd7 | 2908 | ext = read_im16(env, s); |
acf930aa PB |
2909 | |
2910 | acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); | |
2911 | dual = ((insn & 0x30) != 0 && (ext & 3) != 0); | |
d315c888 | 2912 | if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { |
d4d79bb1 | 2913 | disas_undef(env, s, insn); |
d315c888 PB |
2914 | return; |
2915 | } | |
acf930aa PB |
2916 | if (insn & 0x30) { |
2917 | /* MAC with load. */ | |
d4d79bb1 | 2918 | tmp = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2919 | addr = tcg_temp_new(); |
e1f3808e | 2920 | tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); |
acf930aa PB |
2921 | /* Load the value now to ensure correct exception behavior. |
2922 | Perform writeback after reading the MAC inputs. */ | |
2923 | loadval = gen_load(s, OS_LONG, addr, 0); | |
2924 | ||
2925 | acc ^= 1; | |
2926 | rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); | |
2927 | ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); | |
2928 | } else { | |
e1f3808e | 2929 | loadval = addr = NULL_QREG; |
acf930aa PB |
2930 | rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
2931 | ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
2932 | } | |
2933 | ||
e1f3808e PB |
2934 | gen_mac_clear_flags(); |
2935 | #if 0 | |
acf930aa | 2936 | l1 = -1; |
e1f3808e | 2937 | /* Disabled because conditional branches clobber temporary vars. */ |
acf930aa PB |
2938 | if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { |
2939 | /* Skip the multiply if we know we will ignore it. */ | |
2940 | l1 = gen_new_label(); | |
a7812ae4 | 2941 | tmp = tcg_temp_new(); |
e1f3808e | 2942 | tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); |
acf930aa PB |
2943 | gen_op_jmp_nz32(tmp, l1); |
2944 | } | |
e1f3808e | 2945 | #endif |
acf930aa PB |
2946 | |
2947 | if ((ext & 0x0800) == 0) { | |
2948 | /* Word. */ | |
2949 | rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); | |
2950 | ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); | |
2951 | } | |
2952 | if (s->env->macsr & MACSR_FI) { | |
e1f3808e | 2953 | gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2954 | } else { |
2955 | if (s->env->macsr & MACSR_SU) | |
e1f3808e | 2956 | gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); |
acf930aa | 2957 | else |
e1f3808e | 2958 | gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2959 | switch ((ext >> 9) & 3) { |
2960 | case 1: | |
e1f3808e | 2961 | tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2962 | break; |
2963 | case 3: | |
e1f3808e | 2964 | tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2965 | break; |
2966 | } | |
2967 | } | |
2968 | ||
2969 | if (dual) { | |
2970 | /* Save the overflow flag from the multiply. */ | |
a7812ae4 | 2971 | saved_flags = tcg_temp_new(); |
e1f3808e PB |
2972 | tcg_gen_mov_i32(saved_flags, QREG_MACSR); |
2973 | } else { | |
2974 | saved_flags = NULL_QREG; | |
acf930aa PB |
2975 | } |
2976 | ||
e1f3808e PB |
2977 | #if 0 |
2978 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2979 | if ((s->env->macsr & MACSR_OMC) != 0 && dual) { |
2980 | /* Skip the accumulate if the value is already saturated. */ | |
2981 | l1 = gen_new_label(); | |
a7812ae4 | 2982 | tmp = tcg_temp_new(); |
351326a6 | 2983 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2984 | gen_op_jmp_nz32(tmp, l1); |
2985 | } | |
e1f3808e | 2986 | #endif |
acf930aa PB |
2987 | |
2988 | if (insn & 0x100) | |
e1f3808e | 2989 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2990 | else |
e1f3808e | 2991 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa PB |
2992 | |
2993 | if (s->env->macsr & MACSR_FI) | |
e1f3808e | 2994 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2995 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2996 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2997 | else |
e1f3808e | 2998 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2999 | |
e1f3808e PB |
3000 | #if 0 |
3001 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
3002 | if (l1 != -1) |
3003 | gen_set_label(l1); | |
e1f3808e | 3004 | #endif |
acf930aa PB |
3005 | |
3006 | if (dual) { | |
3007 | /* Dual accumulate variant. */ | |
3008 | acc = (ext >> 2) & 3; | |
3009 | /* Restore the overflow flag from the multiplier. */ | |
e1f3808e PB |
3010 | tcg_gen_mov_i32(QREG_MACSR, saved_flags); |
3011 | #if 0 | |
3012 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
3013 | if ((s->env->macsr & MACSR_OMC) != 0) { |
3014 | /* Skip the accumulate if the value is already saturated. */ | |
3015 | l1 = gen_new_label(); | |
a7812ae4 | 3016 | tmp = tcg_temp_new(); |
351326a6 | 3017 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
3018 | gen_op_jmp_nz32(tmp, l1); |
3019 | } | |
e1f3808e | 3020 | #endif |
acf930aa | 3021 | if (ext & 2) |
e1f3808e | 3022 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 3023 | else |
e1f3808e | 3024 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 3025 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 3026 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 3027 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 3028 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 3029 | else |
e1f3808e PB |
3030 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
3031 | #if 0 | |
3032 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
3033 | if (l1 != -1) |
3034 | gen_set_label(l1); | |
e1f3808e | 3035 | #endif |
acf930aa | 3036 | } |
e1f3808e | 3037 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); |
acf930aa PB |
3038 | |
3039 | if (insn & 0x30) { | |
e1f3808e | 3040 | TCGv rw; |
acf930aa | 3041 | rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
e1f3808e | 3042 | tcg_gen_mov_i32(rw, loadval); |
acf930aa PB |
3043 | /* FIXME: Should address writeback happen with the masked or |
3044 | unmasked value? */ | |
3045 | switch ((insn >> 3) & 7) { | |
3046 | case 3: /* Post-increment. */ | |
e1f3808e | 3047 | tcg_gen_addi_i32(AREG(insn, 0), addr, 4); |
acf930aa PB |
3048 | break; |
3049 | case 4: /* Pre-decrement. */ | |
e1f3808e | 3050 | tcg_gen_mov_i32(AREG(insn, 0), addr); |
acf930aa PB |
3051 | } |
3052 | } | |
3053 | } | |
3054 | ||
3055 | DISAS_INSN(from_mac) | |
3056 | { | |
e1f3808e | 3057 | TCGv rx; |
a7812ae4 | 3058 | TCGv_i64 acc; |
e1f3808e | 3059 | int accnum; |
acf930aa PB |
3060 | |
3061 | rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e PB |
3062 | accnum = (insn >> 9) & 3; |
3063 | acc = MACREG(accnum); | |
acf930aa | 3064 | if (s->env->macsr & MACSR_FI) { |
a7812ae4 | 3065 | gen_helper_get_macf(rx, cpu_env, acc); |
acf930aa | 3066 | } else if ((s->env->macsr & MACSR_OMC) == 0) { |
ecc7b3aa | 3067 | tcg_gen_extrl_i64_i32(rx, acc); |
acf930aa | 3068 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 3069 | gen_helper_get_macs(rx, acc); |
acf930aa | 3070 | } else { |
e1f3808e PB |
3071 | gen_helper_get_macu(rx, acc); |
3072 | } | |
3073 | if (insn & 0x40) { | |
3074 | tcg_gen_movi_i64(acc, 0); | |
3075 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
acf930aa | 3076 | } |
acf930aa PB |
3077 | } |
3078 | ||
3079 | DISAS_INSN(move_mac) | |
3080 | { | |
e1f3808e | 3081 | /* FIXME: This can be done without a helper. */ |
acf930aa | 3082 | int src; |
e1f3808e | 3083 | TCGv dest; |
acf930aa | 3084 | src = insn & 3; |
e1f3808e PB |
3085 | dest = tcg_const_i32((insn >> 9) & 3); |
3086 | gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); | |
3087 | gen_mac_clear_flags(); | |
3088 | gen_helper_mac_set_flags(cpu_env, dest); | |
acf930aa PB |
3089 | } |
3090 | ||
3091 | DISAS_INSN(from_macsr) | |
3092 | { | |
e1f3808e | 3093 | TCGv reg; |
acf930aa PB |
3094 | |
3095 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e | 3096 | tcg_gen_mov_i32(reg, QREG_MACSR); |
acf930aa PB |
3097 | } |
3098 | ||
3099 | DISAS_INSN(from_mask) | |
3100 | { | |
e1f3808e | 3101 | TCGv reg; |
acf930aa | 3102 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 3103 | tcg_gen_mov_i32(reg, QREG_MAC_MASK); |
acf930aa PB |
3104 | } |
3105 | ||
3106 | DISAS_INSN(from_mext) | |
3107 | { | |
e1f3808e PB |
3108 | TCGv reg; |
3109 | TCGv acc; | |
acf930aa | 3110 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 3111 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 3112 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 3113 | gen_helper_get_mac_extf(reg, cpu_env, acc); |
acf930aa | 3114 | else |
e1f3808e | 3115 | gen_helper_get_mac_exti(reg, cpu_env, acc); |
acf930aa PB |
3116 | } |
3117 | ||
3118 | DISAS_INSN(macsr_to_ccr) | |
3119 | { | |
620c6cf6 RH |
3120 | TCGv tmp = tcg_temp_new(); |
3121 | tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); | |
3122 | gen_helper_set_sr(cpu_env, tmp); | |
3123 | tcg_temp_free(tmp); | |
9fdb533f | 3124 | set_cc_op(s, CC_OP_FLAGS); |
acf930aa PB |
3125 | } |
3126 | ||
3127 | DISAS_INSN(to_mac) | |
3128 | { | |
a7812ae4 | 3129 | TCGv_i64 acc; |
e1f3808e PB |
3130 | TCGv val; |
3131 | int accnum; | |
3132 | accnum = (insn >> 9) & 3; | |
3133 | acc = MACREG(accnum); | |
d4d79bb1 | 3134 | SRC_EA(env, val, OS_LONG, 0, NULL); |
acf930aa | 3135 | if (s->env->macsr & MACSR_FI) { |
e1f3808e PB |
3136 | tcg_gen_ext_i32_i64(acc, val); |
3137 | tcg_gen_shli_i64(acc, acc, 8); | |
acf930aa | 3138 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 3139 | tcg_gen_ext_i32_i64(acc, val); |
acf930aa | 3140 | } else { |
e1f3808e | 3141 | tcg_gen_extu_i32_i64(acc, val); |
acf930aa | 3142 | } |
e1f3808e PB |
3143 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); |
3144 | gen_mac_clear_flags(); | |
3145 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); | |
acf930aa PB |
3146 | } |
3147 | ||
3148 | DISAS_INSN(to_macsr) | |
3149 | { | |
e1f3808e | 3150 | TCGv val; |
d4d79bb1 | 3151 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 3152 | gen_helper_set_macsr(cpu_env, val); |
acf930aa PB |
3153 | gen_lookup_tb(s); |
3154 | } | |
3155 | ||
3156 | DISAS_INSN(to_mask) | |
3157 | { | |
e1f3808e | 3158 | TCGv val; |
d4d79bb1 | 3159 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 3160 | tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); |
acf930aa PB |
3161 | } |
3162 | ||
3163 | DISAS_INSN(to_mext) | |
3164 | { | |
e1f3808e PB |
3165 | TCGv val; |
3166 | TCGv acc; | |
d4d79bb1 | 3167 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 3168 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 3169 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 3170 | gen_helper_set_mac_extf(cpu_env, val, acc); |
acf930aa | 3171 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 3172 | gen_helper_set_mac_exts(cpu_env, val, acc); |
acf930aa | 3173 | else |
e1f3808e | 3174 | gen_helper_set_mac_extu(cpu_env, val, acc); |
acf930aa PB |
3175 | } |
3176 | ||
e6e5906b PB |
3177 | static disas_proc opcode_table[65536]; |
3178 | ||
3179 | static void | |
3180 | register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) | |
3181 | { | |
3182 | int i; | |
3183 | int from; | |
3184 | int to; | |
3185 | ||
3186 | /* Sanity check. All set bits must be included in the mask. */ | |
5fc4adf6 PB |
3187 | if (opcode & ~mask) { |
3188 | fprintf(stderr, | |
3189 | "qemu internal error: bogus opcode definition %04x/%04x\n", | |
3190 | opcode, mask); | |
e6e5906b | 3191 | abort(); |
5fc4adf6 | 3192 | } |
e6e5906b PB |
3193 | /* This could probably be cleverer. For now just optimize the case where |
3194 | the top bits are known. */ | |
3195 | /* Find the first zero bit in the mask. */ | |
3196 | i = 0x8000; | |
3197 | while ((i & mask) != 0) | |
3198 | i >>= 1; | |
3199 | /* Iterate over all combinations of this and lower bits. */ | |
3200 | if (i == 0) | |
3201 | i = 1; | |
3202 | else | |
3203 | i <<= 1; | |
3204 | from = opcode & ~(i - 1); | |
3205 | to = from + i; | |
0633879f | 3206 | for (i = from; i < to; i++) { |
e6e5906b PB |
3207 | if ((i & mask) == opcode) |
3208 | opcode_table[i] = proc; | |
0633879f | 3209 | } |
e6e5906b PB |
3210 | } |
3211 | ||
3212 | /* Register m68k opcode handlers. Order is important. | |
3213 | Later insn override earlier ones. */ | |
0402f767 | 3214 | void register_m68k_insns (CPUM68KState *env) |
e6e5906b | 3215 | { |
b2085257 JPAG |
3216 | /* Build the opcode table only once to avoid |
3217 | multithreading issues. */ | |
3218 | if (opcode_table[0] != NULL) { | |
3219 | return; | |
3220 | } | |
f076803b LV |
3221 | |
3222 | /* use BASE() for instruction available | |
3223 | * for CF_ISA_A and M68000. | |
3224 | */ | |
3225 | #define BASE(name, opcode, mask) \ | |
3226 | register_opcode(disas_##name, 0x##opcode, 0x##mask) | |
d315c888 | 3227 | #define INSN(name, opcode, mask, feature) do { \ |
0402f767 | 3228 | if (m68k_feature(env, M68K_FEATURE_##feature)) \ |
f076803b | 3229 | BASE(name, opcode, mask); \ |
d315c888 | 3230 | } while(0) |
f076803b | 3231 | BASE(undef, 0000, 0000); |
0402f767 | 3232 | INSN(arith_im, 0080, fff8, CF_ISA_A); |
f076803b LV |
3233 | INSN(arith_im, 0000, ff00, M68000); |
3234 | INSN(undef, 00c0, ffc0, M68000); | |
d315c888 | 3235 | INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); |
f076803b LV |
3236 | BASE(bitop_reg, 0100, f1c0); |
3237 | BASE(bitop_reg, 0140, f1c0); | |
3238 | BASE(bitop_reg, 0180, f1c0); | |
3239 | BASE(bitop_reg, 01c0, f1c0); | |
0402f767 | 3240 | INSN(arith_im, 0280, fff8, CF_ISA_A); |
f076803b LV |
3241 | INSN(arith_im, 0200, ff00, M68000); |
3242 | INSN(undef, 02c0, ffc0, M68000); | |
d315c888 | 3243 | INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); |
0402f767 | 3244 | INSN(arith_im, 0480, fff8, CF_ISA_A); |
f076803b LV |
3245 | INSN(arith_im, 0400, ff00, M68000); |
3246 | INSN(undef, 04c0, ffc0, M68000); | |
3247 | INSN(arith_im, 0600, ff00, M68000); | |
3248 | INSN(undef, 06c0, ffc0, M68000); | |
d315c888 | 3249 | INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); |
0402f767 | 3250 | INSN(arith_im, 0680, fff8, CF_ISA_A); |
0402f767 | 3251 | INSN(arith_im, 0c00, ff38, CF_ISA_A); |
f076803b LV |
3252 | INSN(arith_im, 0c00, ff00, M68000); |
3253 | BASE(bitop_im, 0800, ffc0); | |
3254 | BASE(bitop_im, 0840, ffc0); | |
3255 | BASE(bitop_im, 0880, ffc0); | |
3256 | BASE(bitop_im, 08c0, ffc0); | |
3257 | INSN(arith_im, 0a80, fff8, CF_ISA_A); | |
3258 | INSN(arith_im, 0a00, ff00, M68000); | |
3259 | BASE(move, 1000, f000); | |
3260 | BASE(move, 2000, f000); | |
3261 | BASE(move, 3000, f000); | |
d315c888 | 3262 | INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); |
0402f767 | 3263 | INSN(negx, 4080, fff8, CF_ISA_A); |
a665a820 RH |
3264 | INSN(negx, 4000, ff00, M68000); |
3265 | INSN(undef, 40c0, ffc0, M68000); | |
0402f767 | 3266 | INSN(move_from_sr, 40c0, fff8, CF_ISA_A); |
f076803b LV |
3267 | INSN(move_from_sr, 40c0, ffc0, M68000); |
3268 | BASE(lea, 41c0, f1c0); | |
3269 | BASE(clr, 4200, ff00); | |
3270 | BASE(undef, 42c0, ffc0); | |
0402f767 | 3271 | INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); |
7c0eb318 | 3272 | INSN(move_from_ccr, 42c0, ffc0, M68000); |
0402f767 | 3273 | INSN(neg, 4480, fff8, CF_ISA_A); |
f076803b LV |
3274 | INSN(neg, 4400, ff00, M68000); |
3275 | INSN(undef, 44c0, ffc0, M68000); | |
3276 | BASE(move_to_ccr, 44c0, ffc0); | |
0402f767 | 3277 | INSN(not, 4680, fff8, CF_ISA_A); |
f076803b LV |
3278 | INSN(not, 4600, ff00, M68000); |
3279 | INSN(undef, 46c0, ffc0, M68000); | |
0402f767 | 3280 | INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); |
c630e436 | 3281 | INSN(linkl, 4808, fff8, M68000); |
f076803b LV |
3282 | BASE(pea, 4840, ffc0); |
3283 | BASE(swap, 4840, fff8); | |
71600eda | 3284 | INSN(bkpt, 4848, fff8, BKPT); |
f076803b LV |
3285 | BASE(movem, 48c0, fbc0); |
3286 | BASE(ext, 4880, fff8); | |
3287 | BASE(ext, 48c0, fff8); | |
3288 | BASE(ext, 49c0, fff8); | |
3289 | BASE(tst, 4a00, ff00); | |
0402f767 | 3290 | INSN(tas, 4ac0, ffc0, CF_ISA_B); |
f076803b | 3291 | INSN(tas, 4ac0, ffc0, M68000); |
0402f767 PB |
3292 | INSN(halt, 4ac8, ffff, CF_ISA_A); |
3293 | INSN(pulse, 4acc, ffff, CF_ISA_A); | |
f076803b | 3294 | BASE(illegal, 4afc, ffff); |
0402f767 | 3295 | INSN(mull, 4c00, ffc0, CF_ISA_A); |
f076803b | 3296 | INSN(mull, 4c00, ffc0, LONG_MULDIV); |
0402f767 | 3297 | INSN(divl, 4c40, ffc0, CF_ISA_A); |
f076803b | 3298 | INSN(divl, 4c40, ffc0, LONG_MULDIV); |
0402f767 | 3299 | INSN(sats, 4c80, fff8, CF_ISA_B); |
f076803b LV |
3300 | BASE(trap, 4e40, fff0); |
3301 | BASE(link, 4e50, fff8); | |
3302 | BASE(unlk, 4e58, fff8); | |
20dcee94 PB |
3303 | INSN(move_to_usp, 4e60, fff8, USP); |
3304 | INSN(move_from_usp, 4e68, fff8, USP); | |
f076803b LV |
3305 | BASE(nop, 4e71, ffff); |
3306 | BASE(stop, 4e72, ffff); | |
3307 | BASE(rte, 4e73, ffff); | |
3308 | BASE(rts, 4e75, ffff); | |
0402f767 | 3309 | INSN(movec, 4e7b, ffff, CF_ISA_A); |
f076803b | 3310 | BASE(jump, 4e80, ffc0); |
0402f767 PB |
3311 | INSN(jump, 4ec0, ffc0, CF_ISA_A); |
3312 | INSN(addsubq, 5180, f1c0, CF_ISA_A); | |
f076803b LV |
3313 | INSN(jump, 4ec0, ffc0, M68000); |
3314 | INSN(addsubq, 5000, f080, M68000); | |
3315 | INSN(addsubq, 5080, f0c0, M68000); | |
d5a3cf33 LV |
3316 | INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ |
3317 | INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */ | |
beff27ab | 3318 | INSN(dbcc, 50c8, f0f8, M68000); |
0402f767 PB |
3319 | INSN(addsubq, 5080, f1c0, CF_ISA_A); |
3320 | INSN(tpf, 51f8, fff8, CF_ISA_A); | |
d315c888 PB |
3321 | |
3322 | /* Branch instructions. */ | |
f076803b | 3323 | BASE(branch, 6000, f000); |
d315c888 | 3324 | /* Disable long branch instructions, then add back the ones we want. */ |
f076803b | 3325 | BASE(undef, 60ff, f0ff); /* All long branches. */ |
d315c888 PB |
3326 | INSN(branch, 60ff, f0ff, CF_ISA_B); |
3327 | INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ | |
3328 | INSN(branch, 60ff, ffff, BRAL); | |
f076803b | 3329 | INSN(branch, 60ff, f0ff, BCCL); |
d315c888 | 3330 | |
f076803b | 3331 | BASE(moveq, 7000, f100); |
0402f767 | 3332 | INSN(mvzs, 7100, f100, CF_ISA_B); |
f076803b LV |
3333 | BASE(or, 8000, f000); |
3334 | BASE(divw, 80c0, f0c0); | |
3335 | BASE(addsub, 9000, f000); | |
a665a820 RH |
3336 | INSN(undef, 90c0, f0c0, CF_ISA_A); |
3337 | INSN(subx_reg, 9180, f1f8, CF_ISA_A); | |
3338 | INSN(subx_reg, 9100, f138, M68000); | |
3339 | INSN(subx_mem, 9108, f138, M68000); | |
0402f767 | 3340 | INSN(suba, 91c0, f1c0, CF_ISA_A); |
acf930aa | 3341 | |
f076803b | 3342 | BASE(undef_mac, a000, f000); |
acf930aa PB |
3343 | INSN(mac, a000, f100, CF_EMAC); |
3344 | INSN(from_mac, a180, f9b0, CF_EMAC); | |
3345 | INSN(move_mac, a110, f9fc, CF_EMAC); | |
3346 | INSN(from_macsr,a980, f9f0, CF_EMAC); | |
3347 | INSN(from_mask, ad80, fff0, CF_EMAC); | |
3348 | INSN(from_mext, ab80, fbf0, CF_EMAC); | |
3349 | INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); | |
3350 | INSN(to_mac, a100, f9c0, CF_EMAC); | |
3351 | INSN(to_macsr, a900, ffc0, CF_EMAC); | |
3352 | INSN(to_mext, ab00, fbc0, CF_EMAC); | |
3353 | INSN(to_mask, ad00, ffc0, CF_EMAC); | |
3354 | ||
0402f767 PB |
3355 | INSN(mov3q, a140, f1c0, CF_ISA_B); |
3356 | INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ | |
3357 | INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ | |
3358 | INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ | |
3359 | INSN(cmp, b080, f1c0, CF_ISA_A); | |
3360 | INSN(cmpa, b1c0, f1c0, CF_ISA_A); | |
f076803b LV |
3361 | INSN(cmp, b000, f100, M68000); |
3362 | INSN(eor, b100, f100, M68000); | |
3363 | INSN(cmpa, b0c0, f0c0, M68000); | |
0402f767 | 3364 | INSN(eor, b180, f1c0, CF_ISA_A); |
f076803b | 3365 | BASE(and, c000, f000); |
29cf437d LV |
3366 | INSN(exg_dd, c140, f1f8, M68000); |
3367 | INSN(exg_aa, c148, f1f8, M68000); | |
3368 | INSN(exg_da, c188, f1f8, M68000); | |
f076803b LV |
3369 | BASE(mulw, c0c0, f0c0); |
3370 | BASE(addsub, d000, f000); | |
a665a820 RH |
3371 | INSN(undef, d0c0, f0c0, CF_ISA_A); |
3372 | INSN(addx_reg, d180, f1f8, CF_ISA_A); | |
3373 | INSN(addx_reg, d100, f138, M68000); | |
3374 | INSN(addx_mem, d108, f138, M68000); | |
0402f767 | 3375 | INSN(adda, d1c0, f1c0, CF_ISA_A); |
f076803b | 3376 | INSN(adda, d0c0, f0c0, M68000); |
0402f767 PB |
3377 | INSN(shift_im, e080, f0f0, CF_ISA_A); |
3378 | INSN(shift_reg, e0a0, f0f0, CF_ISA_A); | |
3379 | INSN(undef_fpu, f000, f000, CF_ISA_A); | |
e6e5906b PB |
3380 | INSN(fpu, f200, ffc0, CF_FPU); |
3381 | INSN(fbcc, f280, ffc0, CF_FPU); | |
0633879f PB |
3382 | INSN(frestore, f340, ffc0, CF_FPU); |
3383 | INSN(fsave, f340, ffc0, CF_FPU); | |
0402f767 PB |
3384 | INSN(intouch, f340, ffc0, CF_ISA_A); |
3385 | INSN(cpushl, f428, ff38, CF_ISA_A); | |
3386 | INSN(wddata, fb00, ff00, CF_ISA_A); | |
3387 | INSN(wdebug, fbc0, ffc0, CF_ISA_A); | |
e6e5906b PB |
3388 | #undef INSN |
3389 | } | |
3390 | ||
3391 | /* ??? Some of this implementation is not exception safe. We should always | |
3392 | write back the result to memory before setting the condition codes. */ | |
2b3e3cfe | 3393 | static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) |
e6e5906b PB |
3394 | { |
3395 | uint16_t insn; | |
3396 | ||
28b68cd7 | 3397 | insn = read_im16(env, s); |
e6e5906b | 3398 | |
d4d79bb1 | 3399 | opcode_table[insn](env, s, insn); |
e6e5906b PB |
3400 | } |
3401 | ||
e6e5906b | 3402 | /* generate intermediate code for basic block 'tb'. */ |
4e5e1215 | 3403 | void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 3404 | { |
4e5e1215 | 3405 | M68kCPU *cpu = m68k_env_get_cpu(env); |
ed2803da | 3406 | CPUState *cs = CPU(cpu); |
e6e5906b | 3407 | DisasContext dc1, *dc = &dc1; |
e6e5906b PB |
3408 | target_ulong pc_start; |
3409 | int pc_offset; | |
2e70f6ef PB |
3410 | int num_insns; |
3411 | int max_insns; | |
e6e5906b PB |
3412 | |
3413 | /* generate intermediate code */ | |
3414 | pc_start = tb->pc; | |
3b46e624 | 3415 | |
e6e5906b PB |
3416 | dc->tb = tb; |
3417 | ||
e6dbd3b3 | 3418 | dc->env = env; |
e6e5906b PB |
3419 | dc->is_jmp = DISAS_NEXT; |
3420 | dc->pc = pc_start; | |
3421 | dc->cc_op = CC_OP_DYNAMIC; | |
620c6cf6 | 3422 | dc->cc_op_synced = 1; |
ed2803da | 3423 | dc->singlestep_enabled = cs->singlestep_enabled; |
e6e5906b | 3424 | dc->fpcr = env->fpcr; |
0633879f | 3425 | dc->user = (env->sr & SR_S) == 0; |
a7812ae4 | 3426 | dc->done_mac = 0; |
2e70f6ef PB |
3427 | num_insns = 0; |
3428 | max_insns = tb->cflags & CF_COUNT_MASK; | |
190ce7fb | 3429 | if (max_insns == 0) { |
2e70f6ef | 3430 | max_insns = CF_COUNT_MASK; |
190ce7fb RH |
3431 | } |
3432 | if (max_insns > TCG_MAX_INSNS) { | |
3433 | max_insns = TCG_MAX_INSNS; | |
3434 | } | |
2e70f6ef | 3435 | |
cd42d5b2 | 3436 | gen_tb_start(tb); |
e6e5906b | 3437 | do { |
e6e5906b PB |
3438 | pc_offset = dc->pc - pc_start; |
3439 | gen_throws_exception = NULL; | |
20a8856e | 3440 | tcg_gen_insn_start(dc->pc, dc->cc_op); |
959082fc | 3441 | num_insns++; |
667b8e29 | 3442 | |
b933066a RH |
3443 | if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { |
3444 | gen_exception(dc, dc->pc, EXCP_DEBUG); | |
3445 | dc->is_jmp = DISAS_JUMP; | |
522a0d4e RH |
3446 | /* The address covered by the breakpoint must be included in |
3447 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
3448 | properly cleared -- thus we increment the PC here so that | |
3449 | the logic setting tb->size below does the right thing. */ | |
3450 | dc->pc += 2; | |
b933066a RH |
3451 | break; |
3452 | } | |
3453 | ||
959082fc | 3454 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
2e70f6ef | 3455 | gen_io_start(); |
667b8e29 RH |
3456 | } |
3457 | ||
510ff0b7 | 3458 | dc->insn_pc = dc->pc; |
e6e5906b | 3459 | disas_m68k_insn(env, dc); |
fe700adb | 3460 | } while (!dc->is_jmp && !tcg_op_buf_full() && |
ed2803da | 3461 | !cs->singlestep_enabled && |
1b530a6d | 3462 | !singlestep && |
2e70f6ef PB |
3463 | (pc_offset) < (TARGET_PAGE_SIZE - 32) && |
3464 | num_insns < max_insns); | |
e6e5906b | 3465 | |
2e70f6ef PB |
3466 | if (tb->cflags & CF_LAST_IO) |
3467 | gen_io_end(); | |
ed2803da | 3468 | if (unlikely(cs->singlestep_enabled)) { |
e6e5906b PB |
3469 | /* Make sure the pc is updated, and raise a debug exception. */ |
3470 | if (!dc->is_jmp) { | |
9fdb533f | 3471 | update_cc_op(dc); |
e1f3808e | 3472 | tcg_gen_movi_i32(QREG_PC, dc->pc); |
e6e5906b | 3473 | } |
31871141 | 3474 | gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); |
e6e5906b PB |
3475 | } else { |
3476 | switch(dc->is_jmp) { | |
3477 | case DISAS_NEXT: | |
9fdb533f | 3478 | update_cc_op(dc); |
e6e5906b PB |
3479 | gen_jmp_tb(dc, 0, dc->pc); |
3480 | break; | |
3481 | default: | |
3482 | case DISAS_JUMP: | |
3483 | case DISAS_UPDATE: | |
9fdb533f | 3484 | update_cc_op(dc); |
e6e5906b | 3485 | /* indicate that the hash table must be used to find the next TB */ |
57fec1fe | 3486 | tcg_gen_exit_tb(0); |
e6e5906b PB |
3487 | break; |
3488 | case DISAS_TB_JUMP: | |
3489 | /* nothing more to generate */ | |
3490 | break; | |
3491 | } | |
3492 | } | |
806f352d | 3493 | gen_tb_end(tb, num_insns); |
e6e5906b PB |
3494 | |
3495 | #ifdef DEBUG_DISAS | |
4910e6e4 RH |
3496 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
3497 | && qemu_log_in_addr_range(pc_start)) { | |
93fcfe39 AL |
3498 | qemu_log("----------------\n"); |
3499 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 3500 | log_target_disas(cs, pc_start, dc->pc - pc_start, 0); |
93fcfe39 | 3501 | qemu_log("\n"); |
e6e5906b PB |
3502 | } |
3503 | #endif | |
4e5e1215 RH |
3504 | tb->size = dc->pc - pc_start; |
3505 | tb->icount = num_insns; | |
e6e5906b PB |
3506 | } |
3507 | ||
878096ee AF |
3508 | void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
3509 | int flags) | |
e6e5906b | 3510 | { |
878096ee AF |
3511 | M68kCPU *cpu = M68K_CPU(cs); |
3512 | CPUM68KState *env = &cpu->env; | |
e6e5906b PB |
3513 | int i; |
3514 | uint16_t sr; | |
3515 | CPU_DoubleU u; | |
3516 | for (i = 0; i < 8; i++) | |
3517 | { | |
3518 | u.d = env->fregs[i]; | |
8e394cca RH |
3519 | cpu_fprintf(f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", |
3520 | i, env->dregs[i], i, env->aregs[i], | |
3521 | i, u.l.upper, u.l.lower, *(double *)&u.d); | |
e6e5906b PB |
3522 | } |
3523 | cpu_fprintf (f, "PC = %08x ", env->pc); | |
99c51448 | 3524 | sr = env->sr | cpu_m68k_get_ccr(env); |
8e394cca RH |
3525 | cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-', |
3526 | (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', | |
3527 | (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); | |
8fc7cc58 | 3528 | cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); |
e6e5906b PB |
3529 | } |
3530 | ||
bad729e2 RH |
3531 | void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, |
3532 | target_ulong *data) | |
d2856f1a | 3533 | { |
20a8856e | 3534 | int cc_op = data[1]; |
bad729e2 | 3535 | env->pc = data[0]; |
20a8856e LV |
3536 | if (cc_op != CC_OP_DYNAMIC) { |
3537 | env->cc_op = cc_op; | |
3538 | } | |
d2856f1a | 3539 | } |