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Commit | Line | Data |
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e6e5906b PB |
1 | /* |
2 | * m68k translation | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
e6e5906b | 20 | |
e6e5906b | 21 | #include "cpu.h" |
76cad711 | 22 | #include "disas/disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
1de7afc9 | 24 | #include "qemu/log.h" |
f08b6170 | 25 | #include "exec/cpu_ldst.h" |
e1f3808e | 26 | |
2ef6175a RH |
27 | #include "exec/helper-proto.h" |
28 | #include "exec/helper-gen.h" | |
e6e5906b | 29 | |
a7e30d84 LV |
30 | #include "trace-tcg.h" |
31 | ||
32 | ||
0633879f PB |
33 | //#define DEBUG_DISPATCH 1 |
34 | ||
815a6742 | 35 | /* Fake floating point. */ |
815a6742 | 36 | #define tcg_gen_mov_f64 tcg_gen_mov_i64 |
815a6742 | 37 | #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 |
815a6742 | 38 | #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 |
815a6742 | 39 | |
e1f3808e | 40 | #define DEFO32(name, offset) static TCGv QREG_##name; |
a7812ae4 PB |
41 | #define DEFO64(name, offset) static TCGv_i64 QREG_##name; |
42 | #define DEFF64(name, offset) static TCGv_i64 QREG_##name; | |
e1f3808e PB |
43 | #include "qregs.def" |
44 | #undef DEFO32 | |
45 | #undef DEFO64 | |
46 | #undef DEFF64 | |
47 | ||
259186a7 | 48 | static TCGv_i32 cpu_halted; |
27103424 | 49 | static TCGv_i32 cpu_exception_index; |
259186a7 | 50 | |
a7812ae4 | 51 | static TCGv_ptr cpu_env; |
e1f3808e PB |
52 | |
53 | static char cpu_reg_names[3*8*3 + 5*4]; | |
54 | static TCGv cpu_dregs[8]; | |
55 | static TCGv cpu_aregs[8]; | |
a7812ae4 PB |
56 | static TCGv_i64 cpu_fregs[8]; |
57 | static TCGv_i64 cpu_macc[4]; | |
e1f3808e PB |
58 | |
59 | #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7] | |
60 | #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7] | |
61 | #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7] | |
62 | #define MACREG(acc) cpu_macc[acc] | |
63 | #define QREG_SP cpu_aregs[7] | |
64 | ||
65 | static TCGv NULL_QREG; | |
a7812ae4 | 66 | #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) |
e1f3808e PB |
67 | /* Used to distinguish stores from bad addressing modes. */ |
68 | static TCGv store_dummy; | |
69 | ||
022c62cb | 70 | #include "exec/gen-icount.h" |
2e70f6ef | 71 | |
e1f3808e PB |
72 | void m68k_tcg_init(void) |
73 | { | |
74 | char *p; | |
75 | int i; | |
76 | ||
2b3e3cfe AF |
77 | #define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUM68KState, offset), #name); |
78 | #define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUM68KState, offset), #name); | |
e1f3808e PB |
79 | #define DEFF64(name, offset) DEFO64(name, offset) |
80 | #include "qregs.def" | |
81 | #undef DEFO32 | |
82 | #undef DEFO64 | |
83 | #undef DEFF64 | |
84 | ||
259186a7 AF |
85 | cpu_halted = tcg_global_mem_new_i32(TCG_AREG0, |
86 | -offsetof(M68kCPU, env) + | |
87 | offsetof(CPUState, halted), "HALTED"); | |
27103424 AF |
88 | cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0, |
89 | -offsetof(M68kCPU, env) + | |
90 | offsetof(CPUState, exception_index), | |
91 | "EXCEPTION"); | |
259186a7 | 92 | |
a7812ae4 | 93 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
e1f3808e PB |
94 | |
95 | p = cpu_reg_names; | |
96 | for (i = 0; i < 8; i++) { | |
97 | sprintf(p, "D%d", i); | |
a7812ae4 | 98 | cpu_dregs[i] = tcg_global_mem_new(TCG_AREG0, |
e1f3808e PB |
99 | offsetof(CPUM68KState, dregs[i]), p); |
100 | p += 3; | |
101 | sprintf(p, "A%d", i); | |
a7812ae4 | 102 | cpu_aregs[i] = tcg_global_mem_new(TCG_AREG0, |
e1f3808e PB |
103 | offsetof(CPUM68KState, aregs[i]), p); |
104 | p += 3; | |
105 | sprintf(p, "F%d", i); | |
a7812ae4 | 106 | cpu_fregs[i] = tcg_global_mem_new_i64(TCG_AREG0, |
e1f3808e PB |
107 | offsetof(CPUM68KState, fregs[i]), p); |
108 | p += 3; | |
109 | } | |
110 | for (i = 0; i < 4; i++) { | |
111 | sprintf(p, "ACC%d", i); | |
a7812ae4 | 112 | cpu_macc[i] = tcg_global_mem_new_i64(TCG_AREG0, |
e1f3808e PB |
113 | offsetof(CPUM68KState, macc[i]), p); |
114 | p += 5; | |
115 | } | |
116 | ||
a7812ae4 PB |
117 | NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL"); |
118 | store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL"); | |
e1f3808e PB |
119 | } |
120 | ||
e6e5906b PB |
121 | /* internal defines */ |
122 | typedef struct DisasContext { | |
e6dbd3b3 | 123 | CPUM68KState *env; |
510ff0b7 | 124 | target_ulong insn_pc; /* Start of the current instruction. */ |
e6e5906b PB |
125 | target_ulong pc; |
126 | int is_jmp; | |
127 | int cc_op; | |
0633879f | 128 | int user; |
e6e5906b PB |
129 | uint32_t fpcr; |
130 | struct TranslationBlock *tb; | |
131 | int singlestep_enabled; | |
a7812ae4 PB |
132 | TCGv_i64 mactmp; |
133 | int done_mac; | |
e6e5906b PB |
134 | } DisasContext; |
135 | ||
136 | #define DISAS_JUMP_NEXT 4 | |
137 | ||
0633879f PB |
138 | #if defined(CONFIG_USER_ONLY) |
139 | #define IS_USER(s) 1 | |
140 | #else | |
141 | #define IS_USER(s) s->user | |
142 | #endif | |
143 | ||
e6e5906b PB |
144 | /* XXX: move that elsewhere */ |
145 | /* ??? Fix exceptions. */ | |
146 | static void *gen_throws_exception; | |
147 | #define gen_last_qop NULL | |
148 | ||
e6e5906b PB |
149 | #define OS_BYTE 0 |
150 | #define OS_WORD 1 | |
151 | #define OS_LONG 2 | |
152 | #define OS_SINGLE 4 | |
153 | #define OS_DOUBLE 5 | |
154 | ||
d4d79bb1 | 155 | typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); |
e6e5906b | 156 | |
0633879f | 157 | #ifdef DEBUG_DISPATCH |
d4d79bb1 BS |
158 | #define DISAS_INSN(name) \ |
159 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
160 | uint16_t insn); \ | |
161 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
162 | uint16_t insn) \ | |
163 | { \ | |
164 | qemu_log("Dispatch " #name "\n"); \ | |
165 | real_disas_##name(s, env, insn); \ | |
166 | } \ | |
167 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
168 | uint16_t insn) | |
0633879f | 169 | #else |
d4d79bb1 BS |
170 | #define DISAS_INSN(name) \ |
171 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
172 | uint16_t insn) | |
0633879f | 173 | #endif |
e6e5906b PB |
174 | |
175 | /* Generate a load from the specified address. Narrow values are | |
176 | sign extended to full register width. */ | |
e1f3808e | 177 | static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) |
e6e5906b | 178 | { |
e1f3808e PB |
179 | TCGv tmp; |
180 | int index = IS_USER(s); | |
a7812ae4 | 181 | tmp = tcg_temp_new_i32(); |
e6e5906b PB |
182 | switch(opsize) { |
183 | case OS_BYTE: | |
e6e5906b | 184 | if (sign) |
e1f3808e | 185 | tcg_gen_qemu_ld8s(tmp, addr, index); |
e6e5906b | 186 | else |
e1f3808e | 187 | tcg_gen_qemu_ld8u(tmp, addr, index); |
e6e5906b PB |
188 | break; |
189 | case OS_WORD: | |
e6e5906b | 190 | if (sign) |
e1f3808e | 191 | tcg_gen_qemu_ld16s(tmp, addr, index); |
e6e5906b | 192 | else |
e1f3808e | 193 | tcg_gen_qemu_ld16u(tmp, addr, index); |
e6e5906b PB |
194 | break; |
195 | case OS_LONG: | |
e6e5906b | 196 | case OS_SINGLE: |
a7812ae4 | 197 | tcg_gen_qemu_ld32u(tmp, addr, index); |
e6e5906b PB |
198 | break; |
199 | default: | |
7372c2b9 | 200 | g_assert_not_reached(); |
e6e5906b PB |
201 | } |
202 | gen_throws_exception = gen_last_qop; | |
203 | return tmp; | |
204 | } | |
205 | ||
a7812ae4 PB |
206 | static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) |
207 | { | |
208 | TCGv_i64 tmp; | |
209 | int index = IS_USER(s); | |
a7812ae4 PB |
210 | tmp = tcg_temp_new_i64(); |
211 | tcg_gen_qemu_ldf64(tmp, addr, index); | |
212 | gen_throws_exception = gen_last_qop; | |
213 | return tmp; | |
214 | } | |
215 | ||
e6e5906b | 216 | /* Generate a store. */ |
e1f3808e | 217 | static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) |
e6e5906b | 218 | { |
e1f3808e | 219 | int index = IS_USER(s); |
e6e5906b PB |
220 | switch(opsize) { |
221 | case OS_BYTE: | |
e1f3808e | 222 | tcg_gen_qemu_st8(val, addr, index); |
e6e5906b PB |
223 | break; |
224 | case OS_WORD: | |
e1f3808e | 225 | tcg_gen_qemu_st16(val, addr, index); |
e6e5906b PB |
226 | break; |
227 | case OS_LONG: | |
e6e5906b | 228 | case OS_SINGLE: |
a7812ae4 | 229 | tcg_gen_qemu_st32(val, addr, index); |
e6e5906b PB |
230 | break; |
231 | default: | |
7372c2b9 | 232 | g_assert_not_reached(); |
e6e5906b PB |
233 | } |
234 | gen_throws_exception = gen_last_qop; | |
235 | } | |
236 | ||
a7812ae4 PB |
237 | static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) |
238 | { | |
239 | int index = IS_USER(s); | |
a7812ae4 PB |
240 | tcg_gen_qemu_stf64(val, addr, index); |
241 | gen_throws_exception = gen_last_qop; | |
242 | } | |
243 | ||
e1f3808e PB |
244 | typedef enum { |
245 | EA_STORE, | |
246 | EA_LOADU, | |
247 | EA_LOADS | |
248 | } ea_what; | |
249 | ||
e6e5906b PB |
250 | /* Generate an unsigned load if VAL is 0 a signed load if val is -1, |
251 | otherwise generate a store. */ | |
e1f3808e PB |
252 | static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, |
253 | ea_what what) | |
e6e5906b | 254 | { |
e1f3808e | 255 | if (what == EA_STORE) { |
0633879f | 256 | gen_store(s, opsize, addr, val); |
e1f3808e | 257 | return store_dummy; |
e6e5906b | 258 | } else { |
e1f3808e | 259 | return gen_load(s, opsize, addr, what == EA_LOADS); |
e6e5906b PB |
260 | } |
261 | } | |
262 | ||
e6dbd3b3 | 263 | /* Read a 32-bit immediate constant. */ |
d4d79bb1 | 264 | static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) |
e6dbd3b3 PB |
265 | { |
266 | uint32_t im; | |
d4d79bb1 | 267 | im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16; |
e6dbd3b3 | 268 | s->pc += 2; |
d4d79bb1 | 269 | im |= cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
270 | s->pc += 2; |
271 | return im; | |
272 | } | |
273 | ||
274 | /* Calculate and address index. */ | |
e1f3808e | 275 | static TCGv gen_addr_index(uint16_t ext, TCGv tmp) |
e6dbd3b3 | 276 | { |
e1f3808e | 277 | TCGv add; |
e6dbd3b3 PB |
278 | int scale; |
279 | ||
280 | add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); | |
281 | if ((ext & 0x800) == 0) { | |
e1f3808e | 282 | tcg_gen_ext16s_i32(tmp, add); |
e6dbd3b3 PB |
283 | add = tmp; |
284 | } | |
285 | scale = (ext >> 9) & 3; | |
286 | if (scale != 0) { | |
e1f3808e | 287 | tcg_gen_shli_i32(tmp, add, scale); |
e6dbd3b3 PB |
288 | add = tmp; |
289 | } | |
290 | return add; | |
291 | } | |
292 | ||
e1f3808e PB |
293 | /* Handle a base + index + displacement effective addresss. |
294 | A NULL_QREG base means pc-relative. */ | |
d4d79bb1 BS |
295 | static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, int opsize, |
296 | TCGv base) | |
e6e5906b | 297 | { |
e6e5906b PB |
298 | uint32_t offset; |
299 | uint16_t ext; | |
e1f3808e PB |
300 | TCGv add; |
301 | TCGv tmp; | |
e6dbd3b3 | 302 | uint32_t bd, od; |
e6e5906b PB |
303 | |
304 | offset = s->pc; | |
d4d79bb1 | 305 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 306 | s->pc += 2; |
e6dbd3b3 PB |
307 | |
308 | if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) | |
e1f3808e | 309 | return NULL_QREG; |
e6dbd3b3 PB |
310 | |
311 | if (ext & 0x100) { | |
312 | /* full extension word format */ | |
313 | if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) | |
e1f3808e | 314 | return NULL_QREG; |
e6dbd3b3 PB |
315 | |
316 | if ((ext & 0x30) > 0x10) { | |
317 | /* base displacement */ | |
318 | if ((ext & 0x30) == 0x20) { | |
d4d79bb1 | 319 | bd = (int16_t)cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
320 | s->pc += 2; |
321 | } else { | |
d4d79bb1 | 322 | bd = read_im32(env, s); |
e6dbd3b3 PB |
323 | } |
324 | } else { | |
325 | bd = 0; | |
326 | } | |
a7812ae4 | 327 | tmp = tcg_temp_new(); |
e6dbd3b3 PB |
328 | if ((ext & 0x44) == 0) { |
329 | /* pre-index */ | |
330 | add = gen_addr_index(ext, tmp); | |
331 | } else { | |
e1f3808e | 332 | add = NULL_QREG; |
e6dbd3b3 PB |
333 | } |
334 | if ((ext & 0x80) == 0) { | |
335 | /* base not suppressed */ | |
e1f3808e | 336 | if (IS_NULL_QREG(base)) { |
351326a6 | 337 | base = tcg_const_i32(offset + bd); |
e6dbd3b3 PB |
338 | bd = 0; |
339 | } | |
e1f3808e PB |
340 | if (!IS_NULL_QREG(add)) { |
341 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 PB |
342 | add = tmp; |
343 | } else { | |
344 | add = base; | |
345 | } | |
346 | } | |
e1f3808e | 347 | if (!IS_NULL_QREG(add)) { |
e6dbd3b3 | 348 | if (bd != 0) { |
e1f3808e | 349 | tcg_gen_addi_i32(tmp, add, bd); |
e6dbd3b3 PB |
350 | add = tmp; |
351 | } | |
352 | } else { | |
351326a6 | 353 | add = tcg_const_i32(bd); |
e6dbd3b3 PB |
354 | } |
355 | if ((ext & 3) != 0) { | |
356 | /* memory indirect */ | |
357 | base = gen_load(s, OS_LONG, add, 0); | |
358 | if ((ext & 0x44) == 4) { | |
359 | add = gen_addr_index(ext, tmp); | |
e1f3808e | 360 | tcg_gen_add_i32(tmp, add, base); |
e6dbd3b3 PB |
361 | add = tmp; |
362 | } else { | |
363 | add = base; | |
364 | } | |
365 | if ((ext & 3) > 1) { | |
366 | /* outer displacement */ | |
367 | if ((ext & 3) == 2) { | |
d4d79bb1 | 368 | od = (int16_t)cpu_lduw_code(env, s->pc); |
e6dbd3b3 PB |
369 | s->pc += 2; |
370 | } else { | |
d4d79bb1 | 371 | od = read_im32(env, s); |
e6dbd3b3 PB |
372 | } |
373 | } else { | |
374 | od = 0; | |
375 | } | |
376 | if (od != 0) { | |
e1f3808e | 377 | tcg_gen_addi_i32(tmp, add, od); |
e6dbd3b3 PB |
378 | add = tmp; |
379 | } | |
380 | } | |
e6e5906b | 381 | } else { |
e6dbd3b3 | 382 | /* brief extension word format */ |
a7812ae4 | 383 | tmp = tcg_temp_new(); |
e6dbd3b3 | 384 | add = gen_addr_index(ext, tmp); |
e1f3808e PB |
385 | if (!IS_NULL_QREG(base)) { |
386 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 | 387 | if ((int8_t)ext) |
e1f3808e | 388 | tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); |
e6dbd3b3 | 389 | } else { |
e1f3808e | 390 | tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); |
e6dbd3b3 PB |
391 | } |
392 | add = tmp; | |
e6e5906b | 393 | } |
e6dbd3b3 | 394 | return add; |
e6e5906b PB |
395 | } |
396 | ||
e6e5906b PB |
397 | /* Update the CPU env CC_OP state. */ |
398 | static inline void gen_flush_cc_op(DisasContext *s) | |
399 | { | |
400 | if (s->cc_op != CC_OP_DYNAMIC) | |
e1f3808e | 401 | tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); |
e6e5906b PB |
402 | } |
403 | ||
404 | /* Evaluate all the CC flags. */ | |
405 | static inline void gen_flush_flags(DisasContext *s) | |
406 | { | |
407 | if (s->cc_op == CC_OP_FLAGS) | |
408 | return; | |
0cf5c677 | 409 | gen_flush_cc_op(s); |
e1f3808e | 410 | gen_helper_flush_flags(cpu_env, QREG_CC_OP); |
e6e5906b PB |
411 | s->cc_op = CC_OP_FLAGS; |
412 | } | |
413 | ||
e1f3808e PB |
414 | static void gen_logic_cc(DisasContext *s, TCGv val) |
415 | { | |
416 | tcg_gen_mov_i32(QREG_CC_DEST, val); | |
417 | s->cc_op = CC_OP_LOGIC; | |
418 | } | |
419 | ||
420 | static void gen_update_cc_add(TCGv dest, TCGv src) | |
421 | { | |
422 | tcg_gen_mov_i32(QREG_CC_DEST, dest); | |
423 | tcg_gen_mov_i32(QREG_CC_SRC, src); | |
424 | } | |
425 | ||
e6e5906b PB |
426 | static inline int opsize_bytes(int opsize) |
427 | { | |
428 | switch (opsize) { | |
429 | case OS_BYTE: return 1; | |
430 | case OS_WORD: return 2; | |
431 | case OS_LONG: return 4; | |
432 | case OS_SINGLE: return 4; | |
433 | case OS_DOUBLE: return 8; | |
434 | default: | |
7372c2b9 | 435 | g_assert_not_reached(); |
e6e5906b PB |
436 | } |
437 | } | |
438 | ||
439 | /* Assign value to a register. If the width is less than the register width | |
440 | only the low part of the register is set. */ | |
e1f3808e | 441 | static void gen_partset_reg(int opsize, TCGv reg, TCGv val) |
e6e5906b | 442 | { |
e1f3808e | 443 | TCGv tmp; |
e6e5906b PB |
444 | switch (opsize) { |
445 | case OS_BYTE: | |
e1f3808e | 446 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
a7812ae4 | 447 | tmp = tcg_temp_new(); |
e1f3808e PB |
448 | tcg_gen_ext8u_i32(tmp, val); |
449 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
450 | break; |
451 | case OS_WORD: | |
e1f3808e | 452 | tcg_gen_andi_i32(reg, reg, 0xffff0000); |
a7812ae4 | 453 | tmp = tcg_temp_new(); |
e1f3808e PB |
454 | tcg_gen_ext16u_i32(tmp, val); |
455 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
456 | break; |
457 | case OS_LONG: | |
e6e5906b | 458 | case OS_SINGLE: |
a7812ae4 | 459 | tcg_gen_mov_i32(reg, val); |
e6e5906b PB |
460 | break; |
461 | default: | |
7372c2b9 | 462 | g_assert_not_reached(); |
e6e5906b PB |
463 | } |
464 | } | |
465 | ||
466 | /* Sign or zero extend a value. */ | |
e1f3808e | 467 | static inline TCGv gen_extend(TCGv val, int opsize, int sign) |
e6e5906b | 468 | { |
e1f3808e | 469 | TCGv tmp; |
e6e5906b PB |
470 | |
471 | switch (opsize) { | |
472 | case OS_BYTE: | |
a7812ae4 | 473 | tmp = tcg_temp_new(); |
e6e5906b | 474 | if (sign) |
e1f3808e | 475 | tcg_gen_ext8s_i32(tmp, val); |
e6e5906b | 476 | else |
e1f3808e | 477 | tcg_gen_ext8u_i32(tmp, val); |
e6e5906b PB |
478 | break; |
479 | case OS_WORD: | |
a7812ae4 | 480 | tmp = tcg_temp_new(); |
e6e5906b | 481 | if (sign) |
e1f3808e | 482 | tcg_gen_ext16s_i32(tmp, val); |
e6e5906b | 483 | else |
e1f3808e | 484 | tcg_gen_ext16u_i32(tmp, val); |
e6e5906b PB |
485 | break; |
486 | case OS_LONG: | |
e6e5906b | 487 | case OS_SINGLE: |
a7812ae4 | 488 | tmp = val; |
e6e5906b PB |
489 | break; |
490 | default: | |
7372c2b9 | 491 | g_assert_not_reached(); |
e6e5906b PB |
492 | } |
493 | return tmp; | |
494 | } | |
495 | ||
496 | /* Generate code for an "effective address". Does not adjust the base | |
1addc7c5 | 497 | register for autoincrement addressing modes. */ |
d4d79bb1 BS |
498 | static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
499 | int opsize) | |
e6e5906b | 500 | { |
e1f3808e PB |
501 | TCGv reg; |
502 | TCGv tmp; | |
e6e5906b PB |
503 | uint16_t ext; |
504 | uint32_t offset; | |
505 | ||
e6e5906b PB |
506 | switch ((insn >> 3) & 7) { |
507 | case 0: /* Data register direct. */ | |
508 | case 1: /* Address register direct. */ | |
e1f3808e | 509 | return NULL_QREG; |
e6e5906b PB |
510 | case 2: /* Indirect register */ |
511 | case 3: /* Indirect postincrement. */ | |
e1f3808e | 512 | return AREG(insn, 0); |
e6e5906b | 513 | case 4: /* Indirect predecrememnt. */ |
e1f3808e | 514 | reg = AREG(insn, 0); |
a7812ae4 | 515 | tmp = tcg_temp_new(); |
e1f3808e | 516 | tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); |
e6e5906b PB |
517 | return tmp; |
518 | case 5: /* Indirect displacement. */ | |
e1f3808e | 519 | reg = AREG(insn, 0); |
a7812ae4 | 520 | tmp = tcg_temp_new(); |
d4d79bb1 | 521 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 522 | s->pc += 2; |
e1f3808e | 523 | tcg_gen_addi_i32(tmp, reg, (int16_t)ext); |
e6e5906b PB |
524 | return tmp; |
525 | case 6: /* Indirect index + displacement. */ | |
e1f3808e | 526 | reg = AREG(insn, 0); |
d4d79bb1 | 527 | return gen_lea_indexed(env, s, opsize, reg); |
e6e5906b | 528 | case 7: /* Other */ |
e1f3808e | 529 | switch (insn & 7) { |
e6e5906b | 530 | case 0: /* Absolute short. */ |
d4d79bb1 | 531 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b | 532 | s->pc += 2; |
351326a6 | 533 | return tcg_const_i32(offset); |
e6e5906b | 534 | case 1: /* Absolute long. */ |
d4d79bb1 | 535 | offset = read_im32(env, s); |
351326a6 | 536 | return tcg_const_i32(offset); |
e6e5906b | 537 | case 2: /* pc displacement */ |
e6e5906b | 538 | offset = s->pc; |
d4d79bb1 | 539 | offset += cpu_ldsw_code(env, s->pc); |
e6e5906b | 540 | s->pc += 2; |
351326a6 | 541 | return tcg_const_i32(offset); |
e6e5906b | 542 | case 3: /* pc index+displacement. */ |
d4d79bb1 | 543 | return gen_lea_indexed(env, s, opsize, NULL_QREG); |
e6e5906b PB |
544 | case 4: /* Immediate. */ |
545 | default: | |
e1f3808e | 546 | return NULL_QREG; |
e6e5906b PB |
547 | } |
548 | } | |
549 | /* Should never happen. */ | |
e1f3808e | 550 | return NULL_QREG; |
e6e5906b PB |
551 | } |
552 | ||
553 | /* Helper function for gen_ea. Reuse the computed address between the | |
554 | for read/write operands. */ | |
d4d79bb1 BS |
555 | static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s, |
556 | uint16_t insn, int opsize, TCGv val, | |
557 | TCGv *addrp, ea_what what) | |
e6e5906b | 558 | { |
e1f3808e | 559 | TCGv tmp; |
e6e5906b | 560 | |
e1f3808e | 561 | if (addrp && what == EA_STORE) { |
e6e5906b PB |
562 | tmp = *addrp; |
563 | } else { | |
d4d79bb1 | 564 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
565 | if (IS_NULL_QREG(tmp)) |
566 | return tmp; | |
e6e5906b PB |
567 | if (addrp) |
568 | *addrp = tmp; | |
569 | } | |
e1f3808e | 570 | return gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
571 | } |
572 | ||
f38f7a84 | 573 | /* Generate code to load/store a value from/into an EA. If VAL > 0 this is |
e6e5906b PB |
574 | a write otherwise it is a read (0 == sign extend, -1 == zero extend). |
575 | ADDRP is non-null for readwrite operands. */ | |
d4d79bb1 BS |
576 | static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
577 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
e6e5906b | 578 | { |
e1f3808e PB |
579 | TCGv reg; |
580 | TCGv result; | |
e6e5906b PB |
581 | uint32_t offset; |
582 | ||
e6e5906b PB |
583 | switch ((insn >> 3) & 7) { |
584 | case 0: /* Data register direct. */ | |
e1f3808e PB |
585 | reg = DREG(insn, 0); |
586 | if (what == EA_STORE) { | |
e6e5906b | 587 | gen_partset_reg(opsize, reg, val); |
e1f3808e | 588 | return store_dummy; |
e6e5906b | 589 | } else { |
e1f3808e | 590 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
591 | } |
592 | case 1: /* Address register direct. */ | |
e1f3808e PB |
593 | reg = AREG(insn, 0); |
594 | if (what == EA_STORE) { | |
595 | tcg_gen_mov_i32(reg, val); | |
596 | return store_dummy; | |
e6e5906b | 597 | } else { |
e1f3808e | 598 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
599 | } |
600 | case 2: /* Indirect register */ | |
e1f3808e PB |
601 | reg = AREG(insn, 0); |
602 | return gen_ldst(s, opsize, reg, val, what); | |
e6e5906b | 603 | case 3: /* Indirect postincrement. */ |
e1f3808e PB |
604 | reg = AREG(insn, 0); |
605 | result = gen_ldst(s, opsize, reg, val, what); | |
e6e5906b PB |
606 | /* ??? This is not exception safe. The instruction may still |
607 | fault after this point. */ | |
e1f3808e PB |
608 | if (what == EA_STORE || !addrp) |
609 | tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize)); | |
e6e5906b PB |
610 | return result; |
611 | case 4: /* Indirect predecrememnt. */ | |
612 | { | |
e1f3808e PB |
613 | TCGv tmp; |
614 | if (addrp && what == EA_STORE) { | |
e6e5906b PB |
615 | tmp = *addrp; |
616 | } else { | |
d4d79bb1 | 617 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
618 | if (IS_NULL_QREG(tmp)) |
619 | return tmp; | |
e6e5906b PB |
620 | if (addrp) |
621 | *addrp = tmp; | |
622 | } | |
e1f3808e | 623 | result = gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
624 | /* ??? This is not exception safe. The instruction may still |
625 | fault after this point. */ | |
e1f3808e PB |
626 | if (what == EA_STORE || !addrp) { |
627 | reg = AREG(insn, 0); | |
628 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
629 | } |
630 | } | |
631 | return result; | |
632 | case 5: /* Indirect displacement. */ | |
633 | case 6: /* Indirect index + displacement. */ | |
d4d79bb1 | 634 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b | 635 | case 7: /* Other */ |
e1f3808e | 636 | switch (insn & 7) { |
e6e5906b PB |
637 | case 0: /* Absolute short. */ |
638 | case 1: /* Absolute long. */ | |
639 | case 2: /* pc displacement */ | |
640 | case 3: /* pc index+displacement. */ | |
d4d79bb1 | 641 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b PB |
642 | case 4: /* Immediate. */ |
643 | /* Sign extend values for consistency. */ | |
644 | switch (opsize) { | |
645 | case OS_BYTE: | |
31871141 | 646 | if (what == EA_LOADS) { |
d4d79bb1 | 647 | offset = cpu_ldsb_code(env, s->pc + 1); |
31871141 | 648 | } else { |
d4d79bb1 | 649 | offset = cpu_ldub_code(env, s->pc + 1); |
31871141 | 650 | } |
e6e5906b PB |
651 | s->pc += 2; |
652 | break; | |
653 | case OS_WORD: | |
31871141 | 654 | if (what == EA_LOADS) { |
d4d79bb1 | 655 | offset = cpu_ldsw_code(env, s->pc); |
31871141 | 656 | } else { |
d4d79bb1 | 657 | offset = cpu_lduw_code(env, s->pc); |
31871141 | 658 | } |
e6e5906b PB |
659 | s->pc += 2; |
660 | break; | |
661 | case OS_LONG: | |
d4d79bb1 | 662 | offset = read_im32(env, s); |
e6e5906b PB |
663 | break; |
664 | default: | |
7372c2b9 | 665 | g_assert_not_reached(); |
e6e5906b | 666 | } |
e1f3808e | 667 | return tcg_const_i32(offset); |
e6e5906b | 668 | default: |
e1f3808e | 669 | return NULL_QREG; |
e6e5906b PB |
670 | } |
671 | } | |
672 | /* Should never happen. */ | |
e1f3808e | 673 | return NULL_QREG; |
e6e5906b PB |
674 | } |
675 | ||
e1f3808e | 676 | /* This generates a conditional branch, clobbering all temporaries. */ |
42a268c2 | 677 | static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) |
e6e5906b | 678 | { |
e1f3808e | 679 | TCGv tmp; |
e6e5906b | 680 | |
e1f3808e PB |
681 | /* TODO: Optimize compare/branch pairs rather than always flushing |
682 | flag state to CC_OP_FLAGS. */ | |
e6e5906b PB |
683 | gen_flush_flags(s); |
684 | switch (cond) { | |
685 | case 0: /* T */ | |
e1f3808e | 686 | tcg_gen_br(l1); |
e6e5906b PB |
687 | break; |
688 | case 1: /* F */ | |
689 | break; | |
690 | case 2: /* HI (!C && !Z) */ | |
a7812ae4 | 691 | tmp = tcg_temp_new(); |
e1f3808e PB |
692 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
693 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
694 | break; |
695 | case 3: /* LS (C || Z) */ | |
a7812ae4 | 696 | tmp = tcg_temp_new(); |
e1f3808e PB |
697 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
698 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
699 | break; |
700 | case 4: /* CC (!C) */ | |
a7812ae4 | 701 | tmp = tcg_temp_new(); |
e1f3808e PB |
702 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
703 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
704 | break; |
705 | case 5: /* CS (C) */ | |
a7812ae4 | 706 | tmp = tcg_temp_new(); |
e1f3808e PB |
707 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
708 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
709 | break; |
710 | case 6: /* NE (!Z) */ | |
a7812ae4 | 711 | tmp = tcg_temp_new(); |
e1f3808e PB |
712 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
713 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
714 | break; |
715 | case 7: /* EQ (Z) */ | |
a7812ae4 | 716 | tmp = tcg_temp_new(); |
e1f3808e PB |
717 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
718 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
719 | break; |
720 | case 8: /* VC (!V) */ | |
a7812ae4 | 721 | tmp = tcg_temp_new(); |
e1f3808e PB |
722 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
723 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
724 | break; |
725 | case 9: /* VS (V) */ | |
a7812ae4 | 726 | tmp = tcg_temp_new(); |
e1f3808e PB |
727 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
728 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
729 | break; |
730 | case 10: /* PL (!N) */ | |
a7812ae4 | 731 | tmp = tcg_temp_new(); |
e1f3808e PB |
732 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
733 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
734 | break; |
735 | case 11: /* MI (N) */ | |
a7812ae4 | 736 | tmp = tcg_temp_new(); |
e1f3808e PB |
737 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
738 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
739 | break; |
740 | case 12: /* GE (!(N ^ V)) */ | |
a7812ae4 | 741 | tmp = tcg_temp_new(); |
e1f3808e PB |
742 | assert(CCF_V == (CCF_N >> 2)); |
743 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
744 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
745 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
746 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
747 | break; |
748 | case 13: /* LT (N ^ V) */ | |
a7812ae4 | 749 | tmp = tcg_temp_new(); |
e1f3808e PB |
750 | assert(CCF_V == (CCF_N >> 2)); |
751 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
752 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
753 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
754 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
755 | break; |
756 | case 14: /* GT (!(Z || (N ^ V))) */ | |
a7812ae4 | 757 | tmp = tcg_temp_new(); |
e1f3808e PB |
758 | assert(CCF_V == (CCF_N >> 2)); |
759 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
760 | tcg_gen_shri_i32(tmp, tmp, 2); | |
761 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
762 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
763 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
764 | break; |
765 | case 15: /* LE (Z || (N ^ V)) */ | |
a7812ae4 | 766 | tmp = tcg_temp_new(); |
e1f3808e PB |
767 | assert(CCF_V == (CCF_N >> 2)); |
768 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
769 | tcg_gen_shri_i32(tmp, tmp, 2); | |
770 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
771 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
772 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
773 | break; |
774 | default: | |
775 | /* Should ever happen. */ | |
776 | abort(); | |
777 | } | |
778 | } | |
779 | ||
780 | DISAS_INSN(scc) | |
781 | { | |
42a268c2 | 782 | TCGLabel *l1; |
e6e5906b | 783 | int cond; |
e1f3808e | 784 | TCGv reg; |
e6e5906b PB |
785 | |
786 | l1 = gen_new_label(); | |
787 | cond = (insn >> 8) & 0xf; | |
788 | reg = DREG(insn, 0); | |
e1f3808e PB |
789 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
790 | /* This is safe because we modify the reg directly, with no other values | |
791 | live. */ | |
e6e5906b | 792 | gen_jmpcc(s, cond ^ 1, l1); |
e1f3808e | 793 | tcg_gen_ori_i32(reg, reg, 0xff); |
e6e5906b PB |
794 | gen_set_label(l1); |
795 | } | |
796 | ||
0633879f PB |
797 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
798 | static void gen_lookup_tb(DisasContext *s) | |
799 | { | |
800 | gen_flush_cc_op(s); | |
e1f3808e | 801 | tcg_gen_movi_i32(QREG_PC, s->pc); |
0633879f PB |
802 | s->is_jmp = DISAS_UPDATE; |
803 | } | |
804 | ||
e1f3808e PB |
805 | /* Generate a jump to an immediate address. */ |
806 | static void gen_jmp_im(DisasContext *s, uint32_t dest) | |
807 | { | |
808 | gen_flush_cc_op(s); | |
809 | tcg_gen_movi_i32(QREG_PC, dest); | |
810 | s->is_jmp = DISAS_JUMP; | |
811 | } | |
812 | ||
813 | /* Generate a jump to the address in qreg DEST. */ | |
814 | static void gen_jmp(DisasContext *s, TCGv dest) | |
e6e5906b PB |
815 | { |
816 | gen_flush_cc_op(s); | |
e1f3808e | 817 | tcg_gen_mov_i32(QREG_PC, dest); |
e6e5906b PB |
818 | s->is_jmp = DISAS_JUMP; |
819 | } | |
820 | ||
821 | static void gen_exception(DisasContext *s, uint32_t where, int nr) | |
822 | { | |
823 | gen_flush_cc_op(s); | |
e1f3808e | 824 | gen_jmp_im(s, where); |
31871141 | 825 | gen_helper_raise_exception(cpu_env, tcg_const_i32(nr)); |
e6e5906b PB |
826 | } |
827 | ||
510ff0b7 PB |
828 | static inline void gen_addr_fault(DisasContext *s) |
829 | { | |
830 | gen_exception(s, s->insn_pc, EXCP_ADDRESS); | |
831 | } | |
832 | ||
d4d79bb1 BS |
833 | #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ |
834 | result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ | |
835 | op_sign ? EA_LOADS : EA_LOADU); \ | |
836 | if (IS_NULL_QREG(result)) { \ | |
837 | gen_addr_fault(s); \ | |
838 | return; \ | |
839 | } \ | |
510ff0b7 PB |
840 | } while (0) |
841 | ||
d4d79bb1 BS |
842 | #define DEST_EA(env, insn, opsize, val, addrp) do { \ |
843 | TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ | |
844 | if (IS_NULL_QREG(ea_result)) { \ | |
845 | gen_addr_fault(s); \ | |
846 | return; \ | |
847 | } \ | |
510ff0b7 PB |
848 | } while (0) |
849 | ||
e6e5906b PB |
850 | /* Generate a jump to an immediate address. */ |
851 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | |
852 | { | |
853 | TranslationBlock *tb; | |
854 | ||
855 | tb = s->tb; | |
551bd27f | 856 | if (unlikely(s->singlestep_enabled)) { |
e6e5906b PB |
857 | gen_exception(s, dest, EXCP_DEBUG); |
858 | } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || | |
859 | (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { | |
57fec1fe | 860 | tcg_gen_goto_tb(n); |
e1f3808e | 861 | tcg_gen_movi_i32(QREG_PC, dest); |
8cfd0495 | 862 | tcg_gen_exit_tb((uintptr_t)tb + n); |
e6e5906b | 863 | } else { |
e1f3808e | 864 | gen_jmp_im(s, dest); |
57fec1fe | 865 | tcg_gen_exit_tb(0); |
e6e5906b PB |
866 | } |
867 | s->is_jmp = DISAS_TB_JUMP; | |
868 | } | |
869 | ||
870 | DISAS_INSN(undef_mac) | |
871 | { | |
872 | gen_exception(s, s->pc - 2, EXCP_LINEA); | |
873 | } | |
874 | ||
875 | DISAS_INSN(undef_fpu) | |
876 | { | |
877 | gen_exception(s, s->pc - 2, EXCP_LINEF); | |
878 | } | |
879 | ||
880 | DISAS_INSN(undef) | |
881 | { | |
a47dddd7 AF |
882 | M68kCPU *cpu = m68k_env_get_cpu(env); |
883 | ||
e6e5906b | 884 | gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); |
a47dddd7 | 885 | cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); |
e6e5906b PB |
886 | } |
887 | ||
888 | DISAS_INSN(mulw) | |
889 | { | |
e1f3808e PB |
890 | TCGv reg; |
891 | TCGv tmp; | |
892 | TCGv src; | |
e6e5906b PB |
893 | int sign; |
894 | ||
895 | sign = (insn & 0x100) != 0; | |
896 | reg = DREG(insn, 9); | |
a7812ae4 | 897 | tmp = tcg_temp_new(); |
e6e5906b | 898 | if (sign) |
e1f3808e | 899 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 900 | else |
e1f3808e | 901 | tcg_gen_ext16u_i32(tmp, reg); |
d4d79bb1 | 902 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e PB |
903 | tcg_gen_mul_i32(tmp, tmp, src); |
904 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
905 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
906 | gen_logic_cc(s, tmp); | |
907 | } | |
908 | ||
909 | DISAS_INSN(divw) | |
910 | { | |
e1f3808e PB |
911 | TCGv reg; |
912 | TCGv tmp; | |
913 | TCGv src; | |
e6e5906b PB |
914 | int sign; |
915 | ||
916 | sign = (insn & 0x100) != 0; | |
917 | reg = DREG(insn, 9); | |
918 | if (sign) { | |
e1f3808e | 919 | tcg_gen_ext16s_i32(QREG_DIV1, reg); |
e6e5906b | 920 | } else { |
e1f3808e | 921 | tcg_gen_ext16u_i32(QREG_DIV1, reg); |
e6e5906b | 922 | } |
d4d79bb1 | 923 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e | 924 | tcg_gen_mov_i32(QREG_DIV2, src); |
e6e5906b | 925 | if (sign) { |
e1f3808e | 926 | gen_helper_divs(cpu_env, tcg_const_i32(1)); |
e6e5906b | 927 | } else { |
e1f3808e | 928 | gen_helper_divu(cpu_env, tcg_const_i32(1)); |
e6e5906b PB |
929 | } |
930 | ||
a7812ae4 PB |
931 | tmp = tcg_temp_new(); |
932 | src = tcg_temp_new(); | |
e1f3808e PB |
933 | tcg_gen_ext16u_i32(tmp, QREG_DIV1); |
934 | tcg_gen_shli_i32(src, QREG_DIV2, 16); | |
935 | tcg_gen_or_i32(reg, tmp, src); | |
e6e5906b PB |
936 | s->cc_op = CC_OP_FLAGS; |
937 | } | |
938 | ||
939 | DISAS_INSN(divl) | |
940 | { | |
e1f3808e PB |
941 | TCGv num; |
942 | TCGv den; | |
943 | TCGv reg; | |
e6e5906b PB |
944 | uint16_t ext; |
945 | ||
d4d79bb1 | 946 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
947 | s->pc += 2; |
948 | if (ext & 0x87f8) { | |
949 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
950 | return; | |
951 | } | |
952 | num = DREG(ext, 12); | |
953 | reg = DREG(ext, 0); | |
e1f3808e | 954 | tcg_gen_mov_i32(QREG_DIV1, num); |
d4d79bb1 | 955 | SRC_EA(env, den, OS_LONG, 0, NULL); |
e1f3808e | 956 | tcg_gen_mov_i32(QREG_DIV2, den); |
e6e5906b | 957 | if (ext & 0x0800) { |
e1f3808e | 958 | gen_helper_divs(cpu_env, tcg_const_i32(0)); |
e6e5906b | 959 | } else { |
e1f3808e | 960 | gen_helper_divu(cpu_env, tcg_const_i32(0)); |
e6e5906b | 961 | } |
e1f3808e | 962 | if ((ext & 7) == ((ext >> 12) & 7)) { |
e6e5906b | 963 | /* div */ |
e1f3808e | 964 | tcg_gen_mov_i32 (reg, QREG_DIV1); |
e6e5906b PB |
965 | } else { |
966 | /* rem */ | |
e1f3808e | 967 | tcg_gen_mov_i32 (reg, QREG_DIV2); |
e6e5906b | 968 | } |
e6e5906b PB |
969 | s->cc_op = CC_OP_FLAGS; |
970 | } | |
971 | ||
972 | DISAS_INSN(addsub) | |
973 | { | |
e1f3808e PB |
974 | TCGv reg; |
975 | TCGv dest; | |
976 | TCGv src; | |
977 | TCGv tmp; | |
978 | TCGv addr; | |
e6e5906b PB |
979 | int add; |
980 | ||
981 | add = (insn & 0x4000) != 0; | |
982 | reg = DREG(insn, 9); | |
a7812ae4 | 983 | dest = tcg_temp_new(); |
e6e5906b | 984 | if (insn & 0x100) { |
d4d79bb1 | 985 | SRC_EA(env, tmp, OS_LONG, 0, &addr); |
e6e5906b PB |
986 | src = reg; |
987 | } else { | |
988 | tmp = reg; | |
d4d79bb1 | 989 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b PB |
990 | } |
991 | if (add) { | |
e1f3808e PB |
992 | tcg_gen_add_i32(dest, tmp, src); |
993 | gen_helper_xflag_lt(QREG_CC_X, dest, src); | |
e6e5906b PB |
994 | s->cc_op = CC_OP_ADD; |
995 | } else { | |
e1f3808e PB |
996 | gen_helper_xflag_lt(QREG_CC_X, tmp, src); |
997 | tcg_gen_sub_i32(dest, tmp, src); | |
e6e5906b PB |
998 | s->cc_op = CC_OP_SUB; |
999 | } | |
e1f3808e | 1000 | gen_update_cc_add(dest, src); |
e6e5906b | 1001 | if (insn & 0x100) { |
d4d79bb1 | 1002 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1003 | } else { |
e1f3808e | 1004 | tcg_gen_mov_i32(reg, dest); |
e6e5906b PB |
1005 | } |
1006 | } | |
1007 | ||
1008 | ||
1009 | /* Reverse the order of the bits in REG. */ | |
1010 | DISAS_INSN(bitrev) | |
1011 | { | |
e1f3808e | 1012 | TCGv reg; |
e6e5906b | 1013 | reg = DREG(insn, 0); |
e1f3808e | 1014 | gen_helper_bitrev(reg, reg); |
e6e5906b PB |
1015 | } |
1016 | ||
1017 | DISAS_INSN(bitop_reg) | |
1018 | { | |
1019 | int opsize; | |
1020 | int op; | |
e1f3808e PB |
1021 | TCGv src1; |
1022 | TCGv src2; | |
1023 | TCGv tmp; | |
1024 | TCGv addr; | |
1025 | TCGv dest; | |
e6e5906b PB |
1026 | |
1027 | if ((insn & 0x38) != 0) | |
1028 | opsize = OS_BYTE; | |
1029 | else | |
1030 | opsize = OS_LONG; | |
1031 | op = (insn >> 6) & 3; | |
d4d79bb1 | 1032 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1033 | src2 = DREG(insn, 9); |
a7812ae4 | 1034 | dest = tcg_temp_new(); |
e6e5906b PB |
1035 | |
1036 | gen_flush_flags(s); | |
a7812ae4 | 1037 | tmp = tcg_temp_new(); |
e6e5906b | 1038 | if (opsize == OS_BYTE) |
e1f3808e | 1039 | tcg_gen_andi_i32(tmp, src2, 7); |
e6e5906b | 1040 | else |
e1f3808e | 1041 | tcg_gen_andi_i32(tmp, src2, 31); |
e6e5906b | 1042 | src2 = tmp; |
a7812ae4 | 1043 | tmp = tcg_temp_new(); |
e1f3808e PB |
1044 | tcg_gen_shr_i32(tmp, src1, src2); |
1045 | tcg_gen_andi_i32(tmp, tmp, 1); | |
1046 | tcg_gen_shli_i32(tmp, tmp, 2); | |
1047 | /* Clear CCF_Z if bit set. */ | |
1048 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1049 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1050 | ||
1051 | tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2); | |
e6e5906b PB |
1052 | switch (op) { |
1053 | case 1: /* bchg */ | |
e1f3808e | 1054 | tcg_gen_xor_i32(dest, src1, tmp); |
e6e5906b PB |
1055 | break; |
1056 | case 2: /* bclr */ | |
e1f3808e PB |
1057 | tcg_gen_not_i32(tmp, tmp); |
1058 | tcg_gen_and_i32(dest, src1, tmp); | |
e6e5906b PB |
1059 | break; |
1060 | case 3: /* bset */ | |
e1f3808e | 1061 | tcg_gen_or_i32(dest, src1, tmp); |
e6e5906b PB |
1062 | break; |
1063 | default: /* btst */ | |
1064 | break; | |
1065 | } | |
1066 | if (op) | |
d4d79bb1 | 1067 | DEST_EA(env, insn, opsize, dest, &addr); |
e6e5906b PB |
1068 | } |
1069 | ||
1070 | DISAS_INSN(sats) | |
1071 | { | |
e1f3808e | 1072 | TCGv reg; |
e6e5906b | 1073 | reg = DREG(insn, 0); |
e6e5906b | 1074 | gen_flush_flags(s); |
e1f3808e PB |
1075 | gen_helper_sats(reg, reg, QREG_CC_DEST); |
1076 | gen_logic_cc(s, reg); | |
e6e5906b PB |
1077 | } |
1078 | ||
e1f3808e | 1079 | static void gen_push(DisasContext *s, TCGv val) |
e6e5906b | 1080 | { |
e1f3808e | 1081 | TCGv tmp; |
e6e5906b | 1082 | |
a7812ae4 | 1083 | tmp = tcg_temp_new(); |
e1f3808e | 1084 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1085 | gen_store(s, OS_LONG, tmp, val); |
e1f3808e | 1086 | tcg_gen_mov_i32(QREG_SP, tmp); |
e6e5906b PB |
1087 | } |
1088 | ||
1089 | DISAS_INSN(movem) | |
1090 | { | |
e1f3808e | 1091 | TCGv addr; |
e6e5906b PB |
1092 | int i; |
1093 | uint16_t mask; | |
e1f3808e PB |
1094 | TCGv reg; |
1095 | TCGv tmp; | |
e6e5906b PB |
1096 | int is_load; |
1097 | ||
d4d79bb1 | 1098 | mask = cpu_lduw_code(env, s->pc); |
e6e5906b | 1099 | s->pc += 2; |
d4d79bb1 | 1100 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1101 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1102 | gen_addr_fault(s); |
1103 | return; | |
1104 | } | |
a7812ae4 | 1105 | addr = tcg_temp_new(); |
e1f3808e | 1106 | tcg_gen_mov_i32(addr, tmp); |
e6e5906b PB |
1107 | is_load = ((insn & 0x0400) != 0); |
1108 | for (i = 0; i < 16; i++, mask >>= 1) { | |
1109 | if (mask & 1) { | |
1110 | if (i < 8) | |
1111 | reg = DREG(i, 0); | |
1112 | else | |
1113 | reg = AREG(i, 0); | |
1114 | if (is_load) { | |
0633879f | 1115 | tmp = gen_load(s, OS_LONG, addr, 0); |
e1f3808e | 1116 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b | 1117 | } else { |
0633879f | 1118 | gen_store(s, OS_LONG, addr, reg); |
e6e5906b PB |
1119 | } |
1120 | if (mask != 1) | |
e1f3808e | 1121 | tcg_gen_addi_i32(addr, addr, 4); |
e6e5906b PB |
1122 | } |
1123 | } | |
1124 | } | |
1125 | ||
1126 | DISAS_INSN(bitop_im) | |
1127 | { | |
1128 | int opsize; | |
1129 | int op; | |
e1f3808e | 1130 | TCGv src1; |
e6e5906b PB |
1131 | uint32_t mask; |
1132 | int bitnum; | |
e1f3808e PB |
1133 | TCGv tmp; |
1134 | TCGv addr; | |
e6e5906b PB |
1135 | |
1136 | if ((insn & 0x38) != 0) | |
1137 | opsize = OS_BYTE; | |
1138 | else | |
1139 | opsize = OS_LONG; | |
1140 | op = (insn >> 6) & 3; | |
1141 | ||
d4d79bb1 | 1142 | bitnum = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
1143 | s->pc += 2; |
1144 | if (bitnum & 0xff00) { | |
d4d79bb1 | 1145 | disas_undef(env, s, insn); |
e6e5906b PB |
1146 | return; |
1147 | } | |
1148 | ||
d4d79bb1 | 1149 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b PB |
1150 | |
1151 | gen_flush_flags(s); | |
e6e5906b PB |
1152 | if (opsize == OS_BYTE) |
1153 | bitnum &= 7; | |
1154 | else | |
1155 | bitnum &= 31; | |
1156 | mask = 1 << bitnum; | |
1157 | ||
a7812ae4 | 1158 | tmp = tcg_temp_new(); |
e1f3808e PB |
1159 | assert (CCF_Z == (1 << 2)); |
1160 | if (bitnum > 2) | |
1161 | tcg_gen_shri_i32(tmp, src1, bitnum - 2); | |
1162 | else if (bitnum < 2) | |
1163 | tcg_gen_shli_i32(tmp, src1, 2 - bitnum); | |
e6e5906b | 1164 | else |
e1f3808e PB |
1165 | tcg_gen_mov_i32(tmp, src1); |
1166 | tcg_gen_andi_i32(tmp, tmp, CCF_Z); | |
1167 | /* Clear CCF_Z if bit set. */ | |
1168 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1169 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1170 | if (op) { | |
1171 | switch (op) { | |
1172 | case 1: /* bchg */ | |
1173 | tcg_gen_xori_i32(tmp, src1, mask); | |
1174 | break; | |
1175 | case 2: /* bclr */ | |
1176 | tcg_gen_andi_i32(tmp, src1, ~mask); | |
1177 | break; | |
1178 | case 3: /* bset */ | |
1179 | tcg_gen_ori_i32(tmp, src1, mask); | |
1180 | break; | |
1181 | default: /* btst */ | |
1182 | break; | |
1183 | } | |
d4d79bb1 | 1184 | DEST_EA(env, insn, opsize, tmp, &addr); |
e6e5906b | 1185 | } |
e6e5906b PB |
1186 | } |
1187 | ||
1188 | DISAS_INSN(arith_im) | |
1189 | { | |
1190 | int op; | |
e1f3808e PB |
1191 | uint32_t im; |
1192 | TCGv src1; | |
1193 | TCGv dest; | |
1194 | TCGv addr; | |
e6e5906b PB |
1195 | |
1196 | op = (insn >> 9) & 7; | |
d4d79bb1 BS |
1197 | SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr); |
1198 | im = read_im32(env, s); | |
a7812ae4 | 1199 | dest = tcg_temp_new(); |
e6e5906b PB |
1200 | switch (op) { |
1201 | case 0: /* ori */ | |
e1f3808e | 1202 | tcg_gen_ori_i32(dest, src1, im); |
e6e5906b PB |
1203 | gen_logic_cc(s, dest); |
1204 | break; | |
1205 | case 1: /* andi */ | |
e1f3808e | 1206 | tcg_gen_andi_i32(dest, src1, im); |
e6e5906b PB |
1207 | gen_logic_cc(s, dest); |
1208 | break; | |
1209 | case 2: /* subi */ | |
e1f3808e | 1210 | tcg_gen_mov_i32(dest, src1); |
351326a6 | 1211 | gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); |
e1f3808e | 1212 | tcg_gen_subi_i32(dest, dest, im); |
351326a6 | 1213 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1214 | s->cc_op = CC_OP_SUB; |
1215 | break; | |
1216 | case 3: /* addi */ | |
e1f3808e PB |
1217 | tcg_gen_mov_i32(dest, src1); |
1218 | tcg_gen_addi_i32(dest, dest, im); | |
351326a6 LV |
1219 | gen_update_cc_add(dest, tcg_const_i32(im)); |
1220 | gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); | |
e6e5906b PB |
1221 | s->cc_op = CC_OP_ADD; |
1222 | break; | |
1223 | case 5: /* eori */ | |
e1f3808e | 1224 | tcg_gen_xori_i32(dest, src1, im); |
e6e5906b PB |
1225 | gen_logic_cc(s, dest); |
1226 | break; | |
1227 | case 6: /* cmpi */ | |
e1f3808e PB |
1228 | tcg_gen_mov_i32(dest, src1); |
1229 | tcg_gen_subi_i32(dest, dest, im); | |
351326a6 | 1230 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1231 | s->cc_op = CC_OP_SUB; |
1232 | break; | |
1233 | default: | |
1234 | abort(); | |
1235 | } | |
1236 | if (op != 6) { | |
d4d79bb1 | 1237 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1238 | } |
1239 | } | |
1240 | ||
1241 | DISAS_INSN(byterev) | |
1242 | { | |
e1f3808e | 1243 | TCGv reg; |
e6e5906b PB |
1244 | |
1245 | reg = DREG(insn, 0); | |
66896cb8 | 1246 | tcg_gen_bswap32_i32(reg, reg); |
e6e5906b PB |
1247 | } |
1248 | ||
1249 | DISAS_INSN(move) | |
1250 | { | |
e1f3808e PB |
1251 | TCGv src; |
1252 | TCGv dest; | |
e6e5906b PB |
1253 | int op; |
1254 | int opsize; | |
1255 | ||
1256 | switch (insn >> 12) { | |
1257 | case 1: /* move.b */ | |
1258 | opsize = OS_BYTE; | |
1259 | break; | |
1260 | case 2: /* move.l */ | |
1261 | opsize = OS_LONG; | |
1262 | break; | |
1263 | case 3: /* move.w */ | |
1264 | opsize = OS_WORD; | |
1265 | break; | |
1266 | default: | |
1267 | abort(); | |
1268 | } | |
d4d79bb1 | 1269 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b PB |
1270 | op = (insn >> 6) & 7; |
1271 | if (op == 1) { | |
1272 | /* movea */ | |
1273 | /* The value will already have been sign extended. */ | |
1274 | dest = AREG(insn, 9); | |
e1f3808e | 1275 | tcg_gen_mov_i32(dest, src); |
e6e5906b PB |
1276 | } else { |
1277 | /* normal move */ | |
1278 | uint16_t dest_ea; | |
1279 | dest_ea = ((insn >> 9) & 7) | (op << 3); | |
d4d79bb1 | 1280 | DEST_EA(env, dest_ea, opsize, src, NULL); |
e6e5906b PB |
1281 | /* This will be correct because loads sign extend. */ |
1282 | gen_logic_cc(s, src); | |
1283 | } | |
1284 | } | |
1285 | ||
1286 | DISAS_INSN(negx) | |
1287 | { | |
e1f3808e | 1288 | TCGv reg; |
e6e5906b PB |
1289 | |
1290 | gen_flush_flags(s); | |
1291 | reg = DREG(insn, 0); | |
e1f3808e | 1292 | gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg); |
e6e5906b PB |
1293 | } |
1294 | ||
1295 | DISAS_INSN(lea) | |
1296 | { | |
e1f3808e PB |
1297 | TCGv reg; |
1298 | TCGv tmp; | |
e6e5906b PB |
1299 | |
1300 | reg = AREG(insn, 9); | |
d4d79bb1 | 1301 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1302 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1303 | gen_addr_fault(s); |
1304 | return; | |
1305 | } | |
e1f3808e | 1306 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1307 | } |
1308 | ||
1309 | DISAS_INSN(clr) | |
1310 | { | |
1311 | int opsize; | |
1312 | ||
1313 | switch ((insn >> 6) & 3) { | |
1314 | case 0: /* clr.b */ | |
1315 | opsize = OS_BYTE; | |
1316 | break; | |
1317 | case 1: /* clr.w */ | |
1318 | opsize = OS_WORD; | |
1319 | break; | |
1320 | case 2: /* clr.l */ | |
1321 | opsize = OS_LONG; | |
1322 | break; | |
1323 | default: | |
1324 | abort(); | |
1325 | } | |
d4d79bb1 | 1326 | DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL); |
351326a6 | 1327 | gen_logic_cc(s, tcg_const_i32(0)); |
e6e5906b PB |
1328 | } |
1329 | ||
e1f3808e | 1330 | static TCGv gen_get_ccr(DisasContext *s) |
e6e5906b | 1331 | { |
e1f3808e | 1332 | TCGv dest; |
e6e5906b PB |
1333 | |
1334 | gen_flush_flags(s); | |
a7812ae4 | 1335 | dest = tcg_temp_new(); |
e1f3808e PB |
1336 | tcg_gen_shli_i32(dest, QREG_CC_X, 4); |
1337 | tcg_gen_or_i32(dest, dest, QREG_CC_DEST); | |
0633879f PB |
1338 | return dest; |
1339 | } | |
1340 | ||
1341 | DISAS_INSN(move_from_ccr) | |
1342 | { | |
e1f3808e PB |
1343 | TCGv reg; |
1344 | TCGv ccr; | |
0633879f PB |
1345 | |
1346 | ccr = gen_get_ccr(s); | |
e6e5906b | 1347 | reg = DREG(insn, 0); |
0633879f | 1348 | gen_partset_reg(OS_WORD, reg, ccr); |
e6e5906b PB |
1349 | } |
1350 | ||
1351 | DISAS_INSN(neg) | |
1352 | { | |
e1f3808e PB |
1353 | TCGv reg; |
1354 | TCGv src1; | |
e6e5906b PB |
1355 | |
1356 | reg = DREG(insn, 0); | |
a7812ae4 | 1357 | src1 = tcg_temp_new(); |
e1f3808e PB |
1358 | tcg_gen_mov_i32(src1, reg); |
1359 | tcg_gen_neg_i32(reg, src1); | |
e6e5906b | 1360 | s->cc_op = CC_OP_SUB; |
e1f3808e PB |
1361 | gen_update_cc_add(reg, src1); |
1362 | gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1); | |
e6e5906b PB |
1363 | s->cc_op = CC_OP_SUB; |
1364 | } | |
1365 | ||
0633879f PB |
1366 | static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) |
1367 | { | |
e1f3808e PB |
1368 | tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf); |
1369 | tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4); | |
0633879f | 1370 | if (!ccr_only) { |
e1f3808e | 1371 | gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00)); |
0633879f PB |
1372 | } |
1373 | } | |
1374 | ||
d4d79bb1 BS |
1375 | static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, |
1376 | int ccr_only) | |
e6e5906b | 1377 | { |
e1f3808e PB |
1378 | TCGv tmp; |
1379 | TCGv reg; | |
e6e5906b PB |
1380 | |
1381 | s->cc_op = CC_OP_FLAGS; | |
1382 | if ((insn & 0x38) == 0) | |
1383 | { | |
a7812ae4 | 1384 | tmp = tcg_temp_new(); |
e6e5906b | 1385 | reg = DREG(insn, 0); |
e1f3808e PB |
1386 | tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf); |
1387 | tcg_gen_shri_i32(tmp, reg, 4); | |
1388 | tcg_gen_andi_i32(QREG_CC_X, tmp, 1); | |
0633879f | 1389 | if (!ccr_only) { |
e1f3808e | 1390 | gen_helper_set_sr(cpu_env, reg); |
0633879f | 1391 | } |
e6e5906b | 1392 | } |
0633879f | 1393 | else if ((insn & 0x3f) == 0x3c) |
e6e5906b | 1394 | { |
0633879f | 1395 | uint16_t val; |
d4d79bb1 | 1396 | val = cpu_lduw_code(env, s->pc); |
e6e5906b | 1397 | s->pc += 2; |
0633879f | 1398 | gen_set_sr_im(s, val, ccr_only); |
e6e5906b PB |
1399 | } |
1400 | else | |
d4d79bb1 | 1401 | disas_undef(env, s, insn); |
e6e5906b PB |
1402 | } |
1403 | ||
0633879f PB |
1404 | DISAS_INSN(move_to_ccr) |
1405 | { | |
d4d79bb1 | 1406 | gen_set_sr(env, s, insn, 1); |
0633879f PB |
1407 | } |
1408 | ||
e6e5906b PB |
1409 | DISAS_INSN(not) |
1410 | { | |
e1f3808e | 1411 | TCGv reg; |
e6e5906b PB |
1412 | |
1413 | reg = DREG(insn, 0); | |
e1f3808e | 1414 | tcg_gen_not_i32(reg, reg); |
e6e5906b PB |
1415 | gen_logic_cc(s, reg); |
1416 | } | |
1417 | ||
1418 | DISAS_INSN(swap) | |
1419 | { | |
e1f3808e PB |
1420 | TCGv src1; |
1421 | TCGv src2; | |
1422 | TCGv reg; | |
e6e5906b | 1423 | |
a7812ae4 PB |
1424 | src1 = tcg_temp_new(); |
1425 | src2 = tcg_temp_new(); | |
e6e5906b | 1426 | reg = DREG(insn, 0); |
e1f3808e PB |
1427 | tcg_gen_shli_i32(src1, reg, 16); |
1428 | tcg_gen_shri_i32(src2, reg, 16); | |
1429 | tcg_gen_or_i32(reg, src1, src2); | |
1430 | gen_logic_cc(s, reg); | |
e6e5906b PB |
1431 | } |
1432 | ||
1433 | DISAS_INSN(pea) | |
1434 | { | |
e1f3808e | 1435 | TCGv tmp; |
e6e5906b | 1436 | |
d4d79bb1 | 1437 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1438 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1439 | gen_addr_fault(s); |
1440 | return; | |
1441 | } | |
0633879f | 1442 | gen_push(s, tmp); |
e6e5906b PB |
1443 | } |
1444 | ||
1445 | DISAS_INSN(ext) | |
1446 | { | |
e6e5906b | 1447 | int op; |
e1f3808e PB |
1448 | TCGv reg; |
1449 | TCGv tmp; | |
e6e5906b PB |
1450 | |
1451 | reg = DREG(insn, 0); | |
1452 | op = (insn >> 6) & 7; | |
a7812ae4 | 1453 | tmp = tcg_temp_new(); |
e6e5906b | 1454 | if (op == 3) |
e1f3808e | 1455 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1456 | else |
e1f3808e | 1457 | tcg_gen_ext8s_i32(tmp, reg); |
e6e5906b PB |
1458 | if (op == 2) |
1459 | gen_partset_reg(OS_WORD, reg, tmp); | |
1460 | else | |
e1f3808e | 1461 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1462 | gen_logic_cc(s, tmp); |
1463 | } | |
1464 | ||
1465 | DISAS_INSN(tst) | |
1466 | { | |
1467 | int opsize; | |
e1f3808e | 1468 | TCGv tmp; |
e6e5906b PB |
1469 | |
1470 | switch ((insn >> 6) & 3) { | |
1471 | case 0: /* tst.b */ | |
1472 | opsize = OS_BYTE; | |
1473 | break; | |
1474 | case 1: /* tst.w */ | |
1475 | opsize = OS_WORD; | |
1476 | break; | |
1477 | case 2: /* tst.l */ | |
1478 | opsize = OS_LONG; | |
1479 | break; | |
1480 | default: | |
1481 | abort(); | |
1482 | } | |
d4d79bb1 | 1483 | SRC_EA(env, tmp, opsize, 1, NULL); |
e6e5906b PB |
1484 | gen_logic_cc(s, tmp); |
1485 | } | |
1486 | ||
1487 | DISAS_INSN(pulse) | |
1488 | { | |
1489 | /* Implemented as a NOP. */ | |
1490 | } | |
1491 | ||
1492 | DISAS_INSN(illegal) | |
1493 | { | |
1494 | gen_exception(s, s->pc - 2, EXCP_ILLEGAL); | |
1495 | } | |
1496 | ||
1497 | /* ??? This should be atomic. */ | |
1498 | DISAS_INSN(tas) | |
1499 | { | |
e1f3808e PB |
1500 | TCGv dest; |
1501 | TCGv src1; | |
1502 | TCGv addr; | |
e6e5906b | 1503 | |
a7812ae4 | 1504 | dest = tcg_temp_new(); |
d4d79bb1 | 1505 | SRC_EA(env, src1, OS_BYTE, 1, &addr); |
e6e5906b | 1506 | gen_logic_cc(s, src1); |
e1f3808e | 1507 | tcg_gen_ori_i32(dest, src1, 0x80); |
d4d79bb1 | 1508 | DEST_EA(env, insn, OS_BYTE, dest, &addr); |
e6e5906b PB |
1509 | } |
1510 | ||
1511 | DISAS_INSN(mull) | |
1512 | { | |
1513 | uint16_t ext; | |
e1f3808e PB |
1514 | TCGv reg; |
1515 | TCGv src1; | |
1516 | TCGv dest; | |
e6e5906b PB |
1517 | |
1518 | /* The upper 32 bits of the product are discarded, so | |
1519 | muls.l and mulu.l are functionally equivalent. */ | |
d4d79bb1 | 1520 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
1521 | s->pc += 2; |
1522 | if (ext & 0x87ff) { | |
1523 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
1524 | return; | |
1525 | } | |
1526 | reg = DREG(ext, 12); | |
d4d79bb1 | 1527 | SRC_EA(env, src1, OS_LONG, 0, NULL); |
a7812ae4 | 1528 | dest = tcg_temp_new(); |
e1f3808e PB |
1529 | tcg_gen_mul_i32(dest, src1, reg); |
1530 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1531 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
1532 | gen_logic_cc(s, dest); | |
1533 | } | |
1534 | ||
1535 | DISAS_INSN(link) | |
1536 | { | |
1537 | int16_t offset; | |
e1f3808e PB |
1538 | TCGv reg; |
1539 | TCGv tmp; | |
e6e5906b | 1540 | |
d4d79bb1 | 1541 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1542 | s->pc += 2; |
1543 | reg = AREG(insn, 0); | |
a7812ae4 | 1544 | tmp = tcg_temp_new(); |
e1f3808e | 1545 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1546 | gen_store(s, OS_LONG, tmp, reg); |
e1f3808e PB |
1547 | if ((insn & 7) != 7) |
1548 | tcg_gen_mov_i32(reg, tmp); | |
1549 | tcg_gen_addi_i32(QREG_SP, tmp, offset); | |
e6e5906b PB |
1550 | } |
1551 | ||
1552 | DISAS_INSN(unlk) | |
1553 | { | |
e1f3808e PB |
1554 | TCGv src; |
1555 | TCGv reg; | |
1556 | TCGv tmp; | |
e6e5906b | 1557 | |
a7812ae4 | 1558 | src = tcg_temp_new(); |
e6e5906b | 1559 | reg = AREG(insn, 0); |
e1f3808e | 1560 | tcg_gen_mov_i32(src, reg); |
0633879f | 1561 | tmp = gen_load(s, OS_LONG, src, 0); |
e1f3808e PB |
1562 | tcg_gen_mov_i32(reg, tmp); |
1563 | tcg_gen_addi_i32(QREG_SP, src, 4); | |
e6e5906b PB |
1564 | } |
1565 | ||
1566 | DISAS_INSN(nop) | |
1567 | { | |
1568 | } | |
1569 | ||
1570 | DISAS_INSN(rts) | |
1571 | { | |
e1f3808e | 1572 | TCGv tmp; |
e6e5906b | 1573 | |
0633879f | 1574 | tmp = gen_load(s, OS_LONG, QREG_SP, 0); |
e1f3808e | 1575 | tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); |
e6e5906b PB |
1576 | gen_jmp(s, tmp); |
1577 | } | |
1578 | ||
1579 | DISAS_INSN(jump) | |
1580 | { | |
e1f3808e | 1581 | TCGv tmp; |
e6e5906b PB |
1582 | |
1583 | /* Load the target address first to ensure correct exception | |
1584 | behavior. */ | |
d4d79bb1 | 1585 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1586 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1587 | gen_addr_fault(s); |
1588 | return; | |
1589 | } | |
e6e5906b PB |
1590 | if ((insn & 0x40) == 0) { |
1591 | /* jsr */ | |
351326a6 | 1592 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1593 | } |
1594 | gen_jmp(s, tmp); | |
1595 | } | |
1596 | ||
1597 | DISAS_INSN(addsubq) | |
1598 | { | |
e1f3808e PB |
1599 | TCGv src1; |
1600 | TCGv src2; | |
1601 | TCGv dest; | |
e6e5906b | 1602 | int val; |
e1f3808e | 1603 | TCGv addr; |
e6e5906b | 1604 | |
d4d79bb1 | 1605 | SRC_EA(env, src1, OS_LONG, 0, &addr); |
e6e5906b PB |
1606 | val = (insn >> 9) & 7; |
1607 | if (val == 0) | |
1608 | val = 8; | |
a7812ae4 | 1609 | dest = tcg_temp_new(); |
e1f3808e | 1610 | tcg_gen_mov_i32(dest, src1); |
e6e5906b PB |
1611 | if ((insn & 0x38) == 0x08) { |
1612 | /* Don't update condition codes if the destination is an | |
1613 | address register. */ | |
1614 | if (insn & 0x0100) { | |
e1f3808e | 1615 | tcg_gen_subi_i32(dest, dest, val); |
e6e5906b | 1616 | } else { |
e1f3808e | 1617 | tcg_gen_addi_i32(dest, dest, val); |
e6e5906b PB |
1618 | } |
1619 | } else { | |
351326a6 | 1620 | src2 = tcg_const_i32(val); |
e6e5906b | 1621 | if (insn & 0x0100) { |
e1f3808e PB |
1622 | gen_helper_xflag_lt(QREG_CC_X, dest, src2); |
1623 | tcg_gen_subi_i32(dest, dest, val); | |
e6e5906b PB |
1624 | s->cc_op = CC_OP_SUB; |
1625 | } else { | |
e1f3808e PB |
1626 | tcg_gen_addi_i32(dest, dest, val); |
1627 | gen_helper_xflag_lt(QREG_CC_X, dest, src2); | |
e6e5906b PB |
1628 | s->cc_op = CC_OP_ADD; |
1629 | } | |
e1f3808e | 1630 | gen_update_cc_add(dest, src2); |
e6e5906b | 1631 | } |
d4d79bb1 | 1632 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1633 | } |
1634 | ||
1635 | DISAS_INSN(tpf) | |
1636 | { | |
1637 | switch (insn & 7) { | |
1638 | case 2: /* One extension word. */ | |
1639 | s->pc += 2; | |
1640 | break; | |
1641 | case 3: /* Two extension words. */ | |
1642 | s->pc += 4; | |
1643 | break; | |
1644 | case 4: /* No extension words. */ | |
1645 | break; | |
1646 | default: | |
d4d79bb1 | 1647 | disas_undef(env, s, insn); |
e6e5906b PB |
1648 | } |
1649 | } | |
1650 | ||
1651 | DISAS_INSN(branch) | |
1652 | { | |
1653 | int32_t offset; | |
1654 | uint32_t base; | |
1655 | int op; | |
42a268c2 | 1656 | TCGLabel *l1; |
3b46e624 | 1657 | |
e6e5906b PB |
1658 | base = s->pc; |
1659 | op = (insn >> 8) & 0xf; | |
1660 | offset = (int8_t)insn; | |
1661 | if (offset == 0) { | |
d4d79bb1 | 1662 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1663 | s->pc += 2; |
1664 | } else if (offset == -1) { | |
d4d79bb1 | 1665 | offset = read_im32(env, s); |
e6e5906b PB |
1666 | } |
1667 | if (op == 1) { | |
1668 | /* bsr */ | |
351326a6 | 1669 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1670 | } |
1671 | gen_flush_cc_op(s); | |
1672 | if (op > 1) { | |
1673 | /* Bcc */ | |
1674 | l1 = gen_new_label(); | |
1675 | gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); | |
1676 | gen_jmp_tb(s, 1, base + offset); | |
1677 | gen_set_label(l1); | |
1678 | gen_jmp_tb(s, 0, s->pc); | |
1679 | } else { | |
1680 | /* Unconditional branch. */ | |
1681 | gen_jmp_tb(s, 0, base + offset); | |
1682 | } | |
1683 | } | |
1684 | ||
1685 | DISAS_INSN(moveq) | |
1686 | { | |
e1f3808e | 1687 | uint32_t val; |
e6e5906b | 1688 | |
e1f3808e PB |
1689 | val = (int8_t)insn; |
1690 | tcg_gen_movi_i32(DREG(insn, 9), val); | |
1691 | gen_logic_cc(s, tcg_const_i32(val)); | |
e6e5906b PB |
1692 | } |
1693 | ||
1694 | DISAS_INSN(mvzs) | |
1695 | { | |
1696 | int opsize; | |
e1f3808e PB |
1697 | TCGv src; |
1698 | TCGv reg; | |
e6e5906b PB |
1699 | |
1700 | if (insn & 0x40) | |
1701 | opsize = OS_WORD; | |
1702 | else | |
1703 | opsize = OS_BYTE; | |
d4d79bb1 | 1704 | SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); |
e6e5906b | 1705 | reg = DREG(insn, 9); |
e1f3808e | 1706 | tcg_gen_mov_i32(reg, src); |
e6e5906b PB |
1707 | gen_logic_cc(s, src); |
1708 | } | |
1709 | ||
1710 | DISAS_INSN(or) | |
1711 | { | |
e1f3808e PB |
1712 | TCGv reg; |
1713 | TCGv dest; | |
1714 | TCGv src; | |
1715 | TCGv addr; | |
e6e5906b PB |
1716 | |
1717 | reg = DREG(insn, 9); | |
a7812ae4 | 1718 | dest = tcg_temp_new(); |
e6e5906b | 1719 | if (insn & 0x100) { |
d4d79bb1 | 1720 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1721 | tcg_gen_or_i32(dest, src, reg); |
d4d79bb1 | 1722 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1723 | } else { |
d4d79bb1 | 1724 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1725 | tcg_gen_or_i32(dest, src, reg); |
1726 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1727 | } |
1728 | gen_logic_cc(s, dest); | |
1729 | } | |
1730 | ||
1731 | DISAS_INSN(suba) | |
1732 | { | |
e1f3808e PB |
1733 | TCGv src; |
1734 | TCGv reg; | |
e6e5906b | 1735 | |
d4d79bb1 | 1736 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1737 | reg = AREG(insn, 9); |
e1f3808e | 1738 | tcg_gen_sub_i32(reg, reg, src); |
e6e5906b PB |
1739 | } |
1740 | ||
1741 | DISAS_INSN(subx) | |
1742 | { | |
e1f3808e PB |
1743 | TCGv reg; |
1744 | TCGv src; | |
e6e5906b PB |
1745 | |
1746 | gen_flush_flags(s); | |
1747 | reg = DREG(insn, 9); | |
1748 | src = DREG(insn, 0); | |
e1f3808e | 1749 | gen_helper_subx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1750 | } |
1751 | ||
1752 | DISAS_INSN(mov3q) | |
1753 | { | |
e1f3808e | 1754 | TCGv src; |
e6e5906b PB |
1755 | int val; |
1756 | ||
1757 | val = (insn >> 9) & 7; | |
1758 | if (val == 0) | |
1759 | val = -1; | |
351326a6 | 1760 | src = tcg_const_i32(val); |
e6e5906b | 1761 | gen_logic_cc(s, src); |
d4d79bb1 | 1762 | DEST_EA(env, insn, OS_LONG, src, NULL); |
e6e5906b PB |
1763 | } |
1764 | ||
1765 | DISAS_INSN(cmp) | |
1766 | { | |
1767 | int op; | |
e1f3808e PB |
1768 | TCGv src; |
1769 | TCGv reg; | |
1770 | TCGv dest; | |
e6e5906b PB |
1771 | int opsize; |
1772 | ||
1773 | op = (insn >> 6) & 3; | |
1774 | switch (op) { | |
1775 | case 0: /* cmp.b */ | |
1776 | opsize = OS_BYTE; | |
1777 | s->cc_op = CC_OP_CMPB; | |
1778 | break; | |
1779 | case 1: /* cmp.w */ | |
1780 | opsize = OS_WORD; | |
1781 | s->cc_op = CC_OP_CMPW; | |
1782 | break; | |
1783 | case 2: /* cmp.l */ | |
1784 | opsize = OS_LONG; | |
1785 | s->cc_op = CC_OP_SUB; | |
1786 | break; | |
1787 | default: | |
1788 | abort(); | |
1789 | } | |
d4d79bb1 | 1790 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1791 | reg = DREG(insn, 9); |
a7812ae4 | 1792 | dest = tcg_temp_new(); |
e1f3808e PB |
1793 | tcg_gen_sub_i32(dest, reg, src); |
1794 | gen_update_cc_add(dest, src); | |
e6e5906b PB |
1795 | } |
1796 | ||
1797 | DISAS_INSN(cmpa) | |
1798 | { | |
1799 | int opsize; | |
e1f3808e PB |
1800 | TCGv src; |
1801 | TCGv reg; | |
1802 | TCGv dest; | |
e6e5906b PB |
1803 | |
1804 | if (insn & 0x100) { | |
1805 | opsize = OS_LONG; | |
1806 | } else { | |
1807 | opsize = OS_WORD; | |
1808 | } | |
d4d79bb1 | 1809 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1810 | reg = AREG(insn, 9); |
a7812ae4 | 1811 | dest = tcg_temp_new(); |
e1f3808e PB |
1812 | tcg_gen_sub_i32(dest, reg, src); |
1813 | gen_update_cc_add(dest, src); | |
e6e5906b PB |
1814 | s->cc_op = CC_OP_SUB; |
1815 | } | |
1816 | ||
1817 | DISAS_INSN(eor) | |
1818 | { | |
e1f3808e PB |
1819 | TCGv src; |
1820 | TCGv reg; | |
1821 | TCGv dest; | |
1822 | TCGv addr; | |
e6e5906b | 1823 | |
d4d79bb1 | 1824 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e6e5906b | 1825 | reg = DREG(insn, 9); |
a7812ae4 | 1826 | dest = tcg_temp_new(); |
e1f3808e | 1827 | tcg_gen_xor_i32(dest, src, reg); |
e6e5906b | 1828 | gen_logic_cc(s, dest); |
d4d79bb1 | 1829 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1830 | } |
1831 | ||
1832 | DISAS_INSN(and) | |
1833 | { | |
e1f3808e PB |
1834 | TCGv src; |
1835 | TCGv reg; | |
1836 | TCGv dest; | |
1837 | TCGv addr; | |
e6e5906b PB |
1838 | |
1839 | reg = DREG(insn, 9); | |
a7812ae4 | 1840 | dest = tcg_temp_new(); |
e6e5906b | 1841 | if (insn & 0x100) { |
d4d79bb1 | 1842 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1843 | tcg_gen_and_i32(dest, src, reg); |
d4d79bb1 | 1844 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1845 | } else { |
d4d79bb1 | 1846 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1847 | tcg_gen_and_i32(dest, src, reg); |
1848 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b PB |
1849 | } |
1850 | gen_logic_cc(s, dest); | |
1851 | } | |
1852 | ||
1853 | DISAS_INSN(adda) | |
1854 | { | |
e1f3808e PB |
1855 | TCGv src; |
1856 | TCGv reg; | |
e6e5906b | 1857 | |
d4d79bb1 | 1858 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1859 | reg = AREG(insn, 9); |
e1f3808e | 1860 | tcg_gen_add_i32(reg, reg, src); |
e6e5906b PB |
1861 | } |
1862 | ||
1863 | DISAS_INSN(addx) | |
1864 | { | |
e1f3808e PB |
1865 | TCGv reg; |
1866 | TCGv src; | |
e6e5906b PB |
1867 | |
1868 | gen_flush_flags(s); | |
1869 | reg = DREG(insn, 9); | |
1870 | src = DREG(insn, 0); | |
e1f3808e | 1871 | gen_helper_addx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1872 | s->cc_op = CC_OP_FLAGS; |
1873 | } | |
1874 | ||
e1f3808e | 1875 | /* TODO: This could be implemented without helper functions. */ |
e6e5906b PB |
1876 | DISAS_INSN(shift_im) |
1877 | { | |
e1f3808e | 1878 | TCGv reg; |
e6e5906b | 1879 | int tmp; |
e1f3808e | 1880 | TCGv shift; |
e6e5906b PB |
1881 | |
1882 | reg = DREG(insn, 0); | |
1883 | tmp = (insn >> 9) & 7; | |
1884 | if (tmp == 0) | |
e1f3808e | 1885 | tmp = 8; |
351326a6 | 1886 | shift = tcg_const_i32(tmp); |
e1f3808e | 1887 | /* No need to flush flags becuse we know we will set C flag. */ |
e6e5906b | 1888 | if (insn & 0x100) { |
e1f3808e | 1889 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1890 | } else { |
1891 | if (insn & 8) { | |
e1f3808e | 1892 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1893 | } else { |
e1f3808e | 1894 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1895 | } |
1896 | } | |
e1f3808e | 1897 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1898 | } |
1899 | ||
1900 | DISAS_INSN(shift_reg) | |
1901 | { | |
e1f3808e PB |
1902 | TCGv reg; |
1903 | TCGv shift; | |
e6e5906b PB |
1904 | |
1905 | reg = DREG(insn, 0); | |
e1f3808e PB |
1906 | shift = DREG(insn, 9); |
1907 | /* Shift by zero leaves C flag unmodified. */ | |
1908 | gen_flush_flags(s); | |
e6e5906b | 1909 | if (insn & 0x100) { |
e1f3808e | 1910 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1911 | } else { |
1912 | if (insn & 8) { | |
e1f3808e | 1913 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1914 | } else { |
e1f3808e | 1915 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1916 | } |
1917 | } | |
e1f3808e | 1918 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1919 | } |
1920 | ||
1921 | DISAS_INSN(ff1) | |
1922 | { | |
e1f3808e | 1923 | TCGv reg; |
821f7e76 PB |
1924 | reg = DREG(insn, 0); |
1925 | gen_logic_cc(s, reg); | |
e1f3808e | 1926 | gen_helper_ff1(reg, reg); |
e6e5906b PB |
1927 | } |
1928 | ||
e1f3808e | 1929 | static TCGv gen_get_sr(DisasContext *s) |
0633879f | 1930 | { |
e1f3808e PB |
1931 | TCGv ccr; |
1932 | TCGv sr; | |
0633879f PB |
1933 | |
1934 | ccr = gen_get_ccr(s); | |
a7812ae4 | 1935 | sr = tcg_temp_new(); |
e1f3808e PB |
1936 | tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); |
1937 | tcg_gen_or_i32(sr, sr, ccr); | |
0633879f PB |
1938 | return sr; |
1939 | } | |
1940 | ||
e6e5906b PB |
1941 | DISAS_INSN(strldsr) |
1942 | { | |
1943 | uint16_t ext; | |
1944 | uint32_t addr; | |
1945 | ||
1946 | addr = s->pc - 2; | |
d4d79bb1 | 1947 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b | 1948 | s->pc += 2; |
0633879f | 1949 | if (ext != 0x46FC) { |
e6e5906b | 1950 | gen_exception(s, addr, EXCP_UNSUPPORTED); |
0633879f PB |
1951 | return; |
1952 | } | |
d4d79bb1 | 1953 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
1954 | s->pc += 2; |
1955 | if (IS_USER(s) || (ext & SR_S) == 0) { | |
e6e5906b | 1956 | gen_exception(s, addr, EXCP_PRIVILEGE); |
0633879f PB |
1957 | return; |
1958 | } | |
1959 | gen_push(s, gen_get_sr(s)); | |
1960 | gen_set_sr_im(s, ext, 0); | |
e6e5906b PB |
1961 | } |
1962 | ||
1963 | DISAS_INSN(move_from_sr) | |
1964 | { | |
e1f3808e PB |
1965 | TCGv reg; |
1966 | TCGv sr; | |
0633879f PB |
1967 | |
1968 | if (IS_USER(s)) { | |
1969 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1970 | return; | |
1971 | } | |
1972 | sr = gen_get_sr(s); | |
1973 | reg = DREG(insn, 0); | |
1974 | gen_partset_reg(OS_WORD, reg, sr); | |
e6e5906b PB |
1975 | } |
1976 | ||
1977 | DISAS_INSN(move_to_sr) | |
1978 | { | |
0633879f PB |
1979 | if (IS_USER(s)) { |
1980 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1981 | return; | |
1982 | } | |
d4d79bb1 | 1983 | gen_set_sr(env, s, insn, 0); |
0633879f | 1984 | gen_lookup_tb(s); |
e6e5906b PB |
1985 | } |
1986 | ||
1987 | DISAS_INSN(move_from_usp) | |
1988 | { | |
0633879f PB |
1989 | if (IS_USER(s)) { |
1990 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1991 | return; | |
1992 | } | |
2a8327e8 GU |
1993 | tcg_gen_ld_i32(AREG(insn, 0), cpu_env, |
1994 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
1995 | } |
1996 | ||
1997 | DISAS_INSN(move_to_usp) | |
1998 | { | |
0633879f PB |
1999 | if (IS_USER(s)) { |
2000 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2001 | return; | |
2002 | } | |
2a8327e8 GU |
2003 | tcg_gen_st_i32(AREG(insn, 0), cpu_env, |
2004 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2005 | } |
2006 | ||
2007 | DISAS_INSN(halt) | |
2008 | { | |
e1f3808e | 2009 | gen_exception(s, s->pc, EXCP_HALT_INSN); |
e6e5906b PB |
2010 | } |
2011 | ||
2012 | DISAS_INSN(stop) | |
2013 | { | |
0633879f PB |
2014 | uint16_t ext; |
2015 | ||
2016 | if (IS_USER(s)) { | |
2017 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2018 | return; | |
2019 | } | |
2020 | ||
d4d79bb1 | 2021 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
2022 | s->pc += 2; |
2023 | ||
2024 | gen_set_sr_im(s, ext, 0); | |
259186a7 | 2025 | tcg_gen_movi_i32(cpu_halted, 1); |
e1f3808e | 2026 | gen_exception(s, s->pc, EXCP_HLT); |
e6e5906b PB |
2027 | } |
2028 | ||
2029 | DISAS_INSN(rte) | |
2030 | { | |
0633879f PB |
2031 | if (IS_USER(s)) { |
2032 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2033 | return; | |
2034 | } | |
2035 | gen_exception(s, s->pc - 2, EXCP_RTE); | |
e6e5906b PB |
2036 | } |
2037 | ||
2038 | DISAS_INSN(movec) | |
2039 | { | |
0633879f | 2040 | uint16_t ext; |
e1f3808e | 2041 | TCGv reg; |
0633879f PB |
2042 | |
2043 | if (IS_USER(s)) { | |
2044 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2045 | return; | |
2046 | } | |
2047 | ||
d4d79bb1 | 2048 | ext = cpu_lduw_code(env, s->pc); |
0633879f PB |
2049 | s->pc += 2; |
2050 | ||
2051 | if (ext & 0x8000) { | |
2052 | reg = AREG(ext, 12); | |
2053 | } else { | |
2054 | reg = DREG(ext, 12); | |
2055 | } | |
e1f3808e | 2056 | gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); |
0633879f | 2057 | gen_lookup_tb(s); |
e6e5906b PB |
2058 | } |
2059 | ||
2060 | DISAS_INSN(intouch) | |
2061 | { | |
0633879f PB |
2062 | if (IS_USER(s)) { |
2063 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2064 | return; | |
2065 | } | |
2066 | /* ICache fetch. Implement as no-op. */ | |
e6e5906b PB |
2067 | } |
2068 | ||
2069 | DISAS_INSN(cpushl) | |
2070 | { | |
0633879f PB |
2071 | if (IS_USER(s)) { |
2072 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2073 | return; | |
2074 | } | |
2075 | /* Cache push/invalidate. Implement as no-op. */ | |
e6e5906b PB |
2076 | } |
2077 | ||
2078 | DISAS_INSN(wddata) | |
2079 | { | |
2080 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2081 | } | |
2082 | ||
2083 | DISAS_INSN(wdebug) | |
2084 | { | |
a47dddd7 AF |
2085 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2086 | ||
0633879f PB |
2087 | if (IS_USER(s)) { |
2088 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2089 | return; | |
2090 | } | |
2091 | /* TODO: Implement wdebug. */ | |
a47dddd7 | 2092 | cpu_abort(CPU(cpu), "WDEBUG not implemented"); |
e6e5906b PB |
2093 | } |
2094 | ||
2095 | DISAS_INSN(trap) | |
2096 | { | |
2097 | gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); | |
2098 | } | |
2099 | ||
2100 | /* ??? FP exceptions are not implemented. Most exceptions are deferred until | |
2101 | immediately before the next FP instruction is executed. */ | |
2102 | DISAS_INSN(fpu) | |
2103 | { | |
2104 | uint16_t ext; | |
a7812ae4 | 2105 | int32_t offset; |
e6e5906b | 2106 | int opmode; |
a7812ae4 PB |
2107 | TCGv_i64 src; |
2108 | TCGv_i64 dest; | |
2109 | TCGv_i64 res; | |
2110 | TCGv tmp32; | |
e6e5906b | 2111 | int round; |
a7812ae4 | 2112 | int set_dest; |
e6e5906b PB |
2113 | int opsize; |
2114 | ||
d4d79bb1 | 2115 | ext = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2116 | s->pc += 2; |
2117 | opmode = ext & 0x7f; | |
2118 | switch ((ext >> 13) & 7) { | |
2119 | case 0: case 2: | |
2120 | break; | |
2121 | case 1: | |
2122 | goto undef; | |
2123 | case 3: /* fmove out */ | |
2124 | src = FREG(ext, 7); | |
a7812ae4 | 2125 | tmp32 = tcg_temp_new_i32(); |
e6e5906b PB |
2126 | /* fmove */ |
2127 | /* ??? TODO: Proper behavior on overflow. */ | |
2128 | switch ((ext >> 10) & 7) { | |
2129 | case 0: | |
2130 | opsize = OS_LONG; | |
a7812ae4 | 2131 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2132 | break; |
2133 | case 1: | |
2134 | opsize = OS_SINGLE; | |
a7812ae4 | 2135 | gen_helper_f64_to_f32(tmp32, cpu_env, src); |
e6e5906b PB |
2136 | break; |
2137 | case 4: | |
2138 | opsize = OS_WORD; | |
a7812ae4 | 2139 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b | 2140 | break; |
a7812ae4 PB |
2141 | case 5: /* OS_DOUBLE */ |
2142 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2143 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2144 | case 2: |
2145 | case 3: | |
243ee8f7 | 2146 | break; |
a7812ae4 PB |
2147 | case 4: |
2148 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2149 | break; | |
2150 | case 5: | |
d4d79bb1 | 2151 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2152 | s->pc += 2; |
2153 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2154 | break; | |
2155 | default: | |
2156 | goto undef; | |
2157 | } | |
2158 | gen_store64(s, tmp32, src); | |
c59b97aa | 2159 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2160 | case 3: |
2161 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2162 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2163 | break; | |
2164 | case 4: | |
2165 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2166 | break; | |
2167 | } | |
2168 | tcg_temp_free_i32(tmp32); | |
2169 | return; | |
e6e5906b PB |
2170 | case 6: |
2171 | opsize = OS_BYTE; | |
a7812ae4 | 2172 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2173 | break; |
2174 | default: | |
2175 | goto undef; | |
2176 | } | |
d4d79bb1 | 2177 | DEST_EA(env, insn, opsize, tmp32, NULL); |
a7812ae4 | 2178 | tcg_temp_free_i32(tmp32); |
e6e5906b PB |
2179 | return; |
2180 | case 4: /* fmove to control register. */ | |
2181 | switch ((ext >> 10) & 7) { | |
2182 | case 4: /* FPCR */ | |
2183 | /* Not implemented. Ignore writes. */ | |
2184 | break; | |
2185 | case 1: /* FPIAR */ | |
2186 | case 2: /* FPSR */ | |
2187 | default: | |
2188 | cpu_abort(NULL, "Unimplemented: fmove to control %d", | |
2189 | (ext >> 10) & 7); | |
2190 | } | |
2191 | break; | |
2192 | case 5: /* fmove from control register. */ | |
2193 | switch ((ext >> 10) & 7) { | |
2194 | case 4: /* FPCR */ | |
2195 | /* Not implemented. Always return zero. */ | |
351326a6 | 2196 | tmp32 = tcg_const_i32(0); |
e6e5906b PB |
2197 | break; |
2198 | case 1: /* FPIAR */ | |
2199 | case 2: /* FPSR */ | |
2200 | default: | |
2201 | cpu_abort(NULL, "Unimplemented: fmove from control %d", | |
2202 | (ext >> 10) & 7); | |
2203 | goto undef; | |
2204 | } | |
d4d79bb1 | 2205 | DEST_EA(env, insn, OS_LONG, tmp32, NULL); |
e6e5906b | 2206 | break; |
5fafdf24 | 2207 | case 6: /* fmovem */ |
e6e5906b PB |
2208 | case 7: |
2209 | { | |
e1f3808e PB |
2210 | TCGv addr; |
2211 | uint16_t mask; | |
2212 | int i; | |
2213 | if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) | |
2214 | goto undef; | |
d4d79bb1 | 2215 | tmp32 = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2216 | if (IS_NULL_QREG(tmp32)) { |
e1f3808e PB |
2217 | gen_addr_fault(s); |
2218 | return; | |
2219 | } | |
a7812ae4 PB |
2220 | addr = tcg_temp_new_i32(); |
2221 | tcg_gen_mov_i32(addr, tmp32); | |
e1f3808e PB |
2222 | mask = 0x80; |
2223 | for (i = 0; i < 8; i++) { | |
2224 | if (ext & mask) { | |
e1f3808e PB |
2225 | dest = FREG(i, 0); |
2226 | if (ext & (1 << 13)) { | |
2227 | /* store */ | |
2228 | tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); | |
2229 | } else { | |
2230 | /* load */ | |
2231 | tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); | |
2232 | } | |
2233 | if (ext & (mask - 1)) | |
2234 | tcg_gen_addi_i32(addr, addr, 8); | |
e6e5906b | 2235 | } |
e1f3808e | 2236 | mask >>= 1; |
e6e5906b | 2237 | } |
18307f26 | 2238 | tcg_temp_free_i32(addr); |
e6e5906b PB |
2239 | } |
2240 | return; | |
2241 | } | |
2242 | if (ext & (1 << 14)) { | |
e6e5906b PB |
2243 | /* Source effective address. */ |
2244 | switch ((ext >> 10) & 7) { | |
2245 | case 0: opsize = OS_LONG; break; | |
2246 | case 1: opsize = OS_SINGLE; break; | |
2247 | case 4: opsize = OS_WORD; break; | |
2248 | case 5: opsize = OS_DOUBLE; break; | |
2249 | case 6: opsize = OS_BYTE; break; | |
2250 | default: | |
2251 | goto undef; | |
2252 | } | |
e6e5906b | 2253 | if (opsize == OS_DOUBLE) { |
a7812ae4 PB |
2254 | tmp32 = tcg_temp_new_i32(); |
2255 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2256 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2257 | case 2: |
2258 | case 3: | |
243ee8f7 | 2259 | break; |
a7812ae4 PB |
2260 | case 4: |
2261 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2262 | break; | |
2263 | case 5: | |
d4d79bb1 | 2264 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2265 | s->pc += 2; |
2266 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2267 | break; | |
2268 | case 7: | |
d4d79bb1 | 2269 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2270 | offset += s->pc - 2; |
2271 | s->pc += 2; | |
2272 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2273 | break; | |
2274 | default: | |
2275 | goto undef; | |
2276 | } | |
2277 | src = gen_load64(s, tmp32); | |
c59b97aa | 2278 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2279 | case 3: |
2280 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2281 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2282 | break; | |
2283 | case 4: | |
2284 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2285 | break; | |
2286 | } | |
2287 | tcg_temp_free_i32(tmp32); | |
e6e5906b | 2288 | } else { |
d4d79bb1 | 2289 | SRC_EA(env, tmp32, opsize, 1, NULL); |
a7812ae4 | 2290 | src = tcg_temp_new_i64(); |
e6e5906b PB |
2291 | switch (opsize) { |
2292 | case OS_LONG: | |
2293 | case OS_WORD: | |
2294 | case OS_BYTE: | |
a7812ae4 | 2295 | gen_helper_i32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2296 | break; |
2297 | case OS_SINGLE: | |
a7812ae4 | 2298 | gen_helper_f32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2299 | break; |
2300 | } | |
2301 | } | |
2302 | } else { | |
2303 | /* Source register. */ | |
2304 | src = FREG(ext, 10); | |
2305 | } | |
2306 | dest = FREG(ext, 7); | |
a7812ae4 | 2307 | res = tcg_temp_new_i64(); |
e6e5906b | 2308 | if (opmode != 0x3a) |
e1f3808e | 2309 | tcg_gen_mov_f64(res, dest); |
e6e5906b | 2310 | round = 1; |
a7812ae4 | 2311 | set_dest = 1; |
e6e5906b PB |
2312 | switch (opmode) { |
2313 | case 0: case 0x40: case 0x44: /* fmove */ | |
e1f3808e | 2314 | tcg_gen_mov_f64(res, src); |
e6e5906b PB |
2315 | break; |
2316 | case 1: /* fint */ | |
e1f3808e | 2317 | gen_helper_iround_f64(res, cpu_env, src); |
e6e5906b PB |
2318 | round = 0; |
2319 | break; | |
2320 | case 3: /* fintrz */ | |
e1f3808e | 2321 | gen_helper_itrunc_f64(res, cpu_env, src); |
e6e5906b PB |
2322 | round = 0; |
2323 | break; | |
2324 | case 4: case 0x41: case 0x45: /* fsqrt */ | |
e1f3808e | 2325 | gen_helper_sqrt_f64(res, cpu_env, src); |
e6e5906b PB |
2326 | break; |
2327 | case 0x18: case 0x58: case 0x5c: /* fabs */ | |
e1f3808e | 2328 | gen_helper_abs_f64(res, src); |
e6e5906b PB |
2329 | break; |
2330 | case 0x1a: case 0x5a: case 0x5e: /* fneg */ | |
e1f3808e | 2331 | gen_helper_chs_f64(res, src); |
e6e5906b PB |
2332 | break; |
2333 | case 0x20: case 0x60: case 0x64: /* fdiv */ | |
e1f3808e | 2334 | gen_helper_div_f64(res, cpu_env, res, src); |
e6e5906b PB |
2335 | break; |
2336 | case 0x22: case 0x62: case 0x66: /* fadd */ | |
e1f3808e | 2337 | gen_helper_add_f64(res, cpu_env, res, src); |
e6e5906b PB |
2338 | break; |
2339 | case 0x23: case 0x63: case 0x67: /* fmul */ | |
e1f3808e | 2340 | gen_helper_mul_f64(res, cpu_env, res, src); |
e6e5906b PB |
2341 | break; |
2342 | case 0x28: case 0x68: case 0x6c: /* fsub */ | |
e1f3808e | 2343 | gen_helper_sub_f64(res, cpu_env, res, src); |
e6e5906b PB |
2344 | break; |
2345 | case 0x38: /* fcmp */ | |
e1f3808e | 2346 | gen_helper_sub_cmp_f64(res, cpu_env, res, src); |
a7812ae4 | 2347 | set_dest = 0; |
e6e5906b PB |
2348 | round = 0; |
2349 | break; | |
2350 | case 0x3a: /* ftst */ | |
e1f3808e | 2351 | tcg_gen_mov_f64(res, src); |
a7812ae4 | 2352 | set_dest = 0; |
e6e5906b PB |
2353 | round = 0; |
2354 | break; | |
2355 | default: | |
2356 | goto undef; | |
2357 | } | |
a7812ae4 PB |
2358 | if (ext & (1 << 14)) { |
2359 | tcg_temp_free_i64(src); | |
2360 | } | |
e6e5906b PB |
2361 | if (round) { |
2362 | if (opmode & 0x40) { | |
2363 | if ((opmode & 0x4) != 0) | |
2364 | round = 0; | |
2365 | } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { | |
2366 | round = 0; | |
2367 | } | |
2368 | } | |
2369 | if (round) { | |
a7812ae4 | 2370 | TCGv tmp = tcg_temp_new_i32(); |
e1f3808e PB |
2371 | gen_helper_f64_to_f32(tmp, cpu_env, res); |
2372 | gen_helper_f32_to_f64(res, cpu_env, tmp); | |
a7812ae4 | 2373 | tcg_temp_free_i32(tmp); |
5fafdf24 | 2374 | } |
e1f3808e | 2375 | tcg_gen_mov_f64(QREG_FP_RESULT, res); |
a7812ae4 | 2376 | if (set_dest) { |
e1f3808e | 2377 | tcg_gen_mov_f64(dest, res); |
e6e5906b | 2378 | } |
a7812ae4 | 2379 | tcg_temp_free_i64(res); |
e6e5906b PB |
2380 | return; |
2381 | undef: | |
a7812ae4 | 2382 | /* FIXME: Is this right for offset addressing modes? */ |
e6e5906b | 2383 | s->pc -= 2; |
d4d79bb1 | 2384 | disas_undef_fpu(env, s, insn); |
e6e5906b PB |
2385 | } |
2386 | ||
2387 | DISAS_INSN(fbcc) | |
2388 | { | |
2389 | uint32_t offset; | |
2390 | uint32_t addr; | |
e1f3808e | 2391 | TCGv flag; |
42a268c2 | 2392 | TCGLabel *l1; |
e6e5906b PB |
2393 | |
2394 | addr = s->pc; | |
d4d79bb1 | 2395 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
2396 | s->pc += 2; |
2397 | if (insn & (1 << 6)) { | |
d4d79bb1 | 2398 | offset = (offset << 16) | cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2399 | s->pc += 2; |
2400 | } | |
2401 | ||
2402 | l1 = gen_new_label(); | |
2403 | /* TODO: Raise BSUN exception. */ | |
a7812ae4 | 2404 | flag = tcg_temp_new(); |
e1f3808e | 2405 | gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); |
e6e5906b PB |
2406 | /* Jump to l1 if condition is true. */ |
2407 | switch (insn & 0xf) { | |
2408 | case 0: /* f */ | |
2409 | break; | |
2410 | case 1: /* eq (=0) */ | |
e1f3808e | 2411 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2412 | break; |
2413 | case 2: /* ogt (=1) */ | |
e1f3808e | 2414 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2415 | break; |
2416 | case 3: /* oge (=0 or =1) */ | |
e1f3808e | 2417 | tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2418 | break; |
2419 | case 4: /* olt (=-1) */ | |
e1f3808e | 2420 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2421 | break; |
2422 | case 5: /* ole (=-1 or =0) */ | |
e1f3808e | 2423 | tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2424 | break; |
2425 | case 6: /* ogl (=-1 or =1) */ | |
e1f3808e PB |
2426 | tcg_gen_andi_i32(flag, flag, 1); |
2427 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2428 | break; |
2429 | case 7: /* or (=2) */ | |
e1f3808e | 2430 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2431 | break; |
2432 | case 8: /* un (<2) */ | |
e1f3808e | 2433 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2434 | break; |
2435 | case 9: /* ueq (=0 or =2) */ | |
e1f3808e PB |
2436 | tcg_gen_andi_i32(flag, flag, 1); |
2437 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2438 | break; |
2439 | case 10: /* ugt (>0) */ | |
e1f3808e | 2440 | tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2441 | break; |
2442 | case 11: /* uge (>=0) */ | |
e1f3808e | 2443 | tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2444 | break; |
2445 | case 12: /* ult (=-1 or =2) */ | |
e1f3808e | 2446 | tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2447 | break; |
2448 | case 13: /* ule (!=1) */ | |
e1f3808e | 2449 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2450 | break; |
2451 | case 14: /* ne (!=0) */ | |
e1f3808e | 2452 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2453 | break; |
2454 | case 15: /* t */ | |
e1f3808e | 2455 | tcg_gen_br(l1); |
e6e5906b PB |
2456 | break; |
2457 | } | |
2458 | gen_jmp_tb(s, 0, s->pc); | |
2459 | gen_set_label(l1); | |
2460 | gen_jmp_tb(s, 1, addr + offset); | |
2461 | } | |
2462 | ||
0633879f PB |
2463 | DISAS_INSN(frestore) |
2464 | { | |
a47dddd7 AF |
2465 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2466 | ||
0633879f | 2467 | /* TODO: Implement frestore. */ |
a47dddd7 | 2468 | cpu_abort(CPU(cpu), "FRESTORE not implemented"); |
0633879f PB |
2469 | } |
2470 | ||
2471 | DISAS_INSN(fsave) | |
2472 | { | |
a47dddd7 AF |
2473 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2474 | ||
0633879f | 2475 | /* TODO: Implement fsave. */ |
a47dddd7 | 2476 | cpu_abort(CPU(cpu), "FSAVE not implemented"); |
0633879f PB |
2477 | } |
2478 | ||
e1f3808e | 2479 | static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) |
acf930aa | 2480 | { |
a7812ae4 | 2481 | TCGv tmp = tcg_temp_new(); |
acf930aa PB |
2482 | if (s->env->macsr & MACSR_FI) { |
2483 | if (upper) | |
e1f3808e | 2484 | tcg_gen_andi_i32(tmp, val, 0xffff0000); |
acf930aa | 2485 | else |
e1f3808e | 2486 | tcg_gen_shli_i32(tmp, val, 16); |
acf930aa PB |
2487 | } else if (s->env->macsr & MACSR_SU) { |
2488 | if (upper) | |
e1f3808e | 2489 | tcg_gen_sari_i32(tmp, val, 16); |
acf930aa | 2490 | else |
e1f3808e | 2491 | tcg_gen_ext16s_i32(tmp, val); |
acf930aa PB |
2492 | } else { |
2493 | if (upper) | |
e1f3808e | 2494 | tcg_gen_shri_i32(tmp, val, 16); |
acf930aa | 2495 | else |
e1f3808e | 2496 | tcg_gen_ext16u_i32(tmp, val); |
acf930aa PB |
2497 | } |
2498 | return tmp; | |
2499 | } | |
2500 | ||
e1f3808e PB |
2501 | static void gen_mac_clear_flags(void) |
2502 | { | |
2503 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, | |
2504 | ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); | |
2505 | } | |
2506 | ||
acf930aa PB |
2507 | DISAS_INSN(mac) |
2508 | { | |
e1f3808e PB |
2509 | TCGv rx; |
2510 | TCGv ry; | |
acf930aa PB |
2511 | uint16_t ext; |
2512 | int acc; | |
e1f3808e PB |
2513 | TCGv tmp; |
2514 | TCGv addr; | |
2515 | TCGv loadval; | |
acf930aa | 2516 | int dual; |
e1f3808e PB |
2517 | TCGv saved_flags; |
2518 | ||
a7812ae4 PB |
2519 | if (!s->done_mac) { |
2520 | s->mactmp = tcg_temp_new_i64(); | |
2521 | s->done_mac = 1; | |
2522 | } | |
acf930aa | 2523 | |
d4d79bb1 | 2524 | ext = cpu_lduw_code(env, s->pc); |
acf930aa PB |
2525 | s->pc += 2; |
2526 | ||
2527 | acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); | |
2528 | dual = ((insn & 0x30) != 0 && (ext & 3) != 0); | |
d315c888 | 2529 | if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { |
d4d79bb1 | 2530 | disas_undef(env, s, insn); |
d315c888 PB |
2531 | return; |
2532 | } | |
acf930aa PB |
2533 | if (insn & 0x30) { |
2534 | /* MAC with load. */ | |
d4d79bb1 | 2535 | tmp = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2536 | addr = tcg_temp_new(); |
e1f3808e | 2537 | tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); |
acf930aa PB |
2538 | /* Load the value now to ensure correct exception behavior. |
2539 | Perform writeback after reading the MAC inputs. */ | |
2540 | loadval = gen_load(s, OS_LONG, addr, 0); | |
2541 | ||
2542 | acc ^= 1; | |
2543 | rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); | |
2544 | ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); | |
2545 | } else { | |
e1f3808e | 2546 | loadval = addr = NULL_QREG; |
acf930aa PB |
2547 | rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
2548 | ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
2549 | } | |
2550 | ||
e1f3808e PB |
2551 | gen_mac_clear_flags(); |
2552 | #if 0 | |
acf930aa | 2553 | l1 = -1; |
e1f3808e | 2554 | /* Disabled because conditional branches clobber temporary vars. */ |
acf930aa PB |
2555 | if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { |
2556 | /* Skip the multiply if we know we will ignore it. */ | |
2557 | l1 = gen_new_label(); | |
a7812ae4 | 2558 | tmp = tcg_temp_new(); |
e1f3808e | 2559 | tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); |
acf930aa PB |
2560 | gen_op_jmp_nz32(tmp, l1); |
2561 | } | |
e1f3808e | 2562 | #endif |
acf930aa PB |
2563 | |
2564 | if ((ext & 0x0800) == 0) { | |
2565 | /* Word. */ | |
2566 | rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); | |
2567 | ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); | |
2568 | } | |
2569 | if (s->env->macsr & MACSR_FI) { | |
e1f3808e | 2570 | gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2571 | } else { |
2572 | if (s->env->macsr & MACSR_SU) | |
e1f3808e | 2573 | gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); |
acf930aa | 2574 | else |
e1f3808e | 2575 | gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2576 | switch ((ext >> 9) & 3) { |
2577 | case 1: | |
e1f3808e | 2578 | tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2579 | break; |
2580 | case 3: | |
e1f3808e | 2581 | tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2582 | break; |
2583 | } | |
2584 | } | |
2585 | ||
2586 | if (dual) { | |
2587 | /* Save the overflow flag from the multiply. */ | |
a7812ae4 | 2588 | saved_flags = tcg_temp_new(); |
e1f3808e PB |
2589 | tcg_gen_mov_i32(saved_flags, QREG_MACSR); |
2590 | } else { | |
2591 | saved_flags = NULL_QREG; | |
acf930aa PB |
2592 | } |
2593 | ||
e1f3808e PB |
2594 | #if 0 |
2595 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2596 | if ((s->env->macsr & MACSR_OMC) != 0 && dual) { |
2597 | /* Skip the accumulate if the value is already saturated. */ | |
2598 | l1 = gen_new_label(); | |
a7812ae4 | 2599 | tmp = tcg_temp_new(); |
351326a6 | 2600 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2601 | gen_op_jmp_nz32(tmp, l1); |
2602 | } | |
e1f3808e | 2603 | #endif |
acf930aa PB |
2604 | |
2605 | if (insn & 0x100) | |
e1f3808e | 2606 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2607 | else |
e1f3808e | 2608 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa PB |
2609 | |
2610 | if (s->env->macsr & MACSR_FI) | |
e1f3808e | 2611 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2612 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2613 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2614 | else |
e1f3808e | 2615 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2616 | |
e1f3808e PB |
2617 | #if 0 |
2618 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2619 | if (l1 != -1) |
2620 | gen_set_label(l1); | |
e1f3808e | 2621 | #endif |
acf930aa PB |
2622 | |
2623 | if (dual) { | |
2624 | /* Dual accumulate variant. */ | |
2625 | acc = (ext >> 2) & 3; | |
2626 | /* Restore the overflow flag from the multiplier. */ | |
e1f3808e PB |
2627 | tcg_gen_mov_i32(QREG_MACSR, saved_flags); |
2628 | #if 0 | |
2629 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2630 | if ((s->env->macsr & MACSR_OMC) != 0) { |
2631 | /* Skip the accumulate if the value is already saturated. */ | |
2632 | l1 = gen_new_label(); | |
a7812ae4 | 2633 | tmp = tcg_temp_new(); |
351326a6 | 2634 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2635 | gen_op_jmp_nz32(tmp, l1); |
2636 | } | |
e1f3808e | 2637 | #endif |
acf930aa | 2638 | if (ext & 2) |
e1f3808e | 2639 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2640 | else |
e1f3808e | 2641 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2642 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2643 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2644 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2645 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2646 | else |
e1f3808e PB |
2647 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
2648 | #if 0 | |
2649 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2650 | if (l1 != -1) |
2651 | gen_set_label(l1); | |
e1f3808e | 2652 | #endif |
acf930aa | 2653 | } |
e1f3808e | 2654 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); |
acf930aa PB |
2655 | |
2656 | if (insn & 0x30) { | |
e1f3808e | 2657 | TCGv rw; |
acf930aa | 2658 | rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
e1f3808e | 2659 | tcg_gen_mov_i32(rw, loadval); |
acf930aa PB |
2660 | /* FIXME: Should address writeback happen with the masked or |
2661 | unmasked value? */ | |
2662 | switch ((insn >> 3) & 7) { | |
2663 | case 3: /* Post-increment. */ | |
e1f3808e | 2664 | tcg_gen_addi_i32(AREG(insn, 0), addr, 4); |
acf930aa PB |
2665 | break; |
2666 | case 4: /* Pre-decrement. */ | |
e1f3808e | 2667 | tcg_gen_mov_i32(AREG(insn, 0), addr); |
acf930aa PB |
2668 | } |
2669 | } | |
2670 | } | |
2671 | ||
2672 | DISAS_INSN(from_mac) | |
2673 | { | |
e1f3808e | 2674 | TCGv rx; |
a7812ae4 | 2675 | TCGv_i64 acc; |
e1f3808e | 2676 | int accnum; |
acf930aa PB |
2677 | |
2678 | rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e PB |
2679 | accnum = (insn >> 9) & 3; |
2680 | acc = MACREG(accnum); | |
acf930aa | 2681 | if (s->env->macsr & MACSR_FI) { |
a7812ae4 | 2682 | gen_helper_get_macf(rx, cpu_env, acc); |
acf930aa | 2683 | } else if ((s->env->macsr & MACSR_OMC) == 0) { |
e1f3808e | 2684 | tcg_gen_trunc_i64_i32(rx, acc); |
acf930aa | 2685 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2686 | gen_helper_get_macs(rx, acc); |
acf930aa | 2687 | } else { |
e1f3808e PB |
2688 | gen_helper_get_macu(rx, acc); |
2689 | } | |
2690 | if (insn & 0x40) { | |
2691 | tcg_gen_movi_i64(acc, 0); | |
2692 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
acf930aa | 2693 | } |
acf930aa PB |
2694 | } |
2695 | ||
2696 | DISAS_INSN(move_mac) | |
2697 | { | |
e1f3808e | 2698 | /* FIXME: This can be done without a helper. */ |
acf930aa | 2699 | int src; |
e1f3808e | 2700 | TCGv dest; |
acf930aa | 2701 | src = insn & 3; |
e1f3808e PB |
2702 | dest = tcg_const_i32((insn >> 9) & 3); |
2703 | gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); | |
2704 | gen_mac_clear_flags(); | |
2705 | gen_helper_mac_set_flags(cpu_env, dest); | |
acf930aa PB |
2706 | } |
2707 | ||
2708 | DISAS_INSN(from_macsr) | |
2709 | { | |
e1f3808e | 2710 | TCGv reg; |
acf930aa PB |
2711 | |
2712 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e | 2713 | tcg_gen_mov_i32(reg, QREG_MACSR); |
acf930aa PB |
2714 | } |
2715 | ||
2716 | DISAS_INSN(from_mask) | |
2717 | { | |
e1f3808e | 2718 | TCGv reg; |
acf930aa | 2719 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2720 | tcg_gen_mov_i32(reg, QREG_MAC_MASK); |
acf930aa PB |
2721 | } |
2722 | ||
2723 | DISAS_INSN(from_mext) | |
2724 | { | |
e1f3808e PB |
2725 | TCGv reg; |
2726 | TCGv acc; | |
acf930aa | 2727 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2728 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2729 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2730 | gen_helper_get_mac_extf(reg, cpu_env, acc); |
acf930aa | 2731 | else |
e1f3808e | 2732 | gen_helper_get_mac_exti(reg, cpu_env, acc); |
acf930aa PB |
2733 | } |
2734 | ||
2735 | DISAS_INSN(macsr_to_ccr) | |
2736 | { | |
e1f3808e PB |
2737 | tcg_gen_movi_i32(QREG_CC_X, 0); |
2738 | tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf); | |
acf930aa PB |
2739 | s->cc_op = CC_OP_FLAGS; |
2740 | } | |
2741 | ||
2742 | DISAS_INSN(to_mac) | |
2743 | { | |
a7812ae4 | 2744 | TCGv_i64 acc; |
e1f3808e PB |
2745 | TCGv val; |
2746 | int accnum; | |
2747 | accnum = (insn >> 9) & 3; | |
2748 | acc = MACREG(accnum); | |
d4d79bb1 | 2749 | SRC_EA(env, val, OS_LONG, 0, NULL); |
acf930aa | 2750 | if (s->env->macsr & MACSR_FI) { |
e1f3808e PB |
2751 | tcg_gen_ext_i32_i64(acc, val); |
2752 | tcg_gen_shli_i64(acc, acc, 8); | |
acf930aa | 2753 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2754 | tcg_gen_ext_i32_i64(acc, val); |
acf930aa | 2755 | } else { |
e1f3808e | 2756 | tcg_gen_extu_i32_i64(acc, val); |
acf930aa | 2757 | } |
e1f3808e PB |
2758 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); |
2759 | gen_mac_clear_flags(); | |
2760 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); | |
acf930aa PB |
2761 | } |
2762 | ||
2763 | DISAS_INSN(to_macsr) | |
2764 | { | |
e1f3808e | 2765 | TCGv val; |
d4d79bb1 | 2766 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2767 | gen_helper_set_macsr(cpu_env, val); |
acf930aa PB |
2768 | gen_lookup_tb(s); |
2769 | } | |
2770 | ||
2771 | DISAS_INSN(to_mask) | |
2772 | { | |
e1f3808e | 2773 | TCGv val; |
d4d79bb1 | 2774 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2775 | tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); |
acf930aa PB |
2776 | } |
2777 | ||
2778 | DISAS_INSN(to_mext) | |
2779 | { | |
e1f3808e PB |
2780 | TCGv val; |
2781 | TCGv acc; | |
d4d79bb1 | 2782 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2783 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2784 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2785 | gen_helper_set_mac_extf(cpu_env, val, acc); |
acf930aa | 2786 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2787 | gen_helper_set_mac_exts(cpu_env, val, acc); |
acf930aa | 2788 | else |
e1f3808e | 2789 | gen_helper_set_mac_extu(cpu_env, val, acc); |
acf930aa PB |
2790 | } |
2791 | ||
e6e5906b PB |
2792 | static disas_proc opcode_table[65536]; |
2793 | ||
2794 | static void | |
2795 | register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) | |
2796 | { | |
2797 | int i; | |
2798 | int from; | |
2799 | int to; | |
2800 | ||
2801 | /* Sanity check. All set bits must be included in the mask. */ | |
5fc4adf6 PB |
2802 | if (opcode & ~mask) { |
2803 | fprintf(stderr, | |
2804 | "qemu internal error: bogus opcode definition %04x/%04x\n", | |
2805 | opcode, mask); | |
e6e5906b | 2806 | abort(); |
5fc4adf6 | 2807 | } |
e6e5906b PB |
2808 | /* This could probably be cleverer. For now just optimize the case where |
2809 | the top bits are known. */ | |
2810 | /* Find the first zero bit in the mask. */ | |
2811 | i = 0x8000; | |
2812 | while ((i & mask) != 0) | |
2813 | i >>= 1; | |
2814 | /* Iterate over all combinations of this and lower bits. */ | |
2815 | if (i == 0) | |
2816 | i = 1; | |
2817 | else | |
2818 | i <<= 1; | |
2819 | from = opcode & ~(i - 1); | |
2820 | to = from + i; | |
0633879f | 2821 | for (i = from; i < to; i++) { |
e6e5906b PB |
2822 | if ((i & mask) == opcode) |
2823 | opcode_table[i] = proc; | |
0633879f | 2824 | } |
e6e5906b PB |
2825 | } |
2826 | ||
2827 | /* Register m68k opcode handlers. Order is important. | |
2828 | Later insn override earlier ones. */ | |
0402f767 | 2829 | void register_m68k_insns (CPUM68KState *env) |
e6e5906b | 2830 | { |
d315c888 | 2831 | #define INSN(name, opcode, mask, feature) do { \ |
0402f767 | 2832 | if (m68k_feature(env, M68K_FEATURE_##feature)) \ |
d315c888 PB |
2833 | register_opcode(disas_##name, 0x##opcode, 0x##mask); \ |
2834 | } while(0) | |
0402f767 PB |
2835 | INSN(undef, 0000, 0000, CF_ISA_A); |
2836 | INSN(arith_im, 0080, fff8, CF_ISA_A); | |
d315c888 | 2837 | INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); |
0402f767 PB |
2838 | INSN(bitop_reg, 0100, f1c0, CF_ISA_A); |
2839 | INSN(bitop_reg, 0140, f1c0, CF_ISA_A); | |
2840 | INSN(bitop_reg, 0180, f1c0, CF_ISA_A); | |
2841 | INSN(bitop_reg, 01c0, f1c0, CF_ISA_A); | |
2842 | INSN(arith_im, 0280, fff8, CF_ISA_A); | |
d315c888 | 2843 | INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); |
0402f767 | 2844 | INSN(arith_im, 0480, fff8, CF_ISA_A); |
d315c888 | 2845 | INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); |
0402f767 PB |
2846 | INSN(arith_im, 0680, fff8, CF_ISA_A); |
2847 | INSN(bitop_im, 0800, ffc0, CF_ISA_A); | |
2848 | INSN(bitop_im, 0840, ffc0, CF_ISA_A); | |
2849 | INSN(bitop_im, 0880, ffc0, CF_ISA_A); | |
2850 | INSN(bitop_im, 08c0, ffc0, CF_ISA_A); | |
2851 | INSN(arith_im, 0a80, fff8, CF_ISA_A); | |
2852 | INSN(arith_im, 0c00, ff38, CF_ISA_A); | |
2853 | INSN(move, 1000, f000, CF_ISA_A); | |
2854 | INSN(move, 2000, f000, CF_ISA_A); | |
2855 | INSN(move, 3000, f000, CF_ISA_A); | |
d315c888 | 2856 | INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); |
0402f767 PB |
2857 | INSN(negx, 4080, fff8, CF_ISA_A); |
2858 | INSN(move_from_sr, 40c0, fff8, CF_ISA_A); | |
2859 | INSN(lea, 41c0, f1c0, CF_ISA_A); | |
2860 | INSN(clr, 4200, ff00, CF_ISA_A); | |
2861 | INSN(undef, 42c0, ffc0, CF_ISA_A); | |
2862 | INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); | |
2863 | INSN(neg, 4480, fff8, CF_ISA_A); | |
2864 | INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A); | |
2865 | INSN(not, 4680, fff8, CF_ISA_A); | |
2866 | INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); | |
2867 | INSN(pea, 4840, ffc0, CF_ISA_A); | |
2868 | INSN(swap, 4840, fff8, CF_ISA_A); | |
2869 | INSN(movem, 48c0, fbc0, CF_ISA_A); | |
2870 | INSN(ext, 4880, fff8, CF_ISA_A); | |
2871 | INSN(ext, 48c0, fff8, CF_ISA_A); | |
2872 | INSN(ext, 49c0, fff8, CF_ISA_A); | |
2873 | INSN(tst, 4a00, ff00, CF_ISA_A); | |
2874 | INSN(tas, 4ac0, ffc0, CF_ISA_B); | |
2875 | INSN(halt, 4ac8, ffff, CF_ISA_A); | |
2876 | INSN(pulse, 4acc, ffff, CF_ISA_A); | |
2877 | INSN(illegal, 4afc, ffff, CF_ISA_A); | |
2878 | INSN(mull, 4c00, ffc0, CF_ISA_A); | |
2879 | INSN(divl, 4c40, ffc0, CF_ISA_A); | |
2880 | INSN(sats, 4c80, fff8, CF_ISA_B); | |
2881 | INSN(trap, 4e40, fff0, CF_ISA_A); | |
2882 | INSN(link, 4e50, fff8, CF_ISA_A); | |
2883 | INSN(unlk, 4e58, fff8, CF_ISA_A); | |
20dcee94 PB |
2884 | INSN(move_to_usp, 4e60, fff8, USP); |
2885 | INSN(move_from_usp, 4e68, fff8, USP); | |
0402f767 PB |
2886 | INSN(nop, 4e71, ffff, CF_ISA_A); |
2887 | INSN(stop, 4e72, ffff, CF_ISA_A); | |
2888 | INSN(rte, 4e73, ffff, CF_ISA_A); | |
2889 | INSN(rts, 4e75, ffff, CF_ISA_A); | |
2890 | INSN(movec, 4e7b, ffff, CF_ISA_A); | |
2891 | INSN(jump, 4e80, ffc0, CF_ISA_A); | |
2892 | INSN(jump, 4ec0, ffc0, CF_ISA_A); | |
2893 | INSN(addsubq, 5180, f1c0, CF_ISA_A); | |
2894 | INSN(scc, 50c0, f0f8, CF_ISA_A); | |
2895 | INSN(addsubq, 5080, f1c0, CF_ISA_A); | |
2896 | INSN(tpf, 51f8, fff8, CF_ISA_A); | |
d315c888 PB |
2897 | |
2898 | /* Branch instructions. */ | |
0402f767 | 2899 | INSN(branch, 6000, f000, CF_ISA_A); |
d315c888 PB |
2900 | /* Disable long branch instructions, then add back the ones we want. */ |
2901 | INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */ | |
2902 | INSN(branch, 60ff, f0ff, CF_ISA_B); | |
2903 | INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ | |
2904 | INSN(branch, 60ff, ffff, BRAL); | |
2905 | ||
0402f767 PB |
2906 | INSN(moveq, 7000, f100, CF_ISA_A); |
2907 | INSN(mvzs, 7100, f100, CF_ISA_B); | |
2908 | INSN(or, 8000, f000, CF_ISA_A); | |
2909 | INSN(divw, 80c0, f0c0, CF_ISA_A); | |
2910 | INSN(addsub, 9000, f000, CF_ISA_A); | |
2911 | INSN(subx, 9180, f1f8, CF_ISA_A); | |
2912 | INSN(suba, 91c0, f1c0, CF_ISA_A); | |
acf930aa | 2913 | |
0402f767 | 2914 | INSN(undef_mac, a000, f000, CF_ISA_A); |
acf930aa PB |
2915 | INSN(mac, a000, f100, CF_EMAC); |
2916 | INSN(from_mac, a180, f9b0, CF_EMAC); | |
2917 | INSN(move_mac, a110, f9fc, CF_EMAC); | |
2918 | INSN(from_macsr,a980, f9f0, CF_EMAC); | |
2919 | INSN(from_mask, ad80, fff0, CF_EMAC); | |
2920 | INSN(from_mext, ab80, fbf0, CF_EMAC); | |
2921 | INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); | |
2922 | INSN(to_mac, a100, f9c0, CF_EMAC); | |
2923 | INSN(to_macsr, a900, ffc0, CF_EMAC); | |
2924 | INSN(to_mext, ab00, fbc0, CF_EMAC); | |
2925 | INSN(to_mask, ad00, ffc0, CF_EMAC); | |
2926 | ||
0402f767 PB |
2927 | INSN(mov3q, a140, f1c0, CF_ISA_B); |
2928 | INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ | |
2929 | INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ | |
2930 | INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ | |
2931 | INSN(cmp, b080, f1c0, CF_ISA_A); | |
2932 | INSN(cmpa, b1c0, f1c0, CF_ISA_A); | |
2933 | INSN(eor, b180, f1c0, CF_ISA_A); | |
2934 | INSN(and, c000, f000, CF_ISA_A); | |
2935 | INSN(mulw, c0c0, f0c0, CF_ISA_A); | |
2936 | INSN(addsub, d000, f000, CF_ISA_A); | |
2937 | INSN(addx, d180, f1f8, CF_ISA_A); | |
2938 | INSN(adda, d1c0, f1c0, CF_ISA_A); | |
2939 | INSN(shift_im, e080, f0f0, CF_ISA_A); | |
2940 | INSN(shift_reg, e0a0, f0f0, CF_ISA_A); | |
2941 | INSN(undef_fpu, f000, f000, CF_ISA_A); | |
e6e5906b PB |
2942 | INSN(fpu, f200, ffc0, CF_FPU); |
2943 | INSN(fbcc, f280, ffc0, CF_FPU); | |
0633879f PB |
2944 | INSN(frestore, f340, ffc0, CF_FPU); |
2945 | INSN(fsave, f340, ffc0, CF_FPU); | |
0402f767 PB |
2946 | INSN(intouch, f340, ffc0, CF_ISA_A); |
2947 | INSN(cpushl, f428, ff38, CF_ISA_A); | |
2948 | INSN(wddata, fb00, ff00, CF_ISA_A); | |
2949 | INSN(wdebug, fbc0, ffc0, CF_ISA_A); | |
e6e5906b PB |
2950 | #undef INSN |
2951 | } | |
2952 | ||
2953 | /* ??? Some of this implementation is not exception safe. We should always | |
2954 | write back the result to memory before setting the condition codes. */ | |
2b3e3cfe | 2955 | static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) |
e6e5906b PB |
2956 | { |
2957 | uint16_t insn; | |
2958 | ||
fa547e61 RH |
2959 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
2960 | tcg_gen_debug_insn_start(s->pc); | |
2961 | } | |
2962 | ||
d4d79bb1 | 2963 | insn = cpu_lduw_code(env, s->pc); |
e6e5906b PB |
2964 | s->pc += 2; |
2965 | ||
d4d79bb1 | 2966 | opcode_table[insn](env, s, insn); |
e6e5906b PB |
2967 | } |
2968 | ||
e6e5906b | 2969 | /* generate intermediate code for basic block 'tb'. */ |
2cfc5f17 | 2970 | static inline void |
c296b15b AF |
2971 | gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, |
2972 | bool search_pc) | |
e6e5906b | 2973 | { |
ed2803da | 2974 | CPUState *cs = CPU(cpu); |
c296b15b | 2975 | CPUM68KState *env = &cpu->env; |
e6e5906b | 2976 | DisasContext dc1, *dc = &dc1; |
a1d1bb31 | 2977 | CPUBreakpoint *bp; |
e6e5906b PB |
2978 | int j, lj; |
2979 | target_ulong pc_start; | |
2980 | int pc_offset; | |
2e70f6ef PB |
2981 | int num_insns; |
2982 | int max_insns; | |
e6e5906b PB |
2983 | |
2984 | /* generate intermediate code */ | |
2985 | pc_start = tb->pc; | |
3b46e624 | 2986 | |
e6e5906b PB |
2987 | dc->tb = tb; |
2988 | ||
e6dbd3b3 | 2989 | dc->env = env; |
e6e5906b PB |
2990 | dc->is_jmp = DISAS_NEXT; |
2991 | dc->pc = pc_start; | |
2992 | dc->cc_op = CC_OP_DYNAMIC; | |
ed2803da | 2993 | dc->singlestep_enabled = cs->singlestep_enabled; |
e6e5906b | 2994 | dc->fpcr = env->fpcr; |
0633879f | 2995 | dc->user = (env->sr & SR_S) == 0; |
a7812ae4 | 2996 | dc->done_mac = 0; |
e6e5906b | 2997 | lj = -1; |
2e70f6ef PB |
2998 | num_insns = 0; |
2999 | max_insns = tb->cflags & CF_COUNT_MASK; | |
3000 | if (max_insns == 0) | |
3001 | max_insns = CF_COUNT_MASK; | |
3002 | ||
cd42d5b2 | 3003 | gen_tb_start(tb); |
e6e5906b | 3004 | do { |
e6e5906b PB |
3005 | pc_offset = dc->pc - pc_start; |
3006 | gen_throws_exception = NULL; | |
f0c3c505 AF |
3007 | if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |
3008 | QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { | |
a1d1bb31 | 3009 | if (bp->pc == dc->pc) { |
e6e5906b PB |
3010 | gen_exception(dc, dc->pc, EXCP_DEBUG); |
3011 | dc->is_jmp = DISAS_JUMP; | |
3012 | break; | |
3013 | } | |
3014 | } | |
3015 | if (dc->is_jmp) | |
3016 | break; | |
3017 | } | |
3018 | if (search_pc) { | |
fe700adb | 3019 | j = tcg_op_buf_count(); |
e6e5906b PB |
3020 | if (lj < j) { |
3021 | lj++; | |
3022 | while (lj < j) | |
ab1103de | 3023 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
e6e5906b | 3024 | } |
25983cad | 3025 | tcg_ctx.gen_opc_pc[lj] = dc->pc; |
ab1103de | 3026 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 3027 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
e6e5906b | 3028 | } |
2e70f6ef PB |
3029 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
3030 | gen_io_start(); | |
510ff0b7 | 3031 | dc->insn_pc = dc->pc; |
e6e5906b | 3032 | disas_m68k_insn(env, dc); |
2e70f6ef | 3033 | num_insns++; |
fe700adb | 3034 | } while (!dc->is_jmp && !tcg_op_buf_full() && |
ed2803da | 3035 | !cs->singlestep_enabled && |
1b530a6d | 3036 | !singlestep && |
2e70f6ef PB |
3037 | (pc_offset) < (TARGET_PAGE_SIZE - 32) && |
3038 | num_insns < max_insns); | |
e6e5906b | 3039 | |
2e70f6ef PB |
3040 | if (tb->cflags & CF_LAST_IO) |
3041 | gen_io_end(); | |
ed2803da | 3042 | if (unlikely(cs->singlestep_enabled)) { |
e6e5906b PB |
3043 | /* Make sure the pc is updated, and raise a debug exception. */ |
3044 | if (!dc->is_jmp) { | |
3045 | gen_flush_cc_op(dc); | |
e1f3808e | 3046 | tcg_gen_movi_i32(QREG_PC, dc->pc); |
e6e5906b | 3047 | } |
31871141 | 3048 | gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); |
e6e5906b PB |
3049 | } else { |
3050 | switch(dc->is_jmp) { | |
3051 | case DISAS_NEXT: | |
3052 | gen_flush_cc_op(dc); | |
3053 | gen_jmp_tb(dc, 0, dc->pc); | |
3054 | break; | |
3055 | default: | |
3056 | case DISAS_JUMP: | |
3057 | case DISAS_UPDATE: | |
3058 | gen_flush_cc_op(dc); | |
3059 | /* indicate that the hash table must be used to find the next TB */ | |
57fec1fe | 3060 | tcg_gen_exit_tb(0); |
e6e5906b PB |
3061 | break; |
3062 | case DISAS_TB_JUMP: | |
3063 | /* nothing more to generate */ | |
3064 | break; | |
3065 | } | |
3066 | } | |
806f352d | 3067 | gen_tb_end(tb, num_insns); |
e6e5906b PB |
3068 | |
3069 | #ifdef DEBUG_DISAS | |
8fec2b8c | 3070 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
93fcfe39 AL |
3071 | qemu_log("----------------\n"); |
3072 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 3073 | log_target_disas(cs, pc_start, dc->pc - pc_start, 0); |
93fcfe39 | 3074 | qemu_log("\n"); |
e6e5906b PB |
3075 | } |
3076 | #endif | |
3077 | if (search_pc) { | |
fe700adb | 3078 | j = tcg_op_buf_count(); |
e6e5906b PB |
3079 | lj++; |
3080 | while (lj <= j) | |
ab1103de | 3081 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
e6e5906b PB |
3082 | } else { |
3083 | tb->size = dc->pc - pc_start; | |
2e70f6ef | 3084 | tb->icount = num_insns; |
e6e5906b PB |
3085 | } |
3086 | ||
3087 | //optimize_flags(); | |
3088 | //expand_target_qops(); | |
e6e5906b PB |
3089 | } |
3090 | ||
2b3e3cfe | 3091 | void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 3092 | { |
c296b15b | 3093 | gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, false); |
e6e5906b PB |
3094 | } |
3095 | ||
2b3e3cfe | 3096 | void gen_intermediate_code_pc(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 3097 | { |
c296b15b | 3098 | gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, true); |
e6e5906b PB |
3099 | } |
3100 | ||
878096ee AF |
3101 | void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
3102 | int flags) | |
e6e5906b | 3103 | { |
878096ee AF |
3104 | M68kCPU *cpu = M68K_CPU(cs); |
3105 | CPUM68KState *env = &cpu->env; | |
e6e5906b PB |
3106 | int i; |
3107 | uint16_t sr; | |
3108 | CPU_DoubleU u; | |
3109 | for (i = 0; i < 8; i++) | |
3110 | { | |
3111 | u.d = env->fregs[i]; | |
3112 | cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", | |
3113 | i, env->dregs[i], i, env->aregs[i], | |
8fc7cc58 | 3114 | i, u.l.upper, u.l.lower, *(double *)&u.d); |
e6e5906b PB |
3115 | } |
3116 | cpu_fprintf (f, "PC = %08x ", env->pc); | |
3117 | sr = env->sr; | |
3118 | cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-', | |
3119 | (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', | |
3120 | (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); | |
8fc7cc58 | 3121 | cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); |
e6e5906b PB |
3122 | } |
3123 | ||
2b3e3cfe | 3124 | void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 3125 | { |
25983cad | 3126 | env->pc = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 3127 | } |