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Commit | Line | Data |
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e6e5906b PB |
1 | /* |
2 | * m68k translation | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
e6e5906b | 20 | |
d8416665 | 21 | #include "qemu/osdep.h" |
e6e5906b | 22 | #include "cpu.h" |
76cad711 | 23 | #include "disas/disas.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
57fec1fe | 25 | #include "tcg-op.h" |
1de7afc9 | 26 | #include "qemu/log.h" |
f08b6170 | 27 | #include "exec/cpu_ldst.h" |
e1f3808e | 28 | |
2ef6175a RH |
29 | #include "exec/helper-proto.h" |
30 | #include "exec/helper-gen.h" | |
e6e5906b | 31 | |
a7e30d84 | 32 | #include "trace-tcg.h" |
508127e2 | 33 | #include "exec/log.h" |
a7e30d84 LV |
34 | |
35 | ||
0633879f PB |
36 | //#define DEBUG_DISPATCH 1 |
37 | ||
815a6742 | 38 | /* Fake floating point. */ |
815a6742 | 39 | #define tcg_gen_mov_f64 tcg_gen_mov_i64 |
815a6742 | 40 | #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 |
815a6742 | 41 | #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 |
815a6742 | 42 | |
e1f3808e | 43 | #define DEFO32(name, offset) static TCGv QREG_##name; |
a7812ae4 PB |
44 | #define DEFO64(name, offset) static TCGv_i64 QREG_##name; |
45 | #define DEFF64(name, offset) static TCGv_i64 QREG_##name; | |
e1f3808e PB |
46 | #include "qregs.def" |
47 | #undef DEFO32 | |
48 | #undef DEFO64 | |
49 | #undef DEFF64 | |
50 | ||
259186a7 | 51 | static TCGv_i32 cpu_halted; |
27103424 | 52 | static TCGv_i32 cpu_exception_index; |
259186a7 | 53 | |
1bcea73e | 54 | static TCGv_env cpu_env; |
e1f3808e PB |
55 | |
56 | static char cpu_reg_names[3*8*3 + 5*4]; | |
57 | static TCGv cpu_dregs[8]; | |
58 | static TCGv cpu_aregs[8]; | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fregs[8]; |
60 | static TCGv_i64 cpu_macc[4]; | |
e1f3808e | 61 | |
bcc098b0 LV |
62 | #define REG(insn, pos) (((insn) >> (pos)) & 7) |
63 | #define DREG(insn, pos) cpu_dregs[REG(insn, pos)] | |
64 | #define AREG(insn, pos) cpu_aregs[REG(insn, pos)] | |
65 | #define FREG(insn, pos) cpu_fregs[REG(insn, pos)] | |
e1f3808e PB |
66 | #define MACREG(acc) cpu_macc[acc] |
67 | #define QREG_SP cpu_aregs[7] | |
68 | ||
69 | static TCGv NULL_QREG; | |
a7812ae4 | 70 | #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) |
e1f3808e PB |
71 | /* Used to distinguish stores from bad addressing modes. */ |
72 | static TCGv store_dummy; | |
73 | ||
022c62cb | 74 | #include "exec/gen-icount.h" |
2e70f6ef | 75 | |
e1f3808e PB |
76 | void m68k_tcg_init(void) |
77 | { | |
78 | char *p; | |
79 | int i; | |
80 | ||
e1ccc054 | 81 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7c255043 | 82 | tcg_ctx.tcg_env = cpu_env; |
e1ccc054 RH |
83 | |
84 | #define DEFO32(name, offset) \ | |
85 | QREG_##name = tcg_global_mem_new_i32(cpu_env, \ | |
86 | offsetof(CPUM68KState, offset), #name); | |
87 | #define DEFO64(name, offset) \ | |
88 | QREG_##name = tcg_global_mem_new_i64(cpu_env, \ | |
89 | offsetof(CPUM68KState, offset), #name); | |
90 | #define DEFF64(name, offset) DEFO64(name, offset) | |
e1f3808e PB |
91 | #include "qregs.def" |
92 | #undef DEFO32 | |
93 | #undef DEFO64 | |
94 | #undef DEFF64 | |
95 | ||
e1ccc054 | 96 | cpu_halted = tcg_global_mem_new_i32(cpu_env, |
259186a7 AF |
97 | -offsetof(M68kCPU, env) + |
98 | offsetof(CPUState, halted), "HALTED"); | |
e1ccc054 | 99 | cpu_exception_index = tcg_global_mem_new_i32(cpu_env, |
27103424 AF |
100 | -offsetof(M68kCPU, env) + |
101 | offsetof(CPUState, exception_index), | |
102 | "EXCEPTION"); | |
259186a7 | 103 | |
e1f3808e PB |
104 | p = cpu_reg_names; |
105 | for (i = 0; i < 8; i++) { | |
106 | sprintf(p, "D%d", i); | |
e1ccc054 | 107 | cpu_dregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
108 | offsetof(CPUM68KState, dregs[i]), p); |
109 | p += 3; | |
110 | sprintf(p, "A%d", i); | |
e1ccc054 | 111 | cpu_aregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
112 | offsetof(CPUM68KState, aregs[i]), p); |
113 | p += 3; | |
114 | sprintf(p, "F%d", i); | |
e1ccc054 | 115 | cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
116 | offsetof(CPUM68KState, fregs[i]), p); |
117 | p += 3; | |
118 | } | |
119 | for (i = 0; i < 4; i++) { | |
120 | sprintf(p, "ACC%d", i); | |
e1ccc054 | 121 | cpu_macc[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
122 | offsetof(CPUM68KState, macc[i]), p); |
123 | p += 5; | |
124 | } | |
125 | ||
e1ccc054 RH |
126 | NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL"); |
127 | store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL"); | |
e1f3808e PB |
128 | } |
129 | ||
e6e5906b PB |
130 | /* internal defines */ |
131 | typedef struct DisasContext { | |
e6dbd3b3 | 132 | CPUM68KState *env; |
510ff0b7 | 133 | target_ulong insn_pc; /* Start of the current instruction. */ |
e6e5906b PB |
134 | target_ulong pc; |
135 | int is_jmp; | |
136 | int cc_op; | |
0633879f | 137 | int user; |
e6e5906b PB |
138 | uint32_t fpcr; |
139 | struct TranslationBlock *tb; | |
140 | int singlestep_enabled; | |
a7812ae4 PB |
141 | TCGv_i64 mactmp; |
142 | int done_mac; | |
e6e5906b PB |
143 | } DisasContext; |
144 | ||
145 | #define DISAS_JUMP_NEXT 4 | |
146 | ||
0633879f PB |
147 | #if defined(CONFIG_USER_ONLY) |
148 | #define IS_USER(s) 1 | |
149 | #else | |
150 | #define IS_USER(s) s->user | |
151 | #endif | |
152 | ||
e6e5906b PB |
153 | /* XXX: move that elsewhere */ |
154 | /* ??? Fix exceptions. */ | |
155 | static void *gen_throws_exception; | |
156 | #define gen_last_qop NULL | |
157 | ||
d4d79bb1 | 158 | typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); |
e6e5906b | 159 | |
0633879f | 160 | #ifdef DEBUG_DISPATCH |
d4d79bb1 BS |
161 | #define DISAS_INSN(name) \ |
162 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
163 | uint16_t insn); \ | |
164 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
165 | uint16_t insn) \ | |
166 | { \ | |
167 | qemu_log("Dispatch " #name "\n"); \ | |
a1ff1930 | 168 | real_disas_##name(env, s, insn); \ |
d4d79bb1 BS |
169 | } \ |
170 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
171 | uint16_t insn) | |
0633879f | 172 | #else |
d4d79bb1 BS |
173 | #define DISAS_INSN(name) \ |
174 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
175 | uint16_t insn) | |
0633879f | 176 | #endif |
e6e5906b PB |
177 | |
178 | /* Generate a load from the specified address. Narrow values are | |
179 | sign extended to full register width. */ | |
e1f3808e | 180 | static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) |
e6e5906b | 181 | { |
e1f3808e PB |
182 | TCGv tmp; |
183 | int index = IS_USER(s); | |
a7812ae4 | 184 | tmp = tcg_temp_new_i32(); |
e6e5906b PB |
185 | switch(opsize) { |
186 | case OS_BYTE: | |
e6e5906b | 187 | if (sign) |
e1f3808e | 188 | tcg_gen_qemu_ld8s(tmp, addr, index); |
e6e5906b | 189 | else |
e1f3808e | 190 | tcg_gen_qemu_ld8u(tmp, addr, index); |
e6e5906b PB |
191 | break; |
192 | case OS_WORD: | |
e6e5906b | 193 | if (sign) |
e1f3808e | 194 | tcg_gen_qemu_ld16s(tmp, addr, index); |
e6e5906b | 195 | else |
e1f3808e | 196 | tcg_gen_qemu_ld16u(tmp, addr, index); |
e6e5906b PB |
197 | break; |
198 | case OS_LONG: | |
e6e5906b | 199 | case OS_SINGLE: |
a7812ae4 | 200 | tcg_gen_qemu_ld32u(tmp, addr, index); |
e6e5906b PB |
201 | break; |
202 | default: | |
7372c2b9 | 203 | g_assert_not_reached(); |
e6e5906b PB |
204 | } |
205 | gen_throws_exception = gen_last_qop; | |
206 | return tmp; | |
207 | } | |
208 | ||
a7812ae4 PB |
209 | static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) |
210 | { | |
211 | TCGv_i64 tmp; | |
212 | int index = IS_USER(s); | |
a7812ae4 PB |
213 | tmp = tcg_temp_new_i64(); |
214 | tcg_gen_qemu_ldf64(tmp, addr, index); | |
215 | gen_throws_exception = gen_last_qop; | |
216 | return tmp; | |
217 | } | |
218 | ||
e6e5906b | 219 | /* Generate a store. */ |
e1f3808e | 220 | static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) |
e6e5906b | 221 | { |
e1f3808e | 222 | int index = IS_USER(s); |
e6e5906b PB |
223 | switch(opsize) { |
224 | case OS_BYTE: | |
e1f3808e | 225 | tcg_gen_qemu_st8(val, addr, index); |
e6e5906b PB |
226 | break; |
227 | case OS_WORD: | |
e1f3808e | 228 | tcg_gen_qemu_st16(val, addr, index); |
e6e5906b PB |
229 | break; |
230 | case OS_LONG: | |
e6e5906b | 231 | case OS_SINGLE: |
a7812ae4 | 232 | tcg_gen_qemu_st32(val, addr, index); |
e6e5906b PB |
233 | break; |
234 | default: | |
7372c2b9 | 235 | g_assert_not_reached(); |
e6e5906b PB |
236 | } |
237 | gen_throws_exception = gen_last_qop; | |
238 | } | |
239 | ||
a7812ae4 PB |
240 | static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) |
241 | { | |
242 | int index = IS_USER(s); | |
a7812ae4 PB |
243 | tcg_gen_qemu_stf64(val, addr, index); |
244 | gen_throws_exception = gen_last_qop; | |
245 | } | |
246 | ||
e1f3808e PB |
247 | typedef enum { |
248 | EA_STORE, | |
249 | EA_LOADU, | |
250 | EA_LOADS | |
251 | } ea_what; | |
252 | ||
e6e5906b PB |
253 | /* Generate an unsigned load if VAL is 0 a signed load if val is -1, |
254 | otherwise generate a store. */ | |
e1f3808e PB |
255 | static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, |
256 | ea_what what) | |
e6e5906b | 257 | { |
e1f3808e | 258 | if (what == EA_STORE) { |
0633879f | 259 | gen_store(s, opsize, addr, val); |
e1f3808e | 260 | return store_dummy; |
e6e5906b | 261 | } else { |
e1f3808e | 262 | return gen_load(s, opsize, addr, what == EA_LOADS); |
e6e5906b PB |
263 | } |
264 | } | |
265 | ||
28b68cd7 LV |
266 | /* Read a 16-bit immediate constant */ |
267 | static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) | |
268 | { | |
269 | uint16_t im; | |
270 | im = cpu_lduw_code(env, s->pc); | |
271 | s->pc += 2; | |
272 | return im; | |
273 | } | |
274 | ||
275 | /* Read an 8-bit immediate constant */ | |
276 | static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s) | |
277 | { | |
278 | return read_im16(env, s); | |
279 | } | |
280 | ||
e6dbd3b3 | 281 | /* Read a 32-bit immediate constant. */ |
d4d79bb1 | 282 | static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) |
e6dbd3b3 PB |
283 | { |
284 | uint32_t im; | |
28b68cd7 LV |
285 | im = read_im16(env, s) << 16; |
286 | im |= 0xffff & read_im16(env, s); | |
e6dbd3b3 PB |
287 | return im; |
288 | } | |
289 | ||
290 | /* Calculate and address index. */ | |
e1f3808e | 291 | static TCGv gen_addr_index(uint16_t ext, TCGv tmp) |
e6dbd3b3 | 292 | { |
e1f3808e | 293 | TCGv add; |
e6dbd3b3 PB |
294 | int scale; |
295 | ||
296 | add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); | |
297 | if ((ext & 0x800) == 0) { | |
e1f3808e | 298 | tcg_gen_ext16s_i32(tmp, add); |
e6dbd3b3 PB |
299 | add = tmp; |
300 | } | |
301 | scale = (ext >> 9) & 3; | |
302 | if (scale != 0) { | |
e1f3808e | 303 | tcg_gen_shli_i32(tmp, add, scale); |
e6dbd3b3 PB |
304 | add = tmp; |
305 | } | |
306 | return add; | |
307 | } | |
308 | ||
e1f3808e PB |
309 | /* Handle a base + index + displacement effective addresss. |
310 | A NULL_QREG base means pc-relative. */ | |
a4356126 | 311 | static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) |
e6e5906b | 312 | { |
e6e5906b PB |
313 | uint32_t offset; |
314 | uint16_t ext; | |
e1f3808e PB |
315 | TCGv add; |
316 | TCGv tmp; | |
e6dbd3b3 | 317 | uint32_t bd, od; |
e6e5906b PB |
318 | |
319 | offset = s->pc; | |
28b68cd7 | 320 | ext = read_im16(env, s); |
e6dbd3b3 PB |
321 | |
322 | if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) | |
e1f3808e | 323 | return NULL_QREG; |
e6dbd3b3 | 324 | |
d8633620 LV |
325 | if (m68k_feature(s->env, M68K_FEATURE_M68000) && |
326 | !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) { | |
327 | ext &= ~(3 << 9); | |
328 | } | |
329 | ||
e6dbd3b3 PB |
330 | if (ext & 0x100) { |
331 | /* full extension word format */ | |
332 | if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) | |
e1f3808e | 333 | return NULL_QREG; |
e6dbd3b3 PB |
334 | |
335 | if ((ext & 0x30) > 0x10) { | |
336 | /* base displacement */ | |
337 | if ((ext & 0x30) == 0x20) { | |
28b68cd7 | 338 | bd = (int16_t)read_im16(env, s); |
e6dbd3b3 | 339 | } else { |
d4d79bb1 | 340 | bd = read_im32(env, s); |
e6dbd3b3 PB |
341 | } |
342 | } else { | |
343 | bd = 0; | |
344 | } | |
a7812ae4 | 345 | tmp = tcg_temp_new(); |
e6dbd3b3 PB |
346 | if ((ext & 0x44) == 0) { |
347 | /* pre-index */ | |
348 | add = gen_addr_index(ext, tmp); | |
349 | } else { | |
e1f3808e | 350 | add = NULL_QREG; |
e6dbd3b3 PB |
351 | } |
352 | if ((ext & 0x80) == 0) { | |
353 | /* base not suppressed */ | |
e1f3808e | 354 | if (IS_NULL_QREG(base)) { |
351326a6 | 355 | base = tcg_const_i32(offset + bd); |
e6dbd3b3 PB |
356 | bd = 0; |
357 | } | |
e1f3808e PB |
358 | if (!IS_NULL_QREG(add)) { |
359 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 PB |
360 | add = tmp; |
361 | } else { | |
362 | add = base; | |
363 | } | |
364 | } | |
e1f3808e | 365 | if (!IS_NULL_QREG(add)) { |
e6dbd3b3 | 366 | if (bd != 0) { |
e1f3808e | 367 | tcg_gen_addi_i32(tmp, add, bd); |
e6dbd3b3 PB |
368 | add = tmp; |
369 | } | |
370 | } else { | |
351326a6 | 371 | add = tcg_const_i32(bd); |
e6dbd3b3 PB |
372 | } |
373 | if ((ext & 3) != 0) { | |
374 | /* memory indirect */ | |
375 | base = gen_load(s, OS_LONG, add, 0); | |
376 | if ((ext & 0x44) == 4) { | |
377 | add = gen_addr_index(ext, tmp); | |
e1f3808e | 378 | tcg_gen_add_i32(tmp, add, base); |
e6dbd3b3 PB |
379 | add = tmp; |
380 | } else { | |
381 | add = base; | |
382 | } | |
383 | if ((ext & 3) > 1) { | |
384 | /* outer displacement */ | |
385 | if ((ext & 3) == 2) { | |
28b68cd7 | 386 | od = (int16_t)read_im16(env, s); |
e6dbd3b3 | 387 | } else { |
d4d79bb1 | 388 | od = read_im32(env, s); |
e6dbd3b3 PB |
389 | } |
390 | } else { | |
391 | od = 0; | |
392 | } | |
393 | if (od != 0) { | |
e1f3808e | 394 | tcg_gen_addi_i32(tmp, add, od); |
e6dbd3b3 PB |
395 | add = tmp; |
396 | } | |
397 | } | |
e6e5906b | 398 | } else { |
e6dbd3b3 | 399 | /* brief extension word format */ |
a7812ae4 | 400 | tmp = tcg_temp_new(); |
e6dbd3b3 | 401 | add = gen_addr_index(ext, tmp); |
e1f3808e PB |
402 | if (!IS_NULL_QREG(base)) { |
403 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 | 404 | if ((int8_t)ext) |
e1f3808e | 405 | tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); |
e6dbd3b3 | 406 | } else { |
e1f3808e | 407 | tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); |
e6dbd3b3 PB |
408 | } |
409 | add = tmp; | |
e6e5906b | 410 | } |
e6dbd3b3 | 411 | return add; |
e6e5906b PB |
412 | } |
413 | ||
e6e5906b PB |
414 | /* Update the CPU env CC_OP state. */ |
415 | static inline void gen_flush_cc_op(DisasContext *s) | |
416 | { | |
417 | if (s->cc_op != CC_OP_DYNAMIC) | |
e1f3808e | 418 | tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); |
e6e5906b PB |
419 | } |
420 | ||
421 | /* Evaluate all the CC flags. */ | |
422 | static inline void gen_flush_flags(DisasContext *s) | |
423 | { | |
424 | if (s->cc_op == CC_OP_FLAGS) | |
425 | return; | |
0cf5c677 | 426 | gen_flush_cc_op(s); |
e1f3808e | 427 | gen_helper_flush_flags(cpu_env, QREG_CC_OP); |
e6e5906b PB |
428 | s->cc_op = CC_OP_FLAGS; |
429 | } | |
430 | ||
5dbb6784 LV |
431 | #define SET_CC_OP(opsize, op) do { \ |
432 | switch (opsize) { \ | |
433 | case OS_BYTE: \ | |
434 | s->cc_op = CC_OP_##op##B; break; \ | |
435 | case OS_WORD: \ | |
436 | s->cc_op = CC_OP_##op##W; break; \ | |
437 | case OS_LONG: \ | |
438 | s->cc_op = CC_OP_##op; break; \ | |
439 | default: \ | |
440 | abort(); \ | |
441 | } \ | |
442 | } while (0) | |
443 | ||
444 | static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) | |
e1f3808e PB |
445 | { |
446 | tcg_gen_mov_i32(QREG_CC_DEST, val); | |
5dbb6784 | 447 | SET_CC_OP(opsize, LOGIC); |
e1f3808e PB |
448 | } |
449 | ||
450 | static void gen_update_cc_add(TCGv dest, TCGv src) | |
451 | { | |
452 | tcg_gen_mov_i32(QREG_CC_DEST, dest); | |
453 | tcg_gen_mov_i32(QREG_CC_SRC, src); | |
454 | } | |
455 | ||
e6e5906b PB |
456 | static inline int opsize_bytes(int opsize) |
457 | { | |
458 | switch (opsize) { | |
459 | case OS_BYTE: return 1; | |
460 | case OS_WORD: return 2; | |
461 | case OS_LONG: return 4; | |
462 | case OS_SINGLE: return 4; | |
463 | case OS_DOUBLE: return 8; | |
7ef25cdd LV |
464 | case OS_EXTENDED: return 12; |
465 | case OS_PACKED: return 12; | |
466 | default: | |
467 | g_assert_not_reached(); | |
468 | } | |
469 | } | |
470 | ||
471 | static inline int insn_opsize(int insn) | |
472 | { | |
473 | switch ((insn >> 6) & 3) { | |
474 | case 0: return OS_BYTE; | |
475 | case 1: return OS_WORD; | |
476 | case 2: return OS_LONG; | |
e6e5906b | 477 | default: |
7372c2b9 | 478 | g_assert_not_reached(); |
e6e5906b PB |
479 | } |
480 | } | |
481 | ||
482 | /* Assign value to a register. If the width is less than the register width | |
483 | only the low part of the register is set. */ | |
e1f3808e | 484 | static void gen_partset_reg(int opsize, TCGv reg, TCGv val) |
e6e5906b | 485 | { |
e1f3808e | 486 | TCGv tmp; |
e6e5906b PB |
487 | switch (opsize) { |
488 | case OS_BYTE: | |
e1f3808e | 489 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
a7812ae4 | 490 | tmp = tcg_temp_new(); |
e1f3808e PB |
491 | tcg_gen_ext8u_i32(tmp, val); |
492 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
493 | break; |
494 | case OS_WORD: | |
e1f3808e | 495 | tcg_gen_andi_i32(reg, reg, 0xffff0000); |
a7812ae4 | 496 | tmp = tcg_temp_new(); |
e1f3808e PB |
497 | tcg_gen_ext16u_i32(tmp, val); |
498 | tcg_gen_or_i32(reg, reg, tmp); | |
e6e5906b PB |
499 | break; |
500 | case OS_LONG: | |
e6e5906b | 501 | case OS_SINGLE: |
a7812ae4 | 502 | tcg_gen_mov_i32(reg, val); |
e6e5906b PB |
503 | break; |
504 | default: | |
7372c2b9 | 505 | g_assert_not_reached(); |
e6e5906b PB |
506 | } |
507 | } | |
508 | ||
509 | /* Sign or zero extend a value. */ | |
e1f3808e | 510 | static inline TCGv gen_extend(TCGv val, int opsize, int sign) |
e6e5906b | 511 | { |
e1f3808e | 512 | TCGv tmp; |
e6e5906b PB |
513 | |
514 | switch (opsize) { | |
515 | case OS_BYTE: | |
a7812ae4 | 516 | tmp = tcg_temp_new(); |
e6e5906b | 517 | if (sign) |
e1f3808e | 518 | tcg_gen_ext8s_i32(tmp, val); |
e6e5906b | 519 | else |
e1f3808e | 520 | tcg_gen_ext8u_i32(tmp, val); |
e6e5906b PB |
521 | break; |
522 | case OS_WORD: | |
a7812ae4 | 523 | tmp = tcg_temp_new(); |
e6e5906b | 524 | if (sign) |
e1f3808e | 525 | tcg_gen_ext16s_i32(tmp, val); |
e6e5906b | 526 | else |
e1f3808e | 527 | tcg_gen_ext16u_i32(tmp, val); |
e6e5906b PB |
528 | break; |
529 | case OS_LONG: | |
e6e5906b | 530 | case OS_SINGLE: |
a7812ae4 | 531 | tmp = val; |
e6e5906b PB |
532 | break; |
533 | default: | |
7372c2b9 | 534 | g_assert_not_reached(); |
e6e5906b PB |
535 | } |
536 | return tmp; | |
537 | } | |
538 | ||
539 | /* Generate code for an "effective address". Does not adjust the base | |
1addc7c5 | 540 | register for autoincrement addressing modes. */ |
d4d79bb1 BS |
541 | static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
542 | int opsize) | |
e6e5906b | 543 | { |
e1f3808e PB |
544 | TCGv reg; |
545 | TCGv tmp; | |
e6e5906b PB |
546 | uint16_t ext; |
547 | uint32_t offset; | |
548 | ||
e6e5906b PB |
549 | switch ((insn >> 3) & 7) { |
550 | case 0: /* Data register direct. */ | |
551 | case 1: /* Address register direct. */ | |
e1f3808e | 552 | return NULL_QREG; |
e6e5906b PB |
553 | case 2: /* Indirect register */ |
554 | case 3: /* Indirect postincrement. */ | |
e1f3808e | 555 | return AREG(insn, 0); |
e6e5906b | 556 | case 4: /* Indirect predecrememnt. */ |
e1f3808e | 557 | reg = AREG(insn, 0); |
a7812ae4 | 558 | tmp = tcg_temp_new(); |
e1f3808e | 559 | tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); |
e6e5906b PB |
560 | return tmp; |
561 | case 5: /* Indirect displacement. */ | |
e1f3808e | 562 | reg = AREG(insn, 0); |
a7812ae4 | 563 | tmp = tcg_temp_new(); |
28b68cd7 | 564 | ext = read_im16(env, s); |
e1f3808e | 565 | tcg_gen_addi_i32(tmp, reg, (int16_t)ext); |
e6e5906b PB |
566 | return tmp; |
567 | case 6: /* Indirect index + displacement. */ | |
e1f3808e | 568 | reg = AREG(insn, 0); |
a4356126 | 569 | return gen_lea_indexed(env, s, reg); |
e6e5906b | 570 | case 7: /* Other */ |
e1f3808e | 571 | switch (insn & 7) { |
e6e5906b | 572 | case 0: /* Absolute short. */ |
28b68cd7 | 573 | offset = (int16_t)read_im16(env, s); |
351326a6 | 574 | return tcg_const_i32(offset); |
e6e5906b | 575 | case 1: /* Absolute long. */ |
d4d79bb1 | 576 | offset = read_im32(env, s); |
351326a6 | 577 | return tcg_const_i32(offset); |
e6e5906b | 578 | case 2: /* pc displacement */ |
e6e5906b | 579 | offset = s->pc; |
28b68cd7 | 580 | offset += (int16_t)read_im16(env, s); |
351326a6 | 581 | return tcg_const_i32(offset); |
e6e5906b | 582 | case 3: /* pc index+displacement. */ |
a4356126 | 583 | return gen_lea_indexed(env, s, NULL_QREG); |
e6e5906b PB |
584 | case 4: /* Immediate. */ |
585 | default: | |
e1f3808e | 586 | return NULL_QREG; |
e6e5906b PB |
587 | } |
588 | } | |
589 | /* Should never happen. */ | |
e1f3808e | 590 | return NULL_QREG; |
e6e5906b PB |
591 | } |
592 | ||
593 | /* Helper function for gen_ea. Reuse the computed address between the | |
594 | for read/write operands. */ | |
d4d79bb1 BS |
595 | static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s, |
596 | uint16_t insn, int opsize, TCGv val, | |
597 | TCGv *addrp, ea_what what) | |
e6e5906b | 598 | { |
e1f3808e | 599 | TCGv tmp; |
e6e5906b | 600 | |
e1f3808e | 601 | if (addrp && what == EA_STORE) { |
e6e5906b PB |
602 | tmp = *addrp; |
603 | } else { | |
d4d79bb1 | 604 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
605 | if (IS_NULL_QREG(tmp)) |
606 | return tmp; | |
e6e5906b PB |
607 | if (addrp) |
608 | *addrp = tmp; | |
609 | } | |
e1f3808e | 610 | return gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
611 | } |
612 | ||
f38f7a84 | 613 | /* Generate code to load/store a value from/into an EA. If VAL > 0 this is |
e6e5906b PB |
614 | a write otherwise it is a read (0 == sign extend, -1 == zero extend). |
615 | ADDRP is non-null for readwrite operands. */ | |
d4d79bb1 BS |
616 | static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
617 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
e6e5906b | 618 | { |
e1f3808e PB |
619 | TCGv reg; |
620 | TCGv result; | |
e6e5906b PB |
621 | uint32_t offset; |
622 | ||
e6e5906b PB |
623 | switch ((insn >> 3) & 7) { |
624 | case 0: /* Data register direct. */ | |
e1f3808e PB |
625 | reg = DREG(insn, 0); |
626 | if (what == EA_STORE) { | |
e6e5906b | 627 | gen_partset_reg(opsize, reg, val); |
e1f3808e | 628 | return store_dummy; |
e6e5906b | 629 | } else { |
e1f3808e | 630 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
631 | } |
632 | case 1: /* Address register direct. */ | |
e1f3808e PB |
633 | reg = AREG(insn, 0); |
634 | if (what == EA_STORE) { | |
635 | tcg_gen_mov_i32(reg, val); | |
636 | return store_dummy; | |
e6e5906b | 637 | } else { |
e1f3808e | 638 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
639 | } |
640 | case 2: /* Indirect register */ | |
e1f3808e PB |
641 | reg = AREG(insn, 0); |
642 | return gen_ldst(s, opsize, reg, val, what); | |
e6e5906b | 643 | case 3: /* Indirect postincrement. */ |
e1f3808e PB |
644 | reg = AREG(insn, 0); |
645 | result = gen_ldst(s, opsize, reg, val, what); | |
e6e5906b PB |
646 | /* ??? This is not exception safe. The instruction may still |
647 | fault after this point. */ | |
e1f3808e PB |
648 | if (what == EA_STORE || !addrp) |
649 | tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize)); | |
e6e5906b PB |
650 | return result; |
651 | case 4: /* Indirect predecrememnt. */ | |
652 | { | |
e1f3808e PB |
653 | TCGv tmp; |
654 | if (addrp && what == EA_STORE) { | |
e6e5906b PB |
655 | tmp = *addrp; |
656 | } else { | |
d4d79bb1 | 657 | tmp = gen_lea(env, s, insn, opsize); |
e1f3808e PB |
658 | if (IS_NULL_QREG(tmp)) |
659 | return tmp; | |
e6e5906b PB |
660 | if (addrp) |
661 | *addrp = tmp; | |
662 | } | |
e1f3808e | 663 | result = gen_ldst(s, opsize, tmp, val, what); |
e6e5906b PB |
664 | /* ??? This is not exception safe. The instruction may still |
665 | fault after this point. */ | |
e1f3808e PB |
666 | if (what == EA_STORE || !addrp) { |
667 | reg = AREG(insn, 0); | |
668 | tcg_gen_mov_i32(reg, tmp); | |
e6e5906b PB |
669 | } |
670 | } | |
671 | return result; | |
672 | case 5: /* Indirect displacement. */ | |
673 | case 6: /* Indirect index + displacement. */ | |
d4d79bb1 | 674 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b | 675 | case 7: /* Other */ |
e1f3808e | 676 | switch (insn & 7) { |
e6e5906b PB |
677 | case 0: /* Absolute short. */ |
678 | case 1: /* Absolute long. */ | |
679 | case 2: /* pc displacement */ | |
680 | case 3: /* pc index+displacement. */ | |
d4d79bb1 | 681 | return gen_ea_once(env, s, insn, opsize, val, addrp, what); |
e6e5906b PB |
682 | case 4: /* Immediate. */ |
683 | /* Sign extend values for consistency. */ | |
684 | switch (opsize) { | |
685 | case OS_BYTE: | |
31871141 | 686 | if (what == EA_LOADS) { |
28b68cd7 | 687 | offset = (int8_t)read_im8(env, s); |
31871141 | 688 | } else { |
28b68cd7 | 689 | offset = read_im8(env, s); |
31871141 | 690 | } |
e6e5906b PB |
691 | break; |
692 | case OS_WORD: | |
31871141 | 693 | if (what == EA_LOADS) { |
28b68cd7 | 694 | offset = (int16_t)read_im16(env, s); |
31871141 | 695 | } else { |
28b68cd7 | 696 | offset = read_im16(env, s); |
31871141 | 697 | } |
e6e5906b PB |
698 | break; |
699 | case OS_LONG: | |
d4d79bb1 | 700 | offset = read_im32(env, s); |
e6e5906b PB |
701 | break; |
702 | default: | |
7372c2b9 | 703 | g_assert_not_reached(); |
e6e5906b | 704 | } |
e1f3808e | 705 | return tcg_const_i32(offset); |
e6e5906b | 706 | default: |
e1f3808e | 707 | return NULL_QREG; |
e6e5906b PB |
708 | } |
709 | } | |
710 | /* Should never happen. */ | |
e1f3808e | 711 | return NULL_QREG; |
e6e5906b PB |
712 | } |
713 | ||
e1f3808e | 714 | /* This generates a conditional branch, clobbering all temporaries. */ |
42a268c2 | 715 | static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) |
e6e5906b | 716 | { |
e1f3808e | 717 | TCGv tmp; |
e6e5906b | 718 | |
e1f3808e PB |
719 | /* TODO: Optimize compare/branch pairs rather than always flushing |
720 | flag state to CC_OP_FLAGS. */ | |
e6e5906b PB |
721 | gen_flush_flags(s); |
722 | switch (cond) { | |
723 | case 0: /* T */ | |
e1f3808e | 724 | tcg_gen_br(l1); |
e6e5906b PB |
725 | break; |
726 | case 1: /* F */ | |
727 | break; | |
728 | case 2: /* HI (!C && !Z) */ | |
a7812ae4 | 729 | tmp = tcg_temp_new(); |
e1f3808e PB |
730 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
731 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
732 | break; |
733 | case 3: /* LS (C || Z) */ | |
a7812ae4 | 734 | tmp = tcg_temp_new(); |
e1f3808e PB |
735 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); |
736 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
737 | break; |
738 | case 4: /* CC (!C) */ | |
a7812ae4 | 739 | tmp = tcg_temp_new(); |
e1f3808e PB |
740 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
741 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
742 | break; |
743 | case 5: /* CS (C) */ | |
a7812ae4 | 744 | tmp = tcg_temp_new(); |
e1f3808e PB |
745 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); |
746 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
747 | break; |
748 | case 6: /* NE (!Z) */ | |
a7812ae4 | 749 | tmp = tcg_temp_new(); |
e1f3808e PB |
750 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
751 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
752 | break; |
753 | case 7: /* EQ (Z) */ | |
a7812ae4 | 754 | tmp = tcg_temp_new(); |
e1f3808e PB |
755 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); |
756 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
757 | break; |
758 | case 8: /* VC (!V) */ | |
a7812ae4 | 759 | tmp = tcg_temp_new(); |
e1f3808e PB |
760 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
761 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
762 | break; |
763 | case 9: /* VS (V) */ | |
a7812ae4 | 764 | tmp = tcg_temp_new(); |
e1f3808e PB |
765 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); |
766 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
767 | break; |
768 | case 10: /* PL (!N) */ | |
a7812ae4 | 769 | tmp = tcg_temp_new(); |
e1f3808e PB |
770 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
771 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
772 | break; |
773 | case 11: /* MI (N) */ | |
a7812ae4 | 774 | tmp = tcg_temp_new(); |
e1f3808e PB |
775 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); |
776 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
777 | break; |
778 | case 12: /* GE (!(N ^ V)) */ | |
a7812ae4 | 779 | tmp = tcg_temp_new(); |
e1f3808e PB |
780 | assert(CCF_V == (CCF_N >> 2)); |
781 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
782 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
783 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
784 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
785 | break; |
786 | case 13: /* LT (N ^ V) */ | |
a7812ae4 | 787 | tmp = tcg_temp_new(); |
e1f3808e PB |
788 | assert(CCF_V == (CCF_N >> 2)); |
789 | tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); | |
790 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
791 | tcg_gen_andi_i32(tmp, tmp, CCF_V); | |
792 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
793 | break; |
794 | case 14: /* GT (!(Z || (N ^ V))) */ | |
a7812ae4 | 795 | tmp = tcg_temp_new(); |
e1f3808e PB |
796 | assert(CCF_V == (CCF_N >> 2)); |
797 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
798 | tcg_gen_shri_i32(tmp, tmp, 2); | |
799 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
800 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
801 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); | |
e6e5906b PB |
802 | break; |
803 | case 15: /* LE (Z || (N ^ V)) */ | |
a7812ae4 | 804 | tmp = tcg_temp_new(); |
e1f3808e PB |
805 | assert(CCF_V == (CCF_N >> 2)); |
806 | tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); | |
807 | tcg_gen_shri_i32(tmp, tmp, 2); | |
808 | tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); | |
809 | tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); | |
810 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); | |
e6e5906b PB |
811 | break; |
812 | default: | |
813 | /* Should ever happen. */ | |
814 | abort(); | |
815 | } | |
816 | } | |
817 | ||
818 | DISAS_INSN(scc) | |
819 | { | |
42a268c2 | 820 | TCGLabel *l1; |
e6e5906b | 821 | int cond; |
e1f3808e | 822 | TCGv reg; |
e6e5906b PB |
823 | |
824 | l1 = gen_new_label(); | |
825 | cond = (insn >> 8) & 0xf; | |
826 | reg = DREG(insn, 0); | |
e1f3808e PB |
827 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
828 | /* This is safe because we modify the reg directly, with no other values | |
829 | live. */ | |
e6e5906b | 830 | gen_jmpcc(s, cond ^ 1, l1); |
e1f3808e | 831 | tcg_gen_ori_i32(reg, reg, 0xff); |
e6e5906b PB |
832 | gen_set_label(l1); |
833 | } | |
834 | ||
0633879f PB |
835 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
836 | static void gen_lookup_tb(DisasContext *s) | |
837 | { | |
838 | gen_flush_cc_op(s); | |
e1f3808e | 839 | tcg_gen_movi_i32(QREG_PC, s->pc); |
0633879f PB |
840 | s->is_jmp = DISAS_UPDATE; |
841 | } | |
842 | ||
e1f3808e PB |
843 | /* Generate a jump to an immediate address. */ |
844 | static void gen_jmp_im(DisasContext *s, uint32_t dest) | |
845 | { | |
846 | gen_flush_cc_op(s); | |
847 | tcg_gen_movi_i32(QREG_PC, dest); | |
848 | s->is_jmp = DISAS_JUMP; | |
849 | } | |
850 | ||
851 | /* Generate a jump to the address in qreg DEST. */ | |
852 | static void gen_jmp(DisasContext *s, TCGv dest) | |
e6e5906b PB |
853 | { |
854 | gen_flush_cc_op(s); | |
e1f3808e | 855 | tcg_gen_mov_i32(QREG_PC, dest); |
e6e5906b PB |
856 | s->is_jmp = DISAS_JUMP; |
857 | } | |
858 | ||
859 | static void gen_exception(DisasContext *s, uint32_t where, int nr) | |
860 | { | |
861 | gen_flush_cc_op(s); | |
e1f3808e | 862 | gen_jmp_im(s, where); |
31871141 | 863 | gen_helper_raise_exception(cpu_env, tcg_const_i32(nr)); |
e6e5906b PB |
864 | } |
865 | ||
510ff0b7 PB |
866 | static inline void gen_addr_fault(DisasContext *s) |
867 | { | |
868 | gen_exception(s, s->insn_pc, EXCP_ADDRESS); | |
869 | } | |
870 | ||
d4d79bb1 BS |
871 | #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ |
872 | result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ | |
873 | op_sign ? EA_LOADS : EA_LOADU); \ | |
874 | if (IS_NULL_QREG(result)) { \ | |
875 | gen_addr_fault(s); \ | |
876 | return; \ | |
877 | } \ | |
510ff0b7 PB |
878 | } while (0) |
879 | ||
d4d79bb1 BS |
880 | #define DEST_EA(env, insn, opsize, val, addrp) do { \ |
881 | TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ | |
882 | if (IS_NULL_QREG(ea_result)) { \ | |
883 | gen_addr_fault(s); \ | |
884 | return; \ | |
885 | } \ | |
510ff0b7 PB |
886 | } while (0) |
887 | ||
90aa39a1 SF |
888 | static inline bool use_goto_tb(DisasContext *s, uint32_t dest) |
889 | { | |
890 | #ifndef CONFIG_USER_ONLY | |
891 | return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || | |
892 | (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
893 | #else | |
894 | return true; | |
895 | #endif | |
896 | } | |
897 | ||
e6e5906b PB |
898 | /* Generate a jump to an immediate address. */ |
899 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | |
900 | { | |
551bd27f | 901 | if (unlikely(s->singlestep_enabled)) { |
e6e5906b | 902 | gen_exception(s, dest, EXCP_DEBUG); |
90aa39a1 | 903 | } else if (use_goto_tb(s, dest)) { |
57fec1fe | 904 | tcg_gen_goto_tb(n); |
e1f3808e | 905 | tcg_gen_movi_i32(QREG_PC, dest); |
90aa39a1 | 906 | tcg_gen_exit_tb((uintptr_t)s->tb + n); |
e6e5906b | 907 | } else { |
e1f3808e | 908 | gen_jmp_im(s, dest); |
57fec1fe | 909 | tcg_gen_exit_tb(0); |
e6e5906b PB |
910 | } |
911 | s->is_jmp = DISAS_TB_JUMP; | |
912 | } | |
913 | ||
914 | DISAS_INSN(undef_mac) | |
915 | { | |
916 | gen_exception(s, s->pc - 2, EXCP_LINEA); | |
917 | } | |
918 | ||
919 | DISAS_INSN(undef_fpu) | |
920 | { | |
921 | gen_exception(s, s->pc - 2, EXCP_LINEF); | |
922 | } | |
923 | ||
924 | DISAS_INSN(undef) | |
925 | { | |
a47dddd7 AF |
926 | M68kCPU *cpu = m68k_env_get_cpu(env); |
927 | ||
e6e5906b | 928 | gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); |
a47dddd7 | 929 | cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); |
e6e5906b PB |
930 | } |
931 | ||
932 | DISAS_INSN(mulw) | |
933 | { | |
e1f3808e PB |
934 | TCGv reg; |
935 | TCGv tmp; | |
936 | TCGv src; | |
e6e5906b PB |
937 | int sign; |
938 | ||
939 | sign = (insn & 0x100) != 0; | |
940 | reg = DREG(insn, 9); | |
a7812ae4 | 941 | tmp = tcg_temp_new(); |
e6e5906b | 942 | if (sign) |
e1f3808e | 943 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 944 | else |
e1f3808e | 945 | tcg_gen_ext16u_i32(tmp, reg); |
d4d79bb1 | 946 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e PB |
947 | tcg_gen_mul_i32(tmp, tmp, src); |
948 | tcg_gen_mov_i32(reg, tmp); | |
5dbb6784 | 949 | gen_logic_cc(s, tmp, OS_WORD); |
e6e5906b PB |
950 | } |
951 | ||
952 | DISAS_INSN(divw) | |
953 | { | |
e1f3808e PB |
954 | TCGv reg; |
955 | TCGv tmp; | |
956 | TCGv src; | |
e6e5906b PB |
957 | int sign; |
958 | ||
959 | sign = (insn & 0x100) != 0; | |
960 | reg = DREG(insn, 9); | |
961 | if (sign) { | |
e1f3808e | 962 | tcg_gen_ext16s_i32(QREG_DIV1, reg); |
e6e5906b | 963 | } else { |
e1f3808e | 964 | tcg_gen_ext16u_i32(QREG_DIV1, reg); |
e6e5906b | 965 | } |
d4d79bb1 | 966 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e | 967 | tcg_gen_mov_i32(QREG_DIV2, src); |
e6e5906b | 968 | if (sign) { |
e1f3808e | 969 | gen_helper_divs(cpu_env, tcg_const_i32(1)); |
e6e5906b | 970 | } else { |
e1f3808e | 971 | gen_helper_divu(cpu_env, tcg_const_i32(1)); |
e6e5906b PB |
972 | } |
973 | ||
a7812ae4 PB |
974 | tmp = tcg_temp_new(); |
975 | src = tcg_temp_new(); | |
e1f3808e PB |
976 | tcg_gen_ext16u_i32(tmp, QREG_DIV1); |
977 | tcg_gen_shli_i32(src, QREG_DIV2, 16); | |
978 | tcg_gen_or_i32(reg, tmp, src); | |
e6e5906b PB |
979 | s->cc_op = CC_OP_FLAGS; |
980 | } | |
981 | ||
982 | DISAS_INSN(divl) | |
983 | { | |
e1f3808e PB |
984 | TCGv num; |
985 | TCGv den; | |
986 | TCGv reg; | |
e6e5906b PB |
987 | uint16_t ext; |
988 | ||
28b68cd7 | 989 | ext = read_im16(env, s); |
e6e5906b PB |
990 | if (ext & 0x87f8) { |
991 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
992 | return; | |
993 | } | |
994 | num = DREG(ext, 12); | |
995 | reg = DREG(ext, 0); | |
e1f3808e | 996 | tcg_gen_mov_i32(QREG_DIV1, num); |
d4d79bb1 | 997 | SRC_EA(env, den, OS_LONG, 0, NULL); |
e1f3808e | 998 | tcg_gen_mov_i32(QREG_DIV2, den); |
e6e5906b | 999 | if (ext & 0x0800) { |
e1f3808e | 1000 | gen_helper_divs(cpu_env, tcg_const_i32(0)); |
e6e5906b | 1001 | } else { |
e1f3808e | 1002 | gen_helper_divu(cpu_env, tcg_const_i32(0)); |
e6e5906b | 1003 | } |
e1f3808e | 1004 | if ((ext & 7) == ((ext >> 12) & 7)) { |
e6e5906b | 1005 | /* div */ |
e1f3808e | 1006 | tcg_gen_mov_i32 (reg, QREG_DIV1); |
e6e5906b PB |
1007 | } else { |
1008 | /* rem */ | |
e1f3808e | 1009 | tcg_gen_mov_i32 (reg, QREG_DIV2); |
e6e5906b | 1010 | } |
e6e5906b PB |
1011 | s->cc_op = CC_OP_FLAGS; |
1012 | } | |
1013 | ||
1014 | DISAS_INSN(addsub) | |
1015 | { | |
e1f3808e PB |
1016 | TCGv reg; |
1017 | TCGv dest; | |
1018 | TCGv src; | |
1019 | TCGv tmp; | |
1020 | TCGv addr; | |
e6e5906b PB |
1021 | int add; |
1022 | ||
1023 | add = (insn & 0x4000) != 0; | |
1024 | reg = DREG(insn, 9); | |
a7812ae4 | 1025 | dest = tcg_temp_new(); |
e6e5906b | 1026 | if (insn & 0x100) { |
d4d79bb1 | 1027 | SRC_EA(env, tmp, OS_LONG, 0, &addr); |
e6e5906b PB |
1028 | src = reg; |
1029 | } else { | |
1030 | tmp = reg; | |
d4d79bb1 | 1031 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b PB |
1032 | } |
1033 | if (add) { | |
e1f3808e | 1034 | tcg_gen_add_i32(dest, tmp, src); |
f9083519 | 1035 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); |
e6e5906b PB |
1036 | s->cc_op = CC_OP_ADD; |
1037 | } else { | |
f9083519 | 1038 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); |
e1f3808e | 1039 | tcg_gen_sub_i32(dest, tmp, src); |
e6e5906b PB |
1040 | s->cc_op = CC_OP_SUB; |
1041 | } | |
e1f3808e | 1042 | gen_update_cc_add(dest, src); |
e6e5906b | 1043 | if (insn & 0x100) { |
d4d79bb1 | 1044 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1045 | } else { |
e1f3808e | 1046 | tcg_gen_mov_i32(reg, dest); |
e6e5906b PB |
1047 | } |
1048 | } | |
1049 | ||
1050 | ||
1051 | /* Reverse the order of the bits in REG. */ | |
1052 | DISAS_INSN(bitrev) | |
1053 | { | |
e1f3808e | 1054 | TCGv reg; |
e6e5906b | 1055 | reg = DREG(insn, 0); |
e1f3808e | 1056 | gen_helper_bitrev(reg, reg); |
e6e5906b PB |
1057 | } |
1058 | ||
1059 | DISAS_INSN(bitop_reg) | |
1060 | { | |
1061 | int opsize; | |
1062 | int op; | |
e1f3808e PB |
1063 | TCGv src1; |
1064 | TCGv src2; | |
1065 | TCGv tmp; | |
1066 | TCGv addr; | |
1067 | TCGv dest; | |
e6e5906b PB |
1068 | |
1069 | if ((insn & 0x38) != 0) | |
1070 | opsize = OS_BYTE; | |
1071 | else | |
1072 | opsize = OS_LONG; | |
1073 | op = (insn >> 6) & 3; | |
d4d79bb1 | 1074 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1075 | src2 = DREG(insn, 9); |
a7812ae4 | 1076 | dest = tcg_temp_new(); |
e6e5906b PB |
1077 | |
1078 | gen_flush_flags(s); | |
a7812ae4 | 1079 | tmp = tcg_temp_new(); |
e6e5906b | 1080 | if (opsize == OS_BYTE) |
e1f3808e | 1081 | tcg_gen_andi_i32(tmp, src2, 7); |
e6e5906b | 1082 | else |
e1f3808e | 1083 | tcg_gen_andi_i32(tmp, src2, 31); |
e6e5906b | 1084 | src2 = tmp; |
a7812ae4 | 1085 | tmp = tcg_temp_new(); |
e1f3808e PB |
1086 | tcg_gen_shr_i32(tmp, src1, src2); |
1087 | tcg_gen_andi_i32(tmp, tmp, 1); | |
1088 | tcg_gen_shli_i32(tmp, tmp, 2); | |
1089 | /* Clear CCF_Z if bit set. */ | |
1090 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1091 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1092 | ||
1093 | tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2); | |
e6e5906b PB |
1094 | switch (op) { |
1095 | case 1: /* bchg */ | |
e1f3808e | 1096 | tcg_gen_xor_i32(dest, src1, tmp); |
e6e5906b PB |
1097 | break; |
1098 | case 2: /* bclr */ | |
e1f3808e PB |
1099 | tcg_gen_not_i32(tmp, tmp); |
1100 | tcg_gen_and_i32(dest, src1, tmp); | |
e6e5906b PB |
1101 | break; |
1102 | case 3: /* bset */ | |
e1f3808e | 1103 | tcg_gen_or_i32(dest, src1, tmp); |
e6e5906b PB |
1104 | break; |
1105 | default: /* btst */ | |
1106 | break; | |
1107 | } | |
1108 | if (op) | |
d4d79bb1 | 1109 | DEST_EA(env, insn, opsize, dest, &addr); |
e6e5906b PB |
1110 | } |
1111 | ||
1112 | DISAS_INSN(sats) | |
1113 | { | |
e1f3808e | 1114 | TCGv reg; |
e6e5906b | 1115 | reg = DREG(insn, 0); |
e6e5906b | 1116 | gen_flush_flags(s); |
e1f3808e | 1117 | gen_helper_sats(reg, reg, QREG_CC_DEST); |
5dbb6784 | 1118 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1119 | } |
1120 | ||
e1f3808e | 1121 | static void gen_push(DisasContext *s, TCGv val) |
e6e5906b | 1122 | { |
e1f3808e | 1123 | TCGv tmp; |
e6e5906b | 1124 | |
a7812ae4 | 1125 | tmp = tcg_temp_new(); |
e1f3808e | 1126 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1127 | gen_store(s, OS_LONG, tmp, val); |
e1f3808e | 1128 | tcg_gen_mov_i32(QREG_SP, tmp); |
e6e5906b PB |
1129 | } |
1130 | ||
1131 | DISAS_INSN(movem) | |
1132 | { | |
e1f3808e | 1133 | TCGv addr; |
e6e5906b PB |
1134 | int i; |
1135 | uint16_t mask; | |
e1f3808e PB |
1136 | TCGv reg; |
1137 | TCGv tmp; | |
e6e5906b PB |
1138 | int is_load; |
1139 | ||
28b68cd7 | 1140 | mask = read_im16(env, s); |
d4d79bb1 | 1141 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1142 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1143 | gen_addr_fault(s); |
1144 | return; | |
1145 | } | |
a7812ae4 | 1146 | addr = tcg_temp_new(); |
e1f3808e | 1147 | tcg_gen_mov_i32(addr, tmp); |
e6e5906b PB |
1148 | is_load = ((insn & 0x0400) != 0); |
1149 | for (i = 0; i < 16; i++, mask >>= 1) { | |
1150 | if (mask & 1) { | |
1151 | if (i < 8) | |
1152 | reg = DREG(i, 0); | |
1153 | else | |
1154 | reg = AREG(i, 0); | |
1155 | if (is_load) { | |
0633879f | 1156 | tmp = gen_load(s, OS_LONG, addr, 0); |
e1f3808e | 1157 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b | 1158 | } else { |
0633879f | 1159 | gen_store(s, OS_LONG, addr, reg); |
e6e5906b PB |
1160 | } |
1161 | if (mask != 1) | |
e1f3808e | 1162 | tcg_gen_addi_i32(addr, addr, 4); |
e6e5906b PB |
1163 | } |
1164 | } | |
1165 | } | |
1166 | ||
1167 | DISAS_INSN(bitop_im) | |
1168 | { | |
1169 | int opsize; | |
1170 | int op; | |
e1f3808e | 1171 | TCGv src1; |
e6e5906b PB |
1172 | uint32_t mask; |
1173 | int bitnum; | |
e1f3808e PB |
1174 | TCGv tmp; |
1175 | TCGv addr; | |
e6e5906b PB |
1176 | |
1177 | if ((insn & 0x38) != 0) | |
1178 | opsize = OS_BYTE; | |
1179 | else | |
1180 | opsize = OS_LONG; | |
1181 | op = (insn >> 6) & 3; | |
1182 | ||
28b68cd7 | 1183 | bitnum = read_im16(env, s); |
e6e5906b | 1184 | if (bitnum & 0xff00) { |
d4d79bb1 | 1185 | disas_undef(env, s, insn); |
e6e5906b PB |
1186 | return; |
1187 | } | |
1188 | ||
d4d79bb1 | 1189 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b PB |
1190 | |
1191 | gen_flush_flags(s); | |
e6e5906b PB |
1192 | if (opsize == OS_BYTE) |
1193 | bitnum &= 7; | |
1194 | else | |
1195 | bitnum &= 31; | |
1196 | mask = 1 << bitnum; | |
1197 | ||
a7812ae4 | 1198 | tmp = tcg_temp_new(); |
e1f3808e PB |
1199 | assert (CCF_Z == (1 << 2)); |
1200 | if (bitnum > 2) | |
1201 | tcg_gen_shri_i32(tmp, src1, bitnum - 2); | |
1202 | else if (bitnum < 2) | |
1203 | tcg_gen_shli_i32(tmp, src1, 2 - bitnum); | |
e6e5906b | 1204 | else |
e1f3808e PB |
1205 | tcg_gen_mov_i32(tmp, src1); |
1206 | tcg_gen_andi_i32(tmp, tmp, CCF_Z); | |
1207 | /* Clear CCF_Z if bit set. */ | |
1208 | tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); | |
1209 | tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); | |
1210 | if (op) { | |
1211 | switch (op) { | |
1212 | case 1: /* bchg */ | |
1213 | tcg_gen_xori_i32(tmp, src1, mask); | |
1214 | break; | |
1215 | case 2: /* bclr */ | |
1216 | tcg_gen_andi_i32(tmp, src1, ~mask); | |
1217 | break; | |
1218 | case 3: /* bset */ | |
1219 | tcg_gen_ori_i32(tmp, src1, mask); | |
1220 | break; | |
1221 | default: /* btst */ | |
1222 | break; | |
1223 | } | |
d4d79bb1 | 1224 | DEST_EA(env, insn, opsize, tmp, &addr); |
e6e5906b | 1225 | } |
e6e5906b PB |
1226 | } |
1227 | ||
1228 | DISAS_INSN(arith_im) | |
1229 | { | |
1230 | int op; | |
e1f3808e PB |
1231 | uint32_t im; |
1232 | TCGv src1; | |
1233 | TCGv dest; | |
1234 | TCGv addr; | |
e6e5906b PB |
1235 | |
1236 | op = (insn >> 9) & 7; | |
d4d79bb1 BS |
1237 | SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr); |
1238 | im = read_im32(env, s); | |
a7812ae4 | 1239 | dest = tcg_temp_new(); |
e6e5906b PB |
1240 | switch (op) { |
1241 | case 0: /* ori */ | |
e1f3808e | 1242 | tcg_gen_ori_i32(dest, src1, im); |
5dbb6784 | 1243 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1244 | break; |
1245 | case 1: /* andi */ | |
e1f3808e | 1246 | tcg_gen_andi_i32(dest, src1, im); |
5dbb6784 | 1247 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1248 | break; |
1249 | case 2: /* subi */ | |
e1f3808e | 1250 | tcg_gen_mov_i32(dest, src1); |
f9083519 | 1251 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, tcg_const_i32(im)); |
e1f3808e | 1252 | tcg_gen_subi_i32(dest, dest, im); |
351326a6 | 1253 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1254 | s->cc_op = CC_OP_SUB; |
1255 | break; | |
1256 | case 3: /* addi */ | |
e1f3808e PB |
1257 | tcg_gen_mov_i32(dest, src1); |
1258 | tcg_gen_addi_i32(dest, dest, im); | |
351326a6 | 1259 | gen_update_cc_add(dest, tcg_const_i32(im)); |
f9083519 | 1260 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, tcg_const_i32(im)); |
e6e5906b PB |
1261 | s->cc_op = CC_OP_ADD; |
1262 | break; | |
1263 | case 5: /* eori */ | |
e1f3808e | 1264 | tcg_gen_xori_i32(dest, src1, im); |
5dbb6784 | 1265 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1266 | break; |
1267 | case 6: /* cmpi */ | |
e1f3808e PB |
1268 | tcg_gen_mov_i32(dest, src1); |
1269 | tcg_gen_subi_i32(dest, dest, im); | |
351326a6 | 1270 | gen_update_cc_add(dest, tcg_const_i32(im)); |
e6e5906b PB |
1271 | s->cc_op = CC_OP_SUB; |
1272 | break; | |
1273 | default: | |
1274 | abort(); | |
1275 | } | |
1276 | if (op != 6) { | |
d4d79bb1 | 1277 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1278 | } |
1279 | } | |
1280 | ||
1281 | DISAS_INSN(byterev) | |
1282 | { | |
e1f3808e | 1283 | TCGv reg; |
e6e5906b PB |
1284 | |
1285 | reg = DREG(insn, 0); | |
66896cb8 | 1286 | tcg_gen_bswap32_i32(reg, reg); |
e6e5906b PB |
1287 | } |
1288 | ||
1289 | DISAS_INSN(move) | |
1290 | { | |
e1f3808e PB |
1291 | TCGv src; |
1292 | TCGv dest; | |
e6e5906b PB |
1293 | int op; |
1294 | int opsize; | |
1295 | ||
1296 | switch (insn >> 12) { | |
1297 | case 1: /* move.b */ | |
1298 | opsize = OS_BYTE; | |
1299 | break; | |
1300 | case 2: /* move.l */ | |
1301 | opsize = OS_LONG; | |
1302 | break; | |
1303 | case 3: /* move.w */ | |
1304 | opsize = OS_WORD; | |
1305 | break; | |
1306 | default: | |
1307 | abort(); | |
1308 | } | |
d4d79bb1 | 1309 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b PB |
1310 | op = (insn >> 6) & 7; |
1311 | if (op == 1) { | |
1312 | /* movea */ | |
1313 | /* The value will already have been sign extended. */ | |
1314 | dest = AREG(insn, 9); | |
e1f3808e | 1315 | tcg_gen_mov_i32(dest, src); |
e6e5906b PB |
1316 | } else { |
1317 | /* normal move */ | |
1318 | uint16_t dest_ea; | |
1319 | dest_ea = ((insn >> 9) & 7) | (op << 3); | |
d4d79bb1 | 1320 | DEST_EA(env, dest_ea, opsize, src, NULL); |
e6e5906b | 1321 | /* This will be correct because loads sign extend. */ |
5dbb6784 | 1322 | gen_logic_cc(s, src, opsize); |
e6e5906b PB |
1323 | } |
1324 | } | |
1325 | ||
1326 | DISAS_INSN(negx) | |
1327 | { | |
e1f3808e | 1328 | TCGv reg; |
e6e5906b PB |
1329 | |
1330 | gen_flush_flags(s); | |
1331 | reg = DREG(insn, 0); | |
e1f3808e | 1332 | gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg); |
e6e5906b PB |
1333 | } |
1334 | ||
1335 | DISAS_INSN(lea) | |
1336 | { | |
e1f3808e PB |
1337 | TCGv reg; |
1338 | TCGv tmp; | |
e6e5906b PB |
1339 | |
1340 | reg = AREG(insn, 9); | |
d4d79bb1 | 1341 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1342 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1343 | gen_addr_fault(s); |
1344 | return; | |
1345 | } | |
e1f3808e | 1346 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
1347 | } |
1348 | ||
1349 | DISAS_INSN(clr) | |
1350 | { | |
1351 | int opsize; | |
1352 | ||
7ef25cdd | 1353 | opsize = insn_opsize(insn); |
d4d79bb1 | 1354 | DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL); |
5dbb6784 | 1355 | gen_logic_cc(s, tcg_const_i32(0), opsize); |
e6e5906b PB |
1356 | } |
1357 | ||
e1f3808e | 1358 | static TCGv gen_get_ccr(DisasContext *s) |
e6e5906b | 1359 | { |
e1f3808e | 1360 | TCGv dest; |
e6e5906b PB |
1361 | |
1362 | gen_flush_flags(s); | |
a7812ae4 | 1363 | dest = tcg_temp_new(); |
e1f3808e PB |
1364 | tcg_gen_shli_i32(dest, QREG_CC_X, 4); |
1365 | tcg_gen_or_i32(dest, dest, QREG_CC_DEST); | |
0633879f PB |
1366 | return dest; |
1367 | } | |
1368 | ||
1369 | DISAS_INSN(move_from_ccr) | |
1370 | { | |
e1f3808e PB |
1371 | TCGv reg; |
1372 | TCGv ccr; | |
0633879f PB |
1373 | |
1374 | ccr = gen_get_ccr(s); | |
e6e5906b | 1375 | reg = DREG(insn, 0); |
0633879f | 1376 | gen_partset_reg(OS_WORD, reg, ccr); |
e6e5906b PB |
1377 | } |
1378 | ||
1379 | DISAS_INSN(neg) | |
1380 | { | |
e1f3808e PB |
1381 | TCGv reg; |
1382 | TCGv src1; | |
e6e5906b PB |
1383 | |
1384 | reg = DREG(insn, 0); | |
a7812ae4 | 1385 | src1 = tcg_temp_new(); |
e1f3808e PB |
1386 | tcg_gen_mov_i32(src1, reg); |
1387 | tcg_gen_neg_i32(reg, src1); | |
e6e5906b | 1388 | s->cc_op = CC_OP_SUB; |
e1f3808e | 1389 | gen_update_cc_add(reg, src1); |
f9083519 | 1390 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tcg_const_i32(0), src1); |
e6e5906b PB |
1391 | s->cc_op = CC_OP_SUB; |
1392 | } | |
1393 | ||
0633879f PB |
1394 | static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) |
1395 | { | |
e1f3808e PB |
1396 | tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf); |
1397 | tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4); | |
0633879f | 1398 | if (!ccr_only) { |
e1f3808e | 1399 | gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00)); |
0633879f PB |
1400 | } |
1401 | } | |
1402 | ||
d4d79bb1 BS |
1403 | static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, |
1404 | int ccr_only) | |
e6e5906b | 1405 | { |
e1f3808e PB |
1406 | TCGv tmp; |
1407 | TCGv reg; | |
e6e5906b PB |
1408 | |
1409 | s->cc_op = CC_OP_FLAGS; | |
1410 | if ((insn & 0x38) == 0) | |
1411 | { | |
a7812ae4 | 1412 | tmp = tcg_temp_new(); |
e6e5906b | 1413 | reg = DREG(insn, 0); |
e1f3808e PB |
1414 | tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf); |
1415 | tcg_gen_shri_i32(tmp, reg, 4); | |
1416 | tcg_gen_andi_i32(QREG_CC_X, tmp, 1); | |
0633879f | 1417 | if (!ccr_only) { |
e1f3808e | 1418 | gen_helper_set_sr(cpu_env, reg); |
0633879f | 1419 | } |
e6e5906b | 1420 | } |
0633879f | 1421 | else if ((insn & 0x3f) == 0x3c) |
e6e5906b | 1422 | { |
0633879f | 1423 | uint16_t val; |
28b68cd7 | 1424 | val = read_im16(env, s); |
0633879f | 1425 | gen_set_sr_im(s, val, ccr_only); |
e6e5906b PB |
1426 | } |
1427 | else | |
d4d79bb1 | 1428 | disas_undef(env, s, insn); |
e6e5906b PB |
1429 | } |
1430 | ||
0633879f PB |
1431 | DISAS_INSN(move_to_ccr) |
1432 | { | |
d4d79bb1 | 1433 | gen_set_sr(env, s, insn, 1); |
0633879f PB |
1434 | } |
1435 | ||
e6e5906b PB |
1436 | DISAS_INSN(not) |
1437 | { | |
e1f3808e | 1438 | TCGv reg; |
e6e5906b PB |
1439 | |
1440 | reg = DREG(insn, 0); | |
e1f3808e | 1441 | tcg_gen_not_i32(reg, reg); |
5dbb6784 | 1442 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1443 | } |
1444 | ||
1445 | DISAS_INSN(swap) | |
1446 | { | |
e1f3808e PB |
1447 | TCGv src1; |
1448 | TCGv src2; | |
1449 | TCGv reg; | |
e6e5906b | 1450 | |
a7812ae4 PB |
1451 | src1 = tcg_temp_new(); |
1452 | src2 = tcg_temp_new(); | |
e6e5906b | 1453 | reg = DREG(insn, 0); |
e1f3808e PB |
1454 | tcg_gen_shli_i32(src1, reg, 16); |
1455 | tcg_gen_shri_i32(src2, reg, 16); | |
1456 | tcg_gen_or_i32(reg, src1, src2); | |
5dbb6784 | 1457 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1458 | } |
1459 | ||
1460 | DISAS_INSN(pea) | |
1461 | { | |
e1f3808e | 1462 | TCGv tmp; |
e6e5906b | 1463 | |
d4d79bb1 | 1464 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1465 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1466 | gen_addr_fault(s); |
1467 | return; | |
1468 | } | |
0633879f | 1469 | gen_push(s, tmp); |
e6e5906b PB |
1470 | } |
1471 | ||
1472 | DISAS_INSN(ext) | |
1473 | { | |
e6e5906b | 1474 | int op; |
e1f3808e PB |
1475 | TCGv reg; |
1476 | TCGv tmp; | |
e6e5906b PB |
1477 | |
1478 | reg = DREG(insn, 0); | |
1479 | op = (insn >> 6) & 7; | |
a7812ae4 | 1480 | tmp = tcg_temp_new(); |
e6e5906b | 1481 | if (op == 3) |
e1f3808e | 1482 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1483 | else |
e1f3808e | 1484 | tcg_gen_ext8s_i32(tmp, reg); |
e6e5906b PB |
1485 | if (op == 2) |
1486 | gen_partset_reg(OS_WORD, reg, tmp); | |
1487 | else | |
e1f3808e | 1488 | tcg_gen_mov_i32(reg, tmp); |
5dbb6784 | 1489 | gen_logic_cc(s, tmp, OS_LONG); |
e6e5906b PB |
1490 | } |
1491 | ||
1492 | DISAS_INSN(tst) | |
1493 | { | |
1494 | int opsize; | |
e1f3808e | 1495 | TCGv tmp; |
e6e5906b | 1496 | |
7ef25cdd | 1497 | opsize = insn_opsize(insn); |
d4d79bb1 | 1498 | SRC_EA(env, tmp, opsize, 1, NULL); |
5dbb6784 | 1499 | gen_logic_cc(s, tmp, opsize); |
e6e5906b PB |
1500 | } |
1501 | ||
1502 | DISAS_INSN(pulse) | |
1503 | { | |
1504 | /* Implemented as a NOP. */ | |
1505 | } | |
1506 | ||
1507 | DISAS_INSN(illegal) | |
1508 | { | |
1509 | gen_exception(s, s->pc - 2, EXCP_ILLEGAL); | |
1510 | } | |
1511 | ||
1512 | /* ??? This should be atomic. */ | |
1513 | DISAS_INSN(tas) | |
1514 | { | |
e1f3808e PB |
1515 | TCGv dest; |
1516 | TCGv src1; | |
1517 | TCGv addr; | |
e6e5906b | 1518 | |
a7812ae4 | 1519 | dest = tcg_temp_new(); |
d4d79bb1 | 1520 | SRC_EA(env, src1, OS_BYTE, 1, &addr); |
5dbb6784 | 1521 | gen_logic_cc(s, src1, OS_BYTE); |
e1f3808e | 1522 | tcg_gen_ori_i32(dest, src1, 0x80); |
d4d79bb1 | 1523 | DEST_EA(env, insn, OS_BYTE, dest, &addr); |
e6e5906b PB |
1524 | } |
1525 | ||
1526 | DISAS_INSN(mull) | |
1527 | { | |
1528 | uint16_t ext; | |
e1f3808e PB |
1529 | TCGv reg; |
1530 | TCGv src1; | |
1531 | TCGv dest; | |
e6e5906b PB |
1532 | |
1533 | /* The upper 32 bits of the product are discarded, so | |
1534 | muls.l and mulu.l are functionally equivalent. */ | |
28b68cd7 | 1535 | ext = read_im16(env, s); |
e6e5906b PB |
1536 | if (ext & 0x87ff) { |
1537 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
1538 | return; | |
1539 | } | |
1540 | reg = DREG(ext, 12); | |
d4d79bb1 | 1541 | SRC_EA(env, src1, OS_LONG, 0, NULL); |
a7812ae4 | 1542 | dest = tcg_temp_new(); |
e1f3808e PB |
1543 | tcg_gen_mul_i32(dest, src1, reg); |
1544 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b | 1545 | /* Unlike m68k, coldfire always clears the overflow bit. */ |
5dbb6784 | 1546 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1547 | } |
1548 | ||
1549 | DISAS_INSN(link) | |
1550 | { | |
1551 | int16_t offset; | |
e1f3808e PB |
1552 | TCGv reg; |
1553 | TCGv tmp; | |
e6e5906b | 1554 | |
d4d79bb1 | 1555 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
1556 | s->pc += 2; |
1557 | reg = AREG(insn, 0); | |
a7812ae4 | 1558 | tmp = tcg_temp_new(); |
e1f3808e | 1559 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1560 | gen_store(s, OS_LONG, tmp, reg); |
e1f3808e PB |
1561 | if ((insn & 7) != 7) |
1562 | tcg_gen_mov_i32(reg, tmp); | |
1563 | tcg_gen_addi_i32(QREG_SP, tmp, offset); | |
e6e5906b PB |
1564 | } |
1565 | ||
1566 | DISAS_INSN(unlk) | |
1567 | { | |
e1f3808e PB |
1568 | TCGv src; |
1569 | TCGv reg; | |
1570 | TCGv tmp; | |
e6e5906b | 1571 | |
a7812ae4 | 1572 | src = tcg_temp_new(); |
e6e5906b | 1573 | reg = AREG(insn, 0); |
e1f3808e | 1574 | tcg_gen_mov_i32(src, reg); |
0633879f | 1575 | tmp = gen_load(s, OS_LONG, src, 0); |
e1f3808e PB |
1576 | tcg_gen_mov_i32(reg, tmp); |
1577 | tcg_gen_addi_i32(QREG_SP, src, 4); | |
e6e5906b PB |
1578 | } |
1579 | ||
1580 | DISAS_INSN(nop) | |
1581 | { | |
1582 | } | |
1583 | ||
1584 | DISAS_INSN(rts) | |
1585 | { | |
e1f3808e | 1586 | TCGv tmp; |
e6e5906b | 1587 | |
0633879f | 1588 | tmp = gen_load(s, OS_LONG, QREG_SP, 0); |
e1f3808e | 1589 | tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); |
e6e5906b PB |
1590 | gen_jmp(s, tmp); |
1591 | } | |
1592 | ||
1593 | DISAS_INSN(jump) | |
1594 | { | |
e1f3808e | 1595 | TCGv tmp; |
e6e5906b PB |
1596 | |
1597 | /* Load the target address first to ensure correct exception | |
1598 | behavior. */ | |
d4d79bb1 | 1599 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 1600 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
1601 | gen_addr_fault(s); |
1602 | return; | |
1603 | } | |
e6e5906b PB |
1604 | if ((insn & 0x40) == 0) { |
1605 | /* jsr */ | |
351326a6 | 1606 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1607 | } |
1608 | gen_jmp(s, tmp); | |
1609 | } | |
1610 | ||
1611 | DISAS_INSN(addsubq) | |
1612 | { | |
e1f3808e PB |
1613 | TCGv src1; |
1614 | TCGv src2; | |
1615 | TCGv dest; | |
e6e5906b | 1616 | int val; |
e1f3808e | 1617 | TCGv addr; |
e6e5906b | 1618 | |
d4d79bb1 | 1619 | SRC_EA(env, src1, OS_LONG, 0, &addr); |
e6e5906b PB |
1620 | val = (insn >> 9) & 7; |
1621 | if (val == 0) | |
1622 | val = 8; | |
a7812ae4 | 1623 | dest = tcg_temp_new(); |
e1f3808e | 1624 | tcg_gen_mov_i32(dest, src1); |
e6e5906b PB |
1625 | if ((insn & 0x38) == 0x08) { |
1626 | /* Don't update condition codes if the destination is an | |
1627 | address register. */ | |
1628 | if (insn & 0x0100) { | |
e1f3808e | 1629 | tcg_gen_subi_i32(dest, dest, val); |
e6e5906b | 1630 | } else { |
e1f3808e | 1631 | tcg_gen_addi_i32(dest, dest, val); |
e6e5906b PB |
1632 | } |
1633 | } else { | |
351326a6 | 1634 | src2 = tcg_const_i32(val); |
e6e5906b | 1635 | if (insn & 0x0100) { |
f9083519 | 1636 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); |
e1f3808e | 1637 | tcg_gen_subi_i32(dest, dest, val); |
e6e5906b PB |
1638 | s->cc_op = CC_OP_SUB; |
1639 | } else { | |
e1f3808e | 1640 | tcg_gen_addi_i32(dest, dest, val); |
f9083519 | 1641 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); |
e6e5906b PB |
1642 | s->cc_op = CC_OP_ADD; |
1643 | } | |
e1f3808e | 1644 | gen_update_cc_add(dest, src2); |
e6e5906b | 1645 | } |
d4d79bb1 | 1646 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1647 | } |
1648 | ||
1649 | DISAS_INSN(tpf) | |
1650 | { | |
1651 | switch (insn & 7) { | |
1652 | case 2: /* One extension word. */ | |
1653 | s->pc += 2; | |
1654 | break; | |
1655 | case 3: /* Two extension words. */ | |
1656 | s->pc += 4; | |
1657 | break; | |
1658 | case 4: /* No extension words. */ | |
1659 | break; | |
1660 | default: | |
d4d79bb1 | 1661 | disas_undef(env, s, insn); |
e6e5906b PB |
1662 | } |
1663 | } | |
1664 | ||
1665 | DISAS_INSN(branch) | |
1666 | { | |
1667 | int32_t offset; | |
1668 | uint32_t base; | |
1669 | int op; | |
42a268c2 | 1670 | TCGLabel *l1; |
3b46e624 | 1671 | |
e6e5906b PB |
1672 | base = s->pc; |
1673 | op = (insn >> 8) & 0xf; | |
1674 | offset = (int8_t)insn; | |
1675 | if (offset == 0) { | |
28b68cd7 | 1676 | offset = (int16_t)read_im16(env, s); |
e6e5906b | 1677 | } else if (offset == -1) { |
d4d79bb1 | 1678 | offset = read_im32(env, s); |
e6e5906b PB |
1679 | } |
1680 | if (op == 1) { | |
1681 | /* bsr */ | |
351326a6 | 1682 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
1683 | } |
1684 | gen_flush_cc_op(s); | |
1685 | if (op > 1) { | |
1686 | /* Bcc */ | |
1687 | l1 = gen_new_label(); | |
1688 | gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); | |
1689 | gen_jmp_tb(s, 1, base + offset); | |
1690 | gen_set_label(l1); | |
1691 | gen_jmp_tb(s, 0, s->pc); | |
1692 | } else { | |
1693 | /* Unconditional branch. */ | |
1694 | gen_jmp_tb(s, 0, base + offset); | |
1695 | } | |
1696 | } | |
1697 | ||
1698 | DISAS_INSN(moveq) | |
1699 | { | |
e1f3808e | 1700 | uint32_t val; |
e6e5906b | 1701 | |
e1f3808e PB |
1702 | val = (int8_t)insn; |
1703 | tcg_gen_movi_i32(DREG(insn, 9), val); | |
5dbb6784 | 1704 | gen_logic_cc(s, tcg_const_i32(val), OS_LONG); |
e6e5906b PB |
1705 | } |
1706 | ||
1707 | DISAS_INSN(mvzs) | |
1708 | { | |
1709 | int opsize; | |
e1f3808e PB |
1710 | TCGv src; |
1711 | TCGv reg; | |
e6e5906b PB |
1712 | |
1713 | if (insn & 0x40) | |
1714 | opsize = OS_WORD; | |
1715 | else | |
1716 | opsize = OS_BYTE; | |
d4d79bb1 | 1717 | SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); |
e6e5906b | 1718 | reg = DREG(insn, 9); |
e1f3808e | 1719 | tcg_gen_mov_i32(reg, src); |
5dbb6784 | 1720 | gen_logic_cc(s, src, opsize); |
e6e5906b PB |
1721 | } |
1722 | ||
1723 | DISAS_INSN(or) | |
1724 | { | |
e1f3808e PB |
1725 | TCGv reg; |
1726 | TCGv dest; | |
1727 | TCGv src; | |
1728 | TCGv addr; | |
e6e5906b PB |
1729 | |
1730 | reg = DREG(insn, 9); | |
a7812ae4 | 1731 | dest = tcg_temp_new(); |
e6e5906b | 1732 | if (insn & 0x100) { |
d4d79bb1 | 1733 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1734 | tcg_gen_or_i32(dest, src, reg); |
d4d79bb1 | 1735 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1736 | } else { |
d4d79bb1 | 1737 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1738 | tcg_gen_or_i32(dest, src, reg); |
1739 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b | 1740 | } |
5dbb6784 | 1741 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1742 | } |
1743 | ||
1744 | DISAS_INSN(suba) | |
1745 | { | |
e1f3808e PB |
1746 | TCGv src; |
1747 | TCGv reg; | |
e6e5906b | 1748 | |
d4d79bb1 | 1749 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1750 | reg = AREG(insn, 9); |
e1f3808e | 1751 | tcg_gen_sub_i32(reg, reg, src); |
e6e5906b PB |
1752 | } |
1753 | ||
1754 | DISAS_INSN(subx) | |
1755 | { | |
e1f3808e PB |
1756 | TCGv reg; |
1757 | TCGv src; | |
e6e5906b PB |
1758 | |
1759 | gen_flush_flags(s); | |
1760 | reg = DREG(insn, 9); | |
1761 | src = DREG(insn, 0); | |
e1f3808e | 1762 | gen_helper_subx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1763 | } |
1764 | ||
1765 | DISAS_INSN(mov3q) | |
1766 | { | |
e1f3808e | 1767 | TCGv src; |
e6e5906b PB |
1768 | int val; |
1769 | ||
1770 | val = (insn >> 9) & 7; | |
1771 | if (val == 0) | |
1772 | val = -1; | |
351326a6 | 1773 | src = tcg_const_i32(val); |
5dbb6784 | 1774 | gen_logic_cc(s, src, OS_LONG); |
d4d79bb1 | 1775 | DEST_EA(env, insn, OS_LONG, src, NULL); |
e6e5906b PB |
1776 | } |
1777 | ||
1778 | DISAS_INSN(cmp) | |
1779 | { | |
e1f3808e PB |
1780 | TCGv src; |
1781 | TCGv reg; | |
1782 | TCGv dest; | |
e6e5906b PB |
1783 | int opsize; |
1784 | ||
5dbb6784 LV |
1785 | opsize = insn_opsize(insn); |
1786 | SRC_EA(env, src, opsize, -1, NULL); | |
e6e5906b | 1787 | reg = DREG(insn, 9); |
a7812ae4 | 1788 | dest = tcg_temp_new(); |
e1f3808e PB |
1789 | tcg_gen_sub_i32(dest, reg, src); |
1790 | gen_update_cc_add(dest, src); | |
5dbb6784 | 1791 | SET_CC_OP(opsize, SUB); |
e6e5906b PB |
1792 | } |
1793 | ||
1794 | DISAS_INSN(cmpa) | |
1795 | { | |
1796 | int opsize; | |
e1f3808e PB |
1797 | TCGv src; |
1798 | TCGv reg; | |
1799 | TCGv dest; | |
e6e5906b PB |
1800 | |
1801 | if (insn & 0x100) { | |
1802 | opsize = OS_LONG; | |
1803 | } else { | |
1804 | opsize = OS_WORD; | |
1805 | } | |
d4d79bb1 | 1806 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 1807 | reg = AREG(insn, 9); |
a7812ae4 | 1808 | dest = tcg_temp_new(); |
e1f3808e PB |
1809 | tcg_gen_sub_i32(dest, reg, src); |
1810 | gen_update_cc_add(dest, src); | |
5dbb6784 | 1811 | SET_CC_OP(OS_LONG, SUB); |
e6e5906b PB |
1812 | } |
1813 | ||
1814 | DISAS_INSN(eor) | |
1815 | { | |
e1f3808e PB |
1816 | TCGv src; |
1817 | TCGv reg; | |
1818 | TCGv dest; | |
1819 | TCGv addr; | |
e6e5906b | 1820 | |
d4d79bb1 | 1821 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e6e5906b | 1822 | reg = DREG(insn, 9); |
a7812ae4 | 1823 | dest = tcg_temp_new(); |
e1f3808e | 1824 | tcg_gen_xor_i32(dest, src, reg); |
5dbb6784 | 1825 | gen_logic_cc(s, dest, OS_LONG); |
d4d79bb1 | 1826 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b PB |
1827 | } |
1828 | ||
1829 | DISAS_INSN(and) | |
1830 | { | |
e1f3808e PB |
1831 | TCGv src; |
1832 | TCGv reg; | |
1833 | TCGv dest; | |
1834 | TCGv addr; | |
e6e5906b PB |
1835 | |
1836 | reg = DREG(insn, 9); | |
a7812ae4 | 1837 | dest = tcg_temp_new(); |
e6e5906b | 1838 | if (insn & 0x100) { |
d4d79bb1 | 1839 | SRC_EA(env, src, OS_LONG, 0, &addr); |
e1f3808e | 1840 | tcg_gen_and_i32(dest, src, reg); |
d4d79bb1 | 1841 | DEST_EA(env, insn, OS_LONG, dest, &addr); |
e6e5906b | 1842 | } else { |
d4d79bb1 | 1843 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e1f3808e PB |
1844 | tcg_gen_and_i32(dest, src, reg); |
1845 | tcg_gen_mov_i32(reg, dest); | |
e6e5906b | 1846 | } |
5dbb6784 | 1847 | gen_logic_cc(s, dest, OS_LONG); |
e6e5906b PB |
1848 | } |
1849 | ||
1850 | DISAS_INSN(adda) | |
1851 | { | |
e1f3808e PB |
1852 | TCGv src; |
1853 | TCGv reg; | |
e6e5906b | 1854 | |
d4d79bb1 | 1855 | SRC_EA(env, src, OS_LONG, 0, NULL); |
e6e5906b | 1856 | reg = AREG(insn, 9); |
e1f3808e | 1857 | tcg_gen_add_i32(reg, reg, src); |
e6e5906b PB |
1858 | } |
1859 | ||
1860 | DISAS_INSN(addx) | |
1861 | { | |
e1f3808e PB |
1862 | TCGv reg; |
1863 | TCGv src; | |
e6e5906b PB |
1864 | |
1865 | gen_flush_flags(s); | |
1866 | reg = DREG(insn, 9); | |
1867 | src = DREG(insn, 0); | |
e1f3808e | 1868 | gen_helper_addx_cc(reg, cpu_env, reg, src); |
e6e5906b PB |
1869 | s->cc_op = CC_OP_FLAGS; |
1870 | } | |
1871 | ||
e1f3808e | 1872 | /* TODO: This could be implemented without helper functions. */ |
e6e5906b PB |
1873 | DISAS_INSN(shift_im) |
1874 | { | |
e1f3808e | 1875 | TCGv reg; |
e6e5906b | 1876 | int tmp; |
e1f3808e | 1877 | TCGv shift; |
e6e5906b PB |
1878 | |
1879 | reg = DREG(insn, 0); | |
1880 | tmp = (insn >> 9) & 7; | |
1881 | if (tmp == 0) | |
e1f3808e | 1882 | tmp = 8; |
351326a6 | 1883 | shift = tcg_const_i32(tmp); |
e1f3808e | 1884 | /* No need to flush flags becuse we know we will set C flag. */ |
e6e5906b | 1885 | if (insn & 0x100) { |
e1f3808e | 1886 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1887 | } else { |
1888 | if (insn & 8) { | |
e1f3808e | 1889 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1890 | } else { |
e1f3808e | 1891 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1892 | } |
1893 | } | |
e1f3808e | 1894 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1895 | } |
1896 | ||
1897 | DISAS_INSN(shift_reg) | |
1898 | { | |
e1f3808e PB |
1899 | TCGv reg; |
1900 | TCGv shift; | |
e6e5906b PB |
1901 | |
1902 | reg = DREG(insn, 0); | |
e1f3808e PB |
1903 | shift = DREG(insn, 9); |
1904 | /* Shift by zero leaves C flag unmodified. */ | |
1905 | gen_flush_flags(s); | |
e6e5906b | 1906 | if (insn & 0x100) { |
e1f3808e | 1907 | gen_helper_shl_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1908 | } else { |
1909 | if (insn & 8) { | |
e1f3808e | 1910 | gen_helper_shr_cc(reg, cpu_env, reg, shift); |
e6e5906b | 1911 | } else { |
e1f3808e | 1912 | gen_helper_sar_cc(reg, cpu_env, reg, shift); |
e6e5906b PB |
1913 | } |
1914 | } | |
e1f3808e | 1915 | s->cc_op = CC_OP_SHIFT; |
e6e5906b PB |
1916 | } |
1917 | ||
1918 | DISAS_INSN(ff1) | |
1919 | { | |
e1f3808e | 1920 | TCGv reg; |
821f7e76 | 1921 | reg = DREG(insn, 0); |
5dbb6784 | 1922 | gen_logic_cc(s, reg, OS_LONG); |
e1f3808e | 1923 | gen_helper_ff1(reg, reg); |
e6e5906b PB |
1924 | } |
1925 | ||
e1f3808e | 1926 | static TCGv gen_get_sr(DisasContext *s) |
0633879f | 1927 | { |
e1f3808e PB |
1928 | TCGv ccr; |
1929 | TCGv sr; | |
0633879f PB |
1930 | |
1931 | ccr = gen_get_ccr(s); | |
a7812ae4 | 1932 | sr = tcg_temp_new(); |
e1f3808e PB |
1933 | tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); |
1934 | tcg_gen_or_i32(sr, sr, ccr); | |
0633879f PB |
1935 | return sr; |
1936 | } | |
1937 | ||
e6e5906b PB |
1938 | DISAS_INSN(strldsr) |
1939 | { | |
1940 | uint16_t ext; | |
1941 | uint32_t addr; | |
1942 | ||
1943 | addr = s->pc - 2; | |
28b68cd7 | 1944 | ext = read_im16(env, s); |
0633879f | 1945 | if (ext != 0x46FC) { |
e6e5906b | 1946 | gen_exception(s, addr, EXCP_UNSUPPORTED); |
0633879f PB |
1947 | return; |
1948 | } | |
28b68cd7 | 1949 | ext = read_im16(env, s); |
0633879f | 1950 | if (IS_USER(s) || (ext & SR_S) == 0) { |
e6e5906b | 1951 | gen_exception(s, addr, EXCP_PRIVILEGE); |
0633879f PB |
1952 | return; |
1953 | } | |
1954 | gen_push(s, gen_get_sr(s)); | |
1955 | gen_set_sr_im(s, ext, 0); | |
e6e5906b PB |
1956 | } |
1957 | ||
1958 | DISAS_INSN(move_from_sr) | |
1959 | { | |
e1f3808e PB |
1960 | TCGv reg; |
1961 | TCGv sr; | |
0633879f PB |
1962 | |
1963 | if (IS_USER(s)) { | |
1964 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1965 | return; | |
1966 | } | |
1967 | sr = gen_get_sr(s); | |
1968 | reg = DREG(insn, 0); | |
1969 | gen_partset_reg(OS_WORD, reg, sr); | |
e6e5906b PB |
1970 | } |
1971 | ||
1972 | DISAS_INSN(move_to_sr) | |
1973 | { | |
0633879f PB |
1974 | if (IS_USER(s)) { |
1975 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1976 | return; | |
1977 | } | |
d4d79bb1 | 1978 | gen_set_sr(env, s, insn, 0); |
0633879f | 1979 | gen_lookup_tb(s); |
e6e5906b PB |
1980 | } |
1981 | ||
1982 | DISAS_INSN(move_from_usp) | |
1983 | { | |
0633879f PB |
1984 | if (IS_USER(s)) { |
1985 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1986 | return; | |
1987 | } | |
2a8327e8 GU |
1988 | tcg_gen_ld_i32(AREG(insn, 0), cpu_env, |
1989 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
1990 | } |
1991 | ||
1992 | DISAS_INSN(move_to_usp) | |
1993 | { | |
0633879f PB |
1994 | if (IS_USER(s)) { |
1995 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
1996 | return; | |
1997 | } | |
2a8327e8 GU |
1998 | tcg_gen_st_i32(AREG(insn, 0), cpu_env, |
1999 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
2000 | } |
2001 | ||
2002 | DISAS_INSN(halt) | |
2003 | { | |
e1f3808e | 2004 | gen_exception(s, s->pc, EXCP_HALT_INSN); |
e6e5906b PB |
2005 | } |
2006 | ||
2007 | DISAS_INSN(stop) | |
2008 | { | |
0633879f PB |
2009 | uint16_t ext; |
2010 | ||
2011 | if (IS_USER(s)) { | |
2012 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2013 | return; | |
2014 | } | |
2015 | ||
28b68cd7 | 2016 | ext = read_im16(env, s); |
0633879f PB |
2017 | |
2018 | gen_set_sr_im(s, ext, 0); | |
259186a7 | 2019 | tcg_gen_movi_i32(cpu_halted, 1); |
e1f3808e | 2020 | gen_exception(s, s->pc, EXCP_HLT); |
e6e5906b PB |
2021 | } |
2022 | ||
2023 | DISAS_INSN(rte) | |
2024 | { | |
0633879f PB |
2025 | if (IS_USER(s)) { |
2026 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2027 | return; | |
2028 | } | |
2029 | gen_exception(s, s->pc - 2, EXCP_RTE); | |
e6e5906b PB |
2030 | } |
2031 | ||
2032 | DISAS_INSN(movec) | |
2033 | { | |
0633879f | 2034 | uint16_t ext; |
e1f3808e | 2035 | TCGv reg; |
0633879f PB |
2036 | |
2037 | if (IS_USER(s)) { | |
2038 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2039 | return; | |
2040 | } | |
2041 | ||
28b68cd7 | 2042 | ext = read_im16(env, s); |
0633879f PB |
2043 | |
2044 | if (ext & 0x8000) { | |
2045 | reg = AREG(ext, 12); | |
2046 | } else { | |
2047 | reg = DREG(ext, 12); | |
2048 | } | |
e1f3808e | 2049 | gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); |
0633879f | 2050 | gen_lookup_tb(s); |
e6e5906b PB |
2051 | } |
2052 | ||
2053 | DISAS_INSN(intouch) | |
2054 | { | |
0633879f PB |
2055 | if (IS_USER(s)) { |
2056 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2057 | return; | |
2058 | } | |
2059 | /* ICache fetch. Implement as no-op. */ | |
e6e5906b PB |
2060 | } |
2061 | ||
2062 | DISAS_INSN(cpushl) | |
2063 | { | |
0633879f PB |
2064 | if (IS_USER(s)) { |
2065 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2066 | return; | |
2067 | } | |
2068 | /* Cache push/invalidate. Implement as no-op. */ | |
e6e5906b PB |
2069 | } |
2070 | ||
2071 | DISAS_INSN(wddata) | |
2072 | { | |
2073 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2074 | } | |
2075 | ||
2076 | DISAS_INSN(wdebug) | |
2077 | { | |
a47dddd7 AF |
2078 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2079 | ||
0633879f PB |
2080 | if (IS_USER(s)) { |
2081 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2082 | return; | |
2083 | } | |
2084 | /* TODO: Implement wdebug. */ | |
a47dddd7 | 2085 | cpu_abort(CPU(cpu), "WDEBUG not implemented"); |
e6e5906b PB |
2086 | } |
2087 | ||
2088 | DISAS_INSN(trap) | |
2089 | { | |
2090 | gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); | |
2091 | } | |
2092 | ||
2093 | /* ??? FP exceptions are not implemented. Most exceptions are deferred until | |
2094 | immediately before the next FP instruction is executed. */ | |
2095 | DISAS_INSN(fpu) | |
2096 | { | |
2097 | uint16_t ext; | |
a7812ae4 | 2098 | int32_t offset; |
e6e5906b | 2099 | int opmode; |
a7812ae4 PB |
2100 | TCGv_i64 src; |
2101 | TCGv_i64 dest; | |
2102 | TCGv_i64 res; | |
2103 | TCGv tmp32; | |
e6e5906b | 2104 | int round; |
a7812ae4 | 2105 | int set_dest; |
e6e5906b PB |
2106 | int opsize; |
2107 | ||
28b68cd7 | 2108 | ext = read_im16(env, s); |
e6e5906b PB |
2109 | opmode = ext & 0x7f; |
2110 | switch ((ext >> 13) & 7) { | |
2111 | case 0: case 2: | |
2112 | break; | |
2113 | case 1: | |
2114 | goto undef; | |
2115 | case 3: /* fmove out */ | |
2116 | src = FREG(ext, 7); | |
a7812ae4 | 2117 | tmp32 = tcg_temp_new_i32(); |
e6e5906b PB |
2118 | /* fmove */ |
2119 | /* ??? TODO: Proper behavior on overflow. */ | |
2120 | switch ((ext >> 10) & 7) { | |
2121 | case 0: | |
2122 | opsize = OS_LONG; | |
a7812ae4 | 2123 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2124 | break; |
2125 | case 1: | |
2126 | opsize = OS_SINGLE; | |
a7812ae4 | 2127 | gen_helper_f64_to_f32(tmp32, cpu_env, src); |
e6e5906b PB |
2128 | break; |
2129 | case 4: | |
2130 | opsize = OS_WORD; | |
a7812ae4 | 2131 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b | 2132 | break; |
a7812ae4 PB |
2133 | case 5: /* OS_DOUBLE */ |
2134 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2135 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2136 | case 2: |
2137 | case 3: | |
243ee8f7 | 2138 | break; |
a7812ae4 PB |
2139 | case 4: |
2140 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2141 | break; | |
2142 | case 5: | |
d4d79bb1 | 2143 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2144 | s->pc += 2; |
2145 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2146 | break; | |
2147 | default: | |
2148 | goto undef; | |
2149 | } | |
2150 | gen_store64(s, tmp32, src); | |
c59b97aa | 2151 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2152 | case 3: |
2153 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2154 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2155 | break; | |
2156 | case 4: | |
2157 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2158 | break; | |
2159 | } | |
2160 | tcg_temp_free_i32(tmp32); | |
2161 | return; | |
e6e5906b PB |
2162 | case 6: |
2163 | opsize = OS_BYTE; | |
a7812ae4 | 2164 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
2165 | break; |
2166 | default: | |
2167 | goto undef; | |
2168 | } | |
d4d79bb1 | 2169 | DEST_EA(env, insn, opsize, tmp32, NULL); |
a7812ae4 | 2170 | tcg_temp_free_i32(tmp32); |
e6e5906b PB |
2171 | return; |
2172 | case 4: /* fmove to control register. */ | |
2173 | switch ((ext >> 10) & 7) { | |
2174 | case 4: /* FPCR */ | |
2175 | /* Not implemented. Ignore writes. */ | |
2176 | break; | |
2177 | case 1: /* FPIAR */ | |
2178 | case 2: /* FPSR */ | |
2179 | default: | |
2180 | cpu_abort(NULL, "Unimplemented: fmove to control %d", | |
2181 | (ext >> 10) & 7); | |
2182 | } | |
2183 | break; | |
2184 | case 5: /* fmove from control register. */ | |
2185 | switch ((ext >> 10) & 7) { | |
2186 | case 4: /* FPCR */ | |
2187 | /* Not implemented. Always return zero. */ | |
351326a6 | 2188 | tmp32 = tcg_const_i32(0); |
e6e5906b PB |
2189 | break; |
2190 | case 1: /* FPIAR */ | |
2191 | case 2: /* FPSR */ | |
2192 | default: | |
2193 | cpu_abort(NULL, "Unimplemented: fmove from control %d", | |
2194 | (ext >> 10) & 7); | |
2195 | goto undef; | |
2196 | } | |
d4d79bb1 | 2197 | DEST_EA(env, insn, OS_LONG, tmp32, NULL); |
e6e5906b | 2198 | break; |
5fafdf24 | 2199 | case 6: /* fmovem */ |
e6e5906b PB |
2200 | case 7: |
2201 | { | |
e1f3808e PB |
2202 | TCGv addr; |
2203 | uint16_t mask; | |
2204 | int i; | |
2205 | if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) | |
2206 | goto undef; | |
d4d79bb1 | 2207 | tmp32 = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2208 | if (IS_NULL_QREG(tmp32)) { |
e1f3808e PB |
2209 | gen_addr_fault(s); |
2210 | return; | |
2211 | } | |
a7812ae4 PB |
2212 | addr = tcg_temp_new_i32(); |
2213 | tcg_gen_mov_i32(addr, tmp32); | |
e1f3808e PB |
2214 | mask = 0x80; |
2215 | for (i = 0; i < 8; i++) { | |
2216 | if (ext & mask) { | |
e1f3808e PB |
2217 | dest = FREG(i, 0); |
2218 | if (ext & (1 << 13)) { | |
2219 | /* store */ | |
2220 | tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); | |
2221 | } else { | |
2222 | /* load */ | |
2223 | tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); | |
2224 | } | |
2225 | if (ext & (mask - 1)) | |
2226 | tcg_gen_addi_i32(addr, addr, 8); | |
e6e5906b | 2227 | } |
e1f3808e | 2228 | mask >>= 1; |
e6e5906b | 2229 | } |
18307f26 | 2230 | tcg_temp_free_i32(addr); |
e6e5906b PB |
2231 | } |
2232 | return; | |
2233 | } | |
2234 | if (ext & (1 << 14)) { | |
e6e5906b PB |
2235 | /* Source effective address. */ |
2236 | switch ((ext >> 10) & 7) { | |
2237 | case 0: opsize = OS_LONG; break; | |
2238 | case 1: opsize = OS_SINGLE; break; | |
2239 | case 4: opsize = OS_WORD; break; | |
2240 | case 5: opsize = OS_DOUBLE; break; | |
2241 | case 6: opsize = OS_BYTE; break; | |
2242 | default: | |
2243 | goto undef; | |
2244 | } | |
e6e5906b | 2245 | if (opsize == OS_DOUBLE) { |
a7812ae4 PB |
2246 | tmp32 = tcg_temp_new_i32(); |
2247 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 2248 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2249 | case 2: |
2250 | case 3: | |
243ee8f7 | 2251 | break; |
a7812ae4 PB |
2252 | case 4: |
2253 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2254 | break; | |
2255 | case 5: | |
d4d79bb1 | 2256 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2257 | s->pc += 2; |
2258 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2259 | break; | |
2260 | case 7: | |
d4d79bb1 | 2261 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
2262 | offset += s->pc - 2; |
2263 | s->pc += 2; | |
2264 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2265 | break; | |
2266 | default: | |
2267 | goto undef; | |
2268 | } | |
2269 | src = gen_load64(s, tmp32); | |
c59b97aa | 2270 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
2271 | case 3: |
2272 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2273 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2274 | break; | |
2275 | case 4: | |
2276 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2277 | break; | |
2278 | } | |
2279 | tcg_temp_free_i32(tmp32); | |
e6e5906b | 2280 | } else { |
d4d79bb1 | 2281 | SRC_EA(env, tmp32, opsize, 1, NULL); |
a7812ae4 | 2282 | src = tcg_temp_new_i64(); |
e6e5906b PB |
2283 | switch (opsize) { |
2284 | case OS_LONG: | |
2285 | case OS_WORD: | |
2286 | case OS_BYTE: | |
a7812ae4 | 2287 | gen_helper_i32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2288 | break; |
2289 | case OS_SINGLE: | |
a7812ae4 | 2290 | gen_helper_f32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
2291 | break; |
2292 | } | |
2293 | } | |
2294 | } else { | |
2295 | /* Source register. */ | |
2296 | src = FREG(ext, 10); | |
2297 | } | |
2298 | dest = FREG(ext, 7); | |
a7812ae4 | 2299 | res = tcg_temp_new_i64(); |
e6e5906b | 2300 | if (opmode != 0x3a) |
e1f3808e | 2301 | tcg_gen_mov_f64(res, dest); |
e6e5906b | 2302 | round = 1; |
a7812ae4 | 2303 | set_dest = 1; |
e6e5906b PB |
2304 | switch (opmode) { |
2305 | case 0: case 0x40: case 0x44: /* fmove */ | |
e1f3808e | 2306 | tcg_gen_mov_f64(res, src); |
e6e5906b PB |
2307 | break; |
2308 | case 1: /* fint */ | |
e1f3808e | 2309 | gen_helper_iround_f64(res, cpu_env, src); |
e6e5906b PB |
2310 | round = 0; |
2311 | break; | |
2312 | case 3: /* fintrz */ | |
e1f3808e | 2313 | gen_helper_itrunc_f64(res, cpu_env, src); |
e6e5906b PB |
2314 | round = 0; |
2315 | break; | |
2316 | case 4: case 0x41: case 0x45: /* fsqrt */ | |
e1f3808e | 2317 | gen_helper_sqrt_f64(res, cpu_env, src); |
e6e5906b PB |
2318 | break; |
2319 | case 0x18: case 0x58: case 0x5c: /* fabs */ | |
e1f3808e | 2320 | gen_helper_abs_f64(res, src); |
e6e5906b PB |
2321 | break; |
2322 | case 0x1a: case 0x5a: case 0x5e: /* fneg */ | |
e1f3808e | 2323 | gen_helper_chs_f64(res, src); |
e6e5906b PB |
2324 | break; |
2325 | case 0x20: case 0x60: case 0x64: /* fdiv */ | |
e1f3808e | 2326 | gen_helper_div_f64(res, cpu_env, res, src); |
e6e5906b PB |
2327 | break; |
2328 | case 0x22: case 0x62: case 0x66: /* fadd */ | |
e1f3808e | 2329 | gen_helper_add_f64(res, cpu_env, res, src); |
e6e5906b PB |
2330 | break; |
2331 | case 0x23: case 0x63: case 0x67: /* fmul */ | |
e1f3808e | 2332 | gen_helper_mul_f64(res, cpu_env, res, src); |
e6e5906b PB |
2333 | break; |
2334 | case 0x28: case 0x68: case 0x6c: /* fsub */ | |
e1f3808e | 2335 | gen_helper_sub_f64(res, cpu_env, res, src); |
e6e5906b PB |
2336 | break; |
2337 | case 0x38: /* fcmp */ | |
e1f3808e | 2338 | gen_helper_sub_cmp_f64(res, cpu_env, res, src); |
a7812ae4 | 2339 | set_dest = 0; |
e6e5906b PB |
2340 | round = 0; |
2341 | break; | |
2342 | case 0x3a: /* ftst */ | |
e1f3808e | 2343 | tcg_gen_mov_f64(res, src); |
a7812ae4 | 2344 | set_dest = 0; |
e6e5906b PB |
2345 | round = 0; |
2346 | break; | |
2347 | default: | |
2348 | goto undef; | |
2349 | } | |
a7812ae4 PB |
2350 | if (ext & (1 << 14)) { |
2351 | tcg_temp_free_i64(src); | |
2352 | } | |
e6e5906b PB |
2353 | if (round) { |
2354 | if (opmode & 0x40) { | |
2355 | if ((opmode & 0x4) != 0) | |
2356 | round = 0; | |
2357 | } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { | |
2358 | round = 0; | |
2359 | } | |
2360 | } | |
2361 | if (round) { | |
a7812ae4 | 2362 | TCGv tmp = tcg_temp_new_i32(); |
e1f3808e PB |
2363 | gen_helper_f64_to_f32(tmp, cpu_env, res); |
2364 | gen_helper_f32_to_f64(res, cpu_env, tmp); | |
a7812ae4 | 2365 | tcg_temp_free_i32(tmp); |
5fafdf24 | 2366 | } |
e1f3808e | 2367 | tcg_gen_mov_f64(QREG_FP_RESULT, res); |
a7812ae4 | 2368 | if (set_dest) { |
e1f3808e | 2369 | tcg_gen_mov_f64(dest, res); |
e6e5906b | 2370 | } |
a7812ae4 | 2371 | tcg_temp_free_i64(res); |
e6e5906b PB |
2372 | return; |
2373 | undef: | |
a7812ae4 | 2374 | /* FIXME: Is this right for offset addressing modes? */ |
e6e5906b | 2375 | s->pc -= 2; |
d4d79bb1 | 2376 | disas_undef_fpu(env, s, insn); |
e6e5906b PB |
2377 | } |
2378 | ||
2379 | DISAS_INSN(fbcc) | |
2380 | { | |
2381 | uint32_t offset; | |
2382 | uint32_t addr; | |
e1f3808e | 2383 | TCGv flag; |
42a268c2 | 2384 | TCGLabel *l1; |
e6e5906b PB |
2385 | |
2386 | addr = s->pc; | |
d4d79bb1 | 2387 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
2388 | s->pc += 2; |
2389 | if (insn & (1 << 6)) { | |
28b68cd7 | 2390 | offset = (offset << 16) | read_im16(env, s); |
e6e5906b PB |
2391 | } |
2392 | ||
2393 | l1 = gen_new_label(); | |
2394 | /* TODO: Raise BSUN exception. */ | |
a7812ae4 | 2395 | flag = tcg_temp_new(); |
e1f3808e | 2396 | gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); |
e6e5906b PB |
2397 | /* Jump to l1 if condition is true. */ |
2398 | switch (insn & 0xf) { | |
2399 | case 0: /* f */ | |
2400 | break; | |
2401 | case 1: /* eq (=0) */ | |
e1f3808e | 2402 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2403 | break; |
2404 | case 2: /* ogt (=1) */ | |
e1f3808e | 2405 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2406 | break; |
2407 | case 3: /* oge (=0 or =1) */ | |
e1f3808e | 2408 | tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2409 | break; |
2410 | case 4: /* olt (=-1) */ | |
e1f3808e | 2411 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2412 | break; |
2413 | case 5: /* ole (=-1 or =0) */ | |
e1f3808e | 2414 | tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2415 | break; |
2416 | case 6: /* ogl (=-1 or =1) */ | |
e1f3808e PB |
2417 | tcg_gen_andi_i32(flag, flag, 1); |
2418 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2419 | break; |
2420 | case 7: /* or (=2) */ | |
e1f3808e | 2421 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2422 | break; |
2423 | case 8: /* un (<2) */ | |
e1f3808e | 2424 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2425 | break; |
2426 | case 9: /* ueq (=0 or =2) */ | |
e1f3808e PB |
2427 | tcg_gen_andi_i32(flag, flag, 1); |
2428 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
2429 | break; |
2430 | case 10: /* ugt (>0) */ | |
e1f3808e | 2431 | tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2432 | break; |
2433 | case 11: /* uge (>=0) */ | |
e1f3808e | 2434 | tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2435 | break; |
2436 | case 12: /* ult (=-1 or =2) */ | |
e1f3808e | 2437 | tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
2438 | break; |
2439 | case 13: /* ule (!=1) */ | |
e1f3808e | 2440 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
2441 | break; |
2442 | case 14: /* ne (!=0) */ | |
e1f3808e | 2443 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
2444 | break; |
2445 | case 15: /* t */ | |
e1f3808e | 2446 | tcg_gen_br(l1); |
e6e5906b PB |
2447 | break; |
2448 | } | |
2449 | gen_jmp_tb(s, 0, s->pc); | |
2450 | gen_set_label(l1); | |
2451 | gen_jmp_tb(s, 1, addr + offset); | |
2452 | } | |
2453 | ||
0633879f PB |
2454 | DISAS_INSN(frestore) |
2455 | { | |
a47dddd7 AF |
2456 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2457 | ||
0633879f | 2458 | /* TODO: Implement frestore. */ |
a47dddd7 | 2459 | cpu_abort(CPU(cpu), "FRESTORE not implemented"); |
0633879f PB |
2460 | } |
2461 | ||
2462 | DISAS_INSN(fsave) | |
2463 | { | |
a47dddd7 AF |
2464 | M68kCPU *cpu = m68k_env_get_cpu(env); |
2465 | ||
0633879f | 2466 | /* TODO: Implement fsave. */ |
a47dddd7 | 2467 | cpu_abort(CPU(cpu), "FSAVE not implemented"); |
0633879f PB |
2468 | } |
2469 | ||
e1f3808e | 2470 | static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) |
acf930aa | 2471 | { |
a7812ae4 | 2472 | TCGv tmp = tcg_temp_new(); |
acf930aa PB |
2473 | if (s->env->macsr & MACSR_FI) { |
2474 | if (upper) | |
e1f3808e | 2475 | tcg_gen_andi_i32(tmp, val, 0xffff0000); |
acf930aa | 2476 | else |
e1f3808e | 2477 | tcg_gen_shli_i32(tmp, val, 16); |
acf930aa PB |
2478 | } else if (s->env->macsr & MACSR_SU) { |
2479 | if (upper) | |
e1f3808e | 2480 | tcg_gen_sari_i32(tmp, val, 16); |
acf930aa | 2481 | else |
e1f3808e | 2482 | tcg_gen_ext16s_i32(tmp, val); |
acf930aa PB |
2483 | } else { |
2484 | if (upper) | |
e1f3808e | 2485 | tcg_gen_shri_i32(tmp, val, 16); |
acf930aa | 2486 | else |
e1f3808e | 2487 | tcg_gen_ext16u_i32(tmp, val); |
acf930aa PB |
2488 | } |
2489 | return tmp; | |
2490 | } | |
2491 | ||
e1f3808e PB |
2492 | static void gen_mac_clear_flags(void) |
2493 | { | |
2494 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, | |
2495 | ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); | |
2496 | } | |
2497 | ||
acf930aa PB |
2498 | DISAS_INSN(mac) |
2499 | { | |
e1f3808e PB |
2500 | TCGv rx; |
2501 | TCGv ry; | |
acf930aa PB |
2502 | uint16_t ext; |
2503 | int acc; | |
e1f3808e PB |
2504 | TCGv tmp; |
2505 | TCGv addr; | |
2506 | TCGv loadval; | |
acf930aa | 2507 | int dual; |
e1f3808e PB |
2508 | TCGv saved_flags; |
2509 | ||
a7812ae4 PB |
2510 | if (!s->done_mac) { |
2511 | s->mactmp = tcg_temp_new_i64(); | |
2512 | s->done_mac = 1; | |
2513 | } | |
acf930aa | 2514 | |
28b68cd7 | 2515 | ext = read_im16(env, s); |
acf930aa PB |
2516 | |
2517 | acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); | |
2518 | dual = ((insn & 0x30) != 0 && (ext & 3) != 0); | |
d315c888 | 2519 | if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { |
d4d79bb1 | 2520 | disas_undef(env, s, insn); |
d315c888 PB |
2521 | return; |
2522 | } | |
acf930aa PB |
2523 | if (insn & 0x30) { |
2524 | /* MAC with load. */ | |
d4d79bb1 | 2525 | tmp = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 2526 | addr = tcg_temp_new(); |
e1f3808e | 2527 | tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); |
acf930aa PB |
2528 | /* Load the value now to ensure correct exception behavior. |
2529 | Perform writeback after reading the MAC inputs. */ | |
2530 | loadval = gen_load(s, OS_LONG, addr, 0); | |
2531 | ||
2532 | acc ^= 1; | |
2533 | rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); | |
2534 | ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); | |
2535 | } else { | |
e1f3808e | 2536 | loadval = addr = NULL_QREG; |
acf930aa PB |
2537 | rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
2538 | ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
2539 | } | |
2540 | ||
e1f3808e PB |
2541 | gen_mac_clear_flags(); |
2542 | #if 0 | |
acf930aa | 2543 | l1 = -1; |
e1f3808e | 2544 | /* Disabled because conditional branches clobber temporary vars. */ |
acf930aa PB |
2545 | if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { |
2546 | /* Skip the multiply if we know we will ignore it. */ | |
2547 | l1 = gen_new_label(); | |
a7812ae4 | 2548 | tmp = tcg_temp_new(); |
e1f3808e | 2549 | tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); |
acf930aa PB |
2550 | gen_op_jmp_nz32(tmp, l1); |
2551 | } | |
e1f3808e | 2552 | #endif |
acf930aa PB |
2553 | |
2554 | if ((ext & 0x0800) == 0) { | |
2555 | /* Word. */ | |
2556 | rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); | |
2557 | ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); | |
2558 | } | |
2559 | if (s->env->macsr & MACSR_FI) { | |
e1f3808e | 2560 | gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2561 | } else { |
2562 | if (s->env->macsr & MACSR_SU) | |
e1f3808e | 2563 | gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); |
acf930aa | 2564 | else |
e1f3808e | 2565 | gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
2566 | switch ((ext >> 9) & 3) { |
2567 | case 1: | |
e1f3808e | 2568 | tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2569 | break; |
2570 | case 3: | |
e1f3808e | 2571 | tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
2572 | break; |
2573 | } | |
2574 | } | |
2575 | ||
2576 | if (dual) { | |
2577 | /* Save the overflow flag from the multiply. */ | |
a7812ae4 | 2578 | saved_flags = tcg_temp_new(); |
e1f3808e PB |
2579 | tcg_gen_mov_i32(saved_flags, QREG_MACSR); |
2580 | } else { | |
2581 | saved_flags = NULL_QREG; | |
acf930aa PB |
2582 | } |
2583 | ||
e1f3808e PB |
2584 | #if 0 |
2585 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2586 | if ((s->env->macsr & MACSR_OMC) != 0 && dual) { |
2587 | /* Skip the accumulate if the value is already saturated. */ | |
2588 | l1 = gen_new_label(); | |
a7812ae4 | 2589 | tmp = tcg_temp_new(); |
351326a6 | 2590 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2591 | gen_op_jmp_nz32(tmp, l1); |
2592 | } | |
e1f3808e | 2593 | #endif |
acf930aa PB |
2594 | |
2595 | if (insn & 0x100) | |
e1f3808e | 2596 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2597 | else |
e1f3808e | 2598 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa PB |
2599 | |
2600 | if (s->env->macsr & MACSR_FI) | |
e1f3808e | 2601 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2602 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2603 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2604 | else |
e1f3808e | 2605 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2606 | |
e1f3808e PB |
2607 | #if 0 |
2608 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2609 | if (l1 != -1) |
2610 | gen_set_label(l1); | |
e1f3808e | 2611 | #endif |
acf930aa PB |
2612 | |
2613 | if (dual) { | |
2614 | /* Dual accumulate variant. */ | |
2615 | acc = (ext >> 2) & 3; | |
2616 | /* Restore the overflow flag from the multiplier. */ | |
e1f3808e PB |
2617 | tcg_gen_mov_i32(QREG_MACSR, saved_flags); |
2618 | #if 0 | |
2619 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2620 | if ((s->env->macsr & MACSR_OMC) != 0) { |
2621 | /* Skip the accumulate if the value is already saturated. */ | |
2622 | l1 = gen_new_label(); | |
a7812ae4 | 2623 | tmp = tcg_temp_new(); |
351326a6 | 2624 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
2625 | gen_op_jmp_nz32(tmp, l1); |
2626 | } | |
e1f3808e | 2627 | #endif |
acf930aa | 2628 | if (ext & 2) |
e1f3808e | 2629 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2630 | else |
e1f3808e | 2631 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 2632 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2633 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2634 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2635 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 2636 | else |
e1f3808e PB |
2637 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
2638 | #if 0 | |
2639 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
2640 | if (l1 != -1) |
2641 | gen_set_label(l1); | |
e1f3808e | 2642 | #endif |
acf930aa | 2643 | } |
e1f3808e | 2644 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); |
acf930aa PB |
2645 | |
2646 | if (insn & 0x30) { | |
e1f3808e | 2647 | TCGv rw; |
acf930aa | 2648 | rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
e1f3808e | 2649 | tcg_gen_mov_i32(rw, loadval); |
acf930aa PB |
2650 | /* FIXME: Should address writeback happen with the masked or |
2651 | unmasked value? */ | |
2652 | switch ((insn >> 3) & 7) { | |
2653 | case 3: /* Post-increment. */ | |
e1f3808e | 2654 | tcg_gen_addi_i32(AREG(insn, 0), addr, 4); |
acf930aa PB |
2655 | break; |
2656 | case 4: /* Pre-decrement. */ | |
e1f3808e | 2657 | tcg_gen_mov_i32(AREG(insn, 0), addr); |
acf930aa PB |
2658 | } |
2659 | } | |
2660 | } | |
2661 | ||
2662 | DISAS_INSN(from_mac) | |
2663 | { | |
e1f3808e | 2664 | TCGv rx; |
a7812ae4 | 2665 | TCGv_i64 acc; |
e1f3808e | 2666 | int accnum; |
acf930aa PB |
2667 | |
2668 | rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e PB |
2669 | accnum = (insn >> 9) & 3; |
2670 | acc = MACREG(accnum); | |
acf930aa | 2671 | if (s->env->macsr & MACSR_FI) { |
a7812ae4 | 2672 | gen_helper_get_macf(rx, cpu_env, acc); |
acf930aa | 2673 | } else if ((s->env->macsr & MACSR_OMC) == 0) { |
ecc7b3aa | 2674 | tcg_gen_extrl_i64_i32(rx, acc); |
acf930aa | 2675 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2676 | gen_helper_get_macs(rx, acc); |
acf930aa | 2677 | } else { |
e1f3808e PB |
2678 | gen_helper_get_macu(rx, acc); |
2679 | } | |
2680 | if (insn & 0x40) { | |
2681 | tcg_gen_movi_i64(acc, 0); | |
2682 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
acf930aa | 2683 | } |
acf930aa PB |
2684 | } |
2685 | ||
2686 | DISAS_INSN(move_mac) | |
2687 | { | |
e1f3808e | 2688 | /* FIXME: This can be done without a helper. */ |
acf930aa | 2689 | int src; |
e1f3808e | 2690 | TCGv dest; |
acf930aa | 2691 | src = insn & 3; |
e1f3808e PB |
2692 | dest = tcg_const_i32((insn >> 9) & 3); |
2693 | gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); | |
2694 | gen_mac_clear_flags(); | |
2695 | gen_helper_mac_set_flags(cpu_env, dest); | |
acf930aa PB |
2696 | } |
2697 | ||
2698 | DISAS_INSN(from_macsr) | |
2699 | { | |
e1f3808e | 2700 | TCGv reg; |
acf930aa PB |
2701 | |
2702 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e | 2703 | tcg_gen_mov_i32(reg, QREG_MACSR); |
acf930aa PB |
2704 | } |
2705 | ||
2706 | DISAS_INSN(from_mask) | |
2707 | { | |
e1f3808e | 2708 | TCGv reg; |
acf930aa | 2709 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2710 | tcg_gen_mov_i32(reg, QREG_MAC_MASK); |
acf930aa PB |
2711 | } |
2712 | ||
2713 | DISAS_INSN(from_mext) | |
2714 | { | |
e1f3808e PB |
2715 | TCGv reg; |
2716 | TCGv acc; | |
acf930aa | 2717 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 2718 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2719 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2720 | gen_helper_get_mac_extf(reg, cpu_env, acc); |
acf930aa | 2721 | else |
e1f3808e | 2722 | gen_helper_get_mac_exti(reg, cpu_env, acc); |
acf930aa PB |
2723 | } |
2724 | ||
2725 | DISAS_INSN(macsr_to_ccr) | |
2726 | { | |
e1f3808e PB |
2727 | tcg_gen_movi_i32(QREG_CC_X, 0); |
2728 | tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf); | |
acf930aa PB |
2729 | s->cc_op = CC_OP_FLAGS; |
2730 | } | |
2731 | ||
2732 | DISAS_INSN(to_mac) | |
2733 | { | |
a7812ae4 | 2734 | TCGv_i64 acc; |
e1f3808e PB |
2735 | TCGv val; |
2736 | int accnum; | |
2737 | accnum = (insn >> 9) & 3; | |
2738 | acc = MACREG(accnum); | |
d4d79bb1 | 2739 | SRC_EA(env, val, OS_LONG, 0, NULL); |
acf930aa | 2740 | if (s->env->macsr & MACSR_FI) { |
e1f3808e PB |
2741 | tcg_gen_ext_i32_i64(acc, val); |
2742 | tcg_gen_shli_i64(acc, acc, 8); | |
acf930aa | 2743 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 2744 | tcg_gen_ext_i32_i64(acc, val); |
acf930aa | 2745 | } else { |
e1f3808e | 2746 | tcg_gen_extu_i32_i64(acc, val); |
acf930aa | 2747 | } |
e1f3808e PB |
2748 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); |
2749 | gen_mac_clear_flags(); | |
2750 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); | |
acf930aa PB |
2751 | } |
2752 | ||
2753 | DISAS_INSN(to_macsr) | |
2754 | { | |
e1f3808e | 2755 | TCGv val; |
d4d79bb1 | 2756 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2757 | gen_helper_set_macsr(cpu_env, val); |
acf930aa PB |
2758 | gen_lookup_tb(s); |
2759 | } | |
2760 | ||
2761 | DISAS_INSN(to_mask) | |
2762 | { | |
e1f3808e | 2763 | TCGv val; |
d4d79bb1 | 2764 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2765 | tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); |
acf930aa PB |
2766 | } |
2767 | ||
2768 | DISAS_INSN(to_mext) | |
2769 | { | |
e1f3808e PB |
2770 | TCGv val; |
2771 | TCGv acc; | |
d4d79bb1 | 2772 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 2773 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 2774 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 2775 | gen_helper_set_mac_extf(cpu_env, val, acc); |
acf930aa | 2776 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 2777 | gen_helper_set_mac_exts(cpu_env, val, acc); |
acf930aa | 2778 | else |
e1f3808e | 2779 | gen_helper_set_mac_extu(cpu_env, val, acc); |
acf930aa PB |
2780 | } |
2781 | ||
e6e5906b PB |
2782 | static disas_proc opcode_table[65536]; |
2783 | ||
2784 | static void | |
2785 | register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) | |
2786 | { | |
2787 | int i; | |
2788 | int from; | |
2789 | int to; | |
2790 | ||
2791 | /* Sanity check. All set bits must be included in the mask. */ | |
5fc4adf6 PB |
2792 | if (opcode & ~mask) { |
2793 | fprintf(stderr, | |
2794 | "qemu internal error: bogus opcode definition %04x/%04x\n", | |
2795 | opcode, mask); | |
e6e5906b | 2796 | abort(); |
5fc4adf6 | 2797 | } |
e6e5906b PB |
2798 | /* This could probably be cleverer. For now just optimize the case where |
2799 | the top bits are known. */ | |
2800 | /* Find the first zero bit in the mask. */ | |
2801 | i = 0x8000; | |
2802 | while ((i & mask) != 0) | |
2803 | i >>= 1; | |
2804 | /* Iterate over all combinations of this and lower bits. */ | |
2805 | if (i == 0) | |
2806 | i = 1; | |
2807 | else | |
2808 | i <<= 1; | |
2809 | from = opcode & ~(i - 1); | |
2810 | to = from + i; | |
0633879f | 2811 | for (i = from; i < to; i++) { |
e6e5906b PB |
2812 | if ((i & mask) == opcode) |
2813 | opcode_table[i] = proc; | |
0633879f | 2814 | } |
e6e5906b PB |
2815 | } |
2816 | ||
2817 | /* Register m68k opcode handlers. Order is important. | |
2818 | Later insn override earlier ones. */ | |
0402f767 | 2819 | void register_m68k_insns (CPUM68KState *env) |
e6e5906b | 2820 | { |
b2085257 JPAG |
2821 | /* Build the opcode table only once to avoid |
2822 | multithreading issues. */ | |
2823 | if (opcode_table[0] != NULL) { | |
2824 | return; | |
2825 | } | |
f076803b LV |
2826 | |
2827 | /* use BASE() for instruction available | |
2828 | * for CF_ISA_A and M68000. | |
2829 | */ | |
2830 | #define BASE(name, opcode, mask) \ | |
2831 | register_opcode(disas_##name, 0x##opcode, 0x##mask) | |
d315c888 | 2832 | #define INSN(name, opcode, mask, feature) do { \ |
0402f767 | 2833 | if (m68k_feature(env, M68K_FEATURE_##feature)) \ |
f076803b | 2834 | BASE(name, opcode, mask); \ |
d315c888 | 2835 | } while(0) |
f076803b | 2836 | BASE(undef, 0000, 0000); |
0402f767 | 2837 | INSN(arith_im, 0080, fff8, CF_ISA_A); |
f076803b LV |
2838 | INSN(arith_im, 0000, ff00, M68000); |
2839 | INSN(undef, 00c0, ffc0, M68000); | |
d315c888 | 2840 | INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); |
f076803b LV |
2841 | BASE(bitop_reg, 0100, f1c0); |
2842 | BASE(bitop_reg, 0140, f1c0); | |
2843 | BASE(bitop_reg, 0180, f1c0); | |
2844 | BASE(bitop_reg, 01c0, f1c0); | |
0402f767 | 2845 | INSN(arith_im, 0280, fff8, CF_ISA_A); |
f076803b LV |
2846 | INSN(arith_im, 0200, ff00, M68000); |
2847 | INSN(undef, 02c0, ffc0, M68000); | |
d315c888 | 2848 | INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); |
0402f767 | 2849 | INSN(arith_im, 0480, fff8, CF_ISA_A); |
f076803b LV |
2850 | INSN(arith_im, 0400, ff00, M68000); |
2851 | INSN(undef, 04c0, ffc0, M68000); | |
2852 | INSN(arith_im, 0600, ff00, M68000); | |
2853 | INSN(undef, 06c0, ffc0, M68000); | |
d315c888 | 2854 | INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); |
0402f767 | 2855 | INSN(arith_im, 0680, fff8, CF_ISA_A); |
0402f767 | 2856 | INSN(arith_im, 0c00, ff38, CF_ISA_A); |
f076803b LV |
2857 | INSN(arith_im, 0c00, ff00, M68000); |
2858 | BASE(bitop_im, 0800, ffc0); | |
2859 | BASE(bitop_im, 0840, ffc0); | |
2860 | BASE(bitop_im, 0880, ffc0); | |
2861 | BASE(bitop_im, 08c0, ffc0); | |
2862 | INSN(arith_im, 0a80, fff8, CF_ISA_A); | |
2863 | INSN(arith_im, 0a00, ff00, M68000); | |
2864 | BASE(move, 1000, f000); | |
2865 | BASE(move, 2000, f000); | |
2866 | BASE(move, 3000, f000); | |
d315c888 | 2867 | INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); |
0402f767 PB |
2868 | INSN(negx, 4080, fff8, CF_ISA_A); |
2869 | INSN(move_from_sr, 40c0, fff8, CF_ISA_A); | |
f076803b LV |
2870 | INSN(move_from_sr, 40c0, ffc0, M68000); |
2871 | BASE(lea, 41c0, f1c0); | |
2872 | BASE(clr, 4200, ff00); | |
2873 | BASE(undef, 42c0, ffc0); | |
0402f767 PB |
2874 | INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); |
2875 | INSN(neg, 4480, fff8, CF_ISA_A); | |
f076803b LV |
2876 | INSN(neg, 4400, ff00, M68000); |
2877 | INSN(undef, 44c0, ffc0, M68000); | |
2878 | BASE(move_to_ccr, 44c0, ffc0); | |
0402f767 | 2879 | INSN(not, 4680, fff8, CF_ISA_A); |
f076803b LV |
2880 | INSN(not, 4600, ff00, M68000); |
2881 | INSN(undef, 46c0, ffc0, M68000); | |
0402f767 | 2882 | INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); |
f076803b LV |
2883 | BASE(pea, 4840, ffc0); |
2884 | BASE(swap, 4840, fff8); | |
2885 | BASE(movem, 48c0, fbc0); | |
2886 | BASE(ext, 4880, fff8); | |
2887 | BASE(ext, 48c0, fff8); | |
2888 | BASE(ext, 49c0, fff8); | |
2889 | BASE(tst, 4a00, ff00); | |
0402f767 | 2890 | INSN(tas, 4ac0, ffc0, CF_ISA_B); |
f076803b | 2891 | INSN(tas, 4ac0, ffc0, M68000); |
0402f767 PB |
2892 | INSN(halt, 4ac8, ffff, CF_ISA_A); |
2893 | INSN(pulse, 4acc, ffff, CF_ISA_A); | |
f076803b | 2894 | BASE(illegal, 4afc, ffff); |
0402f767 | 2895 | INSN(mull, 4c00, ffc0, CF_ISA_A); |
f076803b | 2896 | INSN(mull, 4c00, ffc0, LONG_MULDIV); |
0402f767 | 2897 | INSN(divl, 4c40, ffc0, CF_ISA_A); |
f076803b | 2898 | INSN(divl, 4c40, ffc0, LONG_MULDIV); |
0402f767 | 2899 | INSN(sats, 4c80, fff8, CF_ISA_B); |
f076803b LV |
2900 | BASE(trap, 4e40, fff0); |
2901 | BASE(link, 4e50, fff8); | |
2902 | BASE(unlk, 4e58, fff8); | |
20dcee94 PB |
2903 | INSN(move_to_usp, 4e60, fff8, USP); |
2904 | INSN(move_from_usp, 4e68, fff8, USP); | |
f076803b LV |
2905 | BASE(nop, 4e71, ffff); |
2906 | BASE(stop, 4e72, ffff); | |
2907 | BASE(rte, 4e73, ffff); | |
2908 | BASE(rts, 4e75, ffff); | |
0402f767 | 2909 | INSN(movec, 4e7b, ffff, CF_ISA_A); |
f076803b | 2910 | BASE(jump, 4e80, ffc0); |
0402f767 PB |
2911 | INSN(jump, 4ec0, ffc0, CF_ISA_A); |
2912 | INSN(addsubq, 5180, f1c0, CF_ISA_A); | |
f076803b LV |
2913 | INSN(jump, 4ec0, ffc0, M68000); |
2914 | INSN(addsubq, 5000, f080, M68000); | |
2915 | INSN(addsubq, 5080, f0c0, M68000); | |
0402f767 PB |
2916 | INSN(scc, 50c0, f0f8, CF_ISA_A); |
2917 | INSN(addsubq, 5080, f1c0, CF_ISA_A); | |
2918 | INSN(tpf, 51f8, fff8, CF_ISA_A); | |
d315c888 PB |
2919 | |
2920 | /* Branch instructions. */ | |
f076803b | 2921 | BASE(branch, 6000, f000); |
d315c888 | 2922 | /* Disable long branch instructions, then add back the ones we want. */ |
f076803b | 2923 | BASE(undef, 60ff, f0ff); /* All long branches. */ |
d315c888 PB |
2924 | INSN(branch, 60ff, f0ff, CF_ISA_B); |
2925 | INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ | |
2926 | INSN(branch, 60ff, ffff, BRAL); | |
f076803b | 2927 | INSN(branch, 60ff, f0ff, BCCL); |
d315c888 | 2928 | |
f076803b | 2929 | BASE(moveq, 7000, f100); |
0402f767 | 2930 | INSN(mvzs, 7100, f100, CF_ISA_B); |
f076803b LV |
2931 | BASE(or, 8000, f000); |
2932 | BASE(divw, 80c0, f0c0); | |
2933 | BASE(addsub, 9000, f000); | |
0402f767 PB |
2934 | INSN(subx, 9180, f1f8, CF_ISA_A); |
2935 | INSN(suba, 91c0, f1c0, CF_ISA_A); | |
acf930aa | 2936 | |
f076803b | 2937 | BASE(undef_mac, a000, f000); |
acf930aa PB |
2938 | INSN(mac, a000, f100, CF_EMAC); |
2939 | INSN(from_mac, a180, f9b0, CF_EMAC); | |
2940 | INSN(move_mac, a110, f9fc, CF_EMAC); | |
2941 | INSN(from_macsr,a980, f9f0, CF_EMAC); | |
2942 | INSN(from_mask, ad80, fff0, CF_EMAC); | |
2943 | INSN(from_mext, ab80, fbf0, CF_EMAC); | |
2944 | INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); | |
2945 | INSN(to_mac, a100, f9c0, CF_EMAC); | |
2946 | INSN(to_macsr, a900, ffc0, CF_EMAC); | |
2947 | INSN(to_mext, ab00, fbc0, CF_EMAC); | |
2948 | INSN(to_mask, ad00, ffc0, CF_EMAC); | |
2949 | ||
0402f767 PB |
2950 | INSN(mov3q, a140, f1c0, CF_ISA_B); |
2951 | INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ | |
2952 | INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ | |
2953 | INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ | |
2954 | INSN(cmp, b080, f1c0, CF_ISA_A); | |
2955 | INSN(cmpa, b1c0, f1c0, CF_ISA_A); | |
f076803b LV |
2956 | INSN(cmp, b000, f100, M68000); |
2957 | INSN(eor, b100, f100, M68000); | |
2958 | INSN(cmpa, b0c0, f0c0, M68000); | |
0402f767 | 2959 | INSN(eor, b180, f1c0, CF_ISA_A); |
f076803b LV |
2960 | BASE(and, c000, f000); |
2961 | BASE(mulw, c0c0, f0c0); | |
2962 | BASE(addsub, d000, f000); | |
0402f767 PB |
2963 | INSN(addx, d180, f1f8, CF_ISA_A); |
2964 | INSN(adda, d1c0, f1c0, CF_ISA_A); | |
f076803b | 2965 | INSN(adda, d0c0, f0c0, M68000); |
0402f767 PB |
2966 | INSN(shift_im, e080, f0f0, CF_ISA_A); |
2967 | INSN(shift_reg, e0a0, f0f0, CF_ISA_A); | |
2968 | INSN(undef_fpu, f000, f000, CF_ISA_A); | |
e6e5906b PB |
2969 | INSN(fpu, f200, ffc0, CF_FPU); |
2970 | INSN(fbcc, f280, ffc0, CF_FPU); | |
0633879f PB |
2971 | INSN(frestore, f340, ffc0, CF_FPU); |
2972 | INSN(fsave, f340, ffc0, CF_FPU); | |
0402f767 PB |
2973 | INSN(intouch, f340, ffc0, CF_ISA_A); |
2974 | INSN(cpushl, f428, ff38, CF_ISA_A); | |
2975 | INSN(wddata, fb00, ff00, CF_ISA_A); | |
2976 | INSN(wdebug, fbc0, ffc0, CF_ISA_A); | |
e6e5906b PB |
2977 | #undef INSN |
2978 | } | |
2979 | ||
2980 | /* ??? Some of this implementation is not exception safe. We should always | |
2981 | write back the result to memory before setting the condition codes. */ | |
2b3e3cfe | 2982 | static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) |
e6e5906b PB |
2983 | { |
2984 | uint16_t insn; | |
2985 | ||
28b68cd7 | 2986 | insn = read_im16(env, s); |
e6e5906b | 2987 | |
d4d79bb1 | 2988 | opcode_table[insn](env, s, insn); |
e6e5906b PB |
2989 | } |
2990 | ||
e6e5906b | 2991 | /* generate intermediate code for basic block 'tb'. */ |
4e5e1215 | 2992 | void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 2993 | { |
4e5e1215 | 2994 | M68kCPU *cpu = m68k_env_get_cpu(env); |
ed2803da | 2995 | CPUState *cs = CPU(cpu); |
e6e5906b | 2996 | DisasContext dc1, *dc = &dc1; |
e6e5906b PB |
2997 | target_ulong pc_start; |
2998 | int pc_offset; | |
2e70f6ef PB |
2999 | int num_insns; |
3000 | int max_insns; | |
e6e5906b PB |
3001 | |
3002 | /* generate intermediate code */ | |
3003 | pc_start = tb->pc; | |
3b46e624 | 3004 | |
e6e5906b PB |
3005 | dc->tb = tb; |
3006 | ||
e6dbd3b3 | 3007 | dc->env = env; |
e6e5906b PB |
3008 | dc->is_jmp = DISAS_NEXT; |
3009 | dc->pc = pc_start; | |
3010 | dc->cc_op = CC_OP_DYNAMIC; | |
ed2803da | 3011 | dc->singlestep_enabled = cs->singlestep_enabled; |
e6e5906b | 3012 | dc->fpcr = env->fpcr; |
0633879f | 3013 | dc->user = (env->sr & SR_S) == 0; |
a7812ae4 | 3014 | dc->done_mac = 0; |
2e70f6ef PB |
3015 | num_insns = 0; |
3016 | max_insns = tb->cflags & CF_COUNT_MASK; | |
190ce7fb | 3017 | if (max_insns == 0) { |
2e70f6ef | 3018 | max_insns = CF_COUNT_MASK; |
190ce7fb RH |
3019 | } |
3020 | if (max_insns > TCG_MAX_INSNS) { | |
3021 | max_insns = TCG_MAX_INSNS; | |
3022 | } | |
2e70f6ef | 3023 | |
cd42d5b2 | 3024 | gen_tb_start(tb); |
e6e5906b | 3025 | do { |
e6e5906b PB |
3026 | pc_offset = dc->pc - pc_start; |
3027 | gen_throws_exception = NULL; | |
667b8e29 | 3028 | tcg_gen_insn_start(dc->pc); |
959082fc | 3029 | num_insns++; |
667b8e29 | 3030 | |
b933066a RH |
3031 | if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { |
3032 | gen_exception(dc, dc->pc, EXCP_DEBUG); | |
3033 | dc->is_jmp = DISAS_JUMP; | |
522a0d4e RH |
3034 | /* The address covered by the breakpoint must be included in |
3035 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
3036 | properly cleared -- thus we increment the PC here so that | |
3037 | the logic setting tb->size below does the right thing. */ | |
3038 | dc->pc += 2; | |
b933066a RH |
3039 | break; |
3040 | } | |
3041 | ||
959082fc | 3042 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
2e70f6ef | 3043 | gen_io_start(); |
667b8e29 RH |
3044 | } |
3045 | ||
510ff0b7 | 3046 | dc->insn_pc = dc->pc; |
e6e5906b | 3047 | disas_m68k_insn(env, dc); |
fe700adb | 3048 | } while (!dc->is_jmp && !tcg_op_buf_full() && |
ed2803da | 3049 | !cs->singlestep_enabled && |
1b530a6d | 3050 | !singlestep && |
2e70f6ef PB |
3051 | (pc_offset) < (TARGET_PAGE_SIZE - 32) && |
3052 | num_insns < max_insns); | |
e6e5906b | 3053 | |
2e70f6ef PB |
3054 | if (tb->cflags & CF_LAST_IO) |
3055 | gen_io_end(); | |
ed2803da | 3056 | if (unlikely(cs->singlestep_enabled)) { |
e6e5906b PB |
3057 | /* Make sure the pc is updated, and raise a debug exception. */ |
3058 | if (!dc->is_jmp) { | |
3059 | gen_flush_cc_op(dc); | |
e1f3808e | 3060 | tcg_gen_movi_i32(QREG_PC, dc->pc); |
e6e5906b | 3061 | } |
31871141 | 3062 | gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); |
e6e5906b PB |
3063 | } else { |
3064 | switch(dc->is_jmp) { | |
3065 | case DISAS_NEXT: | |
3066 | gen_flush_cc_op(dc); | |
3067 | gen_jmp_tb(dc, 0, dc->pc); | |
3068 | break; | |
3069 | default: | |
3070 | case DISAS_JUMP: | |
3071 | case DISAS_UPDATE: | |
3072 | gen_flush_cc_op(dc); | |
3073 | /* indicate that the hash table must be used to find the next TB */ | |
57fec1fe | 3074 | tcg_gen_exit_tb(0); |
e6e5906b PB |
3075 | break; |
3076 | case DISAS_TB_JUMP: | |
3077 | /* nothing more to generate */ | |
3078 | break; | |
3079 | } | |
3080 | } | |
806f352d | 3081 | gen_tb_end(tb, num_insns); |
e6e5906b PB |
3082 | |
3083 | #ifdef DEBUG_DISAS | |
4910e6e4 RH |
3084 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
3085 | && qemu_log_in_addr_range(pc_start)) { | |
93fcfe39 AL |
3086 | qemu_log("----------------\n"); |
3087 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 3088 | log_target_disas(cs, pc_start, dc->pc - pc_start, 0); |
93fcfe39 | 3089 | qemu_log("\n"); |
e6e5906b PB |
3090 | } |
3091 | #endif | |
4e5e1215 RH |
3092 | tb->size = dc->pc - pc_start; |
3093 | tb->icount = num_insns; | |
e6e5906b PB |
3094 | } |
3095 | ||
878096ee AF |
3096 | void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
3097 | int flags) | |
e6e5906b | 3098 | { |
878096ee AF |
3099 | M68kCPU *cpu = M68K_CPU(cs); |
3100 | CPUM68KState *env = &cpu->env; | |
e6e5906b PB |
3101 | int i; |
3102 | uint16_t sr; | |
3103 | CPU_DoubleU u; | |
3104 | for (i = 0; i < 8; i++) | |
3105 | { | |
3106 | u.d = env->fregs[i]; | |
3107 | cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", | |
3108 | i, env->dregs[i], i, env->aregs[i], | |
8fc7cc58 | 3109 | i, u.l.upper, u.l.lower, *(double *)&u.d); |
e6e5906b PB |
3110 | } |
3111 | cpu_fprintf (f, "PC = %08x ", env->pc); | |
3112 | sr = env->sr; | |
3113 | cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-', | |
3114 | (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', | |
3115 | (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); | |
8fc7cc58 | 3116 | cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); |
e6e5906b PB |
3117 | } |
3118 | ||
bad729e2 RH |
3119 | void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, |
3120 | target_ulong *data) | |
d2856f1a | 3121 | { |
bad729e2 | 3122 | env->pc = data[0]; |
d2856f1a | 3123 | } |