[mirror_qemu.git] / target-microblaze / cpu.h

/*
 *  MicroBlaze virtual CPU header
 *
 *  Copyright (c) 2009 Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef CPU_MICROBLAZE_H
#define CPU_MICROBLAZE_H

#include "config.h"
#include "qemu-common.h"

#define TARGET_LONG_BITS 32

#define CPUArchState struct CPUMBState

#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"
struct CPUMBState;
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif

#define TARGET_HAS_ICE 1

#define ELF_MACHINE	EM_MICROBLAZE

#define EXCP_NMI        1
#define EXCP_MMU        2
#define EXCP_IRQ        3
#define EXCP_BREAK      4
#define EXCP_HW_BREAK   5
#define EXCP_HW_EXCP    6

/* MicroBlaze-specific interrupt pending bits.  */
#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3

/* Meanings of the MBCPU object's two inbound GPIO lines */
#define MB_CPU_IRQ 0
#define MB_CPU_FIR 1

/* Register aliases. R0 - R15 */
#define R_SP     1
#define SR_PC    0
#define SR_MSR   1
#define SR_EAR   3
#define SR_ESR   5
#define SR_FSR   7
#define SR_BTR   0xb
#define SR_EDR   0xd

/* MSR flags.  */
#define MSR_BE  (1<<0) /* 0x001 */
#define MSR_IE  (1<<1) /* 0x002 */
#define MSR_C   (1<<2) /* 0x004 */
#define MSR_BIP (1<<3) /* 0x008 */
#define MSR_FSL (1<<4) /* 0x010 */
#define MSR_ICE (1<<5) /* 0x020 */
#define MSR_DZ  (1<<6) /* 0x040 */
#define MSR_DCE (1<<7) /* 0x080 */
#define MSR_EE  (1<<8) /* 0x100 */
#define MSR_EIP (1<<9) /* 0x200 */
#define MSR_PVR (1<<10) /* 0x400 */
#define MSR_CC  (1<<31)

/* Machine State Register (MSR) Fields */
#define MSR_UM (1<<11) /* User Mode */
#define MSR_UMS        (1<<12) /* User Mode Save */
#define MSR_VM (1<<13) /* Virtual Mode */
#define MSR_VMS        (1<<14) /* Virtual Mode Save */

#define MSR_KERNEL      MSR_EE|MSR_VM
//#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
#define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
//#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE

/* Exception State Register (ESR) Fields */
#define          ESR_DIZ       (1<<11) /* Zone Protection */
#define          ESR_S         (1<<10) /* Store instruction */

#define          ESR_ESS_FSL_OFFSET     5

#define          ESR_EC_FSL             0
#define          ESR_EC_UNALIGNED_DATA  1
#define          ESR_EC_ILLEGAL_OP      2
#define          ESR_EC_INSN_BUS        3
#define          ESR_EC_DATA_BUS        4
#define          ESR_EC_DIVZERO         5
#define          ESR_EC_FPU             6
#define          ESR_EC_PRIVINSN        7
#define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
#define          ESR_EC_DATA_STORAGE    8
#define          ESR_EC_INSN_STORAGE    9
#define          ESR_EC_DATA_TLB        10
#define          ESR_EC_INSN_TLB        11
#define          ESR_EC_MASK            31

/* Floating Point Status Register (FSR) Bits */
#define FSR_IO          (1<<4) /* Invalid operation */
#define FSR_DZ          (1<<3) /* Divide-by-zero */
#define FSR_OF          (1<<2) /* Overflow */
#define FSR_UF          (1<<1) /* Underflow */
#define FSR_DO          (1<<0) /* Denormalized operand error */

/* Version reg.  */
/* Basic PVR mask */
#define PVR0_PVR_FULL_MASK              0x80000000
#define PVR0_USE_BARREL_MASK            0x40000000
#define PVR0_USE_DIV_MASK               0x20000000
#define PVR0_USE_HW_MUL_MASK            0x10000000
#define PVR0_USE_FPU_MASK               0x08000000
#define PVR0_USE_EXC_MASK               0x04000000
#define PVR0_USE_ICACHE_MASK            0x02000000
#define PVR0_USE_DCACHE_MASK            0x01000000
#define PVR0_USE_MMU                    0x00800000      /* new */
#define PVR0_USE_BTC			0x00400000
#define PVR0_ENDI			0x00200000
#define PVR0_FAULT			0x00100000
#define PVR0_VERSION_MASK               0x0000FF00
#define PVR0_USER1_MASK                 0x000000FF

/* User 2 PVR mask */
#define PVR1_USER2_MASK                 0xFFFFFFFF

/* Configuration PVR masks */
#define PVR2_D_OPB_MASK                 0x80000000
#define PVR2_D_LMB_MASK                 0x40000000
#define PVR2_I_OPB_MASK                 0x20000000
#define PVR2_I_LMB_MASK                 0x10000000
#define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
#define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
#define PVR2_D_PLB_MASK                 0x02000000      /* new */
#define PVR2_I_PLB_MASK                 0x01000000      /* new */
#define PVR2_INTERCONNECT               0x00800000      /* new */
#define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
#define PVR2_USE_FSL_EXC                0x00040000      /* new */
#define PVR2_USE_MSR_INSTR              0x00020000
#define PVR2_USE_PCMP_INSTR             0x00010000
#define PVR2_AREA_OPTIMISED             0x00008000
#define PVR2_USE_BARREL_MASK            0x00004000
#define PVR2_USE_DIV_MASK               0x00002000
#define PVR2_USE_HW_MUL_MASK            0x00001000
#define PVR2_USE_FPU_MASK               0x00000800
#define PVR2_USE_MUL64_MASK             0x00000400
#define PVR2_USE_FPU2_MASK              0x00000200      /* new */
#define PVR2_USE_IPLBEXC                0x00000100
#define PVR2_USE_DPLBEXC                0x00000080
#define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
#define PVR2_UNALIGNED_EXC_MASK         0x00000020
#define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
#define PVR2_IOPB_BUS_EXC_MASK          0x00000008
#define PVR2_DOPB_BUS_EXC_MASK          0x00000004
#define PVR2_DIV_ZERO_EXC_MASK          0x00000002
#define PVR2_FPU_EXC_MASK               0x00000001

/* Debug and exception PVR masks */
#define PVR3_DEBUG_ENABLED_MASK         0x80000000
#define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
#define PVR3_FSL_LINKS_MASK             0x00000380

/* ICache config PVR masks */
#define PVR4_USE_ICACHE_MASK            0x80000000
#define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
#define PVR4_ICACHE_USE_FSL_MASK        0x02000000
#define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
#define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
#define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000

/* DCache config PVR masks */
#define PVR5_USE_DCACHE_MASK            0x80000000
#define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
#define PVR5_DCACHE_USE_FSL_MASK        0x02000000
#define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
#define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
#define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
#define PVR5_DCACHE_WRITEBACK_MASK      0x00004000

/* ICache base address PVR mask */
#define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF

/* ICache high address PVR mask */
#define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF

/* DCache base address PVR mask */
#define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF

/* DCache high address PVR mask */
#define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF

/* Target family PVR mask */
#define PVR10_TARGET_FAMILY_MASK        0xFF000000

/* MMU descrtiption */
#define PVR11_USE_MMU                   0xC0000000
#define PVR11_MMU_ITLB_SIZE             0x38000000
#define PVR11_MMU_DTLB_SIZE             0x07000000
#define PVR11_MMU_TLB_ACCESS            0x00C00000
#define PVR11_MMU_ZONES                 0x003E0000
/* MSR Reset value PVR mask */
#define PVR11_MSR_RESET_VALUE_MASK      0x000007FF


/* CPU flags.  */

/* Condition codes.  */
#define CC_GE  5
#define CC_GT  4
#define CC_LE  3
#define CC_LT  2
#define CC_NE  1
#define CC_EQ  0

#define NB_MMU_MODES    3

#define STREAM_EXCEPTION (1 << 0)
#define STREAM_ATOMIC    (1 << 1)
#define STREAM_TEST      (1 << 2)
#define STREAM_CONTROL   (1 << 3)
#define STREAM_NONBLOCK  (1 << 4)

struct CPUMBState {
    uint32_t debug;
    uint32_t btaken;
    uint32_t btarget;
    uint32_t bimm;

    uint32_t imm;
    uint32_t regs[33];
    uint32_t sregs[24];
    float_status fp_status;
    /* Stack protectors. Yes, it's a hw feature.  */
    uint32_t slr, shr;

    /* lwx/swx reserved address */
#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
    uint32_t res_addr;
    uint32_t res_val;

    /* Internal flags.  */
#define IMM_FLAG	4
#define MSR_EE_FLAG     (1 << 8)
#define DRTI_FLAG	(1 << 16)
#define DRTE_FLAG	(1 << 17)
#define DRTB_FLAG	(1 << 18)
#define D_FLAG		(1 << 19)  /* Bit in ESR.  */
/* TB dependent CPUMBState.  */
#define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
    uint32_t iflags;

    struct {
        uint32_t regs[16];
    } pvr;

#if !defined(CONFIG_USER_ONLY)
    /* Unified MMU.  */
    struct microblaze_mmu mmu;
#endif

    CPU_COMMON
};

#include "cpu-qom.h"

void mb_tcg_init(void);
MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
int cpu_mb_exec(CPUMBState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_mb_signal_handler(int host_signum, void *pinfo,
                          void *puc);

enum {
    CC_OP_DYNAMIC, /* Use env->cc_op  */
    CC_OP_FLAGS,
    CC_OP_CMP,
};

/* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
#define TARGET_PAGE_BITS 12
#define MMAP_SHIFT TARGET_PAGE_BITS

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

static inline CPUMBState *cpu_init(const char *cpu_model)
{
    MicroBlazeCPU *cpu = cpu_mb_init(cpu_model);
    if (cpu == NULL) {
        return NULL;
    }
    return &cpu->env;
}

#define cpu_exec cpu_mb_exec
#define cpu_gen_code cpu_mb_gen_code
#define cpu_signal_handler cpu_mb_signal_handler

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _nommu
#define MMU_MODE1_SUFFIX _kernel
#define MMU_MODE2_SUFFIX _user
#define MMU_NOMMU_IDX   0
#define MMU_KERNEL_IDX  1
#define MMU_USER_IDX    2
/* See NB_MMU_MODES further up the file.  */

static inline int cpu_mmu_index (CPUMBState *env)
{
        /* Are we in nommu mode?.  */
        if (!(env->sregs[SR_MSR] & MSR_VM))
            return MMU_NOMMU_IDX;

	if (env->sregs[SR_MSR] & MSR_UM)
            return MMU_USER_IDX;
        return MMU_KERNEL_IDX;
}

int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
                            int mmu_idx);
#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault

static inline int cpu_interrupts_enabled(CPUMBState *env)
{
    return env->sregs[SR_MSR] & MSR_IE;
}

#include "exec/cpu-all.h"

static inline target_ulong cpu_get_pc(CPUMBState *env)
{
    return env->sregs[SR_PC];
}

static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->sregs[SR_PC];
    *cs_base = 0;
    *flags = (env->iflags & IFLAGS_TB_MASK) |
                 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
}

#if !defined(CONFIG_USER_ONLY)
void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
                              bool is_write, bool is_exec, int is_asi,
                              unsigned size);
#endif

#include "exec/exec-all.h"

#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* MicroBlaze virtual CPU header
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	18	*/
	19	#ifndef CPU_MICROBLAZE_H
	20	#define CPU_MICROBLAZE_H
	21
94598c1d SW	22	#include "config.h"
	23	#include "qemu-common.h"
	24
4acb54ba EI	25	#define TARGET_LONG_BITS 32
4acb54ba EI	26
9349b4f9	27	#define CPUArchState struct CPUMBState
4acb54ba	28
022c62cb	29	#include "exec/cpu-defs.h"
6b4c305c	30	#include "fpu/softfloat.h"
4acb54ba	31	struct CPUMBState;
9b9a970a	32	typedef struct CPUMBState CPUMBState;
4acb54ba EI	33	#if !defined(CONFIG_USER_ONLY)
	34	#include "mmu.h"
	35	#endif
	36
	37	#define TARGET_HAS_ICE 1
	38
0d5d4699	39	#define ELF_MACHINE EM_MICROBLAZE
4acb54ba EI	40
	41	#define EXCP_NMI 1
	42	#define EXCP_MMU 2
	43	#define EXCP_IRQ 3
	44	#define EXCP_BREAK 4
	45	#define EXCP_HW_BREAK 5
cedb936b	46	#define EXCP_HW_EXCP 6
4acb54ba	47
85097db6 RH	48	/* MicroBlaze-specific interrupt pending bits. */
	49	#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
	50
73c69456 AF	51	/* Meanings of the MBCPU object's two inbound GPIO lines */
	52	#define MB_CPU_IRQ 0
	53	#define MB_CPU_FIR 1
	54
4acb54ba EI	55	/* Register aliases. R0 - R15 */
	56	#define R_SP 1
	57	#define SR_PC 0
	58	#define SR_MSR 1
	59	#define SR_EAR 3
	60	#define SR_ESR 5
	61	#define SR_FSR 7
	62	#define SR_BTR 0xb
	63	#define SR_EDR 0xd
	64
	65	/* MSR flags. */
	66	#define MSR_BE (1<<0) /* 0x001 */
	67	#define MSR_IE (1<<1) /* 0x002 */
	68	#define MSR_C (1<<2) /* 0x004 */
	69	#define MSR_BIP (1<<3) /* 0x008 */
	70	#define MSR_FSL (1<<4) /* 0x010 */
	71	#define MSR_ICE (1<<5) /* 0x020 */
	72	#define MSR_DZ (1<<6) /* 0x040 */
	73	#define MSR_DCE (1<<7) /* 0x080 */
	74	#define MSR_EE (1<<8) /* 0x100 */
	75	#define MSR_EIP (1<<9) /* 0x200 */
8a84fc6b	76	#define MSR_PVR (1<<10) /* 0x400 */
4acb54ba EI	77	#define MSR_CC (1<<31)
	78
	79	/* Machine State Register (MSR) Fields */
	80	#define MSR_UM (1<<11) /* User Mode */
	81	#define MSR_UMS (1<<12) /* User Mode Save */
	82	#define MSR_VM (1<<13) /* Virtual Mode */
	83	#define MSR_VMS (1<<14) /* Virtual Mode Save */
	84
	85	#define MSR_KERNEL MSR_EE\|MSR_VM
	86	//#define MSR_USER MSR_KERNEL\|MSR_UM\|MSR_IE
	87	#define MSR_KERNEL_VMS MSR_EE\|MSR_VMS
	88	//#define MSR_USER_VMS MSR_KERNEL_VMS\|MSR_UMS\|MSR_IE
	89
	90	/* Exception State Register (ESR) Fields */
	91	#define ESR_DIZ (1<<11) /* Zone Protection */
	92	#define ESR_S (1<<10) /* Store instruction */
	93
85453641 EI	94	#define ESR_ESS_FSL_OFFSET 5
85453641 EI	95
cedb936b EI	96	#define ESR_EC_FSL 0
	97	#define ESR_EC_UNALIGNED_DATA 1
	98	#define ESR_EC_ILLEGAL_OP 2
	99	#define ESR_EC_INSN_BUS 3
	100	#define ESR_EC_DATA_BUS 4
	101	#define ESR_EC_DIVZERO 5
	102	#define ESR_EC_FPU 6
	103	#define ESR_EC_PRIVINSN 7
5818dee5	104	#define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
cedb936b EI	105	#define ESR_EC_DATA_STORAGE 8
	106	#define ESR_EC_INSN_STORAGE 9
	107	#define ESR_EC_DATA_TLB 10
	108	#define ESR_EC_INSN_TLB 11
3b584046	109	#define ESR_EC_MASK 31
4acb54ba	110
bdc0bf29 EI	111	/* Floating Point Status Register (FSR) Bits */
	112	#define FSR_IO (1<<4) /* Invalid operation */
	113	#define FSR_DZ (1<<3) /* Divide-by-zero */
	114	#define FSR_OF (1<<2) /* Overflow */
	115	#define FSR_UF (1<<1) /* Underflow */
	116	#define FSR_DO (1<<0) /* Denormalized operand error */
	117
4acb54ba EI	118	/* Version reg. */
	119	/* Basic PVR mask */
	120	#define PVR0_PVR_FULL_MASK 0x80000000
	121	#define PVR0_USE_BARREL_MASK 0x40000000
	122	#define PVR0_USE_DIV_MASK 0x20000000
	123	#define PVR0_USE_HW_MUL_MASK 0x10000000
	124	#define PVR0_USE_FPU_MASK 0x08000000
	125	#define PVR0_USE_EXC_MASK 0x04000000
	126	#define PVR0_USE_ICACHE_MASK 0x02000000
	127	#define PVR0_USE_DCACHE_MASK 0x01000000
	128	#define PVR0_USE_MMU 0x00800000 /* new */
c4374bb7 MS	129	#define PVR0_USE_BTC 0x00400000
	130	#define PVR0_ENDI 0x00200000
	131	#define PVR0_FAULT 0x00100000
4acb54ba EI	132	#define PVR0_VERSION_MASK 0x0000FF00
	133	#define PVR0_USER1_MASK 0x000000FF
	134
	135	/* User 2 PVR mask */
	136	#define PVR1_USER2_MASK 0xFFFFFFFF
	137
	138	/* Configuration PVR masks */
	139	#define PVR2_D_OPB_MASK 0x80000000
	140	#define PVR2_D_LMB_MASK 0x40000000
	141	#define PVR2_I_OPB_MASK 0x20000000
	142	#define PVR2_I_LMB_MASK 0x10000000
	143	#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
	144	#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
	145	#define PVR2_D_PLB_MASK 0x02000000 /* new */
	146	#define PVR2_I_PLB_MASK 0x01000000 /* new */
	147	#define PVR2_INTERCONNECT 0x00800000 /* new */
	148	#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
	149	#define PVR2_USE_FSL_EXC 0x00040000 /* new */
	150	#define PVR2_USE_MSR_INSTR 0x00020000
	151	#define PVR2_USE_PCMP_INSTR 0x00010000
	152	#define PVR2_AREA_OPTIMISED 0x00008000
	153	#define PVR2_USE_BARREL_MASK 0x00004000
	154	#define PVR2_USE_DIV_MASK 0x00002000
	155	#define PVR2_USE_HW_MUL_MASK 0x00001000
	156	#define PVR2_USE_FPU_MASK 0x00000800
	157	#define PVR2_USE_MUL64_MASK 0x00000400
	158	#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
	159	#define PVR2_USE_IPLBEXC 0x00000100
	160	#define PVR2_USE_DPLBEXC 0x00000080
	161	#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
	162	#define PVR2_UNALIGNED_EXC_MASK 0x00000020
	163	#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
	164	#define PVR2_IOPB_BUS_EXC_MASK 0x00000008
	165	#define PVR2_DOPB_BUS_EXC_MASK 0x00000004
	166	#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
	167	#define PVR2_FPU_EXC_MASK 0x00000001
	168
	169	/* Debug and exception PVR masks */
	170	#define PVR3_DEBUG_ENABLED_MASK 0x80000000
	171	#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
	172	#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
	173	#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
	174	#define PVR3_FSL_LINKS_MASK 0x00000380
	175
	176	/* ICache config PVR masks */
	177	#define PVR4_USE_ICACHE_MASK 0x80000000
	178	#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
	179	#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
	180	#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
	181	#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
	182	#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
	183
	184	/* DCache config PVR masks */
	185	#define PVR5_USE_DCACHE_MASK 0x80000000
	186	#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
	187	#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
	188	#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
	189	#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
	190	#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
c4374bb7	191	#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
4acb54ba EI	192
	193	/* ICache base address PVR mask */
	194	#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
	195
	196	/* ICache high address PVR mask */
	197	#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
	198
	199	/* DCache base address PVR mask */
	200	#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
	201
	202	/* DCache high address PVR mask */
	203	#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
	204
	205	/* Target family PVR mask */
	206	#define PVR10_TARGET_FAMILY_MASK 0xFF000000
	207
	208	/* MMU descrtiption */
	209	#define PVR11_USE_MMU 0xC0000000
	210	#define PVR11_MMU_ITLB_SIZE 0x38000000
	211	#define PVR11_MMU_DTLB_SIZE 0x07000000
	212	#define PVR11_MMU_TLB_ACCESS 0x00C00000
7458a432	213	#define PVR11_MMU_ZONES 0x003E0000
4acb54ba EI	214	/* MSR Reset value PVR mask */
	215	#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
	216
	217
	218
	219	/* CPU flags. */
	220
	221	/* Condition codes. */
	222	#define CC_GE 5
	223	#define CC_GT 4
	224	#define CC_LE 3
	225	#define CC_LT 2
	226	#define CC_NE 1
	227	#define CC_EQ 0
	228
	229	#define NB_MMU_MODES 3
85453641 EI	230
	231	#define STREAM_EXCEPTION (1 << 0)
	232	#define STREAM_ATOMIC (1 << 1)
	233	#define STREAM_TEST (1 << 2)
	234	#define STREAM_CONTROL (1 << 3)
	235	#define STREAM_NONBLOCK (1 << 4)
	236
ae7d54d4	237	struct CPUMBState {
4acb54ba EI	238	uint32_t debug;
	239	uint32_t btaken;
	240	uint32_t btarget;
	241	uint32_t bimm;
	242
	243	uint32_t imm;
	244	uint32_t regs[33];
	245	uint32_t sregs[24];
97694c57	246	float_status fp_status;
5818dee5 EI	247	/* Stack protectors. Yes, it's a hw feature. */
5818dee5 EI	248	uint32_t slr, shr;
4acb54ba	249
8cc9b43f PC	250	/* lwx/swx reserved address */
	251	#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
	252	uint32_t res_addr;
11a76217	253	uint32_t res_val;
8cc9b43f	254
4acb54ba	255	/* Internal flags. */
cedb936b EI	256	#define IMM_FLAG 4
cedb936b EI	257	#define MSR_EE_FLAG (1 << 8)
4acb54ba EI	258	#define DRTI_FLAG (1 << 16)
	259	#define DRTE_FLAG (1 << 17)
	260	#define DRTB_FLAG (1 << 18)
	261	#define D_FLAG (1 << 19) /* Bit in ESR. */
68cee38a	262	/* TB dependent CPUMBState. */
fd1dc858	263	#define IFLAGS_TB_MASK (D_FLAG \| IMM_FLAG \| DRTI_FLAG \| DRTE_FLAG \| DRTB_FLAG)
4acb54ba EI	264	uint32_t iflags;
	265
	266	struct {
	267	uint32_t regs[16];
	268	} pvr;
	269
	270	#if !defined(CONFIG_USER_ONLY)
	271	/* Unified MMU. */
	272	struct microblaze_mmu mmu;
	273	#endif
	274
	275	CPU_COMMON
ae7d54d4	276	};
4acb54ba	277
b77f98ca AF	278	#include "cpu-qom.h"
b77f98ca AF	279
cd0c24f9	280	void mb_tcg_init(void);
b33ab1f7	281	MicroBlazeCPU cpu_mb_init(const char cpu_model);
68cee38a	282	int cpu_mb_exec(CPUMBState *s);
4acb54ba EI	283	/* you can call this signal handler from your SIGBUS and SIGSEGV
	284	signal handlers to inform the virtual CPU of exceptions. non zero
	285	is returned if the signal was handled by the virtual CPU. */
	286	int cpu_mb_signal_handler(int host_signum, void *pinfo,
	287	void *puc);
	288
	289	enum {
	290	CC_OP_DYNAMIC, /* Use env->cc_op */
	291	CC_OP_FLAGS,
	292	CC_OP_CMP,
	293	};
	294
	295	/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
	296	#define TARGET_PAGE_BITS 12
	297	#define MMAP_SHIFT TARGET_PAGE_BITS
	298
52705890 RH	299	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	300	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	301
b33ab1f7 AF	302	static inline CPUMBState cpu_init(const char cpu_model)
	303	{
	304	MicroBlazeCPU *cpu = cpu_mb_init(cpu_model);
	305	if (cpu == NULL) {
	306	return NULL;
	307	}
	308	return &cpu->env;
	309	}
	310
4acb54ba EI	311	#define cpu_exec cpu_mb_exec
	312	#define cpu_gen_code cpu_mb_gen_code
	313	#define cpu_signal_handler cpu_mb_signal_handler
	314
4acb54ba EI	315	/* MMU modes definitions */
	316	#define MMU_MODE0_SUFFIX _nommu
	317	#define MMU_MODE1_SUFFIX _kernel
	318	#define MMU_MODE2_SUFFIX _user
	319	#define MMU_NOMMU_IDX 0
	320	#define MMU_KERNEL_IDX 1
	321	#define MMU_USER_IDX 2
	322	/* See NB_MMU_MODES further up the file. */
	323
68cee38a	324	static inline int cpu_mmu_index (CPUMBState *env)
4acb54ba EI	325	{
	326	/* Are we in nommu mode?. */
	327	if (!(env->sregs[SR_MSR] & MSR_VM))
	328	return MMU_NOMMU_IDX;
	329
	330	if (env->sregs[SR_MSR] & MSR_UM)
	331	return MMU_USER_IDX;
	332	return MMU_KERNEL_IDX;
	333	}
	334
68cee38a	335	int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
97b348e7	336	int mmu_idx);
0b5c1ce8	337	#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
4acb54ba	338
68cee38a	339	static inline int cpu_interrupts_enabled(CPUMBState *env)
4acb54ba EI	340	{
	341	return env->sregs[SR_MSR] & MSR_IE;
	342	}
	343
022c62cb	344	#include "exec/cpu-all.h"
4acb54ba	345
68cee38a	346	static inline target_ulong cpu_get_pc(CPUMBState *env)
4acb54ba EI	347	{
	348	return env->sregs[SR_PC];
	349	}
	350
68cee38a	351	static inline void cpu_get_tb_cpu_state(CPUMBState env, target_ulong pc,
4acb54ba EI	352	target_ulong cs_base, int flags)
	353	{
	354	*pc = env->sregs[SR_PC];
	355	*cs_base = 0;
fd1dc858 EI	356	*flags = (env->iflags & IFLAGS_TB_MASK) \|
fd1dc858 EI	357	(env->sregs[SR_MSR] & (MSR_UM \| MSR_VM \| MSR_EE));
4acb54ba	358	}
faed1c2a	359
3c7b48b7	360	#if !defined(CONFIG_USER_ONLY)
c658b94f AF	361	void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
	362	bool is_write, bool is_exec, int is_asi,
	363	unsigned size);
4acb54ba	364	#endif
f081c76c	365
022c62cb	366	#include "exec/exec-all.h"
f081c76c	367
3c7b48b7	368	#endif