[mirror_qemu.git] / target-microblaze / mmu.c

/*
 *  Microblaze MMU emulation for qemu.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"

#define D(x)

static unsigned int tlb_decode_size(unsigned int f)
{
    static const unsigned int sizes[] = {
        1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
        1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
    };
    assert(f < ARRAY_SIZE(sizes));
    return sizes[f];
}

static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
    CPUState *cs = CPU(mb_env_get_cpu(env));
    struct microblaze_mmu *mmu = &env->mmu;
    unsigned int tlb_size;
    uint32_t tlb_tag, end, t;

    t = mmu->rams[RAM_TAG][idx];
    if (!(t & TLB_VALID))
        return;

    tlb_tag = t & TLB_EPN_MASK;
    tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
    end = tlb_tag + tlb_size;

    while (tlb_tag < end) {
        tlb_flush_page(cs, tlb_tag);
        tlb_tag += TARGET_PAGE_SIZE;
    }
}

static void mmu_change_pid(CPUMBState *env, unsigned int newpid) 
{
    struct microblaze_mmu *mmu = &env->mmu;
    unsigned int i;
    uint32_t t;

    if (newpid & ~0xff)
        qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);

    for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
        /* Lookup and decode.  */
        t = mmu->rams[RAM_TAG][i];
        if (t & TLB_VALID) {
            if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
                mmu_flush_idx(env, i);
        }
    }
}

/* rw - 0 = read, 1 = write, 2 = fetch.  */
unsigned int mmu_translate(struct microblaze_mmu *mmu,
                           struct microblaze_mmu_lookup *lu,
                           target_ulong vaddr, int rw, int mmu_idx)
{
    unsigned int i, hit = 0;
    unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
    unsigned int tlb_size;
    uint32_t tlb_tag, tlb_rpn, mask, t0;

    lu->err = ERR_MISS;
    for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
        uint32_t t, d;

        /* Lookup and decode.  */
        t = mmu->rams[RAM_TAG][i];
        D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
        if (t & TLB_VALID) {
            tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
            if (tlb_size < TARGET_PAGE_SIZE) {
                qemu_log("%d pages not supported\n", tlb_size);
                abort();
            }

            mask = ~(tlb_size - 1);
            tlb_tag = t & TLB_EPN_MASK;
            if ((vaddr & mask) != (tlb_tag & mask)) {
                D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
                           i, vaddr & mask, tlb_tag & mask));
                continue;
            }
            if (mmu->tids[i]
                && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
                D(qemu_log("TLB %d pid=%x != tid=%x\n",
                           i, mmu->regs[MMU_R_PID], mmu->tids[i]));
                continue;
            }

            /* Bring in the data part.  */
            d = mmu->rams[RAM_DATA][i];
            tlb_ex = d & TLB_EX;
            tlb_wr = d & TLB_WR;

            /* Now let's see if there is a zone that overrides the protbits.  */
            tlb_zsel = (d >> 4) & 0xf;
            t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
            t0 &= 0x3;

            if (tlb_zsel > mmu->c_mmu_zones) {
                qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of range! %d\n", tlb_zsel);
                t0 = 1; /* Ignore.  */
            }

            if (mmu->c_mmu == 1) {
                t0 = 1; /* Zones are disabled.  */
            }

            switch (t0) {
                case 0:
                    if (mmu_idx == MMU_USER_IDX)
                        continue;
                    break;
                case 2:
                    if (mmu_idx != MMU_USER_IDX) {
                        tlb_ex = 1;
                        tlb_wr = 1;
                    }
                    break;
                case 3:
                    tlb_ex = 1;
                    tlb_wr = 1;
                    break;
                default: break;
            }

            lu->err = ERR_PROT;
            lu->prot = PAGE_READ;
            if (tlb_wr)
                lu->prot |= PAGE_WRITE;
            else if (rw == 1)
                goto done;
            if (tlb_ex)
                lu->prot |=PAGE_EXEC;
            else if (rw == 2) {
                goto done;
            }

            tlb_rpn = d & TLB_RPN_MASK;

            lu->vaddr = tlb_tag;
            lu->paddr = tlb_rpn;
            lu->size = tlb_size;
            lu->err = ERR_HIT;
            lu->idx = i;
            hit = 1;
            goto done;
        }
    }
done:
    D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
              vaddr, rw, tlb_wr, tlb_ex, hit));
    return hit;
}

/* Writes/reads to the MMU's special regs end up here.  */
uint32_t mmu_read(CPUMBState *env, uint32_t rn)
{
    unsigned int i;
    uint32_t r;

    if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
        qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
        return 0;
    }

    switch (rn) {
        /* Reads to HI/LO trig reads from the mmu rams.  */
        case MMU_R_TLBLO:
        case MMU_R_TLBHI:
            if (!(env->mmu.c_mmu_tlb_access & 1)) {
                qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
                return 0;
            }

            i = env->mmu.regs[MMU_R_TLBX] & 0xff;
            r = env->mmu.rams[rn & 1][i];
            if (rn == MMU_R_TLBHI)
                env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
            break;
        case MMU_R_PID:
        case MMU_R_ZPR:
            if (!(env->mmu.c_mmu_tlb_access & 1)) {
                qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
                return 0;
            }
            r = env->mmu.regs[rn];
            break;
        default:
            r = env->mmu.regs[rn];
            break;
    }
    D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
    return r;
}

void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
    MicroBlazeCPU *cpu = mb_env_get_cpu(env);
    unsigned int i;
    D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));

    if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
        qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
        return;
    }

    switch (rn) {
        /* Writes to HI/LO trig writes to the mmu rams.  */
        case MMU_R_TLBLO:
        case MMU_R_TLBHI:
            i = env->mmu.regs[MMU_R_TLBX] & 0xff;
            if (rn == MMU_R_TLBHI) {
                if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
                    qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%x\n",
                             i, env->sregs[SR_PC]);
                env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
                mmu_flush_idx(env, i);
            }
            env->mmu.rams[rn & 1][i] = v;

            D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v));
            break;
        case MMU_R_ZPR:
            if (env->mmu.c_mmu_tlb_access <= 1) {
                qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
                return;
            }

            /* Changes to the zone protection reg flush the QEMU TLB.
               Fortunately, these are very uncommon.  */
            if (v != env->mmu.regs[rn]) {
                tlb_flush(CPU(cpu), 1);
            }
            env->mmu.regs[rn] = v;
            break;
        case MMU_R_PID:
            if (env->mmu.c_mmu_tlb_access <= 1) {
                qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
                return;
            }

            if (v != env->mmu.regs[rn]) {
                mmu_change_pid(env, v);
                env->mmu.regs[rn] = v;
            }
            break;
        case MMU_R_TLBSX:
        {
            struct microblaze_mmu_lookup lu;
            int hit;

            if (env->mmu.c_mmu_tlb_access <= 1) {
                qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
                return;
            }

            hit = mmu_translate(&env->mmu, &lu,
                                v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
            if (hit) {
                env->mmu.regs[MMU_R_TLBX] = lu.idx;
            } else
                env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
            break;
        }
        default:
            env->mmu.regs[rn] = v;
            break;
   }
}

void mmu_init(struct microblaze_mmu *mmu)
{
    int i;
    for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
        mmu->regs[i] = 0;
    }
}
Commit	Line	Data
afeeceb0 EI	1	/*
	2	* Microblaze MMU emulation for qemu.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
afeeceb0 EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
afeeceb0	19	*/
afeeceb0	20
8fd9dece	21	#include "qemu/osdep.h"
afeeceb0	22	#include "cpu.h"
afeeceb0 EI	23
	24	#define D(x)
	25
	26	static unsigned int tlb_decode_size(unsigned int f)
	27	{
	28	static const unsigned int sizes[] = {
	29	1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
	30	1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
	31	};
	32	assert(f < ARRAY_SIZE(sizes));
	33	return sizes[f];
	34	}
	35
68cee38a	36	static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
afeeceb0	37	{
31b030d4	38	CPUState *cs = CPU(mb_env_get_cpu(env));
afeeceb0 EI	39	struct microblaze_mmu *mmu = &env->mmu;
	40	unsigned int tlb_size;
	41	uint32_t tlb_tag, end, t;
	42
	43	t = mmu->rams[RAM_TAG][idx];
	44	if (!(t & TLB_VALID))
	45	return;
	46
	47	tlb_tag = t & TLB_EPN_MASK;
	48	tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
	49	end = tlb_tag + tlb_size;
	50
	51	while (tlb_tag < end) {
31b030d4	52	tlb_flush_page(cs, tlb_tag);
afeeceb0 EI	53	tlb_tag += TARGET_PAGE_SIZE;
	54	}
	55	}
	56
68cee38a	57	static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
afeeceb0 EI	58	{
	59	struct microblaze_mmu *mmu = &env->mmu;
	60	unsigned int i;
183aa454	61	uint32_t t;
afeeceb0 EI	62
afeeceb0 EI	63	if (newpid & ~0xff)
1d512a65	64	qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);
afeeceb0 EI	65
	66	for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
	67	/* Lookup and decode. */
	68	t = mmu->rams[RAM_TAG][i];
	69	if (t & TLB_VALID) {
afeeceb0 EI	70	if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
	71	mmu_flush_idx(env, i);
	72	}
	73	}
	74	}
	75
	76	/* rw - 0 = read, 1 = write, 2 = fetch. */
	77	unsigned int mmu_translate(struct microblaze_mmu *mmu,
	78	struct microblaze_mmu_lookup *lu,
	79	target_ulong vaddr, int rw, int mmu_idx)
	80	{
	81	unsigned int i, hit = 0;
	82	unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
	83	unsigned int tlb_size;
	84	uint32_t tlb_tag, tlb_rpn, mask, t0;
	85
	86	lu->err = ERR_MISS;
	87	for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
	88	uint32_t t, d;
	89
	90	/* Lookup and decode. */
	91	t = mmu->rams[RAM_TAG][i];
	92	D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
	93	if (t & TLB_VALID) {
	94	tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
	95	if (tlb_size < TARGET_PAGE_SIZE) {
	96	qemu_log("%d pages not supported\n", tlb_size);
	97	abort();
	98	}
	99
	100	mask = ~(tlb_size - 1);
	101	tlb_tag = t & TLB_EPN_MASK;
	102	if ((vaddr & mask) != (tlb_tag & mask)) {
	103	D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
	104	i, vaddr & mask, tlb_tag & mask));
	105	continue;
	106	}
	107	if (mmu->tids[i]
	108	&& ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
	109	D(qemu_log("TLB %d pid=%x != tid=%x\n",
	110	i, mmu->regs[MMU_R_PID], mmu->tids[i]));
	111	continue;
	112	}
	113
	114	/* Bring in the data part. */
	115	d = mmu->rams[RAM_DATA][i];
	116	tlb_ex = d & TLB_EX;
	117	tlb_wr = d & TLB_WR;
	118
e03ba136	119	/* Now let's see if there is a zone that overrides the protbits. */
afeeceb0 EI	120	tlb_zsel = (d >> 4) & 0xf;
	121	t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
	122	t0 &= 0x3;
3c50a71f EI	123
3c50a71f EI	124	if (tlb_zsel > mmu->c_mmu_zones) {
1d512a65	125	qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of range! %d\n", tlb_zsel);
3c50a71f EI	126	t0 = 1; /* Ignore. */
	127	}
	128
	129	if (mmu->c_mmu == 1) {
	130	t0 = 1; /* Zones are disabled. */
	131	}
	132
afeeceb0 EI	133	switch (t0) {
	134	case 0:
	135	if (mmu_idx == MMU_USER_IDX)
	136	continue;
	137	break;
	138	case 2:
	139	if (mmu_idx != MMU_USER_IDX) {
	140	tlb_ex = 1;
	141	tlb_wr = 1;
	142	}
	143	break;
	144	case 3:
	145	tlb_ex = 1;
	146	tlb_wr = 1;
	147	break;
3c50a71f	148	default: break;
afeeceb0 EI	149	}
afeeceb0 EI	150
afeeceb0 EI	151	lu->err = ERR_PROT;
	152	lu->prot = PAGE_READ;
	153	if (tlb_wr)
	154	lu->prot \|= PAGE_WRITE;
	155	else if (rw == 1)
	156	goto done;
	157	if (tlb_ex)
	158	lu->prot \|=PAGE_EXEC;
	159	else if (rw == 2) {
	160	goto done;
	161	}
	162
	163	tlb_rpn = d & TLB_RPN_MASK;
	164
	165	lu->vaddr = tlb_tag;
	166	lu->paddr = tlb_rpn;
	167	lu->size = tlb_size;
	168	lu->err = ERR_HIT;
	169	lu->idx = i;
	170	hit = 1;
	171	goto done;
	172	}
	173	}
	174	done:
	175	D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
	176	vaddr, rw, tlb_wr, tlb_ex, hit));
	177	return hit;
	178	}
	179
	180	/* Writes/reads to the MMU's special regs end up here. */
68cee38a	181	uint32_t mmu_read(CPUMBState *env, uint32_t rn)
afeeceb0 EI	182	{
	183	unsigned int i;
	184	uint32_t r;
	185
3c50a71f	186	if (env->mmu.c_mmu < 2 \|\| !env->mmu.c_mmu_tlb_access) {
1d512a65	187	qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
3c50a71f EI	188	return 0;
	189	}
	190
afeeceb0 EI	191	switch (rn) {
	192	/* Reads to HI/LO trig reads from the mmu rams. */
	193	case MMU_R_TLBLO:
	194	case MMU_R_TLBHI:
3c50a71f	195	if (!(env->mmu.c_mmu_tlb_access & 1)) {
1d512a65	196	qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
3c50a71f EI	197	return 0;
	198	}
	199
afeeceb0 EI	200	i = env->mmu.regs[MMU_R_TLBX] & 0xff;
	201	r = env->mmu.rams[rn & 1][i];
	202	if (rn == MMU_R_TLBHI)
	203	env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
	204	break;
3c50a71f EI	205	case MMU_R_PID:
	206	case MMU_R_ZPR:
	207	if (!(env->mmu.c_mmu_tlb_access & 1)) {
1d512a65	208	qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
3c50a71f EI	209	return 0;
	210	}
	211	r = env->mmu.regs[rn];
	212	break;
afeeceb0 EI	213	default:
	214	r = env->mmu.regs[rn];
	215	break;
	216	}
	217	D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
	218	return r;
	219	}
	220
68cee38a	221	void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
afeeceb0	222	{
00c8cb0a	223	MicroBlazeCPU *cpu = mb_env_get_cpu(env);
afeeceb0 EI	224	unsigned int i;
	225	D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
	226
3c50a71f	227	if (env->mmu.c_mmu < 2 \|\| !env->mmu.c_mmu_tlb_access) {
1d512a65	228	qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
3c50a71f EI	229	return;
	230	}
	231
afeeceb0 EI	232	switch (rn) {
	233	/* Writes to HI/LO trig writes to the mmu rams. */
	234	case MMU_R_TLBLO:
	235	case MMU_R_TLBHI:
	236	i = env->mmu.regs[MMU_R_TLBX] & 0xff;
	237	if (rn == MMU_R_TLBHI) {
	238	if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
1d512a65	239	qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%x\n",
afeeceb0 EI	240	i, env->sregs[SR_PC]);
	241	env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
	242	mmu_flush_idx(env, i);
	243	}
	244	env->mmu.rams[rn & 1][i] = v;
	245
	246	D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v));
	247	break;
	248	case MMU_R_ZPR:
3c50a71f	249	if (env->mmu.c_mmu_tlb_access <= 1) {
1d512a65	250	qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
3c50a71f EI	251	return;
	252	}
	253
d0f3654f EI	254	/* Changes to the zone protection reg flush the QEMU TLB.
	255	Fortunately, these are very uncommon. */
	256	if (v != env->mmu.regs[rn]) {
00c8cb0a	257	tlb_flush(CPU(cpu), 1);
d0f3654f EI	258	}
	259	env->mmu.regs[rn] = v;
	260	break;
afeeceb0	261	case MMU_R_PID:
3c50a71f	262	if (env->mmu.c_mmu_tlb_access <= 1) {
1d512a65	263	qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
3c50a71f EI	264	return;
	265	}
	266
afeeceb0 EI	267	if (v != env->mmu.regs[rn]) {
	268	mmu_change_pid(env, v);
	269	env->mmu.regs[rn] = v;
	270	}
	271	break;
	272	case MMU_R_TLBSX:
	273	{
	274	struct microblaze_mmu_lookup lu;
	275	int hit;
3c50a71f EI	276
3c50a71f EI	277	if (env->mmu.c_mmu_tlb_access <= 1) {
1d512a65	278	qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
3c50a71f EI	279	return;
	280	}
	281
afeeceb0	282	hit = mmu_translate(&env->mmu, &lu,
97ed5ccd	283	v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
afeeceb0 EI	284	if (hit) {
	285	env->mmu.regs[MMU_R_TLBX] = lu.idx;
	286	} else
	287	env->mmu.regs[MMU_R_TLBX] \|= 0x80000000;
	288	break;
	289	}
	290	default:
	291	env->mmu.regs[rn] = v;
	292	break;
	293	}
	294	}
	295
	296	void mmu_init(struct microblaze_mmu *mmu)
	297	{
3c50a71f EI	298	int i;
	299	for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
	300	mmu->regs[i] = 0;
	301	}
afeeceb0	302	}