[mirror_qemu.git] / target-microblaze / op_helper.c

/*
 *  Microblaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"

#define D(x)

#if !defined(CONFIG_USER_ONLY)

/* Try to fill the TLB and return an exception if error. If retaddr is
 * NULL, it means that the function was called in C code (i.e. not
 * from generated code or from helper.c)
 */
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    int ret;

    ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            cpu_restore_state(cs, retaddr);
        }
        cpu_loop_exit(cs);
    }
}
#endif

void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
             id, data,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
}

uint32_t helper_get(uint32_t id, uint32_t ctrl)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
             id,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
    return 0xdead0000 | id;
}

void helper_raise_exception(CPUMBState *env, uint32_t index)
{
    CPUState *cs = CPU(mb_env_get_cpu(env));

    cs->exception_index = index;
    cpu_loop_exit(cs);
}

void helper_debug(CPUMBState *env)
{
    int i;

    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
             env->debug, env->imm, env->iflags);
    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
             env->btaken, env->btarget,
             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_EIP),
             (env->sregs[SR_MSR] & MSR_IE));
    for (i = 0; i < 32; i++) {
        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
        if ((i + 1) % 4 == 0)
            qemu_log("\n");
    }
    qemu_log("\n\n");
}

static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
{
    uint32_t cout = 0;

    if ((b == ~0) && cin)
        cout = 1;
    else if ((~0 - a) < (b + cin))
        cout = 1;
    return cout;
}

uint32_t helper_cmp(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (b & 0x80000000);
    return t;
}

uint32_t helper_cmpu(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (a & 0x80000000);
    return t;
}

uint32_t helper_clz(uint32_t t0)
{
    return clz32(t0);
}

uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
{
    return compute_carry(a, b, cf);
}

static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (b == 0) {
        env->sregs[SR_MSR] |= MSR_DZ;

        if ((env->sregs[SR_MSR] & MSR_EE)
            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
        return 0;
    }
    env->sregs[SR_MSR] &= ~MSR_DZ;
    return 1;
}

uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return (int32_t)a / (int32_t)b;
}

uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return a / b;
}

/* raise FPU exception.  */
static void raise_fpu_exception(CPUMBState *env)
{
    env->sregs[SR_ESR] = ESR_EC_FPU;
    helper_raise_exception(env, EXCP_HW_EXCP);
}

static void update_fpu_flags(CPUMBState *env, int flags)
{
    int raise = 0;

    if (flags & float_flag_invalid) {
        env->sregs[SR_FSR] |= FSR_IO;
        raise = 1;
    }
    if (flags & float_flag_divbyzero) {
        env->sregs[SR_FSR] |= FSR_DZ;
        raise = 1;
    }
    if (flags & float_flag_overflow) {
        env->sregs[SR_FSR] |= FSR_OF;
        raise = 1;
    }
    if (flags & float_flag_underflow) {
        env->sregs[SR_FSR] |= FSR_UF;
        raise = 1;
    }
    if (raise
        && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
        && (env->sregs[SR_MSR] & MSR_EE)) {
        raise_fpu_exception(env);
    }
}

uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_add(fa.f, fb.f, &env->fp_status);

    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_div(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    uint32_t r = 0;

    fa.l = a;
    fb.l = b;

    if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
        update_fpu_flags(env, float_flag_invalid);
        r = 1;
    }

    if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
        r = 1;
    }

    return r;
}

uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_lt(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_le(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);


    return r;
}

uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);
    return r;
}

uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_flt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;

    fa.l = a;
    fd.f = int32_to_float32(fa.l, &env->fp_status);
    return fd.l;
}

uint32_t helper_fint(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fa;
    uint32_t r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    r = float32_to_int32(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return r;
}

uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fd.l = float32_sqrt(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
{
    unsigned int i;
    uint32_t mask = 0xff000000;

    for (i = 0; i < 4; i++) {
        if ((a & mask) == (b & mask))
            return i + 1;
        mask >>= 8;
    }
    return 0;
}

void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
                     uint32_t mask)
{
    if (addr & mask) {
            qemu_log_mask(CPU_LOG_INT,
                          "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
                          addr, mask, wr, dr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                 | (dr & 31) << 5;
            if (mask == 3) {
                env->sregs[SR_ESR] |= 1 << 11;
            }
            if (!(env->sregs[SR_MSR] & MSR_EE)) {
                return;
            }
            helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

void helper_stackprot(CPUMBState *env, uint32_t addr)
{
    if (addr < env->slr || addr > env->shr) {
        qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
                      addr, env->slr, env->shr);
        env->sregs[SR_EAR] = addr;
        env->sregs[SR_ESR] = ESR_EC_STACKPROT;
        helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here.  */
uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
{
    return mmu_read(env, rn);
}

void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
    mmu_write(env, rn, v);
}

void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
                              bool is_write, bool is_exec, int is_asi,
                              unsigned size)
{
    MicroBlazeCPU *cpu;
    CPUMBState *env;

    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
             addr, is_write ? 1 : 0, is_exec ? 1 : 0);
    if (cs == NULL) {
        return;
    }
    cpu = MICROBLAZE_CPU(cs);
    env = &cpu->env;
    if (!(env->sregs[SR_MSR] & MSR_EE)) {
        return;
    }

    env->sregs[SR_EAR] = addr;
    if (is_exec) {
        if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    } else {
        if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    }
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* Microblaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	19	*/
4acb54ba EI	20
8fd9dece	21	#include "qemu/osdep.h"
3e457172	22	#include "cpu.h"
2ef6175a	23	#include "exec/helper-proto.h"
1de7afc9	24	#include "qemu/host-utils.h"
63c91552	25	#include "exec/exec-all.h"
f08b6170	26	#include "exec/cpu_ldst.h"
4acb54ba EI	27
	28	#define D(x)
	29
	30	#if !defined(CONFIG_USER_ONLY)
3e457172	31
4acb54ba	32	/* Try to fill the TLB and return an exception if error. If retaddr is
d5a11fef AF	33	* NULL, it means that the function was called in C code (i.e. not
	34	* from generated code or from helper.c)
	35	*/
	36	void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
20503968	37	uintptr_t retaddr)
4acb54ba	38	{
4acb54ba EI	39	int ret;
4acb54ba EI	40
d5a11fef	41	ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
4acb54ba EI	42	if (unlikely(ret)) {
	43	if (retaddr) {
	44	/* now we have a real cpu fault */
3f38f309	45	cpu_restore_state(cs, retaddr);
4acb54ba	46	}
5638d180	47	cpu_loop_exit(cs);
4acb54ba	48	}
4acb54ba EI	49	}
	50	#endif
	51
6d76d23e EI	52	void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
	53	{
	54	int test = ctrl & STREAM_TEST;
	55	int atomic = ctrl & STREAM_ATOMIC;
	56	int control = ctrl & STREAM_CONTROL;
	57	int nonblock = ctrl & STREAM_NONBLOCK;
	58	int exception = ctrl & STREAM_EXCEPTION;
	59
1d512a65	60	qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
6d76d23e EI	61	id, data,
	62	test ? "t" : "",
	63	nonblock ? "n" : "",
	64	exception ? "e" : "",
	65	control ? "c" : "",
	66	atomic ? "a" : "");
	67	}
	68
	69	uint32_t helper_get(uint32_t id, uint32_t ctrl)
	70	{
	71	int test = ctrl & STREAM_TEST;
	72	int atomic = ctrl & STREAM_ATOMIC;
	73	int control = ctrl & STREAM_CONTROL;
	74	int nonblock = ctrl & STREAM_NONBLOCK;
	75	int exception = ctrl & STREAM_EXCEPTION;
	76
1d512a65	77	qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
6d76d23e EI	78	id,
	79	test ? "t" : "",
	80	nonblock ? "n" : "",
	81	exception ? "e" : "",
	82	control ? "c" : "",
	83	atomic ? "a" : "");
	84	return 0xdead0000 \| id;
	85	}
	86
64254eba	87	void helper_raise_exception(CPUMBState *env, uint32_t index)
4acb54ba	88	{
27103424 AF	89	CPUState *cs = CPU(mb_env_get_cpu(env));
	90
	91	cs->exception_index = index;
5638d180	92	cpu_loop_exit(cs);
4acb54ba EI	93	}
4acb54ba EI	94
64254eba	95	void helper_debug(CPUMBState *env)
4acb54ba EI	96	{
	97	int i;
	98
	99	qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
4c24aa0a MS	100	qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
4c24aa0a MS	101	env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
17c52a43 EI	102	env->debug, env->imm, env->iflags);
	103	qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
	104	env->btaken, env->btarget,
	105	(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
	106	(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
	107	(env->sregs[SR_MSR] & MSR_EIP),
	108	(env->sregs[SR_MSR] & MSR_IE));
4acb54ba EI	109	for (i = 0; i < 32; i++) {
	110	qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
	111	if ((i + 1) % 4 == 0)
	112	qemu_log("\n");
	113	}
	114	qemu_log("\n\n");
	115	}
	116
	117	static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
	118	{
	119	uint32_t cout = 0;
	120
	121	if ((b == ~0) && cin)
	122	cout = 1;
	123	else if ((~0 - a) < (b + cin))
	124	cout = 1;
	125	return cout;
	126	}
	127
	128	uint32_t helper_cmp(uint32_t a, uint32_t b)
	129	{
	130	uint32_t t;
	131
	132	t = b + ~a + 1;
	133	if ((b & 0x80000000) ^ (a & 0x80000000))
	134	t = (t & 0x7fffffff) \| (b & 0x80000000);
	135	return t;
	136	}
	137
	138	uint32_t helper_cmpu(uint32_t a, uint32_t b)
	139	{
	140	uint32_t t;
	141
	142	t = b + ~a + 1;
	143	if ((b & 0x80000000) ^ (a & 0x80000000))
	144	t = (t & 0x7fffffff) \| (a & 0x80000000);
	145	return t;
	146	}
	147
48b5e96f EI	148	uint32_t helper_clz(uint32_t t0)
	149	{
	150	return clz32(t0);
	151	}
	152
5d0bb823	153	uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
4acb54ba	154	{
738c8b01	155	return compute_carry(a, b, cf);
4acb54ba EI	156	}
4acb54ba EI	157
64254eba	158	static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba EI	159	{
	160	if (b == 0) {
	161	env->sregs[SR_MSR] \|= MSR_DZ;
821ebb33 EI	162
	163	if ((env->sregs[SR_MSR] & MSR_EE)
	164	&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
	165	env->sregs[SR_ESR] = ESR_EC_DIVZERO;
64254eba	166	helper_raise_exception(env, EXCP_HW_EXCP);
821ebb33	167	}
4acb54ba EI	168	return 0;
	169	}
	170	env->sregs[SR_MSR] &= ~MSR_DZ;
	171	return 1;
	172	}
	173
64254eba	174	uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	175	{
64254eba	176	if (!div_prepare(env, a, b)) {
4acb54ba	177	return 0;
64254eba	178	}
4acb54ba EI	179	return (int32_t)a / (int32_t)b;
	180	}
	181
64254eba	182	uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	183	{
64254eba	184	if (!div_prepare(env, a, b)) {
4acb54ba	185	return 0;
64254eba	186	}
4acb54ba EI	187	return a / b;
	188	}
	189
97694c57	190	/* raise FPU exception. */
64254eba	191	static void raise_fpu_exception(CPUMBState *env)
97694c57 EI	192	{
97694c57 EI	193	env->sregs[SR_ESR] = ESR_EC_FPU;
64254eba	194	helper_raise_exception(env, EXCP_HW_EXCP);
97694c57 EI	195	}
97694c57 EI	196
64254eba	197	static void update_fpu_flags(CPUMBState *env, int flags)
97694c57 EI	198	{
	199	int raise = 0;
	200
	201	if (flags & float_flag_invalid) {
	202	env->sregs[SR_FSR] \|= FSR_IO;
	203	raise = 1;
	204	}
	205	if (flags & float_flag_divbyzero) {
	206	env->sregs[SR_FSR] \|= FSR_DZ;
	207	raise = 1;
	208	}
	209	if (flags & float_flag_overflow) {
	210	env->sregs[SR_FSR] \|= FSR_OF;
	211	raise = 1;
	212	}
	213	if (flags & float_flag_underflow) {
	214	env->sregs[SR_FSR] \|= FSR_UF;
	215	raise = 1;
	216	}
	217	if (raise
	218	&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
	219	&& (env->sregs[SR_MSR] & MSR_EE)) {
64254eba	220	raise_fpu_exception(env);
97694c57 EI	221	}
	222	}
	223
64254eba	224	uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	225	{
	226	CPU_FloatU fd, fa, fb;
	227	int flags;
	228
	229	set_float_exception_flags(0, &env->fp_status);
	230	fa.l = a;
	231	fb.l = b;
	232	fd.f = float32_add(fa.f, fb.f, &env->fp_status);
	233
	234	flags = get_float_exception_flags(&env->fp_status);
64254eba	235	update_fpu_flags(env, flags);
97694c57 EI	236	return fd.l;
	237	}
	238
64254eba	239	uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	240	{
	241	CPU_FloatU fd, fa, fb;
	242	int flags;
	243
	244	set_float_exception_flags(0, &env->fp_status);
	245	fa.l = a;
	246	fb.l = b;
	247	fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
	248	flags = get_float_exception_flags(&env->fp_status);
64254eba	249	update_fpu_flags(env, flags);
97694c57 EI	250	return fd.l;
	251	}
	252
64254eba	253	uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	254	{
	255	CPU_FloatU fd, fa, fb;
	256	int flags;
	257
	258	set_float_exception_flags(0, &env->fp_status);
	259	fa.l = a;
	260	fb.l = b;
	261	fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
	262	flags = get_float_exception_flags(&env->fp_status);
64254eba	263	update_fpu_flags(env, flags);
97694c57 EI	264
	265	return fd.l;
	266	}
	267
64254eba	268	uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	269	{
	270	CPU_FloatU fd, fa, fb;
	271	int flags;
	272
	273	set_float_exception_flags(0, &env->fp_status);
	274	fa.l = a;
	275	fb.l = b;
	276	fd.f = float32_div(fb.f, fa.f, &env->fp_status);
	277	flags = get_float_exception_flags(&env->fp_status);
64254eba	278	update_fpu_flags(env, flags);
97694c57 EI	279
	280	return fd.l;
	281	}
	282
64254eba	283	uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
97694c57	284	{
ef9d48da EI	285	CPU_FloatU fa, fb;
	286	uint32_t r = 0;
	287
	288	fa.l = a;
	289	fb.l = b;
	290
	291	if (float32_is_signaling_nan(fa.f) \|\| float32_is_signaling_nan(fb.f)) {
64254eba	292	update_fpu_flags(env, float_flag_invalid);
ef9d48da EI	293	r = 1;
	294	}
	295
18569871	296	if (float32_is_quiet_nan(fa.f) \|\| float32_is_quiet_nan(fb.f)) {
ef9d48da EI	297	r = 1;
	298	}
	299
	300	return r;
97694c57 EI	301	}
97694c57 EI	302
64254eba	303	uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	304	{
	305	CPU_FloatU fa, fb;
	306	int r;
	307	int flags;
	308
	309	set_float_exception_flags(0, &env->fp_status);
	310	fa.l = a;
	311	fb.l = b;
	312	r = float32_lt(fb.f, fa.f, &env->fp_status);
	313	flags = get_float_exception_flags(&env->fp_status);
64254eba	314	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	315
	316	return r;
	317	}
	318
64254eba	319	uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	320	{
	321	CPU_FloatU fa, fb;
	322	int flags;
	323	int r;
	324
	325	set_float_exception_flags(0, &env->fp_status);
	326	fa.l = a;
	327	fb.l = b;
211315fb	328	r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	329	flags = get_float_exception_flags(&env->fp_status);
64254eba	330	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	331
	332	return r;
	333	}
	334
64254eba	335	uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	336	{
	337	CPU_FloatU fa, fb;
	338	int flags;
	339	int r;
	340
	341	fa.l = a;
	342	fb.l = b;
	343	set_float_exception_flags(0, &env->fp_status);
	344	r = float32_le(fa.f, fb.f, &env->fp_status);
	345	flags = get_float_exception_flags(&env->fp_status);
64254eba	346	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	347
	348
	349	return r;
	350	}
	351
64254eba	352	uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	353	{
	354	CPU_FloatU fa, fb;
	355	int flags, r;
	356
	357	fa.l = a;
	358	fb.l = b;
	359	set_float_exception_flags(0, &env->fp_status);
	360	r = float32_lt(fa.f, fb.f, &env->fp_status);
	361	flags = get_float_exception_flags(&env->fp_status);
64254eba	362	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	363	return r;
	364	}
	365
64254eba	366	uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	367	{
	368	CPU_FloatU fa, fb;
	369	int flags, r;
	370
	371	fa.l = a;
	372	fb.l = b;
	373	set_float_exception_flags(0, &env->fp_status);
211315fb	374	r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	375	flags = get_float_exception_flags(&env->fp_status);
64254eba	376	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	377
	378	return r;
	379	}
	380
64254eba	381	uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	382	{
	383	CPU_FloatU fa, fb;
	384	int flags, r;
	385
	386	fa.l = a;
	387	fb.l = b;
	388	set_float_exception_flags(0, &env->fp_status);
	389	r = !float32_lt(fa.f, fb.f, &env->fp_status);
	390	flags = get_float_exception_flags(&env->fp_status);
64254eba	391	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	392
	393	return r;
	394	}
	395
64254eba	396	uint32_t helper_flt(CPUMBState *env, uint32_t a)
97694c57 EI	397	{
	398	CPU_FloatU fd, fa;
	399
	400	fa.l = a;
	401	fd.f = int32_to_float32(fa.l, &env->fp_status);
	402	return fd.l;
	403	}
	404
64254eba	405	uint32_t helper_fint(CPUMBState *env, uint32_t a)
97694c57 EI	406	{
	407	CPU_FloatU fa;
	408	uint32_t r;
	409	int flags;
	410
	411	set_float_exception_flags(0, &env->fp_status);
	412	fa.l = a;
	413	r = float32_to_int32(fa.f, &env->fp_status);
	414	flags = get_float_exception_flags(&env->fp_status);
64254eba	415	update_fpu_flags(env, flags);
97694c57 EI	416
	417	return r;
	418	}
	419
64254eba	420	uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
97694c57 EI	421	{
	422	CPU_FloatU fd, fa;
	423	int flags;
	424
	425	set_float_exception_flags(0, &env->fp_status);
	426	fa.l = a;
	427	fd.l = float32_sqrt(fa.f, &env->fp_status);
	428	flags = get_float_exception_flags(&env->fp_status);
64254eba	429	update_fpu_flags(env, flags);
97694c57 EI	430
	431	return fd.l;
	432	}
	433
4acb54ba EI	434	uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
	435	{
	436	unsigned int i;
	437	uint32_t mask = 0xff000000;
	438
	439	for (i = 0; i < 4; i++) {
	440	if ((a & mask) == (b & mask))
	441	return i + 1;
	442	mask >>= 8;
	443	}
	444	return 0;
	445	}
	446
64254eba BS	447	void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
64254eba BS	448	uint32_t mask)
968a40f6	449	{
968a40f6	450	if (addr & mask) {
97f90cbf EI	451	qemu_log_mask(CPU_LOG_INT,
	452	"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
	453	addr, mask, wr, dr);
	454	env->sregs[SR_EAR] = addr;
968a40f6 EI	455	env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA \| (wr << 10) \
968a40f6 EI	456	\| (dr & 31) << 5;
3aa80988	457	if (mask == 3) {
968a40f6 EI	458	env->sregs[SR_ESR] \|= 1 << 11;
968a40f6 EI	459	}
97f90cbf EI	460	if (!(env->sregs[SR_MSR] & MSR_EE)) {
	461	return;
	462	}
64254eba	463	helper_raise_exception(env, EXCP_HW_EXCP);
968a40f6 EI	464	}
	465	}
	466
64254eba	467	void helper_stackprot(CPUMBState *env, uint32_t addr)
5818dee5 EI	468	{
5818dee5 EI	469	if (addr < env->slr \|\| addr > env->shr) {
1d512a65 PB	470	qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
1d512a65 PB	471	addr, env->slr, env->shr);
53432dc9 AF	472	env->sregs[SR_EAR] = addr;
	473	env->sregs[SR_ESR] = ESR_EC_STACKPROT;
	474	helper_raise_exception(env, EXCP_HW_EXCP);
5818dee5 EI	475	}
	476	}
	477
4acb54ba EI	478	#if !defined(CONFIG_USER_ONLY)
4acb54ba EI	479	/* Writes/reads to the MMU's special regs end up here. */
64254eba	480	uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
4acb54ba EI	481	{
	482	return mmu_read(env, rn);
	483	}
	484
64254eba	485	void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
4acb54ba EI	486	{
	487	mmu_write(env, rn, v);
	488	}
faed1c2a	489
c658b94f AF	490	void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
	491	bool is_write, bool is_exec, int is_asi,
	492	unsigned size)
faed1c2a	493	{
c658b94f AF	494	MicroBlazeCPU *cpu;
	495	CPUMBState *env;
	496
97f90cbf	497	qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
c658b94f AF	498	addr, is_write ? 1 : 0, is_exec ? 1 : 0);
	499	if (cs == NULL) {
	500	return;
	501	}
	502	cpu = MICROBLAZE_CPU(cs);
	503	env = &cpu->env;
	504	if (!(env->sregs[SR_MSR] & MSR_EE)) {
faed1c2a EI	505	return;
	506	}
	507
97f90cbf	508	env->sregs[SR_EAR] = addr;
faed1c2a	509	if (is_exec) {
97f90cbf	510	if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
faed1c2a	511	env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
64254eba	512	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	513	}
faed1c2a EI	514	} else {
97f90cbf	515	if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
faed1c2a	516	env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
64254eba	517	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	518	}
	519	}
	520	}
3c7b48b7	521	#endif