[mirror_qemu.git] / target-microblaze / op_helper.c

/*
 *  Microblaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/cpu_ldst.h"

#define D(x)

#if !defined(CONFIG_USER_ONLY)

/* Try to fill the TLB and return an exception if error. If retaddr is
 * NULL, it means that the function was called in C code (i.e. not
 * from generated code or from helper.c)
 */
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    int ret;

    ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            cpu_restore_state(cs, retaddr);
        }
        cpu_loop_exit(cs);
    }
}
#endif

void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
             id, data,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
}

uint32_t helper_get(uint32_t id, uint32_t ctrl)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
             id,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
    return 0xdead0000 | id;
}

void helper_raise_exception(CPUMBState *env, uint32_t index)
{
    CPUState *cs = CPU(mb_env_get_cpu(env));

    cs->exception_index = index;
    cpu_loop_exit(cs);
}

void helper_debug(CPUMBState *env)
{
    int i;

    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
             env->debug, env->imm, env->iflags);
    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
             env->btaken, env->btarget,
             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_EIP),
             (env->sregs[SR_MSR] & MSR_IE));
    for (i = 0; i < 32; i++) {
        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
        if ((i + 1) % 4 == 0)
            qemu_log("\n");
    }
    qemu_log("\n\n");
}

static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
{
    uint32_t cout = 0;

    if ((b == ~0) && cin)
        cout = 1;
    else if ((~0 - a) < (b + cin))
        cout = 1;
    return cout;
}

uint32_t helper_cmp(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (b & 0x80000000);
    return t;
}

uint32_t helper_cmpu(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (a & 0x80000000);
    return t;
}

uint32_t helper_clz(uint32_t t0)
{
    return clz32(t0);
}

uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
{
    return compute_carry(a, b, cf);
}

static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (b == 0) {
        env->sregs[SR_MSR] |= MSR_DZ;

        if ((env->sregs[SR_MSR] & MSR_EE)
            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
        return 0;
    }
    env->sregs[SR_MSR] &= ~MSR_DZ;
    return 1;
}

uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return (int32_t)a / (int32_t)b;
}

uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return a / b;
}

/* raise FPU exception.  */
static void raise_fpu_exception(CPUMBState *env)
{
    env->sregs[SR_ESR] = ESR_EC_FPU;
    helper_raise_exception(env, EXCP_HW_EXCP);
}

static void update_fpu_flags(CPUMBState *env, int flags)
{
    int raise = 0;

    if (flags & float_flag_invalid) {
        env->sregs[SR_FSR] |= FSR_IO;
        raise = 1;
    }
    if (flags & float_flag_divbyzero) {
        env->sregs[SR_FSR] |= FSR_DZ;
        raise = 1;
    }
    if (flags & float_flag_overflow) {
        env->sregs[SR_FSR] |= FSR_OF;
        raise = 1;
    }
    if (flags & float_flag_underflow) {
        env->sregs[SR_FSR] |= FSR_UF;
        raise = 1;
    }
    if (raise
        && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
        && (env->sregs[SR_MSR] & MSR_EE)) {
        raise_fpu_exception(env);
    }
}

uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_add(fa.f, fb.f, &env->fp_status);

    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_div(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    uint32_t r = 0;

    fa.l = a;
    fb.l = b;

    if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
        update_fpu_flags(env, float_flag_invalid);
        r = 1;
    }

    if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
        r = 1;
    }

    return r;
}

uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_lt(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_le(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);


    return r;
}

uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);
    return r;
}

uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_flt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;

    fa.l = a;
    fd.f = int32_to_float32(fa.l, &env->fp_status);
    return fd.l;
}

uint32_t helper_fint(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fa;
    uint32_t r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    r = float32_to_int32(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return r;
}

uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fd.l = float32_sqrt(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
{
    unsigned int i;
    uint32_t mask = 0xff000000;

    for (i = 0; i < 4; i++) {
        if ((a & mask) == (b & mask))
            return i + 1;
        mask >>= 8;
    }
    return 0;
}

void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
                     uint32_t mask)
{
    if (addr & mask) {
            qemu_log_mask(CPU_LOG_INT,
                          "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
                          addr, mask, wr, dr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                 | (dr & 31) << 5;
            if (mask == 3) {
                env->sregs[SR_ESR] |= 1 << 11;
            }
            if (!(env->sregs[SR_MSR] & MSR_EE)) {
                return;
            }
            helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

void helper_stackprot(CPUMBState *env, uint32_t addr)
{
    if (addr < env->slr || addr > env->shr) {
        qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
                      addr, env->slr, env->shr);
        env->sregs[SR_EAR] = addr;
        env->sregs[SR_ESR] = ESR_EC_STACKPROT;
        helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here.  */
uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
{
    return mmu_read(env, rn);
}

void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
    mmu_write(env, rn, v);
}

void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
                              bool is_write, bool is_exec, int is_asi,
                              unsigned size)
{
    MicroBlazeCPU *cpu;
    CPUMBState *env;

    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
             addr, is_write ? 1 : 0, is_exec ? 1 : 0);
    if (cs == NULL) {
        return;
    }
    cpu = MICROBLAZE_CPU(cs);
    env = &cpu->env;
    if (!(env->sregs[SR_MSR] & MSR_EE)) {
        return;
    }

    env->sregs[SR_EAR] = addr;
    if (is_exec) {
        if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    } else {
        if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    }
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* Microblaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	19	*/
4acb54ba EI	20
8fd9dece	21	#include "qemu/osdep.h"
3e457172	22	#include "cpu.h"
2ef6175a	23	#include "exec/helper-proto.h"
1de7afc9	24	#include "qemu/host-utils.h"
f08b6170	25	#include "exec/cpu_ldst.h"
4acb54ba EI	26
	27	#define D(x)
	28
	29	#if !defined(CONFIG_USER_ONLY)
3e457172	30
4acb54ba	31	/* Try to fill the TLB and return an exception if error. If retaddr is
d5a11fef AF	32	* NULL, it means that the function was called in C code (i.e. not
	33	* from generated code or from helper.c)
	34	*/
	35	void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
20503968	36	uintptr_t retaddr)
4acb54ba	37	{
4acb54ba EI	38	int ret;
4acb54ba EI	39
d5a11fef	40	ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
4acb54ba EI	41	if (unlikely(ret)) {
	42	if (retaddr) {
	43	/* now we have a real cpu fault */
3f38f309	44	cpu_restore_state(cs, retaddr);
4acb54ba	45	}
5638d180	46	cpu_loop_exit(cs);
4acb54ba	47	}
4acb54ba EI	48	}
	49	#endif
	50
6d76d23e EI	51	void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
	52	{
	53	int test = ctrl & STREAM_TEST;
	54	int atomic = ctrl & STREAM_ATOMIC;
	55	int control = ctrl & STREAM_CONTROL;
	56	int nonblock = ctrl & STREAM_NONBLOCK;
	57	int exception = ctrl & STREAM_EXCEPTION;
	58
1d512a65	59	qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
6d76d23e EI	60	id, data,
	61	test ? "t" : "",
	62	nonblock ? "n" : "",
	63	exception ? "e" : "",
	64	control ? "c" : "",
	65	atomic ? "a" : "");
	66	}
	67
	68	uint32_t helper_get(uint32_t id, uint32_t ctrl)
	69	{
	70	int test = ctrl & STREAM_TEST;
	71	int atomic = ctrl & STREAM_ATOMIC;
	72	int control = ctrl & STREAM_CONTROL;
	73	int nonblock = ctrl & STREAM_NONBLOCK;
	74	int exception = ctrl & STREAM_EXCEPTION;
	75
1d512a65	76	qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
6d76d23e EI	77	id,
	78	test ? "t" : "",
	79	nonblock ? "n" : "",
	80	exception ? "e" : "",
	81	control ? "c" : "",
	82	atomic ? "a" : "");
	83	return 0xdead0000 \| id;
	84	}
	85
64254eba	86	void helper_raise_exception(CPUMBState *env, uint32_t index)
4acb54ba	87	{
27103424 AF	88	CPUState *cs = CPU(mb_env_get_cpu(env));
	89
	90	cs->exception_index = index;
5638d180	91	cpu_loop_exit(cs);
4acb54ba EI	92	}
4acb54ba EI	93
64254eba	94	void helper_debug(CPUMBState *env)
4acb54ba EI	95	{
	96	int i;
	97
	98	qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
4c24aa0a MS	99	qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
4c24aa0a MS	100	env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
17c52a43 EI	101	env->debug, env->imm, env->iflags);
	102	qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
	103	env->btaken, env->btarget,
	104	(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
	105	(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
	106	(env->sregs[SR_MSR] & MSR_EIP),
	107	(env->sregs[SR_MSR] & MSR_IE));
4acb54ba EI	108	for (i = 0; i < 32; i++) {
	109	qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
	110	if ((i + 1) % 4 == 0)
	111	qemu_log("\n");
	112	}
	113	qemu_log("\n\n");
	114	}
	115
	116	static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
	117	{
	118	uint32_t cout = 0;
	119
	120	if ((b == ~0) && cin)
	121	cout = 1;
	122	else if ((~0 - a) < (b + cin))
	123	cout = 1;
	124	return cout;
	125	}
	126
	127	uint32_t helper_cmp(uint32_t a, uint32_t b)
	128	{
	129	uint32_t t;
	130
	131	t = b + ~a + 1;
	132	if ((b & 0x80000000) ^ (a & 0x80000000))
	133	t = (t & 0x7fffffff) \| (b & 0x80000000);
	134	return t;
	135	}
	136
	137	uint32_t helper_cmpu(uint32_t a, uint32_t b)
	138	{
	139	uint32_t t;
	140
	141	t = b + ~a + 1;
	142	if ((b & 0x80000000) ^ (a & 0x80000000))
	143	t = (t & 0x7fffffff) \| (a & 0x80000000);
	144	return t;
	145	}
	146
48b5e96f EI	147	uint32_t helper_clz(uint32_t t0)
	148	{
	149	return clz32(t0);
	150	}
	151
5d0bb823	152	uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
4acb54ba	153	{
738c8b01	154	return compute_carry(a, b, cf);
4acb54ba EI	155	}
4acb54ba EI	156
64254eba	157	static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba EI	158	{
	159	if (b == 0) {
	160	env->sregs[SR_MSR] \|= MSR_DZ;
821ebb33 EI	161
	162	if ((env->sregs[SR_MSR] & MSR_EE)
	163	&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
	164	env->sregs[SR_ESR] = ESR_EC_DIVZERO;
64254eba	165	helper_raise_exception(env, EXCP_HW_EXCP);
821ebb33	166	}
4acb54ba EI	167	return 0;
	168	}
	169	env->sregs[SR_MSR] &= ~MSR_DZ;
	170	return 1;
	171	}
	172
64254eba	173	uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	174	{
64254eba	175	if (!div_prepare(env, a, b)) {
4acb54ba	176	return 0;
64254eba	177	}
4acb54ba EI	178	return (int32_t)a / (int32_t)b;
	179	}
	180
64254eba	181	uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	182	{
64254eba	183	if (!div_prepare(env, a, b)) {
4acb54ba	184	return 0;
64254eba	185	}
4acb54ba EI	186	return a / b;
	187	}
	188
97694c57	189	/* raise FPU exception. */
64254eba	190	static void raise_fpu_exception(CPUMBState *env)
97694c57 EI	191	{
97694c57 EI	192	env->sregs[SR_ESR] = ESR_EC_FPU;
64254eba	193	helper_raise_exception(env, EXCP_HW_EXCP);
97694c57 EI	194	}
97694c57 EI	195
64254eba	196	static void update_fpu_flags(CPUMBState *env, int flags)
97694c57 EI	197	{
	198	int raise = 0;
	199
	200	if (flags & float_flag_invalid) {
	201	env->sregs[SR_FSR] \|= FSR_IO;
	202	raise = 1;
	203	}
	204	if (flags & float_flag_divbyzero) {
	205	env->sregs[SR_FSR] \|= FSR_DZ;
	206	raise = 1;
	207	}
	208	if (flags & float_flag_overflow) {
	209	env->sregs[SR_FSR] \|= FSR_OF;
	210	raise = 1;
	211	}
	212	if (flags & float_flag_underflow) {
	213	env->sregs[SR_FSR] \|= FSR_UF;
	214	raise = 1;
	215	}
	216	if (raise
	217	&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
	218	&& (env->sregs[SR_MSR] & MSR_EE)) {
64254eba	219	raise_fpu_exception(env);
97694c57 EI	220	}
	221	}
	222
64254eba	223	uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	224	{
	225	CPU_FloatU fd, fa, fb;
	226	int flags;
	227
	228	set_float_exception_flags(0, &env->fp_status);
	229	fa.l = a;
	230	fb.l = b;
	231	fd.f = float32_add(fa.f, fb.f, &env->fp_status);
	232
	233	flags = get_float_exception_flags(&env->fp_status);
64254eba	234	update_fpu_flags(env, flags);
97694c57 EI	235	return fd.l;
	236	}
	237
64254eba	238	uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	239	{
	240	CPU_FloatU fd, fa, fb;
	241	int flags;
	242
	243	set_float_exception_flags(0, &env->fp_status);
	244	fa.l = a;
	245	fb.l = b;
	246	fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
	247	flags = get_float_exception_flags(&env->fp_status);
64254eba	248	update_fpu_flags(env, flags);
97694c57 EI	249	return fd.l;
	250	}
	251
64254eba	252	uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	253	{
	254	CPU_FloatU fd, fa, fb;
	255	int flags;
	256
	257	set_float_exception_flags(0, &env->fp_status);
	258	fa.l = a;
	259	fb.l = b;
	260	fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
	261	flags = get_float_exception_flags(&env->fp_status);
64254eba	262	update_fpu_flags(env, flags);
97694c57 EI	263
	264	return fd.l;
	265	}
	266
64254eba	267	uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	268	{
	269	CPU_FloatU fd, fa, fb;
	270	int flags;
	271
	272	set_float_exception_flags(0, &env->fp_status);
	273	fa.l = a;
	274	fb.l = b;
	275	fd.f = float32_div(fb.f, fa.f, &env->fp_status);
	276	flags = get_float_exception_flags(&env->fp_status);
64254eba	277	update_fpu_flags(env, flags);
97694c57 EI	278
	279	return fd.l;
	280	}
	281
64254eba	282	uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
97694c57	283	{
ef9d48da EI	284	CPU_FloatU fa, fb;
	285	uint32_t r = 0;
	286
	287	fa.l = a;
	288	fb.l = b;
	289
	290	if (float32_is_signaling_nan(fa.f) \|\| float32_is_signaling_nan(fb.f)) {
64254eba	291	update_fpu_flags(env, float_flag_invalid);
ef9d48da EI	292	r = 1;
	293	}
	294
18569871	295	if (float32_is_quiet_nan(fa.f) \|\| float32_is_quiet_nan(fb.f)) {
ef9d48da EI	296	r = 1;
	297	}
	298
	299	return r;
97694c57 EI	300	}
97694c57 EI	301
64254eba	302	uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	303	{
	304	CPU_FloatU fa, fb;
	305	int r;
	306	int flags;
	307
	308	set_float_exception_flags(0, &env->fp_status);
	309	fa.l = a;
	310	fb.l = b;
	311	r = float32_lt(fb.f, fa.f, &env->fp_status);
	312	flags = get_float_exception_flags(&env->fp_status);
64254eba	313	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	314
	315	return r;
	316	}
	317
64254eba	318	uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	319	{
	320	CPU_FloatU fa, fb;
	321	int flags;
	322	int r;
	323
	324	set_float_exception_flags(0, &env->fp_status);
	325	fa.l = a;
	326	fb.l = b;
211315fb	327	r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	328	flags = get_float_exception_flags(&env->fp_status);
64254eba	329	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	330
	331	return r;
	332	}
	333
64254eba	334	uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	335	{
	336	CPU_FloatU fa, fb;
	337	int flags;
	338	int r;
	339
	340	fa.l = a;
	341	fb.l = b;
	342	set_float_exception_flags(0, &env->fp_status);
	343	r = float32_le(fa.f, fb.f, &env->fp_status);
	344	flags = get_float_exception_flags(&env->fp_status);
64254eba	345	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	346
	347
	348	return r;
	349	}
	350
64254eba	351	uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	352	{
	353	CPU_FloatU fa, fb;
	354	int flags, r;
	355
	356	fa.l = a;
	357	fb.l = b;
	358	set_float_exception_flags(0, &env->fp_status);
	359	r = float32_lt(fa.f, fb.f, &env->fp_status);
	360	flags = get_float_exception_flags(&env->fp_status);
64254eba	361	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	362	return r;
	363	}
	364
64254eba	365	uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	366	{
	367	CPU_FloatU fa, fb;
	368	int flags, r;
	369
	370	fa.l = a;
	371	fb.l = b;
	372	set_float_exception_flags(0, &env->fp_status);
211315fb	373	r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	374	flags = get_float_exception_flags(&env->fp_status);
64254eba	375	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	376
	377	return r;
	378	}
	379
64254eba	380	uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	381	{
	382	CPU_FloatU fa, fb;
	383	int flags, r;
	384
	385	fa.l = a;
	386	fb.l = b;
	387	set_float_exception_flags(0, &env->fp_status);
	388	r = !float32_lt(fa.f, fb.f, &env->fp_status);
	389	flags = get_float_exception_flags(&env->fp_status);
64254eba	390	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	391
	392	return r;
	393	}
	394
64254eba	395	uint32_t helper_flt(CPUMBState *env, uint32_t a)
97694c57 EI	396	{
	397	CPU_FloatU fd, fa;
	398
	399	fa.l = a;
	400	fd.f = int32_to_float32(fa.l, &env->fp_status);
	401	return fd.l;
	402	}
	403
64254eba	404	uint32_t helper_fint(CPUMBState *env, uint32_t a)
97694c57 EI	405	{
	406	CPU_FloatU fa;
	407	uint32_t r;
	408	int flags;
	409
	410	set_float_exception_flags(0, &env->fp_status);
	411	fa.l = a;
	412	r = float32_to_int32(fa.f, &env->fp_status);
	413	flags = get_float_exception_flags(&env->fp_status);
64254eba	414	update_fpu_flags(env, flags);
97694c57 EI	415
	416	return r;
	417	}
	418
64254eba	419	uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
97694c57 EI	420	{
	421	CPU_FloatU fd, fa;
	422	int flags;
	423
	424	set_float_exception_flags(0, &env->fp_status);
	425	fa.l = a;
	426	fd.l = float32_sqrt(fa.f, &env->fp_status);
	427	flags = get_float_exception_flags(&env->fp_status);
64254eba	428	update_fpu_flags(env, flags);
97694c57 EI	429
	430	return fd.l;
	431	}
	432
4acb54ba EI	433	uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
	434	{
	435	unsigned int i;
	436	uint32_t mask = 0xff000000;
	437
	438	for (i = 0; i < 4; i++) {
	439	if ((a & mask) == (b & mask))
	440	return i + 1;
	441	mask >>= 8;
	442	}
	443	return 0;
	444	}
	445
64254eba BS	446	void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
64254eba BS	447	uint32_t mask)
968a40f6	448	{
968a40f6	449	if (addr & mask) {
97f90cbf EI	450	qemu_log_mask(CPU_LOG_INT,
	451	"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
	452	addr, mask, wr, dr);
	453	env->sregs[SR_EAR] = addr;
968a40f6 EI	454	env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA \| (wr << 10) \
968a40f6 EI	455	\| (dr & 31) << 5;
3aa80988	456	if (mask == 3) {
968a40f6 EI	457	env->sregs[SR_ESR] \|= 1 << 11;
968a40f6 EI	458	}
97f90cbf EI	459	if (!(env->sregs[SR_MSR] & MSR_EE)) {
	460	return;
	461	}
64254eba	462	helper_raise_exception(env, EXCP_HW_EXCP);
968a40f6 EI	463	}
	464	}
	465
64254eba	466	void helper_stackprot(CPUMBState *env, uint32_t addr)
5818dee5 EI	467	{
5818dee5 EI	468	if (addr < env->slr \|\| addr > env->shr) {
1d512a65 PB	469	qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
1d512a65 PB	470	addr, env->slr, env->shr);
53432dc9 AF	471	env->sregs[SR_EAR] = addr;
	472	env->sregs[SR_ESR] = ESR_EC_STACKPROT;
	473	helper_raise_exception(env, EXCP_HW_EXCP);
5818dee5 EI	474	}
	475	}
	476
4acb54ba EI	477	#if !defined(CONFIG_USER_ONLY)
4acb54ba EI	478	/* Writes/reads to the MMU's special regs end up here. */
64254eba	479	uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
4acb54ba EI	480	{
	481	return mmu_read(env, rn);
	482	}
	483
64254eba	484	void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
4acb54ba EI	485	{
	486	mmu_write(env, rn, v);
	487	}
faed1c2a	488
c658b94f AF	489	void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
	490	bool is_write, bool is_exec, int is_asi,
	491	unsigned size)
faed1c2a	492	{
c658b94f AF	493	MicroBlazeCPU *cpu;
	494	CPUMBState *env;
	495
97f90cbf	496	qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
c658b94f AF	497	addr, is_write ? 1 : 0, is_exec ? 1 : 0);
	498	if (cs == NULL) {
	499	return;
	500	}
	501	cpu = MICROBLAZE_CPU(cs);
	502	env = &cpu->env;
	503	if (!(env->sregs[SR_MSR] & MSR_EE)) {
faed1c2a EI	504	return;
	505	}
	506
97f90cbf	507	env->sregs[SR_EAR] = addr;
faed1c2a	508	if (is_exec) {
97f90cbf	509	if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
faed1c2a	510	env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
64254eba	511	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	512	}
faed1c2a EI	513	} else {
97f90cbf	514	if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
faed1c2a	515	env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
64254eba	516	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	517	}
	518	}
	519	}
3c7b48b7	520	#endif