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Commit | Line | Data |
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4acb54ba EI |
1 | /* |
2 | * Microblaze helper routines. | |
3 | * | |
4 | * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>. | |
dadc1064 | 5 | * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. |
4acb54ba EI |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
4acb54ba EI |
19 | */ |
20 | ||
8fd9dece | 21 | #include "qemu/osdep.h" |
3e457172 | 22 | #include "cpu.h" |
2ef6175a | 23 | #include "exec/helper-proto.h" |
1de7afc9 | 24 | #include "qemu/host-utils.h" |
63c91552 | 25 | #include "exec/exec-all.h" |
f08b6170 | 26 | #include "exec/cpu_ldst.h" |
4acb54ba EI |
27 | |
28 | #define D(x) | |
29 | ||
30 | #if !defined(CONFIG_USER_ONLY) | |
3e457172 | 31 | |
4acb54ba | 32 | /* Try to fill the TLB and return an exception if error. If retaddr is |
d5a11fef AF |
33 | * NULL, it means that the function was called in C code (i.e. not |
34 | * from generated code or from helper.c) | |
35 | */ | |
b35399bb SS |
36 | void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, |
37 | int mmu_idx, uintptr_t retaddr) | |
4acb54ba | 38 | { |
4acb54ba EI |
39 | int ret; |
40 | ||
b35399bb | 41 | ret = mb_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); |
4acb54ba EI |
42 | if (unlikely(ret)) { |
43 | if (retaddr) { | |
44 | /* now we have a real cpu fault */ | |
3f38f309 | 45 | cpu_restore_state(cs, retaddr); |
4acb54ba | 46 | } |
5638d180 | 47 | cpu_loop_exit(cs); |
4acb54ba | 48 | } |
4acb54ba EI |
49 | } |
50 | #endif | |
51 | ||
6d76d23e EI |
52 | void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) |
53 | { | |
54 | int test = ctrl & STREAM_TEST; | |
55 | int atomic = ctrl & STREAM_ATOMIC; | |
56 | int control = ctrl & STREAM_CONTROL; | |
57 | int nonblock = ctrl & STREAM_NONBLOCK; | |
58 | int exception = ctrl & STREAM_EXCEPTION; | |
59 | ||
1d512a65 | 60 | qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n", |
6d76d23e EI |
61 | id, data, |
62 | test ? "t" : "", | |
63 | nonblock ? "n" : "", | |
64 | exception ? "e" : "", | |
65 | control ? "c" : "", | |
66 | atomic ? "a" : ""); | |
67 | } | |
68 | ||
69 | uint32_t helper_get(uint32_t id, uint32_t ctrl) | |
70 | { | |
71 | int test = ctrl & STREAM_TEST; | |
72 | int atomic = ctrl & STREAM_ATOMIC; | |
73 | int control = ctrl & STREAM_CONTROL; | |
74 | int nonblock = ctrl & STREAM_NONBLOCK; | |
75 | int exception = ctrl & STREAM_EXCEPTION; | |
76 | ||
1d512a65 | 77 | qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n", |
6d76d23e EI |
78 | id, |
79 | test ? "t" : "", | |
80 | nonblock ? "n" : "", | |
81 | exception ? "e" : "", | |
82 | control ? "c" : "", | |
83 | atomic ? "a" : ""); | |
84 | return 0xdead0000 | id; | |
85 | } | |
86 | ||
64254eba | 87 | void helper_raise_exception(CPUMBState *env, uint32_t index) |
4acb54ba | 88 | { |
27103424 AF |
89 | CPUState *cs = CPU(mb_env_get_cpu(env)); |
90 | ||
91 | cs->exception_index = index; | |
5638d180 | 92 | cpu_loop_exit(cs); |
4acb54ba EI |
93 | } |
94 | ||
64254eba | 95 | void helper_debug(CPUMBState *env) |
4acb54ba EI |
96 | { |
97 | int i; | |
98 | ||
99 | qemu_log("PC=%8.8x\n", env->sregs[SR_PC]); | |
4c24aa0a MS |
100 | qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n", |
101 | env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], | |
17c52a43 EI |
102 | env->debug, env->imm, env->iflags); |
103 | qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", | |
104 | env->btaken, env->btarget, | |
105 | (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", | |
106 | (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", | |
107 | (env->sregs[SR_MSR] & MSR_EIP), | |
108 | (env->sregs[SR_MSR] & MSR_IE)); | |
4acb54ba EI |
109 | for (i = 0; i < 32; i++) { |
110 | qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); | |
111 | if ((i + 1) % 4 == 0) | |
112 | qemu_log("\n"); | |
113 | } | |
114 | qemu_log("\n\n"); | |
115 | } | |
116 | ||
117 | static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) | |
118 | { | |
119 | uint32_t cout = 0; | |
120 | ||
121 | if ((b == ~0) && cin) | |
122 | cout = 1; | |
123 | else if ((~0 - a) < (b + cin)) | |
124 | cout = 1; | |
125 | return cout; | |
126 | } | |
127 | ||
128 | uint32_t helper_cmp(uint32_t a, uint32_t b) | |
129 | { | |
130 | uint32_t t; | |
131 | ||
132 | t = b + ~a + 1; | |
133 | if ((b & 0x80000000) ^ (a & 0x80000000)) | |
134 | t = (t & 0x7fffffff) | (b & 0x80000000); | |
135 | return t; | |
136 | } | |
137 | ||
138 | uint32_t helper_cmpu(uint32_t a, uint32_t b) | |
139 | { | |
140 | uint32_t t; | |
141 | ||
142 | t = b + ~a + 1; | |
143 | if ((b & 0x80000000) ^ (a & 0x80000000)) | |
144 | t = (t & 0x7fffffff) | (a & 0x80000000); | |
145 | return t; | |
146 | } | |
147 | ||
48b5e96f EI |
148 | uint32_t helper_clz(uint32_t t0) |
149 | { | |
150 | return clz32(t0); | |
151 | } | |
152 | ||
5d0bb823 | 153 | uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) |
4acb54ba | 154 | { |
738c8b01 | 155 | return compute_carry(a, b, cf); |
4acb54ba EI |
156 | } |
157 | ||
64254eba | 158 | static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) |
4acb54ba EI |
159 | { |
160 | if (b == 0) { | |
161 | env->sregs[SR_MSR] |= MSR_DZ; | |
821ebb33 EI |
162 | |
163 | if ((env->sregs[SR_MSR] & MSR_EE) | |
164 | && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) { | |
165 | env->sregs[SR_ESR] = ESR_EC_DIVZERO; | |
64254eba | 166 | helper_raise_exception(env, EXCP_HW_EXCP); |
821ebb33 | 167 | } |
4acb54ba EI |
168 | return 0; |
169 | } | |
170 | env->sregs[SR_MSR] &= ~MSR_DZ; | |
171 | return 1; | |
172 | } | |
173 | ||
64254eba | 174 | uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) |
4acb54ba | 175 | { |
64254eba | 176 | if (!div_prepare(env, a, b)) { |
4acb54ba | 177 | return 0; |
64254eba | 178 | } |
4acb54ba EI |
179 | return (int32_t)a / (int32_t)b; |
180 | } | |
181 | ||
64254eba | 182 | uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) |
4acb54ba | 183 | { |
64254eba | 184 | if (!div_prepare(env, a, b)) { |
4acb54ba | 185 | return 0; |
64254eba | 186 | } |
4acb54ba EI |
187 | return a / b; |
188 | } | |
189 | ||
97694c57 | 190 | /* raise FPU exception. */ |
64254eba | 191 | static void raise_fpu_exception(CPUMBState *env) |
97694c57 EI |
192 | { |
193 | env->sregs[SR_ESR] = ESR_EC_FPU; | |
64254eba | 194 | helper_raise_exception(env, EXCP_HW_EXCP); |
97694c57 EI |
195 | } |
196 | ||
64254eba | 197 | static void update_fpu_flags(CPUMBState *env, int flags) |
97694c57 EI |
198 | { |
199 | int raise = 0; | |
200 | ||
201 | if (flags & float_flag_invalid) { | |
202 | env->sregs[SR_FSR] |= FSR_IO; | |
203 | raise = 1; | |
204 | } | |
205 | if (flags & float_flag_divbyzero) { | |
206 | env->sregs[SR_FSR] |= FSR_DZ; | |
207 | raise = 1; | |
208 | } | |
209 | if (flags & float_flag_overflow) { | |
210 | env->sregs[SR_FSR] |= FSR_OF; | |
211 | raise = 1; | |
212 | } | |
213 | if (flags & float_flag_underflow) { | |
214 | env->sregs[SR_FSR] |= FSR_UF; | |
215 | raise = 1; | |
216 | } | |
217 | if (raise | |
218 | && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) | |
219 | && (env->sregs[SR_MSR] & MSR_EE)) { | |
64254eba | 220 | raise_fpu_exception(env); |
97694c57 EI |
221 | } |
222 | } | |
223 | ||
64254eba | 224 | uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
225 | { |
226 | CPU_FloatU fd, fa, fb; | |
227 | int flags; | |
228 | ||
229 | set_float_exception_flags(0, &env->fp_status); | |
230 | fa.l = a; | |
231 | fb.l = b; | |
232 | fd.f = float32_add(fa.f, fb.f, &env->fp_status); | |
233 | ||
234 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 235 | update_fpu_flags(env, flags); |
97694c57 EI |
236 | return fd.l; |
237 | } | |
238 | ||
64254eba | 239 | uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
240 | { |
241 | CPU_FloatU fd, fa, fb; | |
242 | int flags; | |
243 | ||
244 | set_float_exception_flags(0, &env->fp_status); | |
245 | fa.l = a; | |
246 | fb.l = b; | |
247 | fd.f = float32_sub(fb.f, fa.f, &env->fp_status); | |
248 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 249 | update_fpu_flags(env, flags); |
97694c57 EI |
250 | return fd.l; |
251 | } | |
252 | ||
64254eba | 253 | uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
254 | { |
255 | CPU_FloatU fd, fa, fb; | |
256 | int flags; | |
257 | ||
258 | set_float_exception_flags(0, &env->fp_status); | |
259 | fa.l = a; | |
260 | fb.l = b; | |
261 | fd.f = float32_mul(fa.f, fb.f, &env->fp_status); | |
262 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 263 | update_fpu_flags(env, flags); |
97694c57 EI |
264 | |
265 | return fd.l; | |
266 | } | |
267 | ||
64254eba | 268 | uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
269 | { |
270 | CPU_FloatU fd, fa, fb; | |
271 | int flags; | |
272 | ||
273 | set_float_exception_flags(0, &env->fp_status); | |
274 | fa.l = a; | |
275 | fb.l = b; | |
276 | fd.f = float32_div(fb.f, fa.f, &env->fp_status); | |
277 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 278 | update_fpu_flags(env, flags); |
97694c57 EI |
279 | |
280 | return fd.l; | |
281 | } | |
282 | ||
64254eba | 283 | uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 | 284 | { |
ef9d48da EI |
285 | CPU_FloatU fa, fb; |
286 | uint32_t r = 0; | |
287 | ||
288 | fa.l = a; | |
289 | fb.l = b; | |
290 | ||
af39bc8c AM |
291 | if (float32_is_signaling_nan(fa.f, &env->fp_status) || |
292 | float32_is_signaling_nan(fb.f, &env->fp_status)) { | |
64254eba | 293 | update_fpu_flags(env, float_flag_invalid); |
ef9d48da EI |
294 | r = 1; |
295 | } | |
296 | ||
af39bc8c AM |
297 | if (float32_is_quiet_nan(fa.f, &env->fp_status) || |
298 | float32_is_quiet_nan(fb.f, &env->fp_status)) { | |
ef9d48da EI |
299 | r = 1; |
300 | } | |
301 | ||
302 | return r; | |
97694c57 EI |
303 | } |
304 | ||
64254eba | 305 | uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
306 | { |
307 | CPU_FloatU fa, fb; | |
308 | int r; | |
309 | int flags; | |
310 | ||
311 | set_float_exception_flags(0, &env->fp_status); | |
312 | fa.l = a; | |
313 | fb.l = b; | |
314 | r = float32_lt(fb.f, fa.f, &env->fp_status); | |
315 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 316 | update_fpu_flags(env, flags & float_flag_invalid); |
97694c57 EI |
317 | |
318 | return r; | |
319 | } | |
320 | ||
64254eba | 321 | uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
322 | { |
323 | CPU_FloatU fa, fb; | |
324 | int flags; | |
325 | int r; | |
326 | ||
327 | set_float_exception_flags(0, &env->fp_status); | |
328 | fa.l = a; | |
329 | fb.l = b; | |
211315fb | 330 | r = float32_eq_quiet(fa.f, fb.f, &env->fp_status); |
97694c57 | 331 | flags = get_float_exception_flags(&env->fp_status); |
64254eba | 332 | update_fpu_flags(env, flags & float_flag_invalid); |
97694c57 EI |
333 | |
334 | return r; | |
335 | } | |
336 | ||
64254eba | 337 | uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
338 | { |
339 | CPU_FloatU fa, fb; | |
340 | int flags; | |
341 | int r; | |
342 | ||
343 | fa.l = a; | |
344 | fb.l = b; | |
345 | set_float_exception_flags(0, &env->fp_status); | |
346 | r = float32_le(fa.f, fb.f, &env->fp_status); | |
347 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 348 | update_fpu_flags(env, flags & float_flag_invalid); |
97694c57 EI |
349 | |
350 | ||
351 | return r; | |
352 | } | |
353 | ||
64254eba | 354 | uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
355 | { |
356 | CPU_FloatU fa, fb; | |
357 | int flags, r; | |
358 | ||
359 | fa.l = a; | |
360 | fb.l = b; | |
361 | set_float_exception_flags(0, &env->fp_status); | |
362 | r = float32_lt(fa.f, fb.f, &env->fp_status); | |
363 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 364 | update_fpu_flags(env, flags & float_flag_invalid); |
97694c57 EI |
365 | return r; |
366 | } | |
367 | ||
64254eba | 368 | uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
369 | { |
370 | CPU_FloatU fa, fb; | |
371 | int flags, r; | |
372 | ||
373 | fa.l = a; | |
374 | fb.l = b; | |
375 | set_float_exception_flags(0, &env->fp_status); | |
211315fb | 376 | r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status); |
97694c57 | 377 | flags = get_float_exception_flags(&env->fp_status); |
64254eba | 378 | update_fpu_flags(env, flags & float_flag_invalid); |
97694c57 EI |
379 | |
380 | return r; | |
381 | } | |
382 | ||
64254eba | 383 | uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) |
97694c57 EI |
384 | { |
385 | CPU_FloatU fa, fb; | |
386 | int flags, r; | |
387 | ||
388 | fa.l = a; | |
389 | fb.l = b; | |
390 | set_float_exception_flags(0, &env->fp_status); | |
391 | r = !float32_lt(fa.f, fb.f, &env->fp_status); | |
392 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 393 | update_fpu_flags(env, flags & float_flag_invalid); |
97694c57 EI |
394 | |
395 | return r; | |
396 | } | |
397 | ||
64254eba | 398 | uint32_t helper_flt(CPUMBState *env, uint32_t a) |
97694c57 EI |
399 | { |
400 | CPU_FloatU fd, fa; | |
401 | ||
402 | fa.l = a; | |
403 | fd.f = int32_to_float32(fa.l, &env->fp_status); | |
404 | return fd.l; | |
405 | } | |
406 | ||
64254eba | 407 | uint32_t helper_fint(CPUMBState *env, uint32_t a) |
97694c57 EI |
408 | { |
409 | CPU_FloatU fa; | |
410 | uint32_t r; | |
411 | int flags; | |
412 | ||
413 | set_float_exception_flags(0, &env->fp_status); | |
414 | fa.l = a; | |
415 | r = float32_to_int32(fa.f, &env->fp_status); | |
416 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 417 | update_fpu_flags(env, flags); |
97694c57 EI |
418 | |
419 | return r; | |
420 | } | |
421 | ||
64254eba | 422 | uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) |
97694c57 EI |
423 | { |
424 | CPU_FloatU fd, fa; | |
425 | int flags; | |
426 | ||
427 | set_float_exception_flags(0, &env->fp_status); | |
428 | fa.l = a; | |
429 | fd.l = float32_sqrt(fa.f, &env->fp_status); | |
430 | flags = get_float_exception_flags(&env->fp_status); | |
64254eba | 431 | update_fpu_flags(env, flags); |
97694c57 EI |
432 | |
433 | return fd.l; | |
434 | } | |
435 | ||
4acb54ba EI |
436 | uint32_t helper_pcmpbf(uint32_t a, uint32_t b) |
437 | { | |
438 | unsigned int i; | |
439 | uint32_t mask = 0xff000000; | |
440 | ||
441 | for (i = 0; i < 4; i++) { | |
442 | if ((a & mask) == (b & mask)) | |
443 | return i + 1; | |
444 | mask >>= 8; | |
445 | } | |
446 | return 0; | |
447 | } | |
448 | ||
64254eba BS |
449 | void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr, |
450 | uint32_t mask) | |
968a40f6 | 451 | { |
968a40f6 | 452 | if (addr & mask) { |
97f90cbf EI |
453 | qemu_log_mask(CPU_LOG_INT, |
454 | "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n", | |
455 | addr, mask, wr, dr); | |
456 | env->sregs[SR_EAR] = addr; | |
968a40f6 EI |
457 | env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ |
458 | | (dr & 31) << 5; | |
3aa80988 | 459 | if (mask == 3) { |
968a40f6 EI |
460 | env->sregs[SR_ESR] |= 1 << 11; |
461 | } | |
97f90cbf EI |
462 | if (!(env->sregs[SR_MSR] & MSR_EE)) { |
463 | return; | |
464 | } | |
64254eba | 465 | helper_raise_exception(env, EXCP_HW_EXCP); |
968a40f6 EI |
466 | } |
467 | } | |
468 | ||
64254eba | 469 | void helper_stackprot(CPUMBState *env, uint32_t addr) |
5818dee5 EI |
470 | { |
471 | if (addr < env->slr || addr > env->shr) { | |
1d512a65 PB |
472 | qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n", |
473 | addr, env->slr, env->shr); | |
53432dc9 AF |
474 | env->sregs[SR_EAR] = addr; |
475 | env->sregs[SR_ESR] = ESR_EC_STACKPROT; | |
476 | helper_raise_exception(env, EXCP_HW_EXCP); | |
5818dee5 EI |
477 | } |
478 | } | |
479 | ||
4acb54ba EI |
480 | #if !defined(CONFIG_USER_ONLY) |
481 | /* Writes/reads to the MMU's special regs end up here. */ | |
64254eba | 482 | uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn) |
4acb54ba EI |
483 | { |
484 | return mmu_read(env, rn); | |
485 | } | |
486 | ||
64254eba | 487 | void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) |
4acb54ba EI |
488 | { |
489 | mmu_write(env, rn, v); | |
490 | } | |
faed1c2a | 491 | |
c658b94f AF |
492 | void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr, |
493 | bool is_write, bool is_exec, int is_asi, | |
494 | unsigned size) | |
faed1c2a | 495 | { |
c658b94f AF |
496 | MicroBlazeCPU *cpu; |
497 | CPUMBState *env; | |
498 | ||
97f90cbf | 499 | qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n", |
c658b94f AF |
500 | addr, is_write ? 1 : 0, is_exec ? 1 : 0); |
501 | if (cs == NULL) { | |
502 | return; | |
503 | } | |
504 | cpu = MICROBLAZE_CPU(cs); | |
505 | env = &cpu->env; | |
506 | if (!(env->sregs[SR_MSR] & MSR_EE)) { | |
faed1c2a EI |
507 | return; |
508 | } | |
509 | ||
97f90cbf | 510 | env->sregs[SR_EAR] = addr; |
faed1c2a | 511 | if (is_exec) { |
97f90cbf | 512 | if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { |
faed1c2a | 513 | env->sregs[SR_ESR] = ESR_EC_INSN_BUS; |
64254eba | 514 | helper_raise_exception(env, EXCP_HW_EXCP); |
faed1c2a EI |
515 | } |
516 | } else { | |
97f90cbf | 517 | if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { |
faed1c2a | 518 | env->sregs[SR_ESR] = ESR_EC_DATA_BUS; |
64254eba | 519 | helper_raise_exception(env, EXCP_HW_EXCP); |
faed1c2a EI |
520 | } |
521 | } | |
522 | } | |
3c7b48b7 | 523 | #endif |