[mirror_qemu.git] / target-microblaze / op_helper.c

/*
 *  Microblaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <assert.h>
#include "cpu.h"
#include "helper.h"
#include "qemu/host-utils.h"

#define D(x)

#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"

#define MMUSUFFIX _mmu
#define SHIFT 0
#include "exec/softmmu_template.h"
#define SHIFT 1
#include "exec/softmmu_template.h"
#define SHIFT 2
#include "exec/softmmu_template.h"
#define SHIFT 3
#include "exec/softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
 * NULL, it means that the function was called in C code (i.e. not
 * from generated code or from helper.c)
 */
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    int ret;

    ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
        CPUMBState *env = &cpu->env;

        if (retaddr) {
            /* now we have a real cpu fault */
            cpu_restore_state(env, retaddr);
        }
        cpu_loop_exit(env);
    }
}
#endif

void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
             id, data,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
}

uint32_t helper_get(uint32_t id, uint32_t ctrl)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
             id,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
    return 0xdead0000 | id;
}

void helper_raise_exception(CPUMBState *env, uint32_t index)
{
    CPUState *cs = CPU(mb_env_get_cpu(env));

    cs->exception_index = index;
    cpu_loop_exit(env);
}

void helper_debug(CPUMBState *env)
{
    int i;

    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
             env->debug, env->imm, env->iflags);
    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
             env->btaken, env->btarget,
             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_EIP),
             (env->sregs[SR_MSR] & MSR_IE));
    for (i = 0; i < 32; i++) {
        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
        if ((i + 1) % 4 == 0)
            qemu_log("\n");
    }
    qemu_log("\n\n");
}

static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
{
    uint32_t cout = 0;

    if ((b == ~0) && cin)
        cout = 1;
    else if ((~0 - a) < (b + cin))
        cout = 1;
    return cout;
}

uint32_t helper_cmp(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (b & 0x80000000);
    return t;
}

uint32_t helper_cmpu(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (a & 0x80000000);
    return t;
}

uint32_t helper_clz(uint32_t t0)
{
    return clz32(t0);
}

uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
{
    uint32_t ncf;
    ncf = compute_carry(a, b, cf);
    return ncf;
}

static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (b == 0) {
        env->sregs[SR_MSR] |= MSR_DZ;

        if ((env->sregs[SR_MSR] & MSR_EE)
            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
        return 0;
    }
    env->sregs[SR_MSR] &= ~MSR_DZ;
    return 1;
}

uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return (int32_t)a / (int32_t)b;
}

uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return a / b;
}

/* raise FPU exception.  */
static void raise_fpu_exception(CPUMBState *env)
{
    env->sregs[SR_ESR] = ESR_EC_FPU;
    helper_raise_exception(env, EXCP_HW_EXCP);
}

static void update_fpu_flags(CPUMBState *env, int flags)
{
    int raise = 0;

    if (flags & float_flag_invalid) {
        env->sregs[SR_FSR] |= FSR_IO;
        raise = 1;
    }
    if (flags & float_flag_divbyzero) {
        env->sregs[SR_FSR] |= FSR_DZ;
        raise = 1;
    }
    if (flags & float_flag_overflow) {
        env->sregs[SR_FSR] |= FSR_OF;
        raise = 1;
    }
    if (flags & float_flag_underflow) {
        env->sregs[SR_FSR] |= FSR_UF;
        raise = 1;
    }
    if (raise
        && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
        && (env->sregs[SR_MSR] & MSR_EE)) {
        raise_fpu_exception(env);
    }
}

uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_add(fa.f, fb.f, &env->fp_status);

    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_div(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    uint32_t r = 0;

    fa.l = a;
    fb.l = b;

    if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
        update_fpu_flags(env, float_flag_invalid);
        r = 1;
    }

    if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
        r = 1;
    }

    return r;
}

uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_lt(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_le(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);


    return r;
}

uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);
    return r;
}

uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_flt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;

    fa.l = a;
    fd.f = int32_to_float32(fa.l, &env->fp_status);
    return fd.l;
}

uint32_t helper_fint(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fa;
    uint32_t r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    r = float32_to_int32(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return r;
}

uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fd.l = float32_sqrt(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
{
    unsigned int i;
    uint32_t mask = 0xff000000;

    for (i = 0; i < 4; i++) {
        if ((a & mask) == (b & mask))
            return i + 1;
        mask >>= 8;
    }
    return 0;
}

void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
                     uint32_t mask)
{
    if (addr & mask) {
            qemu_log_mask(CPU_LOG_INT,
                          "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
                          addr, mask, wr, dr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                 | (dr & 31) << 5;
            if (mask == 3) {
                env->sregs[SR_ESR] |= 1 << 11;
            }
            if (!(env->sregs[SR_MSR] & MSR_EE)) {
                return;
            }
            helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

void helper_stackprot(CPUMBState *env, uint32_t addr)
{
    if (addr < env->slr || addr > env->shr) {
            qemu_log("Stack protector violation at %x %x %x\n",
                     addr, env->slr, env->shr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_STACKPROT;
            helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here.  */
uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
{
    return mmu_read(env, rn);
}

void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
    mmu_write(env, rn, v);
}

void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
                              bool is_write, bool is_exec, int is_asi,
                              unsigned size)
{
    MicroBlazeCPU *cpu;
    CPUMBState *env;

    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
             addr, is_write ? 1 : 0, is_exec ? 1 : 0);
    if (cs == NULL) {
        return;
    }
    cpu = MICROBLAZE_CPU(cs);
    env = &cpu->env;
    if (!(env->sregs[SR_MSR] & MSR_EE)) {
        return;
    }

    env->sregs[SR_EAR] = addr;
    if (is_exec) {
        if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    } else {
        if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    }
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* Microblaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	19	*/
	20
	21	#include <assert.h>
3e457172	22	#include "cpu.h"
4acb54ba	23	#include "helper.h"
1de7afc9	24	#include "qemu/host-utils.h"
4acb54ba EI	25
	26	#define D(x)
	27
	28	#if !defined(CONFIG_USER_ONLY)
022c62cb	29	#include "exec/softmmu_exec.h"
3e457172	30
4acb54ba EI	31	#define MMUSUFFIX _mmu
4acb54ba EI	32	#define SHIFT 0
022c62cb	33	#include "exec/softmmu_template.h"
4acb54ba	34	#define SHIFT 1
022c62cb	35	#include "exec/softmmu_template.h"
4acb54ba	36	#define SHIFT 2
022c62cb	37	#include "exec/softmmu_template.h"
4acb54ba	38	#define SHIFT 3
022c62cb	39	#include "exec/softmmu_template.h"
4acb54ba EI	40
4acb54ba EI	41	/* Try to fill the TLB and return an exception if error. If retaddr is
d5a11fef AF	42	* NULL, it means that the function was called in C code (i.e. not
	43	* from generated code or from helper.c)
	44	*/
	45	void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
20503968	46	uintptr_t retaddr)
4acb54ba	47	{
4acb54ba EI	48	int ret;
4acb54ba EI	49
d5a11fef	50	ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
4acb54ba	51	if (unlikely(ret)) {
d5a11fef AF	52	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
	53	CPUMBState *env = &cpu->env;
	54
4acb54ba EI	55	if (retaddr) {
4acb54ba EI	56	/* now we have a real cpu fault */
a8a826a3	57	cpu_restore_state(env, retaddr);
4acb54ba	58	}
1162c041	59	cpu_loop_exit(env);
4acb54ba	60	}
4acb54ba EI	61	}
	62	#endif
	63
6d76d23e EI	64	void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
	65	{
	66	int test = ctrl & STREAM_TEST;
	67	int atomic = ctrl & STREAM_ATOMIC;
	68	int control = ctrl & STREAM_CONTROL;
	69	int nonblock = ctrl & STREAM_NONBLOCK;
	70	int exception = ctrl & STREAM_EXCEPTION;
	71
	72	qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
	73	id, data,
	74	test ? "t" : "",
	75	nonblock ? "n" : "",
	76	exception ? "e" : "",
	77	control ? "c" : "",
	78	atomic ? "a" : "");
	79	}
	80
	81	uint32_t helper_get(uint32_t id, uint32_t ctrl)
	82	{
	83	int test = ctrl & STREAM_TEST;
	84	int atomic = ctrl & STREAM_ATOMIC;
	85	int control = ctrl & STREAM_CONTROL;
	86	int nonblock = ctrl & STREAM_NONBLOCK;
	87	int exception = ctrl & STREAM_EXCEPTION;
	88
	89	qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
	90	id,
	91	test ? "t" : "",
	92	nonblock ? "n" : "",
	93	exception ? "e" : "",
	94	control ? "c" : "",
	95	atomic ? "a" : "");
	96	return 0xdead0000 \| id;
	97	}
	98
64254eba	99	void helper_raise_exception(CPUMBState *env, uint32_t index)
4acb54ba	100	{
27103424 AF	101	CPUState *cs = CPU(mb_env_get_cpu(env));
	102
	103	cs->exception_index = index;
1162c041	104	cpu_loop_exit(env);
4acb54ba EI	105	}
4acb54ba EI	106
64254eba	107	void helper_debug(CPUMBState *env)
4acb54ba EI	108	{
	109	int i;
	110
	111	qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
4c24aa0a MS	112	qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
4c24aa0a MS	113	env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
17c52a43 EI	114	env->debug, env->imm, env->iflags);
	115	qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
	116	env->btaken, env->btarget,
	117	(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
	118	(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
	119	(env->sregs[SR_MSR] & MSR_EIP),
	120	(env->sregs[SR_MSR] & MSR_IE));
4acb54ba EI	121	for (i = 0; i < 32; i++) {
	122	qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
	123	if ((i + 1) % 4 == 0)
	124	qemu_log("\n");
	125	}
	126	qemu_log("\n\n");
	127	}
	128
	129	static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
	130	{
	131	uint32_t cout = 0;
	132
	133	if ((b == ~0) && cin)
	134	cout = 1;
	135	else if ((~0 - a) < (b + cin))
	136	cout = 1;
	137	return cout;
	138	}
	139
	140	uint32_t helper_cmp(uint32_t a, uint32_t b)
	141	{
	142	uint32_t t;
	143
	144	t = b + ~a + 1;
	145	if ((b & 0x80000000) ^ (a & 0x80000000))
	146	t = (t & 0x7fffffff) \| (b & 0x80000000);
	147	return t;
	148	}
	149
	150	uint32_t helper_cmpu(uint32_t a, uint32_t b)
	151	{
	152	uint32_t t;
	153
	154	t = b + ~a + 1;
	155	if ((b & 0x80000000) ^ (a & 0x80000000))
	156	t = (t & 0x7fffffff) \| (a & 0x80000000);
	157	return t;
	158	}
	159
48b5e96f EI	160	uint32_t helper_clz(uint32_t t0)
	161	{
	162	return clz32(t0);
	163	}
	164
5d0bb823	165	uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
4acb54ba	166	{
5d0bb823	167	uint32_t ncf;
40cbf5b7 EI	168	ncf = compute_carry(a, b, cf);
40cbf5b7 EI	169	return ncf;
4acb54ba EI	170	}
4acb54ba EI	171
64254eba	172	static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba EI	173	{
	174	if (b == 0) {
	175	env->sregs[SR_MSR] \|= MSR_DZ;
821ebb33 EI	176
	177	if ((env->sregs[SR_MSR] & MSR_EE)
	178	&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
	179	env->sregs[SR_ESR] = ESR_EC_DIVZERO;
64254eba	180	helper_raise_exception(env, EXCP_HW_EXCP);
821ebb33	181	}
4acb54ba EI	182	return 0;
	183	}
	184	env->sregs[SR_MSR] &= ~MSR_DZ;
	185	return 1;
	186	}
	187
64254eba	188	uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	189	{
64254eba	190	if (!div_prepare(env, a, b)) {
4acb54ba	191	return 0;
64254eba	192	}
4acb54ba EI	193	return (int32_t)a / (int32_t)b;
	194	}
	195
64254eba	196	uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	197	{
64254eba	198	if (!div_prepare(env, a, b)) {
4acb54ba	199	return 0;
64254eba	200	}
4acb54ba EI	201	return a / b;
	202	}
	203
97694c57	204	/* raise FPU exception. */
64254eba	205	static void raise_fpu_exception(CPUMBState *env)
97694c57 EI	206	{
97694c57 EI	207	env->sregs[SR_ESR] = ESR_EC_FPU;
64254eba	208	helper_raise_exception(env, EXCP_HW_EXCP);
97694c57 EI	209	}
97694c57 EI	210
64254eba	211	static void update_fpu_flags(CPUMBState *env, int flags)
97694c57 EI	212	{
	213	int raise = 0;
	214
	215	if (flags & float_flag_invalid) {
	216	env->sregs[SR_FSR] \|= FSR_IO;
	217	raise = 1;
	218	}
	219	if (flags & float_flag_divbyzero) {
	220	env->sregs[SR_FSR] \|= FSR_DZ;
	221	raise = 1;
	222	}
	223	if (flags & float_flag_overflow) {
	224	env->sregs[SR_FSR] \|= FSR_OF;
	225	raise = 1;
	226	}
	227	if (flags & float_flag_underflow) {
	228	env->sregs[SR_FSR] \|= FSR_UF;
	229	raise = 1;
	230	}
	231	if (raise
	232	&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
	233	&& (env->sregs[SR_MSR] & MSR_EE)) {
64254eba	234	raise_fpu_exception(env);
97694c57 EI	235	}
	236	}
	237
64254eba	238	uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	239	{
	240	CPU_FloatU fd, fa, fb;
	241	int flags;
	242
	243	set_float_exception_flags(0, &env->fp_status);
	244	fa.l = a;
	245	fb.l = b;
	246	fd.f = float32_add(fa.f, fb.f, &env->fp_status);
	247
	248	flags = get_float_exception_flags(&env->fp_status);
64254eba	249	update_fpu_flags(env, flags);
97694c57 EI	250	return fd.l;
	251	}
	252
64254eba	253	uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	254	{
	255	CPU_FloatU fd, fa, fb;
	256	int flags;
	257
	258	set_float_exception_flags(0, &env->fp_status);
	259	fa.l = a;
	260	fb.l = b;
	261	fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
	262	flags = get_float_exception_flags(&env->fp_status);
64254eba	263	update_fpu_flags(env, flags);
97694c57 EI	264	return fd.l;
	265	}
	266
64254eba	267	uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	268	{
	269	CPU_FloatU fd, fa, fb;
	270	int flags;
	271
	272	set_float_exception_flags(0, &env->fp_status);
	273	fa.l = a;
	274	fb.l = b;
	275	fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
	276	flags = get_float_exception_flags(&env->fp_status);
64254eba	277	update_fpu_flags(env, flags);
97694c57 EI	278
	279	return fd.l;
	280	}
	281
64254eba	282	uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	283	{
	284	CPU_FloatU fd, fa, fb;
	285	int flags;
	286
	287	set_float_exception_flags(0, &env->fp_status);
	288	fa.l = a;
	289	fb.l = b;
	290	fd.f = float32_div(fb.f, fa.f, &env->fp_status);
	291	flags = get_float_exception_flags(&env->fp_status);
64254eba	292	update_fpu_flags(env, flags);
97694c57 EI	293
	294	return fd.l;
	295	}
	296
64254eba	297	uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
97694c57	298	{
ef9d48da EI	299	CPU_FloatU fa, fb;
	300	uint32_t r = 0;
	301
	302	fa.l = a;
	303	fb.l = b;
	304
	305	if (float32_is_signaling_nan(fa.f) \|\| float32_is_signaling_nan(fb.f)) {
64254eba	306	update_fpu_flags(env, float_flag_invalid);
ef9d48da EI	307	r = 1;
	308	}
	309
18569871	310	if (float32_is_quiet_nan(fa.f) \|\| float32_is_quiet_nan(fb.f)) {
ef9d48da EI	311	r = 1;
	312	}
	313
	314	return r;
97694c57 EI	315	}
97694c57 EI	316
64254eba	317	uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	318	{
	319	CPU_FloatU fa, fb;
	320	int r;
	321	int flags;
	322
	323	set_float_exception_flags(0, &env->fp_status);
	324	fa.l = a;
	325	fb.l = b;
	326	r = float32_lt(fb.f, fa.f, &env->fp_status);
	327	flags = get_float_exception_flags(&env->fp_status);
64254eba	328	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	329
	330	return r;
	331	}
	332
64254eba	333	uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	334	{
	335	CPU_FloatU fa, fb;
	336	int flags;
	337	int r;
	338
	339	set_float_exception_flags(0, &env->fp_status);
	340	fa.l = a;
	341	fb.l = b;
211315fb	342	r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	343	flags = get_float_exception_flags(&env->fp_status);
64254eba	344	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	345
	346	return r;
	347	}
	348
64254eba	349	uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	350	{
	351	CPU_FloatU fa, fb;
	352	int flags;
	353	int r;
	354
	355	fa.l = a;
	356	fb.l = b;
	357	set_float_exception_flags(0, &env->fp_status);
	358	r = float32_le(fa.f, fb.f, &env->fp_status);
	359	flags = get_float_exception_flags(&env->fp_status);
64254eba	360	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	361
	362
	363	return r;
	364	}
	365
64254eba	366	uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	367	{
	368	CPU_FloatU fa, fb;
	369	int flags, r;
	370
	371	fa.l = a;
	372	fb.l = b;
	373	set_float_exception_flags(0, &env->fp_status);
	374	r = float32_lt(fa.f, fb.f, &env->fp_status);
	375	flags = get_float_exception_flags(&env->fp_status);
64254eba	376	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	377	return r;
	378	}
	379
64254eba	380	uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	381	{
	382	CPU_FloatU fa, fb;
	383	int flags, r;
	384
	385	fa.l = a;
	386	fb.l = b;
	387	set_float_exception_flags(0, &env->fp_status);
211315fb	388	r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	389	flags = get_float_exception_flags(&env->fp_status);
64254eba	390	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	391
	392	return r;
	393	}
	394
64254eba	395	uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	396	{
	397	CPU_FloatU fa, fb;
	398	int flags, r;
	399
	400	fa.l = a;
	401	fb.l = b;
	402	set_float_exception_flags(0, &env->fp_status);
	403	r = !float32_lt(fa.f, fb.f, &env->fp_status);
	404	flags = get_float_exception_flags(&env->fp_status);
64254eba	405	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	406
	407	return r;
	408	}
	409
64254eba	410	uint32_t helper_flt(CPUMBState *env, uint32_t a)
97694c57 EI	411	{
	412	CPU_FloatU fd, fa;
	413
	414	fa.l = a;
	415	fd.f = int32_to_float32(fa.l, &env->fp_status);
	416	return fd.l;
	417	}
	418
64254eba	419	uint32_t helper_fint(CPUMBState *env, uint32_t a)
97694c57 EI	420	{
	421	CPU_FloatU fa;
	422	uint32_t r;
	423	int flags;
	424
	425	set_float_exception_flags(0, &env->fp_status);
	426	fa.l = a;
	427	r = float32_to_int32(fa.f, &env->fp_status);
	428	flags = get_float_exception_flags(&env->fp_status);
64254eba	429	update_fpu_flags(env, flags);
97694c57 EI	430
	431	return r;
	432	}
	433
64254eba	434	uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
97694c57 EI	435	{
	436	CPU_FloatU fd, fa;
	437	int flags;
	438
	439	set_float_exception_flags(0, &env->fp_status);
	440	fa.l = a;
	441	fd.l = float32_sqrt(fa.f, &env->fp_status);
	442	flags = get_float_exception_flags(&env->fp_status);
64254eba	443	update_fpu_flags(env, flags);
97694c57 EI	444
	445	return fd.l;
	446	}
	447
4acb54ba EI	448	uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
	449	{
	450	unsigned int i;
	451	uint32_t mask = 0xff000000;
	452
	453	for (i = 0; i < 4; i++) {
	454	if ((a & mask) == (b & mask))
	455	return i + 1;
	456	mask >>= 8;
	457	}
	458	return 0;
	459	}
	460
64254eba BS	461	void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
64254eba BS	462	uint32_t mask)
968a40f6	463	{
968a40f6	464	if (addr & mask) {
97f90cbf EI	465	qemu_log_mask(CPU_LOG_INT,
	466	"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
	467	addr, mask, wr, dr);
	468	env->sregs[SR_EAR] = addr;
968a40f6 EI	469	env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA \| (wr << 10) \
968a40f6 EI	470	\| (dr & 31) << 5;
3aa80988	471	if (mask == 3) {
968a40f6 EI	472	env->sregs[SR_ESR] \|= 1 << 11;
968a40f6 EI	473	}
97f90cbf EI	474	if (!(env->sregs[SR_MSR] & MSR_EE)) {
	475	return;
	476	}
64254eba	477	helper_raise_exception(env, EXCP_HW_EXCP);
968a40f6 EI	478	}
	479	}
	480
64254eba	481	void helper_stackprot(CPUMBState *env, uint32_t addr)
5818dee5 EI	482	{
	483	if (addr < env->slr \|\| addr > env->shr) {
	484	qemu_log("Stack protector violation at %x %x %x\n",
	485	addr, env->slr, env->shr);
	486	env->sregs[SR_EAR] = addr;
	487	env->sregs[SR_ESR] = ESR_EC_STACKPROT;
64254eba	488	helper_raise_exception(env, EXCP_HW_EXCP);
5818dee5 EI	489	}
	490	}
	491
4acb54ba EI	492	#if !defined(CONFIG_USER_ONLY)
4acb54ba EI	493	/* Writes/reads to the MMU's special regs end up here. */
64254eba	494	uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
4acb54ba EI	495	{
	496	return mmu_read(env, rn);
	497	}
	498
64254eba	499	void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
4acb54ba EI	500	{
	501	mmu_write(env, rn, v);
	502	}
faed1c2a	503
c658b94f AF	504	void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
	505	bool is_write, bool is_exec, int is_asi,
	506	unsigned size)
faed1c2a	507	{
c658b94f AF	508	MicroBlazeCPU *cpu;
	509	CPUMBState *env;
	510
97f90cbf	511	qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
c658b94f AF	512	addr, is_write ? 1 : 0, is_exec ? 1 : 0);
	513	if (cs == NULL) {
	514	return;
	515	}
	516	cpu = MICROBLAZE_CPU(cs);
	517	env = &cpu->env;
	518	if (!(env->sregs[SR_MSR] & MSR_EE)) {
faed1c2a EI	519	return;
	520	}
	521
97f90cbf	522	env->sregs[SR_EAR] = addr;
faed1c2a	523	if (is_exec) {
97f90cbf	524	if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
faed1c2a	525	env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
64254eba	526	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	527	}
faed1c2a EI	528	} else {
97f90cbf	529	if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
faed1c2a	530	env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
64254eba	531	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	532	}
	533	}
	534	}
3c7b48b7	535	#endif