]>
Commit | Line | Data |
---|---|---|
4acb54ba EI |
1 | /* |
2 | * Xilinx MicroBlaze emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2009 Edgar E. Iglesias. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
4acb54ba EI |
18 | */ |
19 | ||
20 | #include <stdarg.h> | |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <assert.h> | |
26 | ||
27 | #include "cpu.h" | |
28 | #include "exec-all.h" | |
29 | #include "disas.h" | |
30 | #include "tcg-op.h" | |
31 | #include "helper.h" | |
32 | #include "microblaze-decode.h" | |
33 | #include "qemu-common.h" | |
34 | ||
35 | #define GEN_HELPER 1 | |
36 | #include "helper.h" | |
37 | ||
38 | #define SIM_COMPAT 0 | |
39 | #define DISAS_GNU 1 | |
40 | #define DISAS_MB 1 | |
41 | #if DISAS_MB && !SIM_COMPAT | |
42 | # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) | |
43 | #else | |
44 | # define LOG_DIS(...) do { } while (0) | |
45 | #endif | |
46 | ||
47 | #define D(x) | |
48 | ||
49 | #define EXTRACT_FIELD(src, start, end) \ | |
50 | (((src) >> start) & ((1 << (end - start + 1)) - 1)) | |
51 | ||
52 | static TCGv env_debug; | |
53 | static TCGv_ptr cpu_env; | |
54 | static TCGv cpu_R[32]; | |
55 | static TCGv cpu_SR[18]; | |
56 | static TCGv env_imm; | |
57 | static TCGv env_btaken; | |
58 | static TCGv env_btarget; | |
59 | static TCGv env_iflags; | |
60 | ||
61 | #include "gen-icount.h" | |
62 | ||
63 | /* This is the state at translation time. */ | |
64 | typedef struct DisasContext { | |
65 | CPUState *env; | |
a5efa644 | 66 | target_ulong pc; |
4acb54ba EI |
67 | |
68 | /* Decoder. */ | |
69 | int type_b; | |
70 | uint32_t ir; | |
71 | uint8_t opcode; | |
72 | uint8_t rd, ra, rb; | |
73 | uint16_t imm; | |
74 | ||
75 | unsigned int cpustate_changed; | |
76 | unsigned int delayed_branch; | |
77 | unsigned int tb_flags, synced_flags; /* tb dependent flags. */ | |
78 | unsigned int clear_imm; | |
79 | int is_jmp; | |
80 | ||
844bab60 EI |
81 | #define JMP_NOJMP 0 |
82 | #define JMP_DIRECT 1 | |
83 | #define JMP_DIRECT_CC 2 | |
84 | #define JMP_INDIRECT 3 | |
4acb54ba EI |
85 | unsigned int jmp; |
86 | uint32_t jmp_pc; | |
87 | ||
88 | int abort_at_next_insn; | |
89 | int nr_nops; | |
90 | struct TranslationBlock *tb; | |
91 | int singlestep_enabled; | |
92 | } DisasContext; | |
93 | ||
38972938 | 94 | static const char *regnames[] = |
4acb54ba EI |
95 | { |
96 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
97 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
98 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
99 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
100 | }; | |
101 | ||
38972938 | 102 | static const char *special_regnames[] = |
4acb54ba EI |
103 | { |
104 | "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", | |
105 | "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", | |
106 | "sr16", "sr17", "sr18" | |
107 | }; | |
108 | ||
109 | /* Sign extend at translation time. */ | |
110 | static inline int sign_extend(unsigned int val, unsigned int width) | |
111 | { | |
112 | int sval; | |
113 | ||
114 | /* LSL. */ | |
115 | val <<= 31 - width; | |
116 | sval = val; | |
117 | /* ASR. */ | |
118 | sval >>= 31 - width; | |
119 | return sval; | |
120 | } | |
121 | ||
122 | static inline void t_sync_flags(DisasContext *dc) | |
123 | { | |
124 | /* Synch the tb dependant flags between translator and runtime. */ | |
125 | if (dc->tb_flags != dc->synced_flags) { | |
126 | tcg_gen_movi_tl(env_iflags, dc->tb_flags); | |
127 | dc->synced_flags = dc->tb_flags; | |
128 | } | |
129 | } | |
130 | ||
131 | static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) | |
132 | { | |
133 | TCGv_i32 tmp = tcg_const_i32(index); | |
134 | ||
135 | t_sync_flags(dc); | |
136 | tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); | |
137 | gen_helper_raise_exception(tmp); | |
138 | tcg_temp_free_i32(tmp); | |
139 | dc->is_jmp = DISAS_UPDATE; | |
140 | } | |
141 | ||
142 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) | |
143 | { | |
144 | TranslationBlock *tb; | |
145 | tb = dc->tb; | |
146 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { | |
147 | tcg_gen_goto_tb(n); | |
148 | tcg_gen_movi_tl(cpu_SR[SR_PC], dest); | |
149 | tcg_gen_exit_tb((long)tb + n); | |
150 | } else { | |
151 | tcg_gen_movi_tl(cpu_SR[SR_PC], dest); | |
152 | tcg_gen_exit_tb(0); | |
153 | } | |
154 | } | |
155 | ||
61204ce8 EI |
156 | /* True if ALU operand b is a small immediate that may deserve |
157 | faster treatment. */ | |
158 | static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) | |
159 | { | |
160 | /* Immediate insn without the imm prefix ? */ | |
161 | return dc->type_b && !(dc->tb_flags & IMM_FLAG); | |
162 | } | |
163 | ||
4acb54ba EI |
164 | static inline TCGv *dec_alu_op_b(DisasContext *dc) |
165 | { | |
166 | if (dc->type_b) { | |
167 | if (dc->tb_flags & IMM_FLAG) | |
168 | tcg_gen_ori_tl(env_imm, env_imm, dc->imm); | |
169 | else | |
170 | tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm)); | |
171 | return &env_imm; | |
172 | } else | |
173 | return &cpu_R[dc->rb]; | |
174 | } | |
175 | ||
176 | static void dec_add(DisasContext *dc) | |
177 | { | |
178 | unsigned int k, c; | |
179 | ||
180 | k = dc->opcode & 4; | |
181 | c = dc->opcode & 2; | |
182 | ||
183 | LOG_DIS("add%s%s%s r%d r%d r%d\n", | |
184 | dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "", | |
185 | dc->rd, dc->ra, dc->rb); | |
186 | ||
187 | if (k && !c && dc->rd) | |
188 | tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); | |
189 | else if (dc->rd) | |
190 | gen_helper_addkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)), | |
191 | tcg_const_tl(k), tcg_const_tl(c)); | |
192 | else { | |
193 | TCGv d = tcg_temp_new(); | |
194 | gen_helper_addkc(d, cpu_R[dc->ra], *(dec_alu_op_b(dc)), | |
195 | tcg_const_tl(k), tcg_const_tl(c)); | |
196 | tcg_temp_free(d); | |
197 | } | |
198 | } | |
199 | ||
200 | static void dec_sub(DisasContext *dc) | |
201 | { | |
202 | unsigned int u, cmp, k, c; | |
203 | ||
204 | u = dc->imm & 2; | |
205 | k = dc->opcode & 4; | |
206 | c = dc->opcode & 2; | |
207 | cmp = (dc->imm & 1) && (!dc->type_b) && k; | |
208 | ||
209 | if (cmp) { | |
210 | LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir); | |
211 | if (dc->rd) { | |
212 | if (u) | |
213 | gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
214 | else | |
215 | gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
216 | } | |
217 | } else { | |
218 | LOG_DIS("sub%s%s r%d, r%d r%d\n", | |
219 | k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb); | |
220 | ||
221 | if (!k || c) { | |
222 | TCGv t; | |
223 | t = tcg_temp_new(); | |
224 | if (dc->rd) | |
225 | gen_helper_subkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)), | |
226 | tcg_const_tl(k), tcg_const_tl(c)); | |
227 | else | |
228 | gen_helper_subkc(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)), | |
229 | tcg_const_tl(k), tcg_const_tl(c)); | |
230 | tcg_temp_free(t); | |
231 | } | |
232 | else if (dc->rd) | |
233 | tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); | |
234 | } | |
235 | } | |
236 | ||
237 | static void dec_pattern(DisasContext *dc) | |
238 | { | |
239 | unsigned int mode; | |
240 | int l1; | |
241 | ||
1567a005 | 242 | if ((dc->tb_flags & MSR_EE_FLAG) |
97f90cbf | 243 | && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) |
1567a005 EI |
244 | && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) { |
245 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); | |
246 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
247 | } | |
248 | ||
4acb54ba EI |
249 | mode = dc->opcode & 3; |
250 | switch (mode) { | |
251 | case 0: | |
252 | /* pcmpbf. */ | |
253 | LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); | |
254 | if (dc->rd) | |
255 | gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
256 | break; | |
257 | case 2: | |
258 | LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); | |
259 | if (dc->rd) { | |
260 | TCGv t0 = tcg_temp_local_new(); | |
261 | l1 = gen_new_label(); | |
262 | tcg_gen_movi_tl(t0, 1); | |
263 | tcg_gen_brcond_tl(TCG_COND_EQ, | |
264 | cpu_R[dc->ra], cpu_R[dc->rb], l1); | |
265 | tcg_gen_movi_tl(t0, 0); | |
266 | gen_set_label(l1); | |
267 | tcg_gen_mov_tl(cpu_R[dc->rd], t0); | |
268 | tcg_temp_free(t0); | |
269 | } | |
270 | break; | |
271 | case 3: | |
272 | LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); | |
273 | l1 = gen_new_label(); | |
274 | if (dc->rd) { | |
275 | TCGv t0 = tcg_temp_local_new(); | |
276 | tcg_gen_movi_tl(t0, 1); | |
277 | tcg_gen_brcond_tl(TCG_COND_NE, | |
278 | cpu_R[dc->ra], cpu_R[dc->rb], l1); | |
279 | tcg_gen_movi_tl(t0, 0); | |
280 | gen_set_label(l1); | |
281 | tcg_gen_mov_tl(cpu_R[dc->rd], t0); | |
282 | tcg_temp_free(t0); | |
283 | } | |
284 | break; | |
285 | default: | |
286 | cpu_abort(dc->env, | |
287 | "unsupported pattern insn opcode=%x\n", dc->opcode); | |
288 | break; | |
289 | } | |
290 | } | |
291 | ||
292 | static void dec_and(DisasContext *dc) | |
293 | { | |
294 | unsigned int not; | |
295 | ||
296 | if (!dc->type_b && (dc->imm & (1 << 10))) { | |
297 | dec_pattern(dc); | |
298 | return; | |
299 | } | |
300 | ||
301 | not = dc->opcode & (1 << 1); | |
302 | LOG_DIS("and%s\n", not ? "n" : ""); | |
303 | ||
304 | if (!dc->rd) | |
305 | return; | |
306 | ||
307 | if (not) { | |
308 | TCGv t = tcg_temp_new(); | |
309 | tcg_gen_not_tl(t, *(dec_alu_op_b(dc))); | |
310 | tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t); | |
311 | tcg_temp_free(t); | |
312 | } else | |
313 | tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); | |
314 | } | |
315 | ||
316 | static void dec_or(DisasContext *dc) | |
317 | { | |
318 | if (!dc->type_b && (dc->imm & (1 << 10))) { | |
319 | dec_pattern(dc); | |
320 | return; | |
321 | } | |
322 | ||
323 | LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm); | |
324 | if (dc->rd) | |
325 | tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); | |
326 | } | |
327 | ||
328 | static void dec_xor(DisasContext *dc) | |
329 | { | |
330 | if (!dc->type_b && (dc->imm & (1 << 10))) { | |
331 | dec_pattern(dc); | |
332 | return; | |
333 | } | |
334 | ||
335 | LOG_DIS("xor r%d\n", dc->rd); | |
336 | if (dc->rd) | |
337 | tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); | |
338 | } | |
339 | ||
340 | static void read_carry(DisasContext *dc, TCGv d) | |
341 | { | |
342 | tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31); | |
343 | } | |
344 | ||
345 | static void write_carry(DisasContext *dc, TCGv v) | |
346 | { | |
347 | TCGv t0 = tcg_temp_new(); | |
348 | tcg_gen_shli_tl(t0, v, 31); | |
349 | tcg_gen_sari_tl(t0, t0, 31); | |
350 | tcg_gen_mov_tl(env_debug, t0); | |
351 | tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC)); | |
352 | tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], | |
353 | ~(MSR_C | MSR_CC)); | |
354 | tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0); | |
355 | tcg_temp_free(t0); | |
356 | } | |
357 | ||
358 | ||
359 | static inline void msr_read(DisasContext *dc, TCGv d) | |
360 | { | |
361 | tcg_gen_mov_tl(d, cpu_SR[SR_MSR]); | |
362 | } | |
363 | ||
364 | static inline void msr_write(DisasContext *dc, TCGv v) | |
365 | { | |
366 | dc->cpustate_changed = 1; | |
367 | tcg_gen_mov_tl(cpu_SR[SR_MSR], v); | |
368 | /* PVR, we have a processor version register. */ | |
369 | tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10)); | |
370 | } | |
371 | ||
372 | static void dec_msr(DisasContext *dc) | |
373 | { | |
374 | TCGv t0, t1; | |
375 | unsigned int sr, to, rn; | |
1567a005 | 376 | int mem_index = cpu_mmu_index(dc->env); |
4acb54ba EI |
377 | |
378 | sr = dc->imm & ((1 << 14) - 1); | |
379 | to = dc->imm & (1 << 14); | |
380 | dc->type_b = 1; | |
381 | if (to) | |
382 | dc->cpustate_changed = 1; | |
383 | ||
384 | /* msrclr and msrset. */ | |
385 | if (!(dc->imm & (1 << 15))) { | |
386 | unsigned int clr = dc->ir & (1 << 16); | |
387 | ||
388 | LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", | |
389 | dc->rd, dc->imm); | |
1567a005 EI |
390 | |
391 | if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) { | |
392 | /* nop??? */ | |
393 | return; | |
394 | } | |
395 | ||
396 | if ((dc->tb_flags & MSR_EE_FLAG) | |
397 | && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) { | |
398 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); | |
399 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
400 | return; | |
401 | } | |
402 | ||
4acb54ba EI |
403 | if (dc->rd) |
404 | msr_read(dc, cpu_R[dc->rd]); | |
405 | ||
406 | t0 = tcg_temp_new(); | |
407 | t1 = tcg_temp_new(); | |
408 | msr_read(dc, t0); | |
409 | tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc))); | |
410 | ||
411 | if (clr) { | |
412 | tcg_gen_not_tl(t1, t1); | |
413 | tcg_gen_and_tl(t0, t0, t1); | |
414 | } else | |
415 | tcg_gen_or_tl(t0, t0, t1); | |
416 | msr_write(dc, t0); | |
417 | tcg_temp_free(t0); | |
418 | tcg_temp_free(t1); | |
419 | tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4); | |
420 | dc->is_jmp = DISAS_UPDATE; | |
421 | return; | |
422 | } | |
423 | ||
1567a005 EI |
424 | if (to) { |
425 | if ((dc->tb_flags & MSR_EE_FLAG) | |
426 | && mem_index == MMU_USER_IDX) { | |
427 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); | |
428 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
429 | return; | |
430 | } | |
431 | } | |
432 | ||
4acb54ba EI |
433 | #if !defined(CONFIG_USER_ONLY) |
434 | /* Catch read/writes to the mmu block. */ | |
435 | if ((sr & ~0xff) == 0x1000) { | |
436 | sr &= 7; | |
437 | LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); | |
438 | if (to) | |
439 | gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]); | |
440 | else | |
441 | gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr)); | |
442 | return; | |
443 | } | |
444 | #endif | |
445 | ||
446 | if (to) { | |
447 | LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); | |
448 | switch (sr) { | |
449 | case 0: | |
450 | break; | |
451 | case 1: | |
452 | msr_write(dc, cpu_R[dc->ra]); | |
453 | break; | |
454 | case 0x3: | |
455 | tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]); | |
456 | break; | |
457 | case 0x5: | |
458 | tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]); | |
459 | break; | |
460 | case 0x7: | |
97694c57 | 461 | tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31); |
4acb54ba EI |
462 | break; |
463 | default: | |
464 | cpu_abort(dc->env, "unknown mts reg %x\n", sr); | |
465 | break; | |
466 | } | |
467 | } else { | |
468 | LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); | |
469 | ||
470 | switch (sr) { | |
471 | case 0: | |
472 | tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc); | |
473 | break; | |
474 | case 1: | |
475 | msr_read(dc, cpu_R[dc->rd]); | |
476 | break; | |
477 | case 0x3: | |
478 | tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]); | |
479 | break; | |
480 | case 0x5: | |
481 | tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]); | |
482 | break; | |
483 | case 0x7: | |
97694c57 | 484 | tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]); |
4acb54ba EI |
485 | break; |
486 | case 0xb: | |
487 | tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]); | |
488 | break; | |
489 | case 0x2000: | |
490 | case 0x2001: | |
491 | case 0x2002: | |
492 | case 0x2003: | |
493 | case 0x2004: | |
494 | case 0x2005: | |
495 | case 0x2006: | |
496 | case 0x2007: | |
497 | case 0x2008: | |
498 | case 0x2009: | |
499 | case 0x200a: | |
500 | case 0x200b: | |
501 | case 0x200c: | |
502 | rn = sr & 0xf; | |
503 | tcg_gen_ld_tl(cpu_R[dc->rd], | |
504 | cpu_env, offsetof(CPUState, pvr.regs[rn])); | |
505 | break; | |
506 | default: | |
507 | cpu_abort(dc->env, "unknown mfs reg %x\n", sr); | |
508 | break; | |
509 | } | |
510 | } | |
ee7dbcf8 EI |
511 | |
512 | if (dc->rd == 0) { | |
513 | tcg_gen_movi_tl(cpu_R[0], 0); | |
514 | } | |
4acb54ba EI |
515 | } |
516 | ||
517 | /* 64-bit signed mul, lower result in d and upper in d2. */ | |
518 | static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b) | |
519 | { | |
520 | TCGv_i64 t0, t1; | |
521 | ||
522 | t0 = tcg_temp_new_i64(); | |
523 | t1 = tcg_temp_new_i64(); | |
524 | ||
525 | tcg_gen_ext_i32_i64(t0, a); | |
526 | tcg_gen_ext_i32_i64(t1, b); | |
527 | tcg_gen_mul_i64(t0, t0, t1); | |
528 | ||
529 | tcg_gen_trunc_i64_i32(d, t0); | |
530 | tcg_gen_shri_i64(t0, t0, 32); | |
531 | tcg_gen_trunc_i64_i32(d2, t0); | |
532 | ||
533 | tcg_temp_free_i64(t0); | |
534 | tcg_temp_free_i64(t1); | |
535 | } | |
536 | ||
537 | /* 64-bit unsigned muls, lower result in d and upper in d2. */ | |
538 | static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b) | |
539 | { | |
540 | TCGv_i64 t0, t1; | |
541 | ||
542 | t0 = tcg_temp_new_i64(); | |
543 | t1 = tcg_temp_new_i64(); | |
544 | ||
545 | tcg_gen_extu_i32_i64(t0, a); | |
546 | tcg_gen_extu_i32_i64(t1, b); | |
547 | tcg_gen_mul_i64(t0, t0, t1); | |
548 | ||
549 | tcg_gen_trunc_i64_i32(d, t0); | |
550 | tcg_gen_shri_i64(t0, t0, 32); | |
551 | tcg_gen_trunc_i64_i32(d2, t0); | |
552 | ||
553 | tcg_temp_free_i64(t0); | |
554 | tcg_temp_free_i64(t1); | |
555 | } | |
556 | ||
557 | /* Multiplier unit. */ | |
558 | static void dec_mul(DisasContext *dc) | |
559 | { | |
560 | TCGv d[2]; | |
561 | unsigned int subcode; | |
562 | ||
1567a005 | 563 | if ((dc->tb_flags & MSR_EE_FLAG) |
97f90cbf | 564 | && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) |
1567a005 EI |
565 | && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) { |
566 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); | |
567 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
568 | return; | |
569 | } | |
570 | ||
4acb54ba EI |
571 | subcode = dc->imm & 3; |
572 | d[0] = tcg_temp_new(); | |
573 | d[1] = tcg_temp_new(); | |
574 | ||
575 | if (dc->type_b) { | |
576 | LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm); | |
577 | t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc))); | |
578 | goto done; | |
579 | } | |
580 | ||
1567a005 EI |
581 | /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ |
582 | if (subcode >= 1 && subcode <= 3 | |
583 | && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) { | |
584 | /* nop??? */ | |
585 | } | |
586 | ||
4acb54ba EI |
587 | switch (subcode) { |
588 | case 0: | |
589 | LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); | |
590 | t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]); | |
591 | break; | |
592 | case 1: | |
593 | LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); | |
594 | t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
595 | break; | |
596 | case 2: | |
597 | LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); | |
598 | t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
599 | break; | |
600 | case 3: | |
601 | LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); | |
602 | t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
603 | break; | |
604 | default: | |
605 | cpu_abort(dc->env, "unknown MUL insn %x\n", subcode); | |
606 | break; | |
607 | } | |
608 | done: | |
609 | tcg_temp_free(d[0]); | |
610 | tcg_temp_free(d[1]); | |
611 | } | |
612 | ||
613 | /* Div unit. */ | |
614 | static void dec_div(DisasContext *dc) | |
615 | { | |
616 | unsigned int u; | |
617 | ||
618 | u = dc->imm & 2; | |
619 | LOG_DIS("div\n"); | |
620 | ||
97f90cbf | 621 | if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) |
1567a005 EI |
622 | && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) { |
623 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); | |
624 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
625 | } | |
626 | ||
4acb54ba EI |
627 | if (u) |
628 | gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); | |
629 | else | |
630 | gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); | |
631 | if (!dc->rd) | |
632 | tcg_gen_movi_tl(cpu_R[dc->rd], 0); | |
633 | } | |
634 | ||
635 | static void dec_barrel(DisasContext *dc) | |
636 | { | |
637 | TCGv t0; | |
638 | unsigned int s, t; | |
639 | ||
1567a005 | 640 | if ((dc->tb_flags & MSR_EE_FLAG) |
97f90cbf | 641 | && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) |
1567a005 EI |
642 | && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) { |
643 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); | |
644 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
645 | return; | |
646 | } | |
647 | ||
4acb54ba EI |
648 | s = dc->imm & (1 << 10); |
649 | t = dc->imm & (1 << 9); | |
650 | ||
651 | LOG_DIS("bs%s%s r%d r%d r%d\n", | |
652 | s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); | |
653 | ||
654 | t0 = tcg_temp_new(); | |
655 | ||
656 | tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc))); | |
657 | tcg_gen_andi_tl(t0, t0, 31); | |
658 | ||
659 | if (s) | |
660 | tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); | |
661 | else { | |
662 | if (t) | |
663 | tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); | |
664 | else | |
665 | tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); | |
666 | } | |
667 | } | |
668 | ||
669 | static void dec_bit(DisasContext *dc) | |
670 | { | |
671 | TCGv t0, t1; | |
672 | unsigned int op; | |
1567a005 | 673 | int mem_index = cpu_mmu_index(dc->env); |
4acb54ba EI |
674 | |
675 | op = dc->ir & ((1 << 8) - 1); | |
676 | switch (op) { | |
677 | case 0x21: | |
678 | /* src. */ | |
679 | t0 = tcg_temp_new(); | |
680 | ||
681 | LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); | |
682 | tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1); | |
683 | if (dc->rd) { | |
684 | t1 = tcg_temp_new(); | |
685 | read_carry(dc, t1); | |
686 | tcg_gen_shli_tl(t1, t1, 31); | |
687 | ||
688 | tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1); | |
689 | tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1); | |
690 | tcg_temp_free(t1); | |
691 | } | |
692 | ||
693 | /* Update carry. */ | |
694 | write_carry(dc, t0); | |
695 | tcg_temp_free(t0); | |
696 | break; | |
697 | ||
698 | case 0x1: | |
699 | case 0x41: | |
700 | /* srl. */ | |
701 | t0 = tcg_temp_new(); | |
702 | LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); | |
703 | ||
704 | /* Update carry. */ | |
705 | tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1); | |
706 | write_carry(dc, t0); | |
707 | tcg_temp_free(t0); | |
708 | if (dc->rd) { | |
709 | if (op == 0x41) | |
710 | tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1); | |
711 | else | |
712 | tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1); | |
713 | } | |
714 | break; | |
715 | case 0x60: | |
716 | LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra); | |
717 | tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); | |
718 | break; | |
719 | case 0x61: | |
720 | LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra); | |
721 | tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); | |
722 | break; | |
723 | case 0x64: | |
f062a3c7 EI |
724 | case 0x66: |
725 | case 0x74: | |
726 | case 0x76: | |
4acb54ba EI |
727 | /* wdc. */ |
728 | LOG_DIS("wdc r%d\n", dc->ra); | |
1567a005 EI |
729 | if ((dc->tb_flags & MSR_EE_FLAG) |
730 | && mem_index == MMU_USER_IDX) { | |
731 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); | |
732 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
733 | return; | |
734 | } | |
4acb54ba EI |
735 | break; |
736 | case 0x68: | |
737 | /* wic. */ | |
738 | LOG_DIS("wic r%d\n", dc->ra); | |
1567a005 EI |
739 | if ((dc->tb_flags & MSR_EE_FLAG) |
740 | && mem_index == MMU_USER_IDX) { | |
741 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); | |
742 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
743 | return; | |
744 | } | |
4acb54ba EI |
745 | break; |
746 | default: | |
747 | cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", | |
748 | dc->pc, op, dc->rd, dc->ra, dc->rb); | |
749 | break; | |
750 | } | |
751 | } | |
752 | ||
753 | static inline void sync_jmpstate(DisasContext *dc) | |
754 | { | |
844bab60 EI |
755 | if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { |
756 | if (dc->jmp == JMP_DIRECT) { | |
757 | tcg_gen_movi_tl(env_btaken, 1); | |
758 | } | |
23979dc5 EI |
759 | dc->jmp = JMP_INDIRECT; |
760 | tcg_gen_movi_tl(env_btarget, dc->jmp_pc); | |
4acb54ba EI |
761 | } |
762 | } | |
763 | ||
764 | static void dec_imm(DisasContext *dc) | |
765 | { | |
766 | LOG_DIS("imm %x\n", dc->imm << 16); | |
767 | tcg_gen_movi_tl(env_imm, (dc->imm << 16)); | |
768 | dc->tb_flags |= IMM_FLAG; | |
769 | dc->clear_imm = 0; | |
770 | } | |
771 | ||
772 | static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr, | |
773 | unsigned int size) | |
774 | { | |
775 | int mem_index = cpu_mmu_index(dc->env); | |
776 | ||
777 | if (size == 1) { | |
778 | tcg_gen_qemu_ld8u(dst, addr, mem_index); | |
779 | } else if (size == 2) { | |
780 | tcg_gen_qemu_ld16u(dst, addr, mem_index); | |
781 | } else if (size == 4) { | |
782 | tcg_gen_qemu_ld32u(dst, addr, mem_index); | |
783 | } else | |
784 | cpu_abort(dc->env, "Incorrect load size %d\n", size); | |
785 | } | |
786 | ||
787 | static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) | |
788 | { | |
789 | unsigned int extimm = dc->tb_flags & IMM_FLAG; | |
790 | ||
9ef55357 | 791 | /* Treat the common cases first. */ |
4acb54ba | 792 | if (!dc->type_b) { |
4b5ef0b5 EI |
793 | /* If any of the regs is r0, return a ptr to the other. */ |
794 | if (dc->ra == 0) { | |
795 | return &cpu_R[dc->rb]; | |
796 | } else if (dc->rb == 0) { | |
797 | return &cpu_R[dc->ra]; | |
798 | } | |
799 | ||
4acb54ba EI |
800 | *t = tcg_temp_new(); |
801 | tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]); | |
802 | return t; | |
803 | } | |
804 | /* Immediate. */ | |
805 | if (!extimm) { | |
806 | if (dc->imm == 0) { | |
807 | return &cpu_R[dc->ra]; | |
808 | } | |
809 | *t = tcg_temp_new(); | |
810 | tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm)); | |
811 | tcg_gen_add_tl(*t, cpu_R[dc->ra], *t); | |
812 | } else { | |
813 | *t = tcg_temp_new(); | |
814 | tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); | |
815 | } | |
816 | ||
817 | return t; | |
818 | } | |
819 | ||
9f8beb66 EI |
820 | static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size) |
821 | { | |
822 | if (size == 4) { | |
823 | tcg_gen_bswap32_tl(dst, src); | |
824 | } else if (size == 2) { | |
825 | TCGv t = tcg_temp_new(); | |
826 | ||
827 | /* bswap16 assumes the high bits are zero. */ | |
828 | tcg_gen_andi_tl(t, src, 0xffff); | |
829 | tcg_gen_bswap16_tl(dst, t); | |
830 | tcg_temp_free(t); | |
831 | } else { | |
832 | /* Ignore. | |
833 | cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size); | |
834 | */ | |
835 | } | |
836 | } | |
837 | ||
4acb54ba EI |
838 | static void dec_load(DisasContext *dc) |
839 | { | |
840 | TCGv t, *addr; | |
9f8beb66 | 841 | unsigned int size, rev = 0; |
4acb54ba EI |
842 | |
843 | size = 1 << (dc->opcode & 3); | |
9f8beb66 EI |
844 | |
845 | if (!dc->type_b) { | |
846 | rev = (dc->ir >> 9) & 1; | |
847 | } | |
848 | ||
0187688f | 849 | if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) |
97f90cbf | 850 | && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { |
0187688f EI |
851 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
852 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
853 | return; | |
854 | } | |
4acb54ba | 855 | |
9f8beb66 EI |
856 | LOG_DIS("l%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : ""); |
857 | ||
4acb54ba EI |
858 | t_sync_flags(dc); |
859 | addr = compute_ldst_addr(dc, &t); | |
860 | ||
9f8beb66 EI |
861 | /* |
862 | * When doing reverse accesses we need to do two things. | |
863 | * | |
864 | * 1. Reverse the address wrt endianess. | |
865 | * 2. Byteswap the data lanes on the way back into the CPU core. | |
866 | */ | |
867 | if (rev && size != 4) { | |
868 | /* Endian reverse the address. t is addr. */ | |
869 | switch (size) { | |
870 | case 1: | |
871 | { | |
872 | /* 00 -> 11 | |
873 | 01 -> 10 | |
874 | 10 -> 10 | |
875 | 11 -> 00 */ | |
876 | TCGv low = tcg_temp_new(); | |
877 | ||
878 | /* Force addr into the temp. */ | |
879 | if (addr != &t) { | |
880 | t = tcg_temp_new(); | |
881 | tcg_gen_mov_tl(t, *addr); | |
882 | addr = &t; | |
883 | } | |
884 | ||
885 | tcg_gen_andi_tl(low, t, 3); | |
886 | tcg_gen_sub_tl(low, tcg_const_tl(3), low); | |
887 | tcg_gen_andi_tl(t, t, ~3); | |
888 | tcg_gen_or_tl(t, t, low); | |
889 | tcg_gen_mov_tl(env_debug, low); | |
890 | tcg_gen_mov_tl(env_imm, t); | |
891 | tcg_temp_free(low); | |
892 | break; | |
893 | } | |
894 | ||
895 | case 2: | |
896 | /* 00 -> 10 | |
897 | 10 -> 00. */ | |
898 | /* Force addr into the temp. */ | |
899 | if (addr != &t) { | |
900 | t = tcg_temp_new(); | |
901 | tcg_gen_xori_tl(t, *addr, 2); | |
902 | addr = &t; | |
903 | } else { | |
904 | tcg_gen_xori_tl(t, t, 2); | |
905 | } | |
906 | break; | |
907 | default: | |
908 | cpu_abort(dc->env, "Invalid reverse size\n"); | |
909 | break; | |
910 | } | |
911 | } | |
912 | ||
4acb54ba EI |
913 | /* If we get a fault on a dslot, the jmpstate better be in sync. */ |
914 | sync_jmpstate(dc); | |
968a40f6 EI |
915 | |
916 | /* Verify alignment if needed. */ | |
917 | if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { | |
a12f6507 EI |
918 | TCGv v = tcg_temp_new(); |
919 | ||
920 | /* | |
921 | * Microblaze gives MMU faults priority over faults due to | |
922 | * unaligned addresses. That's why we speculatively do the load | |
923 | * into v. If the load succeeds, we verify alignment of the | |
924 | * address and if that succeeds we write into the destination reg. | |
925 | */ | |
926 | gen_load(dc, v, *addr, size); | |
927 | ||
928 | tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); | |
968a40f6 | 929 | gen_helper_memalign(*addr, tcg_const_tl(dc->rd), |
3aa80988 | 930 | tcg_const_tl(0), tcg_const_tl(size - 1)); |
9f8beb66 EI |
931 | if (dc->rd) { |
932 | if (rev) { | |
933 | dec_byteswap(dc, cpu_R[dc->rd], v, size); | |
934 | } else { | |
935 | tcg_gen_mov_tl(cpu_R[dc->rd], v); | |
936 | } | |
937 | } | |
a12f6507 | 938 | tcg_temp_free(v); |
968a40f6 | 939 | } else { |
a12f6507 EI |
940 | if (dc->rd) { |
941 | gen_load(dc, cpu_R[dc->rd], *addr, size); | |
9f8beb66 EI |
942 | if (rev) { |
943 | dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size); | |
944 | } | |
a12f6507 | 945 | } else { |
9f8beb66 | 946 | /* We are loading into r0, no need to reverse. */ |
a12f6507 EI |
947 | gen_load(dc, env_imm, *addr, size); |
948 | } | |
4acb54ba EI |
949 | } |
950 | ||
951 | if (addr == &t) | |
952 | tcg_temp_free(t); | |
953 | } | |
954 | ||
955 | static void gen_store(DisasContext *dc, TCGv addr, TCGv val, | |
956 | unsigned int size) | |
957 | { | |
958 | int mem_index = cpu_mmu_index(dc->env); | |
959 | ||
960 | if (size == 1) | |
961 | tcg_gen_qemu_st8(val, addr, mem_index); | |
962 | else if (size == 2) { | |
963 | tcg_gen_qemu_st16(val, addr, mem_index); | |
964 | } else if (size == 4) { | |
965 | tcg_gen_qemu_st32(val, addr, mem_index); | |
966 | } else | |
967 | cpu_abort(dc->env, "Incorrect store size %d\n", size); | |
968 | } | |
969 | ||
970 | static void dec_store(DisasContext *dc) | |
971 | { | |
972 | TCGv t, *addr; | |
9f8beb66 | 973 | unsigned int size, rev = 0; |
4acb54ba EI |
974 | |
975 | size = 1 << (dc->opcode & 3); | |
9f8beb66 EI |
976 | if (!dc->type_b) { |
977 | rev = (dc->ir >> 9) & 1; | |
978 | } | |
4acb54ba | 979 | |
0187688f | 980 | if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) |
97f90cbf | 981 | && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { |
0187688f EI |
982 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
983 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
984 | return; | |
985 | } | |
986 | ||
9f8beb66 | 987 | LOG_DIS("s%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : ""); |
4acb54ba EI |
988 | t_sync_flags(dc); |
989 | /* If we get a fault on a dslot, the jmpstate better be in sync. */ | |
990 | sync_jmpstate(dc); | |
991 | addr = compute_ldst_addr(dc, &t); | |
968a40f6 | 992 | |
9f8beb66 EI |
993 | if (rev && size != 4) { |
994 | /* Endian reverse the address. t is addr. */ | |
995 | switch (size) { | |
996 | case 1: | |
997 | { | |
998 | /* 00 -> 11 | |
999 | 01 -> 10 | |
1000 | 10 -> 10 | |
1001 | 11 -> 00 */ | |
1002 | TCGv low = tcg_temp_new(); | |
1003 | ||
1004 | /* Force addr into the temp. */ | |
1005 | if (addr != &t) { | |
1006 | t = tcg_temp_new(); | |
1007 | tcg_gen_mov_tl(t, *addr); | |
1008 | addr = &t; | |
1009 | } | |
1010 | ||
1011 | tcg_gen_andi_tl(low, t, 3); | |
1012 | tcg_gen_sub_tl(low, tcg_const_tl(3), low); | |
1013 | tcg_gen_andi_tl(t, t, ~3); | |
1014 | tcg_gen_or_tl(t, t, low); | |
1015 | tcg_gen_mov_tl(env_debug, low); | |
1016 | tcg_gen_mov_tl(env_imm, t); | |
1017 | tcg_temp_free(low); | |
1018 | break; | |
1019 | } | |
1020 | ||
1021 | case 2: | |
1022 | /* 00 -> 10 | |
1023 | 10 -> 00. */ | |
1024 | /* Force addr into the temp. */ | |
1025 | if (addr != &t) { | |
1026 | t = tcg_temp_new(); | |
1027 | tcg_gen_xori_tl(t, *addr, 2); | |
1028 | addr = &t; | |
1029 | } else { | |
1030 | tcg_gen_xori_tl(t, t, 2); | |
1031 | } | |
1032 | break; | |
1033 | default: | |
1034 | cpu_abort(dc->env, "Invalid reverse size\n"); | |
1035 | break; | |
1036 | } | |
1037 | ||
1038 | if (size != 1) { | |
1039 | TCGv bs_data = tcg_temp_new(); | |
1040 | dec_byteswap(dc, bs_data, cpu_R[dc->rd], size); | |
1041 | gen_store(dc, *addr, bs_data, size); | |
1042 | tcg_temp_free(bs_data); | |
1043 | } else { | |
1044 | gen_store(dc, *addr, cpu_R[dc->rd], size); | |
1045 | } | |
1046 | } else { | |
1047 | if (rev) { | |
1048 | TCGv bs_data = tcg_temp_new(); | |
1049 | dec_byteswap(dc, bs_data, cpu_R[dc->rd], size); | |
1050 | gen_store(dc, *addr, bs_data, size); | |
1051 | tcg_temp_free(bs_data); | |
1052 | } else { | |
1053 | gen_store(dc, *addr, cpu_R[dc->rd], size); | |
1054 | } | |
1055 | } | |
a12f6507 | 1056 | |
968a40f6 EI |
1057 | /* Verify alignment if needed. */ |
1058 | if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { | |
a12f6507 EI |
1059 | tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); |
1060 | /* FIXME: if the alignment is wrong, we should restore the value | |
9f8beb66 EI |
1061 | * in memory. One possible way to acheive this is to probe |
1062 | * the MMU prior to the memaccess, thay way we could put | |
1063 | * the alignment checks in between the probe and the mem | |
1064 | * access. | |
a12f6507 | 1065 | */ |
968a40f6 | 1066 | gen_helper_memalign(*addr, tcg_const_tl(dc->rd), |
3aa80988 | 1067 | tcg_const_tl(1), tcg_const_tl(size - 1)); |
968a40f6 EI |
1068 | } |
1069 | ||
4acb54ba EI |
1070 | if (addr == &t) |
1071 | tcg_temp_free(t); | |
1072 | } | |
1073 | ||
1074 | static inline void eval_cc(DisasContext *dc, unsigned int cc, | |
1075 | TCGv d, TCGv a, TCGv b) | |
1076 | { | |
4acb54ba EI |
1077 | switch (cc) { |
1078 | case CC_EQ: | |
b2565c69 | 1079 | tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b); |
4acb54ba EI |
1080 | break; |
1081 | case CC_NE: | |
b2565c69 | 1082 | tcg_gen_setcond_tl(TCG_COND_NE, d, a, b); |
4acb54ba EI |
1083 | break; |
1084 | case CC_LT: | |
b2565c69 | 1085 | tcg_gen_setcond_tl(TCG_COND_LT, d, a, b); |
4acb54ba EI |
1086 | break; |
1087 | case CC_LE: | |
b2565c69 | 1088 | tcg_gen_setcond_tl(TCG_COND_LE, d, a, b); |
4acb54ba EI |
1089 | break; |
1090 | case CC_GE: | |
b2565c69 | 1091 | tcg_gen_setcond_tl(TCG_COND_GE, d, a, b); |
4acb54ba EI |
1092 | break; |
1093 | case CC_GT: | |
b2565c69 | 1094 | tcg_gen_setcond_tl(TCG_COND_GT, d, a, b); |
4acb54ba EI |
1095 | break; |
1096 | default: | |
1097 | cpu_abort(dc->env, "Unknown condition code %x.\n", cc); | |
1098 | break; | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false) | |
1103 | { | |
1104 | int l1; | |
1105 | ||
1106 | l1 = gen_new_label(); | |
1107 | /* Conditional jmp. */ | |
1108 | tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false); | |
1109 | tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1); | |
1110 | tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true); | |
1111 | gen_set_label(l1); | |
1112 | } | |
1113 | ||
1114 | static void dec_bcc(DisasContext *dc) | |
1115 | { | |
1116 | unsigned int cc; | |
1117 | unsigned int dslot; | |
1118 | ||
1119 | cc = EXTRACT_FIELD(dc->ir, 21, 23); | |
1120 | dslot = dc->ir & (1 << 25); | |
1121 | LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm); | |
1122 | ||
1123 | dc->delayed_branch = 1; | |
1124 | if (dslot) { | |
1125 | dc->delayed_branch = 2; | |
1126 | dc->tb_flags |= D_FLAG; | |
1127 | tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), | |
1128 | cpu_env, offsetof(CPUState, bimm)); | |
1129 | } | |
1130 | ||
61204ce8 EI |
1131 | if (dec_alu_op_b_is_small_imm(dc)) { |
1132 | int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ | |
1133 | ||
1134 | tcg_gen_movi_tl(env_btarget, dc->pc + offset); | |
844bab60 | 1135 | dc->jmp = JMP_DIRECT_CC; |
23979dc5 | 1136 | dc->jmp_pc = dc->pc + offset; |
61204ce8 | 1137 | } else { |
23979dc5 | 1138 | dc->jmp = JMP_INDIRECT; |
61204ce8 EI |
1139 | tcg_gen_movi_tl(env_btarget, dc->pc); |
1140 | tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc))); | |
1141 | } | |
61204ce8 | 1142 | eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0)); |
4acb54ba EI |
1143 | } |
1144 | ||
1145 | static void dec_br(DisasContext *dc) | |
1146 | { | |
1147 | unsigned int dslot, link, abs; | |
ff21f70a | 1148 | int mem_index = cpu_mmu_index(dc->env); |
4acb54ba EI |
1149 | |
1150 | dslot = dc->ir & (1 << 20); | |
1151 | abs = dc->ir & (1 << 19); | |
1152 | link = dc->ir & (1 << 18); | |
1153 | LOG_DIS("br%s%s%s%s imm=%x\n", | |
1154 | abs ? "a" : "", link ? "l" : "", | |
1155 | dc->type_b ? "i" : "", dslot ? "d" : "", | |
1156 | dc->imm); | |
1157 | ||
1158 | dc->delayed_branch = 1; | |
1159 | if (dslot) { | |
1160 | dc->delayed_branch = 2; | |
1161 | dc->tb_flags |= D_FLAG; | |
1162 | tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), | |
1163 | cpu_env, offsetof(CPUState, bimm)); | |
1164 | } | |
1165 | if (link && dc->rd) | |
1166 | tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc); | |
1167 | ||
1168 | dc->jmp = JMP_INDIRECT; | |
1169 | if (abs) { | |
1170 | tcg_gen_movi_tl(env_btaken, 1); | |
1171 | tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc))); | |
ff21f70a EI |
1172 | if (link && !dslot) { |
1173 | if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) | |
1174 | t_gen_raise_exception(dc, EXCP_BREAK); | |
1175 | if (dc->imm == 0) { | |
1176 | if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) { | |
1177 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); | |
1178 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
1179 | return; | |
1180 | } | |
1181 | ||
1182 | t_gen_raise_exception(dc, EXCP_DEBUG); | |
1183 | } | |
1184 | } | |
4acb54ba | 1185 | } else { |
61204ce8 EI |
1186 | if (dec_alu_op_b_is_small_imm(dc)) { |
1187 | dc->jmp = JMP_DIRECT; | |
1188 | dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); | |
1189 | } else { | |
4acb54ba EI |
1190 | tcg_gen_movi_tl(env_btaken, 1); |
1191 | tcg_gen_movi_tl(env_btarget, dc->pc); | |
1192 | tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc))); | |
4acb54ba EI |
1193 | } |
1194 | } | |
1195 | } | |
1196 | ||
1197 | static inline void do_rti(DisasContext *dc) | |
1198 | { | |
1199 | TCGv t0, t1; | |
1200 | t0 = tcg_temp_new(); | |
1201 | t1 = tcg_temp_new(); | |
1202 | tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1); | |
1203 | tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE); | |
1204 | tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); | |
1205 | ||
1206 | tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); | |
1207 | tcg_gen_or_tl(t1, t1, t0); | |
1208 | msr_write(dc, t1); | |
1209 | tcg_temp_free(t1); | |
1210 | tcg_temp_free(t0); | |
1211 | dc->tb_flags &= ~DRTI_FLAG; | |
1212 | } | |
1213 | ||
1214 | static inline void do_rtb(DisasContext *dc) | |
1215 | { | |
1216 | TCGv t0, t1; | |
1217 | t0 = tcg_temp_new(); | |
1218 | t1 = tcg_temp_new(); | |
1219 | tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP); | |
1220 | tcg_gen_shri_tl(t0, t1, 1); | |
1221 | tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); | |
1222 | ||
1223 | tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); | |
1224 | tcg_gen_or_tl(t1, t1, t0); | |
1225 | msr_write(dc, t1); | |
1226 | tcg_temp_free(t1); | |
1227 | tcg_temp_free(t0); | |
1228 | dc->tb_flags &= ~DRTB_FLAG; | |
1229 | } | |
1230 | ||
1231 | static inline void do_rte(DisasContext *dc) | |
1232 | { | |
1233 | TCGv t0, t1; | |
1234 | t0 = tcg_temp_new(); | |
1235 | t1 = tcg_temp_new(); | |
1236 | ||
1237 | tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE); | |
1238 | tcg_gen_andi_tl(t1, t1, ~MSR_EIP); | |
1239 | tcg_gen_shri_tl(t0, t1, 1); | |
1240 | tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); | |
1241 | ||
1242 | tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); | |
1243 | tcg_gen_or_tl(t1, t1, t0); | |
1244 | msr_write(dc, t1); | |
1245 | tcg_temp_free(t1); | |
1246 | tcg_temp_free(t0); | |
1247 | dc->tb_flags &= ~DRTE_FLAG; | |
1248 | } | |
1249 | ||
1250 | static void dec_rts(DisasContext *dc) | |
1251 | { | |
1252 | unsigned int b_bit, i_bit, e_bit; | |
1567a005 | 1253 | int mem_index = cpu_mmu_index(dc->env); |
4acb54ba EI |
1254 | |
1255 | i_bit = dc->ir & (1 << 21); | |
1256 | b_bit = dc->ir & (1 << 22); | |
1257 | e_bit = dc->ir & (1 << 23); | |
1258 | ||
1259 | dc->delayed_branch = 2; | |
1260 | dc->tb_flags |= D_FLAG; | |
1261 | tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), | |
1262 | cpu_env, offsetof(CPUState, bimm)); | |
1263 | ||
1264 | if (i_bit) { | |
1265 | LOG_DIS("rtid ir=%x\n", dc->ir); | |
1567a005 EI |
1266 | if ((dc->tb_flags & MSR_EE_FLAG) |
1267 | && mem_index == MMU_USER_IDX) { | |
1268 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); | |
1269 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
1270 | } | |
4acb54ba EI |
1271 | dc->tb_flags |= DRTI_FLAG; |
1272 | } else if (b_bit) { | |
1273 | LOG_DIS("rtbd ir=%x\n", dc->ir); | |
1567a005 EI |
1274 | if ((dc->tb_flags & MSR_EE_FLAG) |
1275 | && mem_index == MMU_USER_IDX) { | |
1276 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); | |
1277 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
1278 | } | |
4acb54ba EI |
1279 | dc->tb_flags |= DRTB_FLAG; |
1280 | } else if (e_bit) { | |
1281 | LOG_DIS("rted ir=%x\n", dc->ir); | |
1567a005 EI |
1282 | if ((dc->tb_flags & MSR_EE_FLAG) |
1283 | && mem_index == MMU_USER_IDX) { | |
1284 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); | |
1285 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
1286 | } | |
4acb54ba EI |
1287 | dc->tb_flags |= DRTE_FLAG; |
1288 | } else | |
1289 | LOG_DIS("rts ir=%x\n", dc->ir); | |
1290 | ||
23979dc5 | 1291 | dc->jmp = JMP_INDIRECT; |
4acb54ba EI |
1292 | tcg_gen_movi_tl(env_btaken, 1); |
1293 | tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc))); | |
1294 | } | |
1295 | ||
97694c57 EI |
1296 | static int dec_check_fpuv2(DisasContext *dc) |
1297 | { | |
1298 | int r; | |
1299 | ||
1300 | r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK; | |
1301 | ||
1302 | if (!r && (dc->tb_flags & MSR_EE_FLAG)) { | |
1303 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); | |
1304 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
1305 | } | |
1306 | return r; | |
1307 | } | |
1308 | ||
1567a005 EI |
1309 | static void dec_fpu(DisasContext *dc) |
1310 | { | |
97694c57 EI |
1311 | unsigned int fpu_insn; |
1312 | ||
1567a005 | 1313 | if ((dc->tb_flags & MSR_EE_FLAG) |
97f90cbf | 1314 | && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) |
1567a005 | 1315 | && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) { |
97694c57 | 1316 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1567a005 EI |
1317 | t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1318 | return; | |
1319 | } | |
1320 | ||
97694c57 EI |
1321 | fpu_insn = (dc->ir >> 7) & 7; |
1322 | ||
1323 | switch (fpu_insn) { | |
1324 | case 0: | |
1325 | gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
1326 | break; | |
1327 | ||
1328 | case 1: | |
1329 | gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
1330 | break; | |
1331 | ||
1332 | case 2: | |
1333 | gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
1334 | break; | |
1335 | ||
1336 | case 3: | |
1337 | gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); | |
1338 | break; | |
1339 | ||
1340 | case 4: | |
1341 | switch ((dc->ir >> 4) & 7) { | |
1342 | case 0: | |
1343 | gen_helper_fcmp_un(cpu_R[dc->rd], | |
1344 | cpu_R[dc->ra], cpu_R[dc->rb]); | |
1345 | break; | |
1346 | case 1: | |
1347 | gen_helper_fcmp_lt(cpu_R[dc->rd], | |
1348 | cpu_R[dc->ra], cpu_R[dc->rb]); | |
1349 | break; | |
1350 | case 2: | |
1351 | gen_helper_fcmp_eq(cpu_R[dc->rd], | |
1352 | cpu_R[dc->ra], cpu_R[dc->rb]); | |
1353 | break; | |
1354 | case 3: | |
1355 | gen_helper_fcmp_le(cpu_R[dc->rd], | |
1356 | cpu_R[dc->ra], cpu_R[dc->rb]); | |
1357 | break; | |
1358 | case 4: | |
1359 | gen_helper_fcmp_gt(cpu_R[dc->rd], | |
1360 | cpu_R[dc->ra], cpu_R[dc->rb]); | |
1361 | break; | |
1362 | case 5: | |
1363 | gen_helper_fcmp_ne(cpu_R[dc->rd], | |
1364 | cpu_R[dc->ra], cpu_R[dc->rb]); | |
1365 | break; | |
1366 | case 6: | |
1367 | gen_helper_fcmp_ge(cpu_R[dc->rd], | |
1368 | cpu_R[dc->ra], cpu_R[dc->rb]); | |
1369 | break; | |
1370 | default: | |
1371 | qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n", | |
1372 | fpu_insn, dc->pc, dc->opcode); | |
1373 | dc->abort_at_next_insn = 1; | |
1374 | break; | |
1375 | } | |
1376 | break; | |
1377 | ||
1378 | case 5: | |
1379 | if (!dec_check_fpuv2(dc)) { | |
1380 | return; | |
1381 | } | |
1382 | gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]); | |
1383 | break; | |
1384 | ||
1385 | case 6: | |
1386 | if (!dec_check_fpuv2(dc)) { | |
1387 | return; | |
1388 | } | |
1389 | gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]); | |
1390 | break; | |
1391 | ||
1392 | case 7: | |
1393 | if (!dec_check_fpuv2(dc)) { | |
1394 | return; | |
1395 | } | |
1396 | gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]); | |
1397 | break; | |
1398 | ||
1399 | default: | |
1400 | qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n", | |
1401 | fpu_insn, dc->pc, dc->opcode); | |
1402 | dc->abort_at_next_insn = 1; | |
1403 | break; | |
1404 | } | |
1567a005 EI |
1405 | } |
1406 | ||
4acb54ba EI |
1407 | static void dec_null(DisasContext *dc) |
1408 | { | |
02b33596 EI |
1409 | if ((dc->tb_flags & MSR_EE_FLAG) |
1410 | && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { | |
1411 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); | |
1412 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
1413 | return; | |
1414 | } | |
4acb54ba EI |
1415 | qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode); |
1416 | dc->abort_at_next_insn = 1; | |
1417 | } | |
1418 | ||
1419 | static struct decoder_info { | |
1420 | struct { | |
1421 | uint32_t bits; | |
1422 | uint32_t mask; | |
1423 | }; | |
1424 | void (*dec)(DisasContext *dc); | |
1425 | } decinfo[] = { | |
1426 | {DEC_ADD, dec_add}, | |
1427 | {DEC_SUB, dec_sub}, | |
1428 | {DEC_AND, dec_and}, | |
1429 | {DEC_XOR, dec_xor}, | |
1430 | {DEC_OR, dec_or}, | |
1431 | {DEC_BIT, dec_bit}, | |
1432 | {DEC_BARREL, dec_barrel}, | |
1433 | {DEC_LD, dec_load}, | |
1434 | {DEC_ST, dec_store}, | |
1435 | {DEC_IMM, dec_imm}, | |
1436 | {DEC_BR, dec_br}, | |
1437 | {DEC_BCC, dec_bcc}, | |
1438 | {DEC_RTS, dec_rts}, | |
1567a005 | 1439 | {DEC_FPU, dec_fpu}, |
4acb54ba EI |
1440 | {DEC_MUL, dec_mul}, |
1441 | {DEC_DIV, dec_div}, | |
1442 | {DEC_MSR, dec_msr}, | |
1443 | {{0, 0}, dec_null} | |
1444 | }; | |
1445 | ||
1446 | static inline void decode(DisasContext *dc) | |
1447 | { | |
1448 | uint32_t ir; | |
1449 | int i; | |
1450 | ||
1451 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) | |
1452 | tcg_gen_debug_insn_start(dc->pc); | |
1453 | ||
1454 | dc->ir = ir = ldl_code(dc->pc); | |
1455 | LOG_DIS("%8.8x\t", dc->ir); | |
1456 | ||
1457 | if (dc->ir) | |
1458 | dc->nr_nops = 0; | |
1459 | else { | |
1567a005 | 1460 | if ((dc->tb_flags & MSR_EE_FLAG) |
97f90cbf EI |
1461 | && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) |
1462 | && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) { | |
1567a005 EI |
1463 | tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1464 | t_gen_raise_exception(dc, EXCP_HW_EXCP); | |
1465 | return; | |
1466 | } | |
1467 | ||
4acb54ba EI |
1468 | LOG_DIS("nr_nops=%d\t", dc->nr_nops); |
1469 | dc->nr_nops++; | |
1470 | if (dc->nr_nops > 4) | |
1471 | cpu_abort(dc->env, "fetching nop sequence\n"); | |
1472 | } | |
1473 | /* bit 2 seems to indicate insn type. */ | |
1474 | dc->type_b = ir & (1 << 29); | |
1475 | ||
1476 | dc->opcode = EXTRACT_FIELD(ir, 26, 31); | |
1477 | dc->rd = EXTRACT_FIELD(ir, 21, 25); | |
1478 | dc->ra = EXTRACT_FIELD(ir, 16, 20); | |
1479 | dc->rb = EXTRACT_FIELD(ir, 11, 15); | |
1480 | dc->imm = EXTRACT_FIELD(ir, 0, 15); | |
1481 | ||
1482 | /* Large switch for all insns. */ | |
1483 | for (i = 0; i < ARRAY_SIZE(decinfo); i++) { | |
1484 | if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { | |
1485 | decinfo[i].dec(dc); | |
1486 | break; | |
1487 | } | |
1488 | } | |
1489 | } | |
1490 | ||
4acb54ba EI |
1491 | static void check_breakpoint(CPUState *env, DisasContext *dc) |
1492 | { | |
1493 | CPUBreakpoint *bp; | |
1494 | ||
72cf2d4f BS |
1495 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
1496 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
4acb54ba EI |
1497 | if (bp->pc == dc->pc) { |
1498 | t_gen_raise_exception(dc, EXCP_DEBUG); | |
1499 | dc->is_jmp = DISAS_UPDATE; | |
1500 | } | |
1501 | } | |
1502 | } | |
1503 | } | |
1504 | ||
1505 | /* generate intermediate code for basic block 'tb'. */ | |
1506 | static void | |
1507 | gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, | |
1508 | int search_pc) | |
1509 | { | |
1510 | uint16_t *gen_opc_end; | |
1511 | uint32_t pc_start; | |
1512 | int j, lj; | |
1513 | struct DisasContext ctx; | |
1514 | struct DisasContext *dc = &ctx; | |
1515 | uint32_t next_page_start, org_flags; | |
1516 | target_ulong npc; | |
1517 | int num_insns; | |
1518 | int max_insns; | |
1519 | ||
1520 | qemu_log_try_set_file(stderr); | |
1521 | ||
1522 | pc_start = tb->pc; | |
1523 | dc->env = env; | |
1524 | dc->tb = tb; | |
1525 | org_flags = dc->synced_flags = dc->tb_flags = tb->flags; | |
1526 | ||
1527 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; | |
1528 | ||
1529 | dc->is_jmp = DISAS_NEXT; | |
1530 | dc->jmp = 0; | |
1531 | dc->delayed_branch = !!(dc->tb_flags & D_FLAG); | |
23979dc5 EI |
1532 | if (dc->delayed_branch) { |
1533 | dc->jmp = JMP_INDIRECT; | |
1534 | } | |
4acb54ba | 1535 | dc->pc = pc_start; |
4acb54ba EI |
1536 | dc->singlestep_enabled = env->singlestep_enabled; |
1537 | dc->cpustate_changed = 0; | |
1538 | dc->abort_at_next_insn = 0; | |
1539 | dc->nr_nops = 0; | |
1540 | ||
1541 | if (pc_start & 3) | |
1542 | cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start); | |
1543 | ||
1544 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
1545 | #if !SIM_COMPAT | |
1546 | qemu_log("--------------\n"); | |
1547 | log_cpu_state(env, 0); | |
1548 | #endif | |
1549 | } | |
1550 | ||
1551 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
1552 | lj = -1; | |
1553 | num_insns = 0; | |
1554 | max_insns = tb->cflags & CF_COUNT_MASK; | |
1555 | if (max_insns == 0) | |
1556 | max_insns = CF_COUNT_MASK; | |
1557 | ||
1558 | gen_icount_start(); | |
1559 | do | |
1560 | { | |
1561 | #if SIM_COMPAT | |
1562 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
1563 | tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); | |
1564 | gen_helper_debug(); | |
1565 | } | |
1566 | #endif | |
1567 | check_breakpoint(env, dc); | |
1568 | ||
1569 | if (search_pc) { | |
1570 | j = gen_opc_ptr - gen_opc_buf; | |
1571 | if (lj < j) { | |
1572 | lj++; | |
1573 | while (lj < j) | |
1574 | gen_opc_instr_start[lj++] = 0; | |
1575 | } | |
1576 | gen_opc_pc[lj] = dc->pc; | |
1577 | gen_opc_instr_start[lj] = 1; | |
1578 | gen_opc_icount[lj] = num_insns; | |
1579 | } | |
1580 | ||
1581 | /* Pretty disas. */ | |
1582 | LOG_DIS("%8.8x:\t", dc->pc); | |
1583 | ||
1584 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) | |
1585 | gen_io_start(); | |
1586 | ||
1587 | dc->clear_imm = 1; | |
1588 | decode(dc); | |
1589 | if (dc->clear_imm) | |
1590 | dc->tb_flags &= ~IMM_FLAG; | |
4acb54ba EI |
1591 | dc->pc += 4; |
1592 | num_insns++; | |
1593 | ||
1594 | if (dc->delayed_branch) { | |
1595 | dc->delayed_branch--; | |
1596 | if (!dc->delayed_branch) { | |
1597 | if (dc->tb_flags & DRTI_FLAG) | |
1598 | do_rti(dc); | |
1599 | if (dc->tb_flags & DRTB_FLAG) | |
1600 | do_rtb(dc); | |
1601 | if (dc->tb_flags & DRTE_FLAG) | |
1602 | do_rte(dc); | |
1603 | /* Clear the delay slot flag. */ | |
1604 | dc->tb_flags &= ~D_FLAG; | |
1605 | /* If it is a direct jump, try direct chaining. */ | |
23979dc5 | 1606 | if (dc->jmp == JMP_INDIRECT) { |
4acb54ba EI |
1607 | eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc)); |
1608 | dc->is_jmp = DISAS_JUMP; | |
23979dc5 | 1609 | } else if (dc->jmp == JMP_DIRECT) { |
844bab60 EI |
1610 | t_sync_flags(dc); |
1611 | gen_goto_tb(dc, 0, dc->jmp_pc); | |
1612 | dc->is_jmp = DISAS_TB_JUMP; | |
1613 | } else if (dc->jmp == JMP_DIRECT_CC) { | |
23979dc5 EI |
1614 | int l1; |
1615 | ||
1616 | t_sync_flags(dc); | |
1617 | l1 = gen_new_label(); | |
1618 | /* Conditional jmp. */ | |
1619 | tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1); | |
1620 | gen_goto_tb(dc, 1, dc->pc); | |
1621 | gen_set_label(l1); | |
1622 | gen_goto_tb(dc, 0, dc->jmp_pc); | |
1623 | ||
1624 | dc->is_jmp = DISAS_TB_JUMP; | |
4acb54ba EI |
1625 | } |
1626 | break; | |
1627 | } | |
1628 | } | |
1629 | if (env->singlestep_enabled) | |
1630 | break; | |
1631 | } while (!dc->is_jmp && !dc->cpustate_changed | |
1632 | && gen_opc_ptr < gen_opc_end | |
1633 | && !singlestep | |
1634 | && (dc->pc < next_page_start) | |
1635 | && num_insns < max_insns); | |
1636 | ||
1637 | npc = dc->pc; | |
844bab60 | 1638 | if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { |
4acb54ba EI |
1639 | if (dc->tb_flags & D_FLAG) { |
1640 | dc->is_jmp = DISAS_UPDATE; | |
1641 | tcg_gen_movi_tl(cpu_SR[SR_PC], npc); | |
1642 | sync_jmpstate(dc); | |
1643 | } else | |
1644 | npc = dc->jmp_pc; | |
1645 | } | |
1646 | ||
1647 | if (tb->cflags & CF_LAST_IO) | |
1648 | gen_io_end(); | |
1649 | /* Force an update if the per-tb cpu state has changed. */ | |
1650 | if (dc->is_jmp == DISAS_NEXT | |
1651 | && (dc->cpustate_changed || org_flags != dc->tb_flags)) { | |
1652 | dc->is_jmp = DISAS_UPDATE; | |
1653 | tcg_gen_movi_tl(cpu_SR[SR_PC], npc); | |
1654 | } | |
1655 | t_sync_flags(dc); | |
1656 | ||
1657 | if (unlikely(env->singlestep_enabled)) { | |
1658 | t_gen_raise_exception(dc, EXCP_DEBUG); | |
1659 | if (dc->is_jmp == DISAS_NEXT) | |
1660 | tcg_gen_movi_tl(cpu_SR[SR_PC], npc); | |
1661 | } else { | |
1662 | switch(dc->is_jmp) { | |
1663 | case DISAS_NEXT: | |
1664 | gen_goto_tb(dc, 1, npc); | |
1665 | break; | |
1666 | default: | |
1667 | case DISAS_JUMP: | |
1668 | case DISAS_UPDATE: | |
1669 | /* indicate that the hash table must be used | |
1670 | to find the next TB */ | |
1671 | tcg_gen_exit_tb(0); | |
1672 | break; | |
1673 | case DISAS_TB_JUMP: | |
1674 | /* nothing more to generate */ | |
1675 | break; | |
1676 | } | |
1677 | } | |
1678 | gen_icount_end(tb, num_insns); | |
1679 | *gen_opc_ptr = INDEX_op_end; | |
1680 | if (search_pc) { | |
1681 | j = gen_opc_ptr - gen_opc_buf; | |
1682 | lj++; | |
1683 | while (lj <= j) | |
1684 | gen_opc_instr_start[lj++] = 0; | |
1685 | } else { | |
1686 | tb->size = dc->pc - pc_start; | |
1687 | tb->icount = num_insns; | |
1688 | } | |
1689 | ||
1690 | #ifdef DEBUG_DISAS | |
1691 | #if !SIM_COMPAT | |
1692 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
1693 | qemu_log("\n"); | |
1694 | #if DISAS_GNU | |
1695 | log_target_disas(pc_start, dc->pc - pc_start, 0); | |
1696 | #endif | |
e6aa0f11 | 1697 | qemu_log("\nisize=%d osize=%td\n", |
4acb54ba EI |
1698 | dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); |
1699 | } | |
1700 | #endif | |
1701 | #endif | |
1702 | assert(!dc->abort_at_next_insn); | |
1703 | } | |
1704 | ||
1705 | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) | |
1706 | { | |
1707 | gen_intermediate_code_internal(env, tb, 0); | |
1708 | } | |
1709 | ||
1710 | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) | |
1711 | { | |
1712 | gen_intermediate_code_internal(env, tb, 1); | |
1713 | } | |
1714 | ||
9a78eead | 1715 | void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf, |
4acb54ba EI |
1716 | int flags) |
1717 | { | |
1718 | int i; | |
1719 | ||
1720 | if (!env || !f) | |
1721 | return; | |
1722 | ||
1723 | cpu_fprintf(f, "IN: PC=%x %s\n", | |
1724 | env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); | |
97694c57 | 1725 | cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n", |
4c24aa0a | 1726 | env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], |
97694c57 | 1727 | env->debug, env->imm, env->iflags, env->sregs[SR_FSR]); |
17c52a43 | 1728 | cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", |
4acb54ba EI |
1729 | env->btaken, env->btarget, |
1730 | (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", | |
17c52a43 EI |
1731 | (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", |
1732 | (env->sregs[SR_MSR] & MSR_EIP), | |
1733 | (env->sregs[SR_MSR] & MSR_IE)); | |
1734 | ||
4acb54ba EI |
1735 | for (i = 0; i < 32; i++) { |
1736 | cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); | |
1737 | if ((i + 1) % 4 == 0) | |
1738 | cpu_fprintf(f, "\n"); | |
1739 | } | |
1740 | cpu_fprintf(f, "\n\n"); | |
1741 | } | |
1742 | ||
1743 | CPUState *cpu_mb_init (const char *cpu_model) | |
1744 | { | |
1745 | CPUState *env; | |
1746 | static int tcg_initialized = 0; | |
1747 | int i; | |
1748 | ||
1749 | env = qemu_mallocz(sizeof(CPUState)); | |
1750 | ||
1751 | cpu_exec_init(env); | |
1752 | cpu_reset(env); | |
97694c57 | 1753 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
4acb54ba EI |
1754 | |
1755 | if (tcg_initialized) | |
1756 | return env; | |
1757 | ||
1758 | tcg_initialized = 1; | |
1759 | ||
1760 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
1761 | ||
1762 | env_debug = tcg_global_mem_new(TCG_AREG0, | |
1763 | offsetof(CPUState, debug), | |
1764 | "debug0"); | |
1765 | env_iflags = tcg_global_mem_new(TCG_AREG0, | |
1766 | offsetof(CPUState, iflags), | |
1767 | "iflags"); | |
1768 | env_imm = tcg_global_mem_new(TCG_AREG0, | |
1769 | offsetof(CPUState, imm), | |
1770 | "imm"); | |
1771 | env_btarget = tcg_global_mem_new(TCG_AREG0, | |
1772 | offsetof(CPUState, btarget), | |
1773 | "btarget"); | |
1774 | env_btaken = tcg_global_mem_new(TCG_AREG0, | |
1775 | offsetof(CPUState, btaken), | |
1776 | "btaken"); | |
1777 | for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { | |
1778 | cpu_R[i] = tcg_global_mem_new(TCG_AREG0, | |
1779 | offsetof(CPUState, regs[i]), | |
1780 | regnames[i]); | |
1781 | } | |
1782 | for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) { | |
1783 | cpu_SR[i] = tcg_global_mem_new(TCG_AREG0, | |
1784 | offsetof(CPUState, sregs[i]), | |
1785 | special_regnames[i]); | |
1786 | } | |
1787 | #define GEN_HELPER 2 | |
1788 | #include "helper.h" | |
1789 | ||
1790 | return env; | |
1791 | } | |
1792 | ||
1793 | void cpu_reset (CPUState *env) | |
1794 | { | |
1795 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
1796 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
1797 | log_cpu_state(env, 0); | |
1798 | } | |
1799 | ||
1800 | memset(env, 0, offsetof(CPUMBState, breakpoints)); | |
1801 | tlb_flush(env, 1); | |
1802 | ||
4898427e EI |
1803 | env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ |
1804 | | PVR0_USE_BARREL_MASK \ | |
1805 | | PVR0_USE_DIV_MASK \ | |
1806 | | PVR0_USE_HW_MUL_MASK \ | |
1807 | | PVR0_USE_EXC_MASK \ | |
1808 | | PVR0_USE_ICACHE_MASK \ | |
1809 | | PVR0_USE_DCACHE_MASK \ | |
1810 | | PVR0_USE_MMU \ | |
1811 | | (0xb << 8); | |
1812 | env->pvr.regs[2] = PVR2_D_OPB_MASK \ | |
1813 | | PVR2_D_LMB_MASK \ | |
1814 | | PVR2_I_OPB_MASK \ | |
1815 | | PVR2_I_LMB_MASK \ | |
1816 | | PVR2_USE_MSR_INSTR \ | |
1817 | | PVR2_USE_PCMP_INSTR \ | |
1818 | | PVR2_USE_BARREL_MASK \ | |
1819 | | PVR2_USE_DIV_MASK \ | |
1820 | | PVR2_USE_HW_MUL_MASK \ | |
1821 | | PVR2_USE_MUL64_MASK \ | |
97694c57 EI |
1822 | | PVR2_USE_FPU_MASK \ |
1823 | | PVR2_USE_FPU2_MASK \ | |
1824 | | PVR2_FPU_EXC_MASK \ | |
4898427e EI |
1825 | | 0; |
1826 | env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ | |
1827 | env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); | |
1828 | ||
4acb54ba EI |
1829 | #if defined(CONFIG_USER_ONLY) |
1830 | /* start in user mode with interrupts enabled. */ | |
97694c57 | 1831 | env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; |
4acb54ba EI |
1832 | env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ |
1833 | #else | |
97694c57 | 1834 | env->sregs[SR_MSR] = 0; |
4acb54ba | 1835 | mmu_init(&env->mmu); |
4898427e EI |
1836 | env->mmu.c_mmu = 3; |
1837 | env->mmu.c_mmu_tlb_access = 3; | |
1838 | env->mmu.c_mmu_zones = 16; | |
4acb54ba EI |
1839 | #endif |
1840 | } | |
1841 | ||
1842 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, | |
1843 | unsigned long searched_pc, int pc_pos, void *puc) | |
1844 | { | |
1845 | env->sregs[SR_PC] = gen_opc_pc[pc_pos]; | |
1846 | } |