]>
Commit | Line | Data |
---|---|---|
6af0bf9c FB |
1 | #if !defined (__MIPS_CPU_H__) |
2 | #define __MIPS_CPU_H__ | |
3 | ||
3e457172 BS |
4 | //#define DEBUG_OP |
5 | ||
d94f0a8e | 6 | #define ALIGNED_ONLY |
4ad40f36 | 7 | |
9349b4f9 | 8 | #define CPUArchState struct CPUMIPSState |
c2764719 | 9 | |
9a78eead | 10 | #include "qemu-common.h" |
6af0bf9c | 11 | #include "mips-defs.h" |
022c62cb | 12 | #include "exec/cpu-defs.h" |
6b4c305c | 13 | #include "fpu/softfloat.h" |
6af0bf9c | 14 | |
ead9360e | 15 | struct CPUMIPSState; |
6af0bf9c | 16 | |
c227f099 AL |
17 | typedef struct r4k_tlb_t r4k_tlb_t; |
18 | struct r4k_tlb_t { | |
6af0bf9c | 19 | target_ulong VPN; |
9c2149c8 | 20 | uint32_t PageMask; |
d783f789 PM |
21 | uint8_t ASID; |
22 | unsigned int G:1; | |
23 | unsigned int C0:3; | |
24 | unsigned int C1:3; | |
25 | unsigned int V0:1; | |
26 | unsigned int V1:1; | |
27 | unsigned int D0:1; | |
28 | unsigned int D1:1; | |
29 | unsigned int XI0:1; | |
30 | unsigned int XI1:1; | |
31 | unsigned int RI0:1; | |
32 | unsigned int RI1:1; | |
33 | unsigned int EHINV:1; | |
284b731a | 34 | uint64_t PFN[2]; |
6af0bf9c | 35 | }; |
6af0bf9c | 36 | |
3c7b48b7 | 37 | #if !defined(CONFIG_USER_ONLY) |
ead9360e TS |
38 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
39 | struct CPUMIPSTLBContext { | |
40 | uint32_t nb_tlb; | |
41 | uint32_t tlb_in_use; | |
a8170e5e | 42 | int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type); |
895c2d04 BS |
43 | void (*helper_tlbwi)(struct CPUMIPSState *env); |
44 | void (*helper_tlbwr)(struct CPUMIPSState *env); | |
45 | void (*helper_tlbp)(struct CPUMIPSState *env); | |
46 | void (*helper_tlbr)(struct CPUMIPSState *env); | |
9456c2fb LA |
47 | void (*helper_tlbinv)(struct CPUMIPSState *env); |
48 | void (*helper_tlbinvf)(struct CPUMIPSState *env); | |
ead9360e TS |
49 | union { |
50 | struct { | |
c227f099 | 51 | r4k_tlb_t tlb[MIPS_TLB_MAX]; |
ead9360e TS |
52 | } r4k; |
53 | } mmu; | |
54 | }; | |
3c7b48b7 | 55 | #endif |
51b2772f | 56 | |
e97a391d YK |
57 | /* MSA Context */ |
58 | #define MSA_WRLEN (128) | |
59 | ||
60 | enum CPUMIPSMSADataFormat { | |
61 | DF_BYTE = 0, | |
62 | DF_HALF, | |
63 | DF_WORD, | |
64 | DF_DOUBLE | |
65 | }; | |
66 | ||
67 | typedef union wr_t wr_t; | |
68 | union wr_t { | |
69 | int8_t b[MSA_WRLEN/8]; | |
70 | int16_t h[MSA_WRLEN/16]; | |
71 | int32_t w[MSA_WRLEN/32]; | |
72 | int64_t d[MSA_WRLEN/64]; | |
73 | }; | |
74 | ||
c227f099 AL |
75 | typedef union fpr_t fpr_t; |
76 | union fpr_t { | |
ead9360e TS |
77 | float64 fd; /* ieee double precision */ |
78 | float32 fs[2];/* ieee single precision */ | |
79 | uint64_t d; /* binary double fixed-point */ | |
80 | uint32_t w[2]; /* binary single fixed-point */ | |
e97a391d YK |
81 | /* FPU/MSA register mapping is not tested on big-endian hosts. */ |
82 | wr_t wr; /* vector data */ | |
ead9360e TS |
83 | }; |
84 | /* define FP_ENDIAN_IDX to access the same location | |
4ff9786c | 85 | * in the fpr_t union regardless of the host endianness |
ead9360e | 86 | */ |
e2542fe2 | 87 | #if defined(HOST_WORDS_BIGENDIAN) |
ead9360e TS |
88 | # define FP_ENDIAN_IDX 1 |
89 | #else | |
90 | # define FP_ENDIAN_IDX 0 | |
c570fd16 | 91 | #endif |
ead9360e TS |
92 | |
93 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; | |
94 | struct CPUMIPSFPUContext { | |
6af0bf9c | 95 | /* Floating point registers */ |
c227f099 | 96 | fpr_t fpr[32]; |
6ea83fed | 97 | float_status fp_status; |
5a5012ec | 98 | /* fpu implementation/revision register (fir) */ |
6af0bf9c | 99 | uint32_t fcr0; |
7c979afd | 100 | #define FCR0_FREP 29 |
b4dd99a3 | 101 | #define FCR0_UFRP 28 |
5a5012ec TS |
102 | #define FCR0_F64 22 |
103 | #define FCR0_L 21 | |
104 | #define FCR0_W 20 | |
105 | #define FCR0_3D 19 | |
106 | #define FCR0_PS 18 | |
107 | #define FCR0_D 17 | |
108 | #define FCR0_S 16 | |
109 | #define FCR0_PRID 8 | |
110 | #define FCR0_REV 0 | |
6ea83fed FB |
111 | /* fcsr */ |
112 | uint32_t fcr31; | |
f01be154 TS |
113 | #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
114 | #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) | |
115 | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) | |
5a5012ec TS |
116 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
117 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) | |
118 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) | |
119 | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) | |
120 | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) | |
121 | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) | |
122 | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) | |
6ea83fed FB |
123 | #define FP_INEXACT 1 |
124 | #define FP_UNDERFLOW 2 | |
125 | #define FP_OVERFLOW 4 | |
126 | #define FP_DIV0 8 | |
127 | #define FP_INVALID 16 | |
128 | #define FP_UNIMPLEMENTED 32 | |
ead9360e TS |
129 | }; |
130 | ||
623a930e | 131 | #define NB_MMU_MODES 3 |
c20d594e | 132 | #define TARGET_INSN_START_EXTRA_WORDS 2 |
6ebbf390 | 133 | |
ead9360e TS |
134 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
135 | struct CPUMIPSMVPContext { | |
136 | int32_t CP0_MVPControl; | |
137 | #define CP0MVPCo_CPA 3 | |
138 | #define CP0MVPCo_STLB 2 | |
139 | #define CP0MVPCo_VPC 1 | |
140 | #define CP0MVPCo_EVP 0 | |
141 | int32_t CP0_MVPConf0; | |
142 | #define CP0MVPC0_M 31 | |
143 | #define CP0MVPC0_TLBS 29 | |
144 | #define CP0MVPC0_GS 28 | |
145 | #define CP0MVPC0_PCP 27 | |
146 | #define CP0MVPC0_PTLBE 16 | |
147 | #define CP0MVPC0_TCA 15 | |
148 | #define CP0MVPC0_PVPE 10 | |
149 | #define CP0MVPC0_PTC 0 | |
150 | int32_t CP0_MVPConf1; | |
151 | #define CP0MVPC1_CIM 31 | |
152 | #define CP0MVPC1_CIF 30 | |
153 | #define CP0MVPC1_PCX 20 | |
154 | #define CP0MVPC1_PCP2 10 | |
155 | #define CP0MVPC1_PCP1 0 | |
156 | }; | |
157 | ||
c227f099 | 158 | typedef struct mips_def_t mips_def_t; |
ead9360e TS |
159 | |
160 | #define MIPS_SHADOW_SET_MAX 16 | |
161 | #define MIPS_TC_MAX 5 | |
f01be154 | 162 | #define MIPS_FPU_MAX 1 |
ead9360e | 163 | #define MIPS_DSP_ACC 4 |
e98c0d17 | 164 | #define MIPS_KSCRATCH_NUM 6 |
ead9360e | 165 | |
b5dc7732 TS |
166 | typedef struct TCState TCState; |
167 | struct TCState { | |
168 | target_ulong gpr[32]; | |
169 | target_ulong PC; | |
170 | target_ulong HI[MIPS_DSP_ACC]; | |
171 | target_ulong LO[MIPS_DSP_ACC]; | |
172 | target_ulong ACX[MIPS_DSP_ACC]; | |
173 | target_ulong DSPControl; | |
174 | int32_t CP0_TCStatus; | |
175 | #define CP0TCSt_TCU3 31 | |
176 | #define CP0TCSt_TCU2 30 | |
177 | #define CP0TCSt_TCU1 29 | |
178 | #define CP0TCSt_TCU0 28 | |
179 | #define CP0TCSt_TMX 27 | |
180 | #define CP0TCSt_RNST 23 | |
181 | #define CP0TCSt_TDS 21 | |
182 | #define CP0TCSt_DT 20 | |
183 | #define CP0TCSt_DA 15 | |
184 | #define CP0TCSt_A 13 | |
185 | #define CP0TCSt_TKSU 11 | |
186 | #define CP0TCSt_IXMT 10 | |
187 | #define CP0TCSt_TASID 0 | |
188 | int32_t CP0_TCBind; | |
189 | #define CP0TCBd_CurTC 21 | |
190 | #define CP0TCBd_TBE 17 | |
191 | #define CP0TCBd_CurVPE 0 | |
192 | target_ulong CP0_TCHalt; | |
193 | target_ulong CP0_TCContext; | |
194 | target_ulong CP0_TCSchedule; | |
195 | target_ulong CP0_TCScheFBack; | |
196 | int32_t CP0_Debug_tcstatus; | |
d279279e | 197 | target_ulong CP0_UserLocal; |
e97a391d YK |
198 | |
199 | int32_t msacsr; | |
200 | ||
201 | #define MSACSR_FS 24 | |
202 | #define MSACSR_FS_MASK (1 << MSACSR_FS) | |
203 | #define MSACSR_NX 18 | |
204 | #define MSACSR_NX_MASK (1 << MSACSR_NX) | |
205 | #define MSACSR_CEF 2 | |
206 | #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) | |
207 | #define MSACSR_RM 0 | |
208 | #define MSACSR_RM_MASK (0x3 << MSACSR_RM) | |
209 | #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ | |
210 | MSACSR_FS_MASK) | |
211 | ||
212 | float_status msa_fp_status; | |
b5dc7732 TS |
213 | }; |
214 | ||
ead9360e TS |
215 | typedef struct CPUMIPSState CPUMIPSState; |
216 | struct CPUMIPSState { | |
b5dc7732 | 217 | TCState active_tc; |
f01be154 | 218 | CPUMIPSFPUContext active_fpu; |
b5dc7732 | 219 | |
ead9360e | 220 | uint32_t current_tc; |
f01be154 | 221 | uint32_t current_fpu; |
36d23958 | 222 | |
e034e2c3 | 223 | uint32_t SEGBITS; |
6d35524c | 224 | uint32_t PABITS; |
e117f526 LA |
225 | #if defined(TARGET_MIPS64) |
226 | # define PABITS_BASE 36 | |
227 | #else | |
228 | # define PABITS_BASE 32 | |
229 | #endif | |
b6d96bed | 230 | target_ulong SEGMask; |
284b731a | 231 | uint64_t PAMask; |
e117f526 | 232 | #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) |
29929e34 | 233 | |
e97a391d YK |
234 | int32_t msair; |
235 | #define MSAIR_ProcID 8 | |
236 | #define MSAIR_Rev 0 | |
237 | ||
9c2149c8 | 238 | int32_t CP0_Index; |
ead9360e | 239 | /* CP0_MVP* are per MVP registers. */ |
01bc435b YK |
240 | int32_t CP0_VPControl; |
241 | #define CP0VPCtl_DIS 0 | |
9c2149c8 | 242 | int32_t CP0_Random; |
ead9360e TS |
243 | int32_t CP0_VPEControl; |
244 | #define CP0VPECo_YSI 21 | |
245 | #define CP0VPECo_GSI 20 | |
246 | #define CP0VPECo_EXCPT 16 | |
247 | #define CP0VPECo_TE 15 | |
248 | #define CP0VPECo_TargTC 0 | |
249 | int32_t CP0_VPEConf0; | |
250 | #define CP0VPEC0_M 31 | |
251 | #define CP0VPEC0_XTC 21 | |
252 | #define CP0VPEC0_TCS 19 | |
253 | #define CP0VPEC0_SCS 18 | |
254 | #define CP0VPEC0_DSC 17 | |
255 | #define CP0VPEC0_ICS 16 | |
256 | #define CP0VPEC0_MVP 1 | |
257 | #define CP0VPEC0_VPA 0 | |
258 | int32_t CP0_VPEConf1; | |
259 | #define CP0VPEC1_NCX 20 | |
260 | #define CP0VPEC1_NCP2 10 | |
261 | #define CP0VPEC1_NCP1 0 | |
262 | target_ulong CP0_YQMask; | |
263 | target_ulong CP0_VPESchedule; | |
264 | target_ulong CP0_VPEScheFBack; | |
265 | int32_t CP0_VPEOpt; | |
266 | #define CP0VPEOpt_IWX7 15 | |
267 | #define CP0VPEOpt_IWX6 14 | |
268 | #define CP0VPEOpt_IWX5 13 | |
269 | #define CP0VPEOpt_IWX4 12 | |
270 | #define CP0VPEOpt_IWX3 11 | |
271 | #define CP0VPEOpt_IWX2 10 | |
272 | #define CP0VPEOpt_IWX1 9 | |
273 | #define CP0VPEOpt_IWX0 8 | |
274 | #define CP0VPEOpt_DWX7 7 | |
275 | #define CP0VPEOpt_DWX6 6 | |
276 | #define CP0VPEOpt_DWX5 5 | |
277 | #define CP0VPEOpt_DWX4 4 | |
278 | #define CP0VPEOpt_DWX3 3 | |
279 | #define CP0VPEOpt_DWX2 2 | |
280 | #define CP0VPEOpt_DWX1 1 | |
281 | #define CP0VPEOpt_DWX0 0 | |
284b731a LA |
282 | uint64_t CP0_EntryLo0; |
283 | uint64_t CP0_EntryLo1; | |
2fb58b73 LA |
284 | #if defined(TARGET_MIPS64) |
285 | # define CP0EnLo_RI 63 | |
286 | # define CP0EnLo_XI 62 | |
287 | #else | |
288 | # define CP0EnLo_RI 31 | |
289 | # define CP0EnLo_XI 30 | |
290 | #endif | |
01bc435b YK |
291 | int32_t CP0_GlobalNumber; |
292 | #define CP0GN_VPId 0 | |
9c2149c8 | 293 | target_ulong CP0_Context; |
e98c0d17 | 294 | target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; |
9c2149c8 | 295 | int32_t CP0_PageMask; |
7207c7f9 | 296 | int32_t CP0_PageGrain_rw_bitmask; |
9c2149c8 | 297 | int32_t CP0_PageGrain; |
7207c7f9 LA |
298 | #define CP0PG_RIE 31 |
299 | #define CP0PG_XIE 30 | |
e117f526 | 300 | #define CP0PG_ELPA 29 |
92ceb440 | 301 | #define CP0PG_IEC 27 |
9c2149c8 | 302 | int32_t CP0_Wired; |
ead9360e TS |
303 | int32_t CP0_SRSConf0_rw_bitmask; |
304 | int32_t CP0_SRSConf0; | |
305 | #define CP0SRSC0_M 31 | |
306 | #define CP0SRSC0_SRS3 20 | |
307 | #define CP0SRSC0_SRS2 10 | |
308 | #define CP0SRSC0_SRS1 0 | |
309 | int32_t CP0_SRSConf1_rw_bitmask; | |
310 | int32_t CP0_SRSConf1; | |
311 | #define CP0SRSC1_M 31 | |
312 | #define CP0SRSC1_SRS6 20 | |
313 | #define CP0SRSC1_SRS5 10 | |
314 | #define CP0SRSC1_SRS4 0 | |
315 | int32_t CP0_SRSConf2_rw_bitmask; | |
316 | int32_t CP0_SRSConf2; | |
317 | #define CP0SRSC2_M 31 | |
318 | #define CP0SRSC2_SRS9 20 | |
319 | #define CP0SRSC2_SRS8 10 | |
320 | #define CP0SRSC2_SRS7 0 | |
321 | int32_t CP0_SRSConf3_rw_bitmask; | |
322 | int32_t CP0_SRSConf3; | |
323 | #define CP0SRSC3_M 31 | |
324 | #define CP0SRSC3_SRS12 20 | |
325 | #define CP0SRSC3_SRS11 10 | |
326 | #define CP0SRSC3_SRS10 0 | |
327 | int32_t CP0_SRSConf4_rw_bitmask; | |
328 | int32_t CP0_SRSConf4; | |
329 | #define CP0SRSC4_SRS15 20 | |
330 | #define CP0SRSC4_SRS14 10 | |
331 | #define CP0SRSC4_SRS13 0 | |
9c2149c8 | 332 | int32_t CP0_HWREna; |
c570fd16 | 333 | target_ulong CP0_BadVAddr; |
aea14095 LA |
334 | uint32_t CP0_BadInstr; |
335 | uint32_t CP0_BadInstrP; | |
9c2149c8 TS |
336 | int32_t CP0_Count; |
337 | target_ulong CP0_EntryHi; | |
9456c2fb | 338 | #define CP0EnHi_EHINV 10 |
9c2149c8 TS |
339 | int32_t CP0_Compare; |
340 | int32_t CP0_Status; | |
6af0bf9c FB |
341 | #define CP0St_CU3 31 |
342 | #define CP0St_CU2 30 | |
343 | #define CP0St_CU1 29 | |
344 | #define CP0St_CU0 28 | |
345 | #define CP0St_RP 27 | |
6ea83fed | 346 | #define CP0St_FR 26 |
6af0bf9c | 347 | #define CP0St_RE 25 |
7a387fff TS |
348 | #define CP0St_MX 24 |
349 | #define CP0St_PX 23 | |
6af0bf9c FB |
350 | #define CP0St_BEV 22 |
351 | #define CP0St_TS 21 | |
352 | #define CP0St_SR 20 | |
353 | #define CP0St_NMI 19 | |
354 | #define CP0St_IM 8 | |
7a387fff TS |
355 | #define CP0St_KX 7 |
356 | #define CP0St_SX 6 | |
357 | #define CP0St_UX 5 | |
623a930e | 358 | #define CP0St_KSU 3 |
6af0bf9c FB |
359 | #define CP0St_ERL 2 |
360 | #define CP0St_EXL 1 | |
361 | #define CP0St_IE 0 | |
9c2149c8 | 362 | int32_t CP0_IntCtl; |
ead9360e | 363 | #define CP0IntCtl_IPTI 29 |
88991299 | 364 | #define CP0IntCtl_IPPCI 26 |
ead9360e | 365 | #define CP0IntCtl_VS 5 |
9c2149c8 | 366 | int32_t CP0_SRSCtl; |
ead9360e TS |
367 | #define CP0SRSCtl_HSS 26 |
368 | #define CP0SRSCtl_EICSS 18 | |
369 | #define CP0SRSCtl_ESS 12 | |
370 | #define CP0SRSCtl_PSS 6 | |
371 | #define CP0SRSCtl_CSS 0 | |
9c2149c8 | 372 | int32_t CP0_SRSMap; |
ead9360e TS |
373 | #define CP0SRSMap_SSV7 28 |
374 | #define CP0SRSMap_SSV6 24 | |
375 | #define CP0SRSMap_SSV5 20 | |
376 | #define CP0SRSMap_SSV4 16 | |
377 | #define CP0SRSMap_SSV3 12 | |
378 | #define CP0SRSMap_SSV2 8 | |
379 | #define CP0SRSMap_SSV1 4 | |
380 | #define CP0SRSMap_SSV0 0 | |
9c2149c8 | 381 | int32_t CP0_Cause; |
7a387fff TS |
382 | #define CP0Ca_BD 31 |
383 | #define CP0Ca_TI 30 | |
384 | #define CP0Ca_CE 28 | |
385 | #define CP0Ca_DC 27 | |
386 | #define CP0Ca_PCI 26 | |
6af0bf9c | 387 | #define CP0Ca_IV 23 |
7a387fff TS |
388 | #define CP0Ca_WP 22 |
389 | #define CP0Ca_IP 8 | |
4de9b249 | 390 | #define CP0Ca_IP_mask 0x0000FF00 |
7a387fff | 391 | #define CP0Ca_EC 2 |
c570fd16 | 392 | target_ulong CP0_EPC; |
9c2149c8 | 393 | int32_t CP0_PRid; |
b29a0341 | 394 | int32_t CP0_EBase; |
9c2149c8 | 395 | int32_t CP0_Config0; |
6af0bf9c FB |
396 | #define CP0C0_M 31 |
397 | #define CP0C0_K23 28 | |
398 | #define CP0C0_KU 25 | |
399 | #define CP0C0_MDU 20 | |
aff2bc6d | 400 | #define CP0C0_MM 18 |
6af0bf9c FB |
401 | #define CP0C0_BM 16 |
402 | #define CP0C0_BE 15 | |
403 | #define CP0C0_AT 13 | |
404 | #define CP0C0_AR 10 | |
405 | #define CP0C0_MT 7 | |
7a387fff | 406 | #define CP0C0_VI 3 |
6af0bf9c | 407 | #define CP0C0_K0 0 |
9c2149c8 | 408 | int32_t CP0_Config1; |
7a387fff | 409 | #define CP0C1_M 31 |
6af0bf9c FB |
410 | #define CP0C1_MMU 25 |
411 | #define CP0C1_IS 22 | |
412 | #define CP0C1_IL 19 | |
413 | #define CP0C1_IA 16 | |
414 | #define CP0C1_DS 13 | |
415 | #define CP0C1_DL 10 | |
416 | #define CP0C1_DA 7 | |
7a387fff TS |
417 | #define CP0C1_C2 6 |
418 | #define CP0C1_MD 5 | |
6af0bf9c FB |
419 | #define CP0C1_PC 4 |
420 | #define CP0C1_WR 3 | |
421 | #define CP0C1_CA 2 | |
422 | #define CP0C1_EP 1 | |
423 | #define CP0C1_FP 0 | |
9c2149c8 | 424 | int32_t CP0_Config2; |
7a387fff TS |
425 | #define CP0C2_M 31 |
426 | #define CP0C2_TU 28 | |
427 | #define CP0C2_TS 24 | |
428 | #define CP0C2_TL 20 | |
429 | #define CP0C2_TA 16 | |
430 | #define CP0C2_SU 12 | |
431 | #define CP0C2_SS 8 | |
432 | #define CP0C2_SL 4 | |
433 | #define CP0C2_SA 0 | |
9c2149c8 | 434 | int32_t CP0_Config3; |
7a387fff | 435 | #define CP0C3_M 31 |
70409e67 MR |
436 | #define CP0C3_BPG 30 |
437 | #define CP0C3_CMCGR 29 | |
e97a391d | 438 | #define CP0C3_MSAP 28 |
aea14095 LA |
439 | #define CP0C3_BP 27 |
440 | #define CP0C3_BI 26 | |
70409e67 MR |
441 | #define CP0C3_IPLW 21 |
442 | #define CP0C3_MMAR 18 | |
443 | #define CP0C3_MCU 17 | |
bbfa8f72 | 444 | #define CP0C3_ISA_ON_EXC 16 |
70409e67 | 445 | #define CP0C3_ISA 14 |
d279279e | 446 | #define CP0C3_ULRI 13 |
7207c7f9 | 447 | #define CP0C3_RXI 12 |
70409e67 | 448 | #define CP0C3_DSP2P 11 |
7a387fff TS |
449 | #define CP0C3_DSPP 10 |
450 | #define CP0C3_LPA 7 | |
451 | #define CP0C3_VEIC 6 | |
452 | #define CP0C3_VInt 5 | |
453 | #define CP0C3_SP 4 | |
70409e67 | 454 | #define CP0C3_CDMM 3 |
7a387fff TS |
455 | #define CP0C3_MT 2 |
456 | #define CP0C3_SM 1 | |
457 | #define CP0C3_TL 0 | |
8280b12c MR |
458 | int32_t CP0_Config4; |
459 | int32_t CP0_Config4_rw_bitmask; | |
b4160af1 | 460 | #define CP0C4_M 31 |
9456c2fb | 461 | #define CP0C4_IE 29 |
e98c0d17 | 462 | #define CP0C4_KScrExist 16 |
70409e67 MR |
463 | #define CP0C4_MMUExtDef 14 |
464 | #define CP0C4_FTLBPageSize 8 | |
465 | #define CP0C4_FTLBWays 4 | |
466 | #define CP0C4_FTLBSets 0 | |
467 | #define CP0C4_MMUSizeExt 0 | |
8280b12c MR |
468 | int32_t CP0_Config5; |
469 | int32_t CP0_Config5_rw_bitmask; | |
b4dd99a3 PJ |
470 | #define CP0C5_M 31 |
471 | #define CP0C5_K 30 | |
472 | #define CP0C5_CV 29 | |
473 | #define CP0C5_EVA 28 | |
474 | #define CP0C5_MSAEn 27 | |
b00c7218 | 475 | #define CP0C5_XNP 13 |
7c979afd LA |
476 | #define CP0C5_UFE 9 |
477 | #define CP0C5_FRE 8 | |
01bc435b | 478 | #define CP0C5_VP 7 |
faf1f68b | 479 | #define CP0C5_SBRI 6 |
5204ea79 | 480 | #define CP0C5_MVH 5 |
ce9782f4 | 481 | #define CP0C5_LLB 4 |
b4dd99a3 PJ |
482 | #define CP0C5_UFR 2 |
483 | #define CP0C5_NFExists 0 | |
e397ee33 TS |
484 | int32_t CP0_Config6; |
485 | int32_t CP0_Config7; | |
ead9360e | 486 | /* XXX: Maybe make LLAddr per-TC? */ |
284b731a | 487 | uint64_t lladdr; |
590bc601 PB |
488 | target_ulong llval; |
489 | target_ulong llnewval; | |
490 | target_ulong llreg; | |
284b731a | 491 | uint64_t CP0_LLAddr_rw_bitmask; |
2a6e32dd | 492 | int CP0_LLAddr_shift; |
fd88b6ab TS |
493 | target_ulong CP0_WatchLo[8]; |
494 | int32_t CP0_WatchHi[8]; | |
9c2149c8 TS |
495 | target_ulong CP0_XContext; |
496 | int32_t CP0_Framemask; | |
497 | int32_t CP0_Debug; | |
ead9360e | 498 | #define CP0DB_DBD 31 |
6af0bf9c FB |
499 | #define CP0DB_DM 30 |
500 | #define CP0DB_LSNM 28 | |
501 | #define CP0DB_Doze 27 | |
502 | #define CP0DB_Halt 26 | |
503 | #define CP0DB_CNT 25 | |
504 | #define CP0DB_IBEP 24 | |
505 | #define CP0DB_DBEP 21 | |
506 | #define CP0DB_IEXI 20 | |
507 | #define CP0DB_VER 15 | |
508 | #define CP0DB_DEC 10 | |
509 | #define CP0DB_SSt 8 | |
510 | #define CP0DB_DINT 5 | |
511 | #define CP0DB_DIB 4 | |
512 | #define CP0DB_DDBS 3 | |
513 | #define CP0DB_DDBL 2 | |
514 | #define CP0DB_DBp 1 | |
515 | #define CP0DB_DSS 0 | |
c570fd16 | 516 | target_ulong CP0_DEPC; |
9c2149c8 | 517 | int32_t CP0_Performance0; |
284b731a | 518 | uint64_t CP0_TagLo; |
9c2149c8 TS |
519 | int32_t CP0_DataLo; |
520 | int32_t CP0_TagHi; | |
521 | int32_t CP0_DataHi; | |
c570fd16 | 522 | target_ulong CP0_ErrorEPC; |
9c2149c8 | 523 | int32_t CP0_DESAVE; |
b5dc7732 TS |
524 | /* We waste some space so we can handle shadow registers like TCs. */ |
525 | TCState tcs[MIPS_SHADOW_SET_MAX]; | |
f01be154 | 526 | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
5cbdb3a3 | 527 | /* QEMU */ |
6af0bf9c | 528 | int error_code; |
aea14095 LA |
529 | #define EXCP_TLB_NOMATCH 0x1 |
530 | #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ | |
6af0bf9c FB |
531 | uint32_t hflags; /* CPU State */ |
532 | /* TMASK defines different execution modes */ | |
e117f526 | 533 | #define MIPS_HFLAG_TMASK 0x75807FF |
79ef2c4c | 534 | #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
623a930e TS |
535 | /* The KSU flags must be the lowest bits in hflags. The flag order |
536 | must be the same as defined for CP0 Status. This allows to use | |
537 | the bits as the value of mmu_idx. */ | |
79ef2c4c NF |
538 | #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
539 | #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ | |
540 | #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ | |
541 | #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ | |
542 | #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ | |
543 | #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ | |
544 | #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ | |
545 | #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ | |
546 | #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ | |
b8aa4598 TS |
547 | /* True if the MIPS IV COP1X instructions can be used. This also |
548 | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S | |
549 | and RSQRT.D. */ | |
79ef2c4c NF |
550 | #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
551 | #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ | |
01f72885 | 552 | #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ |
79ef2c4c NF |
553 | #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
554 | #define MIPS_HFLAG_M16_SHIFT 10 | |
4ad40f36 FB |
555 | /* If translation is interrupted between the branch instruction and |
556 | * the delay slot, record what type of branch it is so that we can | |
557 | * resume translation properly. It might be possible to reduce | |
558 | * this from three bits to two. */ | |
339cd2a8 | 559 | #define MIPS_HFLAG_BMASK_BASE 0x803800 |
79ef2c4c NF |
560 | #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ |
561 | #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ | |
562 | #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ | |
563 | #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ | |
564 | /* Extra flags about the current pending branch. */ | |
b231c103 | 565 | #define MIPS_HFLAG_BMASK_EXT 0x7C000 |
79ef2c4c NF |
566 | #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
567 | #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ | |
568 | #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ | |
b231c103 YK |
569 | #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ |
570 | #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ | |
79ef2c4c | 571 | #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) |
853c3240 | 572 | /* MIPS DSP resources access. */ |
b231c103 YK |
573 | #define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */ |
574 | #define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */ | |
d279279e | 575 | /* Extra flag about HWREna register. */ |
b231c103 | 576 | #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ |
faf1f68b | 577 | #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ |
339cd2a8 | 578 | #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ |
e97a391d | 579 | #define MIPS_HFLAG_MSA 0x1000000 |
7c979afd | 580 | #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ |
e117f526 | 581 | #define MIPS_HFLAG_ELPA 0x4000000 |
6af0bf9c | 582 | target_ulong btarget; /* Jump / branch target */ |
1ba74fb8 | 583 | target_ulong bcond; /* Branch condition (if needed) */ |
a316d335 | 584 | |
7a387fff TS |
585 | int SYNCI_Step; /* Address step size for SYNCI */ |
586 | int CCRes; /* Cycle count resolution/divisor */ | |
ead9360e TS |
587 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
588 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ | |
e189e748 | 589 | int insn_flags; /* Supported instruction set */ |
7a387fff | 590 | |
a316d335 | 591 | CPU_COMMON |
6ae81775 | 592 | |
f0c3c505 | 593 | /* Fields from here on are preserved across CPU reset. */ |
51cc2e78 | 594 | CPUMIPSMVPContext *mvp; |
3c7b48b7 | 595 | #if !defined(CONFIG_USER_ONLY) |
51cc2e78 | 596 | CPUMIPSTLBContext *tlb; |
3c7b48b7 | 597 | #endif |
51cc2e78 | 598 | |
c227f099 | 599 | const mips_def_t *cpu_model; |
33ac7f16 | 600 | void *irq[8]; |
1246b259 | 601 | QEMUTimer *timer; /* Internal timer */ |
6af0bf9c FB |
602 | }; |
603 | ||
0f71a709 AF |
604 | #include "cpu-qom.h" |
605 | ||
3c7b48b7 | 606 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 607 | int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 608 | target_ulong address, int rw, int access_type); |
a8170e5e | 609 | int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 610 | target_ulong address, int rw, int access_type); |
a8170e5e | 611 | int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 612 | target_ulong address, int rw, int access_type); |
895c2d04 BS |
613 | void r4k_helper_tlbwi(CPUMIPSState *env); |
614 | void r4k_helper_tlbwr(CPUMIPSState *env); | |
615 | void r4k_helper_tlbp(CPUMIPSState *env); | |
616 | void r4k_helper_tlbr(CPUMIPSState *env); | |
9456c2fb LA |
617 | void r4k_helper_tlbinv(CPUMIPSState *env); |
618 | void r4k_helper_tlbinvf(CPUMIPSState *env); | |
33d68b5f | 619 | |
c658b94f AF |
620 | void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
621 | bool is_write, bool is_exec, int unused, | |
622 | unsigned size); | |
3c7b48b7 PB |
623 | #endif |
624 | ||
9a78eead | 625 | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); |
647de6ca | 626 | |
9467d44c | 627 | #define cpu_exec cpu_mips_exec |
9467d44c | 628 | #define cpu_signal_handler cpu_mips_signal_handler |
c732abe2 | 629 | #define cpu_list mips_cpu_list |
9467d44c | 630 | |
084d0497 RH |
631 | extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); |
632 | extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); | |
633 | ||
623a930e TS |
634 | /* MMU modes definitions. We carefully match the indices with our |
635 | hflags layout. */ | |
6ebbf390 | 636 | #define MMU_MODE0_SUFFIX _kernel |
623a930e TS |
637 | #define MMU_MODE1_SUFFIX _super |
638 | #define MMU_MODE2_SUFFIX _user | |
639 | #define MMU_USER_IDX 2 | |
97ed5ccd | 640 | static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) |
6ebbf390 | 641 | { |
623a930e | 642 | return env->hflags & MIPS_HFLAG_KSU; |
6ebbf390 JM |
643 | } |
644 | ||
71ca034a | 645 | static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) |
138afb02 | 646 | { |
71ca034a LA |
647 | return (env->CP0_Status & (1 << CP0St_IE)) && |
648 | !(env->CP0_Status & (1 << CP0St_EXL)) && | |
649 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
650 | !(env->hflags & MIPS_HFLAG_DM) && | |
344eecf6 EI |
651 | /* Note that the TCStatus IXMT field is initialized to zero, |
652 | and only MT capable cores can set it to one. So we don't | |
653 | need to check for MT capabilities here. */ | |
71ca034a LA |
654 | !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); |
655 | } | |
656 | ||
657 | /* Check if there is pending and not masked out interrupt */ | |
658 | static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) | |
659 | { | |
660 | int32_t pending; | |
661 | int32_t status; | |
662 | bool r; | |
4cdc1cd1 | 663 | |
138afb02 EI |
664 | pending = env->CP0_Cause & CP0Ca_IP_mask; |
665 | status = env->CP0_Status & CP0Ca_IP_mask; | |
666 | ||
667 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { | |
668 | /* A MIPS configured with a vectorizing external interrupt controller | |
669 | will feed a vector into the Cause pending lines. The core treats | |
670 | the status lines as a vector level, not as indiviual masks. */ | |
671 | r = pending > status; | |
672 | } else { | |
673 | /* A MIPS configured with compatibility or VInt (Vectored Interrupts) | |
674 | treats the pending lines as individual interrupt lines, the status | |
675 | lines are individual masks. */ | |
71ca034a | 676 | r = (pending & status) != 0; |
138afb02 EI |
677 | } |
678 | return r; | |
679 | } | |
680 | ||
022c62cb | 681 | #include "exec/cpu-all.h" |
6af0bf9c FB |
682 | |
683 | /* Memory access type : | |
684 | * may be needed for precise access rights control and precise exceptions. | |
685 | */ | |
686 | enum { | |
687 | /* 1 bit to define user level / supervisor access */ | |
688 | ACCESS_USER = 0x00, | |
689 | ACCESS_SUPER = 0x01, | |
690 | /* 1 bit to indicate direction */ | |
691 | ACCESS_STORE = 0x02, | |
692 | /* Type of instruction that generated the access */ | |
693 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
694 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
695 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
696 | }; | |
697 | ||
698 | /* Exceptions */ | |
699 | enum { | |
700 | EXCP_NONE = -1, | |
701 | EXCP_RESET = 0, | |
702 | EXCP_SRESET, | |
703 | EXCP_DSS, | |
704 | EXCP_DINT, | |
14e51cc7 TS |
705 | EXCP_DDBL, |
706 | EXCP_DDBS, | |
6af0bf9c FB |
707 | EXCP_NMI, |
708 | EXCP_MCHECK, | |
14e51cc7 | 709 | EXCP_EXT_INTERRUPT, /* 8 */ |
6af0bf9c | 710 | EXCP_DFWATCH, |
14e51cc7 | 711 | EXCP_DIB, |
6af0bf9c FB |
712 | EXCP_IWATCH, |
713 | EXCP_AdEL, | |
714 | EXCP_AdES, | |
715 | EXCP_TLBF, | |
716 | EXCP_IBE, | |
14e51cc7 | 717 | EXCP_DBp, /* 16 */ |
6af0bf9c | 718 | EXCP_SYSCALL, |
14e51cc7 | 719 | EXCP_BREAK, |
4ad40f36 | 720 | EXCP_CpU, |
6af0bf9c FB |
721 | EXCP_RI, |
722 | EXCP_OVERFLOW, | |
723 | EXCP_TRAP, | |
5a5012ec | 724 | EXCP_FPE, |
14e51cc7 | 725 | EXCP_DWATCH, /* 24 */ |
6af0bf9c FB |
726 | EXCP_LTLBL, |
727 | EXCP_TLBL, | |
728 | EXCP_TLBS, | |
729 | EXCP_DBE, | |
ead9360e | 730 | EXCP_THREAD, |
14e51cc7 TS |
731 | EXCP_MDMX, |
732 | EXCP_C2E, | |
733 | EXCP_CACHE, /* 32 */ | |
853c3240 | 734 | EXCP_DSPDIS, |
e97a391d YK |
735 | EXCP_MSADIS, |
736 | EXCP_MSAFPE, | |
92ceb440 LA |
737 | EXCP_TLBXI, |
738 | EXCP_TLBRI, | |
14e51cc7 | 739 | |
92ceb440 | 740 | EXCP_LAST = EXCP_TLBRI, |
6af0bf9c | 741 | }; |
590bc601 PB |
742 | /* Dummy exception for conditional stores. */ |
743 | #define EXCP_SC 0x100 | |
6af0bf9c | 744 | |
f249412c EI |
745 | /* |
746 | * This is an interrnally generated WAKE request line. | |
747 | * It is driven by the CPU itself. Raised when the MT | |
748 | * block wants to wake a VPE from an inactive state and | |
749 | * cleared when VPE goes from active to inactive. | |
750 | */ | |
751 | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 | |
752 | ||
ea3e9847 | 753 | int cpu_mips_exec(CPUState *cpu); |
78ce64f4 | 754 | void mips_tcg_init(void); |
30bf942d | 755 | MIPSCPU *cpu_mips_init(const char *cpu_model); |
388bb21a | 756 | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
6af0bf9c | 757 | |
2994fd96 | 758 | #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) |
30bf942d | 759 | |
b7e516ce AF |
760 | /* TODO QOM'ify CPU reset and remove */ |
761 | void cpu_state_reset(CPUMIPSState *s); | |
762 | ||
f9480ffc | 763 | /* mips_timer.c */ |
7db13fae AF |
764 | uint32_t cpu_mips_get_random (CPUMIPSState *env); |
765 | uint32_t cpu_mips_get_count (CPUMIPSState *env); | |
766 | void cpu_mips_store_count (CPUMIPSState *env, uint32_t value); | |
767 | void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value); | |
768 | void cpu_mips_start_count(CPUMIPSState *env); | |
769 | void cpu_mips_stop_count(CPUMIPSState *env); | |
f9480ffc | 770 | |
5dc5d9f0 | 771 | /* mips_int.c */ |
7db13fae | 772 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); |
5dc5d9f0 | 773 | |
f9480ffc | 774 | /* helper.c */ |
7510454e AF |
775 | int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, |
776 | int mmu_idx); | |
3c7b48b7 | 777 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 778 | void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); |
a8170e5e | 779 | hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, |
c36bbb28 | 780 | int rw); |
3c7b48b7 | 781 | #endif |
1239b472 | 782 | target_ulong exception_resume_pc (CPUMIPSState *env); |
f9480ffc | 783 | |
b7651e95 YK |
784 | /* op_helper.c */ |
785 | extern unsigned int ieee_rm[]; | |
786 | int ieee_ex_to_mips(int xcpt); | |
787 | ||
bb962386 MR |
788 | static inline void restore_rounding_mode(CPUMIPSState *env) |
789 | { | |
790 | set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], | |
791 | &env->active_fpu.fp_status); | |
792 | } | |
793 | ||
794 | static inline void restore_flush_mode(CPUMIPSState *env) | |
795 | { | |
796 | set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, | |
797 | &env->active_fpu.fp_status); | |
798 | } | |
799 | ||
64451111 LA |
800 | static inline void restore_fp_status(CPUMIPSState *env) |
801 | { | |
802 | restore_rounding_mode(env); | |
803 | restore_flush_mode(env); | |
804 | } | |
805 | ||
806 | static inline void restore_msa_fp_status(CPUMIPSState *env) | |
807 | { | |
808 | float_status *status = &env->active_tc.msa_fp_status; | |
809 | int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; | |
810 | bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; | |
811 | ||
812 | set_float_rounding_mode(ieee_rm[rounding_mode], status); | |
813 | set_flush_to_zero(flush_to_zero, status); | |
814 | set_flush_inputs_to_zero(flush_to_zero, status); | |
815 | } | |
816 | ||
e117f526 LA |
817 | static inline void restore_pamask(CPUMIPSState *env) |
818 | { | |
819 | if (env->hflags & MIPS_HFLAG_ELPA) { | |
820 | env->PAMask = (1ULL << env->PABITS) - 1; | |
821 | } else { | |
822 | env->PAMask = PAMASK_BASE; | |
823 | } | |
824 | } | |
825 | ||
7db13fae | 826 | static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, |
6b917547 AL |
827 | target_ulong *cs_base, int *flags) |
828 | { | |
829 | *pc = env->active_tc.PC; | |
830 | *cs_base = 0; | |
d279279e PJ |
831 | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | |
832 | MIPS_HFLAG_HWRENA_ULR); | |
6b917547 AL |
833 | } |
834 | ||
7db13fae | 835 | static inline int mips_vpe_active(CPUMIPSState *env) |
f249412c EI |
836 | { |
837 | int active = 1; | |
838 | ||
839 | /* Check that the VPE is enabled. */ | |
840 | if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { | |
841 | active = 0; | |
842 | } | |
4abf79a4 | 843 | /* Check that the VPE is activated. */ |
f249412c EI |
844 | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { |
845 | active = 0; | |
846 | } | |
847 | ||
848 | /* Now verify that there are active thread contexts in the VPE. | |
849 | ||
850 | This assumes the CPU model will internally reschedule threads | |
851 | if the active one goes to sleep. If there are no threads available | |
852 | the active one will be in a sleeping state, and we can turn off | |
853 | the entire VPE. */ | |
854 | if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { | |
855 | /* TC is not activated. */ | |
856 | active = 0; | |
857 | } | |
858 | if (env->active_tc.CP0_TCHalt & 1) { | |
859 | /* TC is in halt state. */ | |
860 | active = 0; | |
861 | } | |
862 | ||
863 | return active; | |
864 | } | |
865 | ||
01bc435b YK |
866 | static inline int mips_vp_active(CPUMIPSState *env) |
867 | { | |
868 | CPUState *other_cs = first_cpu; | |
869 | ||
870 | /* Check if the VP disabled other VPs (which means the VP is enabled) */ | |
871 | if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { | |
872 | return 1; | |
873 | } | |
874 | ||
875 | /* Check if the virtual processor is disabled due to a DVP */ | |
876 | CPU_FOREACH(other_cs) { | |
877 | MIPSCPU *other_cpu = MIPS_CPU(other_cs); | |
878 | if ((&other_cpu->env != env) && | |
879 | ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { | |
880 | return 0; | |
881 | } | |
882 | } | |
883 | return 1; | |
884 | } | |
885 | ||
022c62cb | 886 | #include "exec/exec-all.h" |
f081c76c | 887 | |
03e6e501 MR |
888 | static inline void compute_hflags(CPUMIPSState *env) |
889 | { | |
890 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | | |
891 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | | |
faf1f68b | 892 | MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | |
e117f526 LA |
893 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE | |
894 | MIPS_HFLAG_ELPA); | |
03e6e501 MR |
895 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
896 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
897 | !(env->hflags & MIPS_HFLAG_DM)) { | |
898 | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; | |
899 | } | |
900 | #if defined(TARGET_MIPS64) | |
d9224450 MR |
901 | if ((env->insn_flags & ISA_MIPS3) && |
902 | (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || | |
903 | (env->CP0_Status & (1 << CP0St_PX)) || | |
904 | (env->CP0_Status & (1 << CP0St_UX)))) { | |
03e6e501 MR |
905 | env->hflags |= MIPS_HFLAG_64; |
906 | } | |
01f72885 | 907 | |
c48245f0 | 908 | if (!(env->insn_flags & ISA_MIPS3)) { |
01f72885 | 909 | env->hflags |= MIPS_HFLAG_AWRAP; |
c48245f0 MR |
910 | } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && |
911 | !(env->CP0_Status & (1 << CP0St_UX))) { | |
912 | env->hflags |= MIPS_HFLAG_AWRAP; | |
913 | } else if (env->insn_flags & ISA_MIPS64R6) { | |
01f72885 LA |
914 | /* Address wrapping for Supervisor and Kernel is specified in R6 */ |
915 | if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && | |
916 | !(env->CP0_Status & (1 << CP0St_SX))) || | |
917 | (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && | |
918 | !(env->CP0_Status & (1 << CP0St_KX)))) { | |
919 | env->hflags |= MIPS_HFLAG_AWRAP; | |
920 | } | |
03e6e501 MR |
921 | } |
922 | #endif | |
a63eb0ce LA |
923 | if (((env->CP0_Status & (1 << CP0St_CU0)) && |
924 | !(env->insn_flags & ISA_MIPS32R6)) || | |
03e6e501 MR |
925 | !(env->hflags & MIPS_HFLAG_KSU)) { |
926 | env->hflags |= MIPS_HFLAG_CP0; | |
927 | } | |
928 | if (env->CP0_Status & (1 << CP0St_CU1)) { | |
929 | env->hflags |= MIPS_HFLAG_FPU; | |
930 | } | |
931 | if (env->CP0_Status & (1 << CP0St_FR)) { | |
932 | env->hflags |= MIPS_HFLAG_F64; | |
933 | } | |
faf1f68b LA |
934 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && |
935 | (env->CP0_Config5 & (1 << CP0C5_SBRI))) { | |
936 | env->hflags |= MIPS_HFLAG_SBRI; | |
937 | } | |
853c3240 JL |
938 | if (env->insn_flags & ASE_DSPR2) { |
939 | /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, | |
940 | so enable to access DSPR2 resources. */ | |
941 | if (env->CP0_Status & (1 << CP0St_MX)) { | |
942 | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; | |
943 | } | |
944 | ||
945 | } else if (env->insn_flags & ASE_DSP) { | |
946 | /* Enables access MIPS DSP resources, now our cpu is DSP ASE, | |
947 | so enable to access DSP resources. */ | |
948 | if (env->CP0_Status & (1 << CP0St_MX)) { | |
949 | env->hflags |= MIPS_HFLAG_DSP; | |
950 | } | |
951 | ||
952 | } | |
03e6e501 MR |
953 | if (env->insn_flags & ISA_MIPS32R2) { |
954 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { | |
955 | env->hflags |= MIPS_HFLAG_COP1X; | |
956 | } | |
957 | } else if (env->insn_flags & ISA_MIPS32) { | |
958 | if (env->hflags & MIPS_HFLAG_64) { | |
959 | env->hflags |= MIPS_HFLAG_COP1X; | |
960 | } | |
961 | } else if (env->insn_flags & ISA_MIPS4) { | |
962 | /* All supported MIPS IV CPUs use the XX (CU3) to enable | |
963 | and disable the MIPS IV extensions to the MIPS III ISA. | |
964 | Some other MIPS IV CPUs ignore the bit, so the check here | |
965 | would be too restrictive for them. */ | |
f45cb2f4 | 966 | if (env->CP0_Status & (1U << CP0St_CU3)) { |
03e6e501 MR |
967 | env->hflags |= MIPS_HFLAG_COP1X; |
968 | } | |
969 | } | |
e97a391d YK |
970 | if (env->insn_flags & ASE_MSA) { |
971 | if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { | |
972 | env->hflags |= MIPS_HFLAG_MSA; | |
973 | } | |
974 | } | |
7c979afd LA |
975 | if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { |
976 | if (env->CP0_Config5 & (1 << CP0C5_FRE)) { | |
977 | env->hflags |= MIPS_HFLAG_FRE; | |
978 | } | |
979 | } | |
e117f526 LA |
980 | if (env->CP0_Config3 & (1 << CP0C3_LPA)) { |
981 | if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { | |
982 | env->hflags |= MIPS_HFLAG_ELPA; | |
983 | } | |
984 | } | |
03e6e501 MR |
985 | } |
986 | ||
81a423e6 | 987 | #ifndef CONFIG_USER_ONLY |
f93c3a8d LA |
988 | static inline void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) |
989 | { | |
990 | MIPSCPU *cpu = mips_env_get_cpu(env); | |
991 | ||
992 | /* Flush qemu's TLB and discard all shadowed entries. */ | |
993 | tlb_flush(CPU(cpu), flush_global); | |
994 | env->tlb->tlb_in_use = env->tlb->nb_tlb; | |
995 | } | |
996 | ||
81a423e6 MR |
997 | /* Called for updates to CP0_Status. */ |
998 | static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) | |
999 | { | |
1000 | int32_t tcstatus, *tcst; | |
1001 | uint32_t v = cpu->CP0_Status; | |
1002 | uint32_t cu, mx, asid, ksu; | |
1003 | uint32_t mask = ((1 << CP0TCSt_TCU3) | |
1004 | | (1 << CP0TCSt_TCU2) | |
1005 | | (1 << CP0TCSt_TCU1) | |
1006 | | (1 << CP0TCSt_TCU0) | |
1007 | | (1 << CP0TCSt_TMX) | |
1008 | | (3 << CP0TCSt_TKSU) | |
1009 | | (0xff << CP0TCSt_TASID)); | |
1010 | ||
1011 | cu = (v >> CP0St_CU0) & 0xf; | |
1012 | mx = (v >> CP0St_MX) & 0x1; | |
1013 | ksu = (v >> CP0St_KSU) & 0x3; | |
1014 | asid = env->CP0_EntryHi & 0xff; | |
1015 | ||
1016 | tcstatus = cu << CP0TCSt_TCU0; | |
1017 | tcstatus |= mx << CP0TCSt_TMX; | |
1018 | tcstatus |= ksu << CP0TCSt_TKSU; | |
1019 | tcstatus |= asid; | |
1020 | ||
1021 | if (tc == cpu->current_tc) { | |
1022 | tcst = &cpu->active_tc.CP0_TCStatus; | |
1023 | } else { | |
1024 | tcst = &cpu->tcs[tc].CP0_TCStatus; | |
1025 | } | |
1026 | ||
1027 | *tcst &= ~mask; | |
1028 | *tcst |= tcstatus; | |
1029 | compute_hflags(cpu); | |
1030 | } | |
1031 | ||
1032 | static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) | |
1033 | { | |
1034 | uint32_t mask = env->CP0_Status_rw_bitmask; | |
f93c3a8d | 1035 | target_ulong old = env->CP0_Status; |
81a423e6 MR |
1036 | |
1037 | if (env->insn_flags & ISA_MIPS32R6) { | |
1038 | bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; | |
2dcf7908 LA |
1039 | #if defined(TARGET_MIPS64) |
1040 | uint32_t ksux = (1 << CP0St_KX) & val; | |
1041 | ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ | |
1042 | ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ | |
1043 | val = (val & ~(7 << CP0St_UX)) | ksux; | |
1044 | #endif | |
81a423e6 MR |
1045 | if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { |
1046 | mask &= ~(3 << CP0St_KSU); | |
1047 | } | |
1048 | mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); | |
1049 | } | |
1050 | ||
f93c3a8d LA |
1051 | env->CP0_Status = (old & ~mask) | (val & mask); |
1052 | #if defined(TARGET_MIPS64) | |
1053 | if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { | |
1054 | /* Access to at least one of the 64-bit segments has been disabled */ | |
1055 | cpu_mips_tlb_flush(env, 1); | |
1056 | } | |
1057 | #endif | |
81a423e6 MR |
1058 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
1059 | sync_c0_status(env, env, env->current_tc); | |
1060 | } else { | |
1061 | compute_hflags(env); | |
1062 | } | |
1063 | } | |
1064 | ||
1065 | static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) | |
1066 | { | |
1067 | uint32_t mask = 0x00C00300; | |
1068 | uint32_t old = env->CP0_Cause; | |
1069 | int i; | |
1070 | ||
1071 | if (env->insn_flags & ISA_MIPS32R2) { | |
1072 | mask |= 1 << CP0Ca_DC; | |
1073 | } | |
1074 | if (env->insn_flags & ISA_MIPS32R6) { | |
1075 | mask &= ~((1 << CP0Ca_WP) & val); | |
1076 | } | |
1077 | ||
1078 | env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); | |
1079 | ||
1080 | if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { | |
1081 | if (env->CP0_Cause & (1 << CP0Ca_DC)) { | |
1082 | cpu_mips_stop_count(env); | |
1083 | } else { | |
1084 | cpu_mips_start_count(env); | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | /* Set/reset software interrupts */ | |
1089 | for (i = 0 ; i < 2 ; i++) { | |
1090 | if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { | |
1091 | cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); | |
1092 | } | |
1093 | } | |
1094 | } | |
1095 | #endif | |
1096 | ||
9c708c7f PD |
1097 | static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, |
1098 | uint32_t exception, | |
1099 | int error_code, | |
1100 | uintptr_t pc) | |
1101 | { | |
1102 | CPUState *cs = CPU(mips_env_get_cpu(env)); | |
1103 | ||
1104 | if (exception < EXCP_SC) { | |
1105 | qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", | |
1106 | __func__, exception, error_code); | |
1107 | } | |
1108 | cs->exception_index = exception; | |
1109 | env->error_code = error_code; | |
1110 | ||
1111 | cpu_loop_exit_restore(cs, pc); | |
1112 | } | |
1113 | ||
1114 | static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, | |
1115 | uint32_t exception, | |
1116 | uintptr_t pc) | |
1117 | { | |
1118 | do_raise_exception_err(env, exception, 0, pc); | |
1119 | } | |
1120 | ||
6af0bf9c | 1121 | #endif /* !defined (__MIPS_CPU_H__) */ |