[mirror_qemu.git] / target-mips / cpu.h

#if !defined (__MIPS_CPU_H__)
#define __MIPS_CPU_H__

#define TARGET_HAS_ICE 1

#define ELF_MACHINE	EM_MIPS

#include "config.h"
#include "mips-defs.h"
#include "cpu-defs.h"
#include "softfloat.h"

// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
// XXX: move that elsewhere
#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
typedef unsigned char           uint_fast8_t;
typedef unsigned int            uint_fast16_t;
#endif

struct CPUMIPSState;

typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t {
    target_ulong VPN;
    uint32_t PageMask;
    uint_fast8_t ASID;
    uint_fast16_t G:1;
    uint_fast16_t C0:3;
    uint_fast16_t C1:3;
    uint_fast16_t V0:1;
    uint_fast16_t V1:1;
    uint_fast16_t D0:1;
    uint_fast16_t D1:1;
    target_ulong PFN[2];
};

typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
struct CPUMIPSTLBContext {
    uint32_t nb_tlb;
    uint32_t tlb_in_use;
    int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
    void (*do_tlbwi) (void);
    void (*do_tlbwr) (void);
    void (*do_tlbp) (void);
    void (*do_tlbr) (void);
    union {
        struct {
            r4k_tlb_t tlb[MIPS_TLB_MAX];
        } r4k;
    } mmu;
};

typedef union fpr_t fpr_t;
union fpr_t {
    float64  fd;   /* ieee double precision */
    float32  fs[2];/* ieee single precision */
    uint64_t d;    /* binary double fixed-point */
    uint32_t w[2]; /* binary single fixed-point */
};
/* define FP_ENDIAN_IDX to access the same location
 * in the fpr_t union regardless of the host endianess
 */
#if defined(WORDS_BIGENDIAN)
#  define FP_ENDIAN_IDX 1
#else
#  define FP_ENDIAN_IDX 0
#endif

typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
struct CPUMIPSFPUContext {
    /* Floating point registers */
    fpr_t fpr[32];
#ifndef USE_HOST_FLOAT_REGS
    fpr_t ft0;
    fpr_t ft1;
    fpr_t ft2;
#endif
    float_status fp_status;
    /* fpu implementation/revision register (fir) */
    uint32_t fcr0;
#define FCR0_F64 22
#define FCR0_L 21
#define FCR0_W 20
#define FCR0_3D 19
#define FCR0_PS 18
#define FCR0_D 17
#define FCR0_S 16
#define FCR0_PRID 8
#define FCR0_REV 0
    /* fcsr */
    uint32_t fcr31;
#define SET_FP_COND(num,env)     do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define CLEAR_FP_COND(num,env)   do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define GET_FP_COND(env)         ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
#define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
#define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
#define FP_INEXACT        1
#define FP_UNDERFLOW      2
#define FP_OVERFLOW       4
#define FP_DIV0           8
#define FP_INVALID        16
#define FP_UNIMPLEMENTED  32
};

#define NB_MMU_MODES 2

typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
    int32_t CP0_MVPControl;
#define CP0MVPCo_CPA	3
#define CP0MVPCo_STLB	2
#define CP0MVPCo_VPC	1
#define CP0MVPCo_EVP	0
    int32_t CP0_MVPConf0;
#define CP0MVPC0_M	31
#define CP0MVPC0_TLBS	29
#define CP0MVPC0_GS	28
#define CP0MVPC0_PCP	27
#define CP0MVPC0_PTLBE	16
#define CP0MVPC0_TCA	15
#define CP0MVPC0_PVPE	10
#define CP0MVPC0_PTC	0
    int32_t CP0_MVPConf1;
#define CP0MVPC1_CIM	31
#define CP0MVPC1_CIF	30
#define CP0MVPC1_PCX	20
#define CP0MVPC1_PCP2	10
#define CP0MVPC1_PCP1	0
};

typedef struct mips_def_t mips_def_t;

#define MIPS_SHADOW_SET_MAX 16
#define MIPS_TC_MAX 5
#define MIPS_DSP_ACC 4

typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
    /* General integer registers */
    target_ulong gpr[32][MIPS_SHADOW_SET_MAX];
    /* Special registers */
    target_ulong PC[MIPS_TC_MAX];
#if TARGET_LONG_BITS > HOST_LONG_BITS
    target_ulong t0;
    target_ulong t1;
    target_ulong t2;
#endif
    target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX];
    target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX];
    target_ulong ACX[MIPS_DSP_ACC][MIPS_TC_MAX];
    target_ulong DSPControl[MIPS_TC_MAX];

    CPUMIPSMVPContext *mvp;
    CPUMIPSTLBContext *tlb;
    CPUMIPSFPUContext *fpu;
    uint32_t current_tc;

    uint32_t SEGBITS;
    target_ulong SEGMask;

    int32_t CP0_Index;
    /* CP0_MVP* are per MVP registers. */
    int32_t CP0_Random;
    int32_t CP0_VPEControl;
#define CP0VPECo_YSI	21
#define CP0VPECo_GSI	20
#define CP0VPECo_EXCPT	16
#define CP0VPECo_TE	15
#define CP0VPECo_TargTC	0
    int32_t CP0_VPEConf0;
#define CP0VPEC0_M	31
#define CP0VPEC0_XTC	21
#define CP0VPEC0_TCS	19
#define CP0VPEC0_SCS	18
#define CP0VPEC0_DSC	17
#define CP0VPEC0_ICS	16
#define CP0VPEC0_MVP	1
#define CP0VPEC0_VPA	0
    int32_t CP0_VPEConf1;
#define CP0VPEC1_NCX	20
#define CP0VPEC1_NCP2	10
#define CP0VPEC1_NCP1	0
    target_ulong CP0_YQMask;
    target_ulong CP0_VPESchedule;
    target_ulong CP0_VPEScheFBack;
    int32_t CP0_VPEOpt;
#define CP0VPEOpt_IWX7	15
#define CP0VPEOpt_IWX6	14
#define CP0VPEOpt_IWX5	13
#define CP0VPEOpt_IWX4	12
#define CP0VPEOpt_IWX3	11
#define CP0VPEOpt_IWX2	10
#define CP0VPEOpt_IWX1	9
#define CP0VPEOpt_IWX0	8
#define CP0VPEOpt_DWX7	7
#define CP0VPEOpt_DWX6	6
#define CP0VPEOpt_DWX5	5
#define CP0VPEOpt_DWX4	4
#define CP0VPEOpt_DWX3	3
#define CP0VPEOpt_DWX2	2
#define CP0VPEOpt_DWX1	1
#define CP0VPEOpt_DWX0	0
    target_ulong CP0_EntryLo0;
    int32_t CP0_TCStatus[MIPS_TC_MAX];
#define CP0TCSt_TCU3	31
#define CP0TCSt_TCU2	30
#define CP0TCSt_TCU1	29
#define CP0TCSt_TCU0	28
#define CP0TCSt_TMX	27
#define CP0TCSt_RNST	23
#define CP0TCSt_TDS	21
#define CP0TCSt_DT	20
#define CP0TCSt_DA	15
#define CP0TCSt_A	13
#define CP0TCSt_TKSU	11
#define CP0TCSt_IXMT	10
#define CP0TCSt_TASID	0
    int32_t CP0_TCBind[MIPS_TC_MAX];
#define CP0TCBd_CurTC	21
#define CP0TCBd_TBE	17
#define CP0TCBd_CurVPE	0
    target_ulong CP0_TCHalt[MIPS_TC_MAX];
    target_ulong CP0_TCContext[MIPS_TC_MAX];
    target_ulong CP0_TCSchedule[MIPS_TC_MAX];
    target_ulong CP0_TCScheFBack[MIPS_TC_MAX];
    target_ulong CP0_EntryLo1;
    target_ulong CP0_Context;
    int32_t CP0_PageMask;
    int32_t CP0_PageGrain;
    int32_t CP0_Wired;
    int32_t CP0_SRSConf0_rw_bitmask;
    int32_t CP0_SRSConf0;
#define CP0SRSC0_M	31
#define CP0SRSC0_SRS3	20
#define CP0SRSC0_SRS2	10
#define CP0SRSC0_SRS1	0
    int32_t CP0_SRSConf1_rw_bitmask;
    int32_t CP0_SRSConf1;
#define CP0SRSC1_M	31
#define CP0SRSC1_SRS6	20
#define CP0SRSC1_SRS5	10
#define CP0SRSC1_SRS4	0
    int32_t CP0_SRSConf2_rw_bitmask;
    int32_t CP0_SRSConf2;
#define CP0SRSC2_M	31
#define CP0SRSC2_SRS9	20
#define CP0SRSC2_SRS8	10
#define CP0SRSC2_SRS7	0
    int32_t CP0_SRSConf3_rw_bitmask;
    int32_t CP0_SRSConf3;
#define CP0SRSC3_M	31
#define CP0SRSC3_SRS12	20
#define CP0SRSC3_SRS11	10
#define CP0SRSC3_SRS10	0
    int32_t CP0_SRSConf4_rw_bitmask;
    int32_t CP0_SRSConf4;
#define CP0SRSC4_SRS15	20
#define CP0SRSC4_SRS14	10
#define CP0SRSC4_SRS13	0
    int32_t CP0_HWREna;
    target_ulong CP0_BadVAddr;
    int32_t CP0_Count;
    target_ulong CP0_EntryHi;
    int32_t CP0_Compare;
    int32_t CP0_Status;
#define CP0St_CU3   31
#define CP0St_CU2   30
#define CP0St_CU1   29
#define CP0St_CU0   28
#define CP0St_RP    27
#define CP0St_FR    26
#define CP0St_RE    25
#define CP0St_MX    24
#define CP0St_PX    23
#define CP0St_BEV   22
#define CP0St_TS    21
#define CP0St_SR    20
#define CP0St_NMI   19
#define CP0St_IM    8
#define CP0St_KX    7
#define CP0St_SX    6
#define CP0St_UX    5
#define CP0St_UM    4
#define CP0St_R0    3
#define CP0St_ERL   2
#define CP0St_EXL   1
#define CP0St_IE    0
    int32_t CP0_IntCtl;
#define CP0IntCtl_IPTI 29
#define CP0IntCtl_IPPC1 26
#define CP0IntCtl_VS 5
    int32_t CP0_SRSCtl;
#define CP0SRSCtl_HSS 26
#define CP0SRSCtl_EICSS 18
#define CP0SRSCtl_ESS 12
#define CP0SRSCtl_PSS 6
#define CP0SRSCtl_CSS 0
    int32_t CP0_SRSMap;
#define CP0SRSMap_SSV7 28
#define CP0SRSMap_SSV6 24
#define CP0SRSMap_SSV5 20
#define CP0SRSMap_SSV4 16
#define CP0SRSMap_SSV3 12
#define CP0SRSMap_SSV2 8
#define CP0SRSMap_SSV1 4
#define CP0SRSMap_SSV0 0
    int32_t CP0_Cause;
#define CP0Ca_BD   31
#define CP0Ca_TI   30
#define CP0Ca_CE   28
#define CP0Ca_DC   27
#define CP0Ca_PCI  26
#define CP0Ca_IV   23
#define CP0Ca_WP   22
#define CP0Ca_IP    8
#define CP0Ca_IP_mask 0x0000FF00
#define CP0Ca_EC    2
    target_ulong CP0_EPC;
    int32_t CP0_PRid;
    int32_t CP0_EBase;
    int32_t CP0_Config0;
#define CP0C0_M    31
#define CP0C0_K23  28
#define CP0C0_KU   25
#define CP0C0_MDU  20
#define CP0C0_MM   17
#define CP0C0_BM   16
#define CP0C0_BE   15
#define CP0C0_AT   13
#define CP0C0_AR   10
#define CP0C0_MT   7
#define CP0C0_VI   3
#define CP0C0_K0   0
    int32_t CP0_Config1;
#define CP0C1_M    31
#define CP0C1_MMU  25
#define CP0C1_IS   22
#define CP0C1_IL   19
#define CP0C1_IA   16
#define CP0C1_DS   13
#define CP0C1_DL   10
#define CP0C1_DA   7
#define CP0C1_C2   6
#define CP0C1_MD   5
#define CP0C1_PC   4
#define CP0C1_WR   3
#define CP0C1_CA   2
#define CP0C1_EP   1
#define CP0C1_FP   0
    int32_t CP0_Config2;
#define CP0C2_M    31
#define CP0C2_TU   28
#define CP0C2_TS   24
#define CP0C2_TL   20
#define CP0C2_TA   16
#define CP0C2_SU   12
#define CP0C2_SS   8
#define CP0C2_SL   4
#define CP0C2_SA   0
    int32_t CP0_Config3;
#define CP0C3_M    31
#define CP0C3_DSPP 10
#define CP0C3_LPA  7
#define CP0C3_VEIC 6
#define CP0C3_VInt 5
#define CP0C3_SP   4
#define CP0C3_MT   2
#define CP0C3_SM   1
#define CP0C3_TL   0
    int32_t CP0_Config6;
    int32_t CP0_Config7;
    /* XXX: Maybe make LLAddr per-TC? */
    target_ulong CP0_LLAddr;
    target_ulong CP0_WatchLo[8];
    int32_t CP0_WatchHi[8];
    target_ulong CP0_XContext;
    int32_t CP0_Framemask;
    int32_t CP0_Debug;
#define CP0DB_DBD  31
#define CP0DB_DM   30
#define CP0DB_LSNM 28
#define CP0DB_Doze 27
#define CP0DB_Halt 26
#define CP0DB_CNT  25
#define CP0DB_IBEP 24
#define CP0DB_DBEP 21
#define CP0DB_IEXI 20
#define CP0DB_VER  15
#define CP0DB_DEC  10
#define CP0DB_SSt  8
#define CP0DB_DINT 5
#define CP0DB_DIB  4
#define CP0DB_DDBS 3
#define CP0DB_DDBL 2
#define CP0DB_DBp  1
#define CP0DB_DSS  0
    int32_t CP0_Debug_tcstatus[MIPS_TC_MAX];
    target_ulong CP0_DEPC;
    int32_t CP0_Performance0;
    int32_t CP0_TagLo;
    int32_t CP0_DataLo;
    int32_t CP0_TagHi;
    int32_t CP0_DataHi;
    target_ulong CP0_ErrorEPC;
    int32_t CP0_DESAVE;
    /* Qemu */
    int interrupt_request;
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    int user_mode_only; /* user mode only simulation */
    uint32_t hflags;    /* CPU State */
    /* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK  0x00FF
#define MIPS_HFLAG_MODE   0x0007 /* execution modes                    */
#define MIPS_HFLAG_UM     0x0001 /* user mode                          */
#define MIPS_HFLAG_DM     0x0002 /* Debug mode                         */
#define MIPS_HFLAG_SM     0x0004 /* Supervisor mode                    */
#define MIPS_HFLAG_64     0x0008 /* 64-bit instructions enabled        */
#define MIPS_HFLAG_CP0    0x0010 /* CP0 enabled                        */
#define MIPS_HFLAG_FPU    0x0020 /* FPU enabled                        */
#define MIPS_HFLAG_F64    0x0040 /* 64-bit FPU enabled                 */
#define MIPS_HFLAG_RE     0x0080 /* Reversed endianness                */
    /* If translation is interrupted between the branch instruction and
     * the delay slot, record what type of branch it is so that we can
     * resume translation properly.  It might be possible to reduce
     * this from three bits to two.  */
#define MIPS_HFLAG_BMASK  0x0700
#define MIPS_HFLAG_B      0x0100 /* Unconditional branch               */
#define MIPS_HFLAG_BC     0x0200 /* Conditional branch                 */
#define MIPS_HFLAG_BL     0x0300 /* Likely branch                      */
#define MIPS_HFLAG_BR     0x0400 /* branch to register (can't link TB) */
    target_ulong btarget;        /* Jump / branch target               */
    int bcond;                   /* Branch condition (if needed)       */

    int halted; /* TRUE if the CPU is in suspend state */

    int SYNCI_Step; /* Address step size for SYNCI */
    int CCRes; /* Cycle count resolution/divisor */
    uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
    uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
    int insn_flags; /* Supported instruction set */

#ifdef CONFIG_USER_ONLY
    target_ulong tls_value;
#endif

    CPU_COMMON

    int ram_size;
    const char *kernel_filename;
    const char *kernel_cmdline;
    const char *initrd_filename;

    mips_def_t *cpu_model;
#ifndef CONFIG_USER_ONLY
    void *irq[8];
#endif

    struct QEMUTimer *timer; /* Internal timer */
};

int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                        target_ulong address, int rw, int access_type);
int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                           target_ulong address, int rw, int access_type);
int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                     target_ulong address, int rw, int access_type);
void r4k_do_tlbwi (void);
void r4k_do_tlbwr (void);
void r4k_do_tlbp (void);
void r4k_do_tlbr (void);
int mips_find_by_name (const unsigned char *name, mips_def_t **def);
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                          int unused);

#define CPUState CPUMIPSState
#define cpu_init cpu_mips_init
#define cpu_exec cpu_mips_exec
#define cpu_gen_code cpu_mips_gen_code
#define cpu_signal_handler cpu_mips_signal_handler
#define cpu_list mips_cpu_list

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env)
{
    return (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 1 : 0;
}

#include "cpu-all.h"

/* Memory access type :
 * may be needed for precise access rights control and precise exceptions.
 */
enum {
    /* 1 bit to define user level / supervisor access */
    ACCESS_USER  = 0x00,
    ACCESS_SUPER = 0x01,
    /* 1 bit to indicate direction */
    ACCESS_STORE = 0x02,
    /* Type of instruction that generated the access */
    ACCESS_CODE  = 0x10, /* Code fetch access                */
    ACCESS_INT   = 0x20, /* Integer load/store access        */
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
};

/* Exceptions */
enum {
    EXCP_NONE          = -1,
    EXCP_RESET         = 0,
    EXCP_SRESET,
    EXCP_DSS,
    EXCP_DINT,
    EXCP_NMI,
    EXCP_MCHECK,
    EXCP_EXT_INTERRUPT,
    EXCP_DFWATCH,
    EXCP_DIB, /* 8 */
    EXCP_IWATCH,
    EXCP_AdEL,
    EXCP_AdES,
    EXCP_TLBF,
    EXCP_IBE,
    EXCP_DBp,
    EXCP_SYSCALL,
    EXCP_BREAK, /* 16 */
    EXCP_CpU,
    EXCP_RI,
    EXCP_OVERFLOW,
    EXCP_TRAP,
    EXCP_FPE,
    EXCP_DDBS,
    EXCP_DWATCH,
    EXCP_LAE, /* 24 */
    EXCP_SAE,
    EXCP_LTLBL,
    EXCP_TLBL,
    EXCP_TLBS,
    EXCP_DBE,
    EXCP_DDBL,
    EXCP_THREAD,
    EXCP_MTCP0         = 0x104, /* mtmsr instruction:               */
                                /* may change privilege level       */
    EXCP_BRANCH        = 0x108, /* branch instruction               */
    EXCP_ERET          = 0x10C, /* return from interrupt            */
    EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
    EXCP_FLUSH         = 0x109,
};

int cpu_mips_exec(CPUMIPSState *s);
CPUMIPSState *cpu_mips_init(void);
uint32_t cpu_mips_get_clock (void);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);

#endif /* !defined (__MIPS_CPU_H__) */
Commit	Line	Data
6af0bf9c FB	1	#if !defined (__MIPS_CPU_H__)
	2	#define __MIPS_CPU_H__
	3
4ad40f36 FB	4	#define TARGET_HAS_ICE 1
4ad40f36 FB	5
9042c0e2 TS	6	#define ELF_MACHINE EM_MIPS
9042c0e2 TS	7
c5d6edc3	8	#include "config.h"
6af0bf9c FB	9	#include "mips-defs.h"
6af0bf9c FB	10	#include "cpu-defs.h"
6af0bf9c FB	11	#include "softfloat.h"
6af0bf9c FB	12
fdbb4691 FB	13	// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
fdbb4691 FB	14	// XXX: move that elsewhere
36bb244b	15	#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
fdbb4691 FB	16	typedef unsigned char uint_fast8_t;
	17	typedef unsigned int uint_fast16_t;
	18	#endif
	19
ead9360e	20	struct CPUMIPSState;
6af0bf9c	21
29929e34 TS	22	typedef struct r4k_tlb_t r4k_tlb_t;
29929e34 TS	23	struct r4k_tlb_t {
6af0bf9c	24	target_ulong VPN;
9c2149c8	25	uint32_t PageMask;
98c1b82b PB	26	uint_fast8_t ASID;
	27	uint_fast16_t G:1;
	28	uint_fast16_t C0:3;
	29	uint_fast16_t C1:3;
	30	uint_fast16_t V0:1;
	31	uint_fast16_t V1:1;
	32	uint_fast16_t D0:1;
	33	uint_fast16_t D1:1;
6af0bf9c FB	34	target_ulong PFN[2];
6af0bf9c FB	35	};
6af0bf9c	36
ead9360e TS	37	typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
	38	struct CPUMIPSTLBContext {
	39	uint32_t nb_tlb;
	40	uint32_t tlb_in_use;
	41	int (map_address) (struct CPUMIPSState env, target_ulong physical, int prot, target_ulong address, int rw, int access_type);
	42	void (*do_tlbwi) (void);
	43	void (*do_tlbwr) (void);
	44	void (*do_tlbp) (void);
	45	void (*do_tlbr) (void);
	46	union {
	47	struct {
	48	r4k_tlb_t tlb[MIPS_TLB_MAX];
	49	} r4k;
	50	} mmu;
	51	};
51b2772f	52
ead9360e TS	53	typedef union fpr_t fpr_t;
	54	union fpr_t {
	55	float64 fd; /* ieee double precision */
	56	float32 fs[2];/* ieee single precision */
	57	uint64_t d; /* binary double fixed-point */
	58	uint32_t w[2]; /* binary single fixed-point */
	59	};
	60	/* define FP_ENDIAN_IDX to access the same location
	61	* in the fpr_t union regardless of the host endianess
	62	*/
	63	#if defined(WORDS_BIGENDIAN)
	64	# define FP_ENDIAN_IDX 1
	65	#else
	66	# define FP_ENDIAN_IDX 0
c570fd16	67	#endif
ead9360e TS	68
	69	typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
	70	struct CPUMIPSFPUContext {
6af0bf9c	71	/* Floating point registers */
f7cfb2a1	72	fpr_t fpr[32];
6ea83fed FB	73	#ifndef USE_HOST_FLOAT_REGS
	74	fpr_t ft0;
	75	fpr_t ft1;
	76	fpr_t ft2;
	77	#endif
	78	float_status fp_status;
5a5012ec	79	/* fpu implementation/revision register (fir) */
6af0bf9c	80	uint32_t fcr0;
5a5012ec TS	81	#define FCR0_F64 22
	82	#define FCR0_L 21
	83	#define FCR0_W 20
	84	#define FCR0_3D 19
	85	#define FCR0_PS 18
	86	#define FCR0_D 17
	87	#define FCR0_S 16
	88	#define FCR0_PRID 8
	89	#define FCR0_REV 0
6ea83fed FB	90	/* fcsr */
6ea83fed FB	91	uint32_t fcr31;
fd4a04eb TS	92	#define SET_FP_COND(num,env) do { ((env)->fcr31) \|= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
	93	#define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
	94	#define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) \| (((env)->fcr31 >> 23) & 0x1))
5a5012ec TS	95	#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
	96	#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
	97	#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
	98	#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) \| ((v & 0x3f) << 12); } while(0)
	99	#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) \| ((v & 0x1f) << 7); } while(0)
	100	#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) \| ((v & 0x1f) << 2); } while(0)
	101	#define UPDATE_FP_FLAGS(reg,v) do { (reg) \|= ((v & 0x1f) << 2); } while(0)
6ea83fed FB	102	#define FP_INEXACT 1
	103	#define FP_UNDERFLOW 2
	104	#define FP_OVERFLOW 4
	105	#define FP_DIV0 8
	106	#define FP_INVALID 16
	107	#define FP_UNIMPLEMENTED 32
ead9360e TS	108	};
ead9360e TS	109
6ebbf390 JM	110	#define NB_MMU_MODES 2
6ebbf390 JM	111
ead9360e TS	112	typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
	113	struct CPUMIPSMVPContext {
	114	int32_t CP0_MVPControl;
	115	#define CP0MVPCo_CPA 3
	116	#define CP0MVPCo_STLB 2
	117	#define CP0MVPCo_VPC 1
	118	#define CP0MVPCo_EVP 0
	119	int32_t CP0_MVPConf0;
	120	#define CP0MVPC0_M 31
	121	#define CP0MVPC0_TLBS 29
	122	#define CP0MVPC0_GS 28
	123	#define CP0MVPC0_PCP 27
	124	#define CP0MVPC0_PTLBE 16
	125	#define CP0MVPC0_TCA 15
	126	#define CP0MVPC0_PVPE 10
	127	#define CP0MVPC0_PTC 0
	128	int32_t CP0_MVPConf1;
	129	#define CP0MVPC1_CIM 31
	130	#define CP0MVPC1_CIF 30
	131	#define CP0MVPC1_PCX 20
	132	#define CP0MVPC1_PCP2 10
	133	#define CP0MVPC1_PCP1 0
	134	};
	135
	136	typedef struct mips_def_t mips_def_t;
	137
	138	#define MIPS_SHADOW_SET_MAX 16
	139	#define MIPS_TC_MAX 5
	140	#define MIPS_DSP_ACC 4
	141
	142	typedef struct CPUMIPSState CPUMIPSState;
	143	struct CPUMIPSState {
	144	/* General integer registers */
	145	target_ulong gpr[32][MIPS_SHADOW_SET_MAX];
	146	/* Special registers */
	147	target_ulong PC[MIPS_TC_MAX];
	148	#if TARGET_LONG_BITS > HOST_LONG_BITS
	149	target_ulong t0;
	150	target_ulong t1;
	151	target_ulong t2;
	152	#endif
	153	target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX];
	154	target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX];
	155	target_ulong ACX[MIPS_DSP_ACC][MIPS_TC_MAX];
	156	target_ulong DSPControl[MIPS_TC_MAX];
	157
	158	CPUMIPSMVPContext *mvp;
	159	CPUMIPSTLBContext *tlb;
	160	CPUMIPSFPUContext *fpu;
	161	uint32_t current_tc;
36d23958	162
e034e2c3 TS	163	uint32_t SEGBITS;
e034e2c3 TS	164	target_ulong SEGMask;
29929e34	165
9c2149c8	166	int32_t CP0_Index;
ead9360e	167	/* CP0_MVP* are per MVP registers. */
9c2149c8	168	int32_t CP0_Random;
ead9360e TS	169	int32_t CP0_VPEControl;
	170	#define CP0VPECo_YSI 21
	171	#define CP0VPECo_GSI 20
	172	#define CP0VPECo_EXCPT 16
	173	#define CP0VPECo_TE 15
	174	#define CP0VPECo_TargTC 0
	175	int32_t CP0_VPEConf0;
	176	#define CP0VPEC0_M 31
	177	#define CP0VPEC0_XTC 21
	178	#define CP0VPEC0_TCS 19
	179	#define CP0VPEC0_SCS 18
	180	#define CP0VPEC0_DSC 17
	181	#define CP0VPEC0_ICS 16
	182	#define CP0VPEC0_MVP 1
	183	#define CP0VPEC0_VPA 0
	184	int32_t CP0_VPEConf1;
	185	#define CP0VPEC1_NCX 20
	186	#define CP0VPEC1_NCP2 10
	187	#define CP0VPEC1_NCP1 0
	188	target_ulong CP0_YQMask;
	189	target_ulong CP0_VPESchedule;
	190	target_ulong CP0_VPEScheFBack;
	191	int32_t CP0_VPEOpt;
	192	#define CP0VPEOpt_IWX7 15
	193	#define CP0VPEOpt_IWX6 14
	194	#define CP0VPEOpt_IWX5 13
	195	#define CP0VPEOpt_IWX4 12
	196	#define CP0VPEOpt_IWX3 11
	197	#define CP0VPEOpt_IWX2 10
	198	#define CP0VPEOpt_IWX1 9
	199	#define CP0VPEOpt_IWX0 8
	200	#define CP0VPEOpt_DWX7 7
	201	#define CP0VPEOpt_DWX6 6
	202	#define CP0VPEOpt_DWX5 5
	203	#define CP0VPEOpt_DWX4 4
	204	#define CP0VPEOpt_DWX3 3
	205	#define CP0VPEOpt_DWX2 2
	206	#define CP0VPEOpt_DWX1 1
	207	#define CP0VPEOpt_DWX0 0
9c2149c8	208	target_ulong CP0_EntryLo0;
ead9360e TS	209	int32_t CP0_TCStatus[MIPS_TC_MAX];
	210	#define CP0TCSt_TCU3 31
	211	#define CP0TCSt_TCU2 30
	212	#define CP0TCSt_TCU1 29
	213	#define CP0TCSt_TCU0 28
	214	#define CP0TCSt_TMX 27
	215	#define CP0TCSt_RNST 23
	216	#define CP0TCSt_TDS 21
	217	#define CP0TCSt_DT 20
	218	#define CP0TCSt_DA 15
	219	#define CP0TCSt_A 13
	220	#define CP0TCSt_TKSU 11
	221	#define CP0TCSt_IXMT 10
	222	#define CP0TCSt_TASID 0
	223	int32_t CP0_TCBind[MIPS_TC_MAX];
	224	#define CP0TCBd_CurTC 21
	225	#define CP0TCBd_TBE 17
	226	#define CP0TCBd_CurVPE 0
	227	target_ulong CP0_TCHalt[MIPS_TC_MAX];
	228	target_ulong CP0_TCContext[MIPS_TC_MAX];
	229	target_ulong CP0_TCSchedule[MIPS_TC_MAX];
	230	target_ulong CP0_TCScheFBack[MIPS_TC_MAX];
9c2149c8 TS	231	target_ulong CP0_EntryLo1;
	232	target_ulong CP0_Context;
	233	int32_t CP0_PageMask;
	234	int32_t CP0_PageGrain;
	235	int32_t CP0_Wired;
ead9360e TS	236	int32_t CP0_SRSConf0_rw_bitmask;
	237	int32_t CP0_SRSConf0;
	238	#define CP0SRSC0_M 31
	239	#define CP0SRSC0_SRS3 20
	240	#define CP0SRSC0_SRS2 10
	241	#define CP0SRSC0_SRS1 0
	242	int32_t CP0_SRSConf1_rw_bitmask;
	243	int32_t CP0_SRSConf1;
	244	#define CP0SRSC1_M 31
	245	#define CP0SRSC1_SRS6 20
	246	#define CP0SRSC1_SRS5 10
	247	#define CP0SRSC1_SRS4 0
	248	int32_t CP0_SRSConf2_rw_bitmask;
	249	int32_t CP0_SRSConf2;
	250	#define CP0SRSC2_M 31
	251	#define CP0SRSC2_SRS9 20
	252	#define CP0SRSC2_SRS8 10
	253	#define CP0SRSC2_SRS7 0
	254	int32_t CP0_SRSConf3_rw_bitmask;
	255	int32_t CP0_SRSConf3;
	256	#define CP0SRSC3_M 31
	257	#define CP0SRSC3_SRS12 20
	258	#define CP0SRSC3_SRS11 10
	259	#define CP0SRSC3_SRS10 0
	260	int32_t CP0_SRSConf4_rw_bitmask;
	261	int32_t CP0_SRSConf4;
	262	#define CP0SRSC4_SRS15 20
	263	#define CP0SRSC4_SRS14 10
	264	#define CP0SRSC4_SRS13 0
9c2149c8	265	int32_t CP0_HWREna;
c570fd16	266	target_ulong CP0_BadVAddr;
9c2149c8 TS	267	int32_t CP0_Count;
	268	target_ulong CP0_EntryHi;
	269	int32_t CP0_Compare;
	270	int32_t CP0_Status;
6af0bf9c FB	271	#define CP0St_CU3 31
	272	#define CP0St_CU2 30
	273	#define CP0St_CU1 29
	274	#define CP0St_CU0 28
	275	#define CP0St_RP 27
6ea83fed	276	#define CP0St_FR 26
6af0bf9c	277	#define CP0St_RE 25
7a387fff TS	278	#define CP0St_MX 24
7a387fff TS	279	#define CP0St_PX 23
6af0bf9c FB	280	#define CP0St_BEV 22
	281	#define CP0St_TS 21
	282	#define CP0St_SR 20
	283	#define CP0St_NMI 19
	284	#define CP0St_IM 8
7a387fff TS	285	#define CP0St_KX 7
	286	#define CP0St_SX 6
	287	#define CP0St_UX 5
6af0bf9c	288	#define CP0St_UM 4
7a387fff	289	#define CP0St_R0 3
6af0bf9c FB	290	#define CP0St_ERL 2
	291	#define CP0St_EXL 1
	292	#define CP0St_IE 0
9c2149c8	293	int32_t CP0_IntCtl;
ead9360e TS	294	#define CP0IntCtl_IPTI 29
	295	#define CP0IntCtl_IPPC1 26
	296	#define CP0IntCtl_VS 5
9c2149c8	297	int32_t CP0_SRSCtl;
ead9360e TS	298	#define CP0SRSCtl_HSS 26
	299	#define CP0SRSCtl_EICSS 18
	300	#define CP0SRSCtl_ESS 12
	301	#define CP0SRSCtl_PSS 6
	302	#define CP0SRSCtl_CSS 0
9c2149c8	303	int32_t CP0_SRSMap;
ead9360e TS	304	#define CP0SRSMap_SSV7 28
	305	#define CP0SRSMap_SSV6 24
	306	#define CP0SRSMap_SSV5 20
	307	#define CP0SRSMap_SSV4 16
	308	#define CP0SRSMap_SSV3 12
	309	#define CP0SRSMap_SSV2 8
	310	#define CP0SRSMap_SSV1 4
	311	#define CP0SRSMap_SSV0 0
9c2149c8	312	int32_t CP0_Cause;
7a387fff TS	313	#define CP0Ca_BD 31
	314	#define CP0Ca_TI 30
	315	#define CP0Ca_CE 28
	316	#define CP0Ca_DC 27
	317	#define CP0Ca_PCI 26
6af0bf9c	318	#define CP0Ca_IV 23
7a387fff TS	319	#define CP0Ca_WP 22
7a387fff TS	320	#define CP0Ca_IP 8
4de9b249	321	#define CP0Ca_IP_mask 0x0000FF00
7a387fff	322	#define CP0Ca_EC 2
c570fd16	323	target_ulong CP0_EPC;
9c2149c8	324	int32_t CP0_PRid;
b29a0341	325	int32_t CP0_EBase;
9c2149c8	326	int32_t CP0_Config0;
6af0bf9c FB	327	#define CP0C0_M 31
	328	#define CP0C0_K23 28
	329	#define CP0C0_KU 25
	330	#define CP0C0_MDU 20
	331	#define CP0C0_MM 17
	332	#define CP0C0_BM 16
	333	#define CP0C0_BE 15
	334	#define CP0C0_AT 13
	335	#define CP0C0_AR 10
	336	#define CP0C0_MT 7
7a387fff	337	#define CP0C0_VI 3
6af0bf9c	338	#define CP0C0_K0 0
9c2149c8	339	int32_t CP0_Config1;
7a387fff	340	#define CP0C1_M 31
6af0bf9c FB	341	#define CP0C1_MMU 25
	342	#define CP0C1_IS 22
	343	#define CP0C1_IL 19
	344	#define CP0C1_IA 16
	345	#define CP0C1_DS 13
	346	#define CP0C1_DL 10
	347	#define CP0C1_DA 7
7a387fff TS	348	#define CP0C1_C2 6
7a387fff TS	349	#define CP0C1_MD 5
6af0bf9c FB	350	#define CP0C1_PC 4
	351	#define CP0C1_WR 3
	352	#define CP0C1_CA 2
	353	#define CP0C1_EP 1
	354	#define CP0C1_FP 0
9c2149c8	355	int32_t CP0_Config2;
7a387fff TS	356	#define CP0C2_M 31
	357	#define CP0C2_TU 28
	358	#define CP0C2_TS 24
	359	#define CP0C2_TL 20
	360	#define CP0C2_TA 16
	361	#define CP0C2_SU 12
	362	#define CP0C2_SS 8
	363	#define CP0C2_SL 4
	364	#define CP0C2_SA 0
9c2149c8	365	int32_t CP0_Config3;
7a387fff TS	366	#define CP0C3_M 31
	367	#define CP0C3_DSPP 10
	368	#define CP0C3_LPA 7
	369	#define CP0C3_VEIC 6
	370	#define CP0C3_VInt 5
	371	#define CP0C3_SP 4
	372	#define CP0C3_MT 2
	373	#define CP0C3_SM 1
	374	#define CP0C3_TL 0
e397ee33 TS	375	int32_t CP0_Config6;
e397ee33 TS	376	int32_t CP0_Config7;
ead9360e	377	/* XXX: Maybe make LLAddr per-TC? */
c570fd16	378	target_ulong CP0_LLAddr;
fd88b6ab TS	379	target_ulong CP0_WatchLo[8];
fd88b6ab TS	380	int32_t CP0_WatchHi[8];
9c2149c8 TS	381	target_ulong CP0_XContext;
	382	int32_t CP0_Framemask;
	383	int32_t CP0_Debug;
ead9360e	384	#define CP0DB_DBD 31
6af0bf9c FB	385	#define CP0DB_DM 30
	386	#define CP0DB_LSNM 28
	387	#define CP0DB_Doze 27
	388	#define CP0DB_Halt 26
	389	#define CP0DB_CNT 25
	390	#define CP0DB_IBEP 24
	391	#define CP0DB_DBEP 21
	392	#define CP0DB_IEXI 20
	393	#define CP0DB_VER 15
	394	#define CP0DB_DEC 10
	395	#define CP0DB_SSt 8
	396	#define CP0DB_DINT 5
	397	#define CP0DB_DIB 4
	398	#define CP0DB_DDBS 3
	399	#define CP0DB_DDBL 2
	400	#define CP0DB_DBp 1
	401	#define CP0DB_DSS 0
ead9360e	402	int32_t CP0_Debug_tcstatus[MIPS_TC_MAX];
c570fd16	403	target_ulong CP0_DEPC;
9c2149c8 TS	404	int32_t CP0_Performance0;
	405	int32_t CP0_TagLo;
	406	int32_t CP0_DataLo;
	407	int32_t CP0_TagHi;
	408	int32_t CP0_DataHi;
c570fd16	409	target_ulong CP0_ErrorEPC;
9c2149c8	410	int32_t CP0_DESAVE;
6af0bf9c	411	/* Qemu */
6af0bf9c FB	412	int interrupt_request;
	413	jmp_buf jmp_env;
	414	int exception_index;
	415	int error_code;
	416	int user_mode_only; /* user mode only simulation */
	417	uint32_t hflags; /* CPU State */
	418	/* TMASK defines different execution modes */
387a8fe5	419	#define MIPS_HFLAG_TMASK 0x00FF
78749ba8	420	#define MIPS_HFLAG_MODE 0x0007 /* execution modes */
6af0bf9c	421	#define MIPS_HFLAG_UM 0x0001 /* user mode */
5e755519 TS	422	#define MIPS_HFLAG_DM 0x0002 /* Debug mode */
	423	#define MIPS_HFLAG_SM 0x0004 /* Supervisor mode */
	424	#define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
387a8fe5 TS	425	#define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
	426	#define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
	427	#define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
	428	#define MIPS_HFLAG_RE 0x0080 /* Reversed endianness */
4ad40f36 FB	429	/* If translation is interrupted between the branch instruction and
	430	* the delay slot, record what type of branch it is so that we can
	431	* resume translation properly. It might be possible to reduce
	432	* this from three bits to two. */
387a8fe5 TS	433	#define MIPS_HFLAG_BMASK 0x0700
	434	#define MIPS_HFLAG_B 0x0100 /* Unconditional branch */
	435	#define MIPS_HFLAG_BC 0x0200 /* Conditional branch */
	436	#define MIPS_HFLAG_BL 0x0300 /* Likely branch */
	437	#define MIPS_HFLAG_BR 0x0400 /* branch to register (can't link TB) */
6af0bf9c FB	438	target_ulong btarget; /* Jump / branch target */
6af0bf9c FB	439	int bcond; /* Branch condition (if needed) */
a316d335	440
4ad40f36 FB	441	int halted; /* TRUE if the CPU is in suspend state */
4ad40f36 FB	442
7a387fff TS	443	int SYNCI_Step; /* Address step size for SYNCI */
7a387fff TS	444	int CCRes; /* Cycle count resolution/divisor */
ead9360e TS	445	uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
ead9360e TS	446	uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
e189e748	447	int insn_flags; /* Supported instruction set */
7a387fff	448
33ac7f16	449	#ifdef CONFIG_USER_ONLY
6f5b89a0 TS	450	target_ulong tls_value;
	451	#endif
	452
a316d335	453	CPU_COMMON
6ae81775 TS	454
	455	int ram_size;
	456	const char *kernel_filename;
	457	const char *kernel_cmdline;
	458	const char *initrd_filename;
	459
51b2772f	460	mips_def_t *cpu_model;
33ac7f16 TS	461	#ifndef CONFIG_USER_ONLY
	462	void *irq[8];
	463	#endif
51b2772f	464
6ae81775	465	struct QEMUTimer timer; / Internal timer */
6af0bf9c FB	466	};
6af0bf9c FB	467
29929e34 TS	468	int no_mmu_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	469	target_ulong address, int rw, int access_type);
	470	int fixed_mmu_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	471	target_ulong address, int rw, int access_type);
	472	int r4k_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	473	target_ulong address, int rw, int access_type);
	474	void r4k_do_tlbwi (void);
	475	void r4k_do_tlbwr (void);
	476	void r4k_do_tlbp (void);
	477	void r4k_do_tlbr (void);
33d68b5f TS	478	int mips_find_by_name (const unsigned char name, mips_def_t *def);
	479	void mips_cpu_list (FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...));
	480	int cpu_mips_register (CPUMIPSState env, mips_def_t def);
	481
647de6ca TS	482	void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
	483	int unused);
	484
9467d44c TS	485	#define CPUState CPUMIPSState
	486	#define cpu_init cpu_mips_init
	487	#define cpu_exec cpu_mips_exec
	488	#define cpu_gen_code cpu_mips_gen_code
	489	#define cpu_signal_handler cpu_mips_signal_handler
c732abe2	490	#define cpu_list mips_cpu_list
9467d44c	491
6ebbf390 JM	492	/* MMU modes definitions */
	493	#define MMU_MODE0_SUFFIX _kernel
	494	#define MMU_MODE1_SUFFIX _user
	495	#define MMU_USER_IDX 1
	496	static inline int cpu_mmu_index (CPUState *env)
	497	{
	498	return (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 1 : 0;
	499	}
	500
6af0bf9c FB	501	#include "cpu-all.h"
	502
	503	/* Memory access type :
	504	* may be needed for precise access rights control and precise exceptions.
	505	*/
	506	enum {
	507	/* 1 bit to define user level / supervisor access */
	508	ACCESS_USER = 0x00,
	509	ACCESS_SUPER = 0x01,
	510	/* 1 bit to indicate direction */
	511	ACCESS_STORE = 0x02,
	512	/* Type of instruction that generated the access */
	513	ACCESS_CODE = 0x10, /* Code fetch access */
	514	ACCESS_INT = 0x20, /* Integer load/store access */
	515	ACCESS_FLOAT = 0x30, /* floating point load/store access */
	516	};
	517
	518	/* Exceptions */
	519	enum {
	520	EXCP_NONE = -1,
	521	EXCP_RESET = 0,
	522	EXCP_SRESET,
	523	EXCP_DSS,
	524	EXCP_DINT,
	525	EXCP_NMI,
	526	EXCP_MCHECK,
	527	EXCP_EXT_INTERRUPT,
	528	EXCP_DFWATCH,
	529	EXCP_DIB, /* 8 */
	530	EXCP_IWATCH,
	531	EXCP_AdEL,
	532	EXCP_AdES,
	533	EXCP_TLBF,
	534	EXCP_IBE,
	535	EXCP_DBp,
	536	EXCP_SYSCALL,
4ad40f36 FB	537	EXCP_BREAK, /* 16 */
4ad40f36 FB	538	EXCP_CpU,
6af0bf9c FB	539	EXCP_RI,
	540	EXCP_OVERFLOW,
	541	EXCP_TRAP,
5a5012ec	542	EXCP_FPE,
6af0bf9c FB	543	EXCP_DDBS,
6af0bf9c FB	544	EXCP_DWATCH,
5a5012ec TS	545	EXCP_LAE, /* 24 */
5a5012ec TS	546	EXCP_SAE,
6af0bf9c FB	547	EXCP_LTLBL,
	548	EXCP_TLBL,
	549	EXCP_TLBS,
	550	EXCP_DBE,
	551	EXCP_DDBL,
ead9360e	552	EXCP_THREAD,
6af0bf9c FB	553	EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
	554	/* may change privilege level */
	555	EXCP_BRANCH = 0x108, /* branch instruction */
	556	EXCP_ERET = 0x10C, /* return from interrupt */
	557	EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
	558	EXCP_FLUSH = 0x109,
	559	};
	560
6af0bf9c FB	561	int cpu_mips_exec(CPUMIPSState *s);
	562	CPUMIPSState *cpu_mips_init(void);
	563	uint32_t cpu_mips_get_clock (void);
388bb21a	564	int cpu_mips_signal_handler(int host_signum, void pinfo, void puc);
6af0bf9c FB	565
6af0bf9c FB	566	#endif /* !defined (__MIPS_CPU_H__) */