[mirror_qemu.git] / target-mips / cpu.h

#if !defined (__MIPS_CPU_H__)
#define __MIPS_CPU_H__

#define TARGET_HAS_ICE 1

#define ELF_MACHINE	EM_MIPS

#include "config.h"
#include "mips-defs.h"
#include "cpu-defs.h"
#include "softfloat.h"

// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
// XXX: move that elsewhere
#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
typedef unsigned char           uint_fast8_t;
typedef unsigned int            uint_fast16_t;
#endif

typedef union fpr_t fpr_t;
union fpr_t {
    float64  fd;   /* ieee double precision */
    float32  fs[2];/* ieee single precision */
    uint64_t d;    /* binary double fixed-point */
    uint32_t w[2]; /* binary single fixed-point */
};
/* define FP_ENDIAN_IDX to access the same location
 * in the fpr_t union regardless of the host endianess
 */
#if defined(WORDS_BIGENDIAN)
#  define FP_ENDIAN_IDX 1
#else
#  define FP_ENDIAN_IDX 0
#endif

typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t {
    target_ulong VPN;
    uint32_t PageMask;
    uint_fast8_t ASID;
    uint_fast16_t G:1;
    uint_fast16_t C0:3;
    uint_fast16_t C1:3;
    uint_fast16_t V0:1;
    uint_fast16_t V1:1;
    uint_fast16_t D0:1;
    uint_fast16_t D1:1;
    target_ulong PFN[2];
};

typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
    /* General integer registers */
    target_ulong gpr[32];
    /* Special registers */
    target_ulong PC;
#if TARGET_LONG_BITS > HOST_LONG_BITS
    target_ulong t0;
    target_ulong t1;
    target_ulong t2;
#endif
    target_ulong HI, LO;
    /* Floating point registers */
    fpr_t fpr[32];
#ifndef USE_HOST_FLOAT_REGS
    fpr_t ft0;
    fpr_t ft1;
    fpr_t ft2;
#endif
    float_status fp_status;
    /* fpu implementation/revision register (fir) */
    uint32_t fcr0;
#define FCR0_F64 22
#define FCR0_L 21
#define FCR0_W 20
#define FCR0_3D 19
#define FCR0_PS 18
#define FCR0_D 17
#define FCR0_S 16
#define FCR0_PRID 8
#define FCR0_REV 0
    /* fcsr */
    uint32_t fcr31;
#define SET_FP_COND(num,env)     do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define CLEAR_FP_COND(num,env)   do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define GET_FP_COND(env)         ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
#define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
#define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
#define FP_INEXACT        1
#define FP_UNDERFLOW      2
#define FP_OVERFLOW       4
#define FP_DIV0           8
#define FP_INVALID        16
#define FP_UNIMPLEMENTED  32

    uint32_t nb_tlb;
    uint32_t tlb_in_use;
    int (*map_address) (CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
    void (*do_tlbwi) (void);
    void (*do_tlbwr) (void);
    void (*do_tlbp) (void);
    void (*do_tlbr) (void);
    union {
        struct {
            r4k_tlb_t tlb[MIPS_TLB_MAX];
        } r4k;
    } mmu;

    int32_t CP0_Index;
    int32_t CP0_Random;
    target_ulong CP0_EntryLo0;
    target_ulong CP0_EntryLo1;
    target_ulong CP0_Context;
    int32_t CP0_PageMask;
    int32_t CP0_PageGrain;
    int32_t CP0_Wired;
    int32_t CP0_HWREna;
    target_ulong CP0_BadVAddr;
    int32_t CP0_Count;
    target_ulong CP0_EntryHi;
    int32_t CP0_Compare;
    int32_t CP0_Status;
#define CP0St_CU3   31
#define CP0St_CU2   30
#define CP0St_CU1   29
#define CP0St_CU0   28
#define CP0St_RP    27
#define CP0St_FR    26
#define CP0St_RE    25
#define CP0St_MX    24
#define CP0St_PX    23
#define CP0St_BEV   22
#define CP0St_TS    21
#define CP0St_SR    20
#define CP0St_NMI   19
#define CP0St_IM    8
#define CP0St_KX    7
#define CP0St_SX    6
#define CP0St_UX    5
#define CP0St_UM    4
#define CP0St_R0    3
#define CP0St_ERL   2
#define CP0St_EXL   1
#define CP0St_IE    0
    int32_t CP0_IntCtl;
    int32_t CP0_SRSCtl;
    int32_t CP0_SRSMap;
    int32_t CP0_Cause;
#define CP0Ca_BD   31
#define CP0Ca_TI   30
#define CP0Ca_CE   28
#define CP0Ca_DC   27
#define CP0Ca_PCI  26
#define CP0Ca_IV   23
#define CP0Ca_WP   22
#define CP0Ca_IP    8
#define CP0Ca_IP_mask 0x0000FF00
#define CP0Ca_EC    2
    target_ulong CP0_EPC;
    int32_t CP0_PRid;
    int32_t CP0_EBase;
    int32_t CP0_Config0;
#define CP0C0_M    31
#define CP0C0_K23  28
#define CP0C0_KU   25
#define CP0C0_MDU  20
#define CP0C0_MM   17
#define CP0C0_BM   16
#define CP0C0_BE   15
#define CP0C0_AT   13
#define CP0C0_AR   10
#define CP0C0_MT   7
#define CP0C0_VI   3
#define CP0C0_K0   0
    int32_t CP0_Config1;
#define CP0C1_M    31
#define CP0C1_MMU  25
#define CP0C1_IS   22
#define CP0C1_IL   19
#define CP0C1_IA   16
#define CP0C1_DS   13
#define CP0C1_DL   10
#define CP0C1_DA   7
#define CP0C1_C2   6
#define CP0C1_MD   5
#define CP0C1_PC   4
#define CP0C1_WR   3
#define CP0C1_CA   2
#define CP0C1_EP   1
#define CP0C1_FP   0
    int32_t CP0_Config2;
#define CP0C2_M    31
#define CP0C2_TU   28
#define CP0C2_TS   24
#define CP0C2_TL   20
#define CP0C2_TA   16
#define CP0C2_SU   12
#define CP0C2_SS   8
#define CP0C2_SL   4
#define CP0C2_SA   0
    int32_t CP0_Config3;
#define CP0C3_M    31
#define CP0C3_DSPP 10
#define CP0C3_LPA  7
#define CP0C3_VEIC 6
#define CP0C3_VInt 5
#define CP0C3_SP   4
#define CP0C3_MT   2
#define CP0C3_SM   1
#define CP0C3_TL   0
    int32_t CP0_Config6;
    int32_t CP0_Config7;
    target_ulong CP0_LLAddr;
    target_ulong CP0_WatchLo;
    int32_t CP0_WatchHi;
    target_ulong CP0_XContext;
    int32_t CP0_Framemask;
    int32_t CP0_Debug;
#define CPDB_DBD   31
#define CP0DB_DM   30
#define CP0DB_LSNM 28
#define CP0DB_Doze 27
#define CP0DB_Halt 26
#define CP0DB_CNT  25
#define CP0DB_IBEP 24
#define CP0DB_DBEP 21
#define CP0DB_IEXI 20
#define CP0DB_VER  15
#define CP0DB_DEC  10
#define CP0DB_SSt  8
#define CP0DB_DINT 5
#define CP0DB_DIB  4
#define CP0DB_DDBS 3
#define CP0DB_DDBL 2
#define CP0DB_DBp  1
#define CP0DB_DSS  0
    target_ulong CP0_DEPC;
    int32_t CP0_Performance0;
    int32_t CP0_TagLo;
    int32_t CP0_DataLo;
    int32_t CP0_TagHi;
    int32_t CP0_DataHi;
    target_ulong CP0_ErrorEPC;
    int32_t CP0_DESAVE;
    /* Qemu */
    int interrupt_request;
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    int user_mode_only; /* user mode only simulation */
    uint32_t hflags;    /* CPU State */
    /* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK  0x007F
#define MIPS_HFLAG_MODE   0x001F /* execution modes                    */
#define MIPS_HFLAG_UM     0x0001 /* user mode                          */
#define MIPS_HFLAG_DM     0x0008 /* Debug mode                         */
#define MIPS_HFLAG_SM     0x0010 /* Supervisor mode                    */
#define MIPS_HFLAG_RE     0x0040 /* Reversed endianness                */
    /* If translation is interrupted between the branch instruction and
     * the delay slot, record what type of branch it is so that we can
     * resume translation properly.  It might be possible to reduce
     * this from three bits to two.  */
#define MIPS_HFLAG_BMASK  0x0380
#define MIPS_HFLAG_B      0x0080 /* Unconditional branch               */
#define MIPS_HFLAG_BC     0x0100 /* Conditional branch                 */
#define MIPS_HFLAG_BL     0x0180 /* Likely branch                      */
#define MIPS_HFLAG_BR     0x0200 /* branch to register (can't link TB) */
    target_ulong btarget;        /* Jump / branch target               */
    int bcond;                   /* Branch condition (if needed)       */

    int halted; /* TRUE if the CPU is in suspend state */

    int SYNCI_Step; /* Address step size for SYNCI */
    int CCRes; /* Cycle count resolution/divisor */
    int Status_rw_bitmask; /* Read/write bits in CP0_Status */

#if defined(CONFIG_USER_ONLY)
    target_ulong tls_value;
#else
    void *irq[8];
#endif

    CPU_COMMON

    int ram_size;
    const char *kernel_filename;
    const char *kernel_cmdline;
    const char *initrd_filename;

    struct QEMUTimer *timer; /* Internal timer */
};

int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                        target_ulong address, int rw, int access_type);
int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                           target_ulong address, int rw, int access_type);
int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                     target_ulong address, int rw, int access_type);
void r4k_do_tlbwi (void);
void r4k_do_tlbwr (void);
void r4k_do_tlbp (void);
void r4k_do_tlbr (void);
typedef struct mips_def_t mips_def_t;
int mips_find_by_name (const unsigned char *name, mips_def_t **def);
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);

#include "cpu-all.h"

/* Memory access type :
 * may be needed for precise access rights control and precise exceptions.
 */
enum {
    /* 1 bit to define user level / supervisor access */
    ACCESS_USER  = 0x00,
    ACCESS_SUPER = 0x01,
    /* 1 bit to indicate direction */
    ACCESS_STORE = 0x02,
    /* Type of instruction that generated the access */
    ACCESS_CODE  = 0x10, /* Code fetch access                */
    ACCESS_INT   = 0x20, /* Integer load/store access        */
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
};

/* Exceptions */
enum {
    EXCP_NONE          = -1,
    EXCP_RESET         = 0,
    EXCP_SRESET,
    EXCP_DSS,
    EXCP_DINT,
    EXCP_NMI,
    EXCP_MCHECK,
    EXCP_EXT_INTERRUPT,
    EXCP_DFWATCH,
    EXCP_DIB, /* 8 */
    EXCP_IWATCH,
    EXCP_AdEL,
    EXCP_AdES,
    EXCP_TLBF,
    EXCP_IBE,
    EXCP_DBp,
    EXCP_SYSCALL,
    EXCP_BREAK, /* 16 */
    EXCP_CpU,
    EXCP_RI,
    EXCP_OVERFLOW,
    EXCP_TRAP,
    EXCP_FPE,
    EXCP_DDBS,
    EXCP_DWATCH,
    EXCP_LAE, /* 24 */
    EXCP_SAE,
    EXCP_LTLBL,
    EXCP_TLBL,
    EXCP_TLBS,
    EXCP_DBE,
    EXCP_DDBL,
    EXCP_MTCP0         = 0x104, /* mtmsr instruction:               */
                                /* may change privilege level       */
    EXCP_BRANCH        = 0x108, /* branch instruction               */
    EXCP_ERET          = 0x10C, /* return from interrupt            */
    EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
    EXCP_FLUSH         = 0x109,
};

int cpu_mips_exec(CPUMIPSState *s);
CPUMIPSState *cpu_mips_init(void);
uint32_t cpu_mips_get_clock (void);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);

#endif /* !defined (__MIPS_CPU_H__) */
Commit	Line	Data
6af0bf9c FB	1	#if !defined (__MIPS_CPU_H__)
	2	#define __MIPS_CPU_H__
	3
4ad40f36 FB	4	#define TARGET_HAS_ICE 1
4ad40f36 FB	5
9042c0e2 TS	6	#define ELF_MACHINE EM_MIPS
9042c0e2 TS	7
c5d6edc3	8	#include "config.h"
6af0bf9c FB	9	#include "mips-defs.h"
6af0bf9c FB	10	#include "cpu-defs.h"
6af0bf9c FB	11	#include "softfloat.h"
6af0bf9c FB	12
fdbb4691 FB	13	// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
fdbb4691 FB	14	// XXX: move that elsewhere
36bb244b	15	#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
fdbb4691 FB	16	typedef unsigned char uint_fast8_t;
	17	typedef unsigned int uint_fast16_t;
	18	#endif
	19
6af0bf9c FB	20	typedef union fpr_t fpr_t;
6af0bf9c FB	21	union fpr_t {
6ea83fed FB	22	float64 fd; /* ieee double precision */
6ea83fed FB	23	float32 fs[2];/* ieee single precision */
5a5012ec	24	uint64_t d; /* binary double fixed-point */
6ea83fed	25	uint32_t w[2]; /* binary single fixed-point */
6af0bf9c	26	};
6ea83fed FB	27	/* define FP_ENDIAN_IDX to access the same location
	28	* in the fpr_t union regardless of the host endianess
	29	*/
	30	#if defined(WORDS_BIGENDIAN)
	31	# define FP_ENDIAN_IDX 1
	32	#else
	33	# define FP_ENDIAN_IDX 0
	34	#endif
6af0bf9c	35
29929e34 TS	36	typedef struct r4k_tlb_t r4k_tlb_t;
29929e34 TS	37	struct r4k_tlb_t {
6af0bf9c	38	target_ulong VPN;
9c2149c8	39	uint32_t PageMask;
98c1b82b PB	40	uint_fast8_t ASID;
	41	uint_fast16_t G:1;
	42	uint_fast16_t C0:3;
	43	uint_fast16_t C1:3;
	44	uint_fast16_t V0:1;
	45	uint_fast16_t V1:1;
	46	uint_fast16_t D0:1;
	47	uint_fast16_t D1:1;
6af0bf9c FB	48	target_ulong PFN[2];
6af0bf9c FB	49	};
6af0bf9c FB	50
	51	typedef struct CPUMIPSState CPUMIPSState;
	52	struct CPUMIPSState {
	53	/* General integer registers */
	54	target_ulong gpr[32];
	55	/* Special registers */
	56	target_ulong PC;
c570fd16 TS	57	#if TARGET_LONG_BITS > HOST_LONG_BITS
	58	target_ulong t0;
	59	target_ulong t1;
	60	target_ulong t2;
	61	#endif
	62	target_ulong HI, LO;
6af0bf9c	63	/* Floating point registers */
f7cfb2a1	64	fpr_t fpr[32];
6ea83fed FB	65	#ifndef USE_HOST_FLOAT_REGS
	66	fpr_t ft0;
	67	fpr_t ft1;
	68	fpr_t ft2;
	69	#endif
	70	float_status fp_status;
5a5012ec	71	/* fpu implementation/revision register (fir) */
6af0bf9c	72	uint32_t fcr0;
5a5012ec TS	73	#define FCR0_F64 22
	74	#define FCR0_L 21
	75	#define FCR0_W 20
	76	#define FCR0_3D 19
	77	#define FCR0_PS 18
	78	#define FCR0_D 17
	79	#define FCR0_S 16
	80	#define FCR0_PRID 8
	81	#define FCR0_REV 0
6ea83fed FB	82	/* fcsr */
6ea83fed FB	83	uint32_t fcr31;
fd4a04eb TS	84	#define SET_FP_COND(num,env) do { ((env)->fcr31) \|= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
	85	#define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
	86	#define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) \| (((env)->fcr31 >> 23) & 0x1))
5a5012ec TS	87	#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
	88	#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
	89	#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
	90	#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) \| ((v & 0x3f) << 12); } while(0)
	91	#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) \| ((v & 0x1f) << 7); } while(0)
	92	#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) \| ((v & 0x1f) << 2); } while(0)
	93	#define UPDATE_FP_FLAGS(reg,v) do { (reg) \|= ((v & 0x1f) << 2); } while(0)
6ea83fed FB	94	#define FP_INEXACT 1
	95	#define FP_UNDERFLOW 2
	96	#define FP_OVERFLOW 4
	97	#define FP_DIV0 8
	98	#define FP_INVALID 16
	99	#define FP_UNIMPLEMENTED 32
36d23958	100
fcb4a419	101	uint32_t nb_tlb;
29929e34 TS	102	uint32_t tlb_in_use;
	103	int (map_address) (CPUMIPSState env, target_ulong physical, int prot, target_ulong address, int rw, int access_type);
	104	void (*do_tlbwi) (void);
	105	void (*do_tlbwr) (void);
	106	void (*do_tlbp) (void);
	107	void (*do_tlbr) (void);
	108	union {
	109	struct {
	110	r4k_tlb_t tlb[MIPS_TLB_MAX];
	111	} r4k;
	112	} mmu;
	113
9c2149c8 TS	114	int32_t CP0_Index;
	115	int32_t CP0_Random;
	116	target_ulong CP0_EntryLo0;
	117	target_ulong CP0_EntryLo1;
	118	target_ulong CP0_Context;
	119	int32_t CP0_PageMask;
	120	int32_t CP0_PageGrain;
	121	int32_t CP0_Wired;
	122	int32_t CP0_HWREna;
c570fd16	123	target_ulong CP0_BadVAddr;
9c2149c8 TS	124	int32_t CP0_Count;
	125	target_ulong CP0_EntryHi;
	126	int32_t CP0_Compare;
	127	int32_t CP0_Status;
6af0bf9c FB	128	#define CP0St_CU3 31
	129	#define CP0St_CU2 30
	130	#define CP0St_CU1 29
	131	#define CP0St_CU0 28
	132	#define CP0St_RP 27
6ea83fed	133	#define CP0St_FR 26
6af0bf9c	134	#define CP0St_RE 25
7a387fff TS	135	#define CP0St_MX 24
7a387fff TS	136	#define CP0St_PX 23
6af0bf9c FB	137	#define CP0St_BEV 22
	138	#define CP0St_TS 21
	139	#define CP0St_SR 20
	140	#define CP0St_NMI 19
	141	#define CP0St_IM 8
7a387fff TS	142	#define CP0St_KX 7
	143	#define CP0St_SX 6
	144	#define CP0St_UX 5
6af0bf9c	145	#define CP0St_UM 4
7a387fff	146	#define CP0St_R0 3
6af0bf9c FB	147	#define CP0St_ERL 2
	148	#define CP0St_EXL 1
	149	#define CP0St_IE 0
9c2149c8 TS	150	int32_t CP0_IntCtl;
	151	int32_t CP0_SRSCtl;
	152	int32_t CP0_SRSMap;
	153	int32_t CP0_Cause;
7a387fff TS	154	#define CP0Ca_BD 31
	155	#define CP0Ca_TI 30
	156	#define CP0Ca_CE 28
	157	#define CP0Ca_DC 27
	158	#define CP0Ca_PCI 26
6af0bf9c	159	#define CP0Ca_IV 23
7a387fff TS	160	#define CP0Ca_WP 22
7a387fff TS	161	#define CP0Ca_IP 8
4de9b249	162	#define CP0Ca_IP_mask 0x0000FF00
7a387fff	163	#define CP0Ca_EC 2
c570fd16	164	target_ulong CP0_EPC;
9c2149c8	165	int32_t CP0_PRid;
b29a0341	166	int32_t CP0_EBase;
9c2149c8	167	int32_t CP0_Config0;
6af0bf9c FB	168	#define CP0C0_M 31
	169	#define CP0C0_K23 28
	170	#define CP0C0_KU 25
	171	#define CP0C0_MDU 20
	172	#define CP0C0_MM 17
	173	#define CP0C0_BM 16
	174	#define CP0C0_BE 15
	175	#define CP0C0_AT 13
	176	#define CP0C0_AR 10
	177	#define CP0C0_MT 7
7a387fff	178	#define CP0C0_VI 3
6af0bf9c	179	#define CP0C0_K0 0
9c2149c8	180	int32_t CP0_Config1;
7a387fff	181	#define CP0C1_M 31
6af0bf9c FB	182	#define CP0C1_MMU 25
	183	#define CP0C1_IS 22
	184	#define CP0C1_IL 19
	185	#define CP0C1_IA 16
	186	#define CP0C1_DS 13
	187	#define CP0C1_DL 10
	188	#define CP0C1_DA 7
7a387fff TS	189	#define CP0C1_C2 6
7a387fff TS	190	#define CP0C1_MD 5
6af0bf9c FB	191	#define CP0C1_PC 4
	192	#define CP0C1_WR 3
	193	#define CP0C1_CA 2
	194	#define CP0C1_EP 1
	195	#define CP0C1_FP 0
9c2149c8	196	int32_t CP0_Config2;
7a387fff TS	197	#define CP0C2_M 31
	198	#define CP0C2_TU 28
	199	#define CP0C2_TS 24
	200	#define CP0C2_TL 20
	201	#define CP0C2_TA 16
	202	#define CP0C2_SU 12
	203	#define CP0C2_SS 8
	204	#define CP0C2_SL 4
	205	#define CP0C2_SA 0
9c2149c8	206	int32_t CP0_Config3;
7a387fff TS	207	#define CP0C3_M 31
	208	#define CP0C3_DSPP 10
	209	#define CP0C3_LPA 7
	210	#define CP0C3_VEIC 6
	211	#define CP0C3_VInt 5
	212	#define CP0C3_SP 4
	213	#define CP0C3_MT 2
	214	#define CP0C3_SM 1
	215	#define CP0C3_TL 0
e397ee33 TS	216	int32_t CP0_Config6;
e397ee33 TS	217	int32_t CP0_Config7;
c570fd16	218	target_ulong CP0_LLAddr;
9c2149c8 TS	219	target_ulong CP0_WatchLo;
	220	int32_t CP0_WatchHi;
	221	target_ulong CP0_XContext;
	222	int32_t CP0_Framemask;
	223	int32_t CP0_Debug;
6af0bf9c FB	224	#define CPDB_DBD 31
	225	#define CP0DB_DM 30
	226	#define CP0DB_LSNM 28
	227	#define CP0DB_Doze 27
	228	#define CP0DB_Halt 26
	229	#define CP0DB_CNT 25
	230	#define CP0DB_IBEP 24
	231	#define CP0DB_DBEP 21
	232	#define CP0DB_IEXI 20
	233	#define CP0DB_VER 15
	234	#define CP0DB_DEC 10
	235	#define CP0DB_SSt 8
	236	#define CP0DB_DINT 5
	237	#define CP0DB_DIB 4
	238	#define CP0DB_DDBS 3
	239	#define CP0DB_DDBL 2
	240	#define CP0DB_DBp 1
	241	#define CP0DB_DSS 0
c570fd16	242	target_ulong CP0_DEPC;
9c2149c8 TS	243	int32_t CP0_Performance0;
	244	int32_t CP0_TagLo;
	245	int32_t CP0_DataLo;
	246	int32_t CP0_TagHi;
	247	int32_t CP0_DataHi;
c570fd16	248	target_ulong CP0_ErrorEPC;
9c2149c8	249	int32_t CP0_DESAVE;
6af0bf9c	250	/* Qemu */
6af0bf9c FB	251	int interrupt_request;
	252	jmp_buf jmp_env;
	253	int exception_index;
	254	int error_code;
	255	int user_mode_only; /* user mode only simulation */
	256	uint32_t hflags; /* CPU State */
	257	/* TMASK defines different execution modes */
56b19403	258	#define MIPS_HFLAG_TMASK 0x007F
6af0bf9c FB	259	#define MIPS_HFLAG_MODE 0x001F /* execution modes */
6af0bf9c FB	260	#define MIPS_HFLAG_UM 0x0001 /* user mode */
6af0bf9c FB	261	#define MIPS_HFLAG_DM 0x0008 /* Debug mode */
	262	#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
	263	#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
4ad40f36 FB	264	/* If translation is interrupted between the branch instruction and
	265	* the delay slot, record what type of branch it is so that we can
	266	* resume translation properly. It might be possible to reduce
	267	* this from three bits to two. */
	268	#define MIPS_HFLAG_BMASK 0x0380
	269	#define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
	270	#define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
	271	#define MIPS_HFLAG_BL 0x0180 /* Likely branch */
	272	#define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
6af0bf9c FB	273	target_ulong btarget; /* Jump / branch target */
6af0bf9c FB	274	int bcond; /* Branch condition (if needed) */
a316d335	275
4ad40f36 FB	276	int halted; /* TRUE if the CPU is in suspend state */
4ad40f36 FB	277
7a387fff TS	278	int SYNCI_Step; /* Address step size for SYNCI */
7a387fff TS	279	int CCRes; /* Cycle count resolution/divisor */
5a5012ec	280	int Status_rw_bitmask; /* Read/write bits in CP0_Status */
7a387fff	281
6f5b89a0 TS	282	#if defined(CONFIG_USER_ONLY)
6f5b89a0 TS	283	target_ulong tls_value;
d537cf6c PB	284	#else
d537cf6c PB	285	void *irq[8];
6f5b89a0 TS	286	#endif
6f5b89a0 TS	287
a316d335	288	CPU_COMMON
6ae81775 TS	289
	290	int ram_size;
	291	const char *kernel_filename;
	292	const char *kernel_cmdline;
	293	const char *initrd_filename;
	294
	295	struct QEMUTimer timer; / Internal timer */
6af0bf9c FB	296	};
6af0bf9c FB	297
29929e34 TS	298	int no_mmu_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	299	target_ulong address, int rw, int access_type);
	300	int fixed_mmu_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	301	target_ulong address, int rw, int access_type);
	302	int r4k_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	303	target_ulong address, int rw, int access_type);
	304	void r4k_do_tlbwi (void);
	305	void r4k_do_tlbwr (void);
	306	void r4k_do_tlbp (void);
	307	void r4k_do_tlbr (void);
33d68b5f TS	308	typedef struct mips_def_t mips_def_t;
	309	int mips_find_by_name (const unsigned char name, mips_def_t *def);
	310	void mips_cpu_list (FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...));
	311	int cpu_mips_register (CPUMIPSState env, mips_def_t def);
	312
6af0bf9c FB	313	#include "cpu-all.h"
	314
	315	/* Memory access type :
	316	* may be needed for precise access rights control and precise exceptions.
	317	*/
	318	enum {
	319	/* 1 bit to define user level / supervisor access */
	320	ACCESS_USER = 0x00,
	321	ACCESS_SUPER = 0x01,
	322	/* 1 bit to indicate direction */
	323	ACCESS_STORE = 0x02,
	324	/* Type of instruction that generated the access */
	325	ACCESS_CODE = 0x10, /* Code fetch access */
	326	ACCESS_INT = 0x20, /* Integer load/store access */
	327	ACCESS_FLOAT = 0x30, /* floating point load/store access */
	328	};
	329
	330	/* Exceptions */
	331	enum {
	332	EXCP_NONE = -1,
	333	EXCP_RESET = 0,
	334	EXCP_SRESET,
	335	EXCP_DSS,
	336	EXCP_DINT,
	337	EXCP_NMI,
	338	EXCP_MCHECK,
	339	EXCP_EXT_INTERRUPT,
	340	EXCP_DFWATCH,
	341	EXCP_DIB, /* 8 */
	342	EXCP_IWATCH,
	343	EXCP_AdEL,
	344	EXCP_AdES,
	345	EXCP_TLBF,
	346	EXCP_IBE,
	347	EXCP_DBp,
	348	EXCP_SYSCALL,
4ad40f36 FB	349	EXCP_BREAK, /* 16 */
4ad40f36 FB	350	EXCP_CpU,
6af0bf9c FB	351	EXCP_RI,
	352	EXCP_OVERFLOW,
	353	EXCP_TRAP,
5a5012ec	354	EXCP_FPE,
6af0bf9c FB	355	EXCP_DDBS,
6af0bf9c FB	356	EXCP_DWATCH,
5a5012ec TS	357	EXCP_LAE, /* 24 */
5a5012ec TS	358	EXCP_SAE,
6af0bf9c FB	359	EXCP_LTLBL,
	360	EXCP_TLBL,
	361	EXCP_TLBS,
	362	EXCP_DBE,
	363	EXCP_DDBL,
	364	EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
	365	/* may change privilege level */
	366	EXCP_BRANCH = 0x108, /* branch instruction */
	367	EXCP_ERET = 0x10C, /* return from interrupt */
	368	EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
	369	EXCP_FLUSH = 0x109,
	370	};
	371
6af0bf9c FB	372	int cpu_mips_exec(CPUMIPSState *s);
	373	CPUMIPSState *cpu_mips_init(void);
	374	uint32_t cpu_mips_get_clock (void);
388bb21a	375	int cpu_mips_signal_handler(int host_signum, void pinfo, void puc);
6af0bf9c FB	376
6af0bf9c FB	377	#endif /* !defined (__MIPS_CPU_H__) */