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Commit | Line | Data |
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6af0bf9c FB |
1 | #if !defined (__MIPS_CPU_H__) |
2 | #define __MIPS_CPU_H__ | |
3 | ||
3e457172 BS |
4 | //#define DEBUG_OP |
5 | ||
d94f0a8e | 6 | #define ALIGNED_ONLY |
4ad40f36 FB |
7 | #define TARGET_HAS_ICE 1 |
8 | ||
9042c0e2 TS |
9 | #define ELF_MACHINE EM_MIPS |
10 | ||
9349b4f9 | 11 | #define CPUArchState struct CPUMIPSState |
c2764719 | 12 | |
c5d6edc3 | 13 | #include "config.h" |
9a78eead | 14 | #include "qemu-common.h" |
6af0bf9c | 15 | #include "mips-defs.h" |
022c62cb | 16 | #include "exec/cpu-defs.h" |
6b4c305c | 17 | #include "fpu/softfloat.h" |
6af0bf9c | 18 | |
ead9360e | 19 | struct CPUMIPSState; |
6af0bf9c | 20 | |
c227f099 AL |
21 | typedef struct r4k_tlb_t r4k_tlb_t; |
22 | struct r4k_tlb_t { | |
6af0bf9c | 23 | target_ulong VPN; |
9c2149c8 | 24 | uint32_t PageMask; |
98c1b82b PB |
25 | uint_fast8_t ASID; |
26 | uint_fast16_t G:1; | |
27 | uint_fast16_t C0:3; | |
28 | uint_fast16_t C1:3; | |
29 | uint_fast16_t V0:1; | |
30 | uint_fast16_t V1:1; | |
31 | uint_fast16_t D0:1; | |
32 | uint_fast16_t D1:1; | |
2fb58b73 LA |
33 | uint_fast16_t XI0:1; |
34 | uint_fast16_t XI1:1; | |
35 | uint_fast16_t RI0:1; | |
36 | uint_fast16_t RI1:1; | |
9456c2fb | 37 | uint_fast16_t EHINV:1; |
6af0bf9c FB |
38 | target_ulong PFN[2]; |
39 | }; | |
6af0bf9c | 40 | |
3c7b48b7 | 41 | #if !defined(CONFIG_USER_ONLY) |
ead9360e TS |
42 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
43 | struct CPUMIPSTLBContext { | |
44 | uint32_t nb_tlb; | |
45 | uint32_t tlb_in_use; | |
a8170e5e | 46 | int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type); |
895c2d04 BS |
47 | void (*helper_tlbwi)(struct CPUMIPSState *env); |
48 | void (*helper_tlbwr)(struct CPUMIPSState *env); | |
49 | void (*helper_tlbp)(struct CPUMIPSState *env); | |
50 | void (*helper_tlbr)(struct CPUMIPSState *env); | |
9456c2fb LA |
51 | void (*helper_tlbinv)(struct CPUMIPSState *env); |
52 | void (*helper_tlbinvf)(struct CPUMIPSState *env); | |
ead9360e TS |
53 | union { |
54 | struct { | |
c227f099 | 55 | r4k_tlb_t tlb[MIPS_TLB_MAX]; |
ead9360e TS |
56 | } r4k; |
57 | } mmu; | |
58 | }; | |
3c7b48b7 | 59 | #endif |
51b2772f | 60 | |
c227f099 AL |
61 | typedef union fpr_t fpr_t; |
62 | union fpr_t { | |
ead9360e TS |
63 | float64 fd; /* ieee double precision */ |
64 | float32 fs[2];/* ieee single precision */ | |
65 | uint64_t d; /* binary double fixed-point */ | |
66 | uint32_t w[2]; /* binary single fixed-point */ | |
67 | }; | |
68 | /* define FP_ENDIAN_IDX to access the same location | |
4ff9786c | 69 | * in the fpr_t union regardless of the host endianness |
ead9360e | 70 | */ |
e2542fe2 | 71 | #if defined(HOST_WORDS_BIGENDIAN) |
ead9360e TS |
72 | # define FP_ENDIAN_IDX 1 |
73 | #else | |
74 | # define FP_ENDIAN_IDX 0 | |
c570fd16 | 75 | #endif |
ead9360e TS |
76 | |
77 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; | |
78 | struct CPUMIPSFPUContext { | |
6af0bf9c | 79 | /* Floating point registers */ |
c227f099 | 80 | fpr_t fpr[32]; |
6ea83fed | 81 | float_status fp_status; |
5a5012ec | 82 | /* fpu implementation/revision register (fir) */ |
6af0bf9c | 83 | uint32_t fcr0; |
b4dd99a3 | 84 | #define FCR0_UFRP 28 |
5a5012ec TS |
85 | #define FCR0_F64 22 |
86 | #define FCR0_L 21 | |
87 | #define FCR0_W 20 | |
88 | #define FCR0_3D 19 | |
89 | #define FCR0_PS 18 | |
90 | #define FCR0_D 17 | |
91 | #define FCR0_S 16 | |
92 | #define FCR0_PRID 8 | |
93 | #define FCR0_REV 0 | |
6ea83fed FB |
94 | /* fcsr */ |
95 | uint32_t fcr31; | |
f01be154 TS |
96 | #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
97 | #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) | |
98 | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) | |
5a5012ec TS |
99 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
100 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) | |
101 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) | |
102 | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) | |
103 | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) | |
104 | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) | |
105 | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) | |
6ea83fed FB |
106 | #define FP_INEXACT 1 |
107 | #define FP_UNDERFLOW 2 | |
108 | #define FP_OVERFLOW 4 | |
109 | #define FP_DIV0 8 | |
110 | #define FP_INVALID 16 | |
111 | #define FP_UNIMPLEMENTED 32 | |
ead9360e TS |
112 | }; |
113 | ||
623a930e | 114 | #define NB_MMU_MODES 3 |
6ebbf390 | 115 | |
ead9360e TS |
116 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
117 | struct CPUMIPSMVPContext { | |
118 | int32_t CP0_MVPControl; | |
119 | #define CP0MVPCo_CPA 3 | |
120 | #define CP0MVPCo_STLB 2 | |
121 | #define CP0MVPCo_VPC 1 | |
122 | #define CP0MVPCo_EVP 0 | |
123 | int32_t CP0_MVPConf0; | |
124 | #define CP0MVPC0_M 31 | |
125 | #define CP0MVPC0_TLBS 29 | |
126 | #define CP0MVPC0_GS 28 | |
127 | #define CP0MVPC0_PCP 27 | |
128 | #define CP0MVPC0_PTLBE 16 | |
129 | #define CP0MVPC0_TCA 15 | |
130 | #define CP0MVPC0_PVPE 10 | |
131 | #define CP0MVPC0_PTC 0 | |
132 | int32_t CP0_MVPConf1; | |
133 | #define CP0MVPC1_CIM 31 | |
134 | #define CP0MVPC1_CIF 30 | |
135 | #define CP0MVPC1_PCX 20 | |
136 | #define CP0MVPC1_PCP2 10 | |
137 | #define CP0MVPC1_PCP1 0 | |
138 | }; | |
139 | ||
c227f099 | 140 | typedef struct mips_def_t mips_def_t; |
ead9360e TS |
141 | |
142 | #define MIPS_SHADOW_SET_MAX 16 | |
143 | #define MIPS_TC_MAX 5 | |
f01be154 | 144 | #define MIPS_FPU_MAX 1 |
ead9360e | 145 | #define MIPS_DSP_ACC 4 |
e98c0d17 | 146 | #define MIPS_KSCRATCH_NUM 6 |
ead9360e | 147 | |
b5dc7732 TS |
148 | typedef struct TCState TCState; |
149 | struct TCState { | |
150 | target_ulong gpr[32]; | |
151 | target_ulong PC; | |
152 | target_ulong HI[MIPS_DSP_ACC]; | |
153 | target_ulong LO[MIPS_DSP_ACC]; | |
154 | target_ulong ACX[MIPS_DSP_ACC]; | |
155 | target_ulong DSPControl; | |
156 | int32_t CP0_TCStatus; | |
157 | #define CP0TCSt_TCU3 31 | |
158 | #define CP0TCSt_TCU2 30 | |
159 | #define CP0TCSt_TCU1 29 | |
160 | #define CP0TCSt_TCU0 28 | |
161 | #define CP0TCSt_TMX 27 | |
162 | #define CP0TCSt_RNST 23 | |
163 | #define CP0TCSt_TDS 21 | |
164 | #define CP0TCSt_DT 20 | |
165 | #define CP0TCSt_DA 15 | |
166 | #define CP0TCSt_A 13 | |
167 | #define CP0TCSt_TKSU 11 | |
168 | #define CP0TCSt_IXMT 10 | |
169 | #define CP0TCSt_TASID 0 | |
170 | int32_t CP0_TCBind; | |
171 | #define CP0TCBd_CurTC 21 | |
172 | #define CP0TCBd_TBE 17 | |
173 | #define CP0TCBd_CurVPE 0 | |
174 | target_ulong CP0_TCHalt; | |
175 | target_ulong CP0_TCContext; | |
176 | target_ulong CP0_TCSchedule; | |
177 | target_ulong CP0_TCScheFBack; | |
178 | int32_t CP0_Debug_tcstatus; | |
d279279e | 179 | target_ulong CP0_UserLocal; |
b5dc7732 TS |
180 | }; |
181 | ||
ead9360e TS |
182 | typedef struct CPUMIPSState CPUMIPSState; |
183 | struct CPUMIPSState { | |
b5dc7732 | 184 | TCState active_tc; |
f01be154 | 185 | CPUMIPSFPUContext active_fpu; |
b5dc7732 | 186 | |
ead9360e | 187 | uint32_t current_tc; |
f01be154 | 188 | uint32_t current_fpu; |
36d23958 | 189 | |
e034e2c3 | 190 | uint32_t SEGBITS; |
6d35524c | 191 | uint32_t PABITS; |
b6d96bed | 192 | target_ulong SEGMask; |
6d35524c | 193 | target_ulong PAMask; |
29929e34 | 194 | |
9c2149c8 | 195 | int32_t CP0_Index; |
ead9360e | 196 | /* CP0_MVP* are per MVP registers. */ |
9c2149c8 | 197 | int32_t CP0_Random; |
ead9360e TS |
198 | int32_t CP0_VPEControl; |
199 | #define CP0VPECo_YSI 21 | |
200 | #define CP0VPECo_GSI 20 | |
201 | #define CP0VPECo_EXCPT 16 | |
202 | #define CP0VPECo_TE 15 | |
203 | #define CP0VPECo_TargTC 0 | |
204 | int32_t CP0_VPEConf0; | |
205 | #define CP0VPEC0_M 31 | |
206 | #define CP0VPEC0_XTC 21 | |
207 | #define CP0VPEC0_TCS 19 | |
208 | #define CP0VPEC0_SCS 18 | |
209 | #define CP0VPEC0_DSC 17 | |
210 | #define CP0VPEC0_ICS 16 | |
211 | #define CP0VPEC0_MVP 1 | |
212 | #define CP0VPEC0_VPA 0 | |
213 | int32_t CP0_VPEConf1; | |
214 | #define CP0VPEC1_NCX 20 | |
215 | #define CP0VPEC1_NCP2 10 | |
216 | #define CP0VPEC1_NCP1 0 | |
217 | target_ulong CP0_YQMask; | |
218 | target_ulong CP0_VPESchedule; | |
219 | target_ulong CP0_VPEScheFBack; | |
220 | int32_t CP0_VPEOpt; | |
221 | #define CP0VPEOpt_IWX7 15 | |
222 | #define CP0VPEOpt_IWX6 14 | |
223 | #define CP0VPEOpt_IWX5 13 | |
224 | #define CP0VPEOpt_IWX4 12 | |
225 | #define CP0VPEOpt_IWX3 11 | |
226 | #define CP0VPEOpt_IWX2 10 | |
227 | #define CP0VPEOpt_IWX1 9 | |
228 | #define CP0VPEOpt_IWX0 8 | |
229 | #define CP0VPEOpt_DWX7 7 | |
230 | #define CP0VPEOpt_DWX6 6 | |
231 | #define CP0VPEOpt_DWX5 5 | |
232 | #define CP0VPEOpt_DWX4 4 | |
233 | #define CP0VPEOpt_DWX3 3 | |
234 | #define CP0VPEOpt_DWX2 2 | |
235 | #define CP0VPEOpt_DWX1 1 | |
236 | #define CP0VPEOpt_DWX0 0 | |
9c2149c8 TS |
237 | target_ulong CP0_EntryLo0; |
238 | target_ulong CP0_EntryLo1; | |
2fb58b73 LA |
239 | #if defined(TARGET_MIPS64) |
240 | # define CP0EnLo_RI 63 | |
241 | # define CP0EnLo_XI 62 | |
242 | #else | |
243 | # define CP0EnLo_RI 31 | |
244 | # define CP0EnLo_XI 30 | |
245 | #endif | |
9c2149c8 | 246 | target_ulong CP0_Context; |
e98c0d17 | 247 | target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; |
9c2149c8 | 248 | int32_t CP0_PageMask; |
7207c7f9 | 249 | int32_t CP0_PageGrain_rw_bitmask; |
9c2149c8 | 250 | int32_t CP0_PageGrain; |
7207c7f9 LA |
251 | #define CP0PG_RIE 31 |
252 | #define CP0PG_XIE 30 | |
92ceb440 | 253 | #define CP0PG_IEC 27 |
9c2149c8 | 254 | int32_t CP0_Wired; |
ead9360e TS |
255 | int32_t CP0_SRSConf0_rw_bitmask; |
256 | int32_t CP0_SRSConf0; | |
257 | #define CP0SRSC0_M 31 | |
258 | #define CP0SRSC0_SRS3 20 | |
259 | #define CP0SRSC0_SRS2 10 | |
260 | #define CP0SRSC0_SRS1 0 | |
261 | int32_t CP0_SRSConf1_rw_bitmask; | |
262 | int32_t CP0_SRSConf1; | |
263 | #define CP0SRSC1_M 31 | |
264 | #define CP0SRSC1_SRS6 20 | |
265 | #define CP0SRSC1_SRS5 10 | |
266 | #define CP0SRSC1_SRS4 0 | |
267 | int32_t CP0_SRSConf2_rw_bitmask; | |
268 | int32_t CP0_SRSConf2; | |
269 | #define CP0SRSC2_M 31 | |
270 | #define CP0SRSC2_SRS9 20 | |
271 | #define CP0SRSC2_SRS8 10 | |
272 | #define CP0SRSC2_SRS7 0 | |
273 | int32_t CP0_SRSConf3_rw_bitmask; | |
274 | int32_t CP0_SRSConf3; | |
275 | #define CP0SRSC3_M 31 | |
276 | #define CP0SRSC3_SRS12 20 | |
277 | #define CP0SRSC3_SRS11 10 | |
278 | #define CP0SRSC3_SRS10 0 | |
279 | int32_t CP0_SRSConf4_rw_bitmask; | |
280 | int32_t CP0_SRSConf4; | |
281 | #define CP0SRSC4_SRS15 20 | |
282 | #define CP0SRSC4_SRS14 10 | |
283 | #define CP0SRSC4_SRS13 0 | |
9c2149c8 | 284 | int32_t CP0_HWREna; |
c570fd16 | 285 | target_ulong CP0_BadVAddr; |
aea14095 LA |
286 | uint32_t CP0_BadInstr; |
287 | uint32_t CP0_BadInstrP; | |
9c2149c8 TS |
288 | int32_t CP0_Count; |
289 | target_ulong CP0_EntryHi; | |
9456c2fb | 290 | #define CP0EnHi_EHINV 10 |
9c2149c8 TS |
291 | int32_t CP0_Compare; |
292 | int32_t CP0_Status; | |
6af0bf9c FB |
293 | #define CP0St_CU3 31 |
294 | #define CP0St_CU2 30 | |
295 | #define CP0St_CU1 29 | |
296 | #define CP0St_CU0 28 | |
297 | #define CP0St_RP 27 | |
6ea83fed | 298 | #define CP0St_FR 26 |
6af0bf9c | 299 | #define CP0St_RE 25 |
7a387fff TS |
300 | #define CP0St_MX 24 |
301 | #define CP0St_PX 23 | |
6af0bf9c FB |
302 | #define CP0St_BEV 22 |
303 | #define CP0St_TS 21 | |
304 | #define CP0St_SR 20 | |
305 | #define CP0St_NMI 19 | |
306 | #define CP0St_IM 8 | |
7a387fff TS |
307 | #define CP0St_KX 7 |
308 | #define CP0St_SX 6 | |
309 | #define CP0St_UX 5 | |
623a930e | 310 | #define CP0St_KSU 3 |
6af0bf9c FB |
311 | #define CP0St_ERL 2 |
312 | #define CP0St_EXL 1 | |
313 | #define CP0St_IE 0 | |
9c2149c8 | 314 | int32_t CP0_IntCtl; |
ead9360e TS |
315 | #define CP0IntCtl_IPTI 29 |
316 | #define CP0IntCtl_IPPC1 26 | |
317 | #define CP0IntCtl_VS 5 | |
9c2149c8 | 318 | int32_t CP0_SRSCtl; |
ead9360e TS |
319 | #define CP0SRSCtl_HSS 26 |
320 | #define CP0SRSCtl_EICSS 18 | |
321 | #define CP0SRSCtl_ESS 12 | |
322 | #define CP0SRSCtl_PSS 6 | |
323 | #define CP0SRSCtl_CSS 0 | |
9c2149c8 | 324 | int32_t CP0_SRSMap; |
ead9360e TS |
325 | #define CP0SRSMap_SSV7 28 |
326 | #define CP0SRSMap_SSV6 24 | |
327 | #define CP0SRSMap_SSV5 20 | |
328 | #define CP0SRSMap_SSV4 16 | |
329 | #define CP0SRSMap_SSV3 12 | |
330 | #define CP0SRSMap_SSV2 8 | |
331 | #define CP0SRSMap_SSV1 4 | |
332 | #define CP0SRSMap_SSV0 0 | |
9c2149c8 | 333 | int32_t CP0_Cause; |
7a387fff TS |
334 | #define CP0Ca_BD 31 |
335 | #define CP0Ca_TI 30 | |
336 | #define CP0Ca_CE 28 | |
337 | #define CP0Ca_DC 27 | |
338 | #define CP0Ca_PCI 26 | |
6af0bf9c | 339 | #define CP0Ca_IV 23 |
7a387fff TS |
340 | #define CP0Ca_WP 22 |
341 | #define CP0Ca_IP 8 | |
4de9b249 | 342 | #define CP0Ca_IP_mask 0x0000FF00 |
7a387fff | 343 | #define CP0Ca_EC 2 |
c570fd16 | 344 | target_ulong CP0_EPC; |
9c2149c8 | 345 | int32_t CP0_PRid; |
b29a0341 | 346 | int32_t CP0_EBase; |
9c2149c8 | 347 | int32_t CP0_Config0; |
6af0bf9c FB |
348 | #define CP0C0_M 31 |
349 | #define CP0C0_K23 28 | |
350 | #define CP0C0_KU 25 | |
351 | #define CP0C0_MDU 20 | |
352 | #define CP0C0_MM 17 | |
353 | #define CP0C0_BM 16 | |
354 | #define CP0C0_BE 15 | |
355 | #define CP0C0_AT 13 | |
356 | #define CP0C0_AR 10 | |
357 | #define CP0C0_MT 7 | |
7a387fff | 358 | #define CP0C0_VI 3 |
6af0bf9c | 359 | #define CP0C0_K0 0 |
9c2149c8 | 360 | int32_t CP0_Config1; |
7a387fff | 361 | #define CP0C1_M 31 |
6af0bf9c FB |
362 | #define CP0C1_MMU 25 |
363 | #define CP0C1_IS 22 | |
364 | #define CP0C1_IL 19 | |
365 | #define CP0C1_IA 16 | |
366 | #define CP0C1_DS 13 | |
367 | #define CP0C1_DL 10 | |
368 | #define CP0C1_DA 7 | |
7a387fff TS |
369 | #define CP0C1_C2 6 |
370 | #define CP0C1_MD 5 | |
6af0bf9c FB |
371 | #define CP0C1_PC 4 |
372 | #define CP0C1_WR 3 | |
373 | #define CP0C1_CA 2 | |
374 | #define CP0C1_EP 1 | |
375 | #define CP0C1_FP 0 | |
9c2149c8 | 376 | int32_t CP0_Config2; |
7a387fff TS |
377 | #define CP0C2_M 31 |
378 | #define CP0C2_TU 28 | |
379 | #define CP0C2_TS 24 | |
380 | #define CP0C2_TL 20 | |
381 | #define CP0C2_TA 16 | |
382 | #define CP0C2_SU 12 | |
383 | #define CP0C2_SS 8 | |
384 | #define CP0C2_SL 4 | |
385 | #define CP0C2_SA 0 | |
9c2149c8 | 386 | int32_t CP0_Config3; |
7a387fff | 387 | #define CP0C3_M 31 |
aea14095 LA |
388 | #define CP0C3_BP 27 |
389 | #define CP0C3_BI 26 | |
bbfa8f72 | 390 | #define CP0C3_ISA_ON_EXC 16 |
d279279e | 391 | #define CP0C3_ULRI 13 |
7207c7f9 | 392 | #define CP0C3_RXI 12 |
7a387fff TS |
393 | #define CP0C3_DSPP 10 |
394 | #define CP0C3_LPA 7 | |
395 | #define CP0C3_VEIC 6 | |
396 | #define CP0C3_VInt 5 | |
397 | #define CP0C3_SP 4 | |
398 | #define CP0C3_MT 2 | |
399 | #define CP0C3_SM 1 | |
400 | #define CP0C3_TL 0 | |
b4160af1 PJ |
401 | uint32_t CP0_Config4; |
402 | uint32_t CP0_Config4_rw_bitmask; | |
403 | #define CP0C4_M 31 | |
9456c2fb | 404 | #define CP0C4_IE 29 |
e98c0d17 | 405 | #define CP0C4_KScrExist 16 |
b4dd99a3 PJ |
406 | uint32_t CP0_Config5; |
407 | uint32_t CP0_Config5_rw_bitmask; | |
408 | #define CP0C5_M 31 | |
409 | #define CP0C5_K 30 | |
410 | #define CP0C5_CV 29 | |
411 | #define CP0C5_EVA 28 | |
412 | #define CP0C5_MSAEn 27 | |
faf1f68b | 413 | #define CP0C5_SBRI 6 |
b4dd99a3 PJ |
414 | #define CP0C5_UFR 2 |
415 | #define CP0C5_NFExists 0 | |
e397ee33 TS |
416 | int32_t CP0_Config6; |
417 | int32_t CP0_Config7; | |
ead9360e | 418 | /* XXX: Maybe make LLAddr per-TC? */ |
5499b6ff | 419 | target_ulong lladdr; |
590bc601 PB |
420 | target_ulong llval; |
421 | target_ulong llnewval; | |
422 | target_ulong llreg; | |
2a6e32dd AJ |
423 | target_ulong CP0_LLAddr_rw_bitmask; |
424 | int CP0_LLAddr_shift; | |
fd88b6ab TS |
425 | target_ulong CP0_WatchLo[8]; |
426 | int32_t CP0_WatchHi[8]; | |
9c2149c8 TS |
427 | target_ulong CP0_XContext; |
428 | int32_t CP0_Framemask; | |
429 | int32_t CP0_Debug; | |
ead9360e | 430 | #define CP0DB_DBD 31 |
6af0bf9c FB |
431 | #define CP0DB_DM 30 |
432 | #define CP0DB_LSNM 28 | |
433 | #define CP0DB_Doze 27 | |
434 | #define CP0DB_Halt 26 | |
435 | #define CP0DB_CNT 25 | |
436 | #define CP0DB_IBEP 24 | |
437 | #define CP0DB_DBEP 21 | |
438 | #define CP0DB_IEXI 20 | |
439 | #define CP0DB_VER 15 | |
440 | #define CP0DB_DEC 10 | |
441 | #define CP0DB_SSt 8 | |
442 | #define CP0DB_DINT 5 | |
443 | #define CP0DB_DIB 4 | |
444 | #define CP0DB_DDBS 3 | |
445 | #define CP0DB_DDBL 2 | |
446 | #define CP0DB_DBp 1 | |
447 | #define CP0DB_DSS 0 | |
c570fd16 | 448 | target_ulong CP0_DEPC; |
9c2149c8 TS |
449 | int32_t CP0_Performance0; |
450 | int32_t CP0_TagLo; | |
451 | int32_t CP0_DataLo; | |
452 | int32_t CP0_TagHi; | |
453 | int32_t CP0_DataHi; | |
c570fd16 | 454 | target_ulong CP0_ErrorEPC; |
9c2149c8 | 455 | int32_t CP0_DESAVE; |
b5dc7732 TS |
456 | /* We waste some space so we can handle shadow registers like TCs. */ |
457 | TCState tcs[MIPS_SHADOW_SET_MAX]; | |
f01be154 | 458 | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
5cbdb3a3 | 459 | /* QEMU */ |
6af0bf9c | 460 | int error_code; |
aea14095 LA |
461 | #define EXCP_TLB_NOMATCH 0x1 |
462 | #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ | |
6af0bf9c FB |
463 | uint32_t hflags; /* CPU State */ |
464 | /* TMASK defines different execution modes */ | |
faf1f68b | 465 | #define MIPS_HFLAG_TMASK 0x5807FF |
79ef2c4c | 466 | #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
623a930e TS |
467 | /* The KSU flags must be the lowest bits in hflags. The flag order |
468 | must be the same as defined for CP0 Status. This allows to use | |
469 | the bits as the value of mmu_idx. */ | |
79ef2c4c NF |
470 | #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
471 | #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ | |
472 | #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ | |
473 | #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ | |
474 | #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ | |
475 | #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ | |
476 | #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ | |
477 | #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ | |
478 | #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ | |
b8aa4598 TS |
479 | /* True if the MIPS IV COP1X instructions can be used. This also |
480 | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S | |
481 | and RSQRT.D. */ | |
79ef2c4c NF |
482 | #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
483 | #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ | |
01f72885 | 484 | #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ |
79ef2c4c NF |
485 | #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
486 | #define MIPS_HFLAG_M16_SHIFT 10 | |
4ad40f36 FB |
487 | /* If translation is interrupted between the branch instruction and |
488 | * the delay slot, record what type of branch it is so that we can | |
489 | * resume translation properly. It might be possible to reduce | |
490 | * this from three bits to two. */ | |
79ef2c4c NF |
491 | #define MIPS_HFLAG_BMASK_BASE 0x03800 |
492 | #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ | |
493 | #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ | |
494 | #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ | |
495 | #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ | |
496 | /* Extra flags about the current pending branch. */ | |
b231c103 | 497 | #define MIPS_HFLAG_BMASK_EXT 0x7C000 |
79ef2c4c NF |
498 | #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
499 | #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ | |
500 | #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ | |
b231c103 YK |
501 | #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ |
502 | #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ | |
79ef2c4c | 503 | #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) |
853c3240 | 504 | /* MIPS DSP resources access. */ |
b231c103 YK |
505 | #define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */ |
506 | #define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */ | |
d279279e | 507 | /* Extra flag about HWREna register. */ |
b231c103 | 508 | #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ |
faf1f68b | 509 | #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ |
6af0bf9c | 510 | target_ulong btarget; /* Jump / branch target */ |
1ba74fb8 | 511 | target_ulong bcond; /* Branch condition (if needed) */ |
a316d335 | 512 | |
7a387fff TS |
513 | int SYNCI_Step; /* Address step size for SYNCI */ |
514 | int CCRes; /* Cycle count resolution/divisor */ | |
ead9360e TS |
515 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
516 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ | |
e189e748 | 517 | int insn_flags; /* Supported instruction set */ |
7a387fff | 518 | |
a316d335 | 519 | CPU_COMMON |
6ae81775 | 520 | |
f0c3c505 | 521 | /* Fields from here on are preserved across CPU reset. */ |
51cc2e78 | 522 | CPUMIPSMVPContext *mvp; |
3c7b48b7 | 523 | #if !defined(CONFIG_USER_ONLY) |
51cc2e78 | 524 | CPUMIPSTLBContext *tlb; |
3c7b48b7 | 525 | #endif |
51cc2e78 | 526 | |
c227f099 | 527 | const mips_def_t *cpu_model; |
33ac7f16 | 528 | void *irq[8]; |
1246b259 | 529 | QEMUTimer *timer; /* Internal timer */ |
6af0bf9c FB |
530 | }; |
531 | ||
0f71a709 AF |
532 | #include "cpu-qom.h" |
533 | ||
3c7b48b7 | 534 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 535 | int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 536 | target_ulong address, int rw, int access_type); |
a8170e5e | 537 | int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 538 | target_ulong address, int rw, int access_type); |
a8170e5e | 539 | int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 540 | target_ulong address, int rw, int access_type); |
895c2d04 BS |
541 | void r4k_helper_tlbwi(CPUMIPSState *env); |
542 | void r4k_helper_tlbwr(CPUMIPSState *env); | |
543 | void r4k_helper_tlbp(CPUMIPSState *env); | |
544 | void r4k_helper_tlbr(CPUMIPSState *env); | |
9456c2fb LA |
545 | void r4k_helper_tlbinv(CPUMIPSState *env); |
546 | void r4k_helper_tlbinvf(CPUMIPSState *env); | |
33d68b5f | 547 | |
c658b94f AF |
548 | void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
549 | bool is_write, bool is_exec, int unused, | |
550 | unsigned size); | |
3c7b48b7 PB |
551 | #endif |
552 | ||
9a78eead | 553 | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); |
647de6ca | 554 | |
9467d44c TS |
555 | #define cpu_exec cpu_mips_exec |
556 | #define cpu_gen_code cpu_mips_gen_code | |
557 | #define cpu_signal_handler cpu_mips_signal_handler | |
c732abe2 | 558 | #define cpu_list mips_cpu_list |
9467d44c | 559 | |
084d0497 RH |
560 | extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); |
561 | extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); | |
562 | ||
460c81f1 | 563 | #define CPU_SAVE_VERSION 5 |
b3c7724c | 564 | |
623a930e TS |
565 | /* MMU modes definitions. We carefully match the indices with our |
566 | hflags layout. */ | |
6ebbf390 | 567 | #define MMU_MODE0_SUFFIX _kernel |
623a930e TS |
568 | #define MMU_MODE1_SUFFIX _super |
569 | #define MMU_MODE2_SUFFIX _user | |
570 | #define MMU_USER_IDX 2 | |
7db13fae | 571 | static inline int cpu_mmu_index (CPUMIPSState *env) |
6ebbf390 | 572 | { |
623a930e | 573 | return env->hflags & MIPS_HFLAG_KSU; |
6ebbf390 JM |
574 | } |
575 | ||
7db13fae | 576 | static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) |
138afb02 EI |
577 | { |
578 | int32_t pending; | |
579 | int32_t status; | |
580 | int r; | |
581 | ||
4cdc1cd1 AJ |
582 | if (!(env->CP0_Status & (1 << CP0St_IE)) || |
583 | (env->CP0_Status & (1 << CP0St_EXL)) || | |
584 | (env->CP0_Status & (1 << CP0St_ERL)) || | |
344eecf6 EI |
585 | /* Note that the TCStatus IXMT field is initialized to zero, |
586 | and only MT capable cores can set it to one. So we don't | |
587 | need to check for MT capabilities here. */ | |
588 | (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) || | |
4cdc1cd1 AJ |
589 | (env->hflags & MIPS_HFLAG_DM)) { |
590 | /* Interrupts are disabled */ | |
591 | return 0; | |
592 | } | |
593 | ||
138afb02 EI |
594 | pending = env->CP0_Cause & CP0Ca_IP_mask; |
595 | status = env->CP0_Status & CP0Ca_IP_mask; | |
596 | ||
597 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { | |
598 | /* A MIPS configured with a vectorizing external interrupt controller | |
599 | will feed a vector into the Cause pending lines. The core treats | |
600 | the status lines as a vector level, not as indiviual masks. */ | |
601 | r = pending > status; | |
602 | } else { | |
603 | /* A MIPS configured with compatibility or VInt (Vectored Interrupts) | |
604 | treats the pending lines as individual interrupt lines, the status | |
605 | lines are individual masks. */ | |
606 | r = pending & status; | |
607 | } | |
608 | return r; | |
609 | } | |
610 | ||
022c62cb | 611 | #include "exec/cpu-all.h" |
6af0bf9c FB |
612 | |
613 | /* Memory access type : | |
614 | * may be needed for precise access rights control and precise exceptions. | |
615 | */ | |
616 | enum { | |
617 | /* 1 bit to define user level / supervisor access */ | |
618 | ACCESS_USER = 0x00, | |
619 | ACCESS_SUPER = 0x01, | |
620 | /* 1 bit to indicate direction */ | |
621 | ACCESS_STORE = 0x02, | |
622 | /* Type of instruction that generated the access */ | |
623 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
624 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
625 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
626 | }; | |
627 | ||
628 | /* Exceptions */ | |
629 | enum { | |
630 | EXCP_NONE = -1, | |
631 | EXCP_RESET = 0, | |
632 | EXCP_SRESET, | |
633 | EXCP_DSS, | |
634 | EXCP_DINT, | |
14e51cc7 TS |
635 | EXCP_DDBL, |
636 | EXCP_DDBS, | |
6af0bf9c FB |
637 | EXCP_NMI, |
638 | EXCP_MCHECK, | |
14e51cc7 | 639 | EXCP_EXT_INTERRUPT, /* 8 */ |
6af0bf9c | 640 | EXCP_DFWATCH, |
14e51cc7 | 641 | EXCP_DIB, |
6af0bf9c FB |
642 | EXCP_IWATCH, |
643 | EXCP_AdEL, | |
644 | EXCP_AdES, | |
645 | EXCP_TLBF, | |
646 | EXCP_IBE, | |
14e51cc7 | 647 | EXCP_DBp, /* 16 */ |
6af0bf9c | 648 | EXCP_SYSCALL, |
14e51cc7 | 649 | EXCP_BREAK, |
4ad40f36 | 650 | EXCP_CpU, |
6af0bf9c FB |
651 | EXCP_RI, |
652 | EXCP_OVERFLOW, | |
653 | EXCP_TRAP, | |
5a5012ec | 654 | EXCP_FPE, |
14e51cc7 | 655 | EXCP_DWATCH, /* 24 */ |
6af0bf9c FB |
656 | EXCP_LTLBL, |
657 | EXCP_TLBL, | |
658 | EXCP_TLBS, | |
659 | EXCP_DBE, | |
ead9360e | 660 | EXCP_THREAD, |
14e51cc7 TS |
661 | EXCP_MDMX, |
662 | EXCP_C2E, | |
663 | EXCP_CACHE, /* 32 */ | |
853c3240 | 664 | EXCP_DSPDIS, |
92ceb440 LA |
665 | EXCP_TLBXI, |
666 | EXCP_TLBRI, | |
14e51cc7 | 667 | |
92ceb440 | 668 | EXCP_LAST = EXCP_TLBRI, |
6af0bf9c | 669 | }; |
590bc601 PB |
670 | /* Dummy exception for conditional stores. */ |
671 | #define EXCP_SC 0x100 | |
6af0bf9c | 672 | |
f249412c EI |
673 | /* |
674 | * This is an interrnally generated WAKE request line. | |
675 | * It is driven by the CPU itself. Raised when the MT | |
676 | * block wants to wake a VPE from an inactive state and | |
677 | * cleared when VPE goes from active to inactive. | |
678 | */ | |
679 | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 | |
680 | ||
6af0bf9c | 681 | int cpu_mips_exec(CPUMIPSState *s); |
78ce64f4 | 682 | void mips_tcg_init(void); |
30bf942d | 683 | MIPSCPU *cpu_mips_init(const char *cpu_model); |
388bb21a | 684 | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
6af0bf9c | 685 | |
30bf942d AF |
686 | static inline CPUMIPSState *cpu_init(const char *cpu_model) |
687 | { | |
688 | MIPSCPU *cpu = cpu_mips_init(cpu_model); | |
689 | if (cpu == NULL) { | |
690 | return NULL; | |
691 | } | |
692 | return &cpu->env; | |
693 | } | |
694 | ||
b7e516ce AF |
695 | /* TODO QOM'ify CPU reset and remove */ |
696 | void cpu_state_reset(CPUMIPSState *s); | |
697 | ||
f9480ffc | 698 | /* mips_timer.c */ |
7db13fae AF |
699 | uint32_t cpu_mips_get_random (CPUMIPSState *env); |
700 | uint32_t cpu_mips_get_count (CPUMIPSState *env); | |
701 | void cpu_mips_store_count (CPUMIPSState *env, uint32_t value); | |
702 | void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value); | |
703 | void cpu_mips_start_count(CPUMIPSState *env); | |
704 | void cpu_mips_stop_count(CPUMIPSState *env); | |
f9480ffc | 705 | |
5dc5d9f0 | 706 | /* mips_int.c */ |
7db13fae | 707 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); |
5dc5d9f0 | 708 | |
f9480ffc | 709 | /* helper.c */ |
7510454e AF |
710 | int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, |
711 | int mmu_idx); | |
3c7b48b7 | 712 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 713 | void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); |
a8170e5e | 714 | hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, |
c36bbb28 | 715 | int rw); |
3c7b48b7 | 716 | #endif |
1239b472 | 717 | target_ulong exception_resume_pc (CPUMIPSState *env); |
f9480ffc | 718 | |
7db13fae | 719 | static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, |
6b917547 AL |
720 | target_ulong *cs_base, int *flags) |
721 | { | |
722 | *pc = env->active_tc.PC; | |
723 | *cs_base = 0; | |
d279279e PJ |
724 | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | |
725 | MIPS_HFLAG_HWRENA_ULR); | |
6b917547 AL |
726 | } |
727 | ||
7db13fae | 728 | static inline int mips_vpe_active(CPUMIPSState *env) |
f249412c EI |
729 | { |
730 | int active = 1; | |
731 | ||
732 | /* Check that the VPE is enabled. */ | |
733 | if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { | |
734 | active = 0; | |
735 | } | |
4abf79a4 | 736 | /* Check that the VPE is activated. */ |
f249412c EI |
737 | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { |
738 | active = 0; | |
739 | } | |
740 | ||
741 | /* Now verify that there are active thread contexts in the VPE. | |
742 | ||
743 | This assumes the CPU model will internally reschedule threads | |
744 | if the active one goes to sleep. If there are no threads available | |
745 | the active one will be in a sleeping state, and we can turn off | |
746 | the entire VPE. */ | |
747 | if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { | |
748 | /* TC is not activated. */ | |
749 | active = 0; | |
750 | } | |
751 | if (env->active_tc.CP0_TCHalt & 1) { | |
752 | /* TC is in halt state. */ | |
753 | active = 0; | |
754 | } | |
755 | ||
756 | return active; | |
757 | } | |
758 | ||
022c62cb | 759 | #include "exec/exec-all.h" |
f081c76c | 760 | |
03e6e501 MR |
761 | static inline void compute_hflags(CPUMIPSState *env) |
762 | { | |
763 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | | |
764 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | | |
faf1f68b LA |
765 | MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | |
766 | MIPS_HFLAG_SBRI); | |
03e6e501 MR |
767 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
768 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
769 | !(env->hflags & MIPS_HFLAG_DM)) { | |
770 | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; | |
771 | } | |
772 | #if defined(TARGET_MIPS64) | |
773 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || | |
774 | (env->CP0_Status & (1 << CP0St_PX)) || | |
775 | (env->CP0_Status & (1 << CP0St_UX))) { | |
776 | env->hflags |= MIPS_HFLAG_64; | |
777 | } | |
01f72885 LA |
778 | |
779 | if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && | |
780 | !(env->CP0_Status & (1 << CP0St_UX))) { | |
781 | env->hflags |= MIPS_HFLAG_AWRAP; | |
782 | } else if (env->insn_flags & ISA_MIPS32R6) { | |
783 | /* Address wrapping for Supervisor and Kernel is specified in R6 */ | |
784 | if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && | |
785 | !(env->CP0_Status & (1 << CP0St_SX))) || | |
786 | (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && | |
787 | !(env->CP0_Status & (1 << CP0St_KX)))) { | |
788 | env->hflags |= MIPS_HFLAG_AWRAP; | |
789 | } | |
03e6e501 MR |
790 | } |
791 | #endif | |
792 | if ((env->CP0_Status & (1 << CP0St_CU0)) || | |
793 | !(env->hflags & MIPS_HFLAG_KSU)) { | |
794 | env->hflags |= MIPS_HFLAG_CP0; | |
795 | } | |
796 | if (env->CP0_Status & (1 << CP0St_CU1)) { | |
797 | env->hflags |= MIPS_HFLAG_FPU; | |
798 | } | |
799 | if (env->CP0_Status & (1 << CP0St_FR)) { | |
800 | env->hflags |= MIPS_HFLAG_F64; | |
801 | } | |
faf1f68b LA |
802 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && |
803 | (env->CP0_Config5 & (1 << CP0C5_SBRI))) { | |
804 | env->hflags |= MIPS_HFLAG_SBRI; | |
805 | } | |
853c3240 JL |
806 | if (env->insn_flags & ASE_DSPR2) { |
807 | /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, | |
808 | so enable to access DSPR2 resources. */ | |
809 | if (env->CP0_Status & (1 << CP0St_MX)) { | |
810 | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; | |
811 | } | |
812 | ||
813 | } else if (env->insn_flags & ASE_DSP) { | |
814 | /* Enables access MIPS DSP resources, now our cpu is DSP ASE, | |
815 | so enable to access DSP resources. */ | |
816 | if (env->CP0_Status & (1 << CP0St_MX)) { | |
817 | env->hflags |= MIPS_HFLAG_DSP; | |
818 | } | |
819 | ||
820 | } | |
03e6e501 MR |
821 | if (env->insn_flags & ISA_MIPS32R2) { |
822 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { | |
823 | env->hflags |= MIPS_HFLAG_COP1X; | |
824 | } | |
825 | } else if (env->insn_flags & ISA_MIPS32) { | |
826 | if (env->hflags & MIPS_HFLAG_64) { | |
827 | env->hflags |= MIPS_HFLAG_COP1X; | |
828 | } | |
829 | } else if (env->insn_flags & ISA_MIPS4) { | |
830 | /* All supported MIPS IV CPUs use the XX (CU3) to enable | |
831 | and disable the MIPS IV extensions to the MIPS III ISA. | |
832 | Some other MIPS IV CPUs ignore the bit, so the check here | |
833 | would be too restrictive for them. */ | |
f45cb2f4 | 834 | if (env->CP0_Status & (1U << CP0St_CU3)) { |
03e6e501 MR |
835 | env->hflags |= MIPS_HFLAG_COP1X; |
836 | } | |
837 | } | |
838 | } | |
839 | ||
6af0bf9c | 840 | #endif /* !defined (__MIPS_CPU_H__) */ |