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Commit | Line | Data |
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6af0bf9c FB |
1 | #if !defined(__QEMU_MIPS_EXEC_H__) |
2 | #define __QEMU_MIPS_EXEC_H__ | |
3 | ||
01dbbdf1 | 4 | //#define DEBUG_OP |
6af0bf9c | 5 | |
c570fd16 | 6 | #include "config.h" |
6af0bf9c FB |
7 | #include "mips-defs.h" |
8 | #include "dyngen-exec.h" | |
01179c38 | 9 | #include "cpu-defs.h" |
6af0bf9c FB |
10 | |
11 | register struct CPUMIPSState *env asm(AREG0); | |
12 | ||
6af0bf9c FB |
13 | #include "cpu.h" |
14 | #include "exec-all.h" | |
15 | ||
16 | #if !defined(CONFIG_USER_ONLY) | |
a9049a07 | 17 | #include "softmmu_exec.h" |
6af0bf9c FB |
18 | #endif /* !defined(CONFIG_USER_ONLY) */ |
19 | ||
6ea83fed | 20 | void dump_fpu(CPUState *env); |
5fafdf24 | 21 | void fpu_dump_state(CPUState *env, FILE *f, |
6ea83fed FB |
22 | int (*fpu_fprintf)(FILE *f, const char *fmt, ...), |
23 | int flags); | |
6af0bf9c | 24 | |
6af0bf9c | 25 | void cpu_mips_clock_init (CPUState *env); |
814b9a47 | 26 | void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
6af0bf9c | 27 | |
c904ef0e | 28 | static inline void env_to_regs(void) |
bfed01fc TS |
29 | { |
30 | } | |
31 | ||
c904ef0e | 32 | static inline void regs_to_env(void) |
bfed01fc TS |
33 | { |
34 | } | |
35 | ||
6a4955a8 AL |
36 | static inline int cpu_has_work(CPUState *env) |
37 | { | |
38 | return (env->interrupt_request & | |
39 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)); | |
40 | } | |
41 | ||
42 | ||
c904ef0e | 43 | static inline int cpu_halted(CPUState *env) |
08fa4bab | 44 | { |
bfed01fc TS |
45 | if (!env->halted) |
46 | return 0; | |
6a4955a8 | 47 | if (cpu_has_work(env)) { |
bfed01fc TS |
48 | env->halted = 0; |
49 | return 0; | |
50 | } | |
51 | return EXCP_HALTED; | |
52 | } | |
53 | ||
c904ef0e | 54 | static inline void compute_hflags(CPUState *env) |
08fa4bab | 55 | { |
b8aa4598 | 56 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
2623c1ec AJ |
57 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
58 | MIPS_HFLAG_UX); | |
08fa4bab TS |
59 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
60 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
671880e6 | 61 | !(env->hflags & MIPS_HFLAG_DM)) { |
623a930e | 62 | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
671880e6 | 63 | } |
d26bc211 | 64 | #if defined(TARGET_MIPS64) |
623a930e | 65 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || |
08fa4bab TS |
66 | (env->CP0_Status & (1 << CP0St_PX)) || |
67 | (env->CP0_Status & (1 << CP0St_UX))) | |
68 | env->hflags |= MIPS_HFLAG_64; | |
2623c1ec AJ |
69 | if (env->CP0_Status & (1 << CP0St_UX)) |
70 | env->hflags |= MIPS_HFLAG_UX; | |
08fa4bab | 71 | #endif |
671880e6 | 72 | if ((env->CP0_Status & (1 << CP0St_CU0)) || |
623a930e | 73 | !(env->hflags & MIPS_HFLAG_KSU)) |
08fa4bab TS |
74 | env->hflags |= MIPS_HFLAG_CP0; |
75 | if (env->CP0_Status & (1 << CP0St_CU1)) | |
76 | env->hflags |= MIPS_HFLAG_FPU; | |
77 | if (env->CP0_Status & (1 << CP0St_FR)) | |
78 | env->hflags |= MIPS_HFLAG_F64; | |
b8aa4598 | 79 | if (env->insn_flags & ISA_MIPS32R2) { |
f01be154 | 80 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
b8aa4598 TS |
81 | env->hflags |= MIPS_HFLAG_COP1X; |
82 | } else if (env->insn_flags & ISA_MIPS32) { | |
83 | if (env->hflags & MIPS_HFLAG_64) | |
84 | env->hflags |= MIPS_HFLAG_COP1X; | |
85 | } else if (env->insn_flags & ISA_MIPS4) { | |
86 | /* All supported MIPS IV CPUs use the XX (CU3) to enable | |
87 | and disable the MIPS IV extensions to the MIPS III ISA. | |
88 | Some other MIPS IV CPUs ignore the bit, so the check here | |
89 | would be too restrictive for them. */ | |
90 | if (env->CP0_Status & (1 << CP0St_CU3)) | |
91 | env->hflags |= MIPS_HFLAG_COP1X; | |
92 | } | |
08fa4bab TS |
93 | } |
94 | ||
6af0bf9c | 95 | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |