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reset key modifiers when switching console (aka savevm keyboard bug)
[mirror_qemu.git] / target-mips / exec.h
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1#if !defined(__QEMU_MIPS_EXEC_H__)
2#define __QEMU_MIPS_EXEC_H__
3
01dbbdf1 4//#define DEBUG_OP
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5
6#include "mips-defs.h"
7#include "dyngen-exec.h"
8
9register struct CPUMIPSState *env asm(AREG0);
10
11#if defined (USE_64BITS_REGS)
12typedef int64_t host_int_t;
13typedef uint64_t host_uint_t;
14#else
15typedef int32_t host_int_t;
16typedef uint32_t host_uint_t;
17#endif
18
19register host_uint_t T0 asm(AREG1);
20register host_uint_t T1 asm(AREG2);
21register host_uint_t T2 asm(AREG3);
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22
23#if defined (USE_HOST_FLOAT_REGS)
6ea83fed 24#error "implement me."
6af0bf9c 25#else
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26#define FDT0 (env->ft0.fd)
27#define FDT1 (env->ft1.fd)
28#define FDT2 (env->ft2.fd)
29#define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
30#define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
31#define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
32#define DT0 (env->ft0.d)
33#define DT1 (env->ft1.d)
34#define DT2 (env->ft2.d)
35#define WT0 (env->ft0.w[FP_ENDIAN_IDX])
36#define WT1 (env->ft1.w[FP_ENDIAN_IDX])
37#define WT2 (env->ft2.w[FP_ENDIAN_IDX])
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38#endif
39
40#if defined (DEBUG_OP)
41#define RETURN() __asm__ __volatile__("nop");
42#else
43#define RETURN() __asm__ __volatile__("");
44#endif
45
46#include "cpu.h"
47#include "exec-all.h"
48
49#if !defined(CONFIG_USER_ONLY)
a9049a07 50#include "softmmu_exec.h"
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51#endif /* !defined(CONFIG_USER_ONLY) */
52
53static inline void env_to_regs(void)
54{
55}
56
57static inline void regs_to_env(void)
58{
59}
60
61#if (HOST_LONG_BITS == 32)
62void do_mult (void);
63void do_multu (void);
64void do_madd (void);
65void do_maddu (void);
66void do_msub (void);
67void do_msubu (void);
68#endif
6af0bf9c 69void do_mfc0(int reg, int sel);
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70void do_mtc0(int reg, int sel);
71void do_tlbwi (void);
72void do_tlbwr (void);
73void do_tlbp (void);
74void do_tlbr (void);
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75#ifdef MIPS_USES_FPU
76void dump_fpu(CPUState *env);
77void fpu_dump_state(CPUState *env, FILE *f,
78 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
79 int flags);
80#endif
81void dump_sc (void);
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82void do_lwl_raw (uint32_t);
83void do_lwr_raw (uint32_t);
84uint32_t do_swl_raw (uint32_t);
85uint32_t do_swr_raw (uint32_t);
6af0bf9c 86#if !defined(CONFIG_USER_ONLY)
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87void do_lwl_user (uint32_t);
88void do_lwl_kernel (uint32_t);
89void do_lwr_user (uint32_t);
90void do_lwr_kernel (uint32_t);
91uint32_t do_swl_user (uint32_t);
92uint32_t do_swl_kernel (uint32_t);
93uint32_t do_swr_user (uint32_t);
94uint32_t do_swr_kernel (uint32_t);
6af0bf9c 95#endif
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96void do_pmon (int function);
97
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98void dump_sc (void);
99
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100int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
101 int is_user, int is_softmmu);
102void do_interrupt (CPUState *env);
103
104void cpu_loop_exit(void);
6af0bf9c 105void do_raise_exception_err (uint32_t exception, int error_code);
6af0bf9c 106void do_raise_exception (uint32_t exception);
4ad40f36 107void do_raise_exception_direct (uint32_t exception);
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108
109void cpu_dump_state(CPUState *env, FILE *f,
110 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
111 int flags);
112void cpu_mips_irqctrl_init (void);
113uint32_t cpu_mips_get_random (CPUState *env);
114uint32_t cpu_mips_get_count (CPUState *env);
115void cpu_mips_store_count (CPUState *env, uint32_t value);
116void cpu_mips_store_compare (CPUState *env, uint32_t value);
117void cpu_mips_clock_init (CPUState *env);
118
119#endif /* !defined(__QEMU_MIPS_EXEC_H__) */