[mirror_qemu.git] / target-mips / exec.h

#if !defined(__QEMU_MIPS_EXEC_H__)
#define __QEMU_MIPS_EXEC_H__

//#define DEBUG_OP

#include "config.h"
#include "mips-defs.h"
#include "dyngen-exec.h"
#include "cpu-defs.h"

register struct CPUMIPSState *env asm(AREG0);

#if TARGET_LONG_BITS > HOST_LONG_BITS
#define T0 (env->t0)
#define T1 (env->t1)
#define T2 (env->t2)
#else
register target_ulong T0 asm(AREG1);
register target_ulong T1 asm(AREG2);
register target_ulong T2 asm(AREG3);
#endif

#if defined (USE_HOST_FLOAT_REGS)
#error "implement me."
#else
#define FDT0 (env->fpu->ft0.fd)
#define FDT1 (env->fpu->ft1.fd)
#define FDT2 (env->fpu->ft2.fd)
#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
#define DT0 (env->fpu->ft0.d)
#define DT1 (env->fpu->ft1.d)
#define DT2 (env->fpu->ft2.d)
#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
#endif

#include "cpu.h"
#include "exec-all.h"

#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */

#if defined(TARGET_MIPS64)
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_dsll (void);
void do_dsll32 (void);
void do_dsra (void);
void do_dsra32 (void);
void do_dsrl (void);
void do_dsrl32 (void);
void do_drotr (void);
void do_drotr32 (void);
void do_dsllv (void);
void do_dsrav (void);
void do_dsrlv (void);
void do_drotrv (void);
void do_dclo (void);
void do_dclz (void);
#endif
#endif

#if HOST_LONG_BITS < 64
void do_div (void);
#endif
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_mult (void);
void do_multu (void);
void do_madd (void);
void do_maddu (void);
void do_msub (void);
void do_msubu (void);
void do_muls (void);
void do_mulsu (void);
void do_macc (void);
void do_macchi (void);
void do_maccu (void);
void do_macchiu (void);
void do_msac (void);
void do_msachi (void);
void do_msacu (void);
void do_msachiu (void);
void do_mulhi (void);
void do_mulhiu (void);
void do_mulshi (void);
void do_mulshiu (void);
#endif
#if defined(TARGET_MIPS64)
void do_ddiv (void);
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_ddivu (void);
#endif
#endif
void do_mfc0_random(void);
void do_mfc0_count(void);
void do_mtc0_entryhi(uint32_t in);
void do_mtc0_status_debug(uint32_t old, uint32_t val);
void do_mtc0_status_irqraise_debug(void);
void dump_fpu(CPUState *env);
void fpu_dump_state(CPUState *env, FILE *f,
                    int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
                    int flags);
void dump_sc (void);
void do_pmon (int function);

void dump_sc (void);

int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu);
void do_interrupt (CPUState *env);
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);

void cpu_loop_exit(void);
void do_raise_exception_err (uint32_t exception, int error_code);
void do_raise_exception (uint32_t exception);
void do_raise_exception_direct_err (uint32_t exception, int error_code);
void do_raise_exception_direct (uint32_t exception);

void cpu_dump_state(CPUState *env, FILE *f,
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
                    int flags);
void cpu_mips_irqctrl_init (void);
uint32_t cpu_mips_get_random (CPUState *env);
uint32_t cpu_mips_get_count (CPUState *env);
void cpu_mips_store_count (CPUState *env, uint32_t value);
void cpu_mips_store_compare (CPUState *env, uint32_t value);
void cpu_mips_start_count(CPUState *env);
void cpu_mips_stop_count(CPUState *env);
void cpu_mips_update_irq (CPUState *env);
void cpu_mips_clock_init (CPUState *env);
void cpu_mips_tlb_flush (CPUState *env, int flush_global);

void do_cfc1 (int reg);
void do_ctc1 (int reg);

#define FOP_PROTO(op)              \
void do_float_ ## op ## _s(void);  \
void do_float_ ## op ## _d(void);
FOP_PROTO(roundl)
FOP_PROTO(roundw)
FOP_PROTO(truncl)
FOP_PROTO(truncw)
FOP_PROTO(ceill)
FOP_PROTO(ceilw)
FOP_PROTO(floorl)
FOP_PROTO(floorw)
FOP_PROTO(rsqrt)
FOP_PROTO(recip)
#undef FOP_PROTO

#define FOP_PROTO(op)              \
void do_float_ ## op ## _s(void);  \
void do_float_ ## op ## _d(void);  \
void do_float_ ## op ## _ps(void);
FOP_PROTO(add)
FOP_PROTO(sub)
FOP_PROTO(mul)
FOP_PROTO(div)
FOP_PROTO(recip1)
FOP_PROTO(recip2)
FOP_PROTO(rsqrt1)
FOP_PROTO(rsqrt2)
#undef FOP_PROTO

void do_float_cvtd_s(void);
void do_float_cvtd_w(void);
void do_float_cvtd_l(void);
void do_float_cvtl_d(void);
void do_float_cvtl_s(void);
void do_float_cvtps_pw(void);
void do_float_cvtpw_ps(void);
void do_float_cvts_d(void);
void do_float_cvts_w(void);
void do_float_cvts_l(void);
void do_float_cvts_pl(void);
void do_float_cvts_pu(void);
void do_float_cvtw_s(void);
void do_float_cvtw_d(void);

void do_float_addr_ps(void);
void do_float_mulr_ps(void);

#define FOP_PROTO(op)                      \
void do_cmp_d_ ## op(long cc);             \
void do_cmpabs_d_ ## op(long cc);          \
void do_cmp_s_ ## op(long cc);             \
void do_cmpabs_s_ ## op(long cc);          \
void do_cmp_ps_ ## op(long cc);            \
void do_cmpabs_ps_ ## op(long cc);

FOP_PROTO(f)
FOP_PROTO(un)
FOP_PROTO(eq)
FOP_PROTO(ueq)
FOP_PROTO(olt)
FOP_PROTO(ult)
FOP_PROTO(ole)
FOP_PROTO(ule)
FOP_PROTO(sf)
FOP_PROTO(ngle)
FOP_PROTO(seq)
FOP_PROTO(ngl)
FOP_PROTO(lt)
FOP_PROTO(nge)
FOP_PROTO(le)
FOP_PROTO(ngt)
#undef FOP_PROTO

static always_inline void env_to_regs(void)
{
}

static always_inline void regs_to_env(void)
{
}

static always_inline int cpu_halted(CPUState *env)
{
    if (!env->halted)
        return 0;
    if (env->interrupt_request &
        (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
        env->halted = 0;
        return 0;
    }
    return EXCP_HALTED;
}

static always_inline void compute_hflags(CPUState *env)
{
    env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
                     MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU);
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM)) {
        env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
    }
#if defined(TARGET_MIPS64)
    if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
        (env->CP0_Status & (1 << CP0St_PX)) ||
        (env->CP0_Status & (1 << CP0St_UX)))
        env->hflags |= MIPS_HFLAG_64;
#endif
    if ((env->CP0_Status & (1 << CP0St_CU0)) ||
        !(env->hflags & MIPS_HFLAG_KSU))
        env->hflags |= MIPS_HFLAG_CP0;
    if (env->CP0_Status & (1 << CP0St_CU1))
        env->hflags |= MIPS_HFLAG_FPU;
    if (env->CP0_Status & (1 << CP0St_FR))
        env->hflags |= MIPS_HFLAG_F64;
    if (env->insn_flags & ISA_MIPS32R2) {
        if (env->fpu->fcr0 & (1 << FCR0_F64))
            env->hflags |= MIPS_HFLAG_COP1X;
    } else if (env->insn_flags & ISA_MIPS32) {
        if (env->hflags & MIPS_HFLAG_64)
            env->hflags |= MIPS_HFLAG_COP1X;
    } else if (env->insn_flags & ISA_MIPS4) {
        /* All supported MIPS IV CPUs use the XX (CU3) to enable
           and disable the MIPS IV extensions to the MIPS III ISA.
           Some other MIPS IV CPUs ignore the bit, so the check here
           would be too restrictive for them.  */
        if (env->CP0_Status & (1 << CP0St_CU3))
            env->hflags |= MIPS_HFLAG_COP1X;
    }
}

#endif /* !defined(__QEMU_MIPS_EXEC_H__) */
Commit	Line	Data
6af0bf9c FB	1	#if !defined(__QEMU_MIPS_EXEC_H__)
	2	#define __QEMU_MIPS_EXEC_H__
	3
01dbbdf1	4	//#define DEBUG_OP
6af0bf9c	5
c570fd16	6	#include "config.h"
6af0bf9c FB	7	#include "mips-defs.h"
6af0bf9c FB	8	#include "dyngen-exec.h"
01179c38	9	#include "cpu-defs.h"
6af0bf9c FB	10
	11	register struct CPUMIPSState *env asm(AREG0);
	12
c570fd16 TS	13	#if TARGET_LONG_BITS > HOST_LONG_BITS
	14	#define T0 (env->t0)
	15	#define T1 (env->t1)
	16	#define T2 (env->t2)
	17	#else
01179c38 TS	18	register target_ulong T0 asm(AREG1);
	19	register target_ulong T1 asm(AREG2);
	20	register target_ulong T2 asm(AREG3);
c570fd16	21	#endif
6af0bf9c FB	22
6af0bf9c FB	23	#if defined (USE_HOST_FLOAT_REGS)
6ea83fed	24	#error "implement me."
6af0bf9c	25	#else
ead9360e TS	26	#define FDT0 (env->fpu->ft0.fd)
	27	#define FDT1 (env->fpu->ft1.fd)
	28	#define FDT2 (env->fpu->ft2.fd)
	29	#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
	30	#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
	31	#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
	32	#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
	33	#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
	34	#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
	35	#define DT0 (env->fpu->ft0.d)
	36	#define DT1 (env->fpu->ft1.d)
	37	#define DT2 (env->fpu->ft2.d)
	38	#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
	39	#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
	40	#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
	41	#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
	42	#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
	43	#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
6af0bf9c FB	44	#endif
6af0bf9c FB	45
6af0bf9c FB	46	#include "cpu.h"
	47	#include "exec-all.h"
	48
	49	#if !defined(CONFIG_USER_ONLY)
a9049a07	50	#include "softmmu_exec.h"
6af0bf9c FB	51	#endif /* !defined(CONFIG_USER_ONLY) */
6af0bf9c FB	52
d26bc211	53	#if defined(TARGET_MIPS64)
c570fd16 TS	54	#if TARGET_LONG_BITS > HOST_LONG_BITS
	55	void do_dsll (void);
	56	void do_dsll32 (void);
	57	void do_dsra (void);
	58	void do_dsra32 (void);
	59	void do_dsrl (void);
	60	void do_dsrl32 (void);
	61	void do_drotr (void);
	62	void do_drotr32 (void);
	63	void do_dsllv (void);
	64	void do_dsrav (void);
	65	void do_dsrlv (void);
	66	void do_drotrv (void);
05f778c8 TS	67	void do_dclo (void);
05f778c8 TS	68	void do_dclz (void);
c570fd16 TS	69	#endif
	70	#endif
	71
80c27194 TS	72	#if HOST_LONG_BITS < 64
	73	void do_div (void);
	74	#endif
c570fd16	75	#if TARGET_LONG_BITS > HOST_LONG_BITS
6af0bf9c FB	76	void do_mult (void);
	77	void do_multu (void);
	78	void do_madd (void);
	79	void do_maddu (void);
	80	void do_msub (void);
	81	void do_msubu (void);
e9c71dd1 TS	82	void do_muls (void);
	83	void do_mulsu (void);
	84	void do_macc (void);
	85	void do_macchi (void);
	86	void do_maccu (void);
	87	void do_macchiu (void);
	88	void do_msac (void);
	89	void do_msachi (void);
	90	void do_msacu (void);
	91	void do_msachiu (void);
	92	void do_mulhi (void);
	93	void do_mulhiu (void);
	94	void do_mulshi (void);
	95	void do_mulshiu (void);
80c27194	96	#endif
d26bc211	97	#if defined(TARGET_MIPS64)
c570fd16	98	void do_ddiv (void);
80c27194	99	#if TARGET_LONG_BITS > HOST_LONG_BITS
c570fd16 TS	100	void do_ddivu (void);
c570fd16 TS	101	#endif
6af0bf9c	102	#endif
873eb012 TS	103	void do_mfc0_random(void);
873eb012 TS	104	void do_mfc0_count(void);
7a387fff	105	void do_mtc0_entryhi(uint32_t in);
8c0fdd85 TS	106	void do_mtc0_status_debug(uint32_t old, uint32_t val);
8c0fdd85 TS	107	void do_mtc0_status_irqraise_debug(void);
6ea83fed	108	void dump_fpu(CPUState *env);
5fafdf24	109	void fpu_dump_state(CPUState env, FILE f,
6ea83fed FB	110	int (fpu_fprintf)(FILE f, const char *fmt, ...),
6ea83fed FB	111	int flags);
6ea83fed	112	void dump_sc (void);
6af0bf9c FB	113	void do_pmon (int function);
6af0bf9c FB	114
d2ec1774 PB	115	void dump_sc (void);
d2ec1774 PB	116
6af0bf9c	117	int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390	118	int mmu_idx, int is_softmmu);
6af0bf9c	119	void do_interrupt (CPUState *env);
29929e34	120	void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
6af0bf9c FB	121
6af0bf9c FB	122	void cpu_loop_exit(void);
6af0bf9c	123	void do_raise_exception_err (uint32_t exception, int error_code);
6af0bf9c	124	void do_raise_exception (uint32_t exception);
e397ee33	125	void do_raise_exception_direct_err (uint32_t exception, int error_code);
4ad40f36	126	void do_raise_exception_direct (uint32_t exception);
6af0bf9c	127
5fafdf24	128	void cpu_dump_state(CPUState env, FILE f,
6af0bf9c FB	129	int (cpu_fprintf)(FILE f, const char *fmt, ...),
	130	int flags);
	131	void cpu_mips_irqctrl_init (void);
	132	uint32_t cpu_mips_get_random (CPUState *env);
	133	uint32_t cpu_mips_get_count (CPUState *env);
	134	void cpu_mips_store_count (CPUState *env, uint32_t value);
	135	void cpu_mips_store_compare (CPUState *env, uint32_t value);
42532189 TS	136	void cpu_mips_start_count(CPUState *env);
42532189 TS	137	void cpu_mips_stop_count(CPUState *env);
a4bc3afc	138	void cpu_mips_update_irq (CPUState *env);
6af0bf9c	139	void cpu_mips_clock_init (CPUState *env);
814b9a47	140	void cpu_mips_tlb_flush (CPUState *env, int flush_global);
6af0bf9c	141
ead9360e TS	142	void do_cfc1 (int reg);
ead9360e TS	143	void do_ctc1 (int reg);
57fa1fb3 TS	144
	145	#define FOP_PROTO(op) \
	146	void do_float_ ## op ## _s(void); \
	147	void do_float_ ## op ## _d(void);
	148	FOP_PROTO(roundl)
	149	FOP_PROTO(roundw)
	150	FOP_PROTO(truncl)
	151	FOP_PROTO(truncw)
	152	FOP_PROTO(ceill)
	153	FOP_PROTO(ceilw)
	154	FOP_PROTO(floorl)
	155	FOP_PROTO(floorw)
	156	FOP_PROTO(rsqrt)
	157	FOP_PROTO(recip)
	158	#undef FOP_PROTO
	159
	160	#define FOP_PROTO(op) \
	161	void do_float_ ## op ## _s(void); \
	162	void do_float_ ## op ## _d(void); \
	163	void do_float_ ## op ## _ps(void);
	164	FOP_PROTO(add)
	165	FOP_PROTO(sub)
	166	FOP_PROTO(mul)
	167	FOP_PROTO(div)
	168	FOP_PROTO(recip1)
	169	FOP_PROTO(recip2)
	170	FOP_PROTO(rsqrt1)
	171	FOP_PROTO(rsqrt2)
	172	#undef FOP_PROTO
	173
fd4a04eb TS	174	void do_float_cvtd_s(void);
	175	void do_float_cvtd_w(void);
	176	void do_float_cvtd_l(void);
	177	void do_float_cvtl_d(void);
	178	void do_float_cvtl_s(void);
	179	void do_float_cvtps_pw(void);
	180	void do_float_cvtpw_ps(void);
	181	void do_float_cvts_d(void);
	182	void do_float_cvts_w(void);
	183	void do_float_cvts_l(void);
	184	void do_float_cvts_pl(void);
	185	void do_float_cvts_pu(void);
	186	void do_float_cvtw_s(void);
	187	void do_float_cvtw_d(void);
57fa1fb3	188
fd4a04eb	189	void do_float_addr_ps(void);
57fa1fb3	190	void do_float_mulr_ps(void);
fd4a04eb	191
57fa1fb3	192	#define FOP_PROTO(op) \
fd4a04eb TS	193	void do_cmp_d_ ## op(long cc); \
	194	void do_cmpabs_d_ ## op(long cc); \
	195	void do_cmp_s_ ## op(long cc); \
	196	void do_cmpabs_s_ ## op(long cc); \
	197	void do_cmp_ps_ ## op(long cc); \
	198	void do_cmpabs_ps_ ## op(long cc);
	199
57fa1fb3 TS	200	FOP_PROTO(f)
	201	FOP_PROTO(un)
	202	FOP_PROTO(eq)
	203	FOP_PROTO(ueq)
	204	FOP_PROTO(olt)
	205	FOP_PROTO(ult)
	206	FOP_PROTO(ole)
	207	FOP_PROTO(ule)
	208	FOP_PROTO(sf)
	209	FOP_PROTO(ngle)
	210	FOP_PROTO(seq)
	211	FOP_PROTO(ngl)
	212	FOP_PROTO(lt)
	213	FOP_PROTO(nge)
	214	FOP_PROTO(le)
	215	FOP_PROTO(ngt)
	216	#undef FOP_PROTO
fd4a04eb	217
aa343735	218	static always_inline void env_to_regs(void)
bfed01fc TS	219	{
	220	}
	221
aa343735	222	static always_inline void regs_to_env(void)
bfed01fc TS	223	{
	224	}
	225
aa343735	226	static always_inline int cpu_halted(CPUState *env)
08fa4bab	227	{
bfed01fc TS	228	if (!env->halted)
	229	return 0;
	230	if (env->interrupt_request &
	231	(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_TIMER)) {
	232	env->halted = 0;
	233	return 0;
	234	}
	235	return EXCP_HALTED;
	236	}
	237
aa343735	238	static always_inline void compute_hflags(CPUState *env)
08fa4bab	239	{
b8aa4598 TS	240	env->hflags &= ~(MIPS_HFLAG_COP1X \| MIPS_HFLAG_64 \| MIPS_HFLAG_CP0 \|
b8aa4598 TS	241	MIPS_HFLAG_F64 \| MIPS_HFLAG_FPU \| MIPS_HFLAG_KSU);
08fa4bab TS	242	if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
08fa4bab TS	243	!(env->CP0_Status & (1 << CP0St_ERL)) &&
671880e6	244	!(env->hflags & MIPS_HFLAG_DM)) {
623a930e	245	env->hflags \|= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
671880e6	246	}
d26bc211	247	#if defined(TARGET_MIPS64)
623a930e	248	if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) \|\|
08fa4bab TS	249	(env->CP0_Status & (1 << CP0St_PX)) \|\|
	250	(env->CP0_Status & (1 << CP0St_UX)))
	251	env->hflags \|= MIPS_HFLAG_64;
	252	#endif
671880e6	253	if ((env->CP0_Status & (1 << CP0St_CU0)) \|\|
623a930e	254	!(env->hflags & MIPS_HFLAG_KSU))
08fa4bab TS	255	env->hflags \|= MIPS_HFLAG_CP0;
	256	if (env->CP0_Status & (1 << CP0St_CU1))
	257	env->hflags \|= MIPS_HFLAG_FPU;
	258	if (env->CP0_Status & (1 << CP0St_FR))
	259	env->hflags \|= MIPS_HFLAG_F64;
b8aa4598	260	if (env->insn_flags & ISA_MIPS32R2) {
a139a3ad	261	if (env->fpu->fcr0 & (1 << FCR0_F64))
b8aa4598 TS	262	env->hflags \|= MIPS_HFLAG_COP1X;
	263	} else if (env->insn_flags & ISA_MIPS32) {
	264	if (env->hflags & MIPS_HFLAG_64)
	265	env->hflags \|= MIPS_HFLAG_COP1X;
	266	} else if (env->insn_flags & ISA_MIPS4) {
	267	/* All supported MIPS IV CPUs use the XX (CU3) to enable
	268	and disable the MIPS IV extensions to the MIPS III ISA.
	269	Some other MIPS IV CPUs ignore the bit, so the check here
	270	would be too restrictive for them. */
	271	if (env->CP0_Status & (1 << CP0St_CU3))
	272	env->hflags \|= MIPS_HFLAG_COP1X;
	273	}
08fa4bab TS	274	}
08fa4bab TS	275
6af0bf9c	276	#endif /* !defined(__QEMU_MIPS_EXEC_H__) */