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6af0bf9c FB |
1 | #if !defined(__QEMU_MIPS_EXEC_H__) |
2 | #define __QEMU_MIPS_EXEC_H__ | |
3 | ||
01dbbdf1 | 4 | //#define DEBUG_OP |
6af0bf9c FB |
5 | |
6 | #include "mips-defs.h" | |
7 | #include "dyngen-exec.h" | |
8 | ||
9 | register struct CPUMIPSState *env asm(AREG0); | |
10 | ||
11 | #if defined (USE_64BITS_REGS) | |
12 | typedef int64_t host_int_t; | |
13 | typedef uint64_t host_uint_t; | |
14 | #else | |
15 | typedef int32_t host_int_t; | |
16 | typedef uint32_t host_uint_t; | |
17 | #endif | |
18 | ||
19 | register host_uint_t T0 asm(AREG1); | |
20 | register host_uint_t T1 asm(AREG2); | |
21 | register host_uint_t T2 asm(AREG3); | |
6af0bf9c FB |
22 | |
23 | #if defined (USE_HOST_FLOAT_REGS) | |
24 | register double FT0 asm(FREG0); | |
25 | register double FT1 asm(FREG1); | |
26 | register double FT2 asm(FREG2); | |
6af0bf9c FB |
27 | #else |
28 | #define FT0 (env->ft0.d) | |
29 | #define FT1 (env->ft1.d) | |
30 | #define FT2 (env->ft2.d) | |
6af0bf9c FB |
31 | #endif |
32 | ||
33 | #if defined (DEBUG_OP) | |
34 | #define RETURN() __asm__ __volatile__("nop"); | |
35 | #else | |
36 | #define RETURN() __asm__ __volatile__(""); | |
37 | #endif | |
38 | ||
39 | #include "cpu.h" | |
40 | #include "exec-all.h" | |
41 | ||
42 | #if !defined(CONFIG_USER_ONLY) | |
a9049a07 | 43 | #include "softmmu_exec.h" |
6af0bf9c FB |
44 | #endif /* !defined(CONFIG_USER_ONLY) */ |
45 | ||
46 | static inline void env_to_regs(void) | |
47 | { | |
48 | } | |
49 | ||
50 | static inline void regs_to_env(void) | |
51 | { | |
52 | } | |
53 | ||
54 | #if (HOST_LONG_BITS == 32) | |
55 | void do_mult (void); | |
56 | void do_multu (void); | |
57 | void do_madd (void); | |
58 | void do_maddu (void); | |
59 | void do_msub (void); | |
60 | void do_msubu (void); | |
61 | #endif | |
6af0bf9c | 62 | void do_mfc0(int reg, int sel); |
6af0bf9c FB |
63 | void do_mtc0(int reg, int sel); |
64 | void do_tlbwi (void); | |
65 | void do_tlbwr (void); | |
66 | void do_tlbp (void); | |
67 | void do_tlbr (void); | |
4ad40f36 FB |
68 | void do_lwl_raw (uint32_t); |
69 | void do_lwr_raw (uint32_t); | |
70 | uint32_t do_swl_raw (uint32_t); | |
71 | uint32_t do_swr_raw (uint32_t); | |
6af0bf9c | 72 | #if !defined(CONFIG_USER_ONLY) |
4ad40f36 FB |
73 | void do_lwl_user (uint32_t); |
74 | void do_lwl_kernel (uint32_t); | |
75 | void do_lwr_user (uint32_t); | |
76 | void do_lwr_kernel (uint32_t); | |
77 | uint32_t do_swl_user (uint32_t); | |
78 | uint32_t do_swl_kernel (uint32_t); | |
79 | uint32_t do_swr_user (uint32_t); | |
80 | uint32_t do_swr_kernel (uint32_t); | |
6af0bf9c | 81 | #endif |
6af0bf9c FB |
82 | void do_pmon (int function); |
83 | ||
d2ec1774 PB |
84 | void dump_sc (void); |
85 | ||
6af0bf9c FB |
86 | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
87 | int is_user, int is_softmmu); | |
88 | void do_interrupt (CPUState *env); | |
89 | ||
90 | void cpu_loop_exit(void); | |
6af0bf9c | 91 | void do_raise_exception_err (uint32_t exception, int error_code); |
6af0bf9c | 92 | void do_raise_exception (uint32_t exception); |
4ad40f36 | 93 | void do_raise_exception_direct (uint32_t exception); |
6af0bf9c FB |
94 | |
95 | void cpu_dump_state(CPUState *env, FILE *f, | |
96 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
97 | int flags); | |
98 | void cpu_mips_irqctrl_init (void); | |
99 | uint32_t cpu_mips_get_random (CPUState *env); | |
100 | uint32_t cpu_mips_get_count (CPUState *env); | |
101 | void cpu_mips_store_count (CPUState *env, uint32_t value); | |
102 | void cpu_mips_store_compare (CPUState *env, uint32_t value); | |
103 | void cpu_mips_clock_init (CPUState *env); | |
104 | ||
105 | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |