[mirror_qemu.git] / target-mips / exec.h

#if !defined(__QEMU_MIPS_EXEC_H__)
#define __QEMU_MIPS_EXEC_H__

//#define DEBUG_OP

#include "config.h"
#include "mips-defs.h"
#include "dyngen-exec.h"
#include "cpu-defs.h"

register struct CPUMIPSState *env asm(AREG0);

#if TARGET_LONG_BITS > HOST_LONG_BITS
#define T0 (env->t0)
#define T1 (env->t1)
#define T2 (env->t2)
#else
register target_ulong T0 asm(AREG1);
register target_ulong T1 asm(AREG2);
register target_ulong T2 asm(AREG3);
#endif

#if defined (USE_HOST_FLOAT_REGS)
#error "implement me."
#else
#define FDT0 (env->fpu->ft0.fd)
#define FDT1 (env->fpu->ft1.fd)
#define FDT2 (env->fpu->ft2.fd)
#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
#define DT0 (env->fpu->ft0.d)
#define DT1 (env->fpu->ft1.d)
#define DT2 (env->fpu->ft2.d)
#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
#endif

#if defined (DEBUG_OP)
# define RETURN() __asm__ __volatile__("nop" : : : "memory");
#else
# define RETURN() __asm__ __volatile__("" : : : "memory");
#endif

#include "cpu.h"
#include "exec-all.h"

#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */

#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_dsll (void);
void do_dsll32 (void);
void do_dsra (void);
void do_dsra32 (void);
void do_dsrl (void);
void do_dsrl32 (void);
void do_drotr (void);
void do_drotr32 (void);
void do_dsllv (void);
void do_dsrav (void);
void do_dsrlv (void);
void do_drotrv (void);
#endif
#endif

#if HOST_LONG_BITS < 64
void do_div (void);
#endif
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_mult (void);
void do_multu (void);
void do_madd (void);
void do_maddu (void);
void do_msub (void);
void do_msubu (void);
#endif
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
void do_ddiv (void);
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_ddivu (void);
#endif
#endif
void do_mfc0_random(void);
void do_mfc0_count(void);
void do_mtc0_entryhi(uint32_t in);
void do_mtc0_status_debug(uint32_t old, uint32_t val);
void do_mtc0_status_irqraise_debug(void);
void dump_fpu(CPUState *env);
void fpu_dump_state(CPUState *env, FILE *f,
                    int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
                    int flags);
void dump_sc (void);
void do_pmon (int function);

void dump_sc (void);

int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu);
void do_interrupt (CPUState *env);
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);

void cpu_loop_exit(void);
void do_raise_exception_err (uint32_t exception, int error_code);
void do_raise_exception (uint32_t exception);
void do_raise_exception_direct_err (uint32_t exception, int error_code);
void do_raise_exception_direct (uint32_t exception);

void cpu_dump_state(CPUState *env, FILE *f,
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
                    int flags);
void cpu_mips_irqctrl_init (void);
uint32_t cpu_mips_get_random (CPUState *env);
uint32_t cpu_mips_get_count (CPUState *env);
void cpu_mips_store_count (CPUState *env, uint32_t value);
void cpu_mips_store_compare (CPUState *env, uint32_t value);
void cpu_mips_start_count(CPUState *env);
void cpu_mips_stop_count(CPUState *env);
void cpu_mips_update_irq (CPUState *env);
void cpu_mips_clock_init (CPUState *env);
void cpu_mips_tlb_flush (CPUState *env, int flush_global);

void do_cfc1 (int reg);
void do_ctc1 (int reg);

#define FOP_PROTO(op)              \
void do_float_ ## op ## _s(void);  \
void do_float_ ## op ## _d(void);
FOP_PROTO(roundl)
FOP_PROTO(roundw)
FOP_PROTO(truncl)
FOP_PROTO(truncw)
FOP_PROTO(ceill)
FOP_PROTO(ceilw)
FOP_PROTO(floorl)
FOP_PROTO(floorw)
FOP_PROTO(rsqrt)
FOP_PROTO(recip)
#undef FOP_PROTO

#define FOP_PROTO(op)              \
void do_float_ ## op ## _s(void);  \
void do_float_ ## op ## _d(void);  \
void do_float_ ## op ## _ps(void);
FOP_PROTO(add)
FOP_PROTO(sub)
FOP_PROTO(mul)
FOP_PROTO(div)
FOP_PROTO(recip1)
FOP_PROTO(recip2)
FOP_PROTO(rsqrt1)
FOP_PROTO(rsqrt2)
#undef FOP_PROTO

void do_float_cvtd_s(void);
void do_float_cvtd_w(void);
void do_float_cvtd_l(void);
void do_float_cvtl_d(void);
void do_float_cvtl_s(void);
void do_float_cvtps_pw(void);
void do_float_cvtpw_ps(void);
void do_float_cvts_d(void);
void do_float_cvts_w(void);
void do_float_cvts_l(void);
void do_float_cvts_pl(void);
void do_float_cvts_pu(void);
void do_float_cvtw_s(void);
void do_float_cvtw_d(void);

void do_float_addr_ps(void);
void do_float_mulr_ps(void);

#define FOP_PROTO(op)                      \
void do_cmp_d_ ## op(long cc);             \
void do_cmpabs_d_ ## op(long cc);          \
void do_cmp_s_ ## op(long cc);             \
void do_cmpabs_s_ ## op(long cc);          \
void do_cmp_ps_ ## op(long cc);            \
void do_cmpabs_ps_ ## op(long cc);

FOP_PROTO(f)
FOP_PROTO(un)
FOP_PROTO(eq)
FOP_PROTO(ueq)
FOP_PROTO(olt)
FOP_PROTO(ult)
FOP_PROTO(ole)
FOP_PROTO(ule)
FOP_PROTO(sf)
FOP_PROTO(ngle)
FOP_PROTO(seq)
FOP_PROTO(ngl)
FOP_PROTO(lt)
FOP_PROTO(nge)
FOP_PROTO(le)
FOP_PROTO(ngt)
#undef FOP_PROTO

static always_inline void env_to_regs(void)
{
}

static always_inline void regs_to_env(void)
{
}

static always_inline int cpu_halted(CPUState *env)
{
    if (!env->halted)
        return 0;
    if (env->interrupt_request &
        (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
        env->halted = 0;
        return 0;
    }
    return EXCP_HALTED;
}

static always_inline void compute_hflags(CPUState *env)
{
    env->hflags &= ~(MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | MIPS_HFLAG_F64 |
                     MIPS_HFLAG_FPU | MIPS_HFLAG_UM);
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM)) {
        if (env->CP0_Status & (1 << CP0St_UM))
            env->hflags |= MIPS_HFLAG_UM;
        if (env->CP0_Status & (1 << CP0St_R0))
            env->hflags |= MIPS_HFLAG_SM;
    }
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
    if (!(env->hflags & MIPS_HFLAG_UM) ||
        (env->CP0_Status & (1 << CP0St_PX)) ||
        (env->CP0_Status & (1 << CP0St_UX)))
        env->hflags |= MIPS_HFLAG_64;
#endif
    if ((env->CP0_Status & (1 << CP0St_CU0)) ||
        (!(env->hflags & MIPS_HFLAG_UM) &&
         !(env->hflags & MIPS_HFLAG_SM)))
        env->hflags |= MIPS_HFLAG_CP0;
    if (env->CP0_Status & (1 << CP0St_CU1))
        env->hflags |= MIPS_HFLAG_FPU;
    if (env->CP0_Status & (1 << CP0St_FR))
        env->hflags |= MIPS_HFLAG_F64;
}

#endif /* !defined(__QEMU_MIPS_EXEC_H__) */
Commit	Line	Data
6af0bf9c FB	1	#if !defined(__QEMU_MIPS_EXEC_H__)
	2	#define __QEMU_MIPS_EXEC_H__
	3
01dbbdf1	4	//#define DEBUG_OP
6af0bf9c	5
c570fd16	6	#include "config.h"
6af0bf9c FB	7	#include "mips-defs.h"
6af0bf9c FB	8	#include "dyngen-exec.h"
01179c38	9	#include "cpu-defs.h"
6af0bf9c FB	10
	11	register struct CPUMIPSState *env asm(AREG0);
	12
c570fd16 TS	13	#if TARGET_LONG_BITS > HOST_LONG_BITS
	14	#define T0 (env->t0)
	15	#define T1 (env->t1)
	16	#define T2 (env->t2)
	17	#else
01179c38 TS	18	register target_ulong T0 asm(AREG1);
	19	register target_ulong T1 asm(AREG2);
	20	register target_ulong T2 asm(AREG3);
c570fd16	21	#endif
6af0bf9c FB	22
6af0bf9c FB	23	#if defined (USE_HOST_FLOAT_REGS)
6ea83fed	24	#error "implement me."
6af0bf9c	25	#else
ead9360e TS	26	#define FDT0 (env->fpu->ft0.fd)
	27	#define FDT1 (env->fpu->ft1.fd)
	28	#define FDT2 (env->fpu->ft2.fd)
	29	#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
	30	#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
	31	#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
	32	#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
	33	#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
	34	#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
	35	#define DT0 (env->fpu->ft0.d)
	36	#define DT1 (env->fpu->ft1.d)
	37	#define DT2 (env->fpu->ft2.d)
	38	#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
	39	#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
	40	#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
	41	#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
	42	#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
	43	#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
6af0bf9c FB	44	#endif
	45
	46	#if defined (DEBUG_OP)
70ead434	47	# define RETURN() __asm__ __volatile__("nop" : : : "memory");
6af0bf9c	48	#else
70ead434	49	# define RETURN() __asm__ __volatile__("" : : : "memory");
6af0bf9c FB	50	#endif
	51
	52	#include "cpu.h"
	53	#include "exec-all.h"
	54
	55	#if !defined(CONFIG_USER_ONLY)
a9049a07	56	#include "softmmu_exec.h"
6af0bf9c FB	57	#endif /* !defined(CONFIG_USER_ONLY) */
6af0bf9c FB	58
540635ba	59	#if defined(TARGET_MIPSN32) \|\| defined(TARGET_MIPS64)
c570fd16 TS	60	#if TARGET_LONG_BITS > HOST_LONG_BITS
	61	void do_dsll (void);
	62	void do_dsll32 (void);
	63	void do_dsra (void);
	64	void do_dsra32 (void);
	65	void do_dsrl (void);
	66	void do_dsrl32 (void);
	67	void do_drotr (void);
	68	void do_drotr32 (void);
	69	void do_dsllv (void);
	70	void do_dsrav (void);
	71	void do_dsrlv (void);
	72	void do_drotrv (void);
	73	#endif
	74	#endif
	75
80c27194 TS	76	#if HOST_LONG_BITS < 64
	77	void do_div (void);
	78	#endif
c570fd16	79	#if TARGET_LONG_BITS > HOST_LONG_BITS
6af0bf9c FB	80	void do_mult (void);
	81	void do_multu (void);
	82	void do_madd (void);
	83	void do_maddu (void);
	84	void do_msub (void);
	85	void do_msubu (void);
80c27194	86	#endif
540635ba	87	#if defined(TARGET_MIPSN32) \|\| defined(TARGET_MIPS64)
c570fd16	88	void do_ddiv (void);
80c27194	89	#if TARGET_LONG_BITS > HOST_LONG_BITS
c570fd16 TS	90	void do_ddivu (void);
c570fd16 TS	91	#endif
6af0bf9c	92	#endif
873eb012 TS	93	void do_mfc0_random(void);
873eb012 TS	94	void do_mfc0_count(void);
7a387fff	95	void do_mtc0_entryhi(uint32_t in);
8c0fdd85 TS	96	void do_mtc0_status_debug(uint32_t old, uint32_t val);
8c0fdd85 TS	97	void do_mtc0_status_irqraise_debug(void);
6ea83fed	98	void dump_fpu(CPUState *env);
5fafdf24	99	void fpu_dump_state(CPUState env, FILE f,
6ea83fed FB	100	int (fpu_fprintf)(FILE f, const char *fmt, ...),
6ea83fed FB	101	int flags);
6ea83fed	102	void dump_sc (void);
6af0bf9c FB	103	void do_pmon (int function);
6af0bf9c FB	104
d2ec1774 PB	105	void dump_sc (void);
d2ec1774 PB	106
6af0bf9c	107	int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390	108	int mmu_idx, int is_softmmu);
6af0bf9c	109	void do_interrupt (CPUState *env);
29929e34	110	void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
6af0bf9c FB	111
6af0bf9c FB	112	void cpu_loop_exit(void);
6af0bf9c	113	void do_raise_exception_err (uint32_t exception, int error_code);
6af0bf9c	114	void do_raise_exception (uint32_t exception);
e397ee33	115	void do_raise_exception_direct_err (uint32_t exception, int error_code);
4ad40f36	116	void do_raise_exception_direct (uint32_t exception);
6af0bf9c	117
5fafdf24	118	void cpu_dump_state(CPUState env, FILE f,
6af0bf9c FB	119	int (cpu_fprintf)(FILE f, const char *fmt, ...),
	120	int flags);
	121	void cpu_mips_irqctrl_init (void);
	122	uint32_t cpu_mips_get_random (CPUState *env);
	123	uint32_t cpu_mips_get_count (CPUState *env);
	124	void cpu_mips_store_count (CPUState *env, uint32_t value);
	125	void cpu_mips_store_compare (CPUState *env, uint32_t value);
42532189 TS	126	void cpu_mips_start_count(CPUState *env);
42532189 TS	127	void cpu_mips_stop_count(CPUState *env);
a4bc3afc	128	void cpu_mips_update_irq (CPUState *env);
6af0bf9c	129	void cpu_mips_clock_init (CPUState *env);
814b9a47	130	void cpu_mips_tlb_flush (CPUState *env, int flush_global);
6af0bf9c	131
ead9360e TS	132	void do_cfc1 (int reg);
ead9360e TS	133	void do_ctc1 (int reg);
57fa1fb3 TS	134
	135	#define FOP_PROTO(op) \
	136	void do_float_ ## op ## _s(void); \
	137	void do_float_ ## op ## _d(void);
	138	FOP_PROTO(roundl)
	139	FOP_PROTO(roundw)
	140	FOP_PROTO(truncl)
	141	FOP_PROTO(truncw)
	142	FOP_PROTO(ceill)
	143	FOP_PROTO(ceilw)
	144	FOP_PROTO(floorl)
	145	FOP_PROTO(floorw)
	146	FOP_PROTO(rsqrt)
	147	FOP_PROTO(recip)
	148	#undef FOP_PROTO
	149
	150	#define FOP_PROTO(op) \
	151	void do_float_ ## op ## _s(void); \
	152	void do_float_ ## op ## _d(void); \
	153	void do_float_ ## op ## _ps(void);
	154	FOP_PROTO(add)
	155	FOP_PROTO(sub)
	156	FOP_PROTO(mul)
	157	FOP_PROTO(div)
	158	FOP_PROTO(recip1)
	159	FOP_PROTO(recip2)
	160	FOP_PROTO(rsqrt1)
	161	FOP_PROTO(rsqrt2)
	162	#undef FOP_PROTO
	163
fd4a04eb TS	164	void do_float_cvtd_s(void);
	165	void do_float_cvtd_w(void);
	166	void do_float_cvtd_l(void);
	167	void do_float_cvtl_d(void);
	168	void do_float_cvtl_s(void);
	169	void do_float_cvtps_pw(void);
	170	void do_float_cvtpw_ps(void);
	171	void do_float_cvts_d(void);
	172	void do_float_cvts_w(void);
	173	void do_float_cvts_l(void);
	174	void do_float_cvts_pl(void);
	175	void do_float_cvts_pu(void);
	176	void do_float_cvtw_s(void);
	177	void do_float_cvtw_d(void);
57fa1fb3	178
fd4a04eb	179	void do_float_addr_ps(void);
57fa1fb3	180	void do_float_mulr_ps(void);
fd4a04eb	181
57fa1fb3	182	#define FOP_PROTO(op) \
fd4a04eb TS	183	void do_cmp_d_ ## op(long cc); \
	184	void do_cmpabs_d_ ## op(long cc); \
	185	void do_cmp_s_ ## op(long cc); \
	186	void do_cmpabs_s_ ## op(long cc); \
	187	void do_cmp_ps_ ## op(long cc); \
	188	void do_cmpabs_ps_ ## op(long cc);
	189
57fa1fb3 TS	190	FOP_PROTO(f)
	191	FOP_PROTO(un)
	192	FOP_PROTO(eq)
	193	FOP_PROTO(ueq)
	194	FOP_PROTO(olt)
	195	FOP_PROTO(ult)
	196	FOP_PROTO(ole)
	197	FOP_PROTO(ule)
	198	FOP_PROTO(sf)
	199	FOP_PROTO(ngle)
	200	FOP_PROTO(seq)
	201	FOP_PROTO(ngl)
	202	FOP_PROTO(lt)
	203	FOP_PROTO(nge)
	204	FOP_PROTO(le)
	205	FOP_PROTO(ngt)
	206	#undef FOP_PROTO
fd4a04eb	207
aa343735	208	static always_inline void env_to_regs(void)
bfed01fc TS	209	{
	210	}
	211
aa343735	212	static always_inline void regs_to_env(void)
bfed01fc TS	213	{
	214	}
	215
aa343735	216	static always_inline int cpu_halted(CPUState *env)
08fa4bab	217	{
bfed01fc TS	218	if (!env->halted)
	219	return 0;
	220	if (env->interrupt_request &
	221	(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_TIMER)) {
	222	env->halted = 0;
	223	return 0;
	224	}
	225	return EXCP_HALTED;
	226	}
	227
aa343735	228	static always_inline void compute_hflags(CPUState *env)
08fa4bab TS	229	{
	230	env->hflags &= ~(MIPS_HFLAG_64 \| MIPS_HFLAG_CP0 \| MIPS_HFLAG_F64 \|
	231	MIPS_HFLAG_FPU \| MIPS_HFLAG_UM);
	232	if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
	233	!(env->CP0_Status & (1 << CP0St_ERL)) &&
671880e6 TS	234	!(env->hflags & MIPS_HFLAG_DM)) {
	235	if (env->CP0_Status & (1 << CP0St_UM))
	236	env->hflags \|= MIPS_HFLAG_UM;
	237	if (env->CP0_Status & (1 << CP0St_R0))
	238	env->hflags \|= MIPS_HFLAG_SM;
	239	}
540635ba	240	#if defined(TARGET_MIPSN32) \|\| defined(TARGET_MIPS64)
08fa4bab TS	241	if (!(env->hflags & MIPS_HFLAG_UM) \|\|
	242	(env->CP0_Status & (1 << CP0St_PX)) \|\|
	243	(env->CP0_Status & (1 << CP0St_UX)))
	244	env->hflags \|= MIPS_HFLAG_64;
	245	#endif
671880e6 TS	246	if ((env->CP0_Status & (1 << CP0St_CU0)) \|\|
	247	(!(env->hflags & MIPS_HFLAG_UM) &&
	248	!(env->hflags & MIPS_HFLAG_SM)))
08fa4bab TS	249	env->hflags \|= MIPS_HFLAG_CP0;
	250	if (env->CP0_Status & (1 << CP0St_CU1))
	251	env->hflags \|= MIPS_HFLAG_FPU;
	252	if (env->CP0_Status & (1 << CP0St_FR))
	253	env->hflags \|= MIPS_HFLAG_F64;
	254	}
	255
6af0bf9c	256	#endif /* !defined(__QEMU_MIPS_EXEC_H__) */