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Partial support for 34K multithreading, not functional yet.
[mirror_qemu.git] / target-mips / exec.h
CommitLineData
6af0bf9c
FB		 1#if !defined(__QEMU_MIPS_EXEC_H__)
2#define __QEMU_MIPS_EXEC_H__
3
01dbbdf1 4//#define DEBUG_OP
6af0bf9c 5
c570fd16 6#include "config.h"
6af0bf9c
FB		 7#include "mips-defs.h"
8#include "dyngen-exec.h"
01179c38 9#include "cpu-defs.h"
6af0bf9c
FB		 10
11register struct CPUMIPSState *env asm(AREG0);
12
c570fd16
TS		 13#if TARGET_LONG_BITS > HOST_LONG_BITS
14#define T0 (env->t0)
15#define T1 (env->t1)
16#define T2 (env->t2)
17#else
01179c38
TS		 18register target_ulong T0 asm(AREG1);
19register target_ulong T1 asm(AREG2);
20register target_ulong T2 asm(AREG3);
c570fd16 21#endif
6af0bf9c
FB		 22
23#if defined (USE_HOST_FLOAT_REGS)
6ea83fed 24#error "implement me."
6af0bf9c 25#else
ead9360e
TS		 26#define FDT0 (env->fpu->ft0.fd)
27#define FDT1 (env->fpu->ft1.fd)
28#define FDT2 (env->fpu->ft2.fd)
29#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
30#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
31#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
32#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
33#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
34#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
35#define DT0 (env->fpu->ft0.d)
36#define DT1 (env->fpu->ft1.d)
37#define DT2 (env->fpu->ft2.d)
38#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
39#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
40#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
41#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
42#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
43#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
6af0bf9c
FB		 44#endif
45
46#if defined (DEBUG_OP)
70ead434 47# define RETURN() __asm__ __volatile__("nop" : : : "memory");
6af0bf9c 48#else
70ead434 49# define RETURN() __asm__ __volatile__("" : : : "memory");
6af0bf9c
FB		 50#endif
51
52#include "cpu.h"
53#include "exec-all.h"
54
55#if !defined(CONFIG_USER_ONLY)
a9049a07 56#include "softmmu_exec.h"
6af0bf9c
FB		 57#endif /* !defined(CONFIG_USER_ONLY) */
58
60aa19ab 59#ifdef TARGET_MIPS64
c570fd16
TS		 60#if TARGET_LONG_BITS > HOST_LONG_BITS
61void do_dsll (void);
62void do_dsll32 (void);
63void do_dsra (void);
64void do_dsra32 (void);
65void do_dsrl (void);
66void do_dsrl32 (void);
67void do_drotr (void);
68void do_drotr32 (void);
69void do_dsllv (void);
70void do_dsrav (void);
71void do_dsrlv (void);
72void do_drotrv (void);
73#endif
74#endif
75
80c27194
TS		 76#if HOST_LONG_BITS < 64
77void do_div (void);
78#endif
c570fd16 79#if TARGET_LONG_BITS > HOST_LONG_BITS
6af0bf9c
FB		 80void do_mult (void);
81void do_multu (void);
82void do_madd (void);
83void do_maddu (void);
84void do_msub (void);
85void do_msubu (void);
80c27194
TS		 86#endif
87#ifdef TARGET_MIPS64
c570fd16 88void do_ddiv (void);
80c27194 89#if TARGET_LONG_BITS > HOST_LONG_BITS
c570fd16
TS		 90void do_ddivu (void);
91#endif
6af0bf9c 92#endif
873eb012
TS		 93void do_mfc0_random(void);
94void do_mfc0_count(void);
7a387fff 95void do_mtc0_entryhi(uint32_t in);
8c0fdd85
TS		 96void do_mtc0_status_debug(uint32_t old, uint32_t val);
97void do_mtc0_status_irqraise_debug(void);
6ea83fed
FB		 98void dump_fpu(CPUState *env);
99void fpu_dump_state(CPUState *env, FILE *f,
100 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
101 int flags);
6ea83fed 102void dump_sc (void);
4ad40f36
FB		 103void do_lwl_raw (uint32_t);
104void do_lwr_raw (uint32_t);
105uint32_t do_swl_raw (uint32_t);
106uint32_t do_swr_raw (uint32_t);
60aa19ab 107#ifdef TARGET_MIPS64
c570fd16
TS		 108void do_ldl_raw (uint64_t);
109void do_ldr_raw (uint64_t);
110uint64_t do_sdl_raw (uint64_t);
111uint64_t do_sdr_raw (uint64_t);
112#endif
6af0bf9c 113#if !defined(CONFIG_USER_ONLY)
4ad40f36
FB		 114void do_lwl_user (uint32_t);
115void do_lwl_kernel (uint32_t);
116void do_lwr_user (uint32_t);
117void do_lwr_kernel (uint32_t);
118uint32_t do_swl_user (uint32_t);
119uint32_t do_swl_kernel (uint32_t);
120uint32_t do_swr_user (uint32_t);
121uint32_t do_swr_kernel (uint32_t);
60aa19ab 122#ifdef TARGET_MIPS64
c570fd16
TS		 123void do_ldl_user (uint64_t);
124void do_ldl_kernel (uint64_t);
125void do_ldr_user (uint64_t);
126void do_ldr_kernel (uint64_t);
127uint64_t do_sdl_user (uint64_t);
128uint64_t do_sdl_kernel (uint64_t);
129uint64_t do_sdr_user (uint64_t);
130uint64_t do_sdr_kernel (uint64_t);
131#endif
6af0bf9c 132#endif
6af0bf9c
FB		 133void do_pmon (int function);
134
d2ec1774
PB		 135void dump_sc (void);
136
6af0bf9c
FB		 137int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
138 int is_user, int is_softmmu);
139void do_interrupt (CPUState *env);
29929e34 140void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
6af0bf9c
FB		 141
142void cpu_loop_exit(void);
6af0bf9c 143void do_raise_exception_err (uint32_t exception, int error_code);
6af0bf9c 144void do_raise_exception (uint32_t exception);
e397ee33 145void do_raise_exception_direct_err (uint32_t exception, int error_code);
4ad40f36 146void do_raise_exception_direct (uint32_t exception);
6af0bf9c
FB		 147
148void cpu_dump_state(CPUState *env, FILE *f,
149 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
150 int flags);
151void cpu_mips_irqctrl_init (void);
152uint32_t cpu_mips_get_random (CPUState *env);
153uint32_t cpu_mips_get_count (CPUState *env);
154void cpu_mips_store_count (CPUState *env, uint32_t value);
155void cpu_mips_store_compare (CPUState *env, uint32_t value);
a4bc3afc 156void cpu_mips_update_irq (CPUState *env);
6af0bf9c 157void cpu_mips_clock_init (CPUState *env);
814b9a47 158void cpu_mips_tlb_flush (CPUState *env, int flush_global);
6af0bf9c 159
ead9360e
TS		 160void do_cfc1 (int reg);
161void do_ctc1 (int reg);
57fa1fb3
TS		 162
163#define FOP_PROTO(op) \
164void do_float_ ## op ## _s(void); \
165void do_float_ ## op ## _d(void);
166FOP_PROTO(roundl)
167FOP_PROTO(roundw)
168FOP_PROTO(truncl)
169FOP_PROTO(truncw)
170FOP_PROTO(ceill)
171FOP_PROTO(ceilw)
172FOP_PROTO(floorl)
173FOP_PROTO(floorw)
174FOP_PROTO(rsqrt)
175FOP_PROTO(recip)
176#undef FOP_PROTO
177
178#define FOP_PROTO(op) \
179void do_float_ ## op ## _s(void); \
180void do_float_ ## op ## _d(void); \
181void do_float_ ## op ## _ps(void);
182FOP_PROTO(add)
183FOP_PROTO(sub)
184FOP_PROTO(mul)
185FOP_PROTO(div)
186FOP_PROTO(recip1)
187FOP_PROTO(recip2)
188FOP_PROTO(rsqrt1)
189FOP_PROTO(rsqrt2)
190#undef FOP_PROTO
191
fd4a04eb
TS		 192void do_float_cvtd_s(void);
193void do_float_cvtd_w(void);
194void do_float_cvtd_l(void);
195void do_float_cvtl_d(void);
196void do_float_cvtl_s(void);
197void do_float_cvtps_pw(void);
198void do_float_cvtpw_ps(void);
199void do_float_cvts_d(void);
200void do_float_cvts_w(void);
201void do_float_cvts_l(void);
202void do_float_cvts_pl(void);
203void do_float_cvts_pu(void);
204void do_float_cvtw_s(void);
205void do_float_cvtw_d(void);
57fa1fb3 206
fd4a04eb 207void do_float_addr_ps(void);
57fa1fb3 208void do_float_mulr_ps(void);
fd4a04eb 209
57fa1fb3 210#define FOP_PROTO(op) \
fd4a04eb
TS		 211void do_cmp_d_ ## op(long cc); \
212void do_cmpabs_d_ ## op(long cc); \
213void do_cmp_s_ ## op(long cc); \
214void do_cmpabs_s_ ## op(long cc); \
215void do_cmp_ps_ ## op(long cc); \
216void do_cmpabs_ps_ ## op(long cc);
217
57fa1fb3
TS		 218FOP_PROTO(f)
219FOP_PROTO(un)
220FOP_PROTO(eq)
221FOP_PROTO(ueq)
222FOP_PROTO(olt)
223FOP_PROTO(ult)
224FOP_PROTO(ole)
225FOP_PROTO(ule)
226FOP_PROTO(sf)
227FOP_PROTO(ngle)
228FOP_PROTO(seq)
229FOP_PROTO(ngl)
230FOP_PROTO(lt)
231FOP_PROTO(nge)
232FOP_PROTO(le)
233FOP_PROTO(ngt)
234#undef FOP_PROTO
fd4a04eb 235
bfed01fc
TS		 236static inline void env_to_regs(void)
237{
238}
239
240static inline void regs_to_env(void)
241{
242}
243
244static inline int cpu_halted(CPUState *env) {
245 if (!env->halted)
246 return 0;
247 if (env->interrupt_request &
248 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
249 env->halted = 0;
250 return 0;
251 }
252 return EXCP_HALTED;
253}
254
6af0bf9c 255#endif /* !defined(__QEMU_MIPS_EXEC_H__) */
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