]> git.proxmox.com Git - mirror_qemu.git/blame - target-mips/exec.h
Wrap a few often used tests with unlikely(), by Aurelien Jarno.
[mirror_qemu.git] / target-mips / exec.h
CommitLineData
6af0bf9c
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1#if !defined(__QEMU_MIPS_EXEC_H__)
2#define __QEMU_MIPS_EXEC_H__
3
01dbbdf1 4//#define DEBUG_OP
6af0bf9c 5
c570fd16 6#include "config.h"
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7#include "mips-defs.h"
8#include "dyngen-exec.h"
01179c38 9#include "cpu-defs.h"
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10
11register struct CPUMIPSState *env asm(AREG0);
12
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13#if TARGET_LONG_BITS > HOST_LONG_BITS
14#define T0 (env->t0)
15#define T1 (env->t1)
16#define T2 (env->t2)
17#else
01179c38
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18register target_ulong T0 asm(AREG1);
19register target_ulong T1 asm(AREG2);
20register target_ulong T2 asm(AREG3);
c570fd16 21#endif
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22
23#if defined (USE_HOST_FLOAT_REGS)
6ea83fed 24#error "implement me."
6af0bf9c 25#else
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26#define FDT0 (env->fpu->ft0.fd)
27#define FDT1 (env->fpu->ft1.fd)
28#define FDT2 (env->fpu->ft2.fd)
29#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
30#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
31#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
32#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
33#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
34#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
35#define DT0 (env->fpu->ft0.d)
36#define DT1 (env->fpu->ft1.d)
37#define DT2 (env->fpu->ft2.d)
38#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
39#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
40#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
41#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
42#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
43#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
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44#endif
45
46#if defined (DEBUG_OP)
70ead434 47# define RETURN() __asm__ __volatile__("nop" : : : "memory");
6af0bf9c 48#else
70ead434 49# define RETURN() __asm__ __volatile__("" : : : "memory");
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50#endif
51
52#include "cpu.h"
53#include "exec-all.h"
54
55#if !defined(CONFIG_USER_ONLY)
a9049a07 56#include "softmmu_exec.h"
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57#endif /* !defined(CONFIG_USER_ONLY) */
58
60aa19ab 59#ifdef TARGET_MIPS64
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60#if TARGET_LONG_BITS > HOST_LONG_BITS
61void do_dsll (void);
62void do_dsll32 (void);
63void do_dsra (void);
64void do_dsra32 (void);
65void do_dsrl (void);
66void do_dsrl32 (void);
67void do_drotr (void);
68void do_drotr32 (void);
69void do_dsllv (void);
70void do_dsrav (void);
71void do_dsrlv (void);
72void do_drotrv (void);
73#endif
74#endif
75
80c27194
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76#if HOST_LONG_BITS < 64
77void do_div (void);
78#endif
c570fd16 79#if TARGET_LONG_BITS > HOST_LONG_BITS
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80void do_mult (void);
81void do_multu (void);
82void do_madd (void);
83void do_maddu (void);
84void do_msub (void);
85void do_msubu (void);
80c27194
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86#endif
87#ifdef TARGET_MIPS64
c570fd16 88void do_ddiv (void);
80c27194 89#if TARGET_LONG_BITS > HOST_LONG_BITS
c570fd16
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90void do_ddivu (void);
91#endif
6af0bf9c 92#endif
873eb012
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93void do_mfc0_random(void);
94void do_mfc0_count(void);
7a387fff 95void do_mtc0_entryhi(uint32_t in);
8c0fdd85
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96void do_mtc0_status_debug(uint32_t old, uint32_t val);
97void do_mtc0_status_irqraise_debug(void);
6ea83fed 98void dump_fpu(CPUState *env);
5fafdf24 99void fpu_dump_state(CPUState *env, FILE *f,
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100 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
101 int flags);
6ea83fed 102void dump_sc (void);
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103void do_lwl_raw (uint32_t);
104void do_lwr_raw (uint32_t);
105uint32_t do_swl_raw (uint32_t);
106uint32_t do_swr_raw (uint32_t);
60aa19ab 107#ifdef TARGET_MIPS64
c570fd16
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108void do_ldl_raw (uint64_t);
109void do_ldr_raw (uint64_t);
110uint64_t do_sdl_raw (uint64_t);
111uint64_t do_sdr_raw (uint64_t);
112#endif
6af0bf9c 113#if !defined(CONFIG_USER_ONLY)
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114void do_lwl_user (uint32_t);
115void do_lwl_kernel (uint32_t);
116void do_lwr_user (uint32_t);
117void do_lwr_kernel (uint32_t);
118uint32_t do_swl_user (uint32_t);
119uint32_t do_swl_kernel (uint32_t);
120uint32_t do_swr_user (uint32_t);
121uint32_t do_swr_kernel (uint32_t);
60aa19ab 122#ifdef TARGET_MIPS64
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123void do_ldl_user (uint64_t);
124void do_ldl_kernel (uint64_t);
125void do_ldr_user (uint64_t);
126void do_ldr_kernel (uint64_t);
127uint64_t do_sdl_user (uint64_t);
128uint64_t do_sdl_kernel (uint64_t);
129uint64_t do_sdr_user (uint64_t);
130uint64_t do_sdr_kernel (uint64_t);
131#endif
6af0bf9c 132#endif
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133void do_pmon (int function);
134
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135void dump_sc (void);
136
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137int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
138 int is_user, int is_softmmu);
139void do_interrupt (CPUState *env);
29929e34 140void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
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141
142void cpu_loop_exit(void);
6af0bf9c 143void do_raise_exception_err (uint32_t exception, int error_code);
6af0bf9c 144void do_raise_exception (uint32_t exception);
e397ee33 145void do_raise_exception_direct_err (uint32_t exception, int error_code);
4ad40f36 146void do_raise_exception_direct (uint32_t exception);
6af0bf9c 147
5fafdf24 148void cpu_dump_state(CPUState *env, FILE *f,
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149 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
150 int flags);
151void cpu_mips_irqctrl_init (void);
152uint32_t cpu_mips_get_random (CPUState *env);
153uint32_t cpu_mips_get_count (CPUState *env);
154void cpu_mips_store_count (CPUState *env, uint32_t value);
155void cpu_mips_store_compare (CPUState *env, uint32_t value);
42532189
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156void cpu_mips_start_count(CPUState *env);
157void cpu_mips_stop_count(CPUState *env);
a4bc3afc 158void cpu_mips_update_irq (CPUState *env);
6af0bf9c 159void cpu_mips_clock_init (CPUState *env);
814b9a47 160void cpu_mips_tlb_flush (CPUState *env, int flush_global);
6af0bf9c 161
ead9360e
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162void do_cfc1 (int reg);
163void do_ctc1 (int reg);
57fa1fb3
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164
165#define FOP_PROTO(op) \
166void do_float_ ## op ## _s(void); \
167void do_float_ ## op ## _d(void);
168FOP_PROTO(roundl)
169FOP_PROTO(roundw)
170FOP_PROTO(truncl)
171FOP_PROTO(truncw)
172FOP_PROTO(ceill)
173FOP_PROTO(ceilw)
174FOP_PROTO(floorl)
175FOP_PROTO(floorw)
176FOP_PROTO(rsqrt)
177FOP_PROTO(recip)
178#undef FOP_PROTO
179
180#define FOP_PROTO(op) \
181void do_float_ ## op ## _s(void); \
182void do_float_ ## op ## _d(void); \
183void do_float_ ## op ## _ps(void);
184FOP_PROTO(add)
185FOP_PROTO(sub)
186FOP_PROTO(mul)
187FOP_PROTO(div)
188FOP_PROTO(recip1)
189FOP_PROTO(recip2)
190FOP_PROTO(rsqrt1)
191FOP_PROTO(rsqrt2)
192#undef FOP_PROTO
193
fd4a04eb
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194void do_float_cvtd_s(void);
195void do_float_cvtd_w(void);
196void do_float_cvtd_l(void);
197void do_float_cvtl_d(void);
198void do_float_cvtl_s(void);
199void do_float_cvtps_pw(void);
200void do_float_cvtpw_ps(void);
201void do_float_cvts_d(void);
202void do_float_cvts_w(void);
203void do_float_cvts_l(void);
204void do_float_cvts_pl(void);
205void do_float_cvts_pu(void);
206void do_float_cvtw_s(void);
207void do_float_cvtw_d(void);
57fa1fb3 208
fd4a04eb 209void do_float_addr_ps(void);
57fa1fb3 210void do_float_mulr_ps(void);
fd4a04eb 211
57fa1fb3 212#define FOP_PROTO(op) \
fd4a04eb
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213void do_cmp_d_ ## op(long cc); \
214void do_cmpabs_d_ ## op(long cc); \
215void do_cmp_s_ ## op(long cc); \
216void do_cmpabs_s_ ## op(long cc); \
217void do_cmp_ps_ ## op(long cc); \
218void do_cmpabs_ps_ ## op(long cc);
219
57fa1fb3
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220FOP_PROTO(f)
221FOP_PROTO(un)
222FOP_PROTO(eq)
223FOP_PROTO(ueq)
224FOP_PROTO(olt)
225FOP_PROTO(ult)
226FOP_PROTO(ole)
227FOP_PROTO(ule)
228FOP_PROTO(sf)
229FOP_PROTO(ngle)
230FOP_PROTO(seq)
231FOP_PROTO(ngl)
232FOP_PROTO(lt)
233FOP_PROTO(nge)
234FOP_PROTO(le)
235FOP_PROTO(ngt)
236#undef FOP_PROTO
fd4a04eb 237
bfed01fc
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238static inline void env_to_regs(void)
239{
240}
241
242static inline void regs_to_env(void)
243{
244}
245
246static inline int cpu_halted(CPUState *env) {
247 if (!env->halted)
248 return 0;
249 if (env->interrupt_request &
250 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
251 env->halted = 0;
252 return 0;
253 }
254 return EXCP_HALTED;
255}
256
6af0bf9c 257#endif /* !defined(__QEMU_MIPS_EXEC_H__) */