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6ea83fed 1/*
5fafdf24 2 * MIPS emulation micro-operations templates for floating point reg
6ea83fed 3 * load & store for qemu.
5fafdf24 4 *
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5 * Copyright (c) 2006 Marius Groeger
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
5a5012ec 22#if defined(FREG)
6ea83fed 23
5a5012ec
TS
24#define OP_WLOAD_FREG(treg, tregname, FREG) \
25 void glue(glue(op_load_fpr_,tregname), FREG) (void) \
26 { \
ead9360e 27 treg = env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX]; \
5a5012ec 28 RETURN(); \
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29 }
30
5a5012ec
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31#define OP_WSTORE_FREG(treg, tregname, FREG) \
32 void glue(glue(op_store_fpr_,tregname), FREG) (void) \
33 { \
ead9360e 34 env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX] = treg; \
5a5012ec 35 RETURN(); \
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36 }
37
5a5012ec
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38/* WT0 = FREG.w: op_load_fpr_WT0_fprFREG */
39OP_WLOAD_FREG(WT0, WT0_fpr, FREG)
40/* FREG.w = WT0: op_store_fpr_WT0_fprFREG */
41OP_WSTORE_FREG(WT0, WT0_fpr, FREG)
42
43OP_WLOAD_FREG(WT1, WT1_fpr, FREG)
44OP_WSTORE_FREG(WT1, WT1_fpr, FREG)
45
46OP_WLOAD_FREG(WT2, WT2_fpr, FREG)
47OP_WSTORE_FREG(WT2, WT2_fpr, FREG)
48
49#define OP_DLOAD_FREG(treg, tregname, FREG) \
50 void glue(glue(op_load_fpr_,tregname), FREG) (void) \
51 { \
5e755519 52 if (env->hflags & MIPS_HFLAG_F64) \
ead9360e 53 treg = env->fpu->fpr[FREG].fd; \
5a5012ec 54 else \
ead9360e
TS
55 treg = (uint64_t)(env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX]) << 32 | \
56 env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX]; \
5a5012ec
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57 RETURN(); \
58 }
6ea83fed 59
5a5012ec
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60#define OP_DSTORE_FREG(treg, tregname, FREG) \
61 void glue(glue(op_store_fpr_,tregname), FREG) (void) \
62 { \
5e755519 63 if (env->hflags & MIPS_HFLAG_F64) \
ead9360e 64 env->fpu->fpr[FREG].fd = treg; \
5a5012ec 65 else { \
ead9360e
TS
66 env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX] = treg >> 32; \
67 env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX] = treg; \
5a5012ec
TS
68 } \
69 RETURN(); \
70 }
6ea83fed 71
5a5012ec
TS
72OP_DLOAD_FREG(DT0, DT0_fpr, FREG)
73OP_DSTORE_FREG(DT0, DT0_fpr, FREG)
6ea83fed 74
5a5012ec
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75OP_DLOAD_FREG(DT1, DT1_fpr, FREG)
76OP_DSTORE_FREG(DT1, DT1_fpr, FREG)
6ea83fed 77
5a5012ec
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78OP_DLOAD_FREG(DT2, DT2_fpr, FREG)
79OP_DSTORE_FREG(DT2, DT2_fpr, FREG)
6ea83fed 80
5a5012ec
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81#define OP_PSLOAD_FREG(treg, tregname, FREG) \
82 void glue(glue(op_load_fpr_,tregname), FREG) (void) \
83 { \
ead9360e 84 treg = env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX]; \
5a5012ec 85 RETURN(); \
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86 }
87
5a5012ec
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88#define OP_PSSTORE_FREG(treg, tregname, FREG) \
89 void glue(glue(op_store_fpr_,tregname), FREG) (void) \
90 { \
ead9360e 91 env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX] = treg; \
5a5012ec 92 RETURN(); \
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93 }
94
5a5012ec
TS
95OP_PSLOAD_FREG(WTH0, WTH0_fpr, FREG)
96OP_PSSTORE_FREG(WTH0, WTH0_fpr, FREG)
6ea83fed 97
5a5012ec
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98OP_PSLOAD_FREG(WTH1, WTH1_fpr, FREG)
99OP_PSSTORE_FREG(WTH1, WTH1_fpr, FREG)
6ea83fed 100
5a5012ec
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101OP_PSLOAD_FREG(WTH2, WTH2_fpr, FREG)
102OP_PSSTORE_FREG(WTH2, WTH2_fpr, FREG)
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103
104#endif
105
106#if defined (FTN)
107
5a5012ec 108#define SET_RESET(treg, tregname) \
6ea83fed 109 void glue(op_set, tregname)(void) \
5a5012ec
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110 { \
111 treg = PARAM1; \
112 RETURN(); \
113 } \
6ea83fed 114 void glue(op_reset, tregname)(void) \
5a5012ec
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115 { \
116 treg = 0; \
117 RETURN(); \
118 }
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119
120SET_RESET(WT0, _WT0)
121SET_RESET(WT1, _WT1)
122SET_RESET(WT2, _WT2)
123SET_RESET(DT0, _DT0)
124SET_RESET(DT1, _DT1)
125SET_RESET(DT2, _DT2)
5a5012ec
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126SET_RESET(WTH0, _WTH0)
127SET_RESET(WTH1, _WTH1)
128SET_RESET(WTH2, _WTH2)
6ea83fed 129
c570fd16 130#undef SET_RESET
6ea83fed 131#endif