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1 | /* |
2 | * MIPS gdb server stub | |
3 | * | |
4 | * Copyright (c) 2003-2005 Fabrice Bellard | |
5 | * Copyright (c) 2013 SUSE LINUX Products GmbH | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n) | |
22 | { | |
23 | if (n < 32) { | |
24 | GET_REGL(env->active_tc.gpr[n]); | |
25 | } | |
26 | if (env->CP0_Config1 & (1 << CP0C1_FP)) { | |
27 | if (n >= 38 && n < 70) { | |
28 | if (env->CP0_Status & (1 << CP0St_FR)) { | |
29 | GET_REGL(env->active_fpu.fpr[n - 38].d); | |
30 | } else { | |
31 | GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); | |
32 | } | |
33 | } | |
34 | switch (n) { | |
35 | case 70: | |
36 | GET_REGL((int32_t)env->active_fpu.fcr31); | |
37 | case 71: | |
38 | GET_REGL((int32_t)env->active_fpu.fcr0); | |
39 | } | |
40 | } | |
41 | switch (n) { | |
42 | case 32: | |
43 | GET_REGL((int32_t)env->CP0_Status); | |
44 | case 33: | |
45 | GET_REGL(env->active_tc.LO[0]); | |
46 | case 34: | |
47 | GET_REGL(env->active_tc.HI[0]); | |
48 | case 35: | |
49 | GET_REGL(env->CP0_BadVAddr); | |
50 | case 36: | |
51 | GET_REGL((int32_t)env->CP0_Cause); | |
52 | case 37: | |
53 | GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16)); | |
54 | case 72: | |
55 | GET_REGL(0); /* fp */ | |
56 | case 89: | |
57 | GET_REGL((int32_t)env->CP0_PRid); | |
58 | } | |
59 | if (n >= 73 && n <= 88) { | |
60 | /* 16 embedded regs. */ | |
61 | GET_REGL(0); | |
62 | } | |
63 | ||
64 | return 0; | |
65 | } | |
66 | ||
67 | /* convert MIPS rounding mode in FCR31 to IEEE library */ | |
68 | static unsigned int ieee_rm[] = { | |
69 | float_round_nearest_even, | |
70 | float_round_to_zero, | |
71 | float_round_up, | |
72 | float_round_down | |
73 | }; | |
74 | #define RESTORE_ROUNDING_MODE \ | |
75 | set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \ | |
76 | &env->active_fpu.fp_status) | |
77 | ||
78 | static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n) | |
79 | { | |
80 | target_ulong tmp; | |
81 | ||
82 | tmp = ldtul_p(mem_buf); | |
83 | ||
84 | if (n < 32) { | |
85 | env->active_tc.gpr[n] = tmp; | |
86 | return sizeof(target_ulong); | |
87 | } | |
88 | if (env->CP0_Config1 & (1 << CP0C1_FP) | |
89 | && n >= 38 && n < 73) { | |
90 | if (n < 70) { | |
91 | if (env->CP0_Status & (1 << CP0St_FR)) { | |
92 | env->active_fpu.fpr[n - 38].d = tmp; | |
93 | } else { | |
94 | env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; | |
95 | } | |
96 | } | |
97 | switch (n) { | |
98 | case 70: | |
99 | env->active_fpu.fcr31 = tmp & 0xFF83FFFF; | |
100 | /* set rounding mode */ | |
101 | RESTORE_ROUNDING_MODE; | |
102 | break; | |
103 | case 71: | |
104 | env->active_fpu.fcr0 = tmp; | |
105 | break; | |
106 | } | |
107 | return sizeof(target_ulong); | |
108 | } | |
109 | switch (n) { | |
110 | case 32: | |
111 | env->CP0_Status = tmp; | |
112 | break; | |
113 | case 33: | |
114 | env->active_tc.LO[0] = tmp; | |
115 | break; | |
116 | case 34: | |
117 | env->active_tc.HI[0] = tmp; | |
118 | break; | |
119 | case 35: | |
120 | env->CP0_BadVAddr = tmp; | |
121 | break; | |
122 | case 36: | |
123 | env->CP0_Cause = tmp; | |
124 | break; | |
125 | case 37: | |
126 | env->active_tc.PC = tmp & ~(target_ulong)1; | |
127 | if (tmp & 1) { | |
128 | env->hflags |= MIPS_HFLAG_M16; | |
129 | } else { | |
130 | env->hflags &= ~(MIPS_HFLAG_M16); | |
131 | } | |
132 | break; | |
133 | case 72: /* fp, ignored */ | |
134 | break; | |
135 | default: | |
136 | if (n > 89) { | |
137 | return 0; | |
138 | } | |
139 | /* Other registers are readonly. Ignore writes. */ | |
140 | break; | |
141 | } | |
142 | ||
143 | return sizeof(target_ulong); | |
144 | } |