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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
fad6cb1a | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
6af0bf9c | 19 | */ |
e37e863f FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <signal.h> | |
e37e863f FB |
26 | |
27 | #include "cpu.h" | |
28 | #include "exec-all.h" | |
6af0bf9c | 29 | |
43057ab1 FB |
30 | enum { |
31 | TLBRET_DIRTY = -4, | |
32 | TLBRET_INVALID = -3, | |
33 | TLBRET_NOMATCH = -2, | |
34 | TLBRET_BADADDR = -1, | |
35 | TLBRET_MATCH = 0 | |
36 | }; | |
37 | ||
29929e34 TS |
38 | /* no MMU emulation */ |
39 | int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, | |
6af0bf9c | 40 | target_ulong address, int rw, int access_type) |
29929e34 TS |
41 | { |
42 | *physical = address; | |
43 | *prot = PAGE_READ | PAGE_WRITE; | |
44 | return TLBRET_MATCH; | |
45 | } | |
46 | ||
47 | /* fixed mapping MMU emulation */ | |
48 | int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, | |
49 | target_ulong address, int rw, int access_type) | |
50 | { | |
51 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
52 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
53 | *physical = address + 0x40000000UL; | |
54 | else | |
55 | *physical = address; | |
56 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
57 | *physical = address & 0x1FFFFFFF; | |
58 | else | |
59 | *physical = address; | |
60 | ||
61 | *prot = PAGE_READ | PAGE_WRITE; | |
62 | return TLBRET_MATCH; | |
63 | } | |
64 | ||
65 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
66 | int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, | |
67 | target_ulong address, int rw, int access_type) | |
6af0bf9c | 68 | { |
925fd0f2 | 69 | uint8_t ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 70 | int i; |
6af0bf9c | 71 | |
ead9360e TS |
72 | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
73 | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; | |
3b1c8be4 | 74 | /* 1k pages are not supported. */ |
f2e9ebef | 75 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 76 | target_ulong tag = address & ~mask; |
f2e9ebef | 77 | target_ulong VPN = tlb->VPN & ~mask; |
d26bc211 | 78 | #if defined(TARGET_MIPS64) |
e034e2c3 | 79 | tag &= env->SEGMask; |
100ce988 | 80 | #endif |
3b1c8be4 | 81 | |
6af0bf9c | 82 | /* Check ASID, virtual page number & size */ |
f2e9ebef | 83 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
6af0bf9c | 84 | /* TLB match */ |
f2e9ebef | 85 | int n = !!(address & mask & ~(mask >> 1)); |
6af0bf9c | 86 | /* Check access rights */ |
f2e9ebef | 87 | if (!(n ? tlb->V1 : tlb->V0)) |
43057ab1 | 88 | return TLBRET_INVALID; |
f2e9ebef | 89 | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
3b1c8be4 | 90 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
9fb63ac2 | 91 | *prot = PAGE_READ; |
98c1b82b | 92 | if (n ? tlb->D1 : tlb->D0) |
9fb63ac2 | 93 | *prot |= PAGE_WRITE; |
43057ab1 | 94 | return TLBRET_MATCH; |
6af0bf9c | 95 | } |
43057ab1 | 96 | return TLBRET_DIRTY; |
6af0bf9c FB |
97 | } |
98 | } | |
43057ab1 | 99 | return TLBRET_NOMATCH; |
6af0bf9c | 100 | } |
6af0bf9c | 101 | |
932e71cd | 102 | #if !defined(CONFIG_USER_ONLY) |
43057ab1 FB |
103 | static int get_physical_address (CPUState *env, target_ulong *physical, |
104 | int *prot, target_ulong address, | |
105 | int rw, int access_type) | |
6af0bf9c | 106 | { |
b4ab4b4e | 107 | /* User mode can only access useg/xuseg */ |
43057ab1 | 108 | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
671880e6 TS |
109 | int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; |
110 | int kernel_mode = !user_mode && !supervisor_mode; | |
d26bc211 | 111 | #if defined(TARGET_MIPS64) |
b4ab4b4e TS |
112 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
113 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
114 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
115 | #endif | |
43057ab1 FB |
116 | int ret = TLBRET_MATCH; |
117 | ||
6af0bf9c | 118 | #if 0 |
93fcfe39 | 119 | qemu_log("user mode %d h %08x\n", user_mode, env->hflags); |
6af0bf9c | 120 | #endif |
b4ab4b4e | 121 | |
b4ab4b4e TS |
122 | if (address <= (int32_t)0x7FFFFFFFUL) { |
123 | /* useg */ | |
996ba2cc | 124 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
29929e34 | 125 | *physical = address & 0xFFFFFFFF; |
6af0bf9c | 126 | *prot = PAGE_READ | PAGE_WRITE; |
996ba2cc | 127 | } else { |
ead9360e | 128 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
6af0bf9c | 129 | } |
d26bc211 | 130 | #if defined(TARGET_MIPS64) |
89fc88da | 131 | } else if (address < 0x4000000000000000ULL) { |
b4ab4b4e | 132 | /* xuseg */ |
6958549d | 133 | if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
ead9360e | 134 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
6958549d AJ |
135 | } else { |
136 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 137 | } |
89fc88da | 138 | } else if (address < 0x8000000000000000ULL) { |
b4ab4b4e | 139 | /* xsseg */ |
6958549d AJ |
140 | if ((supervisor_mode || kernel_mode) && |
141 | SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { | |
ead9360e | 142 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
6958549d AJ |
143 | } else { |
144 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 145 | } |
89fc88da | 146 | } else if (address < 0xC000000000000000ULL) { |
b4ab4b4e | 147 | /* xkphys */ |
671880e6 | 148 | if (kernel_mode && KX && |
6d35524c TS |
149 | (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { |
150 | *physical = address & env->PAMask; | |
b4ab4b4e | 151 | *prot = PAGE_READ | PAGE_WRITE; |
6958549d AJ |
152 | } else { |
153 | ret = TLBRET_BADADDR; | |
154 | } | |
89fc88da | 155 | } else if (address < 0xFFFFFFFF80000000ULL) { |
b4ab4b4e | 156 | /* xkseg */ |
6958549d AJ |
157 | if (kernel_mode && KX && |
158 | address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { | |
ead9360e | 159 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
6958549d AJ |
160 | } else { |
161 | ret = TLBRET_BADADDR; | |
162 | } | |
b4ab4b4e | 163 | #endif |
5dc4b744 | 164 | } else if (address < (int32_t)0xA0000000UL) { |
6af0bf9c | 165 | /* kseg0 */ |
671880e6 TS |
166 | if (kernel_mode) { |
167 | *physical = address - (int32_t)0x80000000UL; | |
168 | *prot = PAGE_READ | PAGE_WRITE; | |
169 | } else { | |
170 | ret = TLBRET_BADADDR; | |
171 | } | |
5dc4b744 | 172 | } else if (address < (int32_t)0xC0000000UL) { |
6af0bf9c | 173 | /* kseg1 */ |
671880e6 TS |
174 | if (kernel_mode) { |
175 | *physical = address - (int32_t)0xA0000000UL; | |
176 | *prot = PAGE_READ | PAGE_WRITE; | |
177 | } else { | |
178 | ret = TLBRET_BADADDR; | |
179 | } | |
5dc4b744 | 180 | } else if (address < (int32_t)0xE0000000UL) { |
89fc88da | 181 | /* sseg (kseg2) */ |
671880e6 TS |
182 | if (supervisor_mode || kernel_mode) { |
183 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
184 | } else { | |
185 | ret = TLBRET_BADADDR; | |
186 | } | |
6af0bf9c FB |
187 | } else { |
188 | /* kseg3 */ | |
6af0bf9c | 189 | /* XXX: debug segment is not emulated */ |
671880e6 TS |
190 | if (kernel_mode) { |
191 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
192 | } else { | |
193 | ret = TLBRET_BADADDR; | |
194 | } | |
6af0bf9c FB |
195 | } |
196 | #if 0 | |
93fcfe39 AL |
197 | qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n", |
198 | address, rw, access_type, *physical, *prot, ret); | |
6af0bf9c FB |
199 | } |
200 | #endif | |
201 | ||
202 | return ret; | |
203 | } | |
932e71cd | 204 | #endif |
6af0bf9c | 205 | |
9b3c35e0 | 206 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
6af0bf9c | 207 | { |
932e71cd AJ |
208 | #if defined(CONFIG_USER_ONLY) |
209 | return addr; | |
210 | #else | |
211 | target_ulong phys_addr; | |
212 | int prot; | |
6af0bf9c | 213 | |
932e71cd AJ |
214 | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
215 | return -1; | |
216 | return phys_addr; | |
217 | #endif | |
6af0bf9c | 218 | } |
6af0bf9c | 219 | |
6af0bf9c | 220 | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 221 | int mmu_idx, int is_softmmu) |
6af0bf9c | 222 | { |
932e71cd | 223 | #if !defined(CONFIG_USER_ONLY) |
6af0bf9c FB |
224 | target_ulong physical; |
225 | int prot; | |
932e71cd | 226 | #endif |
6af0bf9c FB |
227 | int exception = 0, error_code = 0; |
228 | int access_type; | |
229 | int ret = 0; | |
230 | ||
4ad40f36 | 231 | #if 0 |
93fcfe39 | 232 | log_cpu_state(env, 0); |
4ad40f36 | 233 | #endif |
93fcfe39 AL |
234 | qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", |
235 | __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu); | |
4ad40f36 FB |
236 | |
237 | rw &= 1; | |
238 | ||
6af0bf9c FB |
239 | /* data access */ |
240 | /* XXX: put correct access by using cpu_restore_state() | |
241 | correctly */ | |
242 | access_type = ACCESS_INT; | |
932e71cd AJ |
243 | #if defined(CONFIG_USER_ONLY) |
244 | ret = TLBRET_NOMATCH; | |
245 | #else | |
6af0bf9c FB |
246 | ret = get_physical_address(env, &physical, &prot, |
247 | address, rw, access_type); | |
93fcfe39 AL |
248 | qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n", |
249 | __func__, address, ret, physical, prot); | |
43057ab1 FB |
250 | if (ret == TLBRET_MATCH) { |
251 | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, | |
252 | physical & TARGET_PAGE_MASK, prot, | |
6ebbf390 | 253 | mmu_idx, is_softmmu); |
932e71cd AJ |
254 | } else if (ret < 0) |
255 | #endif | |
256 | { | |
6af0bf9c FB |
257 | switch (ret) { |
258 | default: | |
43057ab1 | 259 | case TLBRET_BADADDR: |
6af0bf9c FB |
260 | /* Reference to kernel address from user mode or supervisor mode */ |
261 | /* Reference to supervisor address from user mode */ | |
262 | if (rw) | |
263 | exception = EXCP_AdES; | |
264 | else | |
265 | exception = EXCP_AdEL; | |
266 | break; | |
43057ab1 | 267 | case TLBRET_NOMATCH: |
6af0bf9c FB |
268 | /* No TLB match for a mapped address */ |
269 | if (rw) | |
270 | exception = EXCP_TLBS; | |
271 | else | |
272 | exception = EXCP_TLBL; | |
273 | error_code = 1; | |
274 | break; | |
43057ab1 | 275 | case TLBRET_INVALID: |
6af0bf9c FB |
276 | /* TLB match with no valid bit */ |
277 | if (rw) | |
278 | exception = EXCP_TLBS; | |
279 | else | |
280 | exception = EXCP_TLBL; | |
6af0bf9c | 281 | break; |
43057ab1 | 282 | case TLBRET_DIRTY: |
6af0bf9c FB |
283 | /* TLB match but 'D' bit is cleared */ |
284 | exception = EXCP_LTLBL; | |
285 | break; | |
3b46e624 | 286 | |
6af0bf9c | 287 | } |
6af0bf9c FB |
288 | /* Raise exception */ |
289 | env->CP0_BadVAddr = address; | |
100ce988 | 290 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | |
6958549d | 291 | ((address >> 9) & 0x007ffff0); |
6af0bf9c | 292 | env->CP0_EntryHi = |
43057ab1 | 293 | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
d26bc211 | 294 | #if defined(TARGET_MIPS64) |
e034e2c3 TS |
295 | env->CP0_EntryHi &= env->SEGMask; |
296 | env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | | |
9c67ef0c | 297 | ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | |
e034e2c3 | 298 | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); |
100ce988 | 299 | #endif |
6af0bf9c FB |
300 | env->exception_index = exception; |
301 | env->error_code = error_code; | |
302 | ret = 1; | |
303 | } | |
304 | ||
305 | return ret; | |
306 | } | |
307 | ||
9a5d878f TS |
308 | static const char * const excp_names[EXCP_LAST + 1] = { |
309 | [EXCP_RESET] = "reset", | |
310 | [EXCP_SRESET] = "soft reset", | |
311 | [EXCP_DSS] = "debug single step", | |
312 | [EXCP_DINT] = "debug interrupt", | |
313 | [EXCP_NMI] = "non-maskable interrupt", | |
314 | [EXCP_MCHECK] = "machine check", | |
315 | [EXCP_EXT_INTERRUPT] = "interrupt", | |
316 | [EXCP_DFWATCH] = "deferred watchpoint", | |
317 | [EXCP_DIB] = "debug instruction breakpoint", | |
318 | [EXCP_IWATCH] = "instruction fetch watchpoint", | |
319 | [EXCP_AdEL] = "address error load", | |
320 | [EXCP_AdES] = "address error store", | |
321 | [EXCP_TLBF] = "TLB refill", | |
322 | [EXCP_IBE] = "instruction bus error", | |
323 | [EXCP_DBp] = "debug breakpoint", | |
324 | [EXCP_SYSCALL] = "syscall", | |
325 | [EXCP_BREAK] = "break", | |
326 | [EXCP_CpU] = "coprocessor unusable", | |
327 | [EXCP_RI] = "reserved instruction", | |
328 | [EXCP_OVERFLOW] = "arithmetic overflow", | |
329 | [EXCP_TRAP] = "trap", | |
330 | [EXCP_FPE] = "floating point", | |
331 | [EXCP_DDBS] = "debug data break store", | |
332 | [EXCP_DWATCH] = "data watchpoint", | |
333 | [EXCP_LTLBL] = "TLB modify", | |
334 | [EXCP_TLBL] = "TLB load", | |
335 | [EXCP_TLBS] = "TLB store", | |
336 | [EXCP_DBE] = "data bus error", | |
337 | [EXCP_DDBL] = "debug data break load", | |
338 | [EXCP_THREAD] = "thread", | |
339 | [EXCP_MDMX] = "MDMX", | |
340 | [EXCP_C2E] = "precise coprocessor 2", | |
341 | [EXCP_CACHE] = "cache error", | |
14e51cc7 | 342 | }; |
14e51cc7 | 343 | |
6af0bf9c FB |
344 | void do_interrupt (CPUState *env) |
345 | { | |
932e71cd AJ |
346 | #if !defined(CONFIG_USER_ONLY) |
347 | target_ulong offset; | |
348 | int cause = -1; | |
349 | const char *name; | |
100ce988 | 350 | |
93fcfe39 | 351 | if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { |
932e71cd AJ |
352 | if (env->exception_index < 0 || env->exception_index > EXCP_LAST) |
353 | name = "unknown"; | |
354 | else | |
355 | name = excp_names[env->exception_index]; | |
b67bfe8d | 356 | |
93fcfe39 AL |
357 | qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", |
358 | __func__, env->active_tc.PC, env->CP0_EPC, name); | |
932e71cd AJ |
359 | } |
360 | if (env->exception_index == EXCP_EXT_INTERRUPT && | |
361 | (env->hflags & MIPS_HFLAG_DM)) | |
362 | env->exception_index = EXCP_DINT; | |
363 | offset = 0x180; | |
364 | switch (env->exception_index) { | |
365 | case EXCP_DSS: | |
366 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
367 | /* Debug single step cannot be raised inside a delay slot and | |
368 | resume will always occur on the next instruction | |
369 | (but we assume the pc has always been updated during | |
370 | code translation). */ | |
371 | env->CP0_DEPC = env->active_tc.PC; | |
372 | goto enter_debug_mode; | |
373 | case EXCP_DINT: | |
374 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
375 | goto set_DEPC; | |
376 | case EXCP_DIB: | |
377 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
378 | goto set_DEPC; | |
379 | case EXCP_DBp: | |
380 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
381 | goto set_DEPC; | |
382 | case EXCP_DDBS: | |
383 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
384 | goto set_DEPC; | |
385 | case EXCP_DDBL: | |
386 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
387 | set_DEPC: | |
388 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
389 | /* If the exception was raised from a delay slot, | |
390 | come back to the jump. */ | |
391 | env->CP0_DEPC = env->active_tc.PC - 4; | |
392 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
393 | } else { | |
0eaef5aa | 394 | env->CP0_DEPC = env->active_tc.PC; |
932e71cd | 395 | } |
0eaef5aa | 396 | enter_debug_mode: |
932e71cd AJ |
397 | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
398 | env->hflags &= ~(MIPS_HFLAG_KSU); | |
399 | /* EJTAG probe trap enable is not implemented... */ | |
400 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
401 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
402 | env->active_tc.PC = (int32_t)0xBFC00480; | |
403 | break; | |
404 | case EXCP_RESET: | |
405 | cpu_reset(env); | |
406 | break; | |
407 | case EXCP_SRESET: | |
408 | env->CP0_Status |= (1 << CP0St_SR); | |
409 | memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); | |
410 | goto set_error_EPC; | |
411 | case EXCP_NMI: | |
412 | env->CP0_Status |= (1 << CP0St_NMI); | |
0eaef5aa | 413 | set_error_EPC: |
932e71cd AJ |
414 | if (env->hflags & MIPS_HFLAG_BMASK) { |
415 | /* If the exception was raised from a delay slot, | |
416 | come back to the jump. */ | |
417 | env->CP0_ErrorEPC = env->active_tc.PC - 4; | |
418 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
419 | } else { | |
420 | env->CP0_ErrorEPC = env->active_tc.PC; | |
421 | } | |
422 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); | |
423 | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; | |
424 | env->hflags &= ~(MIPS_HFLAG_KSU); | |
425 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
426 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
427 | env->active_tc.PC = (int32_t)0xBFC00000; | |
428 | break; | |
429 | case EXCP_EXT_INTERRUPT: | |
430 | cause = 0; | |
431 | if (env->CP0_Cause & (1 << CP0Ca_IV)) | |
432 | offset = 0x200; | |
433 | goto set_EPC; | |
434 | case EXCP_LTLBL: | |
435 | cause = 1; | |
436 | goto set_EPC; | |
437 | case EXCP_TLBL: | |
438 | cause = 2; | |
439 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 440 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
441 | int R = env->CP0_BadVAddr >> 62; |
442 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
443 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
444 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 445 | |
932e71cd AJ |
446 | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
447 | offset = 0x080; | |
448 | else | |
0eaef5aa | 449 | #endif |
932e71cd AJ |
450 | offset = 0x000; |
451 | } | |
452 | goto set_EPC; | |
453 | case EXCP_TLBS: | |
454 | cause = 3; | |
455 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 456 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
457 | int R = env->CP0_BadVAddr >> 62; |
458 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
459 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
460 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 461 | |
932e71cd AJ |
462 | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
463 | offset = 0x080; | |
464 | else | |
0eaef5aa | 465 | #endif |
932e71cd AJ |
466 | offset = 0x000; |
467 | } | |
468 | goto set_EPC; | |
469 | case EXCP_AdEL: | |
470 | cause = 4; | |
471 | goto set_EPC; | |
472 | case EXCP_AdES: | |
473 | cause = 5; | |
474 | goto set_EPC; | |
475 | case EXCP_IBE: | |
476 | cause = 6; | |
477 | goto set_EPC; | |
478 | case EXCP_DBE: | |
479 | cause = 7; | |
480 | goto set_EPC; | |
481 | case EXCP_SYSCALL: | |
482 | cause = 8; | |
483 | goto set_EPC; | |
484 | case EXCP_BREAK: | |
485 | cause = 9; | |
486 | goto set_EPC; | |
487 | case EXCP_RI: | |
488 | cause = 10; | |
489 | goto set_EPC; | |
490 | case EXCP_CpU: | |
491 | cause = 11; | |
492 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | | |
493 | (env->error_code << CP0Ca_CE); | |
494 | goto set_EPC; | |
495 | case EXCP_OVERFLOW: | |
496 | cause = 12; | |
497 | goto set_EPC; | |
498 | case EXCP_TRAP: | |
499 | cause = 13; | |
500 | goto set_EPC; | |
501 | case EXCP_FPE: | |
502 | cause = 15; | |
503 | goto set_EPC; | |
504 | case EXCP_C2E: | |
505 | cause = 18; | |
506 | goto set_EPC; | |
507 | case EXCP_MDMX: | |
508 | cause = 22; | |
509 | goto set_EPC; | |
510 | case EXCP_DWATCH: | |
511 | cause = 23; | |
512 | /* XXX: TODO: manage defered watch exceptions */ | |
513 | goto set_EPC; | |
514 | case EXCP_MCHECK: | |
515 | cause = 24; | |
516 | goto set_EPC; | |
517 | case EXCP_THREAD: | |
518 | cause = 25; | |
519 | goto set_EPC; | |
520 | case EXCP_CACHE: | |
521 | cause = 30; | |
522 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
523 | offset = 0x100; | |
524 | } else { | |
525 | offset = 0x20000100; | |
526 | } | |
0eaef5aa | 527 | set_EPC: |
932e71cd AJ |
528 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
529 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
530 | /* If the exception was raised from a delay slot, | |
531 | come back to the jump. */ | |
532 | env->CP0_EPC = env->active_tc.PC - 4; | |
533 | env->CP0_Cause |= (1 << CP0Ca_BD); | |
0eaef5aa | 534 | } else { |
932e71cd AJ |
535 | env->CP0_EPC = env->active_tc.PC; |
536 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
0eaef5aa | 537 | } |
932e71cd AJ |
538 | env->CP0_Status |= (1 << CP0St_EXL); |
539 | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; | |
540 | env->hflags &= ~(MIPS_HFLAG_KSU); | |
6af0bf9c | 541 | } |
932e71cd AJ |
542 | env->hflags &= ~MIPS_HFLAG_BMASK; |
543 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
544 | env->active_tc.PC = (int32_t)0xBFC00200; | |
545 | } else { | |
546 | env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); | |
6af0bf9c | 547 | } |
932e71cd AJ |
548 | env->active_tc.PC += offset; |
549 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); | |
550 | break; | |
551 | default: | |
93fcfe39 | 552 | qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index); |
932e71cd AJ |
553 | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); |
554 | exit(1); | |
555 | } | |
93fcfe39 AL |
556 | if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { |
557 | qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" | |
932e71cd AJ |
558 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
559 | __func__, env->active_tc.PC, env->CP0_EPC, cause, | |
560 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, | |
561 | env->CP0_DEPC); | |
6af0bf9c | 562 | } |
932e71cd | 563 | #endif |
6af0bf9c FB |
564 | env->exception_index = EXCP_NONE; |
565 | } | |
2ee4aed8 | 566 | |
29929e34 | 567 | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) |
2ee4aed8 | 568 | { |
29929e34 | 569 | r4k_tlb_t *tlb; |
3b1c8be4 TS |
570 | target_ulong addr; |
571 | target_ulong end; | |
572 | uint8_t ASID = env->CP0_EntryHi & 0xFF; | |
573 | target_ulong mask; | |
2ee4aed8 | 574 | |
ead9360e | 575 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 576 | /* The qemu TLB is flushed when the ASID changes, so no need to |
2ee4aed8 FB |
577 | flush these entries again. */ |
578 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
579 | return; | |
580 | } | |
581 | ||
ead9360e | 582 | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { |
2ee4aed8 | 583 | /* For tlbwr, we can shadow the discarded entry into |
6958549d AJ |
584 | a new (fake) TLB entry, as long as the guest can not |
585 | tell that it's there. */ | |
ead9360e TS |
586 | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
587 | env->tlb->tlb_in_use++; | |
2ee4aed8 FB |
588 | return; |
589 | } | |
590 | ||
3b1c8be4 | 591 | /* 1k pages are not supported. */ |
f2e9ebef | 592 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 593 | if (tlb->V0) { |
f2e9ebef | 594 | addr = tlb->VPN & ~mask; |
d26bc211 | 595 | #if defined(TARGET_MIPS64) |
e034e2c3 | 596 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
597 | addr |= 0x3FFFFF0000000000ULL; |
598 | } | |
599 | #endif | |
3b1c8be4 TS |
600 | end = addr | (mask >> 1); |
601 | while (addr < end) { | |
602 | tlb_flush_page (env, addr); | |
603 | addr += TARGET_PAGE_SIZE; | |
604 | } | |
605 | } | |
606 | if (tlb->V1) { | |
f2e9ebef | 607 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
d26bc211 | 608 | #if defined(TARGET_MIPS64) |
e034e2c3 | 609 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
610 | addr |= 0x3FFFFF0000000000ULL; |
611 | } | |
612 | #endif | |
3b1c8be4 | 613 | end = addr | mask; |
53715e48 | 614 | while (addr - 1 < end) { |
3b1c8be4 TS |
615 | tlb_flush_page (env, addr); |
616 | addr += TARGET_PAGE_SIZE; | |
617 | } | |
618 | } | |
2ee4aed8 | 619 | } |