[mirror_qemu.git] / target-mips / helper.c

/*
 *  MIPS emulation helpers for qemu.
 * 
 *  Copyright (c) 2004-2005 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"

/* MIPS32 4K MMU emulation */
#ifdef MIPS_USES_R4K_TLB
static int map_address (CPUState *env, target_ulong *physical, int *prot,
                        target_ulong address, int rw, int access_type)
{
    tlb_t *tlb;
    target_ulong tag;
    uint8_t ASID;
    int i, n;
    int ret;

    ret = -2;
    tag = (address & 0xFFFFE000);
    ASID = env->CP0_EntryHi & 0x000000FF;
    for (i = 0; i < MIPS_TLB_NB; i++) {
        tlb = &env->tlb[i];
        /* Check ASID, virtual page number & size */
        if ((tlb->G == 1 || tlb->ASID == ASID) &&
            tlb->VPN == tag && address < tlb->end2) {
            /* TLB match */
            n = (address >> 12) & 1;
            /* Check access rights */
            if ((tlb->V[n] & 2) && (rw == 0 || (tlb->D[n] & 4))) {
                *physical = tlb->PFN[n] | (address & 0xFFF);
                *prot = PAGE_READ;
                if (tlb->D[n])
                    *prot |= PAGE_WRITE;
                return 0;
            } else if (!(tlb->V[n] & 2)) {
                return -3;
            } else {
                return -4;
            }
        }
    }

    return ret;
}
#endif

int get_physical_address (CPUState *env, target_ulong *physical, int *prot,
                          target_ulong address, int rw, int access_type)
{
    int user_mode;
    int ret;

    /* User mode can only access useg */
    user_mode = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) ? 1 : 0;
#if 0
    if (logfile) {
        fprintf(logfile, "user mode %d h %08x\n",
                user_mode, env->hflags);
    }
#endif
    if (user_mode && address > 0x7FFFFFFFUL)
        return -1;
    ret = 0;
    if (address < 0x80000000UL) {
        if (!(env->hflags & MIPS_HFLAG_ERL)) {
#ifdef MIPS_USES_R4K_TLB
            ret = map_address(env, physical, prot, address, rw, access_type);
#else
            *physical = address + 0x40000000UL;
            *prot = PAGE_READ | PAGE_WRITE;
#endif
        } else {
            *physical = address;
            *prot = PAGE_READ | PAGE_WRITE;
        }
    } else if (address < 0xA0000000UL) {
        /* kseg0 */
        /* XXX: check supervisor mode */
        *physical = address - 0x80000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < 0xC0000000UL) {
        /* kseg1 */
        /* XXX: check supervisor mode */
        *physical = address - 0xA0000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < 0xE0000000UL) {
        /* kseg2 */
#ifdef MIPS_USES_R4K_TLB
        ret = map_address(env, physical, prot, address, rw, access_type);
#else
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
#endif
    } else {
        /* kseg3 */
        /* XXX: check supervisor mode */
        /* XXX: debug segment is not emulated */
#ifdef MIPS_USES_R4K_TLB
        ret = map_address(env, physical, prot, address, rw, access_type);
#else
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
#endif
    }
#if 0
    if (logfile) {
        fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
                access_type, *physical, *prot, ret);
    }
#endif

    return ret;
}

#if defined(CONFIG_USER_ONLY) 
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    target_ulong phys_addr;
    int prot;

    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
        return -1;
    return phys_addr;
}

void cpu_mips_init_mmu (CPUState *env)
{
}
#endif /* !defined(CONFIG_USER_ONLY) */

int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int is_user, int is_softmmu)
{
    target_ulong physical;
    int prot;
    int exception = 0, error_code = 0;
    int access_type;
    int ret = 0;

    if (logfile) {
#if 0
        cpu_dump_state(env, logfile, fprintf, 0);
#endif
        fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
                __func__, env->PC, address, rw, is_user, is_softmmu);
    }

    rw &= 1;

    /* data access */
    /* XXX: put correct access by using cpu_restore_state()
       correctly */
    access_type = ACCESS_INT;
    if (env->user_mode_only) {
        /* user mode only emulation */
        ret = -2;
        goto do_fault;
    }
    ret = get_physical_address(env, &physical, &prot,
                               address, rw, access_type);
    if (logfile) {
        fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
                __func__, address, ret, physical, prot);
    }
    if (ret == 0) {
	ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot,
			   is_user, is_softmmu);
    } else if (ret < 0) {
    do_fault:
        switch (ret) {
        default:
        case -1:
            /* Reference to kernel address from user mode or supervisor mode */
            /* Reference to supervisor address from user mode */
            if (rw)
                exception = EXCP_AdES;
            else
                exception = EXCP_AdEL;
            break;
        case -2:
            /* No TLB match for a mapped address */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            error_code = 1;
            break;
        case -3:
            /* TLB match with no valid bit */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            error_code = 0;
            break;
        case -4:
            /* TLB match but 'D' bit is cleared */
            exception = EXCP_LTLBL;
            break;
                
        }
        /* Raise exception */
        env->CP0_BadVAddr = address;
        env->CP0_Context = (env->CP0_Context & 0xff800000) |
	                   ((address >> 9) &   0x007ffff0);
        env->CP0_EntryHi =
            (env->CP0_EntryHi & 0x000000FF) | (address & 0xFFFFF000);
        env->exception_index = exception;
        env->error_code = error_code;
        ret = 1;
    }

    return ret;
}

void do_interrupt (CPUState *env)
{
    target_ulong pc, offset;
    int cause = -1;

    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
                __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
    }
    if (env->exception_index == EXCP_EXT_INTERRUPT &&
        (env->hflags & MIPS_HFLAG_DM))
        env->exception_index = EXCP_DINT;
    offset = 0x180;
    switch (env->exception_index) {
    case EXCP_DSS:
        env->CP0_Debug |= 1 << CP0DB_DSS;
        /* Debug single step cannot be raised inside a delay slot and
         * resume will always occur on the next instruction
         * (but we assume the pc has always been updated during
         *  code translation).
         */
        env->CP0_DEPC = env->PC;
        goto enter_debug_mode;
    case EXCP_DINT:
        env->CP0_Debug |= 1 << CP0DB_DINT;
        goto set_DEPC;
    case EXCP_DIB:
        env->CP0_Debug |= 1 << CP0DB_DIB;
        goto set_DEPC;
    case EXCP_DBp:
        env->CP0_Debug |= 1 << CP0DB_DBp;
        goto set_DEPC;
    case EXCP_DDBS:
        env->CP0_Debug |= 1 << CP0DB_DDBS;
        goto set_DEPC;
    case EXCP_DDBL:
        env->CP0_Debug |= 1 << CP0DB_DDBL;
        goto set_DEPC;
    set_DEPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
             * come back to the jump
             */
            env->CP0_DEPC = env->PC - 4;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_DEPC = env->PC;
        }
    enter_debug_mode:
        env->hflags |= MIPS_HFLAG_DM;
        /* EJTAG probe trap enable is not implemented... */
        pc = 0xBFC00480;
        break;
    case EXCP_RESET:
#ifdef MIPS_USES_R4K_TLB
        env->CP0_random = MIPS_TLB_NB - 1;
#endif
        env->CP0_Wired = 0;
        env->CP0_Config0 = MIPS_CONFIG0;
#if defined (MIPS_CONFIG1)
        env->CP0_Config1 = MIPS_CONFIG1;
#endif
#if defined (MIPS_CONFIG2)
        env->CP0_Config2 = MIPS_CONFIG2;
#endif
#if defined (MIPS_CONFIG3)
        env->CP0_Config3 = MIPS_CONFIG3;
#endif
        env->CP0_WatchLo = 0;
        env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
        goto set_error_EPC;
    case EXCP_SRESET:
        env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
            (1 << CP0St_SR);
        env->CP0_WatchLo = 0;
        goto set_error_EPC;
    case EXCP_NMI:
        env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
            (1 << CP0St_NMI);
    set_error_EPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
             * come back to the jump
             */
            env->CP0_ErrorEPC = env->PC - 4;
        } else {
            env->CP0_ErrorEPC = env->PC;
        }
        env->hflags = MIPS_HFLAG_ERL;
        pc = 0xBFC00000;
        break;
    case EXCP_MCHECK:
        cause = 24;
        goto set_EPC;
    case EXCP_EXT_INTERRUPT:
        cause = 0;
        if (env->CP0_Cause & (1 << CP0Ca_IV))
            offset = 0x200;
        goto set_EPC;
    case EXCP_DWATCH:
        cause = 23;
        /* XXX: TODO: manage defered watch exceptions */
        goto set_EPC;
    case EXCP_AdEL:
    case EXCP_AdES:
        cause = 4;
        goto set_EPC;
    case EXCP_TLBL:
    case EXCP_TLBF:
        cause = 2;
        if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
            offset = 0x000;
        goto set_EPC;
    case EXCP_IBE:
        cause = 6;
        goto set_EPC;
    case EXCP_DBE:
        cause = 7;
        goto set_EPC;
    case EXCP_SYSCALL:
        cause = 8;
        goto set_EPC;
    case EXCP_BREAK:
        cause = 9;
        goto set_EPC;
    case EXCP_RI:
        cause = 10;
        goto set_EPC;
    case EXCP_CpU:
        cause = 11;
        env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
        goto set_EPC;
    case EXCP_OVERFLOW:
        cause = 12;
        goto set_EPC;
    case EXCP_TRAP:
        cause = 13;
        goto set_EPC;
    case EXCP_LTLBL:
        cause = 1;
        goto set_EPC;
    case EXCP_TLBS:
        cause = 3;
        if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
            offset = 0x000;
        goto set_EPC;
    set_EPC:
        if (env->CP0_Status & (1 << CP0St_BEV)) {
            pc = 0xBFC00200;
        } else {
            pc = 0x80000000;
        }
        env->hflags |= MIPS_HFLAG_EXL;
        pc += offset;
        env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
             * come back to the jump
             */
            env->CP0_EPC = env->PC - 4;
            env->CP0_Cause |= 0x80000000;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_EPC = env->PC;
            env->CP0_Cause &= ~0x80000000;
        }
        break;
    default:
        if (logfile) {
            fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
                    env->exception_index);
        }
        printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
        exit(1);
    }
    env->PC = pc;
    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
                "    S %08x C %08x A %08x D %08x\n",
                __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
                env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
                env->CP0_DEPC);
    }
    env->exception_index = EXCP_NONE;
}
Commit	Line	Data
6af0bf9c FB	1	/*
	2	* MIPS emulation helpers for qemu.
	3	*
	4	* Copyright (c) 2004-2005 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
e37e863f FB	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
6af0bf9c FB	30
6af0bf9c FB	31	/* MIPS32 4K MMU emulation */
9fb63ac2	32	#ifdef MIPS_USES_R4K_TLB
6af0bf9c FB	33	static int map_address (CPUState env, target_ulong physical, int *prot,
	34	target_ulong address, int rw, int access_type)
	35	{
	36	tlb_t *tlb;
	37	target_ulong tag;
	38	uint8_t ASID;
	39	int i, n;
	40	int ret;
	41
	42	ret = -2;
	43	tag = (address & 0xFFFFE000);
	44	ASID = env->CP0_EntryHi & 0x000000FF;
7a962d30	45	for (i = 0; i < MIPS_TLB_NB; i++) {
6af0bf9c FB	46	tlb = &env->tlb[i];
	47	/* Check ASID, virtual page number & size */
	48	if ((tlb->G == 1 \|\| tlb->ASID == ASID) &&
4ad40f36	49	tlb->VPN == tag && address < tlb->end2) {
6af0bf9c FB	50	/* TLB match */
	51	n = (address >> 12) & 1;
	52	/* Check access rights */
	53	if ((tlb->V[n] & 2) && (rw == 0 \|\| (tlb->D[n] & 4))) {
	54	*physical = tlb->PFN[n] \| (address & 0xFFF);
9fb63ac2	55	*prot = PAGE_READ;
6af0bf9c	56	if (tlb->D[n])
9fb63ac2	57	*prot \|= PAGE_WRITE;
6af0bf9c FB	58	return 0;
	59	} else if (!(tlb->V[n] & 2)) {
	60	return -3;
	61	} else {
	62	return -4;
	63	}
	64	}
	65	}
	66
	67	return ret;
	68	}
	69	#endif
	70
	71	int get_physical_address (CPUState env, target_ulong physical, int *prot,
	72	target_ulong address, int rw, int access_type)
	73	{
	74	int user_mode;
	75	int ret;
	76
	77	/* User mode can only access useg */
	78	user_mode = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) ? 1 : 0;
	79	#if 0
	80	if (logfile) {
	81	fprintf(logfile, "user mode %d h %08x\n",
	82	user_mode, env->hflags);
	83	}
	84	#endif
	85	if (user_mode && address > 0x7FFFFFFFUL)
	86	return -1;
	87	ret = 0;
	88	if (address < 0x80000000UL) {
9fb63ac2 FB	89	if (!(env->hflags & MIPS_HFLAG_ERL)) {
	90	#ifdef MIPS_USES_R4K_TLB
	91	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	92	#else
	93	*physical = address + 0x40000000UL;
	94	*prot = PAGE_READ \| PAGE_WRITE;
	95	#endif
	96	} else {
	97	*physical = address;
	98	*prot = PAGE_READ \| PAGE_WRITE;
	99	}
	100	} else if (address < 0xA0000000UL) {
	101	/* kseg0 */
	102	/* XXX: check supervisor mode */
	103	*physical = address - 0x80000000UL;
	104	*prot = PAGE_READ \| PAGE_WRITE;
	105	} else if (address < 0xC0000000UL) {
	106	/* kseg1 */
	107	/* XXX: check supervisor mode */
	108	*physical = address - 0xA0000000UL;
	109	*prot = PAGE_READ \| PAGE_WRITE;
	110	} else if (address < 0xE0000000UL) {
	111	/* kseg2 */
9fb63ac2 FB	112	#ifdef MIPS_USES_R4K_TLB
9fb63ac2 FB	113	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	114	#else
	115	*physical = address;
	116	*prot = PAGE_READ \| PAGE_WRITE;
	117	#endif
	118	} else {
	119	/* kseg3 */
	120	/* XXX: check supervisor mode */
	121	/* XXX: debug segment is not emulated */
9fb63ac2 FB	122	#ifdef MIPS_USES_R4K_TLB
9fb63ac2 FB	123	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	124	#else
	125	*physical = address;
	126	*prot = PAGE_READ \| PAGE_WRITE;
	127	#endif
	128	}
	129	#if 0
	130	if (logfile) {
	131	fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
	132	access_type, physical, prot, ret);
	133	}
	134	#endif
	135
	136	return ret;
	137	}
	138
	139	#if defined(CONFIG_USER_ONLY)
	140	target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
	141	{
	142	return addr;
	143	}
	144	#else
	145	target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
	146	{
	147	target_ulong phys_addr;
	148	int prot;
	149
	150	if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
	151	return -1;
	152	return phys_addr;
	153	}
6af0bf9c FB	154
	155	void cpu_mips_init_mmu (CPUState *env)
	156	{
	157	}
6af0bf9c FB	158	#endif /* !defined(CONFIG_USER_ONLY) */
	159
	160	int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
	161	int is_user, int is_softmmu)
	162	{
	163	target_ulong physical;
	164	int prot;
	165	int exception = 0, error_code = 0;
	166	int access_type;
	167	int ret = 0;
	168
	169	if (logfile) {
4ad40f36	170	#if 0
6af0bf9c	171	cpu_dump_state(env, logfile, fprintf, 0);
4ad40f36	172	#endif
6af0bf9c FB	173	fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
	174	__func__, env->PC, address, rw, is_user, is_softmmu);
	175	}
4ad40f36 FB	176
	177	rw &= 1;
	178
6af0bf9c FB	179	/* data access */
	180	/* XXX: put correct access by using cpu_restore_state()
	181	correctly */
	182	access_type = ACCESS_INT;
	183	if (env->user_mode_only) {
	184	/* user mode only emulation */
	185	ret = -2;
	186	goto do_fault;
	187	}
	188	ret = get_physical_address(env, &physical, &prot,
	189	address, rw, access_type);
	190	if (logfile) {
	191	fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
	192	__func__, address, ret, physical, prot);
	193	}
	194	if (ret == 0) {
	195	ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot,
	196	is_user, is_softmmu);
	197	} else if (ret < 0) {
	198	do_fault:
	199	switch (ret) {
	200	default:
	201	case -1:
	202	/* Reference to kernel address from user mode or supervisor mode */
	203	/* Reference to supervisor address from user mode */
	204	if (rw)
	205	exception = EXCP_AdES;
	206	else
	207	exception = EXCP_AdEL;
	208	break;
	209	case -2:
	210	/* No TLB match for a mapped address */
	211	if (rw)
	212	exception = EXCP_TLBS;
	213	else
	214	exception = EXCP_TLBL;
	215	error_code = 1;
	216	break;
	217	case -3:
	218	/* TLB match with no valid bit */
	219	if (rw)
	220	exception = EXCP_TLBS;
	221	else
	222	exception = EXCP_TLBL;
	223	error_code = 0;
	224	break;
	225	case -4:
	226	/* TLB match but 'D' bit is cleared */
	227	exception = EXCP_LTLBL;
	228	break;
	229
	230	}
6af0bf9c FB	231	/* Raise exception */
6af0bf9c FB	232	env->CP0_BadVAddr = address;
85498508	233	env->CP0_Context = (env->CP0_Context & 0xff800000) \|
4ad40f36	234	((address >> 9) & 0x007ffff0);
6af0bf9c	235	env->CP0_EntryHi =
85498508	236	(env->CP0_EntryHi & 0x000000FF) \| (address & 0xFFFFF000);
6af0bf9c FB	237	env->exception_index = exception;
	238	env->error_code = error_code;
	239	ret = 1;
	240	}
	241
	242	return ret;
	243	}
	244
	245	void do_interrupt (CPUState *env)
	246	{
	247	target_ulong pc, offset;
	248	int cause = -1;
	249
	250	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
	251	fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
	252	__func__, env->PC, env->CP0_EPC, cause, env->exception_index);
	253	}
	254	if (env->exception_index == EXCP_EXT_INTERRUPT &&
	255	(env->hflags & MIPS_HFLAG_DM))
	256	env->exception_index = EXCP_DINT;
	257	offset = 0x180;
	258	switch (env->exception_index) {
	259	case EXCP_DSS:
	260	env->CP0_Debug \|= 1 << CP0DB_DSS;
	261	/* Debug single step cannot be raised inside a delay slot and
	262	* resume will always occur on the next instruction
	263	* (but we assume the pc has always been updated during
	264	* code translation).
	265	*/
	266	env->CP0_DEPC = env->PC;
	267	goto enter_debug_mode;
	268	case EXCP_DINT:
	269	env->CP0_Debug \|= 1 << CP0DB_DINT;
	270	goto set_DEPC;
	271	case EXCP_DIB:
	272	env->CP0_Debug \|= 1 << CP0DB_DIB;
	273	goto set_DEPC;
	274	case EXCP_DBp:
	275	env->CP0_Debug \|= 1 << CP0DB_DBp;
	276	goto set_DEPC;
	277	case EXCP_DDBS:
	278	env->CP0_Debug \|= 1 << CP0DB_DDBS;
	279	goto set_DEPC;
	280	case EXCP_DDBL:
	281	env->CP0_Debug \|= 1 << CP0DB_DDBL;
	282	goto set_DEPC;
	283	set_DEPC:
4ad40f36	284	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c FB	285	/* If the exception was raised from a delay slot,
	286	* come back to the jump
	287	*/
	288	env->CP0_DEPC = env->PC - 4;
4ad40f36	289	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	290	} else {
	291	env->CP0_DEPC = env->PC;
	292	}
	293	enter_debug_mode:
	294	env->hflags \|= MIPS_HFLAG_DM;
	295	/* EJTAG probe trap enable is not implemented... */
	296	pc = 0xBFC00480;
	297	break;
	298	case EXCP_RESET:
9fb63ac2	299	#ifdef MIPS_USES_R4K_TLB
6af0bf9c FB	300	env->CP0_random = MIPS_TLB_NB - 1;
	301	#endif
	302	env->CP0_Wired = 0;
	303	env->CP0_Config0 = MIPS_CONFIG0;
	304	#if defined (MIPS_CONFIG1)
	305	env->CP0_Config1 = MIPS_CONFIG1;
	306	#endif
	307	#if defined (MIPS_CONFIG2)
	308	env->CP0_Config2 = MIPS_CONFIG2;
	309	#endif
	310	#if defined (MIPS_CONFIG3)
	311	env->CP0_Config3 = MIPS_CONFIG3;
	312	#endif
	313	env->CP0_WatchLo = 0;
	314	env->CP0_Status = (1 << CP0St_CU0) \| (1 << CP0St_BEV);
	315	goto set_error_EPC;
	316	case EXCP_SRESET:
	317	env->CP0_Status = (1 << CP0St_CU0) \| (1 << CP0St_BEV) \|
	318	(1 << CP0St_SR);
	319	env->CP0_WatchLo = 0;
	320	goto set_error_EPC;
	321	case EXCP_NMI:
	322	env->CP0_Status = (1 << CP0St_CU0) \| (1 << CP0St_BEV) \|
	323	(1 << CP0St_NMI);
	324	set_error_EPC:
4ad40f36	325	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c FB	326	/* If the exception was raised from a delay slot,
	327	* come back to the jump
	328	*/
	329	env->CP0_ErrorEPC = env->PC - 4;
	330	} else {
	331	env->CP0_ErrorEPC = env->PC;
	332	}
4ad40f36	333	env->hflags = MIPS_HFLAG_ERL;
6af0bf9c FB	334	pc = 0xBFC00000;
	335	break;
	336	case EXCP_MCHECK:
	337	cause = 24;
	338	goto set_EPC;
	339	case EXCP_EXT_INTERRUPT:
	340	cause = 0;
	341	if (env->CP0_Cause & (1 << CP0Ca_IV))
	342	offset = 0x200;
	343	goto set_EPC;
	344	case EXCP_DWATCH:
	345	cause = 23;
	346	/* XXX: TODO: manage defered watch exceptions */
	347	goto set_EPC;
	348	case EXCP_AdEL:
	349	case EXCP_AdES:
	350	cause = 4;
	351	goto set_EPC;
	352	case EXCP_TLBL:
	353	case EXCP_TLBF:
	354	cause = 2;
	355	if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
	356	offset = 0x000;
	357	goto set_EPC;
	358	case EXCP_IBE:
	359	cause = 6;
	360	goto set_EPC;
	361	case EXCP_DBE:
	362	cause = 7;
	363	goto set_EPC;
	364	case EXCP_SYSCALL:
	365	cause = 8;
	366	goto set_EPC;
	367	case EXCP_BREAK:
	368	cause = 9;
	369	goto set_EPC;
	370	case EXCP_RI:
	371	cause = 10;
	372	goto set_EPC;
	373	case EXCP_CpU:
	374	cause = 11;
4ad40f36	375	env->CP0_Cause = (env->CP0_Cause & ~0x03000000) \| (env->error_code << 28);
6af0bf9c FB	376	goto set_EPC;
	377	case EXCP_OVERFLOW:
	378	cause = 12;
	379	goto set_EPC;
	380	case EXCP_TRAP:
	381	cause = 13;
	382	goto set_EPC;
	383	case EXCP_LTLBL:
	384	cause = 1;
	385	goto set_EPC;
	386	case EXCP_TLBS:
	387	cause = 3;
0d8aca8c FB	388	if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
	389	offset = 0x000;
	390	goto set_EPC;
6af0bf9c FB	391	set_EPC:
	392	if (env->CP0_Status & (1 << CP0St_BEV)) {
	393	pc = 0xBFC00200;
	394	} else {
	395	pc = 0x80000000;
	396	}
	397	env->hflags \|= MIPS_HFLAG_EXL;
	398	pc += offset;
	399	env->CP0_Cause = (env->CP0_Cause & ~0x7C) \| (cause << 2);
4ad40f36	400	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c FB	401	/* If the exception was raised from a delay slot,
	402	* come back to the jump
	403	*/
	404	env->CP0_EPC = env->PC - 4;
	405	env->CP0_Cause \|= 0x80000000;
4ad40f36	406	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	407	} else {
	408	env->CP0_EPC = env->PC;
	409	env->CP0_Cause &= ~0x80000000;
	410	}
	411	break;
	412	default:
	413	if (logfile) {
	414	fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
	415	env->exception_index);
	416	}
	417	printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
	418	exit(1);
	419	}
	420	env->PC = pc;
	421	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
	422	fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
	423	" S %08x C %08x A %08x D %08x\n",
	424	__func__, env->PC, env->CP0_EPC, cause, env->exception_index,
	425	env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
	426	env->CP0_DEPC);
	427	}
	428	env->exception_index = EXCP_NONE;
	429	}