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Commit | Line | Data |
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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
e37e863f FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <signal.h> | |
26 | #include <assert.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
6af0bf9c | 30 | |
43057ab1 FB |
31 | enum { |
32 | TLBRET_DIRTY = -4, | |
33 | TLBRET_INVALID = -3, | |
34 | TLBRET_NOMATCH = -2, | |
35 | TLBRET_BADADDR = -1, | |
36 | TLBRET_MATCH = 0 | |
37 | }; | |
38 | ||
29929e34 TS |
39 | /* no MMU emulation */ |
40 | int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, | |
6af0bf9c | 41 | target_ulong address, int rw, int access_type) |
29929e34 TS |
42 | { |
43 | *physical = address; | |
44 | *prot = PAGE_READ | PAGE_WRITE; | |
45 | return TLBRET_MATCH; | |
46 | } | |
47 | ||
48 | /* fixed mapping MMU emulation */ | |
49 | int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, | |
50 | target_ulong address, int rw, int access_type) | |
51 | { | |
52 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
53 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
54 | *physical = address + 0x40000000UL; | |
55 | else | |
56 | *physical = address; | |
57 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
58 | *physical = address & 0x1FFFFFFF; | |
59 | else | |
60 | *physical = address; | |
61 | ||
62 | *prot = PAGE_READ | PAGE_WRITE; | |
63 | return TLBRET_MATCH; | |
64 | } | |
65 | ||
66 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
67 | int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, | |
68 | target_ulong address, int rw, int access_type) | |
6af0bf9c | 69 | { |
925fd0f2 | 70 | uint8_t ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 71 | int i; |
6af0bf9c | 72 | |
ead9360e TS |
73 | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
74 | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; | |
3b1c8be4 | 75 | /* 1k pages are not supported. */ |
f2e9ebef | 76 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 77 | target_ulong tag = address & ~mask; |
f2e9ebef | 78 | target_ulong VPN = tlb->VPN & ~mask; |
100ce988 | 79 | #ifdef TARGET_MIPS64 |
e034e2c3 | 80 | tag &= env->SEGMask; |
100ce988 | 81 | #endif |
3b1c8be4 | 82 | |
6af0bf9c | 83 | /* Check ASID, virtual page number & size */ |
f2e9ebef | 84 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
6af0bf9c | 85 | /* TLB match */ |
f2e9ebef | 86 | int n = !!(address & mask & ~(mask >> 1)); |
6af0bf9c | 87 | /* Check access rights */ |
f2e9ebef | 88 | if (!(n ? tlb->V1 : tlb->V0)) |
43057ab1 | 89 | return TLBRET_INVALID; |
f2e9ebef | 90 | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
3b1c8be4 | 91 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
9fb63ac2 | 92 | *prot = PAGE_READ; |
98c1b82b | 93 | if (n ? tlb->D1 : tlb->D0) |
9fb63ac2 | 94 | *prot |= PAGE_WRITE; |
43057ab1 | 95 | return TLBRET_MATCH; |
6af0bf9c | 96 | } |
43057ab1 | 97 | return TLBRET_DIRTY; |
6af0bf9c FB |
98 | } |
99 | } | |
43057ab1 | 100 | return TLBRET_NOMATCH; |
6af0bf9c | 101 | } |
6af0bf9c | 102 | |
43057ab1 FB |
103 | static int get_physical_address (CPUState *env, target_ulong *physical, |
104 | int *prot, target_ulong address, | |
105 | int rw, int access_type) | |
6af0bf9c | 106 | { |
b4ab4b4e | 107 | /* User mode can only access useg/xuseg */ |
43057ab1 | 108 | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
671880e6 TS |
109 | int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; |
110 | int kernel_mode = !user_mode && !supervisor_mode; | |
b4ab4b4e TS |
111 | #ifdef TARGET_MIPS64 |
112 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
113 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
114 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
115 | #endif | |
43057ab1 FB |
116 | int ret = TLBRET_MATCH; |
117 | ||
6af0bf9c FB |
118 | #if 0 |
119 | if (logfile) { | |
120 | fprintf(logfile, "user mode %d h %08x\n", | |
121 | user_mode, env->hflags); | |
122 | } | |
123 | #endif | |
b4ab4b4e | 124 | |
b4ab4b4e TS |
125 | if (address <= (int32_t)0x7FFFFFFFUL) { |
126 | /* useg */ | |
996ba2cc | 127 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
29929e34 | 128 | *physical = address & 0xFFFFFFFF; |
6af0bf9c | 129 | *prot = PAGE_READ | PAGE_WRITE; |
996ba2cc | 130 | } else { |
ead9360e | 131 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
6af0bf9c | 132 | } |
b4ab4b4e TS |
133 | #ifdef TARGET_MIPS64 |
134 | /* | |
135 | XXX: Assuming : | |
136 | - PABITS = 36 (correct for MIPS64R1) | |
b4ab4b4e TS |
137 | */ |
138 | } else if (address < 0x3FFFFFFFFFFFFFFFULL) { | |
139 | /* xuseg */ | |
e034e2c3 | 140 | if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
ead9360e | 141 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
b4ab4b4e TS |
142 | } else { |
143 | ret = TLBRET_BADADDR; | |
144 | } | |
145 | } else if (address < 0x7FFFFFFFFFFFFFFFULL) { | |
146 | /* xsseg */ | |
671880e6 TS |
147 | if ((supervisor_mode || kernel_mode) && |
148 | SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { | |
ead9360e | 149 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
b4ab4b4e TS |
150 | } else { |
151 | ret = TLBRET_BADADDR; | |
152 | } | |
153 | } else if (address < 0xBFFFFFFFFFFFFFFFULL) { | |
154 | /* xkphys */ | |
671880e6 TS |
155 | if (kernel_mode && KX && |
156 | (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) { | |
e034e2c3 | 157 | *physical = address & 0X0000000FFFFFFFFFULL; |
b4ab4b4e TS |
158 | *prot = PAGE_READ | PAGE_WRITE; |
159 | } else { | |
160 | ret = TLBRET_BADADDR; | |
161 | } | |
162 | } else if (address < 0xFFFFFFFF7FFFFFFFULL) { | |
163 | /* xkseg */ | |
671880e6 TS |
164 | if (kernel_mode && KX && |
165 | address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { | |
ead9360e | 166 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
b4ab4b4e TS |
167 | } else { |
168 | ret = TLBRET_BADADDR; | |
169 | } | |
170 | #endif | |
5dc4b744 | 171 | } else if (address < (int32_t)0xA0000000UL) { |
6af0bf9c | 172 | /* kseg0 */ |
671880e6 TS |
173 | if (kernel_mode) { |
174 | *physical = address - (int32_t)0x80000000UL; | |
175 | *prot = PAGE_READ | PAGE_WRITE; | |
176 | } else { | |
177 | ret = TLBRET_BADADDR; | |
178 | } | |
5dc4b744 | 179 | } else if (address < (int32_t)0xC0000000UL) { |
6af0bf9c | 180 | /* kseg1 */ |
671880e6 TS |
181 | if (kernel_mode) { |
182 | *physical = address - (int32_t)0xA0000000UL; | |
183 | *prot = PAGE_READ | PAGE_WRITE; | |
184 | } else { | |
185 | ret = TLBRET_BADADDR; | |
186 | } | |
5dc4b744 | 187 | } else if (address < (int32_t)0xE0000000UL) { |
671880e6 TS |
188 | /* sseg */ |
189 | if (supervisor_mode || kernel_mode) { | |
190 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
191 | } else { | |
192 | ret = TLBRET_BADADDR; | |
193 | } | |
6af0bf9c FB |
194 | } else { |
195 | /* kseg3 */ | |
6af0bf9c | 196 | /* XXX: debug segment is not emulated */ |
671880e6 TS |
197 | if (kernel_mode) { |
198 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
199 | } else { | |
200 | ret = TLBRET_BADADDR; | |
201 | } | |
6af0bf9c FB |
202 | } |
203 | #if 0 | |
204 | if (logfile) { | |
3594c774 | 205 | fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n", |
c570fd16 | 206 | address, rw, access_type, *physical, *prot, ret); |
6af0bf9c FB |
207 | } |
208 | #endif | |
209 | ||
210 | return ret; | |
211 | } | |
212 | ||
5fafdf24 | 213 | #if defined(CONFIG_USER_ONLY) |
9b3c35e0 | 214 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
6af0bf9c FB |
215 | { |
216 | return addr; | |
217 | } | |
218 | #else | |
9b3c35e0 | 219 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
6af0bf9c FB |
220 | { |
221 | target_ulong phys_addr; | |
222 | int prot; | |
223 | ||
224 | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) | |
225 | return -1; | |
226 | return phys_addr; | |
227 | } | |
6af0bf9c FB |
228 | |
229 | void cpu_mips_init_mmu (CPUState *env) | |
230 | { | |
231 | } | |
6af0bf9c FB |
232 | #endif /* !defined(CONFIG_USER_ONLY) */ |
233 | ||
234 | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | |
235 | int is_user, int is_softmmu) | |
236 | { | |
237 | target_ulong physical; | |
238 | int prot; | |
239 | int exception = 0, error_code = 0; | |
240 | int access_type; | |
241 | int ret = 0; | |
242 | ||
243 | if (logfile) { | |
4ad40f36 | 244 | #if 0 |
6af0bf9c | 245 | cpu_dump_state(env, logfile, fprintf, 0); |
4ad40f36 | 246 | #endif |
3594c774 | 247 | fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n", |
ead9360e | 248 | __func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu); |
6af0bf9c | 249 | } |
4ad40f36 FB |
250 | |
251 | rw &= 1; | |
252 | ||
6af0bf9c FB |
253 | /* data access */ |
254 | /* XXX: put correct access by using cpu_restore_state() | |
255 | correctly */ | |
256 | access_type = ACCESS_INT; | |
257 | if (env->user_mode_only) { | |
258 | /* user mode only emulation */ | |
43057ab1 | 259 | ret = TLBRET_NOMATCH; |
6af0bf9c FB |
260 | goto do_fault; |
261 | } | |
262 | ret = get_physical_address(env, &physical, &prot, | |
263 | address, rw, access_type); | |
264 | if (logfile) { | |
3594c774 | 265 | fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n", |
6af0bf9c FB |
266 | __func__, address, ret, physical, prot); |
267 | } | |
43057ab1 FB |
268 | if (ret == TLBRET_MATCH) { |
269 | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, | |
270 | physical & TARGET_PAGE_MASK, prot, | |
271 | is_user, is_softmmu); | |
6af0bf9c FB |
272 | } else if (ret < 0) { |
273 | do_fault: | |
274 | switch (ret) { | |
275 | default: | |
43057ab1 | 276 | case TLBRET_BADADDR: |
6af0bf9c FB |
277 | /* Reference to kernel address from user mode or supervisor mode */ |
278 | /* Reference to supervisor address from user mode */ | |
279 | if (rw) | |
280 | exception = EXCP_AdES; | |
281 | else | |
282 | exception = EXCP_AdEL; | |
283 | break; | |
43057ab1 | 284 | case TLBRET_NOMATCH: |
6af0bf9c FB |
285 | /* No TLB match for a mapped address */ |
286 | if (rw) | |
287 | exception = EXCP_TLBS; | |
288 | else | |
289 | exception = EXCP_TLBL; | |
290 | error_code = 1; | |
291 | break; | |
43057ab1 | 292 | case TLBRET_INVALID: |
6af0bf9c FB |
293 | /* TLB match with no valid bit */ |
294 | if (rw) | |
295 | exception = EXCP_TLBS; | |
296 | else | |
297 | exception = EXCP_TLBL; | |
6af0bf9c | 298 | break; |
43057ab1 | 299 | case TLBRET_DIRTY: |
6af0bf9c FB |
300 | /* TLB match but 'D' bit is cleared */ |
301 | exception = EXCP_LTLBL; | |
302 | break; | |
3b46e624 | 303 | |
6af0bf9c | 304 | } |
6af0bf9c FB |
305 | /* Raise exception */ |
306 | env->CP0_BadVAddr = address; | |
100ce988 | 307 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | |
4ad40f36 | 308 | ((address >> 9) & 0x007ffff0); |
6af0bf9c | 309 | env->CP0_EntryHi = |
43057ab1 | 310 | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
100ce988 | 311 | #ifdef TARGET_MIPS64 |
e034e2c3 TS |
312 | env->CP0_EntryHi &= env->SEGMask; |
313 | env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | | |
314 | ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) | | |
315 | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); | |
100ce988 | 316 | #endif |
6af0bf9c FB |
317 | env->exception_index = exception; |
318 | env->error_code = error_code; | |
319 | ret = 1; | |
320 | } | |
321 | ||
322 | return ret; | |
323 | } | |
324 | ||
ca7c2b1b TS |
325 | #if defined(CONFIG_USER_ONLY) |
326 | void do_interrupt (CPUState *env) | |
327 | { | |
328 | env->exception_index = EXCP_NONE; | |
329 | } | |
330 | #else | |
6af0bf9c FB |
331 | void do_interrupt (CPUState *env) |
332 | { | |
aa328add | 333 | target_ulong offset; |
6af0bf9c FB |
334 | int cause = -1; |
335 | ||
336 | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) { | |
3594c774 | 337 | fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n", |
ead9360e | 338 | __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index); |
6af0bf9c FB |
339 | } |
340 | if (env->exception_index == EXCP_EXT_INTERRUPT && | |
341 | (env->hflags & MIPS_HFLAG_DM)) | |
342 | env->exception_index = EXCP_DINT; | |
343 | offset = 0x180; | |
344 | switch (env->exception_index) { | |
345 | case EXCP_DSS: | |
346 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
347 | /* Debug single step cannot be raised inside a delay slot and | |
348 | * resume will always occur on the next instruction | |
349 | * (but we assume the pc has always been updated during | |
350 | * code translation). | |
351 | */ | |
ead9360e | 352 | env->CP0_DEPC = env->PC[env->current_tc]; |
6af0bf9c FB |
353 | goto enter_debug_mode; |
354 | case EXCP_DINT: | |
355 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
356 | goto set_DEPC; | |
357 | case EXCP_DIB: | |
358 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
359 | goto set_DEPC; | |
360 | case EXCP_DBp: | |
361 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
362 | goto set_DEPC; | |
363 | case EXCP_DDBS: | |
364 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
365 | goto set_DEPC; | |
366 | case EXCP_DDBL: | |
367 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
6af0bf9c | 368 | set_DEPC: |
4ad40f36 | 369 | if (env->hflags & MIPS_HFLAG_BMASK) { |
6af0bf9c | 370 | /* If the exception was raised from a delay slot, |
aa328add | 371 | come back to the jump. */ |
ead9360e | 372 | env->CP0_DEPC = env->PC[env->current_tc] - 4; |
4ad40f36 | 373 | env->hflags &= ~MIPS_HFLAG_BMASK; |
6af0bf9c | 374 | } else { |
ead9360e | 375 | env->CP0_DEPC = env->PC[env->current_tc]; |
6af0bf9c FB |
376 | } |
377 | enter_debug_mode: | |
08fa4bab | 378 | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
671880e6 | 379 | env->hflags &= ~(MIPS_HFLAG_SM | MIPS_HFLAG_UM); |
6af0bf9c | 380 | /* EJTAG probe trap enable is not implemented... */ |
0a6de750 TS |
381 | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
382 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
ead9360e | 383 | env->PC[env->current_tc] = (int32_t)0xBFC00480; |
6af0bf9c FB |
384 | break; |
385 | case EXCP_RESET: | |
aa328add TS |
386 | cpu_reset(env); |
387 | break; | |
6af0bf9c | 388 | case EXCP_SRESET: |
24c7b0e3 | 389 | env->CP0_Status |= (1 << CP0St_SR); |
fd88b6ab | 390 | memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); |
6af0bf9c FB |
391 | goto set_error_EPC; |
392 | case EXCP_NMI: | |
24c7b0e3 | 393 | env->CP0_Status |= (1 << CP0St_NMI); |
6af0bf9c | 394 | set_error_EPC: |
4ad40f36 | 395 | if (env->hflags & MIPS_HFLAG_BMASK) { |
6af0bf9c | 396 | /* If the exception was raised from a delay slot, |
aa328add | 397 | come back to the jump. */ |
ead9360e | 398 | env->CP0_ErrorEPC = env->PC[env->current_tc] - 4; |
ecd78a0a | 399 | env->hflags &= ~MIPS_HFLAG_BMASK; |
6af0bf9c | 400 | } else { |
ead9360e | 401 | env->CP0_ErrorEPC = env->PC[env->current_tc]; |
6af0bf9c | 402 | } |
24c7b0e3 | 403 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
08fa4bab | 404 | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
671880e6 | 405 | env->hflags &= ~(MIPS_HFLAG_SM | MIPS_HFLAG_UM); |
0a6de750 TS |
406 | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
407 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
ead9360e | 408 | env->PC[env->current_tc] = (int32_t)0xBFC00000; |
6af0bf9c FB |
409 | break; |
410 | case EXCP_MCHECK: | |
411 | cause = 24; | |
412 | goto set_EPC; | |
413 | case EXCP_EXT_INTERRUPT: | |
414 | cause = 0; | |
415 | if (env->CP0_Cause & (1 << CP0Ca_IV)) | |
416 | offset = 0x200; | |
417 | goto set_EPC; | |
418 | case EXCP_DWATCH: | |
419 | cause = 23; | |
420 | /* XXX: TODO: manage defered watch exceptions */ | |
421 | goto set_EPC; | |
422 | case EXCP_AdEL: | |
6af0bf9c FB |
423 | cause = 4; |
424 | goto set_EPC; | |
beb811bd TS |
425 | case EXCP_AdES: |
426 | cause = 5; | |
427 | goto set_EPC; | |
6af0bf9c | 428 | case EXCP_TLBL: |
6af0bf9c | 429 | cause = 2; |
100ce988 TS |
430 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
431 | #ifdef TARGET_MIPS64 | |
432 | int R = env->CP0_BadVAddr >> 62; | |
433 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
434 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
435 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
436 | ||
437 | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) | |
438 | offset = 0x080; | |
439 | else | |
440 | #endif | |
441 | offset = 0x000; | |
442 | } | |
6af0bf9c FB |
443 | goto set_EPC; |
444 | case EXCP_IBE: | |
445 | cause = 6; | |
446 | goto set_EPC; | |
447 | case EXCP_DBE: | |
448 | cause = 7; | |
449 | goto set_EPC; | |
450 | case EXCP_SYSCALL: | |
451 | cause = 8; | |
452 | goto set_EPC; | |
453 | case EXCP_BREAK: | |
454 | cause = 9; | |
455 | goto set_EPC; | |
456 | case EXCP_RI: | |
457 | cause = 10; | |
458 | goto set_EPC; | |
459 | case EXCP_CpU: | |
460 | cause = 11; | |
39d51eb8 TS |
461 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
462 | (env->error_code << CP0Ca_CE); | |
6af0bf9c FB |
463 | goto set_EPC; |
464 | case EXCP_OVERFLOW: | |
465 | cause = 12; | |
466 | goto set_EPC; | |
467 | case EXCP_TRAP: | |
468 | cause = 13; | |
469 | goto set_EPC; | |
5a5012ec TS |
470 | case EXCP_FPE: |
471 | cause = 15; | |
472 | goto set_EPC; | |
6af0bf9c FB |
473 | case EXCP_LTLBL: |
474 | cause = 1; | |
475 | goto set_EPC; | |
476 | case EXCP_TLBS: | |
477 | cause = 3; | |
ead9360e TS |
478 | goto set_EPC; |
479 | case EXCP_THREAD: | |
480 | cause = 25; | |
100ce988 TS |
481 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
482 | #ifdef TARGET_MIPS64 | |
483 | int R = env->CP0_BadVAddr >> 62; | |
484 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
485 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
486 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
487 | ||
488 | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) | |
489 | offset = 0x080; | |
490 | else | |
491 | #endif | |
492 | offset = 0x000; | |
493 | } | |
6af0bf9c | 494 | set_EPC: |
24c7b0e3 TS |
495 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
496 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
497 | /* If the exception was raised from a delay slot, | |
498 | come back to the jump. */ | |
ead9360e | 499 | env->CP0_EPC = env->PC[env->current_tc] - 4; |
39d51eb8 | 500 | env->CP0_Cause |= (1 << CP0Ca_BD); |
24c7b0e3 | 501 | } else { |
ead9360e | 502 | env->CP0_EPC = env->PC[env->current_tc]; |
24c7b0e3 TS |
503 | env->CP0_Cause &= ~(1 << CP0Ca_BD); |
504 | } | |
24c7b0e3 | 505 | env->CP0_Status |= (1 << CP0St_EXL); |
08fa4bab | 506 | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
671880e6 | 507 | env->hflags &= ~(MIPS_HFLAG_SM | MIPS_HFLAG_UM); |
6af0bf9c | 508 | } |
c53f4a62 | 509 | env->hflags &= ~MIPS_HFLAG_BMASK; |
aa328add | 510 | if (env->CP0_Status & (1 << CP0St_BEV)) { |
ead9360e | 511 | env->PC[env->current_tc] = (int32_t)0xBFC00200; |
aa328add | 512 | } else { |
ead9360e | 513 | env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff); |
aa328add | 514 | } |
ead9360e | 515 | env->PC[env->current_tc] += offset; |
e58c8ba5 | 516 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
6af0bf9c FB |
517 | break; |
518 | default: | |
519 | if (logfile) { | |
520 | fprintf(logfile, "Invalid MIPS exception %d. Exiting\n", | |
521 | env->exception_index); | |
522 | } | |
523 | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); | |
524 | exit(1); | |
525 | } | |
6af0bf9c | 526 | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) { |
3594c774 TS |
527 | fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n" |
528 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", | |
ead9360e | 529 | __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index, |
6af0bf9c FB |
530 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
531 | env->CP0_DEPC); | |
532 | } | |
533 | env->exception_index = EXCP_NONE; | |
534 | } | |
ca7c2b1b | 535 | #endif /* !defined(CONFIG_USER_ONLY) */ |
2ee4aed8 | 536 | |
29929e34 | 537 | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) |
2ee4aed8 | 538 | { |
29929e34 | 539 | r4k_tlb_t *tlb; |
3b1c8be4 TS |
540 | target_ulong addr; |
541 | target_ulong end; | |
542 | uint8_t ASID = env->CP0_EntryHi & 0xFF; | |
543 | target_ulong mask; | |
2ee4aed8 | 544 | |
ead9360e | 545 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 546 | /* The qemu TLB is flushed when the ASID changes, so no need to |
2ee4aed8 FB |
547 | flush these entries again. */ |
548 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
549 | return; | |
550 | } | |
551 | ||
ead9360e | 552 | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { |
2ee4aed8 FB |
553 | /* For tlbwr, we can shadow the discarded entry into |
554 | a new (fake) TLB entry, as long as the guest can not | |
555 | tell that it's there. */ | |
ead9360e TS |
556 | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
557 | env->tlb->tlb_in_use++; | |
2ee4aed8 FB |
558 | return; |
559 | } | |
560 | ||
3b1c8be4 | 561 | /* 1k pages are not supported. */ |
f2e9ebef | 562 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 563 | if (tlb->V0) { |
f2e9ebef | 564 | addr = tlb->VPN & ~mask; |
100ce988 | 565 | #ifdef TARGET_MIPS64 |
e034e2c3 | 566 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
567 | addr |= 0x3FFFFF0000000000ULL; |
568 | } | |
569 | #endif | |
3b1c8be4 TS |
570 | end = addr | (mask >> 1); |
571 | while (addr < end) { | |
572 | tlb_flush_page (env, addr); | |
573 | addr += TARGET_PAGE_SIZE; | |
574 | } | |
575 | } | |
576 | if (tlb->V1) { | |
f2e9ebef | 577 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
100ce988 | 578 | #ifdef TARGET_MIPS64 |
e034e2c3 | 579 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
580 | addr |= 0x3FFFFF0000000000ULL; |
581 | } | |
582 | #endif | |
3b1c8be4 TS |
583 | end = addr | mask; |
584 | while (addr < end) { | |
585 | tlb_flush_page (env, addr); | |
586 | addr += TARGET_PAGE_SIZE; | |
587 | } | |
588 | } | |
2ee4aed8 | 589 | } |