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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
6af0bf9c | 18 | */ |
e37e863f FB |
19 | #include <stdarg.h> |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
e37e863f FB |
24 | |
25 | #include "cpu.h" | |
4ef37e69 | 26 | #include "sysemu/kvm.h" |
aea14095 | 27 | #include "exec/cpu_ldst.h" |
6af0bf9c | 28 | |
43057ab1 | 29 | enum { |
2fb58b73 LA |
30 | TLBRET_XI = -6, |
31 | TLBRET_RI = -5, | |
43057ab1 FB |
32 | TLBRET_DIRTY = -4, |
33 | TLBRET_INVALID = -3, | |
34 | TLBRET_NOMATCH = -2, | |
35 | TLBRET_BADADDR = -1, | |
36 | TLBRET_MATCH = 0 | |
37 | }; | |
38 | ||
3c7b48b7 PB |
39 | #if !defined(CONFIG_USER_ONLY) |
40 | ||
29929e34 | 41 | /* no MMU emulation */ |
a8170e5e | 42 | int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
6af0bf9c | 43 | target_ulong address, int rw, int access_type) |
29929e34 TS |
44 | { |
45 | *physical = address; | |
46 | *prot = PAGE_READ | PAGE_WRITE; | |
47 | return TLBRET_MATCH; | |
48 | } | |
49 | ||
50 | /* fixed mapping MMU emulation */ | |
a8170e5e | 51 | int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 TS |
52 | target_ulong address, int rw, int access_type) |
53 | { | |
54 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
55 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
56 | *physical = address + 0x40000000UL; | |
57 | else | |
58 | *physical = address; | |
59 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
60 | *physical = address & 0x1FFFFFFF; | |
61 | else | |
62 | *physical = address; | |
63 | ||
64 | *prot = PAGE_READ | PAGE_WRITE; | |
65 | return TLBRET_MATCH; | |
66 | } | |
67 | ||
68 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
a8170e5e | 69 | int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 70 | target_ulong address, int rw, int access_type) |
6af0bf9c | 71 | { |
925fd0f2 | 72 | uint8_t ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 73 | int i; |
6af0bf9c | 74 | |
ead9360e | 75 | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
c227f099 | 76 | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; |
3b1c8be4 | 77 | /* 1k pages are not supported. */ |
f2e9ebef | 78 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 79 | target_ulong tag = address & ~mask; |
f2e9ebef | 80 | target_ulong VPN = tlb->VPN & ~mask; |
d26bc211 | 81 | #if defined(TARGET_MIPS64) |
e034e2c3 | 82 | tag &= env->SEGMask; |
100ce988 | 83 | #endif |
3b1c8be4 | 84 | |
6af0bf9c | 85 | /* Check ASID, virtual page number & size */ |
9456c2fb | 86 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) { |
6af0bf9c | 87 | /* TLB match */ |
f2e9ebef | 88 | int n = !!(address & mask & ~(mask >> 1)); |
6af0bf9c | 89 | /* Check access rights */ |
2fb58b73 | 90 | if (!(n ? tlb->V1 : tlb->V0)) { |
43057ab1 | 91 | return TLBRET_INVALID; |
2fb58b73 LA |
92 | } |
93 | if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) { | |
94 | return TLBRET_XI; | |
95 | } | |
96 | if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) { | |
97 | return TLBRET_RI; | |
98 | } | |
9f6bcedb | 99 | if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { |
3b1c8be4 | 100 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
9fb63ac2 | 101 | *prot = PAGE_READ; |
98c1b82b | 102 | if (n ? tlb->D1 : tlb->D0) |
9fb63ac2 | 103 | *prot |= PAGE_WRITE; |
43057ab1 | 104 | return TLBRET_MATCH; |
6af0bf9c | 105 | } |
43057ab1 | 106 | return TLBRET_DIRTY; |
6af0bf9c FB |
107 | } |
108 | } | |
43057ab1 | 109 | return TLBRET_NOMATCH; |
6af0bf9c | 110 | } |
6af0bf9c | 111 | |
a8170e5e | 112 | static int get_physical_address (CPUMIPSState *env, hwaddr *physical, |
4ef37e69 | 113 | int *prot, target_ulong real_address, |
43057ab1 | 114 | int rw, int access_type) |
6af0bf9c | 115 | { |
b4ab4b4e | 116 | /* User mode can only access useg/xuseg */ |
43057ab1 | 117 | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
671880e6 TS |
118 | int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; |
119 | int kernel_mode = !user_mode && !supervisor_mode; | |
d26bc211 | 120 | #if defined(TARGET_MIPS64) |
b4ab4b4e TS |
121 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
122 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
123 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
124 | #endif | |
43057ab1 | 125 | int ret = TLBRET_MATCH; |
4ef37e69 JH |
126 | /* effective address (modified for KVM T&E kernel segments) */ |
127 | target_ulong address = real_address; | |
43057ab1 | 128 | |
22010ce7 JH |
129 | #define USEG_LIMIT 0x7FFFFFFFUL |
130 | #define KSEG0_BASE 0x80000000UL | |
131 | #define KSEG1_BASE 0xA0000000UL | |
132 | #define KSEG2_BASE 0xC0000000UL | |
133 | #define KSEG3_BASE 0xE0000000UL | |
134 | ||
4ef37e69 JH |
135 | #define KVM_KSEG0_BASE 0x40000000UL |
136 | #define KVM_KSEG2_BASE 0x60000000UL | |
137 | ||
138 | if (kvm_enabled()) { | |
139 | /* KVM T&E adds guest kernel segments in useg */ | |
140 | if (real_address >= KVM_KSEG0_BASE) { | |
141 | if (real_address < KVM_KSEG2_BASE) { | |
142 | /* kseg0 */ | |
143 | address += KSEG0_BASE - KVM_KSEG0_BASE; | |
144 | } else if (real_address <= USEG_LIMIT) { | |
145 | /* kseg2/3 */ | |
146 | address += KSEG2_BASE - KVM_KSEG2_BASE; | |
147 | } | |
148 | } | |
149 | } | |
150 | ||
22010ce7 | 151 | if (address <= USEG_LIMIT) { |
b4ab4b4e | 152 | /* useg */ |
996ba2cc | 153 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
29929e34 | 154 | *physical = address & 0xFFFFFFFF; |
6af0bf9c | 155 | *prot = PAGE_READ | PAGE_WRITE; |
996ba2cc | 156 | } else { |
4ef37e69 | 157 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6af0bf9c | 158 | } |
d26bc211 | 159 | #if defined(TARGET_MIPS64) |
89fc88da | 160 | } else if (address < 0x4000000000000000ULL) { |
b4ab4b4e | 161 | /* xuseg */ |
6958549d | 162 | if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
4ef37e69 | 163 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
164 | } else { |
165 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 166 | } |
89fc88da | 167 | } else if (address < 0x8000000000000000ULL) { |
b4ab4b4e | 168 | /* xsseg */ |
6958549d AJ |
169 | if ((supervisor_mode || kernel_mode) && |
170 | SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { | |
4ef37e69 | 171 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
172 | } else { |
173 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 174 | } |
89fc88da | 175 | } else if (address < 0xC000000000000000ULL) { |
b4ab4b4e | 176 | /* xkphys */ |
671880e6 | 177 | if (kernel_mode && KX && |
6d35524c TS |
178 | (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { |
179 | *physical = address & env->PAMask; | |
b4ab4b4e | 180 | *prot = PAGE_READ | PAGE_WRITE; |
6958549d AJ |
181 | } else { |
182 | ret = TLBRET_BADADDR; | |
183 | } | |
89fc88da | 184 | } else if (address < 0xFFFFFFFF80000000ULL) { |
b4ab4b4e | 185 | /* xkseg */ |
6958549d AJ |
186 | if (kernel_mode && KX && |
187 | address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { | |
4ef37e69 | 188 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
189 | } else { |
190 | ret = TLBRET_BADADDR; | |
191 | } | |
b4ab4b4e | 192 | #endif |
22010ce7 | 193 | } else if (address < (int32_t)KSEG1_BASE) { |
6af0bf9c | 194 | /* kseg0 */ |
671880e6 | 195 | if (kernel_mode) { |
22010ce7 | 196 | *physical = address - (int32_t)KSEG0_BASE; |
671880e6 TS |
197 | *prot = PAGE_READ | PAGE_WRITE; |
198 | } else { | |
199 | ret = TLBRET_BADADDR; | |
200 | } | |
22010ce7 | 201 | } else if (address < (int32_t)KSEG2_BASE) { |
6af0bf9c | 202 | /* kseg1 */ |
671880e6 | 203 | if (kernel_mode) { |
22010ce7 | 204 | *physical = address - (int32_t)KSEG1_BASE; |
671880e6 TS |
205 | *prot = PAGE_READ | PAGE_WRITE; |
206 | } else { | |
207 | ret = TLBRET_BADADDR; | |
208 | } | |
22010ce7 | 209 | } else if (address < (int32_t)KSEG3_BASE) { |
89fc88da | 210 | /* sseg (kseg2) */ |
671880e6 | 211 | if (supervisor_mode || kernel_mode) { |
4ef37e69 | 212 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
671880e6 TS |
213 | } else { |
214 | ret = TLBRET_BADADDR; | |
215 | } | |
6af0bf9c FB |
216 | } else { |
217 | /* kseg3 */ | |
6af0bf9c | 218 | /* XXX: debug segment is not emulated */ |
671880e6 | 219 | if (kernel_mode) { |
4ef37e69 | 220 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
671880e6 TS |
221 | } else { |
222 | ret = TLBRET_BADADDR; | |
223 | } | |
6af0bf9c | 224 | } |
6af0bf9c FB |
225 | return ret; |
226 | } | |
932e71cd | 227 | #endif |
6af0bf9c | 228 | |
7db13fae | 229 | static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, |
1147e189 AJ |
230 | int rw, int tlb_error) |
231 | { | |
27103424 | 232 | CPUState *cs = CPU(mips_env_get_cpu(env)); |
1147e189 AJ |
233 | int exception = 0, error_code = 0; |
234 | ||
aea14095 LA |
235 | if (rw == MMU_INST_FETCH) { |
236 | error_code |= EXCP_INST_NOTAVAIL; | |
237 | } | |
238 | ||
1147e189 AJ |
239 | switch (tlb_error) { |
240 | default: | |
241 | case TLBRET_BADADDR: | |
242 | /* Reference to kernel address from user mode or supervisor mode */ | |
243 | /* Reference to supervisor address from user mode */ | |
9f6bcedb | 244 | if (rw == MMU_DATA_STORE) { |
1147e189 | 245 | exception = EXCP_AdES; |
9f6bcedb | 246 | } else { |
1147e189 | 247 | exception = EXCP_AdEL; |
9f6bcedb | 248 | } |
1147e189 AJ |
249 | break; |
250 | case TLBRET_NOMATCH: | |
251 | /* No TLB match for a mapped address */ | |
9f6bcedb | 252 | if (rw == MMU_DATA_STORE) { |
1147e189 | 253 | exception = EXCP_TLBS; |
9f6bcedb | 254 | } else { |
1147e189 | 255 | exception = EXCP_TLBL; |
9f6bcedb | 256 | } |
aea14095 | 257 | error_code |= EXCP_TLB_NOMATCH; |
1147e189 AJ |
258 | break; |
259 | case TLBRET_INVALID: | |
260 | /* TLB match with no valid bit */ | |
9f6bcedb | 261 | if (rw == MMU_DATA_STORE) { |
1147e189 | 262 | exception = EXCP_TLBS; |
9f6bcedb | 263 | } else { |
1147e189 | 264 | exception = EXCP_TLBL; |
9f6bcedb | 265 | } |
1147e189 AJ |
266 | break; |
267 | case TLBRET_DIRTY: | |
268 | /* TLB match but 'D' bit is cleared */ | |
269 | exception = EXCP_LTLBL; | |
270 | break; | |
92ceb440 LA |
271 | case TLBRET_XI: |
272 | /* Execute-Inhibit Exception */ | |
273 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { | |
274 | exception = EXCP_TLBXI; | |
275 | } else { | |
276 | exception = EXCP_TLBL; | |
277 | } | |
278 | break; | |
279 | case TLBRET_RI: | |
280 | /* Read-Inhibit Exception */ | |
281 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { | |
282 | exception = EXCP_TLBRI; | |
283 | } else { | |
284 | exception = EXCP_TLBL; | |
285 | } | |
286 | break; | |
1147e189 AJ |
287 | } |
288 | /* Raise exception */ | |
289 | env->CP0_BadVAddr = address; | |
290 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | | |
291 | ((address >> 9) & 0x007ffff0); | |
292 | env->CP0_EntryHi = | |
293 | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); | |
294 | #if defined(TARGET_MIPS64) | |
295 | env->CP0_EntryHi &= env->SEGMask; | |
60270f85 YK |
296 | env->CP0_XContext = |
297 | /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | | |
298 | /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | | |
299 | /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4); | |
1147e189 | 300 | #endif |
27103424 | 301 | cs->exception_index = exception; |
1147e189 AJ |
302 | env->error_code = error_code; |
303 | } | |
304 | ||
4fcc562b | 305 | #if !defined(CONFIG_USER_ONLY) |
00b941e5 | 306 | hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
6af0bf9c | 307 | { |
00b941e5 | 308 | MIPSCPU *cpu = MIPS_CPU(cs); |
a8170e5e | 309 | hwaddr phys_addr; |
932e71cd | 310 | int prot; |
6af0bf9c | 311 | |
00b941e5 AF |
312 | if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, |
313 | ACCESS_INT) != 0) { | |
932e71cd | 314 | return -1; |
00b941e5 | 315 | } |
932e71cd | 316 | return phys_addr; |
6af0bf9c | 317 | } |
4fcc562b | 318 | #endif |
6af0bf9c | 319 | |
7510454e AF |
320 | int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, |
321 | int mmu_idx) | |
6af0bf9c | 322 | { |
7510454e AF |
323 | MIPSCPU *cpu = MIPS_CPU(cs); |
324 | CPUMIPSState *env = &cpu->env; | |
932e71cd | 325 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 326 | hwaddr physical; |
6af0bf9c | 327 | int prot; |
6af0bf9c | 328 | int access_type; |
99e43d36 | 329 | #endif |
6af0bf9c FB |
330 | int ret = 0; |
331 | ||
4ad40f36 | 332 | #if 0 |
7510454e | 333 | log_cpu_state(cs, 0); |
4ad40f36 | 334 | #endif |
339aaf5b AP |
335 | qemu_log_mask(CPU_LOG_MMU, |
336 | "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", | |
97b348e7 | 337 | __func__, env->active_tc.PC, address, rw, mmu_idx); |
4ad40f36 | 338 | |
6af0bf9c | 339 | /* data access */ |
99e43d36 | 340 | #if !defined(CONFIG_USER_ONLY) |
6af0bf9c FB |
341 | /* XXX: put correct access by using cpu_restore_state() |
342 | correctly */ | |
343 | access_type = ACCESS_INT; | |
6af0bf9c FB |
344 | ret = get_physical_address(env, &physical, &prot, |
345 | address, rw, access_type); | |
339aaf5b AP |
346 | qemu_log_mask(CPU_LOG_MMU, |
347 | "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx | |
7510454e AF |
348 | " prot %d\n", |
349 | __func__, address, ret, physical, prot); | |
43057ab1 | 350 | if (ret == TLBRET_MATCH) { |
0c591eb0 | 351 | tlb_set_page(cs, address & TARGET_PAGE_MASK, |
99e43d36 AJ |
352 | physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, |
353 | mmu_idx, TARGET_PAGE_SIZE); | |
354 | ret = 0; | |
932e71cd AJ |
355 | } else if (ret < 0) |
356 | #endif | |
357 | { | |
1147e189 | 358 | raise_mmu_exception(env, address, rw, ret); |
6af0bf9c FB |
359 | ret = 1; |
360 | } | |
361 | ||
362 | return ret; | |
363 | } | |
364 | ||
25b91e32 | 365 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 366 | hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) |
25b91e32 | 367 | { |
a8170e5e | 368 | hwaddr physical; |
25b91e32 AJ |
369 | int prot; |
370 | int access_type; | |
371 | int ret = 0; | |
372 | ||
25b91e32 AJ |
373 | /* data access */ |
374 | access_type = ACCESS_INT; | |
375 | ret = get_physical_address(env, &physical, &prot, | |
376 | address, rw, access_type); | |
377 | if (ret != TLBRET_MATCH) { | |
378 | raise_mmu_exception(env, address, rw, ret); | |
c36bbb28 AJ |
379 | return -1LL; |
380 | } else { | |
381 | return physical; | |
25b91e32 | 382 | } |
25b91e32 | 383 | } |
25b91e32 | 384 | |
9a5d878f TS |
385 | static const char * const excp_names[EXCP_LAST + 1] = { |
386 | [EXCP_RESET] = "reset", | |
387 | [EXCP_SRESET] = "soft reset", | |
388 | [EXCP_DSS] = "debug single step", | |
389 | [EXCP_DINT] = "debug interrupt", | |
390 | [EXCP_NMI] = "non-maskable interrupt", | |
391 | [EXCP_MCHECK] = "machine check", | |
392 | [EXCP_EXT_INTERRUPT] = "interrupt", | |
393 | [EXCP_DFWATCH] = "deferred watchpoint", | |
394 | [EXCP_DIB] = "debug instruction breakpoint", | |
395 | [EXCP_IWATCH] = "instruction fetch watchpoint", | |
396 | [EXCP_AdEL] = "address error load", | |
397 | [EXCP_AdES] = "address error store", | |
398 | [EXCP_TLBF] = "TLB refill", | |
399 | [EXCP_IBE] = "instruction bus error", | |
400 | [EXCP_DBp] = "debug breakpoint", | |
401 | [EXCP_SYSCALL] = "syscall", | |
402 | [EXCP_BREAK] = "break", | |
403 | [EXCP_CpU] = "coprocessor unusable", | |
404 | [EXCP_RI] = "reserved instruction", | |
405 | [EXCP_OVERFLOW] = "arithmetic overflow", | |
406 | [EXCP_TRAP] = "trap", | |
407 | [EXCP_FPE] = "floating point", | |
408 | [EXCP_DDBS] = "debug data break store", | |
409 | [EXCP_DWATCH] = "data watchpoint", | |
410 | [EXCP_LTLBL] = "TLB modify", | |
411 | [EXCP_TLBL] = "TLB load", | |
412 | [EXCP_TLBS] = "TLB store", | |
413 | [EXCP_DBE] = "data bus error", | |
414 | [EXCP_DDBL] = "debug data break load", | |
415 | [EXCP_THREAD] = "thread", | |
416 | [EXCP_MDMX] = "MDMX", | |
417 | [EXCP_C2E] = "precise coprocessor 2", | |
418 | [EXCP_CACHE] = "cache error", | |
92ceb440 LA |
419 | [EXCP_TLBXI] = "TLB execute-inhibit", |
420 | [EXCP_TLBRI] = "TLB read-inhibit", | |
b10ac204 YK |
421 | [EXCP_MSADIS] = "MSA disabled", |
422 | [EXCP_MSAFPE] = "MSA floating point", | |
14e51cc7 | 423 | }; |
d4fa5354 | 424 | #endif |
14e51cc7 | 425 | |
1239b472 | 426 | target_ulong exception_resume_pc (CPUMIPSState *env) |
32188a03 NF |
427 | { |
428 | target_ulong bad_pc; | |
429 | target_ulong isa_mode; | |
430 | ||
431 | isa_mode = !!(env->hflags & MIPS_HFLAG_M16); | |
432 | bad_pc = env->active_tc.PC | isa_mode; | |
433 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
434 | /* If the exception was raised from a delay slot, come back to | |
435 | the jump. */ | |
436 | bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); | |
437 | } | |
438 | ||
439 | return bad_pc; | |
440 | } | |
bbfa8f72 | 441 | |
1239b472 | 442 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 443 | static void set_hflags_for_handler (CPUMIPSState *env) |
bbfa8f72 NF |
444 | { |
445 | /* Exception handlers are entered in 32-bit mode. */ | |
446 | env->hflags &= ~(MIPS_HFLAG_M16); | |
447 | /* ...except that microMIPS lets you choose. */ | |
448 | if (env->insn_flags & ASE_MICROMIPS) { | |
449 | env->hflags |= (!!(env->CP0_Config3 | |
450 | & (1 << CP0C3_ISA_ON_EXC)) | |
451 | << MIPS_HFLAG_M16_SHIFT); | |
452 | } | |
453 | } | |
aea14095 LA |
454 | |
455 | static inline void set_badinstr_registers(CPUMIPSState *env) | |
456 | { | |
457 | if (env->hflags & MIPS_HFLAG_M16) { | |
458 | /* TODO: add BadInstr support for microMIPS */ | |
459 | return; | |
460 | } | |
461 | if (env->CP0_Config3 & (1 << CP0C3_BI)) { | |
462 | env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); | |
463 | } | |
464 | if ((env->CP0_Config3 & (1 << CP0C3_BP)) && | |
465 | (env->hflags & MIPS_HFLAG_BMASK)) { | |
466 | env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); | |
467 | } | |
468 | } | |
32188a03 NF |
469 | #endif |
470 | ||
97a8ea5a | 471 | void mips_cpu_do_interrupt(CPUState *cs) |
6af0bf9c | 472 | { |
27103424 | 473 | #if !defined(CONFIG_USER_ONLY) |
97a8ea5a AF |
474 | MIPSCPU *cpu = MIPS_CPU(cs); |
475 | CPUMIPSState *env = &cpu->env; | |
aea14095 | 476 | bool update_badinstr = 0; |
932e71cd AJ |
477 | target_ulong offset; |
478 | int cause = -1; | |
479 | const char *name; | |
100ce988 | 480 | |
c8557016 RH |
481 | if (qemu_loglevel_mask(CPU_LOG_INT) |
482 | && cs->exception_index != EXCP_EXT_INTERRUPT) { | |
27103424 | 483 | if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) { |
932e71cd | 484 | name = "unknown"; |
27103424 AF |
485 | } else { |
486 | name = excp_names[cs->exception_index]; | |
487 | } | |
b67bfe8d | 488 | |
c8557016 RH |
489 | qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx |
490 | " %s exception\n", | |
93fcfe39 | 491 | __func__, env->active_tc.PC, env->CP0_EPC, name); |
932e71cd | 492 | } |
27103424 AF |
493 | if (cs->exception_index == EXCP_EXT_INTERRUPT && |
494 | (env->hflags & MIPS_HFLAG_DM)) { | |
495 | cs->exception_index = EXCP_DINT; | |
496 | } | |
932e71cd | 497 | offset = 0x180; |
27103424 | 498 | switch (cs->exception_index) { |
932e71cd AJ |
499 | case EXCP_DSS: |
500 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
501 | /* Debug single step cannot be raised inside a delay slot and | |
502 | resume will always occur on the next instruction | |
503 | (but we assume the pc has always been updated during | |
504 | code translation). */ | |
32188a03 | 505 | env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); |
932e71cd AJ |
506 | goto enter_debug_mode; |
507 | case EXCP_DINT: | |
508 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
509 | goto set_DEPC; | |
510 | case EXCP_DIB: | |
511 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
512 | goto set_DEPC; | |
513 | case EXCP_DBp: | |
514 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
515 | goto set_DEPC; | |
516 | case EXCP_DDBS: | |
517 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
518 | goto set_DEPC; | |
519 | case EXCP_DDBL: | |
520 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
521 | set_DEPC: | |
32188a03 NF |
522 | env->CP0_DEPC = exception_resume_pc(env); |
523 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
0eaef5aa | 524 | enter_debug_mode: |
d9224450 MR |
525 | if (env->insn_flags & ISA_MIPS3) { |
526 | env->hflags |= MIPS_HFLAG_64; | |
7871abb9 JH |
527 | if (!(env->insn_flags & ISA_MIPS64R6) || |
528 | env->CP0_Status & (1 << CP0St_KX)) { | |
529 | env->hflags &= ~MIPS_HFLAG_AWRAP; | |
530 | } | |
d9224450 MR |
531 | } |
532 | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0; | |
932e71cd AJ |
533 | env->hflags &= ~(MIPS_HFLAG_KSU); |
534 | /* EJTAG probe trap enable is not implemented... */ | |
535 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
f45cb2f4 | 536 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
932e71cd | 537 | env->active_tc.PC = (int32_t)0xBFC00480; |
bbfa8f72 | 538 | set_hflags_for_handler(env); |
932e71cd AJ |
539 | break; |
540 | case EXCP_RESET: | |
fca1be7c | 541 | cpu_reset(CPU(cpu)); |
932e71cd AJ |
542 | break; |
543 | case EXCP_SRESET: | |
544 | env->CP0_Status |= (1 << CP0St_SR); | |
545 | memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); | |
546 | goto set_error_EPC; | |
547 | case EXCP_NMI: | |
548 | env->CP0_Status |= (1 << CP0St_NMI); | |
0eaef5aa | 549 | set_error_EPC: |
32188a03 NF |
550 | env->CP0_ErrorEPC = exception_resume_pc(env); |
551 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
932e71cd | 552 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
d9224450 MR |
553 | if (env->insn_flags & ISA_MIPS3) { |
554 | env->hflags |= MIPS_HFLAG_64; | |
7871abb9 JH |
555 | if (!(env->insn_flags & ISA_MIPS64R6) || |
556 | env->CP0_Status & (1 << CP0St_KX)) { | |
557 | env->hflags &= ~MIPS_HFLAG_AWRAP; | |
558 | } | |
d9224450 MR |
559 | } |
560 | env->hflags |= MIPS_HFLAG_CP0; | |
932e71cd AJ |
561 | env->hflags &= ~(MIPS_HFLAG_KSU); |
562 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
f45cb2f4 | 563 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
932e71cd | 564 | env->active_tc.PC = (int32_t)0xBFC00000; |
bbfa8f72 | 565 | set_hflags_for_handler(env); |
932e71cd AJ |
566 | break; |
567 | case EXCP_EXT_INTERRUPT: | |
568 | cause = 0; | |
da52a4df YK |
569 | if (env->CP0_Cause & (1 << CP0Ca_IV)) { |
570 | uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f; | |
571 | ||
572 | if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) { | |
573 | offset = 0x200; | |
574 | } else { | |
575 | uint32_t vector = 0; | |
576 | uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP; | |
577 | ||
578 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { | |
579 | /* For VEIC mode, the external interrupt controller feeds | |
580 | * the vector through the CP0Cause IP lines. */ | |
581 | vector = pending; | |
582 | } else { | |
583 | /* Vectored Interrupts | |
584 | * Mask with Status.IM7-IM0 to get enabled interrupts. */ | |
585 | pending &= (env->CP0_Status >> CP0St_IM) & 0xff; | |
586 | /* Find the highest-priority interrupt. */ | |
587 | while (pending >>= 1) { | |
588 | vector++; | |
138afb02 | 589 | } |
138afb02 | 590 | } |
da52a4df | 591 | offset = 0x200 + (vector * (spacing << 5)); |
138afb02 | 592 | } |
138afb02 | 593 | } |
932e71cd AJ |
594 | goto set_EPC; |
595 | case EXCP_LTLBL: | |
596 | cause = 1; | |
aea14095 | 597 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
932e71cd AJ |
598 | goto set_EPC; |
599 | case EXCP_TLBL: | |
600 | cause = 2; | |
aea14095 LA |
601 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
602 | if ((env->error_code & EXCP_TLB_NOMATCH) && | |
603 | !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 604 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
605 | int R = env->CP0_BadVAddr >> 62; |
606 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
607 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
608 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 609 | |
3fc00a7b AJ |
610 | if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && |
611 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) | |
932e71cd AJ |
612 | offset = 0x080; |
613 | else | |
0eaef5aa | 614 | #endif |
932e71cd AJ |
615 | offset = 0x000; |
616 | } | |
617 | goto set_EPC; | |
618 | case EXCP_TLBS: | |
619 | cause = 3; | |
aea14095 LA |
620 | update_badinstr = 1; |
621 | if ((env->error_code & EXCP_TLB_NOMATCH) && | |
622 | !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 623 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
624 | int R = env->CP0_BadVAddr >> 62; |
625 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
626 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
627 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 628 | |
3fc00a7b AJ |
629 | if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && |
630 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) | |
932e71cd AJ |
631 | offset = 0x080; |
632 | else | |
0eaef5aa | 633 | #endif |
932e71cd AJ |
634 | offset = 0x000; |
635 | } | |
636 | goto set_EPC; | |
637 | case EXCP_AdEL: | |
638 | cause = 4; | |
aea14095 | 639 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
932e71cd AJ |
640 | goto set_EPC; |
641 | case EXCP_AdES: | |
642 | cause = 5; | |
aea14095 | 643 | update_badinstr = 1; |
932e71cd AJ |
644 | goto set_EPC; |
645 | case EXCP_IBE: | |
646 | cause = 6; | |
647 | goto set_EPC; | |
648 | case EXCP_DBE: | |
649 | cause = 7; | |
650 | goto set_EPC; | |
651 | case EXCP_SYSCALL: | |
652 | cause = 8; | |
aea14095 | 653 | update_badinstr = 1; |
932e71cd AJ |
654 | goto set_EPC; |
655 | case EXCP_BREAK: | |
656 | cause = 9; | |
aea14095 | 657 | update_badinstr = 1; |
932e71cd AJ |
658 | goto set_EPC; |
659 | case EXCP_RI: | |
660 | cause = 10; | |
aea14095 | 661 | update_badinstr = 1; |
932e71cd AJ |
662 | goto set_EPC; |
663 | case EXCP_CpU: | |
664 | cause = 11; | |
aea14095 | 665 | update_badinstr = 1; |
932e71cd AJ |
666 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
667 | (env->error_code << CP0Ca_CE); | |
668 | goto set_EPC; | |
669 | case EXCP_OVERFLOW: | |
670 | cause = 12; | |
aea14095 | 671 | update_badinstr = 1; |
932e71cd AJ |
672 | goto set_EPC; |
673 | case EXCP_TRAP: | |
674 | cause = 13; | |
aea14095 | 675 | update_badinstr = 1; |
932e71cd | 676 | goto set_EPC; |
b10ac204 YK |
677 | case EXCP_MSAFPE: |
678 | cause = 14; | |
679 | update_badinstr = 1; | |
680 | goto set_EPC; | |
932e71cd AJ |
681 | case EXCP_FPE: |
682 | cause = 15; | |
aea14095 | 683 | update_badinstr = 1; |
932e71cd AJ |
684 | goto set_EPC; |
685 | case EXCP_C2E: | |
686 | cause = 18; | |
687 | goto set_EPC; | |
92ceb440 LA |
688 | case EXCP_TLBRI: |
689 | cause = 19; | |
aea14095 | 690 | update_badinstr = 1; |
92ceb440 LA |
691 | goto set_EPC; |
692 | case EXCP_TLBXI: | |
693 | cause = 20; | |
694 | goto set_EPC; | |
b10ac204 YK |
695 | case EXCP_MSADIS: |
696 | cause = 21; | |
697 | update_badinstr = 1; | |
698 | goto set_EPC; | |
932e71cd AJ |
699 | case EXCP_MDMX: |
700 | cause = 22; | |
701 | goto set_EPC; | |
702 | case EXCP_DWATCH: | |
703 | cause = 23; | |
67cc32eb | 704 | /* XXX: TODO: manage deferred watch exceptions */ |
932e71cd AJ |
705 | goto set_EPC; |
706 | case EXCP_MCHECK: | |
707 | cause = 24; | |
708 | goto set_EPC; | |
709 | case EXCP_THREAD: | |
710 | cause = 25; | |
711 | goto set_EPC; | |
853c3240 JL |
712 | case EXCP_DSPDIS: |
713 | cause = 26; | |
714 | goto set_EPC; | |
932e71cd AJ |
715 | case EXCP_CACHE: |
716 | cause = 30; | |
717 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
718 | offset = 0x100; | |
719 | } else { | |
720 | offset = 0x20000100; | |
721 | } | |
0eaef5aa | 722 | set_EPC: |
932e71cd | 723 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
32188a03 | 724 | env->CP0_EPC = exception_resume_pc(env); |
aea14095 LA |
725 | if (update_badinstr) { |
726 | set_badinstr_registers(env); | |
727 | } | |
932e71cd | 728 | if (env->hflags & MIPS_HFLAG_BMASK) { |
f45cb2f4 | 729 | env->CP0_Cause |= (1U << CP0Ca_BD); |
0eaef5aa | 730 | } else { |
f45cb2f4 | 731 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
0eaef5aa | 732 | } |
932e71cd | 733 | env->CP0_Status |= (1 << CP0St_EXL); |
d9224450 MR |
734 | if (env->insn_flags & ISA_MIPS3) { |
735 | env->hflags |= MIPS_HFLAG_64; | |
7871abb9 JH |
736 | if (!(env->insn_flags & ISA_MIPS64R6) || |
737 | env->CP0_Status & (1 << CP0St_KX)) { | |
738 | env->hflags &= ~MIPS_HFLAG_AWRAP; | |
739 | } | |
d9224450 MR |
740 | } |
741 | env->hflags |= MIPS_HFLAG_CP0; | |
932e71cd | 742 | env->hflags &= ~(MIPS_HFLAG_KSU); |
6af0bf9c | 743 | } |
932e71cd AJ |
744 | env->hflags &= ~MIPS_HFLAG_BMASK; |
745 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
746 | env->active_tc.PC = (int32_t)0xBFC00200; | |
747 | } else { | |
748 | env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); | |
6af0bf9c | 749 | } |
932e71cd | 750 | env->active_tc.PC += offset; |
bbfa8f72 | 751 | set_hflags_for_handler(env); |
932e71cd AJ |
752 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
753 | break; | |
754 | default: | |
c8557016 | 755 | abort(); |
932e71cd | 756 | } |
c8557016 RH |
757 | if (qemu_loglevel_mask(CPU_LOG_INT) |
758 | && cs->exception_index != EXCP_EXT_INTERRUPT) { | |
93fcfe39 | 759 | qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" |
c8557016 RH |
760 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
761 | __func__, env->active_tc.PC, env->CP0_EPC, cause, | |
762 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, | |
763 | env->CP0_DEPC); | |
6af0bf9c | 764 | } |
932e71cd | 765 | #endif |
27103424 | 766 | cs->exception_index = EXCP_NONE; |
6af0bf9c | 767 | } |
2ee4aed8 | 768 | |
fa4faba4 RH |
769 | bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
770 | { | |
771 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
772 | MIPSCPU *cpu = MIPS_CPU(cs); | |
773 | CPUMIPSState *env = &cpu->env; | |
774 | ||
71ca034a LA |
775 | if (cpu_mips_hw_interrupts_enabled(env) && |
776 | cpu_mips_hw_interrupts_pending(env)) { | |
fa4faba4 RH |
777 | /* Raise it */ |
778 | cs->exception_index = EXCP_EXT_INTERRUPT; | |
779 | env->error_code = 0; | |
780 | mips_cpu_do_interrupt(cs); | |
781 | return true; | |
782 | } | |
783 | } | |
784 | return false; | |
785 | } | |
786 | ||
3c7b48b7 | 787 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 788 | void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) |
2ee4aed8 | 789 | { |
31b030d4 AF |
790 | MIPSCPU *cpu = mips_env_get_cpu(env); |
791 | CPUState *cs; | |
c227f099 | 792 | r4k_tlb_t *tlb; |
3b1c8be4 TS |
793 | target_ulong addr; |
794 | target_ulong end; | |
795 | uint8_t ASID = env->CP0_EntryHi & 0xFF; | |
796 | target_ulong mask; | |
2ee4aed8 | 797 | |
ead9360e | 798 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 799 | /* The qemu TLB is flushed when the ASID changes, so no need to |
2ee4aed8 FB |
800 | flush these entries again. */ |
801 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
802 | return; | |
803 | } | |
804 | ||
ead9360e | 805 | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { |
2ee4aed8 | 806 | /* For tlbwr, we can shadow the discarded entry into |
6958549d AJ |
807 | a new (fake) TLB entry, as long as the guest can not |
808 | tell that it's there. */ | |
ead9360e TS |
809 | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
810 | env->tlb->tlb_in_use++; | |
2ee4aed8 FB |
811 | return; |
812 | } | |
813 | ||
3b1c8be4 | 814 | /* 1k pages are not supported. */ |
f2e9ebef | 815 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 816 | if (tlb->V0) { |
31b030d4 | 817 | cs = CPU(cpu); |
f2e9ebef | 818 | addr = tlb->VPN & ~mask; |
d26bc211 | 819 | #if defined(TARGET_MIPS64) |
e034e2c3 | 820 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
821 | addr |= 0x3FFFFF0000000000ULL; |
822 | } | |
823 | #endif | |
3b1c8be4 TS |
824 | end = addr | (mask >> 1); |
825 | while (addr < end) { | |
31b030d4 | 826 | tlb_flush_page(cs, addr); |
3b1c8be4 TS |
827 | addr += TARGET_PAGE_SIZE; |
828 | } | |
829 | } | |
830 | if (tlb->V1) { | |
31b030d4 | 831 | cs = CPU(cpu); |
f2e9ebef | 832 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
d26bc211 | 833 | #if defined(TARGET_MIPS64) |
e034e2c3 | 834 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
835 | addr |= 0x3FFFFF0000000000ULL; |
836 | } | |
837 | #endif | |
3b1c8be4 | 838 | end = addr | mask; |
53715e48 | 839 | while (addr - 1 < end) { |
31b030d4 | 840 | tlb_flush_page(cs, addr); |
3b1c8be4 TS |
841 | addr += TARGET_PAGE_SIZE; |
842 | } | |
843 | } | |
2ee4aed8 | 844 | } |
3c7b48b7 | 845 | #endif |