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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
6af0bf9c | 18 | */ |
e37e863f FB |
19 | #include <stdarg.h> |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
e37e863f FB |
25 | |
26 | #include "cpu.h" | |
4ef37e69 | 27 | #include "sysemu/kvm.h" |
aea14095 | 28 | #include "exec/cpu_ldst.h" |
6af0bf9c | 29 | |
43057ab1 | 30 | enum { |
2fb58b73 LA |
31 | TLBRET_XI = -6, |
32 | TLBRET_RI = -5, | |
43057ab1 FB |
33 | TLBRET_DIRTY = -4, |
34 | TLBRET_INVALID = -3, | |
35 | TLBRET_NOMATCH = -2, | |
36 | TLBRET_BADADDR = -1, | |
37 | TLBRET_MATCH = 0 | |
38 | }; | |
39 | ||
3c7b48b7 PB |
40 | #if !defined(CONFIG_USER_ONLY) |
41 | ||
29929e34 | 42 | /* no MMU emulation */ |
a8170e5e | 43 | int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
6af0bf9c | 44 | target_ulong address, int rw, int access_type) |
29929e34 TS |
45 | { |
46 | *physical = address; | |
47 | *prot = PAGE_READ | PAGE_WRITE; | |
48 | return TLBRET_MATCH; | |
49 | } | |
50 | ||
51 | /* fixed mapping MMU emulation */ | |
a8170e5e | 52 | int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 TS |
53 | target_ulong address, int rw, int access_type) |
54 | { | |
55 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
56 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
57 | *physical = address + 0x40000000UL; | |
58 | else | |
59 | *physical = address; | |
60 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
61 | *physical = address & 0x1FFFFFFF; | |
62 | else | |
63 | *physical = address; | |
64 | ||
65 | *prot = PAGE_READ | PAGE_WRITE; | |
66 | return TLBRET_MATCH; | |
67 | } | |
68 | ||
69 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
a8170e5e | 70 | int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 71 | target_ulong address, int rw, int access_type) |
6af0bf9c | 72 | { |
925fd0f2 | 73 | uint8_t ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 74 | int i; |
6af0bf9c | 75 | |
ead9360e | 76 | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
c227f099 | 77 | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; |
3b1c8be4 | 78 | /* 1k pages are not supported. */ |
f2e9ebef | 79 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 80 | target_ulong tag = address & ~mask; |
f2e9ebef | 81 | target_ulong VPN = tlb->VPN & ~mask; |
d26bc211 | 82 | #if defined(TARGET_MIPS64) |
e034e2c3 | 83 | tag &= env->SEGMask; |
100ce988 | 84 | #endif |
3b1c8be4 | 85 | |
6af0bf9c | 86 | /* Check ASID, virtual page number & size */ |
9456c2fb | 87 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) { |
6af0bf9c | 88 | /* TLB match */ |
f2e9ebef | 89 | int n = !!(address & mask & ~(mask >> 1)); |
6af0bf9c | 90 | /* Check access rights */ |
2fb58b73 | 91 | if (!(n ? tlb->V1 : tlb->V0)) { |
43057ab1 | 92 | return TLBRET_INVALID; |
2fb58b73 LA |
93 | } |
94 | if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) { | |
95 | return TLBRET_XI; | |
96 | } | |
97 | if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) { | |
98 | return TLBRET_RI; | |
99 | } | |
9f6bcedb | 100 | if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { |
3b1c8be4 | 101 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
9fb63ac2 | 102 | *prot = PAGE_READ; |
98c1b82b | 103 | if (n ? tlb->D1 : tlb->D0) |
9fb63ac2 | 104 | *prot |= PAGE_WRITE; |
43057ab1 | 105 | return TLBRET_MATCH; |
6af0bf9c | 106 | } |
43057ab1 | 107 | return TLBRET_DIRTY; |
6af0bf9c FB |
108 | } |
109 | } | |
43057ab1 | 110 | return TLBRET_NOMATCH; |
6af0bf9c | 111 | } |
6af0bf9c | 112 | |
a8170e5e | 113 | static int get_physical_address (CPUMIPSState *env, hwaddr *physical, |
4ef37e69 | 114 | int *prot, target_ulong real_address, |
43057ab1 | 115 | int rw, int access_type) |
6af0bf9c | 116 | { |
b4ab4b4e | 117 | /* User mode can only access useg/xuseg */ |
43057ab1 | 118 | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
671880e6 TS |
119 | int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; |
120 | int kernel_mode = !user_mode && !supervisor_mode; | |
d26bc211 | 121 | #if defined(TARGET_MIPS64) |
b4ab4b4e TS |
122 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
123 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
124 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
125 | #endif | |
43057ab1 | 126 | int ret = TLBRET_MATCH; |
4ef37e69 JH |
127 | /* effective address (modified for KVM T&E kernel segments) */ |
128 | target_ulong address = real_address; | |
43057ab1 | 129 | |
6af0bf9c | 130 | #if 0 |
93fcfe39 | 131 | qemu_log("user mode %d h %08x\n", user_mode, env->hflags); |
6af0bf9c | 132 | #endif |
b4ab4b4e | 133 | |
22010ce7 JH |
134 | #define USEG_LIMIT 0x7FFFFFFFUL |
135 | #define KSEG0_BASE 0x80000000UL | |
136 | #define KSEG1_BASE 0xA0000000UL | |
137 | #define KSEG2_BASE 0xC0000000UL | |
138 | #define KSEG3_BASE 0xE0000000UL | |
139 | ||
4ef37e69 JH |
140 | #define KVM_KSEG0_BASE 0x40000000UL |
141 | #define KVM_KSEG2_BASE 0x60000000UL | |
142 | ||
143 | if (kvm_enabled()) { | |
144 | /* KVM T&E adds guest kernel segments in useg */ | |
145 | if (real_address >= KVM_KSEG0_BASE) { | |
146 | if (real_address < KVM_KSEG2_BASE) { | |
147 | /* kseg0 */ | |
148 | address += KSEG0_BASE - KVM_KSEG0_BASE; | |
149 | } else if (real_address <= USEG_LIMIT) { | |
150 | /* kseg2/3 */ | |
151 | address += KSEG2_BASE - KVM_KSEG2_BASE; | |
152 | } | |
153 | } | |
154 | } | |
155 | ||
22010ce7 | 156 | if (address <= USEG_LIMIT) { |
b4ab4b4e | 157 | /* useg */ |
996ba2cc | 158 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
29929e34 | 159 | *physical = address & 0xFFFFFFFF; |
6af0bf9c | 160 | *prot = PAGE_READ | PAGE_WRITE; |
996ba2cc | 161 | } else { |
4ef37e69 | 162 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6af0bf9c | 163 | } |
d26bc211 | 164 | #if defined(TARGET_MIPS64) |
89fc88da | 165 | } else if (address < 0x4000000000000000ULL) { |
b4ab4b4e | 166 | /* xuseg */ |
6958549d | 167 | if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
4ef37e69 | 168 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
169 | } else { |
170 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 171 | } |
89fc88da | 172 | } else if (address < 0x8000000000000000ULL) { |
b4ab4b4e | 173 | /* xsseg */ |
6958549d AJ |
174 | if ((supervisor_mode || kernel_mode) && |
175 | SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { | |
4ef37e69 | 176 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
177 | } else { |
178 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 179 | } |
89fc88da | 180 | } else if (address < 0xC000000000000000ULL) { |
b4ab4b4e | 181 | /* xkphys */ |
671880e6 | 182 | if (kernel_mode && KX && |
6d35524c TS |
183 | (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { |
184 | *physical = address & env->PAMask; | |
b4ab4b4e | 185 | *prot = PAGE_READ | PAGE_WRITE; |
6958549d AJ |
186 | } else { |
187 | ret = TLBRET_BADADDR; | |
188 | } | |
89fc88da | 189 | } else if (address < 0xFFFFFFFF80000000ULL) { |
b4ab4b4e | 190 | /* xkseg */ |
6958549d AJ |
191 | if (kernel_mode && KX && |
192 | address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { | |
4ef37e69 | 193 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
194 | } else { |
195 | ret = TLBRET_BADADDR; | |
196 | } | |
b4ab4b4e | 197 | #endif |
22010ce7 | 198 | } else if (address < (int32_t)KSEG1_BASE) { |
6af0bf9c | 199 | /* kseg0 */ |
671880e6 | 200 | if (kernel_mode) { |
22010ce7 | 201 | *physical = address - (int32_t)KSEG0_BASE; |
671880e6 TS |
202 | *prot = PAGE_READ | PAGE_WRITE; |
203 | } else { | |
204 | ret = TLBRET_BADADDR; | |
205 | } | |
22010ce7 | 206 | } else if (address < (int32_t)KSEG2_BASE) { |
6af0bf9c | 207 | /* kseg1 */ |
671880e6 | 208 | if (kernel_mode) { |
22010ce7 | 209 | *physical = address - (int32_t)KSEG1_BASE; |
671880e6 TS |
210 | *prot = PAGE_READ | PAGE_WRITE; |
211 | } else { | |
212 | ret = TLBRET_BADADDR; | |
213 | } | |
22010ce7 | 214 | } else if (address < (int32_t)KSEG3_BASE) { |
89fc88da | 215 | /* sseg (kseg2) */ |
671880e6 | 216 | if (supervisor_mode || kernel_mode) { |
4ef37e69 | 217 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
671880e6 TS |
218 | } else { |
219 | ret = TLBRET_BADADDR; | |
220 | } | |
6af0bf9c FB |
221 | } else { |
222 | /* kseg3 */ | |
6af0bf9c | 223 | /* XXX: debug segment is not emulated */ |
671880e6 | 224 | if (kernel_mode) { |
4ef37e69 | 225 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
671880e6 TS |
226 | } else { |
227 | ret = TLBRET_BADADDR; | |
228 | } | |
6af0bf9c FB |
229 | } |
230 | #if 0 | |
951fab99 | 231 | qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n", |
93fcfe39 | 232 | address, rw, access_type, *physical, *prot, ret); |
6af0bf9c FB |
233 | #endif |
234 | ||
235 | return ret; | |
236 | } | |
932e71cd | 237 | #endif |
6af0bf9c | 238 | |
7db13fae | 239 | static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, |
1147e189 AJ |
240 | int rw, int tlb_error) |
241 | { | |
27103424 | 242 | CPUState *cs = CPU(mips_env_get_cpu(env)); |
1147e189 AJ |
243 | int exception = 0, error_code = 0; |
244 | ||
aea14095 LA |
245 | if (rw == MMU_INST_FETCH) { |
246 | error_code |= EXCP_INST_NOTAVAIL; | |
247 | } | |
248 | ||
1147e189 AJ |
249 | switch (tlb_error) { |
250 | default: | |
251 | case TLBRET_BADADDR: | |
252 | /* Reference to kernel address from user mode or supervisor mode */ | |
253 | /* Reference to supervisor address from user mode */ | |
9f6bcedb | 254 | if (rw == MMU_DATA_STORE) { |
1147e189 | 255 | exception = EXCP_AdES; |
9f6bcedb | 256 | } else { |
1147e189 | 257 | exception = EXCP_AdEL; |
9f6bcedb | 258 | } |
1147e189 AJ |
259 | break; |
260 | case TLBRET_NOMATCH: | |
261 | /* No TLB match for a mapped address */ | |
9f6bcedb | 262 | if (rw == MMU_DATA_STORE) { |
1147e189 | 263 | exception = EXCP_TLBS; |
9f6bcedb | 264 | } else { |
1147e189 | 265 | exception = EXCP_TLBL; |
9f6bcedb | 266 | } |
aea14095 | 267 | error_code |= EXCP_TLB_NOMATCH; |
1147e189 AJ |
268 | break; |
269 | case TLBRET_INVALID: | |
270 | /* TLB match with no valid bit */ | |
9f6bcedb | 271 | if (rw == MMU_DATA_STORE) { |
1147e189 | 272 | exception = EXCP_TLBS; |
9f6bcedb | 273 | } else { |
1147e189 | 274 | exception = EXCP_TLBL; |
9f6bcedb | 275 | } |
1147e189 AJ |
276 | break; |
277 | case TLBRET_DIRTY: | |
278 | /* TLB match but 'D' bit is cleared */ | |
279 | exception = EXCP_LTLBL; | |
280 | break; | |
92ceb440 LA |
281 | case TLBRET_XI: |
282 | /* Execute-Inhibit Exception */ | |
283 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { | |
284 | exception = EXCP_TLBXI; | |
285 | } else { | |
286 | exception = EXCP_TLBL; | |
287 | } | |
288 | break; | |
289 | case TLBRET_RI: | |
290 | /* Read-Inhibit Exception */ | |
291 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { | |
292 | exception = EXCP_TLBRI; | |
293 | } else { | |
294 | exception = EXCP_TLBL; | |
295 | } | |
296 | break; | |
1147e189 AJ |
297 | } |
298 | /* Raise exception */ | |
299 | env->CP0_BadVAddr = address; | |
300 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | | |
301 | ((address >> 9) & 0x007ffff0); | |
302 | env->CP0_EntryHi = | |
303 | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); | |
304 | #if defined(TARGET_MIPS64) | |
305 | env->CP0_EntryHi &= env->SEGMask; | |
306 | env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | | |
307 | ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | | |
308 | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); | |
309 | #endif | |
27103424 | 310 | cs->exception_index = exception; |
1147e189 AJ |
311 | env->error_code = error_code; |
312 | } | |
313 | ||
4fcc562b | 314 | #if !defined(CONFIG_USER_ONLY) |
00b941e5 | 315 | hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
6af0bf9c | 316 | { |
00b941e5 | 317 | MIPSCPU *cpu = MIPS_CPU(cs); |
a8170e5e | 318 | hwaddr phys_addr; |
932e71cd | 319 | int prot; |
6af0bf9c | 320 | |
00b941e5 AF |
321 | if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, |
322 | ACCESS_INT) != 0) { | |
932e71cd | 323 | return -1; |
00b941e5 | 324 | } |
932e71cd | 325 | return phys_addr; |
6af0bf9c | 326 | } |
4fcc562b | 327 | #endif |
6af0bf9c | 328 | |
7510454e AF |
329 | int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, |
330 | int mmu_idx) | |
6af0bf9c | 331 | { |
7510454e AF |
332 | MIPSCPU *cpu = MIPS_CPU(cs); |
333 | CPUMIPSState *env = &cpu->env; | |
932e71cd | 334 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 335 | hwaddr physical; |
6af0bf9c | 336 | int prot; |
6af0bf9c | 337 | int access_type; |
99e43d36 | 338 | #endif |
6af0bf9c FB |
339 | int ret = 0; |
340 | ||
4ad40f36 | 341 | #if 0 |
7510454e | 342 | log_cpu_state(cs, 0); |
4ad40f36 | 343 | #endif |
7510454e | 344 | qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", |
97b348e7 | 345 | __func__, env->active_tc.PC, address, rw, mmu_idx); |
4ad40f36 | 346 | |
6af0bf9c | 347 | /* data access */ |
99e43d36 | 348 | #if !defined(CONFIG_USER_ONLY) |
6af0bf9c FB |
349 | /* XXX: put correct access by using cpu_restore_state() |
350 | correctly */ | |
351 | access_type = ACCESS_INT; | |
6af0bf9c FB |
352 | ret = get_physical_address(env, &physical, &prot, |
353 | address, rw, access_type); | |
7510454e AF |
354 | qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx |
355 | " prot %d\n", | |
356 | __func__, address, ret, physical, prot); | |
43057ab1 | 357 | if (ret == TLBRET_MATCH) { |
0c591eb0 | 358 | tlb_set_page(cs, address & TARGET_PAGE_MASK, |
99e43d36 AJ |
359 | physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, |
360 | mmu_idx, TARGET_PAGE_SIZE); | |
361 | ret = 0; | |
932e71cd AJ |
362 | } else if (ret < 0) |
363 | #endif | |
364 | { | |
1147e189 | 365 | raise_mmu_exception(env, address, rw, ret); |
6af0bf9c FB |
366 | ret = 1; |
367 | } | |
368 | ||
369 | return ret; | |
370 | } | |
371 | ||
25b91e32 | 372 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 373 | hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) |
25b91e32 | 374 | { |
a8170e5e | 375 | hwaddr physical; |
25b91e32 AJ |
376 | int prot; |
377 | int access_type; | |
378 | int ret = 0; | |
379 | ||
25b91e32 AJ |
380 | /* data access */ |
381 | access_type = ACCESS_INT; | |
382 | ret = get_physical_address(env, &physical, &prot, | |
383 | address, rw, access_type); | |
384 | if (ret != TLBRET_MATCH) { | |
385 | raise_mmu_exception(env, address, rw, ret); | |
c36bbb28 AJ |
386 | return -1LL; |
387 | } else { | |
388 | return physical; | |
25b91e32 | 389 | } |
25b91e32 AJ |
390 | } |
391 | #endif | |
392 | ||
9a5d878f TS |
393 | static const char * const excp_names[EXCP_LAST + 1] = { |
394 | [EXCP_RESET] = "reset", | |
395 | [EXCP_SRESET] = "soft reset", | |
396 | [EXCP_DSS] = "debug single step", | |
397 | [EXCP_DINT] = "debug interrupt", | |
398 | [EXCP_NMI] = "non-maskable interrupt", | |
399 | [EXCP_MCHECK] = "machine check", | |
400 | [EXCP_EXT_INTERRUPT] = "interrupt", | |
401 | [EXCP_DFWATCH] = "deferred watchpoint", | |
402 | [EXCP_DIB] = "debug instruction breakpoint", | |
403 | [EXCP_IWATCH] = "instruction fetch watchpoint", | |
404 | [EXCP_AdEL] = "address error load", | |
405 | [EXCP_AdES] = "address error store", | |
406 | [EXCP_TLBF] = "TLB refill", | |
407 | [EXCP_IBE] = "instruction bus error", | |
408 | [EXCP_DBp] = "debug breakpoint", | |
409 | [EXCP_SYSCALL] = "syscall", | |
410 | [EXCP_BREAK] = "break", | |
411 | [EXCP_CpU] = "coprocessor unusable", | |
412 | [EXCP_RI] = "reserved instruction", | |
413 | [EXCP_OVERFLOW] = "arithmetic overflow", | |
414 | [EXCP_TRAP] = "trap", | |
415 | [EXCP_FPE] = "floating point", | |
416 | [EXCP_DDBS] = "debug data break store", | |
417 | [EXCP_DWATCH] = "data watchpoint", | |
418 | [EXCP_LTLBL] = "TLB modify", | |
419 | [EXCP_TLBL] = "TLB load", | |
420 | [EXCP_TLBS] = "TLB store", | |
421 | [EXCP_DBE] = "data bus error", | |
422 | [EXCP_DDBL] = "debug data break load", | |
423 | [EXCP_THREAD] = "thread", | |
424 | [EXCP_MDMX] = "MDMX", | |
425 | [EXCP_C2E] = "precise coprocessor 2", | |
426 | [EXCP_CACHE] = "cache error", | |
92ceb440 LA |
427 | [EXCP_TLBXI] = "TLB execute-inhibit", |
428 | [EXCP_TLBRI] = "TLB read-inhibit", | |
b10ac204 YK |
429 | [EXCP_MSADIS] = "MSA disabled", |
430 | [EXCP_MSAFPE] = "MSA floating point", | |
14e51cc7 | 431 | }; |
14e51cc7 | 432 | |
1239b472 | 433 | target_ulong exception_resume_pc (CPUMIPSState *env) |
32188a03 NF |
434 | { |
435 | target_ulong bad_pc; | |
436 | target_ulong isa_mode; | |
437 | ||
438 | isa_mode = !!(env->hflags & MIPS_HFLAG_M16); | |
439 | bad_pc = env->active_tc.PC | isa_mode; | |
440 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
441 | /* If the exception was raised from a delay slot, come back to | |
442 | the jump. */ | |
443 | bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); | |
444 | } | |
445 | ||
446 | return bad_pc; | |
447 | } | |
bbfa8f72 | 448 | |
1239b472 | 449 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 450 | static void set_hflags_for_handler (CPUMIPSState *env) |
bbfa8f72 NF |
451 | { |
452 | /* Exception handlers are entered in 32-bit mode. */ | |
453 | env->hflags &= ~(MIPS_HFLAG_M16); | |
454 | /* ...except that microMIPS lets you choose. */ | |
455 | if (env->insn_flags & ASE_MICROMIPS) { | |
456 | env->hflags |= (!!(env->CP0_Config3 | |
457 | & (1 << CP0C3_ISA_ON_EXC)) | |
458 | << MIPS_HFLAG_M16_SHIFT); | |
459 | } | |
460 | } | |
aea14095 LA |
461 | |
462 | static inline void set_badinstr_registers(CPUMIPSState *env) | |
463 | { | |
464 | if (env->hflags & MIPS_HFLAG_M16) { | |
465 | /* TODO: add BadInstr support for microMIPS */ | |
466 | return; | |
467 | } | |
468 | if (env->CP0_Config3 & (1 << CP0C3_BI)) { | |
469 | env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); | |
470 | } | |
471 | if ((env->CP0_Config3 & (1 << CP0C3_BP)) && | |
472 | (env->hflags & MIPS_HFLAG_BMASK)) { | |
473 | env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); | |
474 | } | |
475 | } | |
32188a03 NF |
476 | #endif |
477 | ||
97a8ea5a | 478 | void mips_cpu_do_interrupt(CPUState *cs) |
6af0bf9c | 479 | { |
27103424 | 480 | #if !defined(CONFIG_USER_ONLY) |
97a8ea5a AF |
481 | MIPSCPU *cpu = MIPS_CPU(cs); |
482 | CPUMIPSState *env = &cpu->env; | |
aea14095 | 483 | bool update_badinstr = 0; |
932e71cd AJ |
484 | target_ulong offset; |
485 | int cause = -1; | |
486 | const char *name; | |
100ce988 | 487 | |
27103424 AF |
488 | if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) { |
489 | if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) { | |
932e71cd | 490 | name = "unknown"; |
27103424 AF |
491 | } else { |
492 | name = excp_names[cs->exception_index]; | |
493 | } | |
b67bfe8d | 494 | |
93fcfe39 AL |
495 | qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", |
496 | __func__, env->active_tc.PC, env->CP0_EPC, name); | |
932e71cd | 497 | } |
27103424 AF |
498 | if (cs->exception_index == EXCP_EXT_INTERRUPT && |
499 | (env->hflags & MIPS_HFLAG_DM)) { | |
500 | cs->exception_index = EXCP_DINT; | |
501 | } | |
932e71cd | 502 | offset = 0x180; |
27103424 | 503 | switch (cs->exception_index) { |
932e71cd AJ |
504 | case EXCP_DSS: |
505 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
506 | /* Debug single step cannot be raised inside a delay slot and | |
507 | resume will always occur on the next instruction | |
508 | (but we assume the pc has always been updated during | |
509 | code translation). */ | |
32188a03 | 510 | env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); |
932e71cd AJ |
511 | goto enter_debug_mode; |
512 | case EXCP_DINT: | |
513 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
514 | goto set_DEPC; | |
515 | case EXCP_DIB: | |
516 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
517 | goto set_DEPC; | |
518 | case EXCP_DBp: | |
519 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
520 | goto set_DEPC; | |
521 | case EXCP_DDBS: | |
522 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
523 | goto set_DEPC; | |
524 | case EXCP_DDBL: | |
525 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
526 | set_DEPC: | |
32188a03 NF |
527 | env->CP0_DEPC = exception_resume_pc(env); |
528 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
0eaef5aa | 529 | enter_debug_mode: |
d9224450 MR |
530 | if (env->insn_flags & ISA_MIPS3) { |
531 | env->hflags |= MIPS_HFLAG_64; | |
532 | } | |
533 | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0; | |
932e71cd AJ |
534 | env->hflags &= ~(MIPS_HFLAG_KSU); |
535 | /* EJTAG probe trap enable is not implemented... */ | |
536 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
f45cb2f4 | 537 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
932e71cd | 538 | env->active_tc.PC = (int32_t)0xBFC00480; |
bbfa8f72 | 539 | set_hflags_for_handler(env); |
932e71cd AJ |
540 | break; |
541 | case EXCP_RESET: | |
fca1be7c | 542 | cpu_reset(CPU(cpu)); |
932e71cd AJ |
543 | break; |
544 | case EXCP_SRESET: | |
545 | env->CP0_Status |= (1 << CP0St_SR); | |
546 | memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); | |
547 | goto set_error_EPC; | |
548 | case EXCP_NMI: | |
549 | env->CP0_Status |= (1 << CP0St_NMI); | |
0eaef5aa | 550 | set_error_EPC: |
32188a03 NF |
551 | env->CP0_ErrorEPC = exception_resume_pc(env); |
552 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
932e71cd | 553 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
d9224450 MR |
554 | if (env->insn_flags & ISA_MIPS3) { |
555 | env->hflags |= MIPS_HFLAG_64; | |
556 | } | |
557 | env->hflags |= MIPS_HFLAG_CP0; | |
932e71cd AJ |
558 | env->hflags &= ~(MIPS_HFLAG_KSU); |
559 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
f45cb2f4 | 560 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
932e71cd | 561 | env->active_tc.PC = (int32_t)0xBFC00000; |
bbfa8f72 | 562 | set_hflags_for_handler(env); |
932e71cd AJ |
563 | break; |
564 | case EXCP_EXT_INTERRUPT: | |
565 | cause = 0; | |
566 | if (env->CP0_Cause & (1 << CP0Ca_IV)) | |
567 | offset = 0x200; | |
138afb02 EI |
568 | |
569 | if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) { | |
570 | /* Vectored Interrupts. */ | |
571 | unsigned int spacing; | |
572 | unsigned int vector; | |
573 | unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8; | |
574 | ||
e4280973 | 575 | pending &= env->CP0_Status >> 8; |
138afb02 EI |
576 | /* Compute the Vector Spacing. */ |
577 | spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1); | |
578 | spacing <<= 5; | |
579 | ||
580 | if (env->CP0_Config3 & (1 << CP0C3_VInt)) { | |
581 | /* For VInt mode, the MIPS computes the vector internally. */ | |
e4280973 EI |
582 | for (vector = 7; vector > 0; vector--) { |
583 | if (pending & (1 << vector)) { | |
138afb02 EI |
584 | /* Found it. */ |
585 | break; | |
586 | } | |
138afb02 EI |
587 | } |
588 | } else { | |
589 | /* For VEIC mode, the external interrupt controller feeds the | |
e7d81004 | 590 | vector through the CP0Cause IP lines. */ |
138afb02 EI |
591 | vector = pending; |
592 | } | |
593 | offset = 0x200 + vector * spacing; | |
594 | } | |
932e71cd AJ |
595 | goto set_EPC; |
596 | case EXCP_LTLBL: | |
597 | cause = 1; | |
aea14095 | 598 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
932e71cd AJ |
599 | goto set_EPC; |
600 | case EXCP_TLBL: | |
601 | cause = 2; | |
aea14095 LA |
602 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
603 | if ((env->error_code & EXCP_TLB_NOMATCH) && | |
604 | !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 605 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
606 | int R = env->CP0_BadVAddr >> 62; |
607 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
608 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
609 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 610 | |
3fc00a7b AJ |
611 | if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && |
612 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) | |
932e71cd AJ |
613 | offset = 0x080; |
614 | else | |
0eaef5aa | 615 | #endif |
932e71cd AJ |
616 | offset = 0x000; |
617 | } | |
618 | goto set_EPC; | |
619 | case EXCP_TLBS: | |
620 | cause = 3; | |
aea14095 LA |
621 | update_badinstr = 1; |
622 | if ((env->error_code & EXCP_TLB_NOMATCH) && | |
623 | !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 624 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
625 | int R = env->CP0_BadVAddr >> 62; |
626 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
627 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
628 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 629 | |
3fc00a7b AJ |
630 | if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && |
631 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) | |
932e71cd AJ |
632 | offset = 0x080; |
633 | else | |
0eaef5aa | 634 | #endif |
932e71cd AJ |
635 | offset = 0x000; |
636 | } | |
637 | goto set_EPC; | |
638 | case EXCP_AdEL: | |
639 | cause = 4; | |
aea14095 | 640 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
932e71cd AJ |
641 | goto set_EPC; |
642 | case EXCP_AdES: | |
643 | cause = 5; | |
aea14095 | 644 | update_badinstr = 1; |
932e71cd AJ |
645 | goto set_EPC; |
646 | case EXCP_IBE: | |
647 | cause = 6; | |
648 | goto set_EPC; | |
649 | case EXCP_DBE: | |
650 | cause = 7; | |
651 | goto set_EPC; | |
652 | case EXCP_SYSCALL: | |
653 | cause = 8; | |
aea14095 | 654 | update_badinstr = 1; |
932e71cd AJ |
655 | goto set_EPC; |
656 | case EXCP_BREAK: | |
657 | cause = 9; | |
aea14095 | 658 | update_badinstr = 1; |
932e71cd AJ |
659 | goto set_EPC; |
660 | case EXCP_RI: | |
661 | cause = 10; | |
aea14095 | 662 | update_badinstr = 1; |
932e71cd AJ |
663 | goto set_EPC; |
664 | case EXCP_CpU: | |
665 | cause = 11; | |
aea14095 | 666 | update_badinstr = 1; |
932e71cd AJ |
667 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
668 | (env->error_code << CP0Ca_CE); | |
669 | goto set_EPC; | |
670 | case EXCP_OVERFLOW: | |
671 | cause = 12; | |
aea14095 | 672 | update_badinstr = 1; |
932e71cd AJ |
673 | goto set_EPC; |
674 | case EXCP_TRAP: | |
675 | cause = 13; | |
aea14095 | 676 | update_badinstr = 1; |
932e71cd | 677 | goto set_EPC; |
b10ac204 YK |
678 | case EXCP_MSAFPE: |
679 | cause = 14; | |
680 | update_badinstr = 1; | |
681 | goto set_EPC; | |
932e71cd AJ |
682 | case EXCP_FPE: |
683 | cause = 15; | |
aea14095 | 684 | update_badinstr = 1; |
932e71cd AJ |
685 | goto set_EPC; |
686 | case EXCP_C2E: | |
687 | cause = 18; | |
688 | goto set_EPC; | |
92ceb440 LA |
689 | case EXCP_TLBRI: |
690 | cause = 19; | |
aea14095 | 691 | update_badinstr = 1; |
92ceb440 LA |
692 | goto set_EPC; |
693 | case EXCP_TLBXI: | |
694 | cause = 20; | |
695 | goto set_EPC; | |
b10ac204 YK |
696 | case EXCP_MSADIS: |
697 | cause = 21; | |
698 | update_badinstr = 1; | |
699 | goto set_EPC; | |
932e71cd AJ |
700 | case EXCP_MDMX: |
701 | cause = 22; | |
702 | goto set_EPC; | |
703 | case EXCP_DWATCH: | |
704 | cause = 23; | |
705 | /* XXX: TODO: manage defered watch exceptions */ | |
706 | goto set_EPC; | |
707 | case EXCP_MCHECK: | |
708 | cause = 24; | |
709 | goto set_EPC; | |
710 | case EXCP_THREAD: | |
711 | cause = 25; | |
712 | goto set_EPC; | |
853c3240 JL |
713 | case EXCP_DSPDIS: |
714 | cause = 26; | |
715 | goto set_EPC; | |
932e71cd AJ |
716 | case EXCP_CACHE: |
717 | cause = 30; | |
718 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
719 | offset = 0x100; | |
720 | } else { | |
721 | offset = 0x20000100; | |
722 | } | |
0eaef5aa | 723 | set_EPC: |
932e71cd | 724 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
32188a03 | 725 | env->CP0_EPC = exception_resume_pc(env); |
aea14095 LA |
726 | if (update_badinstr) { |
727 | set_badinstr_registers(env); | |
728 | } | |
932e71cd | 729 | if (env->hflags & MIPS_HFLAG_BMASK) { |
f45cb2f4 | 730 | env->CP0_Cause |= (1U << CP0Ca_BD); |
0eaef5aa | 731 | } else { |
f45cb2f4 | 732 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
0eaef5aa | 733 | } |
932e71cd | 734 | env->CP0_Status |= (1 << CP0St_EXL); |
d9224450 MR |
735 | if (env->insn_flags & ISA_MIPS3) { |
736 | env->hflags |= MIPS_HFLAG_64; | |
737 | } | |
738 | env->hflags |= MIPS_HFLAG_CP0; | |
932e71cd | 739 | env->hflags &= ~(MIPS_HFLAG_KSU); |
6af0bf9c | 740 | } |
932e71cd AJ |
741 | env->hflags &= ~MIPS_HFLAG_BMASK; |
742 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
743 | env->active_tc.PC = (int32_t)0xBFC00200; | |
744 | } else { | |
745 | env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); | |
6af0bf9c | 746 | } |
932e71cd | 747 | env->active_tc.PC += offset; |
bbfa8f72 | 748 | set_hflags_for_handler(env); |
932e71cd AJ |
749 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
750 | break; | |
751 | default: | |
27103424 AF |
752 | qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index); |
753 | printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index); | |
932e71cd AJ |
754 | exit(1); |
755 | } | |
27103424 | 756 | if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) { |
93fcfe39 | 757 | qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" |
932e71cd AJ |
758 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
759 | __func__, env->active_tc.PC, env->CP0_EPC, cause, | |
760 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, | |
761 | env->CP0_DEPC); | |
6af0bf9c | 762 | } |
932e71cd | 763 | #endif |
27103424 | 764 | cs->exception_index = EXCP_NONE; |
6af0bf9c | 765 | } |
2ee4aed8 | 766 | |
fa4faba4 RH |
767 | bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
768 | { | |
769 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
770 | MIPSCPU *cpu = MIPS_CPU(cs); | |
771 | CPUMIPSState *env = &cpu->env; | |
772 | ||
773 | if (cpu_mips_hw_interrupts_pending(env)) { | |
774 | /* Raise it */ | |
775 | cs->exception_index = EXCP_EXT_INTERRUPT; | |
776 | env->error_code = 0; | |
777 | mips_cpu_do_interrupt(cs); | |
778 | return true; | |
779 | } | |
780 | } | |
781 | return false; | |
782 | } | |
783 | ||
3c7b48b7 | 784 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 785 | void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) |
2ee4aed8 | 786 | { |
31b030d4 AF |
787 | MIPSCPU *cpu = mips_env_get_cpu(env); |
788 | CPUState *cs; | |
c227f099 | 789 | r4k_tlb_t *tlb; |
3b1c8be4 TS |
790 | target_ulong addr; |
791 | target_ulong end; | |
792 | uint8_t ASID = env->CP0_EntryHi & 0xFF; | |
793 | target_ulong mask; | |
2ee4aed8 | 794 | |
ead9360e | 795 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 796 | /* The qemu TLB is flushed when the ASID changes, so no need to |
2ee4aed8 FB |
797 | flush these entries again. */ |
798 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
799 | return; | |
800 | } | |
801 | ||
ead9360e | 802 | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { |
2ee4aed8 | 803 | /* For tlbwr, we can shadow the discarded entry into |
6958549d AJ |
804 | a new (fake) TLB entry, as long as the guest can not |
805 | tell that it's there. */ | |
ead9360e TS |
806 | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
807 | env->tlb->tlb_in_use++; | |
2ee4aed8 FB |
808 | return; |
809 | } | |
810 | ||
3b1c8be4 | 811 | /* 1k pages are not supported. */ |
f2e9ebef | 812 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 813 | if (tlb->V0) { |
31b030d4 | 814 | cs = CPU(cpu); |
f2e9ebef | 815 | addr = tlb->VPN & ~mask; |
d26bc211 | 816 | #if defined(TARGET_MIPS64) |
e034e2c3 | 817 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
818 | addr |= 0x3FFFFF0000000000ULL; |
819 | } | |
820 | #endif | |
3b1c8be4 TS |
821 | end = addr | (mask >> 1); |
822 | while (addr < end) { | |
31b030d4 | 823 | tlb_flush_page(cs, addr); |
3b1c8be4 TS |
824 | addr += TARGET_PAGE_SIZE; |
825 | } | |
826 | } | |
827 | if (tlb->V1) { | |
31b030d4 | 828 | cs = CPU(cpu); |
f2e9ebef | 829 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
d26bc211 | 830 | #if defined(TARGET_MIPS64) |
e034e2c3 | 831 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
832 | addr |= 0x3FFFFF0000000000ULL; |
833 | } | |
834 | #endif | |
3b1c8be4 | 835 | end = addr | mask; |
53715e48 | 836 | while (addr - 1 < end) { |
31b030d4 | 837 | tlb_flush_page(cs, addr); |
3b1c8be4 TS |
838 | addr += TARGET_PAGE_SIZE; |
839 | } | |
840 | } | |
2ee4aed8 | 841 | } |
3c7b48b7 | 842 | #endif |