[mirror_qemu.git] / target-mips / helper.c

/*
 *  MIPS emulation helpers for qemu.
 * 
 *  Copyright (c) 2004-2005 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"

/* MIPS32 4K MMU emulation */
#ifdef MIPS_USES_R4K_TLB
static int map_address (CPUState *env, target_ulong *physical, int *prot,
                        target_ulong address, int rw, int access_type)
{
    tlb_t *tlb;
    target_ulong tag;
    uint8_t ASID;
    int i, n;
    int ret;

    ret = -2;
    tag = address & 0xFFFFE000;
    ASID = env->CP0_EntryHi & 0xFF;
    for (i = 0; i < MIPS_TLB_NB; i++) {
        tlb = &env->tlb[i];
        /* Check ASID, virtual page number & size */
        if ((tlb->G == 1 || tlb->ASID == ASID) &&
            tlb->VPN == tag && address < tlb->end2) {
            /* TLB match */
            n = (address >> 12) & 1;
            /* Check access rights */
	    if (!(n ? tlb->V1 : tlb->V0))
                return -3;
	    if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
                *physical = tlb->PFN[n] | (address & 0xFFF);
                *prot = PAGE_READ;
                if (n ? tlb->D1 : tlb->D0)
                    *prot |= PAGE_WRITE;
                return 0;
            }
            return -4;
        }
    }

    return ret;
}
#endif

int get_physical_address (CPUState *env, target_ulong *physical, int *prot,
                          target_ulong address, int rw, int access_type)
{
    int user_mode;
    int ret;

    /* User mode can only access useg */
    user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
#if 0
    if (logfile) {
        fprintf(logfile, "user mode %d h %08x\n",
                user_mode, env->hflags);
    }
#endif
    if (user_mode && address > 0x7FFFFFFFUL)
        return -1;
    ret = 0;
    if (address < 0x80000000UL) {
        if (!(env->hflags & MIPS_HFLAG_ERL)) {
#ifdef MIPS_USES_R4K_TLB
            ret = map_address(env, physical, prot, address, rw, access_type);
#else
            *physical = address + 0x40000000UL;
            *prot = PAGE_READ | PAGE_WRITE;
#endif
        } else {
            *physical = address;
            *prot = PAGE_READ | PAGE_WRITE;
        }
    } else if (address < 0xA0000000UL) {
        /* kseg0 */
        /* XXX: check supervisor mode */
        *physical = address - 0x80000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < 0xC0000000UL) {
        /* kseg1 */
        /* XXX: check supervisor mode */
        *physical = address - 0xA0000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < 0xE0000000UL) {
        /* kseg2 */
#ifdef MIPS_USES_R4K_TLB
        ret = map_address(env, physical, prot, address, rw, access_type);
#else
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
#endif
    } else {
        /* kseg3 */
        /* XXX: check supervisor mode */
        /* XXX: debug segment is not emulated */
#ifdef MIPS_USES_R4K_TLB
        ret = map_address(env, physical, prot, address, rw, access_type);
#else
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
#endif
    }
#if 0
    if (logfile) {
        fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
                access_type, *physical, *prot, ret);
    }
#endif

    return ret;
}

#if defined(CONFIG_USER_ONLY) 
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    target_ulong phys_addr;
    int prot;

    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
        return -1;
    return phys_addr;
}

void cpu_mips_init_mmu (CPUState *env)
{
}
#endif /* !defined(CONFIG_USER_ONLY) */

int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int is_user, int is_softmmu)
{
    target_ulong physical;
    int prot;
    int exception = 0, error_code = 0;
    int access_type;
    int ret = 0;

    if (logfile) {
#if 0
        cpu_dump_state(env, logfile, fprintf, 0);
#endif
        fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
                __func__, env->PC, address, rw, is_user, is_softmmu);
    }

    rw &= 1;

    /* data access */
    /* XXX: put correct access by using cpu_restore_state()
       correctly */
    access_type = ACCESS_INT;
    if (env->user_mode_only) {
        /* user mode only emulation */
        ret = -2;
        goto do_fault;
    }
    ret = get_physical_address(env, &physical, &prot,
                               address, rw, access_type);
    if (logfile) {
        fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
                __func__, address, ret, physical, prot);
    }
    if (ret == 0) {
	ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot,
			   is_user, is_softmmu);
    } else if (ret < 0) {
    do_fault:
        switch (ret) {
        default:
        case -1:
            /* Reference to kernel address from user mode or supervisor mode */
            /* Reference to supervisor address from user mode */
            if (rw)
                exception = EXCP_AdES;
            else
                exception = EXCP_AdEL;
            break;
        case -2:
            /* No TLB match for a mapped address */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            error_code = 1;
            break;
        case -3:
            /* TLB match with no valid bit */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            break;
        case -4:
            /* TLB match but 'D' bit is cleared */
            exception = EXCP_LTLBL;
            break;
                
        }
        /* Raise exception */
        env->CP0_BadVAddr = address;
        env->CP0_Context = (env->CP0_Context & 0xff800000) |
	                   ((address >> 9) &   0x007ffff0);
        env->CP0_EntryHi =
            (env->CP0_EntryHi & 0xFF) | (address & 0xFFFFE000);
        env->exception_index = exception;
        env->error_code = error_code;
        ret = 1;
    }

    return ret;
}

void do_interrupt (CPUState *env)
{
    target_ulong pc, offset;
    int cause = -1;

    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
                __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
    }
    if (env->exception_index == EXCP_EXT_INTERRUPT &&
        (env->hflags & MIPS_HFLAG_DM))
        env->exception_index = EXCP_DINT;
    offset = 0x180;
    switch (env->exception_index) {
    case EXCP_DSS:
        env->CP0_Debug |= 1 << CP0DB_DSS;
        /* Debug single step cannot be raised inside a delay slot and
         * resume will always occur on the next instruction
         * (but we assume the pc has always been updated during
         *  code translation).
         */
        env->CP0_DEPC = env->PC;
        goto enter_debug_mode;
    case EXCP_DINT:
        env->CP0_Debug |= 1 << CP0DB_DINT;
        goto set_DEPC;
    case EXCP_DIB:
        env->CP0_Debug |= 1 << CP0DB_DIB;
        goto set_DEPC;
    case EXCP_DBp:
        env->CP0_Debug |= 1 << CP0DB_DBp;
        goto set_DEPC;
    case EXCP_DDBS:
        env->CP0_Debug |= 1 << CP0DB_DDBS;
        goto set_DEPC;
    case EXCP_DDBL:
        env->CP0_Debug |= 1 << CP0DB_DDBL;
        goto set_DEPC;
    set_DEPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
             * come back to the jump
             */
            env->CP0_DEPC = env->PC - 4;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_DEPC = env->PC;
        }
    enter_debug_mode:
        env->hflags |= MIPS_HFLAG_DM;
        /* EJTAG probe trap enable is not implemented... */
        pc = 0xBFC00480;
        break;
    case EXCP_RESET:
#ifdef MIPS_USES_R4K_TLB
        env->CP0_random = MIPS_TLB_NB - 1;
#endif
        env->CP0_Wired = 0;
        env->CP0_Config0 = MIPS_CONFIG0;
#if defined (MIPS_CONFIG1)
        env->CP0_Config1 = MIPS_CONFIG1;
#endif
#if defined (MIPS_CONFIG2)
        env->CP0_Config2 = MIPS_CONFIG2;
#endif
#if defined (MIPS_CONFIG3)
        env->CP0_Config3 = MIPS_CONFIG3;
#endif
        env->CP0_WatchLo = 0;
        env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
        goto set_error_EPC;
    case EXCP_SRESET:
        env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
            (1 << CP0St_SR);
        env->CP0_WatchLo = 0;
        goto set_error_EPC;
    case EXCP_NMI:
        env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
            (1 << CP0St_NMI);
    set_error_EPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
             * come back to the jump
             */
            env->CP0_ErrorEPC = env->PC - 4;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_ErrorEPC = env->PC;
        }
        env->hflags = MIPS_HFLAG_ERL;
        pc = 0xBFC00000;
        break;
    case EXCP_MCHECK:
        cause = 24;
        goto set_EPC;
    case EXCP_EXT_INTERRUPT:
        cause = 0;
        if (env->CP0_Cause & (1 << CP0Ca_IV))
            offset = 0x200;
        goto set_EPC;
    case EXCP_DWATCH:
        cause = 23;
        /* XXX: TODO: manage defered watch exceptions */
        goto set_EPC;
    case EXCP_AdEL:
    case EXCP_AdES:
        cause = 4;
        goto set_EPC;
    case EXCP_TLBL:
        cause = 2;
        if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
            offset = 0x000;
        goto set_EPC;
    case EXCP_IBE:
        cause = 6;
        goto set_EPC;
    case EXCP_DBE:
        cause = 7;
        goto set_EPC;
    case EXCP_SYSCALL:
        cause = 8;
        goto set_EPC;
    case EXCP_BREAK:
        cause = 9;
        goto set_EPC;
    case EXCP_RI:
        cause = 10;
        goto set_EPC;
    case EXCP_CpU:
        cause = 11;
        env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
        goto set_EPC;
    case EXCP_OVERFLOW:
        cause = 12;
        goto set_EPC;
    case EXCP_TRAP:
        cause = 13;
        goto set_EPC;
    case EXCP_LTLBL:
        cause = 1;
        goto set_EPC;
    case EXCP_TLBS:
        cause = 3;
        if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
            offset = 0x000;
        goto set_EPC;
    set_EPC:
        if (env->CP0_Status & (1 << CP0St_BEV)) {
            pc = 0xBFC00200;
        } else {
            pc = 0x80000000;
        }
        env->hflags |= MIPS_HFLAG_EXL;
        pc += offset;
        env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
             * come back to the jump
             */
            env->CP0_EPC = env->PC - 4;
            env->CP0_Cause |= 0x80000000;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_EPC = env->PC;
            env->CP0_Cause &= ~0x80000000;
        }
        break;
    default:
        if (logfile) {
            fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
                    env->exception_index);
        }
        printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
        exit(1);
    }
    env->PC = pc;
    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
                "    S %08x C %08x A %08x D %08x\n",
                __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
                env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
                env->CP0_DEPC);
    }
    env->exception_index = EXCP_NONE;
}
Commit	Line	Data
6af0bf9c FB	1	/*
	2	* MIPS emulation helpers for qemu.
	3	*
	4	* Copyright (c) 2004-2005 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
e37e863f FB	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
6af0bf9c FB	30
6af0bf9c FB	31	/* MIPS32 4K MMU emulation */
9fb63ac2	32	#ifdef MIPS_USES_R4K_TLB
6af0bf9c FB	33	static int map_address (CPUState env, target_ulong physical, int *prot,
	34	target_ulong address, int rw, int access_type)
	35	{
	36	tlb_t *tlb;
	37	target_ulong tag;
	38	uint8_t ASID;
	39	int i, n;
	40	int ret;
	41
	42	ret = -2;
3d9fb9fe FB	43	tag = address & 0xFFFFE000;
3d9fb9fe FB	44	ASID = env->CP0_EntryHi & 0xFF;
7a962d30	45	for (i = 0; i < MIPS_TLB_NB; i++) {
6af0bf9c FB	46	tlb = &env->tlb[i];
	47	/* Check ASID, virtual page number & size */
	48	if ((tlb->G == 1 \|\| tlb->ASID == ASID) &&
4ad40f36	49	tlb->VPN == tag && address < tlb->end2) {
6af0bf9c FB	50	/* TLB match */
	51	n = (address >> 12) & 1;
	52	/* Check access rights */
98c1b82b PB	53	if (!(n ? tlb->V1 : tlb->V0))
	54	return -3;
	55	if (rw == 0 \|\| (n ? tlb->D1 : tlb->D0)) {
6af0bf9c	56	*physical = tlb->PFN[n] \| (address & 0xFFF);
9fb63ac2	57	*prot = PAGE_READ;
98c1b82b	58	if (n ? tlb->D1 : tlb->D0)
9fb63ac2	59	*prot \|= PAGE_WRITE;
6af0bf9c	60	return 0;
6af0bf9c	61	}
98c1b82b	62	return -4;
6af0bf9c FB	63	}
	64	}
	65
	66	return ret;
	67	}
	68	#endif
	69
	70	int get_physical_address (CPUState env, target_ulong physical, int *prot,
	71	target_ulong address, int rw, int access_type)
	72	{
	73	int user_mode;
	74	int ret;
	75
	76	/* User mode can only access useg */
3d9fb9fe	77	user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
6af0bf9c FB	78	#if 0
	79	if (logfile) {
	80	fprintf(logfile, "user mode %d h %08x\n",
	81	user_mode, env->hflags);
	82	}
	83	#endif
	84	if (user_mode && address > 0x7FFFFFFFUL)
	85	return -1;
	86	ret = 0;
	87	if (address < 0x80000000UL) {
9fb63ac2 FB	88	if (!(env->hflags & MIPS_HFLAG_ERL)) {
	89	#ifdef MIPS_USES_R4K_TLB
	90	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	91	#else
	92	*physical = address + 0x40000000UL;
	93	*prot = PAGE_READ \| PAGE_WRITE;
	94	#endif
	95	} else {
	96	*physical = address;
	97	*prot = PAGE_READ \| PAGE_WRITE;
	98	}
	99	} else if (address < 0xA0000000UL) {
	100	/* kseg0 */
	101	/* XXX: check supervisor mode */
	102	*physical = address - 0x80000000UL;
	103	*prot = PAGE_READ \| PAGE_WRITE;
	104	} else if (address < 0xC0000000UL) {
	105	/* kseg1 */
	106	/* XXX: check supervisor mode */
	107	*physical = address - 0xA0000000UL;
	108	*prot = PAGE_READ \| PAGE_WRITE;
	109	} else if (address < 0xE0000000UL) {
	110	/* kseg2 */
9fb63ac2 FB	111	#ifdef MIPS_USES_R4K_TLB
9fb63ac2 FB	112	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	113	#else
	114	*physical = address;
	115	*prot = PAGE_READ \| PAGE_WRITE;
	116	#endif
	117	} else {
	118	/* kseg3 */
	119	/* XXX: check supervisor mode */
	120	/* XXX: debug segment is not emulated */
9fb63ac2 FB	121	#ifdef MIPS_USES_R4K_TLB
9fb63ac2 FB	122	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	123	#else
	124	*physical = address;
	125	*prot = PAGE_READ \| PAGE_WRITE;
	126	#endif
	127	}
	128	#if 0
	129	if (logfile) {
	130	fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
	131	access_type, physical, prot, ret);
	132	}
	133	#endif
	134
	135	return ret;
	136	}
	137
	138	#if defined(CONFIG_USER_ONLY)
	139	target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
	140	{
	141	return addr;
	142	}
	143	#else
	144	target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
	145	{
	146	target_ulong phys_addr;
	147	int prot;
	148
	149	if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
	150	return -1;
	151	return phys_addr;
	152	}
6af0bf9c FB	153
	154	void cpu_mips_init_mmu (CPUState *env)
	155	{
	156	}
6af0bf9c FB	157	#endif /* !defined(CONFIG_USER_ONLY) */
	158
	159	int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
	160	int is_user, int is_softmmu)
	161	{
	162	target_ulong physical;
	163	int prot;
	164	int exception = 0, error_code = 0;
	165	int access_type;
	166	int ret = 0;
	167
	168	if (logfile) {
4ad40f36	169	#if 0
6af0bf9c	170	cpu_dump_state(env, logfile, fprintf, 0);
4ad40f36	171	#endif
6af0bf9c FB	172	fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
	173	__func__, env->PC, address, rw, is_user, is_softmmu);
	174	}
4ad40f36 FB	175
	176	rw &= 1;
	177
6af0bf9c FB	178	/* data access */
	179	/* XXX: put correct access by using cpu_restore_state()
	180	correctly */
	181	access_type = ACCESS_INT;
	182	if (env->user_mode_only) {
	183	/* user mode only emulation */
	184	ret = -2;
	185	goto do_fault;
	186	}
	187	ret = get_physical_address(env, &physical, &prot,
	188	address, rw, access_type);
	189	if (logfile) {
	190	fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
	191	__func__, address, ret, physical, prot);
	192	}
	193	if (ret == 0) {
	194	ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot,
	195	is_user, is_softmmu);
	196	} else if (ret < 0) {
	197	do_fault:
	198	switch (ret) {
	199	default:
	200	case -1:
	201	/* Reference to kernel address from user mode or supervisor mode */
	202	/* Reference to supervisor address from user mode */
	203	if (rw)
	204	exception = EXCP_AdES;
	205	else
	206	exception = EXCP_AdEL;
	207	break;
	208	case -2:
	209	/* No TLB match for a mapped address */
	210	if (rw)
	211	exception = EXCP_TLBS;
	212	else
	213	exception = EXCP_TLBL;
	214	error_code = 1;
	215	break;
	216	case -3:
	217	/* TLB match with no valid bit */
	218	if (rw)
	219	exception = EXCP_TLBS;
	220	else
	221	exception = EXCP_TLBL;
6af0bf9c FB	222	break;
	223	case -4:
	224	/* TLB match but 'D' bit is cleared */
	225	exception = EXCP_LTLBL;
	226	break;
	227
	228	}
6af0bf9c FB	229	/* Raise exception */
6af0bf9c FB	230	env->CP0_BadVAddr = address;
85498508	231	env->CP0_Context = (env->CP0_Context & 0xff800000) \|
4ad40f36	232	((address >> 9) & 0x007ffff0);
6af0bf9c	233	env->CP0_EntryHi =
ba9a74da	234	(env->CP0_EntryHi & 0xFF) \| (address & 0xFFFFE000);
6af0bf9c FB	235	env->exception_index = exception;
	236	env->error_code = error_code;
	237	ret = 1;
	238	}
	239
	240	return ret;
	241	}
	242
	243	void do_interrupt (CPUState *env)
	244	{
	245	target_ulong pc, offset;
	246	int cause = -1;
	247
	248	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
	249	fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
	250	__func__, env->PC, env->CP0_EPC, cause, env->exception_index);
	251	}
	252	if (env->exception_index == EXCP_EXT_INTERRUPT &&
	253	(env->hflags & MIPS_HFLAG_DM))
	254	env->exception_index = EXCP_DINT;
	255	offset = 0x180;
	256	switch (env->exception_index) {
	257	case EXCP_DSS:
	258	env->CP0_Debug \|= 1 << CP0DB_DSS;
	259	/* Debug single step cannot be raised inside a delay slot and
	260	* resume will always occur on the next instruction
	261	* (but we assume the pc has always been updated during
	262	* code translation).
	263	*/
	264	env->CP0_DEPC = env->PC;
	265	goto enter_debug_mode;
	266	case EXCP_DINT:
	267	env->CP0_Debug \|= 1 << CP0DB_DINT;
	268	goto set_DEPC;
	269	case EXCP_DIB:
	270	env->CP0_Debug \|= 1 << CP0DB_DIB;
	271	goto set_DEPC;
	272	case EXCP_DBp:
	273	env->CP0_Debug \|= 1 << CP0DB_DBp;
	274	goto set_DEPC;
	275	case EXCP_DDBS:
	276	env->CP0_Debug \|= 1 << CP0DB_DDBS;
	277	goto set_DEPC;
	278	case EXCP_DDBL:
	279	env->CP0_Debug \|= 1 << CP0DB_DDBL;
	280	goto set_DEPC;
	281	set_DEPC:
4ad40f36	282	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c FB	283	/* If the exception was raised from a delay slot,
	284	* come back to the jump
	285	*/
	286	env->CP0_DEPC = env->PC - 4;
4ad40f36	287	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	288	} else {
	289	env->CP0_DEPC = env->PC;
	290	}
	291	enter_debug_mode:
	292	env->hflags \|= MIPS_HFLAG_DM;
	293	/* EJTAG probe trap enable is not implemented... */
	294	pc = 0xBFC00480;
	295	break;
	296	case EXCP_RESET:
9fb63ac2	297	#ifdef MIPS_USES_R4K_TLB
6af0bf9c FB	298	env->CP0_random = MIPS_TLB_NB - 1;
	299	#endif
	300	env->CP0_Wired = 0;
	301	env->CP0_Config0 = MIPS_CONFIG0;
	302	#if defined (MIPS_CONFIG1)
	303	env->CP0_Config1 = MIPS_CONFIG1;
	304	#endif
	305	#if defined (MIPS_CONFIG2)
	306	env->CP0_Config2 = MIPS_CONFIG2;
	307	#endif
	308	#if defined (MIPS_CONFIG3)
	309	env->CP0_Config3 = MIPS_CONFIG3;
	310	#endif
	311	env->CP0_WatchLo = 0;
	312	env->CP0_Status = (1 << CP0St_CU0) \| (1 << CP0St_BEV);
	313	goto set_error_EPC;
	314	case EXCP_SRESET:
	315	env->CP0_Status = (1 << CP0St_CU0) \| (1 << CP0St_BEV) \|
	316	(1 << CP0St_SR);
	317	env->CP0_WatchLo = 0;
	318	goto set_error_EPC;
	319	case EXCP_NMI:
	320	env->CP0_Status = (1 << CP0St_CU0) \| (1 << CP0St_BEV) \|
	321	(1 << CP0St_NMI);
	322	set_error_EPC:
4ad40f36	323	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c FB	324	/* If the exception was raised from a delay slot,
	325	* come back to the jump
	326	*/
	327	env->CP0_ErrorEPC = env->PC - 4;
ecd78a0a	328	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	329	} else {
	330	env->CP0_ErrorEPC = env->PC;
	331	}
4ad40f36	332	env->hflags = MIPS_HFLAG_ERL;
6af0bf9c FB	333	pc = 0xBFC00000;
	334	break;
	335	case EXCP_MCHECK:
	336	cause = 24;
	337	goto set_EPC;
	338	case EXCP_EXT_INTERRUPT:
	339	cause = 0;
	340	if (env->CP0_Cause & (1 << CP0Ca_IV))
	341	offset = 0x200;
	342	goto set_EPC;
	343	case EXCP_DWATCH:
	344	cause = 23;
	345	/* XXX: TODO: manage defered watch exceptions */
	346	goto set_EPC;
	347	case EXCP_AdEL:
	348	case EXCP_AdES:
	349	cause = 4;
	350	goto set_EPC;
	351	case EXCP_TLBL:
6af0bf9c FB	352	cause = 2;
	353	if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
	354	offset = 0x000;
	355	goto set_EPC;
	356	case EXCP_IBE:
	357	cause = 6;
	358	goto set_EPC;
	359	case EXCP_DBE:
	360	cause = 7;
	361	goto set_EPC;
	362	case EXCP_SYSCALL:
	363	cause = 8;
	364	goto set_EPC;
	365	case EXCP_BREAK:
	366	cause = 9;
	367	goto set_EPC;
	368	case EXCP_RI:
	369	cause = 10;
	370	goto set_EPC;
	371	case EXCP_CpU:
	372	cause = 11;
4ad40f36	373	env->CP0_Cause = (env->CP0_Cause & ~0x03000000) \| (env->error_code << 28);
6af0bf9c FB	374	goto set_EPC;
	375	case EXCP_OVERFLOW:
	376	cause = 12;
	377	goto set_EPC;
	378	case EXCP_TRAP:
	379	cause = 13;
	380	goto set_EPC;
	381	case EXCP_LTLBL:
	382	cause = 1;
	383	goto set_EPC;
	384	case EXCP_TLBS:
	385	cause = 3;
0d8aca8c FB	386	if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
	387	offset = 0x000;
	388	goto set_EPC;
6af0bf9c FB	389	set_EPC:
	390	if (env->CP0_Status & (1 << CP0St_BEV)) {
	391	pc = 0xBFC00200;
	392	} else {
	393	pc = 0x80000000;
	394	}
	395	env->hflags \|= MIPS_HFLAG_EXL;
	396	pc += offset;
	397	env->CP0_Cause = (env->CP0_Cause & ~0x7C) \| (cause << 2);
4ad40f36	398	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c FB	399	/* If the exception was raised from a delay slot,
	400	* come back to the jump
	401	*/
	402	env->CP0_EPC = env->PC - 4;
	403	env->CP0_Cause \|= 0x80000000;
4ad40f36	404	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	405	} else {
	406	env->CP0_EPC = env->PC;
	407	env->CP0_Cause &= ~0x80000000;
	408	}
	409	break;
	410	default:
	411	if (logfile) {
	412	fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
	413	env->exception_index);
	414	}
	415	printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
	416	exit(1);
	417	}
	418	env->PC = pc;
	419	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
	420	fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
	421	" S %08x C %08x A %08x D %08x\n",
	422	__func__, env->PC, env->CP0_EPC, cause, env->exception_index,
	423	env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
	424	env->CP0_DEPC);
	425	}
	426	env->exception_index = EXCP_NONE;
	427	}