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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
3 | * | |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
e37e863f FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <signal.h> | |
26 | #include <assert.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
6af0bf9c | 30 | |
43057ab1 FB |
31 | enum { |
32 | TLBRET_DIRTY = -4, | |
33 | TLBRET_INVALID = -3, | |
34 | TLBRET_NOMATCH = -2, | |
35 | TLBRET_BADADDR = -1, | |
36 | TLBRET_MATCH = 0 | |
37 | }; | |
38 | ||
29929e34 TS |
39 | /* no MMU emulation */ |
40 | int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, | |
6af0bf9c | 41 | target_ulong address, int rw, int access_type) |
29929e34 TS |
42 | { |
43 | *physical = address; | |
44 | *prot = PAGE_READ | PAGE_WRITE; | |
45 | return TLBRET_MATCH; | |
46 | } | |
47 | ||
48 | /* fixed mapping MMU emulation */ | |
49 | int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, | |
50 | target_ulong address, int rw, int access_type) | |
51 | { | |
52 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
53 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
54 | *physical = address + 0x40000000UL; | |
55 | else | |
56 | *physical = address; | |
57 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
58 | *physical = address & 0x1FFFFFFF; | |
59 | else | |
60 | *physical = address; | |
61 | ||
62 | *prot = PAGE_READ | PAGE_WRITE; | |
63 | return TLBRET_MATCH; | |
64 | } | |
65 | ||
66 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
67 | int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, | |
68 | target_ulong address, int rw, int access_type) | |
6af0bf9c | 69 | { |
925fd0f2 | 70 | uint8_t ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 71 | int i; |
6af0bf9c | 72 | |
814b9a47 | 73 | for (i = 0; i < env->tlb_in_use; i++) { |
29929e34 | 74 | r4k_tlb_t *tlb = &env->mmu.r4k.tlb[i]; |
3b1c8be4 | 75 | /* 1k pages are not supported. */ |
f2e9ebef | 76 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 77 | target_ulong tag = address & ~mask; |
f2e9ebef | 78 | target_ulong VPN = tlb->VPN & ~mask; |
100ce988 | 79 | #ifdef TARGET_MIPS64 |
e034e2c3 | 80 | tag &= env->SEGMask; |
100ce988 | 81 | #endif |
3b1c8be4 | 82 | |
6af0bf9c | 83 | /* Check ASID, virtual page number & size */ |
f2e9ebef | 84 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
6af0bf9c | 85 | /* TLB match */ |
f2e9ebef | 86 | int n = !!(address & mask & ~(mask >> 1)); |
6af0bf9c | 87 | /* Check access rights */ |
f2e9ebef | 88 | if (!(n ? tlb->V1 : tlb->V0)) |
43057ab1 | 89 | return TLBRET_INVALID; |
f2e9ebef | 90 | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
3b1c8be4 | 91 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
9fb63ac2 | 92 | *prot = PAGE_READ; |
98c1b82b | 93 | if (n ? tlb->D1 : tlb->D0) |
9fb63ac2 | 94 | *prot |= PAGE_WRITE; |
43057ab1 | 95 | return TLBRET_MATCH; |
6af0bf9c | 96 | } |
43057ab1 | 97 | return TLBRET_DIRTY; |
6af0bf9c FB |
98 | } |
99 | } | |
43057ab1 | 100 | return TLBRET_NOMATCH; |
6af0bf9c | 101 | } |
6af0bf9c | 102 | |
43057ab1 FB |
103 | static int get_physical_address (CPUState *env, target_ulong *physical, |
104 | int *prot, target_ulong address, | |
105 | int rw, int access_type) | |
6af0bf9c | 106 | { |
b4ab4b4e | 107 | /* User mode can only access useg/xuseg */ |
43057ab1 | 108 | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
b4ab4b4e TS |
109 | #ifdef TARGET_MIPS64 |
110 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
111 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
112 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
113 | #endif | |
43057ab1 FB |
114 | int ret = TLBRET_MATCH; |
115 | ||
6af0bf9c FB |
116 | #if 0 |
117 | if (logfile) { | |
118 | fprintf(logfile, "user mode %d h %08x\n", | |
119 | user_mode, env->hflags); | |
120 | } | |
121 | #endif | |
b4ab4b4e TS |
122 | |
123 | #ifdef TARGET_MIPS64 | |
124 | if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL) | |
125 | return TLBRET_BADADDR; | |
126 | #else | |
6af0bf9c | 127 | if (user_mode && address > 0x7FFFFFFFUL) |
43057ab1 | 128 | return TLBRET_BADADDR; |
b4ab4b4e TS |
129 | #endif |
130 | ||
131 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
132 | /* useg */ | |
133 | if (!(env->CP0_Status & (1 << CP0St_ERL) && user_mode)) { | |
29929e34 | 134 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
6af0bf9c | 135 | } else { |
29929e34 | 136 | *physical = address & 0xFFFFFFFF; |
6af0bf9c FB |
137 | *prot = PAGE_READ | PAGE_WRITE; |
138 | } | |
b4ab4b4e TS |
139 | #ifdef TARGET_MIPS64 |
140 | /* | |
141 | XXX: Assuming : | |
142 | - PABITS = 36 (correct for MIPS64R1) | |
b4ab4b4e TS |
143 | */ |
144 | } else if (address < 0x3FFFFFFFFFFFFFFFULL) { | |
145 | /* xuseg */ | |
e034e2c3 | 146 | if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
29929e34 | 147 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
b4ab4b4e TS |
148 | } else { |
149 | ret = TLBRET_BADADDR; | |
150 | } | |
151 | } else if (address < 0x7FFFFFFFFFFFFFFFULL) { | |
152 | /* xsseg */ | |
e034e2c3 | 153 | if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
29929e34 | 154 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
b4ab4b4e TS |
155 | } else { |
156 | ret = TLBRET_BADADDR; | |
157 | } | |
158 | } else if (address < 0xBFFFFFFFFFFFFFFFULL) { | |
159 | /* xkphys */ | |
160 | /* XXX: check supervisor mode */ | |
e034e2c3 | 161 | if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) |
b4ab4b4e | 162 | { |
e034e2c3 | 163 | *physical = address & 0X0000000FFFFFFFFFULL; |
b4ab4b4e TS |
164 | *prot = PAGE_READ | PAGE_WRITE; |
165 | } else { | |
166 | ret = TLBRET_BADADDR; | |
167 | } | |
168 | } else if (address < 0xFFFFFFFF7FFFFFFFULL) { | |
169 | /* xkseg */ | |
170 | /* XXX: check supervisor mode */ | |
e034e2c3 | 171 | if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { |
29929e34 | 172 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
b4ab4b4e TS |
173 | } else { |
174 | ret = TLBRET_BADADDR; | |
175 | } | |
176 | #endif | |
5dc4b744 | 177 | } else if (address < (int32_t)0xA0000000UL) { |
6af0bf9c FB |
178 | /* kseg0 */ |
179 | /* XXX: check supervisor mode */ | |
5dc4b744 | 180 | *physical = address - (int32_t)0x80000000UL; |
6af0bf9c | 181 | *prot = PAGE_READ | PAGE_WRITE; |
5dc4b744 | 182 | } else if (address < (int32_t)0xC0000000UL) { |
6af0bf9c FB |
183 | /* kseg1 */ |
184 | /* XXX: check supervisor mode */ | |
5dc4b744 | 185 | *physical = address - (int32_t)0xA0000000UL; |
6af0bf9c | 186 | *prot = PAGE_READ | PAGE_WRITE; |
5dc4b744 | 187 | } else if (address < (int32_t)0xE0000000UL) { |
6af0bf9c | 188 | /* kseg2 */ |
29929e34 | 189 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
6af0bf9c FB |
190 | } else { |
191 | /* kseg3 */ | |
192 | /* XXX: check supervisor mode */ | |
193 | /* XXX: debug segment is not emulated */ | |
29929e34 | 194 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
6af0bf9c FB |
195 | } |
196 | #if 0 | |
197 | if (logfile) { | |
3594c774 | 198 | fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n", |
c570fd16 | 199 | address, rw, access_type, *physical, *prot, ret); |
6af0bf9c FB |
200 | } |
201 | #endif | |
202 | ||
203 | return ret; | |
204 | } | |
205 | ||
206 | #if defined(CONFIG_USER_ONLY) | |
9b3c35e0 | 207 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
6af0bf9c FB |
208 | { |
209 | return addr; | |
210 | } | |
211 | #else | |
9b3c35e0 | 212 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
6af0bf9c FB |
213 | { |
214 | target_ulong phys_addr; | |
215 | int prot; | |
216 | ||
217 | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) | |
218 | return -1; | |
219 | return phys_addr; | |
220 | } | |
6af0bf9c FB |
221 | |
222 | void cpu_mips_init_mmu (CPUState *env) | |
223 | { | |
224 | } | |
6af0bf9c FB |
225 | #endif /* !defined(CONFIG_USER_ONLY) */ |
226 | ||
227 | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | |
228 | int is_user, int is_softmmu) | |
229 | { | |
230 | target_ulong physical; | |
231 | int prot; | |
232 | int exception = 0, error_code = 0; | |
233 | int access_type; | |
234 | int ret = 0; | |
235 | ||
236 | if (logfile) { | |
4ad40f36 | 237 | #if 0 |
6af0bf9c | 238 | cpu_dump_state(env, logfile, fprintf, 0); |
4ad40f36 | 239 | #endif |
3594c774 | 240 | fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n", |
6af0bf9c FB |
241 | __func__, env->PC, address, rw, is_user, is_softmmu); |
242 | } | |
4ad40f36 FB |
243 | |
244 | rw &= 1; | |
245 | ||
6af0bf9c FB |
246 | /* data access */ |
247 | /* XXX: put correct access by using cpu_restore_state() | |
248 | correctly */ | |
249 | access_type = ACCESS_INT; | |
250 | if (env->user_mode_only) { | |
251 | /* user mode only emulation */ | |
43057ab1 | 252 | ret = TLBRET_NOMATCH; |
6af0bf9c FB |
253 | goto do_fault; |
254 | } | |
255 | ret = get_physical_address(env, &physical, &prot, | |
256 | address, rw, access_type); | |
257 | if (logfile) { | |
3594c774 | 258 | fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n", |
6af0bf9c FB |
259 | __func__, address, ret, physical, prot); |
260 | } | |
43057ab1 FB |
261 | if (ret == TLBRET_MATCH) { |
262 | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, | |
263 | physical & TARGET_PAGE_MASK, prot, | |
264 | is_user, is_softmmu); | |
6af0bf9c FB |
265 | } else if (ret < 0) { |
266 | do_fault: | |
267 | switch (ret) { | |
268 | default: | |
43057ab1 | 269 | case TLBRET_BADADDR: |
6af0bf9c FB |
270 | /* Reference to kernel address from user mode or supervisor mode */ |
271 | /* Reference to supervisor address from user mode */ | |
272 | if (rw) | |
273 | exception = EXCP_AdES; | |
274 | else | |
275 | exception = EXCP_AdEL; | |
276 | break; | |
43057ab1 | 277 | case TLBRET_NOMATCH: |
6af0bf9c FB |
278 | /* No TLB match for a mapped address */ |
279 | if (rw) | |
280 | exception = EXCP_TLBS; | |
281 | else | |
282 | exception = EXCP_TLBL; | |
283 | error_code = 1; | |
284 | break; | |
43057ab1 | 285 | case TLBRET_INVALID: |
6af0bf9c FB |
286 | /* TLB match with no valid bit */ |
287 | if (rw) | |
288 | exception = EXCP_TLBS; | |
289 | else | |
290 | exception = EXCP_TLBL; | |
6af0bf9c | 291 | break; |
43057ab1 | 292 | case TLBRET_DIRTY: |
6af0bf9c FB |
293 | /* TLB match but 'D' bit is cleared */ |
294 | exception = EXCP_LTLBL; | |
295 | break; | |
296 | ||
297 | } | |
6af0bf9c FB |
298 | /* Raise exception */ |
299 | env->CP0_BadVAddr = address; | |
100ce988 | 300 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | |
4ad40f36 | 301 | ((address >> 9) & 0x007ffff0); |
6af0bf9c | 302 | env->CP0_EntryHi = |
43057ab1 | 303 | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
100ce988 | 304 | #ifdef TARGET_MIPS64 |
e034e2c3 TS |
305 | env->CP0_EntryHi &= env->SEGMask; |
306 | env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | | |
307 | ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) | | |
308 | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); | |
100ce988 | 309 | #endif |
6af0bf9c FB |
310 | env->exception_index = exception; |
311 | env->error_code = error_code; | |
312 | ret = 1; | |
313 | } | |
314 | ||
315 | return ret; | |
316 | } | |
317 | ||
ca7c2b1b TS |
318 | #if defined(CONFIG_USER_ONLY) |
319 | void do_interrupt (CPUState *env) | |
320 | { | |
321 | env->exception_index = EXCP_NONE; | |
322 | } | |
323 | #else | |
6af0bf9c FB |
324 | void do_interrupt (CPUState *env) |
325 | { | |
aa328add | 326 | target_ulong offset; |
6af0bf9c FB |
327 | int cause = -1; |
328 | ||
329 | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) { | |
3594c774 | 330 | fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n", |
6af0bf9c FB |
331 | __func__, env->PC, env->CP0_EPC, cause, env->exception_index); |
332 | } | |
333 | if (env->exception_index == EXCP_EXT_INTERRUPT && | |
334 | (env->hflags & MIPS_HFLAG_DM)) | |
335 | env->exception_index = EXCP_DINT; | |
336 | offset = 0x180; | |
337 | switch (env->exception_index) { | |
338 | case EXCP_DSS: | |
339 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
340 | /* Debug single step cannot be raised inside a delay slot and | |
341 | * resume will always occur on the next instruction | |
342 | * (but we assume the pc has always been updated during | |
343 | * code translation). | |
344 | */ | |
345 | env->CP0_DEPC = env->PC; | |
346 | goto enter_debug_mode; | |
347 | case EXCP_DINT: | |
348 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
349 | goto set_DEPC; | |
350 | case EXCP_DIB: | |
351 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
352 | goto set_DEPC; | |
353 | case EXCP_DBp: | |
354 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
355 | goto set_DEPC; | |
356 | case EXCP_DDBS: | |
357 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
358 | goto set_DEPC; | |
359 | case EXCP_DDBL: | |
360 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
6af0bf9c | 361 | set_DEPC: |
4ad40f36 | 362 | if (env->hflags & MIPS_HFLAG_BMASK) { |
6af0bf9c | 363 | /* If the exception was raised from a delay slot, |
aa328add | 364 | come back to the jump. */ |
6af0bf9c | 365 | env->CP0_DEPC = env->PC - 4; |
4ad40f36 | 366 | env->hflags &= ~MIPS_HFLAG_BMASK; |
6af0bf9c FB |
367 | } else { |
368 | env->CP0_DEPC = env->PC; | |
369 | } | |
370 | enter_debug_mode: | |
371 | env->hflags |= MIPS_HFLAG_DM; | |
6e473128 | 372 | env->hflags |= MIPS_HFLAG_64; |
24c7b0e3 | 373 | env->hflags &= ~MIPS_HFLAG_UM; |
6af0bf9c | 374 | /* EJTAG probe trap enable is not implemented... */ |
0a6de750 TS |
375 | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
376 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
5dc4b744 | 377 | env->PC = (int32_t)0xBFC00480; |
6af0bf9c FB |
378 | break; |
379 | case EXCP_RESET: | |
aa328add TS |
380 | cpu_reset(env); |
381 | break; | |
6af0bf9c | 382 | case EXCP_SRESET: |
24c7b0e3 | 383 | env->CP0_Status |= (1 << CP0St_SR); |
fd88b6ab | 384 | memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); |
6af0bf9c FB |
385 | goto set_error_EPC; |
386 | case EXCP_NMI: | |
24c7b0e3 | 387 | env->CP0_Status |= (1 << CP0St_NMI); |
6af0bf9c | 388 | set_error_EPC: |
4ad40f36 | 389 | if (env->hflags & MIPS_HFLAG_BMASK) { |
6af0bf9c | 390 | /* If the exception was raised from a delay slot, |
aa328add | 391 | come back to the jump. */ |
6af0bf9c | 392 | env->CP0_ErrorEPC = env->PC - 4; |
ecd78a0a | 393 | env->hflags &= ~MIPS_HFLAG_BMASK; |
6af0bf9c FB |
394 | } else { |
395 | env->CP0_ErrorEPC = env->PC; | |
396 | } | |
24c7b0e3 | 397 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
6e473128 | 398 | env->hflags |= MIPS_HFLAG_64; |
24c7b0e3 | 399 | env->hflags &= ~MIPS_HFLAG_UM; |
0a6de750 TS |
400 | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
401 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
5dc4b744 | 402 | env->PC = (int32_t)0xBFC00000; |
6af0bf9c FB |
403 | break; |
404 | case EXCP_MCHECK: | |
405 | cause = 24; | |
406 | goto set_EPC; | |
407 | case EXCP_EXT_INTERRUPT: | |
408 | cause = 0; | |
409 | if (env->CP0_Cause & (1 << CP0Ca_IV)) | |
410 | offset = 0x200; | |
411 | goto set_EPC; | |
412 | case EXCP_DWATCH: | |
413 | cause = 23; | |
414 | /* XXX: TODO: manage defered watch exceptions */ | |
415 | goto set_EPC; | |
416 | case EXCP_AdEL: | |
6af0bf9c FB |
417 | cause = 4; |
418 | goto set_EPC; | |
beb811bd TS |
419 | case EXCP_AdES: |
420 | cause = 5; | |
421 | goto set_EPC; | |
6af0bf9c | 422 | case EXCP_TLBL: |
6af0bf9c | 423 | cause = 2; |
100ce988 TS |
424 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
425 | #ifdef TARGET_MIPS64 | |
426 | int R = env->CP0_BadVAddr >> 62; | |
427 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
428 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
429 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
430 | ||
431 | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) | |
432 | offset = 0x080; | |
433 | else | |
434 | #endif | |
435 | offset = 0x000; | |
436 | } | |
6af0bf9c FB |
437 | goto set_EPC; |
438 | case EXCP_IBE: | |
439 | cause = 6; | |
440 | goto set_EPC; | |
441 | case EXCP_DBE: | |
442 | cause = 7; | |
443 | goto set_EPC; | |
444 | case EXCP_SYSCALL: | |
445 | cause = 8; | |
446 | goto set_EPC; | |
447 | case EXCP_BREAK: | |
448 | cause = 9; | |
449 | goto set_EPC; | |
450 | case EXCP_RI: | |
451 | cause = 10; | |
452 | goto set_EPC; | |
453 | case EXCP_CpU: | |
454 | cause = 11; | |
39d51eb8 TS |
455 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
456 | (env->error_code << CP0Ca_CE); | |
6af0bf9c FB |
457 | goto set_EPC; |
458 | case EXCP_OVERFLOW: | |
459 | cause = 12; | |
460 | goto set_EPC; | |
461 | case EXCP_TRAP: | |
462 | cause = 13; | |
463 | goto set_EPC; | |
5a5012ec TS |
464 | case EXCP_FPE: |
465 | cause = 15; | |
466 | goto set_EPC; | |
6af0bf9c FB |
467 | case EXCP_LTLBL: |
468 | cause = 1; | |
469 | goto set_EPC; | |
470 | case EXCP_TLBS: | |
471 | cause = 3; | |
100ce988 TS |
472 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
473 | #ifdef TARGET_MIPS64 | |
474 | int R = env->CP0_BadVAddr >> 62; | |
475 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
476 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
477 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
478 | ||
479 | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) | |
480 | offset = 0x080; | |
481 | else | |
482 | #endif | |
483 | offset = 0x000; | |
484 | } | |
6af0bf9c | 485 | set_EPC: |
24c7b0e3 TS |
486 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
487 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
488 | /* If the exception was raised from a delay slot, | |
489 | come back to the jump. */ | |
490 | env->CP0_EPC = env->PC - 4; | |
39d51eb8 | 491 | env->CP0_Cause |= (1 << CP0Ca_BD); |
24c7b0e3 TS |
492 | } else { |
493 | env->CP0_EPC = env->PC; | |
494 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
495 | } | |
24c7b0e3 | 496 | env->CP0_Status |= (1 << CP0St_EXL); |
6e473128 | 497 | env->hflags |= MIPS_HFLAG_64; |
24c7b0e3 | 498 | env->hflags &= ~MIPS_HFLAG_UM; |
6af0bf9c | 499 | } |
c53f4a62 | 500 | env->hflags &= ~MIPS_HFLAG_BMASK; |
aa328add | 501 | if (env->CP0_Status & (1 << CP0St_BEV)) { |
5dc4b744 | 502 | env->PC = (int32_t)0xBFC00200; |
aa328add | 503 | } else { |
acd858d9 | 504 | env->PC = (int32_t)(env->CP0_EBase & ~0x3ff); |
aa328add | 505 | } |
aa328add | 506 | env->PC += offset; |
e58c8ba5 | 507 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
6af0bf9c FB |
508 | break; |
509 | default: | |
510 | if (logfile) { | |
511 | fprintf(logfile, "Invalid MIPS exception %d. Exiting\n", | |
512 | env->exception_index); | |
513 | } | |
514 | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); | |
515 | exit(1); | |
516 | } | |
6af0bf9c | 517 | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) { |
3594c774 TS |
518 | fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n" |
519 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", | |
6af0bf9c FB |
520 | __func__, env->PC, env->CP0_EPC, cause, env->exception_index, |
521 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, | |
522 | env->CP0_DEPC); | |
523 | } | |
524 | env->exception_index = EXCP_NONE; | |
525 | } | |
ca7c2b1b | 526 | #endif /* !defined(CONFIG_USER_ONLY) */ |
2ee4aed8 | 527 | |
29929e34 | 528 | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) |
2ee4aed8 | 529 | { |
29929e34 | 530 | r4k_tlb_t *tlb; |
3b1c8be4 TS |
531 | target_ulong addr; |
532 | target_ulong end; | |
533 | uint8_t ASID = env->CP0_EntryHi & 0xFF; | |
534 | target_ulong mask; | |
2ee4aed8 | 535 | |
29929e34 | 536 | tlb = &env->mmu.r4k.tlb[idx]; |
f2e9ebef | 537 | /* The qemu TLB is flushed when the ASID changes, so no need to |
2ee4aed8 FB |
538 | flush these entries again. */ |
539 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
540 | return; | |
541 | } | |
542 | ||
543 | if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) { | |
544 | /* For tlbwr, we can shadow the discarded entry into | |
545 | a new (fake) TLB entry, as long as the guest can not | |
546 | tell that it's there. */ | |
29929e34 | 547 | env->mmu.r4k.tlb[env->tlb_in_use] = *tlb; |
2ee4aed8 FB |
548 | env->tlb_in_use++; |
549 | return; | |
550 | } | |
551 | ||
3b1c8be4 | 552 | /* 1k pages are not supported. */ |
f2e9ebef | 553 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 554 | if (tlb->V0) { |
f2e9ebef | 555 | addr = tlb->VPN & ~mask; |
100ce988 | 556 | #ifdef TARGET_MIPS64 |
e034e2c3 | 557 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
558 | addr |= 0x3FFFFF0000000000ULL; |
559 | } | |
560 | #endif | |
3b1c8be4 TS |
561 | end = addr | (mask >> 1); |
562 | while (addr < end) { | |
563 | tlb_flush_page (env, addr); | |
564 | addr += TARGET_PAGE_SIZE; | |
565 | } | |
566 | } | |
567 | if (tlb->V1) { | |
f2e9ebef | 568 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
100ce988 | 569 | #ifdef TARGET_MIPS64 |
e034e2c3 | 570 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
571 | addr |= 0x3FFFFF0000000000ULL; |
572 | } | |
573 | #endif | |
3b1c8be4 TS |
574 | end = addr | mask; |
575 | while (addr < end) { | |
576 | tlb_flush_page (env, addr); | |
577 | addr += TARGET_PAGE_SIZE; | |
578 | } | |
579 | } | |
2ee4aed8 | 580 | } |