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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
3 | * | |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
e37e863f FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <signal.h> | |
26 | #include <assert.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
6af0bf9c | 30 | |
43057ab1 FB |
31 | enum { |
32 | TLBRET_DIRTY = -4, | |
33 | TLBRET_INVALID = -3, | |
34 | TLBRET_NOMATCH = -2, | |
35 | TLBRET_BADADDR = -1, | |
36 | TLBRET_MATCH = 0 | |
37 | }; | |
38 | ||
29929e34 TS |
39 | /* no MMU emulation */ |
40 | int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, | |
6af0bf9c | 41 | target_ulong address, int rw, int access_type) |
29929e34 TS |
42 | { |
43 | *physical = address; | |
44 | *prot = PAGE_READ | PAGE_WRITE; | |
45 | return TLBRET_MATCH; | |
46 | } | |
47 | ||
48 | /* fixed mapping MMU emulation */ | |
49 | int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, | |
50 | target_ulong address, int rw, int access_type) | |
51 | { | |
52 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
53 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
54 | *physical = address + 0x40000000UL; | |
55 | else | |
56 | *physical = address; | |
57 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
58 | *physical = address & 0x1FFFFFFF; | |
59 | else | |
60 | *physical = address; | |
61 | ||
62 | *prot = PAGE_READ | PAGE_WRITE; | |
63 | return TLBRET_MATCH; | |
64 | } | |
65 | ||
66 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
67 | int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, | |
68 | target_ulong address, int rw, int access_type) | |
6af0bf9c | 69 | { |
925fd0f2 | 70 | uint8_t ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 71 | int i; |
6af0bf9c | 72 | |
814b9a47 | 73 | for (i = 0; i < env->tlb_in_use; i++) { |
29929e34 | 74 | r4k_tlb_t *tlb = &env->mmu.r4k.tlb[i]; |
3b1c8be4 | 75 | /* 1k pages are not supported. */ |
f2e9ebef | 76 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 77 | target_ulong tag = address & ~mask; |
f2e9ebef | 78 | target_ulong VPN = tlb->VPN & ~mask; |
3b1c8be4 | 79 | |
6af0bf9c | 80 | /* Check ASID, virtual page number & size */ |
f2e9ebef | 81 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
6af0bf9c | 82 | /* TLB match */ |
f2e9ebef | 83 | int n = !!(address & mask & ~(mask >> 1)); |
6af0bf9c | 84 | /* Check access rights */ |
f2e9ebef | 85 | if (!(n ? tlb->V1 : tlb->V0)) |
43057ab1 | 86 | return TLBRET_INVALID; |
f2e9ebef | 87 | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
3b1c8be4 | 88 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
9fb63ac2 | 89 | *prot = PAGE_READ; |
98c1b82b | 90 | if (n ? tlb->D1 : tlb->D0) |
9fb63ac2 | 91 | *prot |= PAGE_WRITE; |
43057ab1 | 92 | return TLBRET_MATCH; |
6af0bf9c | 93 | } |
43057ab1 | 94 | return TLBRET_DIRTY; |
6af0bf9c FB |
95 | } |
96 | } | |
43057ab1 | 97 | return TLBRET_NOMATCH; |
6af0bf9c | 98 | } |
6af0bf9c | 99 | |
43057ab1 FB |
100 | static int get_physical_address (CPUState *env, target_ulong *physical, |
101 | int *prot, target_ulong address, | |
102 | int rw, int access_type) | |
6af0bf9c | 103 | { |
b4ab4b4e | 104 | /* User mode can only access useg/xuseg */ |
43057ab1 | 105 | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
b4ab4b4e TS |
106 | #ifdef TARGET_MIPS64 |
107 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
108 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
109 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
110 | #endif | |
43057ab1 FB |
111 | int ret = TLBRET_MATCH; |
112 | ||
6af0bf9c FB |
113 | #if 0 |
114 | if (logfile) { | |
115 | fprintf(logfile, "user mode %d h %08x\n", | |
116 | user_mode, env->hflags); | |
117 | } | |
118 | #endif | |
b4ab4b4e TS |
119 | |
120 | #ifdef TARGET_MIPS64 | |
121 | if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL) | |
122 | return TLBRET_BADADDR; | |
123 | #else | |
6af0bf9c | 124 | if (user_mode && address > 0x7FFFFFFFUL) |
43057ab1 | 125 | return TLBRET_BADADDR; |
b4ab4b4e TS |
126 | #endif |
127 | ||
128 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
129 | /* useg */ | |
130 | if (!(env->CP0_Status & (1 << CP0St_ERL) && user_mode)) { | |
29929e34 | 131 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
6af0bf9c | 132 | } else { |
29929e34 | 133 | *physical = address & 0xFFFFFFFF; |
6af0bf9c FB |
134 | *prot = PAGE_READ | PAGE_WRITE; |
135 | } | |
b4ab4b4e TS |
136 | #ifdef TARGET_MIPS64 |
137 | /* | |
138 | XXX: Assuming : | |
139 | - PABITS = 36 (correct for MIPS64R1) | |
140 | - SEGBITS = 40 | |
141 | */ | |
142 | } else if (address < 0x3FFFFFFFFFFFFFFFULL) { | |
143 | /* xuseg */ | |
144 | if (UX && address < 0x000000FFFFFFFFFFULL) { | |
29929e34 | 145 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
b4ab4b4e TS |
146 | } else { |
147 | ret = TLBRET_BADADDR; | |
148 | } | |
149 | } else if (address < 0x7FFFFFFFFFFFFFFFULL) { | |
150 | /* xsseg */ | |
151 | if (SX && address < 0x400000FFFFFFFFFFULL) { | |
29929e34 | 152 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
b4ab4b4e TS |
153 | } else { |
154 | ret = TLBRET_BADADDR; | |
155 | } | |
156 | } else if (address < 0xBFFFFFFFFFFFFFFFULL) { | |
157 | /* xkphys */ | |
158 | /* XXX: check supervisor mode */ | |
159 | if (KX && (address & 0x03FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) | |
160 | { | |
161 | *physical = address & 0X000000FFFFFFFFFFULL; | |
162 | *prot = PAGE_READ | PAGE_WRITE; | |
163 | } else { | |
164 | ret = TLBRET_BADADDR; | |
165 | } | |
166 | } else if (address < 0xFFFFFFFF7FFFFFFFULL) { | |
167 | /* xkseg */ | |
168 | /* XXX: check supervisor mode */ | |
169 | if (KX && address < 0xC00000FF7FFFFFFFULL) { | |
29929e34 | 170 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
b4ab4b4e TS |
171 | } else { |
172 | ret = TLBRET_BADADDR; | |
173 | } | |
174 | #endif | |
5dc4b744 | 175 | } else if (address < (int32_t)0xA0000000UL) { |
6af0bf9c FB |
176 | /* kseg0 */ |
177 | /* XXX: check supervisor mode */ | |
5dc4b744 | 178 | *physical = address - (int32_t)0x80000000UL; |
6af0bf9c | 179 | *prot = PAGE_READ | PAGE_WRITE; |
5dc4b744 | 180 | } else if (address < (int32_t)0xC0000000UL) { |
6af0bf9c FB |
181 | /* kseg1 */ |
182 | /* XXX: check supervisor mode */ | |
5dc4b744 | 183 | *physical = address - (int32_t)0xA0000000UL; |
6af0bf9c | 184 | *prot = PAGE_READ | PAGE_WRITE; |
5dc4b744 | 185 | } else if (address < (int32_t)0xE0000000UL) { |
6af0bf9c | 186 | /* kseg2 */ |
29929e34 | 187 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
6af0bf9c FB |
188 | } else { |
189 | /* kseg3 */ | |
190 | /* XXX: check supervisor mode */ | |
191 | /* XXX: debug segment is not emulated */ | |
29929e34 | 192 | ret = env->map_address(env, physical, prot, address, rw, access_type); |
6af0bf9c FB |
193 | } |
194 | #if 0 | |
195 | if (logfile) { | |
3594c774 | 196 | fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n", |
c570fd16 | 197 | address, rw, access_type, *physical, *prot, ret); |
6af0bf9c FB |
198 | } |
199 | #endif | |
200 | ||
201 | return ret; | |
202 | } | |
203 | ||
204 | #if defined(CONFIG_USER_ONLY) | |
9b3c35e0 | 205 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
6af0bf9c FB |
206 | { |
207 | return addr; | |
208 | } | |
209 | #else | |
9b3c35e0 | 210 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
6af0bf9c FB |
211 | { |
212 | target_ulong phys_addr; | |
213 | int prot; | |
214 | ||
215 | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) | |
216 | return -1; | |
217 | return phys_addr; | |
218 | } | |
6af0bf9c FB |
219 | |
220 | void cpu_mips_init_mmu (CPUState *env) | |
221 | { | |
222 | } | |
6af0bf9c FB |
223 | #endif /* !defined(CONFIG_USER_ONLY) */ |
224 | ||
225 | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | |
226 | int is_user, int is_softmmu) | |
227 | { | |
228 | target_ulong physical; | |
229 | int prot; | |
230 | int exception = 0, error_code = 0; | |
231 | int access_type; | |
232 | int ret = 0; | |
233 | ||
234 | if (logfile) { | |
4ad40f36 | 235 | #if 0 |
6af0bf9c | 236 | cpu_dump_state(env, logfile, fprintf, 0); |
4ad40f36 | 237 | #endif |
3594c774 | 238 | fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n", |
6af0bf9c FB |
239 | __func__, env->PC, address, rw, is_user, is_softmmu); |
240 | } | |
4ad40f36 FB |
241 | |
242 | rw &= 1; | |
243 | ||
6af0bf9c FB |
244 | /* data access */ |
245 | /* XXX: put correct access by using cpu_restore_state() | |
246 | correctly */ | |
247 | access_type = ACCESS_INT; | |
248 | if (env->user_mode_only) { | |
249 | /* user mode only emulation */ | |
43057ab1 | 250 | ret = TLBRET_NOMATCH; |
6af0bf9c FB |
251 | goto do_fault; |
252 | } | |
253 | ret = get_physical_address(env, &physical, &prot, | |
254 | address, rw, access_type); | |
255 | if (logfile) { | |
3594c774 | 256 | fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n", |
6af0bf9c FB |
257 | __func__, address, ret, physical, prot); |
258 | } | |
43057ab1 FB |
259 | if (ret == TLBRET_MATCH) { |
260 | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, | |
261 | physical & TARGET_PAGE_MASK, prot, | |
262 | is_user, is_softmmu); | |
6af0bf9c FB |
263 | } else if (ret < 0) { |
264 | do_fault: | |
265 | switch (ret) { | |
266 | default: | |
43057ab1 | 267 | case TLBRET_BADADDR: |
6af0bf9c FB |
268 | /* Reference to kernel address from user mode or supervisor mode */ |
269 | /* Reference to supervisor address from user mode */ | |
270 | if (rw) | |
271 | exception = EXCP_AdES; | |
272 | else | |
273 | exception = EXCP_AdEL; | |
274 | break; | |
43057ab1 | 275 | case TLBRET_NOMATCH: |
6af0bf9c FB |
276 | /* No TLB match for a mapped address */ |
277 | if (rw) | |
278 | exception = EXCP_TLBS; | |
279 | else | |
280 | exception = EXCP_TLBL; | |
281 | error_code = 1; | |
282 | break; | |
43057ab1 | 283 | case TLBRET_INVALID: |
6af0bf9c FB |
284 | /* TLB match with no valid bit */ |
285 | if (rw) | |
286 | exception = EXCP_TLBS; | |
287 | else | |
288 | exception = EXCP_TLBL; | |
6af0bf9c | 289 | break; |
43057ab1 | 290 | case TLBRET_DIRTY: |
6af0bf9c FB |
291 | /* TLB match but 'D' bit is cleared */ |
292 | exception = EXCP_LTLBL; | |
293 | break; | |
294 | ||
295 | } | |
6af0bf9c FB |
296 | /* Raise exception */ |
297 | env->CP0_BadVAddr = address; | |
85498508 | 298 | env->CP0_Context = (env->CP0_Context & 0xff800000) | |
4ad40f36 | 299 | ((address >> 9) & 0x007ffff0); |
6af0bf9c | 300 | env->CP0_EntryHi = |
43057ab1 | 301 | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
6af0bf9c FB |
302 | env->exception_index = exception; |
303 | env->error_code = error_code; | |
304 | ret = 1; | |
305 | } | |
306 | ||
307 | return ret; | |
308 | } | |
309 | ||
ca7c2b1b TS |
310 | #if defined(CONFIG_USER_ONLY) |
311 | void do_interrupt (CPUState *env) | |
312 | { | |
313 | env->exception_index = EXCP_NONE; | |
314 | } | |
315 | #else | |
6af0bf9c FB |
316 | void do_interrupt (CPUState *env) |
317 | { | |
aa328add | 318 | target_ulong offset; |
6af0bf9c FB |
319 | int cause = -1; |
320 | ||
321 | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) { | |
3594c774 | 322 | fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n", |
6af0bf9c FB |
323 | __func__, env->PC, env->CP0_EPC, cause, env->exception_index); |
324 | } | |
325 | if (env->exception_index == EXCP_EXT_INTERRUPT && | |
326 | (env->hflags & MIPS_HFLAG_DM)) | |
327 | env->exception_index = EXCP_DINT; | |
328 | offset = 0x180; | |
329 | switch (env->exception_index) { | |
330 | case EXCP_DSS: | |
331 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
332 | /* Debug single step cannot be raised inside a delay slot and | |
333 | * resume will always occur on the next instruction | |
334 | * (but we assume the pc has always been updated during | |
335 | * code translation). | |
336 | */ | |
337 | env->CP0_DEPC = env->PC; | |
338 | goto enter_debug_mode; | |
339 | case EXCP_DINT: | |
340 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
341 | goto set_DEPC; | |
342 | case EXCP_DIB: | |
343 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
344 | goto set_DEPC; | |
345 | case EXCP_DBp: | |
346 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
347 | goto set_DEPC; | |
348 | case EXCP_DDBS: | |
349 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
350 | goto set_DEPC; | |
351 | case EXCP_DDBL: | |
352 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
6af0bf9c | 353 | set_DEPC: |
4ad40f36 | 354 | if (env->hflags & MIPS_HFLAG_BMASK) { |
6af0bf9c | 355 | /* If the exception was raised from a delay slot, |
aa328add | 356 | come back to the jump. */ |
6af0bf9c | 357 | env->CP0_DEPC = env->PC - 4; |
4ad40f36 | 358 | env->hflags &= ~MIPS_HFLAG_BMASK; |
6af0bf9c FB |
359 | } else { |
360 | env->CP0_DEPC = env->PC; | |
361 | } | |
362 | enter_debug_mode: | |
363 | env->hflags |= MIPS_HFLAG_DM; | |
24c7b0e3 | 364 | env->hflags &= ~MIPS_HFLAG_UM; |
6af0bf9c | 365 | /* EJTAG probe trap enable is not implemented... */ |
0a6de750 TS |
366 | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
367 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
5dc4b744 | 368 | env->PC = (int32_t)0xBFC00480; |
6af0bf9c FB |
369 | break; |
370 | case EXCP_RESET: | |
aa328add TS |
371 | cpu_reset(env); |
372 | break; | |
6af0bf9c | 373 | case EXCP_SRESET: |
24c7b0e3 | 374 | env->CP0_Status |= (1 << CP0St_SR); |
6af0bf9c FB |
375 | env->CP0_WatchLo = 0; |
376 | goto set_error_EPC; | |
377 | case EXCP_NMI: | |
24c7b0e3 | 378 | env->CP0_Status |= (1 << CP0St_NMI); |
6af0bf9c | 379 | set_error_EPC: |
4ad40f36 | 380 | if (env->hflags & MIPS_HFLAG_BMASK) { |
6af0bf9c | 381 | /* If the exception was raised from a delay slot, |
aa328add | 382 | come back to the jump. */ |
6af0bf9c | 383 | env->CP0_ErrorEPC = env->PC - 4; |
ecd78a0a | 384 | env->hflags &= ~MIPS_HFLAG_BMASK; |
6af0bf9c FB |
385 | } else { |
386 | env->CP0_ErrorEPC = env->PC; | |
387 | } | |
24c7b0e3 TS |
388 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
389 | env->hflags &= ~MIPS_HFLAG_UM; | |
0a6de750 TS |
390 | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
391 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
5dc4b744 | 392 | env->PC = (int32_t)0xBFC00000; |
6af0bf9c FB |
393 | break; |
394 | case EXCP_MCHECK: | |
395 | cause = 24; | |
396 | goto set_EPC; | |
397 | case EXCP_EXT_INTERRUPT: | |
398 | cause = 0; | |
399 | if (env->CP0_Cause & (1 << CP0Ca_IV)) | |
400 | offset = 0x200; | |
401 | goto set_EPC; | |
402 | case EXCP_DWATCH: | |
403 | cause = 23; | |
404 | /* XXX: TODO: manage defered watch exceptions */ | |
405 | goto set_EPC; | |
406 | case EXCP_AdEL: | |
6af0bf9c FB |
407 | cause = 4; |
408 | goto set_EPC; | |
beb811bd TS |
409 | case EXCP_AdES: |
410 | cause = 5; | |
411 | goto set_EPC; | |
6af0bf9c | 412 | case EXCP_TLBL: |
6af0bf9c | 413 | cause = 2; |
24c7b0e3 | 414 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) |
6af0bf9c FB |
415 | offset = 0x000; |
416 | goto set_EPC; | |
417 | case EXCP_IBE: | |
418 | cause = 6; | |
419 | goto set_EPC; | |
420 | case EXCP_DBE: | |
421 | cause = 7; | |
422 | goto set_EPC; | |
423 | case EXCP_SYSCALL: | |
424 | cause = 8; | |
425 | goto set_EPC; | |
426 | case EXCP_BREAK: | |
427 | cause = 9; | |
428 | goto set_EPC; | |
429 | case EXCP_RI: | |
430 | cause = 10; | |
431 | goto set_EPC; | |
432 | case EXCP_CpU: | |
433 | cause = 11; | |
39d51eb8 TS |
434 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
435 | (env->error_code << CP0Ca_CE); | |
6af0bf9c FB |
436 | goto set_EPC; |
437 | case EXCP_OVERFLOW: | |
438 | cause = 12; | |
439 | goto set_EPC; | |
440 | case EXCP_TRAP: | |
441 | cause = 13; | |
442 | goto set_EPC; | |
5a5012ec TS |
443 | case EXCP_FPE: |
444 | cause = 15; | |
445 | goto set_EPC; | |
6af0bf9c FB |
446 | case EXCP_LTLBL: |
447 | cause = 1; | |
448 | goto set_EPC; | |
449 | case EXCP_TLBS: | |
450 | cause = 3; | |
24c7b0e3 | 451 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) |
0d8aca8c | 452 | offset = 0x000; |
6af0bf9c | 453 | set_EPC: |
24c7b0e3 TS |
454 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
455 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
456 | /* If the exception was raised from a delay slot, | |
457 | come back to the jump. */ | |
458 | env->CP0_EPC = env->PC - 4; | |
39d51eb8 | 459 | env->CP0_Cause |= (1 << CP0Ca_BD); |
24c7b0e3 TS |
460 | } else { |
461 | env->CP0_EPC = env->PC; | |
462 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
463 | } | |
24c7b0e3 TS |
464 | env->CP0_Status |= (1 << CP0St_EXL); |
465 | env->hflags &= ~MIPS_HFLAG_UM; | |
6af0bf9c | 466 | } |
c53f4a62 | 467 | env->hflags &= ~MIPS_HFLAG_BMASK; |
aa328add | 468 | if (env->CP0_Status & (1 << CP0St_BEV)) { |
5dc4b744 | 469 | env->PC = (int32_t)0xBFC00200; |
aa328add | 470 | } else { |
acd858d9 | 471 | env->PC = (int32_t)(env->CP0_EBase & ~0x3ff); |
aa328add | 472 | } |
aa328add | 473 | env->PC += offset; |
e58c8ba5 | 474 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
6af0bf9c FB |
475 | break; |
476 | default: | |
477 | if (logfile) { | |
478 | fprintf(logfile, "Invalid MIPS exception %d. Exiting\n", | |
479 | env->exception_index); | |
480 | } | |
481 | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); | |
482 | exit(1); | |
483 | } | |
6af0bf9c | 484 | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) { |
3594c774 TS |
485 | fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n" |
486 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", | |
6af0bf9c FB |
487 | __func__, env->PC, env->CP0_EPC, cause, env->exception_index, |
488 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, | |
489 | env->CP0_DEPC); | |
490 | } | |
491 | env->exception_index = EXCP_NONE; | |
492 | } | |
ca7c2b1b | 493 | #endif /* !defined(CONFIG_USER_ONLY) */ |
2ee4aed8 | 494 | |
29929e34 | 495 | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) |
2ee4aed8 | 496 | { |
29929e34 | 497 | r4k_tlb_t *tlb; |
3b1c8be4 TS |
498 | target_ulong addr; |
499 | target_ulong end; | |
500 | uint8_t ASID = env->CP0_EntryHi & 0xFF; | |
501 | target_ulong mask; | |
2ee4aed8 | 502 | |
29929e34 | 503 | tlb = &env->mmu.r4k.tlb[idx]; |
f2e9ebef | 504 | /* The qemu TLB is flushed when the ASID changes, so no need to |
2ee4aed8 FB |
505 | flush these entries again. */ |
506 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
507 | return; | |
508 | } | |
509 | ||
510 | if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) { | |
511 | /* For tlbwr, we can shadow the discarded entry into | |
512 | a new (fake) TLB entry, as long as the guest can not | |
513 | tell that it's there. */ | |
29929e34 | 514 | env->mmu.r4k.tlb[env->tlb_in_use] = *tlb; |
2ee4aed8 FB |
515 | env->tlb_in_use++; |
516 | return; | |
517 | } | |
518 | ||
3b1c8be4 | 519 | /* 1k pages are not supported. */ |
f2e9ebef | 520 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 521 | if (tlb->V0) { |
f2e9ebef | 522 | addr = tlb->VPN & ~mask; |
3b1c8be4 TS |
523 | end = addr | (mask >> 1); |
524 | while (addr < end) { | |
525 | tlb_flush_page (env, addr); | |
526 | addr += TARGET_PAGE_SIZE; | |
527 | } | |
528 | } | |
529 | if (tlb->V1) { | |
f2e9ebef | 530 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
3b1c8be4 TS |
531 | end = addr | mask; |
532 | while (addr < end) { | |
533 | tlb_flush_page (env, addr); | |
534 | addr += TARGET_PAGE_SIZE; | |
535 | } | |
536 | } | |
2ee4aed8 | 537 | } |