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e2132e0b SL |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * KVM/MIPS: MIPS specific KVM APIs | |
7 | * | |
8 | * Copyright (C) 2012-2014 Imagination Technologies Ltd. | |
9 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
10 | */ | |
11 | ||
c684822a | 12 | #include "qemu/osdep.h" |
e2132e0b SL |
13 | #include <sys/ioctl.h> |
14 | #include <sys/mman.h> | |
15 | ||
16 | #include <linux/kvm.h> | |
17 | ||
18 | #include "qemu-common.h" | |
19 | #include "qemu/error-report.h" | |
20 | #include "qemu/timer.h" | |
21 | #include "sysemu/sysemu.h" | |
22 | #include "sysemu/kvm.h" | |
23 | #include "cpu.h" | |
24 | #include "sysemu/cpus.h" | |
25 | #include "kvm_mips.h" | |
4c663752 | 26 | #include "exec/memattrs.h" |
e2132e0b SL |
27 | |
28 | #define DEBUG_KVM 0 | |
29 | ||
30 | #define DPRINTF(fmt, ...) \ | |
31 | do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0) | |
32 | ||
33 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { | |
34 | KVM_CAP_LAST_INFO | |
35 | }; | |
36 | ||
37 | static void kvm_mips_update_state(void *opaque, int running, RunState state); | |
38 | ||
39 | unsigned long kvm_arch_vcpu_id(CPUState *cs) | |
40 | { | |
41 | return cs->cpu_index; | |
42 | } | |
43 | ||
b16565b3 | 44 | int kvm_arch_init(MachineState *ms, KVMState *s) |
e2132e0b SL |
45 | { |
46 | /* MIPS has 128 signals */ | |
47 | kvm_set_sigmask_len(s, 16); | |
48 | ||
49 | DPRINTF("%s\n", __func__); | |
50 | return 0; | |
51 | } | |
52 | ||
53 | int kvm_arch_init_vcpu(CPUState *cs) | |
54 | { | |
55 | int ret = 0; | |
56 | ||
57 | qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); | |
58 | ||
59 | DPRINTF("%s\n", __func__); | |
60 | return ret; | |
61 | } | |
62 | ||
63 | void kvm_mips_reset_vcpu(MIPSCPU *cpu) | |
64 | { | |
0e928b12 JH |
65 | CPUMIPSState *env = &cpu->env; |
66 | ||
67 | if (env->CP0_Config1 & (1 << CP0C1_FP)) { | |
68 | fprintf(stderr, "Warning: FPU not supported with KVM, disabling\n"); | |
69 | env->CP0_Config1 &= ~(1 << CP0C1_FP); | |
70 | } | |
71 | ||
e2132e0b SL |
72 | DPRINTF("%s\n", __func__); |
73 | } | |
74 | ||
75 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) | |
76 | { | |
77 | DPRINTF("%s\n", __func__); | |
78 | return 0; | |
79 | } | |
80 | ||
81 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) | |
82 | { | |
83 | DPRINTF("%s\n", __func__); | |
84 | return 0; | |
85 | } | |
86 | ||
87 | static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu) | |
88 | { | |
89 | CPUMIPSState *env = &cpu->env; | |
90 | ||
e2132e0b SL |
91 | return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)); |
92 | } | |
93 | ||
94 | ||
95 | void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) | |
96 | { | |
97 | MIPSCPU *cpu = MIPS_CPU(cs); | |
98 | int r; | |
99 | struct kvm_mips_interrupt intr; | |
100 | ||
4b8523ee JK |
101 | qemu_mutex_lock_iothread(); |
102 | ||
e2132e0b SL |
103 | if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
104 | cpu_mips_io_interrupts_pending(cpu)) { | |
105 | intr.cpu = -1; | |
106 | intr.irq = 2; | |
107 | r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); | |
108 | if (r < 0) { | |
109 | error_report("%s: cpu %d: failed to inject IRQ %x", | |
110 | __func__, cs->cpu_index, intr.irq); | |
111 | } | |
112 | } | |
4b8523ee JK |
113 | |
114 | qemu_mutex_unlock_iothread(); | |
e2132e0b SL |
115 | } |
116 | ||
4c663752 | 117 | MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) |
e2132e0b | 118 | { |
4c663752 | 119 | return MEMTXATTRS_UNSPECIFIED; |
e2132e0b SL |
120 | } |
121 | ||
122 | int kvm_arch_process_async_events(CPUState *cs) | |
123 | { | |
124 | return cs->halted; | |
125 | } | |
126 | ||
127 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) | |
128 | { | |
129 | int ret; | |
130 | ||
131 | DPRINTF("%s\n", __func__); | |
132 | switch (run->exit_reason) { | |
133 | default: | |
134 | error_report("%s: unknown exit reason %d", | |
135 | __func__, run->exit_reason); | |
136 | ret = -1; | |
137 | break; | |
138 | } | |
139 | ||
140 | return ret; | |
141 | } | |
142 | ||
143 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) | |
144 | { | |
145 | DPRINTF("%s\n", __func__); | |
146 | return true; | |
147 | } | |
148 | ||
149 | int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr) | |
150 | { | |
151 | DPRINTF("%s\n", __func__); | |
152 | return 1; | |
153 | } | |
154 | ||
155 | int kvm_arch_on_sigbus(int code, void *addr) | |
156 | { | |
157 | DPRINTF("%s\n", __func__); | |
158 | return 1; | |
159 | } | |
160 | ||
161 | void kvm_arch_init_irq_routing(KVMState *s) | |
162 | { | |
163 | } | |
164 | ||
165 | int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level) | |
166 | { | |
167 | CPUState *cs = CPU(cpu); | |
168 | struct kvm_mips_interrupt intr; | |
169 | ||
170 | if (!kvm_enabled()) { | |
171 | return 0; | |
172 | } | |
173 | ||
174 | intr.cpu = -1; | |
175 | ||
176 | if (level) { | |
177 | intr.irq = irq; | |
178 | } else { | |
179 | intr.irq = -irq; | |
180 | } | |
181 | ||
182 | kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); | |
183 | ||
184 | return 0; | |
185 | } | |
186 | ||
187 | int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) | |
188 | { | |
189 | CPUState *cs = current_cpu; | |
190 | CPUState *dest_cs = CPU(cpu); | |
191 | struct kvm_mips_interrupt intr; | |
192 | ||
193 | if (!kvm_enabled()) { | |
194 | return 0; | |
195 | } | |
196 | ||
197 | intr.cpu = dest_cs->cpu_index; | |
198 | ||
199 | if (level) { | |
200 | intr.irq = irq; | |
201 | } else { | |
202 | intr.irq = -irq; | |
203 | } | |
204 | ||
205 | DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq); | |
206 | ||
207 | kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | #define MIPS_CP0_32(_R, _S) \ | |
5a2db896 | 213 | (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) |
e2132e0b SL |
214 | |
215 | #define MIPS_CP0_64(_R, _S) \ | |
5a2db896 | 216 | (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) |
e2132e0b SL |
217 | |
218 | #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) | |
219 | #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) | |
220 | #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) | |
221 | #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) | |
222 | #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) | |
223 | #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) | |
224 | #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) | |
225 | #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) | |
226 | #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) | |
227 | #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) | |
228 | #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) | |
229 | #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) | |
230 | #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) | |
461a1582 | 231 | #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) |
03cbfd7b JH |
232 | #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) |
233 | #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) | |
234 | #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) | |
235 | #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) | |
236 | #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) | |
237 | #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) | |
e2132e0b SL |
238 | #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) |
239 | ||
e2132e0b SL |
240 | static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, |
241 | int32_t *addr) | |
242 | { | |
e2132e0b SL |
243 | struct kvm_one_reg cp0reg = { |
244 | .id = reg_id, | |
f8b3e48b | 245 | .addr = (uintptr_t)addr |
e2132e0b SL |
246 | }; |
247 | ||
248 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); | |
249 | } | |
250 | ||
251 | static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id, | |
252 | target_ulong *addr) | |
253 | { | |
254 | uint64_t val64 = *addr; | |
255 | struct kvm_one_reg cp0reg = { | |
256 | .id = reg_id, | |
257 | .addr = (uintptr_t)&val64 | |
258 | }; | |
259 | ||
260 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); | |
261 | } | |
262 | ||
263 | static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id, | |
264 | uint64_t *addr) | |
265 | { | |
266 | struct kvm_one_reg cp0reg = { | |
267 | .id = reg_id, | |
268 | .addr = (uintptr_t)addr | |
269 | }; | |
270 | ||
271 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); | |
272 | } | |
273 | ||
274 | static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id, | |
275 | int32_t *addr) | |
276 | { | |
e2132e0b SL |
277 | struct kvm_one_reg cp0reg = { |
278 | .id = reg_id, | |
f8b3e48b | 279 | .addr = (uintptr_t)addr |
e2132e0b SL |
280 | }; |
281 | ||
f8b3e48b | 282 | return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); |
e2132e0b SL |
283 | } |
284 | ||
182f42fd | 285 | static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id, |
e2132e0b SL |
286 | target_ulong *addr) |
287 | { | |
288 | int ret; | |
289 | uint64_t val64 = 0; | |
290 | struct kvm_one_reg cp0reg = { | |
291 | .id = reg_id, | |
292 | .addr = (uintptr_t)&val64 | |
293 | }; | |
294 | ||
295 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); | |
296 | if (ret >= 0) { | |
297 | *addr = val64; | |
298 | } | |
299 | return ret; | |
300 | } | |
301 | ||
182f42fd | 302 | static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id, |
e2132e0b SL |
303 | uint64_t *addr) |
304 | { | |
305 | struct kvm_one_reg cp0reg = { | |
306 | .id = reg_id, | |
307 | .addr = (uintptr_t)addr | |
308 | }; | |
309 | ||
310 | return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); | |
311 | } | |
312 | ||
03cbfd7b JH |
313 | #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M) |
314 | #define KVM_REG_MIPS_CP0_CONFIG1_MASK (1U << CP0C1_M) | |
315 | #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M) | |
316 | #define KVM_REG_MIPS_CP0_CONFIG3_MASK (1U << CP0C3_M) | |
317 | #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M) | |
318 | #define KVM_REG_MIPS_CP0_CONFIG5_MASK 0 | |
319 | ||
320 | static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, | |
321 | int32_t *addr, int32_t mask) | |
322 | { | |
323 | int err; | |
324 | int32_t tmp, change; | |
325 | ||
326 | err = kvm_mips_get_one_reg(cs, reg_id, &tmp); | |
327 | if (err < 0) { | |
328 | return err; | |
329 | } | |
330 | ||
331 | /* only change bits in mask */ | |
332 | change = (*addr ^ tmp) & mask; | |
333 | if (!change) { | |
334 | return 0; | |
335 | } | |
336 | ||
337 | tmp = tmp ^ change; | |
338 | return kvm_mips_put_one_reg(cs, reg_id, &tmp); | |
339 | } | |
340 | ||
e2132e0b SL |
341 | /* |
342 | * We freeze the KVM timer when either the VM clock is stopped or the state is | |
343 | * saved (the state is dirty). | |
344 | */ | |
345 | ||
346 | /* | |
347 | * Save the state of the KVM timer when VM clock is stopped or state is synced | |
348 | * to QEMU. | |
349 | */ | |
350 | static int kvm_mips_save_count(CPUState *cs) | |
351 | { | |
352 | MIPSCPU *cpu = MIPS_CPU(cs); | |
353 | CPUMIPSState *env = &cpu->env; | |
354 | uint64_t count_ctl; | |
355 | int err, ret = 0; | |
356 | ||
357 | /* freeze KVM timer */ | |
358 | err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); | |
359 | if (err < 0) { | |
360 | DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err); | |
361 | ret = err; | |
362 | } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { | |
363 | count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; | |
364 | err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); | |
365 | if (err < 0) { | |
366 | DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); | |
367 | ret = err; | |
368 | } | |
369 | } | |
370 | ||
371 | /* read CP0_Cause */ | |
372 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); | |
373 | if (err < 0) { | |
374 | DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err); | |
375 | ret = err; | |
376 | } | |
377 | ||
378 | /* read CP0_Count */ | |
379 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); | |
380 | if (err < 0) { | |
381 | DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err); | |
382 | ret = err; | |
383 | } | |
384 | ||
385 | return ret; | |
386 | } | |
387 | ||
388 | /* | |
389 | * Restore the state of the KVM timer when VM clock is restarted or state is | |
390 | * synced to KVM. | |
391 | */ | |
392 | static int kvm_mips_restore_count(CPUState *cs) | |
393 | { | |
394 | MIPSCPU *cpu = MIPS_CPU(cs); | |
395 | CPUMIPSState *env = &cpu->env; | |
396 | uint64_t count_ctl; | |
397 | int err_dc, err, ret = 0; | |
398 | ||
399 | /* check the timer is frozen */ | |
400 | err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); | |
401 | if (err_dc < 0) { | |
402 | DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc); | |
403 | ret = err_dc; | |
404 | } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { | |
405 | /* freeze timer (sets COUNT_RESUME for us) */ | |
406 | count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; | |
407 | err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); | |
408 | if (err < 0) { | |
409 | DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); | |
410 | ret = err; | |
411 | } | |
412 | } | |
413 | ||
414 | /* load CP0_Cause */ | |
415 | err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); | |
416 | if (err < 0) { | |
417 | DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err); | |
418 | ret = err; | |
419 | } | |
420 | ||
421 | /* load CP0_Count */ | |
422 | err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); | |
423 | if (err < 0) { | |
424 | DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err); | |
425 | ret = err; | |
426 | } | |
427 | ||
428 | /* resume KVM timer */ | |
429 | if (err_dc >= 0) { | |
430 | count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC; | |
431 | err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); | |
432 | if (err < 0) { | |
433 | DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err); | |
434 | ret = err; | |
435 | } | |
436 | } | |
437 | ||
438 | return ret; | |
439 | } | |
440 | ||
441 | /* | |
442 | * Handle the VM clock being started or stopped | |
443 | */ | |
444 | static void kvm_mips_update_state(void *opaque, int running, RunState state) | |
445 | { | |
446 | CPUState *cs = opaque; | |
447 | int ret; | |
448 | uint64_t count_resume; | |
449 | ||
450 | /* | |
451 | * If state is already dirty (synced to QEMU) then the KVM timer state is | |
452 | * already saved and can be restored when it is synced back to KVM. | |
453 | */ | |
454 | if (!running) { | |
455 | if (!cs->kvm_vcpu_dirty) { | |
456 | ret = kvm_mips_save_count(cs); | |
457 | if (ret < 0) { | |
458 | fprintf(stderr, "Failed saving count\n"); | |
459 | } | |
460 | } | |
461 | } else { | |
462 | /* Set clock restore time to now */ | |
906b53a2 | 463 | count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
e2132e0b SL |
464 | ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME, |
465 | &count_resume); | |
466 | if (ret < 0) { | |
467 | fprintf(stderr, "Failed setting COUNT_RESUME\n"); | |
468 | return; | |
469 | } | |
470 | ||
471 | if (!cs->kvm_vcpu_dirty) { | |
472 | ret = kvm_mips_restore_count(cs); | |
473 | if (ret < 0) { | |
474 | fprintf(stderr, "Failed restoring count\n"); | |
475 | } | |
476 | } | |
477 | } | |
478 | } | |
479 | ||
480 | static int kvm_mips_put_cp0_registers(CPUState *cs, int level) | |
481 | { | |
482 | MIPSCPU *cpu = MIPS_CPU(cs); | |
483 | CPUMIPSState *env = &cpu->env; | |
484 | int err, ret = 0; | |
485 | ||
486 | (void)level; | |
487 | ||
488 | err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); | |
489 | if (err < 0) { | |
490 | DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); | |
491 | ret = err; | |
492 | } | |
493 | err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, | |
494 | &env->CP0_Context); | |
495 | if (err < 0) { | |
496 | DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err); | |
497 | ret = err; | |
498 | } | |
499 | err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, | |
500 | &env->active_tc.CP0_UserLocal); | |
501 | if (err < 0) { | |
502 | DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err); | |
503 | ret = err; | |
504 | } | |
505 | err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, | |
506 | &env->CP0_PageMask); | |
507 | if (err < 0) { | |
508 | DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); | |
509 | ret = err; | |
510 | } | |
511 | err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); | |
512 | if (err < 0) { | |
513 | DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); | |
514 | ret = err; | |
515 | } | |
516 | err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); | |
517 | if (err < 0) { | |
518 | DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); | |
519 | ret = err; | |
520 | } | |
521 | err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, | |
522 | &env->CP0_BadVAddr); | |
523 | if (err < 0) { | |
524 | DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err); | |
525 | ret = err; | |
526 | } | |
527 | ||
528 | /* If VM clock stopped then state will be restored when it is restarted */ | |
529 | if (runstate_is_running()) { | |
530 | err = kvm_mips_restore_count(cs); | |
531 | if (err < 0) { | |
532 | ret = err; | |
533 | } | |
534 | } | |
535 | ||
536 | err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, | |
537 | &env->CP0_EntryHi); | |
538 | if (err < 0) { | |
539 | DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err); | |
540 | ret = err; | |
541 | } | |
542 | err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, | |
543 | &env->CP0_Compare); | |
544 | if (err < 0) { | |
545 | DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err); | |
546 | ret = err; | |
547 | } | |
548 | err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); | |
549 | if (err < 0) { | |
550 | DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err); | |
551 | ret = err; | |
552 | } | |
553 | err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); | |
554 | if (err < 0) { | |
555 | DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); | |
556 | ret = err; | |
557 | } | |
461a1582 JH |
558 | err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); |
559 | if (err < 0) { | |
560 | DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); | |
561 | ret = err; | |
562 | } | |
03cbfd7b JH |
563 | err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, |
564 | &env->CP0_Config0, | |
565 | KVM_REG_MIPS_CP0_CONFIG_MASK); | |
566 | if (err < 0) { | |
567 | DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__, err); | |
568 | ret = err; | |
569 | } | |
570 | err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, | |
571 | &env->CP0_Config1, | |
572 | KVM_REG_MIPS_CP0_CONFIG1_MASK); | |
573 | if (err < 0) { | |
574 | DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__, err); | |
575 | ret = err; | |
576 | } | |
577 | err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, | |
578 | &env->CP0_Config2, | |
579 | KVM_REG_MIPS_CP0_CONFIG2_MASK); | |
580 | if (err < 0) { | |
581 | DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__, err); | |
582 | ret = err; | |
583 | } | |
584 | err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, | |
585 | &env->CP0_Config3, | |
586 | KVM_REG_MIPS_CP0_CONFIG3_MASK); | |
587 | if (err < 0) { | |
588 | DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__, err); | |
589 | ret = err; | |
590 | } | |
591 | err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, | |
592 | &env->CP0_Config4, | |
593 | KVM_REG_MIPS_CP0_CONFIG4_MASK); | |
594 | if (err < 0) { | |
595 | DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__, err); | |
596 | ret = err; | |
597 | } | |
598 | err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, | |
599 | &env->CP0_Config5, | |
600 | KVM_REG_MIPS_CP0_CONFIG5_MASK); | |
601 | if (err < 0) { | |
602 | DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err); | |
603 | ret = err; | |
604 | } | |
e2132e0b SL |
605 | err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, |
606 | &env->CP0_ErrorEPC); | |
607 | if (err < 0) { | |
608 | DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); | |
609 | ret = err; | |
610 | } | |
611 | ||
612 | return ret; | |
613 | } | |
614 | ||
615 | static int kvm_mips_get_cp0_registers(CPUState *cs) | |
616 | { | |
617 | MIPSCPU *cpu = MIPS_CPU(cs); | |
618 | CPUMIPSState *env = &cpu->env; | |
619 | int err, ret = 0; | |
620 | ||
621 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); | |
622 | if (err < 0) { | |
623 | DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); | |
624 | ret = err; | |
625 | } | |
626 | err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, | |
627 | &env->CP0_Context); | |
628 | if (err < 0) { | |
629 | DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err); | |
630 | ret = err; | |
631 | } | |
632 | err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, | |
633 | &env->active_tc.CP0_UserLocal); | |
634 | if (err < 0) { | |
635 | DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err); | |
636 | ret = err; | |
637 | } | |
638 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, | |
639 | &env->CP0_PageMask); | |
640 | if (err < 0) { | |
641 | DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); | |
642 | ret = err; | |
643 | } | |
644 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); | |
645 | if (err < 0) { | |
646 | DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); | |
647 | ret = err; | |
648 | } | |
649 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); | |
650 | if (err < 0) { | |
651 | DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); | |
652 | ret = err; | |
653 | } | |
654 | err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, | |
655 | &env->CP0_BadVAddr); | |
656 | if (err < 0) { | |
657 | DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err); | |
658 | ret = err; | |
659 | } | |
660 | err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, | |
661 | &env->CP0_EntryHi); | |
662 | if (err < 0) { | |
663 | DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err); | |
664 | ret = err; | |
665 | } | |
666 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, | |
667 | &env->CP0_Compare); | |
668 | if (err < 0) { | |
669 | DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err); | |
670 | ret = err; | |
671 | } | |
672 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); | |
673 | if (err < 0) { | |
674 | DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err); | |
675 | ret = err; | |
676 | } | |
677 | ||
678 | /* If VM clock stopped then state was already saved when it was stopped */ | |
679 | if (runstate_is_running()) { | |
680 | err = kvm_mips_save_count(cs); | |
681 | if (err < 0) { | |
682 | ret = err; | |
683 | } | |
684 | } | |
685 | ||
686 | err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); | |
687 | if (err < 0) { | |
688 | DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); | |
689 | ret = err; | |
690 | } | |
461a1582 JH |
691 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); |
692 | if (err < 0) { | |
693 | DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); | |
694 | ret = err; | |
695 | } | |
03cbfd7b JH |
696 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0); |
697 | if (err < 0) { | |
698 | DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err); | |
699 | ret = err; | |
700 | } | |
701 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1); | |
702 | if (err < 0) { | |
703 | DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__, err); | |
704 | ret = err; | |
705 | } | |
706 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, &env->CP0_Config2); | |
707 | if (err < 0) { | |
708 | DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__, err); | |
709 | ret = err; | |
710 | } | |
711 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, &env->CP0_Config3); | |
712 | if (err < 0) { | |
713 | DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__, err); | |
714 | ret = err; | |
715 | } | |
716 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, &env->CP0_Config4); | |
717 | if (err < 0) { | |
718 | DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__, err); | |
719 | ret = err; | |
720 | } | |
721 | err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5); | |
722 | if (err < 0) { | |
723 | DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err); | |
724 | ret = err; | |
725 | } | |
e2132e0b SL |
726 | err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, |
727 | &env->CP0_ErrorEPC); | |
728 | if (err < 0) { | |
729 | DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); | |
730 | ret = err; | |
731 | } | |
732 | ||
733 | return ret; | |
734 | } | |
735 | ||
736 | int kvm_arch_put_registers(CPUState *cs, int level) | |
737 | { | |
738 | MIPSCPU *cpu = MIPS_CPU(cs); | |
739 | CPUMIPSState *env = &cpu->env; | |
740 | struct kvm_regs regs; | |
741 | int ret; | |
742 | int i; | |
743 | ||
744 | /* Set the registers based on QEMU's view of things */ | |
745 | for (i = 0; i < 32; i++) { | |
02dae26a | 746 | regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i]; |
e2132e0b SL |
747 | } |
748 | ||
02dae26a JH |
749 | regs.hi = (int64_t)(target_long)env->active_tc.HI[0]; |
750 | regs.lo = (int64_t)(target_long)env->active_tc.LO[0]; | |
751 | regs.pc = (int64_t)(target_long)env->active_tc.PC; | |
e2132e0b SL |
752 | |
753 | ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); | |
754 | ||
755 | if (ret < 0) { | |
756 | return ret; | |
757 | } | |
758 | ||
759 | ret = kvm_mips_put_cp0_registers(cs, level); | |
760 | if (ret < 0) { | |
761 | return ret; | |
762 | } | |
763 | ||
764 | return ret; | |
765 | } | |
766 | ||
767 | int kvm_arch_get_registers(CPUState *cs) | |
768 | { | |
769 | MIPSCPU *cpu = MIPS_CPU(cs); | |
770 | CPUMIPSState *env = &cpu->env; | |
771 | int ret = 0; | |
772 | struct kvm_regs regs; | |
773 | int i; | |
774 | ||
775 | /* Get the current register set as KVM seems it */ | |
776 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); | |
777 | ||
778 | if (ret < 0) { | |
779 | return ret; | |
780 | } | |
781 | ||
782 | for (i = 0; i < 32; i++) { | |
783 | env->active_tc.gpr[i] = regs.gpr[i]; | |
784 | } | |
785 | ||
786 | env->active_tc.HI[0] = regs.hi; | |
787 | env->active_tc.LO[0] = regs.lo; | |
788 | env->active_tc.PC = regs.pc; | |
789 | ||
790 | kvm_mips_get_cp0_registers(cs); | |
791 | ||
792 | return ret; | |
793 | } | |
9e03a040 FB |
794 | |
795 | int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, | |
dc9f06ca | 796 | uint64_t address, uint32_t data, PCIDevice *dev) |
9e03a040 FB |
797 | { |
798 | return 0; | |
799 | } | |
1850b6b7 EA |
800 | |
801 | int kvm_arch_msi_data_to_gsi(uint32_t data) | |
802 | { | |
803 | abort(); | |
804 | } |